Datasheet FAN1655 Datasheet (Fairchild Semiconductor)

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FAN1655

3A DDR Bus Termination Regulator

Features

• Sinks and sources 2.1A continuous, 3A peak

• 0 to +125°C operating temperature range

• 5mA Buffered VREFOUT = VDDQ/2

• Load regulation: VTT = VREFOUT ± 40mV

• On-chip thermal limiting

• Low Cost SO-14, Power Enhanced eTSSOP or
8-pin 5x6mm MLP packages

• Low-Current Shutdown Mode

• Output Short Circuit Protection

Applications

• DDR Terminator VTT supply

Block Diagram

Description

The FAN1655 is a low-cost bi-directional LDO specifically
designed for terminating DDR memory bus. It can both sink
and source up to 2.1A continuous, 3A peak, providing
enough current for most DDR applications. Load regulation
meets the JEDEC spec, VTT = VREFOUT ± 40mV.

The FAN1655 includes a buffered reference voltage capable
of supplying up to 5mA current. On-chip thermal limiting
provides protection against a combination of power ov erload
and ambient temperature that would create an excessive
junction temperature. A shutdown input puts the FAN1655
into a low power mode.

The FAN1655 regulator is available in a power-enhanced
eTSSOP™-16 package, and the standard SOIC-14

VREFOUT

VREFIN

VDDQ

VSSQ

200k

200k

FAN1655

VDD VDD VDD

-

+

+

-

VSS VSS

VSS

SHDN

VTTFORCE

VTTFORCE

VTTSENSE

REV. 1.1.3 2/20/03

6

5

3

0

9

3

5

6

8

655

C

Q

Q

SHDN

SE

C

CE

SS

SS

CE

SS

3

0

9

8

3

5

6

655M

Q

OUT

Q

SHDN

SE

SS

CE

SS

SS

CE

SHDN

CE

CE

GND

3

6

5

PRODUCT SPECIFICATION FAN1655

Pin Assignments

1

VTTFOR

VTTFOR

N
VDD

1

VREFOUT
V
V

V

FAN1

VSS

1

1

VTTSEN

N

VTTFOR

VTTFOR

V
V

FAN1

VDD
VREF

1

VSS

1

VTTSEN
V

VTTFOR

VTTFOR

8

7

VDDQ

VREFOUT

VTTSENSE

16-Lead Plastic eTSSOP-16

θJC = 4˚C/W*

*With package power slug soldered to 0.5
square inch copper area over backside
ground plane of internal power plane

Pin Definitions

Pin

1, 4 1, 2, 7 1, 2, 7 VDD Input power for the LDO.
2, 3 3, 6 3, 6 VTTFORCE The VTT output voltage.

PAD 4, 5, 8 4, 5, 8 VSS IC Ground.

5 10 9 VTTSENSE Feedback for remote sense of the VTT voltage.

6 12 11 SHDN

7 14 13 VREFOUT Buffered Voltage Reference Output.
8 15 14 VDDQ VDDQ Input. Attach this pin to the VDDQ supply to

11 10 VREFIN Alternative input for direct control of VTTOUT and

13 12 VSSQ Signal Ground.

9, 16 NC No Internal Connection

14-Lead Plastic SOIC

θJC = 37˚C/W, θ

Pin Name Pin Function DescriptionMLP eTSSOP SOIC-14

= 88˚C/W

JA

8-Lead MLP Package (5x6mm)

= 4˚C/W, θ

θ

JC

= 34˚C/W as

JA

measured on FAN1655MP

Eval Board

VREFOUT.
Shutdown. This active low shutdown turns off both VTT

and VREFOUT. This pin has an internal pull-down, and
must be externally driven high for the IC to be on.

generate VTT and VREFOUT.

Typical Application

VDDQ

VDD

VTTFORCE

16
15

14
13
12

11
10

10k

9

1nF

GND

100µF
6V

10µF

1
2
3
4

FAN1655

5
6
7
8

Figure 1. (eTSSOP pinout shown)

2

470µF

10µF

VREFOUT

1nF

SHDN

VTTSENSE

(connect to VTTFORCE

at the load)

GND

REV. 1.1.3 2/20/03

FAN1655 PRODUCT SPECIFICATION

Typical Performance Characteristics

Quiescent Current vs. Temperature

V

REF

7.5

9

1.0

6

0.5

Output Change vs. I

VDD = V
TA = 25˚C

REF

DDQ

= 2.5V

4.5

3

1.5

QUIESCENT CURRENT (mA)

0

-60

-40

-20 0

Figure 2. Quiescent Current vs.

1.260

1.255

1.250

OUTPUT (V)

TT

V

1.245

20

40 60 80

AMBIENT TEMPERATURE (˚C)

Ambient Temperature

100

120

140

(mV)

0

REFOUT

∆ V

-0.5

-1.0

-5

-6

-4 -3

V

REF

Figure 3. Reference Output

Load Regulation

100.0

10.0

Current Pulse Duration (S)

-1 0

-2

LOAD CURRENT (mA)

1

=70°C

T

A

TA=25°C

2

4

3

56

1.240

-3000 -2000 -1000 0 1000 2000 3000
Load Current (mA)

V

TT

Figure 4. V

Load Regulation

TT

REV. 1.1.3 2/20/03

1.0
1 1.5 2 2.5 3

Peak Load Current (A)

Figure 5. Maximum Non-Repetitive Output

Current vs. Pulse Width

(FAN1655M SO-14 Package)

3

PRODUCT SPECIFICATION FAN1655

Absolute Maximum Ratings

Supply Voltage VDD, VDDQ 6V
Junction Temperature, T
Storage Temperature -65 to 150˚C
Lead Soldering Temperature, 10 seconds 300˚C
Power Dissipation, P

J

D

FAN1655M (SOIC-14) 1.4W
FAN1655MTF (e-TSSOP)

FAN1655MP (MLP)

See “Power Dissipation

150˚C

and Derating”

Recommended Operating Conditions

Parameter Conditions Min. Typ. Max. Units

Supply Voltage VDD 2.3 2.5 3.6 V
Supply Voltage VDDQ 2.2 2.5 3.0 V
Ambient Operating Temperature 0 125 ˚C
VREFIN 1.1 1.25 1.5 V

Electrical Characteristics

(VDD = VDDQ = 2.5V ± 0.2V, and T
The • denotes specifications which apply over the specified operating temperature range.

VTT Output Voltage

VTT Output Slew Rate Cload = 10µF 0.3 V/µS
VTT Leakage Current SHDN = 0V • -50 50 µA
VTT Current Limit ±3.1 A
VREFIN Input Impedance 100 K Ω
VREFOUT Output Voltage No load

VREFOUT Output Current VDDQ = 2.3V • -5 5 mA
VREFOUT Leakage Current SHDN = 0V • -10 10 µA
SHDN Logic High • 1.667 V
SHDN Logic Low • 0.800 V
IDD Supply Current No load, SHDN = 2.7V • 7.5 20 mA
VDDQ Leakage Current SHDN = 0V • 610µA
VDD Leakage Current SHDN = 0V • 350µA
SHDN Input Current SHDN = 2.7V • 50 75 µA
Over-Temperature Shutdown 155 ˚C
Over-Temperature Hysteresis 30 ˚C

Parameter Conditions Min. Typ. Max. Units

= 25˚C using circuit in Figure 1, unless otherwise noted.)

A

I

= 0A, VREFIN = open

OUT

I

= ±2.1A, VREFIN = open

OUT

VDDQ = 2.3V
VDDQ = 2.5V
VDDQ = 2.7V

VDDQ = 2.3V
VDDQ = 2.5V
VDDQ = 2.7V

VREFIN = 1.150V
VREFIN = 1.250V
VREFIN = 1.350V

•

•

•

•

•

•

1.135

1.235

1.335

1.110

1.210

1.310

1.145

1.245

1.345

1.150

1.250

1.350

1.150

1.250

1.350

1.150

1.250

1.350

1.165

1.265

1.365

1.190

1.290

1.390

1.155

1.255

1.355

V
V
V

V
V
V

V
V
V

4

REV. 1.1.3 2/20/03

∆

FAN1655 PRODUCT SPECIFICATION

Applications Information

Output Capacitor selection

The JEDEC specification for DDR termination requires that
VTT stay within ±40mV of VREF, which must track
VDDQ/2 within 1%. During the initial load transient, the
output capacitor keeps the output within spec. To stay within
the 40mV window, the “load step” due to the load transient
current dropping across the output capacitor’s ESR should be

kept to around 25mV: where ESR < is given in m Ω , and

I is the maximum load current.

For example, to handle a 3A maximum load transient, the
ESR should be no greater than 8m Ω . Furthermore, the output
capacitor must be able to hold the load in spec while the
regulator recovers (about 15µS). A minimum v alue of 470µF
is recommended.

These requirements can be achieved by a combination of
capacitors. FAN1655 requires a minimum of 5m Ω of ESR
in the output and is not stable with all-ceramic output
capacitors.

25

----- ­∆I

Power Dissipation and Derating

The maximum output current (sink or source) for a 1.25V
output is:

P

I

OUT MAX()

where P

where T
and T

D(MAX)

P

D MAX()

J(MAX)

is the operating ambient temperature.

A

FAN1655 has an internal thermal limit at 150°C, which
defines T

J(MAX)

88°C/W. Using equation 2, the maximum dissipation at

= 25°C is 1.4W, which is its rated maximum dissipation.

T

A

The e-TSSOP or MLP package, however, use the PCB
copper to cool the IC through the thermal pad on the package
bottom. For maximum dissipation, this pad should be
soldered to the PCB copper, with as much copper area as
possible surrounding it to cool the package. Thermal vias
should be placed as close to the thermal pad as possible to
transfer heat to other layers of copper on the PCB. With lar ge
areas of PCB copper for heat sinking, a θ
can easily be achieved.

D MAX()

----------------------=

1.25

is the maximum power dissipation which is:

T

----------------------------------=

–

J MAX()TA

θ

JA

is the maximum die temperature of the IC

. For the SOIC-14 package, θ

is given at

JA

of under 40°C/W

JA

(1)

(2)

REV. 1.1.3 2/20/03

5

PRODUCT SPECIFICATION FAN1655

Mechanical Dimensions

16 Lead eTSSOP

9

M

-A-

-B-

4.4 ± 0.1

0.2

CBA

ALL LEAD TIPS

+0.15

(0.90)

–0.10

0.10±0.05 TYP

16

3.40

(1.78)

1

0.65 TYP
LAND PATTERN RECOMMENDATION

SEE DETAIL A

4.00

0.42 TYP

9

7.72

4.16

8

0.1

5.0 ± 0.1

C

(0.19–0.30)

0.10 C B A

0.10 TYP

6.4

PIN #1 IDENT.

1.2 MAX

-C-

0.65 TYP

16

3.2

18

ALL LEAD TIPS

9

8

NOTES:
A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION ABT,

DATED 10/97.
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,
AND THE BAR EXTENSIONS.
D. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994.

1.7 MIN

BOTTOM VIEW

16

1.5 MIN

1

R0.09MIN

0°–8°

0.75

0.45

(0.09–0.20)

12° TOP & BOTTOM

GAGE PLANE

0.25

SEATING PLANE

(1.00)

DETAIL A

6

REV. 1.1.3 2/20/03

PRODUCT SPECIFICATION FAN1655

Mechanical Dimensions

14-Lead SOIC

NOTES:

1. This package conforms to JEDEC MS-012, variation AB, ISSUEC dated May, 1990.

2. All dimensions are in millimeters

3. Standard lead finished
200 microinches / 5.08 microns min.
Lead/Tin (solder) oncopper

S8.71-8.51;

7.62
8

S4.00-3.80

7

S0.51-0.35;

S6.20-5.80;

12

13

14

1

1.27

10 9

11

65432

0.50

5.75

1.00

1.27

7.62

LAND PATTERN RECOMMENDATION

S1.75-1.35;

S0.25-0.10;z

S0.25-0.19;

S0.50-0.25;X45˚

S8˚-0˚

S1.27-0.40;

SEATING PLANE

7

REV. 1.1.3 2/20/03

PRODUCT SPECIFICATION FAN1655

Mechanical Dimensions

5mmX6mm 8-Lead MLP

5.0

A

B

4.50

6.25

4.25

0.65 TYP

0.252XC

0.252XC

TOP VIEW

6.0

3.50

(1.00)

1.27 TYP

LAND PATTERN RECOMMENDATION

C

0.10

1.0 MAX

C

0.08

PIN #1 IDENT.
(OPTIONAL)

0.05

0.00

SIDE VIEW

4.25

A

1.75

1234

(0.25)

SEATING
PLANE

0.75

0.35

3.25

1.25

C

A

NOTES:

A) DOES NOT FULLY CONFORM TO JEDEC

A

REGISTRATION MO-229, DATED 11/2001.
B) DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONING AND TOLERANCES PER

ASME Y14.5–1994.

8765

1.27

3.81
A

0.28–0.40

A

MC

0.10
M

0.05 C

AB

BOTTOM VIEW

8

REV. 1.1.3 2/20/03



PRODUCT SPECIFICATION FAN1655

Ordering Information

Part Number Temperature Range Package Packing

FAN1655M 0°C to 125°C SOIC-14 Rails
FAN1655MX 0°C to 125°C SOIC-14 Tape and Reel
FAN1655MTF 0°C to 125°C eTSSOP-16 Rails
FAN1655MTFX 0°C to 125°C eTSSOP-16 Tape and Reel
FAN1655MPX 0°C to 125°C MLP-08 Tape and Reel

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PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

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when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
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reasonably expected to cause the failure of the life support
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