Cypress Semiconductor CY7C4841-25AC, CY7C4841-15AC, CY7C4841-10AC, CY7C4831-25AC, CY7C4831-15AC Datasheet

fax id: 5414

CY7C4801/4811/4821

CY7C4831/4841/4851

Features

•Double high speed, low power, first-in first-out (FIFO) memories

•Double 256 x 9 (CY7C4801)

•Double 512 x 9 (CY7C4811)

•Double 1K x 9 (CY7C4821)

•Double 2K x 9 (CY7C4831)

•Double 4K x 9 (CY7C4841)

•Double 8K x 9 (CY7C4851)

•Functionally equivalent to two CY7C4201/4211/4221/ 4231/4241/4251 FIFOs in a single package

•0.65 micron CMOS for optimum speed/power

•High-speed 100-MHz operation (10 ns read/write cycle times)

•Offers optimal combination of large capacity, high speed, design flexibility, and small footprint

•Fully asynchronous and simultaneous read and write operation

•Four status flags per device: Empty, Full, and programmable Almost Empty/Almost Full

• Low power — I CC1= 60mA

•Output Enable (OEA/OEB) pins

•Depth Expansion Capabilty

•Width Expansion Capabilty

256/512/1K/2K/4K/8K x9 x2 Double Syncä FIFOs

These FIFOs have two independent sets of 9-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free-running clock (WCLKA,WCLKB) and two write-enable pins (WENA1, WENA2/LDA, WENB1, WENB2/LDB).

When (WENA1,WENB1) is LOW and (WENA2/LDA, WENB2/LDB) is HIGH, data is written into the FIFO on the rising edge of the (WCLKA,WCLKB) signal. While (WENA1, WENA2/LDA, WENB1, WENB2/LDB) is held active, data is continually written into the FIFO on each WCLKA, WCLKB cycle. The output port is controlled in a similar manner by a free-running read clock (RCLKA, RCLKB) and two read-en- able pins ((RENA1,RENB1), (RENA2,RENB2)). In addition,

the CY7C48X1 has output enable pins (OEA, OEB) for each FIFO. The read (RCLKA, RCLKB) and write (WCLKA, WCLKB) clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 100 MHz are achievable.

Depth expansion is possible using one enable input for system control, while the other enable is controlled by expansion logic to direct the flow of data.

The CY7C48X1 provides two sets of four different status pins: Empty, Full, Almost Empty, Almost Full. The Almost Empty/Almost Full flags are programmable to single word granularity. The programmable flags default to Empty+7 and Full–7.

•Space-saving 64-pin TQFP

•Pin compatible and functionally equivalent to IDT72801, 72811, 72821, 72831, 72841,72851

Functional Description

The CY7C48X1 are Double high-speed, low-power, first-in first-out (FIFO) memories with clocked read and write interfaces. All are 9 bits wide and operate as two separate FIFOs. The CY7C48X1 are pin-compatible to IDT728X1. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering.

The flags are synchronous, i.e., they change state relative to either the read clock (RCLKA,RCLKB) or the write clock (WCLKA,WCLKB). When entering or exiting the Empty and Almost Empty states, the flags are updated exclusively by the (RCLKA,RCLKB). The flags denoting Almost Full, and Full states are updated exclusively by (WCLKA,WCLKB) The synchronous flag architecture guarantees that the flags maintain their status for at least one cycle

All configurations are fabricated using an advanced 0.65μ N-Well CMOS technology. Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings.

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 October 1996 - Revised January 15, 1997

							CY7C4801/4811/4821
							CY7C4831/4841/4851
Logic Block Diagram			DA0-8	DB0-8		FLAG	LDA
						PROGRAM	LDB
						REGISTER
WCLKA	WCLKB
WENA1		WENB1					EFA
WENA2/LDA		WENB2/LDB					PAEA
						FLAG	PAFA
			INPUT				FFA
						LOGIC	EFB
			REGISTER
							PAEB
				INPUT			PAFB
				REGISTER			FFB
WRITE
CONTROL		WRITE
		CONTROL	RAM
			ARRAY A
			256x9
WRITE			.
			.
POINTER A			8k x 9			READ	READ
				RAM		POINTER A	POINTER B
		WRITE		ARRAY B
				256 x9
		POINTER B		.
				.
				8k x 9		READ	READ
						CONTROL A	CONTROL B
RSA	RESET
			THREE–STATE
RSB	LOGIC
		OUTPUT REGISTER
				THREE–STATE
		OEA	QA0-8	OUTPUT REGISTER
					RCLKA		RCLKB
				OEB		RENA1
							RENB1
				QB0-8		RENA2
							48X1–1
							RENB2
Pin Configuration					TQFP
					Top View
			QA1	1		48	QB0
			QA2	2		47	FFB
			QA3	3		46	EFB
			QA4	4	CY7C4801	45	OEB
			QA5	5	CY7C4811	44	RENB2
			QA6	6		43	RCLKB
			QA7	7	CY7C4821	42	RENB1
			QA8	8	CY7C4831	41	GND
			Vcc	9	CY7C4841	40	Vcc
			WENA2/LDA	10	CY7C4851	39	PAEB
			WCLKA	11		38	PAFB
			WENA1	12		37	DB0
			RSA	13		36	DB1
			DA8	14		35	DB2
			DA7	15		34	DB3
			DA6	16		33	DB4
							48X1–1
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Selection Guide

		7C48X1-10	7C48X1-15	7C48X1-25	7C48X1-35
Maximum Frequency (MHz)		100	66.7	40	28.6
Maximum Access Time (ns)		8	10	15	20
Minimum Cycle Time (ns)		10	15	25	35
Minimum Data or Enable Set-Up (ns)		3	4	6	7
Minimum Data or Enable Hold (ns)		0.5	1	1	2
Maximum Flag Delay (ns)		8	10	15	20
Active Power Supply	Commercial	60	60	60	60
Current (ICC1) (mA)
	Industrial	70	70	70	70

	CY7C4801	CY7C4811	CY7C4821	CY7C4831	CY7C4841	CY7C4851
Density	Double 256 x 9	Double 512 x 9	Double 1K x 9	Double 2K x 9	Double 4K x 9	Double 8K x 9
Package	64-pin TQFP	64-pin TQFP	64-pin TQFP	64-pin TQFP	64-pin TQFP	64-pin TQFP

Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested.)

Storage Temperature .......................................	−65°C to +150°C
Ambient Temperature with	−55°C to +125°C
Power Applied....................................................
Supply Voltage to Ground Potential .................	−0.5V to +7.0V
DC Voltage Applied to Outputs	−0.5V to +7.0V
in High Z State .....................................................
DC Input Voltage .................................................	−0.5V to +7.0V
Output Current into Outputs (LOW) .............................	20 mA

Static Discharge Voltage ...........................................	>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................	>200 mA

Operating Range

	Ambient
Range	Temperature	VCC
Commercial	0°C to +70°C	5V ± 10%
Industrial[1]	−40°C to +85°C	5V ± 10%

Notes:

1.TA is the “instant on” case temperature.

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CY7C4831/4841/4851

Pin Definitions

Signal Name

Description

I/O

Description

DA0 − 8

Data Inputs

I

Data Inputs for 9-bit bus

DB0 − 8

Data Inputs

I

Data Inputs for 9-bit bus

QA0 − 8

Data Outputs

O

Data Outputs for 9-bit bus

QB0 − 8

Data Outputs

O

Data Outputs for 9-bit bus

Write Enable 1

I

WENA1 and WENB1become the only write enables when the device is configured to

WENA1

have programmable flags. Data is written on a LOW-to-HIGH transition of WCLK when

WENB1

(WENA1,WENB1) is LOW and (FFA,FFB) is HIGH. If the FIFO is configured to have two write

enables, data is written on a LOW-to-HIGH transition of WCLK when

(WENA1,WENB1) is

LOW and (WENA2/LDA,WENB2/LDB) and (FFA,FFB) are HIGH.

Write Enable 2

I

If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this pin

WENA2/LDA

operates as a control to write or read the programmable flag offsets. (WENA1,WENB1)

Load

I

WENB2/LDB

must be LOW and (WENA2/LDA,WENB2/LDB) must be HIGH to write data into the FIFO.

Dual Mode Pin

Data will not be written into the FIFO if the

(FFA

,FFB) is LOW. If the FIFO is configured to have

programmable flags, (WENA2/LDA,WENB2/LDB) is held LOW to write or read the program-

mable flag offsets.

Read Enable

I

Enables the device for Read operation.

RENA1

RENA2

Inputs

RENB1

RENB2

WCLKA

Write Clock

I

The rising edge clocks data into the FIFO when

(WENA1,WENB1) is LOW and

WCKLB

(WENA2/

LDA

,WENB2/

LDB

) is HIGH and the FIFO is not Full. When

(WENA2/LDA,WENB2/LDB) is asserted, WCLK writes data into the programmable flag-offset

register.

RCLKA

Read Clock

I

The rising edge clocks data out of the FIFO when

and

(RENA1

,RENB1)

(RENA2,RENB2)

RCLKB

are LOW and the FIFO is not Empty. When (WENA2/LDA,WENB2/LDB) is LOW,

(RCLKA,RCLKB) reads data out of the programmable flag-offset register.

Empty Flag

O

When

EFA,EFB

(EFA,EFB) is LOW, the FIFO is empty.(EFA,EFB) is synchronized to (RCLKA,RCLKB).

Full Flag

O

When

FFA,FFB

(FFA,FFB) is LOW, the FIFO is full. (FFA,FFB) is synchronized to (WCLKA,WCLKB).

PAEA

Programmable

O

When

(PAEA,PAEB) is LOW, the FIFO is almost empty based on the almost empty offset value

PAEB

Almost Empty

programmed into the FIFO. PAE is synchronized to RCLK.

Programmable

O

When

PAFA

(PAFA,PAFB) is LOW, the FIFO is almost full based on the almost full offset value pro-

PAFB

Almost Full

grammed into the FIFO. PAF is synchronized to WCLK.

Reset

I

Resets device to empty condition. A reset is required before an initial read or write

RSA

RSB

operation after power-up.

Output Enable

I

When

OEA

(OEA,OEB) is LOW, the FIFO’s data outputs drive the bus to which they are connected.

If

OEB

(OEA,OEB) is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.

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Electrical Characteristics Over the Operating Range[2]

7C48X1-10

7C48X1-15

7C48X1-25

7C48X1-35

Parameter

Description

Test Conditions

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

VOH

Output HIGH Voltage

VCC = Min.,

2.4

2.4

2.4

2.4

V

IOH = −2.0 mA

VOL

Output LOW Voltage

VCC = Min.,

0.4

0.4

0.4

0.4

V

IOL = 8.0 mA

VIH

Input HIGH Voltage

2.0

VCC

2.0

VCC

2.0

VCC

2.0

VCC

V

VIL

Input LOW Voltage

−0.5

0.8

−0.5

0.8

−0.5

0.8

−0.5

0.8

V

IIX

Input Leakage

VCC = Max.

−10

+10

−10

+10

−10

+10

−10

+10

μA

Current

[3]

Output Short

VCC = Max.,

−90

−90

−90

−90

mA

IOS

Circuit Current

VOUT = GND

IOZL

Output OFF,

> VIH,

−10

+10

−10

+10

−10

+10

−10

+10

μA

OE

IOZH

High Z Current

VSS < VO < VCC

[4]

Active Power Supply

Com’l

60

60

60

60

mA

ICC1

Current

Ind

70

70

70

70

mA

Capacitance[5]

	Parameter	Description	Test Conditions	Max.	Unit
	CIN	Input Capacitance	TA = 25°C, f = 1 MHz,	10	pF
			VCC = 5.0V
	COUT	Output Capacitance		10	pF

AC Test Loads and Waveforms[6, 7]

		R1 1.1KΩ		ALL INPUT PULSES
	5V
	OUTPUT		3.0V	90%	90%
					10%
	CL	R2	GND	10%
		680Ω	≤ 3 ns		≤ 3 ns
	INCLUDING
	JIG AND
	SCOPE	48X1–4			48X1–5

Equivalent to:

THÉVENIN EQUIVALENT

420Ω

OUTPUT 1.91V

Notes:

2.See the last page of this specification for Group A subgroup testing information.

3.Test no more than one output at a time for not more than one second.

4.Outputs open. Tested at Frequency = 20 MHz.

5.Tested initially and after any design or process changes that may affect these parameters.

6.CL = 30 pF for all AC parameters except for tOHZ.

7.CL = 5 pF for tOHZ.

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Switching Characteristics Over the Operating Range

		7C48X1-10		7C48X1-15		7C48X1-25		7C48X1-35
Parameter	Description	Min.	Max.	Min.	Max.	Min.	Max.	Min.	Max.	Unit
fS	Clock Cycle Frequency		100		66.7		40		28.6	MHz
tA	Data Access Time	2	8	2	10	2	15	2	20	ns
tCLK	Clock Cycle Time	10		15		25		35		ns
tCLKH	Clock HIGH Time	4.5		6		10		14		ns
tCLKL	Clock LOW Time	4.5		6		10		14		ns
tDS	Data Set-Up Time	3.5		4		6		7		ns
tDH	Data Hold Time	0.5		1		1		2		ns
tENS	Enable Set-Up Time	3.5		4		6		7		ns
tENH	Enable Hold Time	0.5		1		1		2		ns
tRS	Reset Pulse Width[8.]	10		15		25		35		ns
tRSS	Reset Set-Up Time	8		10		15		20		ns
tRSR	Reset Recovery Time	8		10		15		20		ns
tRSF	Reset to Flag and Output Time		10		15		25		35	ns
tOLZ	Output Enable to Output in Low Z[9]	0		0		0		0		ns
tOE	Output Enable to Output Valid	3	7	3	8	3	12	3	15	ns
tOHZ	Output Enable to Output in High Z[9]	3	7	3	8	3	12	3	15	ns
tWFF	Write Clock to Full Flag		8		10		15		20	ns
tREF	Read Clock to Empty Flag		8		10		15		20	ns
tPAF	Clock to Programmable Almost-Full Flag		8		10		15		20	ns
tPAE	Clock to Programmable Almost-Full Flag		8		10		15		20	ns
tSKEW1	Skew Time between Read Clock and Write	5		6		10		12		ns
	Clock for Empty Flag and Full Flag
tSKEW2	Skew Time between Read Clock and Write	15		15		18		20		ns
	Clock for Almost-Empty Flag and Almost-Full
	Flag
Notes:

8.Pulse widths less than minimum values are not allowed.

9.Values guaranteed by design, not currently tested.

6

					CY7C4801/4811/4821
					CY7C4831/4841/4851
Switching Waveforms
Write Cycle Timing				tCLK
			tCLKH	tCLKL
WCLKA (WCLKB)
				tDS	tDH
DA0 −DA8
(DB0−DB8)					tENH
				tENS
WENA1					NO OPERATION
(WENB1)
WENA2(WENB2)					NO OPERATION
(if applicable)			tWFF		tWFF
FFA (FFB)
			tSKEW1 [10]
RCLKA (RCLKB)
RENA1,RENB2
(RENB1, RENB2)
					48X1–6
Read Cycle Timing				tCLK
			tCLKH	tCLKL
RCLKA (RCLKB)
	tENS		tENH
RENA1,RENA2				NO OPERATION
(RENB1,RENB2)			tREF
					tREF
EFA(EFB)
			tA
QA0−QA8					VALID DATA
(QB0−QB8)		tOLZ			tOHZ
			tOE
OEA(OEB)
				[11]
				tSKEW1
WCLKA,WCLKB
WENA1(WENB1)
WENA2(WENB2)					48X1–7
Notes:
10.	tSKEW1 is the minimum time between a rising (RCLKA,RCLKB) edge and a rising (WCLKA,WCLKB) edge to guarantee that (FFA,FFB) will go HIGH during the current clock
	cycle. If the time between the rising edge of (RCLKA,RCLKB) and the rising edge of (WCLKA,WCLKB) is less than tSKEW1, then (FFA,FFB) may not change state until the
	next (WCLKA,WCLKB) rising edge.
11.	tSKEW1 is the minimum time between a rising (WCLKA,WCLKB) edge and a rising (RCLKA,RCLKB) edge to guarantee that (EFA,EFB) will go HIGH during the current clock
	cycle. It the time between the rising edge of (WCLKA,WCLKB) and the rising edge of RCLK is less than tSKEW1, then (EFA,EFB) may not change state until the next
	(RCLKA,RCLKB) rising edge.
				7