Cypress Semiconductor CY7C1382CV25-167AI, CY7C1382CV25-167AC, CY7C1380CV25-250BZC, CY7C1380CV25-250BGC, CY7C1380CV25-250AC Datasheet

		CY7C1380CV25
	PRELIMINARY	CY7C1382CV25

512K x 36/1M x 18 Pipelined SRAM

Features

•Fast clock speed: 250, 225, 200, 167 MHz

•Provide high-performance 3-1-1-1 access rate

•Fast OE access times: 2.6, 2.8, 3.0, 3.4 ns

•Optimal for depth expansion

•Single 2.5V ± 5% power supply

•Common data inputs and data outputs

•Byte Write Enable and Global Write control

•Chip enable for address pipeline

•Address, data, and control registers

•Internally self-timed Write cycle

•Burst control pins (interleaved or linear burst sequence)

•Automatic power-down available using ZZ mode or CE deselect

•Available in 119-ball bump BGA, 165-ball FBGA and 100-pin TQFP packages

•JTAG boundary scan for BGA packaging version

Functional Description

The Cypress Synchronous Burst SRAM family employs highspeed, low-power CMOS designs using advanced single-layer polysilicon, triple-layer metal technology. Each memory cell consists of six transistors.

The CY7C1382CV25 and CY7C1380CV25 SRAMs integrate 1,048,576x18 and 524,288x36 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input

(CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE), burst control in- puts (ADSC, ADSP, and ADV), write enables (BWa, BWb, BWc, BWd and BWE), and global write (GW).

Asynchronous inputs include the output enable (OE) and burst mode control (MODE). The data (DQa,b,c,d) and the data parity (DQPa,b,c,d) outputs, enabled by OE, are also asynchronous.

DQa,b,c,d and DPa,b,c,d apply to CY7C1380CV25 and DQa,b and DPa,b apply to CY7C1382CV25. a, b, c, d each are of 8 bits wide in the case of DQ and 1 bit wide in the case of DP.

Addresses and chip enables are registered with either address status processor (ADSP) or address status controller (ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the burst advance pin (ADV).

Address, data inputs, and write controls are registered on-chip to initiate self-timed Write cycle. Write cycles can be one to four bytes wide as controlled by the write control inputs. Individual byte write allows individual byte to be written. BWa controls DQa and DPa. BWb controls DQb and DPb. BWc controls DQc and DPd. BWd controls DQd and DPd. BWa, BWb BWc, and BWd can be active only with BWE being LOW. GW being LOW causes all bytes to be written. Write pass-through capability allows written data available at the output for the next Read cycle. This device also incorporates pipelined enable circuit for easy depth expansion without penalizing system performance.

All inputs and outputs of the CY7C1380CV25 and the CY7C1382CV25 are JEDEC standard JESD8-5 compatible.

Selection Guide

	250 MHz	225 MHz	200 MHz	167 MHz	Unit
Maximum Access Time	2.6	2.8	3.0	3.4	ns
Maximum Operating Current	350	325	300	275	mA
Maximum CMOS Standby Current	70	70	70	70	mA

Shaded areas contain advance information.

Cypress Semiconductor Corporation	•	3901 North First Street	•	San Jose, CA 95134	•	408-943-2600
Document #: 38-05240 Rev. *A				Revised November 20, 2002

CY7C1380CV25

PRELIMINARY

CY7C1382CV25

CY7C1380CV25 - 512K x 36

MODE

(A[1;0])

2

CLK

BURST

Q0

ADV

CE

COUNTER

Q1

ADSC

CLR

ADSP

Q

ADDRESS

17

19

512KX36

CE

A[18:0]

REGISTER

19

17

D

MEMORY

GW

D

DQd, DPd

Q

ARRAY

BWE

BYTEWRITE

BWd

REGISTERS

D

DQc, DPc

Q

BW

c

BYTEWRITE

REGISTERS

D

DQb, DPb

Q

BWb

BYTEWRITE

REGISTERS

D

DQa, DPa

Q

BWa

BYTEWRITE

REGISTERS

36

36

CE1

CE2

D

Q

ENABLE CE

CE3

REGISTER

D ENABLE DELAY Q

OUTPUT

INPUT

REGISTER

REGISTERS

REGISTERS

CLK

CLK

OE

ZZ

SLEEP

CONTROL

DQa,b,c,d

DPa,b

CY7C1382CV25 - 1M X 18

MODE

(A[1;0]) 2

CLK

BURST

Q0

ADV

CE

COUNTER

Q1

ADSC

CLR

ADSP

ADDRESS

Q

18

20

1M X 18

CE

A[19:0]

REGISTER

D

20

18

MEMORY

GW

D

DQb, DPb

Q

ARRAY

BWE

BYTEWRITE

BWb

REGISTERS

D

DQa, DPa

Q

BWa

BYTEWRITE

REGISTERS

18

18

CE

1

CE2

D

Q

ENABLE CE

CE

CE3

REGISTER

D ENABLE DELAY Q

OUTPUT

INPUT

REGISTER

REGISTERS

REGISTERS

CLK

CLK

OE

ZZ

SLEEP

CONTROL

DQa,b

DPa,b

Document #: 38-05240 Rev. *A

Page 2 of 33

																																																																															CY7C1380CV25
																																		PRELIMINARY																																													CY7C1382CV25
Pin Configurations
																																																				100-Pin TQFP
																																																						Top View
				A		A		CE		CE			BWd			BWc			BWb			BWa		CE			V		V		CLK		GW			BWE		OE			ADSC			ADSP		ADV		A		A									A		A		CE		CE		NC		NC		BWb		BWa		CE		V		V		CLK		GW			BWE		OE			ADSC			ADSP		ADV		A			A
								1		2														3				DD		SS																																	1		2										3			DD		SS
NC,DQPc			100			99		98		97		96			95			94			93			92		91			90		89		88		87			86		85			84			83		82		81				NC,DQPb				100			99		98		97		96		95		94		93		92		91		90		89		88		87			86		85			84			83		82		81
			1																																													80							NC			1																																								80							A
DQc			2																																													79						DQb	NC			2																																								79							NC
DQc
VDDQ			3																																													78						DQb	NC			3																																								78							NC
			4																																													77						VDDQ	VDDQ																																																		VDDQ
VSSQ			5																																													76						VSSQ				4																																								77
DQc			6																																													75						DQb	VSSQ			5																																								76							VSSQ
DQc			7																																													74						DQb	NC			6																																								75							NC
																																																							NC
DQc			8																																													73						DQb				7																																								74							DPa
DQc			9																																													72						DQb	DQb			8																																								73							DQa
VSSQ
VDDQ			10																																													71						VSSQ	DQb			9																																								72							DQa
DQc			11																																													70						VDDQ	VSSQ			10																																								71							VSSQ
DQc			12																																													69						DQb	VDDQ			11																																								70							VDDQ
			13																																													68						DQb	DQb
NC			14															CY7C1380CV25																														67						VSS				12																																								69							DQa
VDD																																																							DQb			13												CY7C1382CV25																												68							DQa
			15																		(512K X 36)																											66						NC	NC																																																		VSS
NC			16																																													65						VDD				14																																								67
VSS			17																																													64						ZZ	VDD			15																(1M x 18)																								66							NC
DQd			18																																													63						DQa	NC			16																																								65							VDD
																																																							VSS
DQd			19																																													62						DQa				17																																								64							ZZ
VDDQ			20																																													61						VDDQ	DQb			18																																								63							DQa
VSSQ			21																																													60						VSSQ	DQb			19																																								62							DQa
DQd			22																																													59						DQa	VDDQ			20																																								61							VDDQ
DQd
DQd			23																																													58						DQa	VSSQ			21																																								60							VSSQ
DQd			24																																													57						DQa	DQb			22																																								59							DQa
VSSQ			25																																													56						DQa	DQb			23																																								58							DQa
			26																																													55						VSSQ	DPb			24																																								57							NC
VDDQ			27																																													54						VDDQ	NC			25																																								56							NC
DQd			28																																													53						DQa	VSSQ
DQd			29																																													52						DQa				26																																								55							VSSQ
NC,DQPd			30																																													51						NC,DQPa	VDDQ			27																																								54							VDDQ
			31			32		33		34		35			36			37			38			39		40			41		42		43		44			45		46			47			48		49		50					NC			28																																								53							NC
																																																							NC			29																																								52							NC
																																																							NC			30																																								51							NC
			MODE			A		A		A		A			1			0			NC			NC			SS		DD		A		A		A			A		A A A A A																		31			32		33		34		35		36		37		38		39		40		41		42		43		44			45		46			47			48		49		50
															A			A								V			V
																																																										MODE			A A A A								1		0		NC NC				SS		DD		A A A A A A A																	A A
																																																																					A A								V		V

Document #: 38-05240 Rev. *A

Page 3 of 33

	CY7C1380CV25
PRELIMINARY	CY7C1382CV25

Pin Configurations (continued)

119-Ball BGA

CY7C1380CV25 (512K x 36)

1

2

3

4

5

6

7

A

VDDQ

A

A

A

A

VDDQ

ADSP

B

A

A

A

NC

A

ADSC

NC

C

NC

A

A

VDD

A

A

NC

D

DQc

DQPc

VSS

NC

VSS

DQPb

DQb

E

DQc

DQc

VSS

V

DQb

DQb

CE

SS

1

F

VDDQ

DQc

VSS

DQb

VDDQ

OE

VSS

G

DQb

DQb

DQc

DQc

BWc

ADV

BWb

H

DQc

DQc

VSS

GW

VSS

DQb

DQb

J

VDDQ

VDD

NC

VDD

NC

VDD

VDDQ

K

DQd

DQd

VSS

CLK

VSS

DQa

DQa

L

DQd

DQd

DQa

BWd

NC

BWa

DQa

M

VDDQ

DQd

VSS

VSS

DQa

VDDQ

BWE

N

DQd

DQd

VSS

A1

VSS

DQa

DQa

P

DQd

DQPd

VSS

A0

VSS

DQPa

DQa

R

NC

A

MODE

VDD

NC

A

NC

T

NC

72M

A

A

A

36M

ZZ

U

VDDQ

TMS

TDI

TCK

TDO

NC

VDDQ

CY7C1382CV25 (1M x 18)

1

2

3

4

5

6

7

A

VDDQ

A

A

A

A

VDDQ

ADSP

B

NC

A

A

A

A

NC

ADSC

C

NC

A

A

VDD

A

A

NC

D

DQb

NC

VSS

NC

VSS

DQPa

NC

E

NC

DQb

VSS

V

NC

DQa

CE

SS

1

F

VDDQ

NC

VSS

DQa

VDDQ

OE

VSS

G

NC

DQa

NC

DQb

BWb

ADV

VSS

H

DQb

NC

VSS

GW

VSS

DQa

NC

J

VDDQ

VDD

NC

VDD

NC

VDD

VDDQ

K

NC

DQb

VSS

CLK

VSS

NC

DQa

L

DQb

NC

VSS

DQa

NC

NC

BWa

M

VDDQ

DQb

VSS

NC

VDDQ

VSS

BWE

N

DQb

NC

VSS

A1

VSS

DQa

NC

P

NC

DQPb

VSS

A0

VSS

NC

DQa

R

NC

A

MODE

VDD

NC

A

NC

T

72M

A

A

36M

A

A

ZZ

U

VDDQ

TMS

TDI

TCK

TDO

NC

VDDQ

Document #: 38-05240 Rev. *A

Page 4 of 33

	CY7C1380CV25
PRELIMINARY	CY7C1382CV25

Pin Configurations (continued)

165-Ball Bump FBGA

CY7C1380CV25 (512K x 36) - 11 x 15 FBGA

1

2

3

4

5

6

7

8

9

10

11

A

NC

A

CE

1

BWc

BWb

CE

3

BWE

ADSC

ADV

A

NC

B

NC

A

CE2

CLK

BWd

BWa

GW

OE

ADSP

A

144M

C

DPc

NC

VDDQ

VSS

VSS

VSS

VSS

VSS

VDDQ

NC

DPb

D

DQc

DQc

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQb

DQb

E

DQc

DQc

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQb

DQb

F

DQc

DQc

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQb

DQb

G

DQc

DQc

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQb

DQb

H

NC

VSS

NC

VDD

VSS

VSS

VSS

VDD

NC

NC

ZZ

J

DQd

DQd

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQa

DQa

K

DQd

DQd

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQa

DQa

L

DQd

DQd

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQa

DQa

M

DQd

DQd

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQa

DQa

N

DPd

NC

VDDQ

VSS

NC

A

VSS

VSS

VDDQ

NC

DPa

P

NC

72M

A

A

TDI

A1

TDO

A

A

A

A

R

MODE

36M

A

A

TMS

A0

TCK

A

A

A

A

CY7C1382CV25 (1M x 18) - 11 x 15 FBGA

1

2

3

4

5

6

7

8

9

10

11

A

NC

A

NC

CE

1

BWb

CE

3

BWE

ADSC

ADV

A

A

B

NC

A

CE2

NC

CLK

BWa

GW

OE

ADSP

A

144M

C

NC

NC

VDDQ

VSS

VSS

VSS

VSS

VSS

VDDQ

NC

DPa

D

NC

DQb

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

NC

DQa

E

NC

DQb

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

NC

DQa

F

NC

DQb

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

NC

DQa

G

NC

DQb

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

NC

DQa

H

NC

VSS

NC

VDD

VSS

VSS

VSS

VDD

NC

NC

ZZ

J

DQb

NC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQa

NC

K

DQb

NC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQa

NC

L

DQb

NC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQa

NC

M

DQb

NC

VDDQ

VDD

VSS

VSS

VSS

VDD

VDDQ

DQa

NC

N

DPb

NC

VDDQ

VSS

NC

A

VSS

VSS

VDDQ

NC

NC

P

NC

72M

A

A

TDI

A1

TDO

A

A

A

A

R

MODE

36M

A

A

TMS

A0

TCK

A

A

A

A

Document #: 38-05240 Rev. *A

Page 5 of 33

CY7C1380CV25

PRELIMINARY

CY7C1382CV25

Pin Definitions

Name

I/O

Description

A0

Input-

Address Inputs used to select one of the address locations. Sampled at

A1

Synchronous

the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2,

A

and CE3 are sampled active. A[1:0] feed the 2-bit counter.

Input-

Byte Write Select Inputs, active LOW. Qualified with

to conduct byte

BWa

BWE

BWb

Synchronous

writes to the SRAM. Sampled on the rising edge of CLK.

BWc

BWd

Input-

Global Write Enable Input, active LOW. When asserted LOW on the rising

GW

Synchronous

edge of CLK, a global write is conducted (ALL bytes are written, regardless of

the values on

BWa,b,c,d and BWE).

Input-

Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK.

BWE

Synchronous

This signal must be asserted LOW to conduct a byte write.

CLK

Input-Clock

Clock Input. Used to capture all synchronous inputs to the device. Also used

to increment the burst counter when ADV is asserted LOW, during a burst

operation.

1

Input-

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used

CE

Synchronous

in conjunction with CE2 and CE3 to select/deselect the device. ADSP is ig-

nored if CE1 is HIGH.

CE2

Input-

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used

Synchronous

in conjunction with CE1 and CE3 to select/deselect the device. (TQFP Only)

3

Input-

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used

CE

Synchronous

in conjunction with CE1 and CE2 to select/deselect the device. (TQFP Only)

Input-

Output Enable, asynchronous input, active LOW. Controls the direction of

OE

Asynchronous

the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted

HIGH, I/O pins are three-stated, and act as input data pins. OE is masked

during the first clock of a read cycle when emerging from a deselected state.

Input-

Advance Input signal, sampled on the rising edge of CLK. When asserted,

ADV

Synchronous

it automatically increments the address in a burst cycle.

Input-

Address Strobe from Processor, sampled on the rising edge of CLK.

ADSP

Synchronous

When asserted LOW, A is captured

in the

address registers. A[1:0] are also

loaded into the burst counter. When ADSP and ADSC are both asserted, only

ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.

Input-

Address Strobe from Controller, sampled on the rising edge of CLK.

ADSC

Synchronous

When asserted LOW, A[x:0] is captured in the address registers. A[1:0] are also

loaded into the burst counter. When ADSP and ADSC are both asserted, only

ADSP is recognized.

MODE

Input-Pin

Selects Burst Order. When tied to GND selects linear burst sequence. When

tied to VDDQ or left floating selects interleaved burst sequence. This is a strap

pin and should remain static during device operation.

ZZ

Input-

ZZ “sleep” Input. This active HIGH input places the device in a non-time

Asynchronous

critical “sleep” condition with data integrity preserved.

DQa, DPa

I/O-

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register

DQb, DPb

Synchronous

that is triggered by the rising edge of CLK. As outputs, they deliver the data

DQc, DPc

contained in the memory location specified by A[X] during the previous clock

DQd, DPd

rise of the read cycle. The direction of the pins is controlled by OE. When OE

is asserted LOW, the pins behave as outputs. When HIGH, DQx and DPx are

placed in a three-state condition. DQ a,b,c, and d are 8 bits wide and the DP

a,b,c, and d are 1 bit wide.

TDO

JTAG serial output

Serial data-out to the JTAG circuit. Delivers data on the negative edge of

Synchronous

TCK. (BGA Only)

TDI

JTAG serial input

Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK.(BGA

Synchronous

Only)

Document #: 38-05240 Rev. *A

Page 6 of 33

					CY7C1380CV25
			PRELIMINARY		CY7C1382CV25
Pin Definitions
Name			I/O	Description
TMS		Test Mode Select		This pin controls the Test Access Port state machine. Sampled on the
		Synchronous		rising edge of TCK. (BGA Only)
TCK		JTAG serial clock		Serial clock to the JTAG circuit. (BGA Only)
VDD		Power Supply		Power supply inputs to the core of the device. Should be connected to 2.5V
				± 5% power supply.
VSS		Ground		Ground for the core of the device. Should be connected to ground of the
				system.
VDDQ		I/O Power Supply		Power supply for the I/O circuitry.
VSSQ		I/O Ground		Ground for the I/O circuitry. Should be connected to ground of the system.
NC		-		No Connects.Pins are not internally connected.
36M		-		No Connects. Reserved for address expansion.
72M
144M

Document #: 38-05240 Rev. *A

Page 7 of 33

							CY7C1380CV25
PRELIMINARY							CY7C1382CV25

Introduction

Functional Overview

All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 2.6 ns (250-MHz device).

The CY7C1380CV25/CY7C1382CV25 supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium® and i486 processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access.

Byte write operations are qualified with the Byte Write Enable

(BWE) and Byte Write Select (BWa,b,c,d for CY7C1380V25 and BWa,b for CY7C1382V25) inputs. A Global Write Enable (GW)

overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry.

Synchronous Chip Selects (CE1, CE2, CE3 for TQFP / CE1 for BGA) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. ADSP is ignored if CE1 is HIGH.

Single Read Accesses

This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) chip selects are all asserted active, and (3) the write signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs is stored into the address advancement logic and the Address Register while being presented to the memory core. The corresponding data is allowed to propagate to the input of the Output Registers. At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within 2.6 ns (250-MHz device) if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always three-stated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE signal. Consecutive single read cycles are supported. Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output will three-state immediately.

Single Write Accesses Initiated by ADSP

This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) chip select is asserted active. The address presented is loaded into the address register and the address advancement logic while being delivered to the RAM core. The write signals

(GW, BWE, and BWx) and ADV inputs are ignored during this first cycle.

ADSP triggered write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQx inputs is written into the corresponding address location in the RAM core. If GW is HIGH, then the write operation is controlled by BWE and BWx signals. The CY7C1380CV25/CY7C1382CV25 provides byte write capability that is described in the write cycle description table. Asserting the Byte Write Enable input (BWE) with the selected Byte Write (BWa,b,c,d for CY7C1380CV25 and BWa,b for CY7C1382CV25) input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations.

Because the CY7C1380CV25/CY7C1382CV25 is a common I/O device, the output enable (OE) must be deasserted HIGH before presenting data to the DQ inputs. Doing so will threestate the output drivers. As a safety precaution, DQ are automatically three-stated whenever a write cycle is detected, regardless of the state of OE.

Single Write Accesses Initiated by ADSC

ADSC write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted HIGH, (3) chip select is asserted active, and (4) the appropriate combination of the write inputs (GW, BWE, and BWx) are asserted active to conduct a write to the desired byte(s). ADSC triggered write accesses require a single clock

cycle to complete. The address presented to A[17:0] is loaded into the address register and the address advancement logic

while being delivered to the RAM core. The ADV input is ignored during this cycle. If a global write is conducted, the data presented to the DQ[x:0] is written into the corresponding address location in the RAM core. If a byte write is conducted, only the selected bytes are written. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations.

Because the CY7C1380CV25/CY7C1382CV25 is a common I/O device, the output enable (OE) must be deasserted HIGH before presenting data to the DQ[x:0] inputs. Doing so will three-state the output drivers. As a safety precaution, DQ[x:0] are automatically three-stated whenever a write cycle is detected, regardless of the state of OE.

Burst Sequences

The CY7C1380CV25/CY7C1382CV25 provides a two-bit wraparound counter, fed by A[1:0], that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel® Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input.

Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both read and write burst operations are supported.

Document #: 38-05240 Rev. *A

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	CY7C1380CV25
PRELIMINARY	CY7C1382CV25

Interleaved Burst Sequence

First	Second	Third	Fourth
Address	Address	Address	Address
A[1:0]]	A[1:0]	A[1:0]	A[1:0]
00	01	10	11
01	00	11	10
10	11	00	01
11	10	01	00

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CEs, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW.

Linear Burst Sequence

First	Second	Third	Fourth
Address	Address	Address	Address
A[1:0]	A[1:0]	A[1:0]	A[1:0]
00	01	10	11
01	10	11	00
10	11	00	01
11	00	01	10

ZZ Mode Electrical Characteristics

Parameter	Description	Test Conditions			Min.	Max.	Unit
IDDZZ	Sleep mode stand-	ZZ >	VDD −	0.2V		60	mA
	by current
tZZS	Device operation to	ZZ >	VDD −	0.2V		2tCYC	ns
	ZZ
tZZREC	ZZ recovery time	ZZ < 0.2V			2tCYC		ns

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CY7C1380CV25

PRELIMINARY

CY7C1382CV25

Cycle Descriptions[1, 2, 3, 4]

Next Cycle

Add. Used

ZZ

CE3

CE2

CE1

ADSP

ADSC

ADV

OE

DQ

Write

Unselected

None

0

X

X

1

X

0

X

X

Hi-Z

X

Unselected

None

0

1

X

0

0

X

X

X

Hi-Z

X

Unselected

None

0

X

0

0

0

X

X

X

Hi-Z

X

Unselected

None

0

1

X

0

1

0

X

X

Hi-Z

X

Unselected

None

0

X

0

0

1

0

X

X

Hi-Z

X

Begin Read

External

0

0

1

0

0

X

X

X

Hi-Z

X

Begin Read

External

0

0

1

0

1

0

X

X

Hi-Z

Read

Continue Read

Next

0

X

X

X

1

1

0

1

Hi-Z

Read

Continue Read

Next

0

X

X

X

1

1

0

0

DQ

Read

Continue Read

Next

0

X

X

1

X

1

0

1

Hi-Z

Read

Continue Read

Next

0

X

X

1

X

1

0

0

DQ

Read

Suspend Read

Current

0

X

X

X

1

1

1

1

Hi-Z

Read

Suspend Read

Current

0

X

X

X

1

1

1

0

DQ

Read

Suspend Read

Current

0

X

X

1

X

1

1

1

Hi-Z

Read

Suspend Read

Current

0

X

X

1

X

1

1

0

DQ

Read

Begin Write

Current

0

X

X

X

1

1

1

X

Hi-Z

Write

Begin Write

Current

0

X

X

1

X

1

1

X

Hi-Z

Write

Begin Write

External

0

0

1

0

1

0

X

X

Hi-Z

Write

Continue Write

Next

0

X

X

X

1

1

0

X

Hi-Z

Write

Continue Write

Next

0

X

X

1

X

1

0

X

Hi-Z

Write

Suspend Write

Current

0

X

X

X

1

1

1

X

Hi-Z

Write

Suspend Write

Current

0

X

X

1

X

1

1

X

Hi-Z

Write

ZZ “sleep”

None

1

X

X

X

X

X

X

X

Hi-Z

X

Notes:

1.X = “Don't Care,” 1 = HIGH, 0 = LOW.

2.Write is defined by BWE, BWx, and GW. See Write Cycle Descriptions table.

3.The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

4.CE1, CE2 and CE3 are available only in the TQFP package. The BGA package has a single chip select, CE1.

Document #: 38-05240 Rev. *A

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