Cypress Semiconductor CY7C4421V-25JC, CY7C4421V-25AC, CY7C4421V-15JC, CY7C4421V-15AC, CY7C4421V-10JC Datasheet

CY7C4421V/4201V/4211V/4221V

CY7C4231V/4241V/4251V

Low Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs

Features

•High-speed, low-power, first-in, first-out (FIFO) memories

•64 x 9 (CY7C4421V)

•256 x 9 (CY7C4201V)

•512 x 9 (CY7C4211V)

•1K x 9 (CY7C4221V)

•2K x 9 (CY7C4231V)

•4K x 9 (CY7C4241V)

•8K x 9 (CY7C4251V)

•High-speed 66-MHz operation (15-ns read/write cycle time)

•Low power (ICC = 20 mA)

•3.3V operation for low power consumption and easy integration into low-voltage systems

•5V tolerant inputs VIH max= 5V

•Fully asynchronous and simultaneous read and write operation

•Empty, Full, and Programmable Almost Empty and Almost Full status flags

•TTL compatible

•Output Enable (OE) pin

•Independent read and write enable pins

•Center power and ground pins for reduced noise

•Width expansion capability

•Space saving 32-pin 7 mm x 7 mm TQFP

• 32-pin PLCC

Functional Description

The CY7C42X1V are high-speed, low-power, first-in first-out (FIFO) memories with clocked read and write interfaces. All are 9 bits wide. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering.

These FIFOs have 9-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a Free-Running Clock (WCLK) and two Write Enable pins (WEN1, WEN2/LD).

When WEN1 is LOW and WEN2/LD is HIGH, data is written into the FIFO on the rising edge of the WCLK signal. While WEN1, WEN2/LD is held active, data is continually written into the FIFO on each WCLK cycle. The output port is controlled in a similar manner by a Free-Running Read Clock (RCLK) and two Read Enable Pins (REN1, REN2). In addition, the CY7C42X1V has an Output Enable Pin (OE). The Read (RCLK) and Write (WCLK) clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 66 MHz are achievable.

Depth expansion is possible using one enable input for system control, while the other enable is controlled by expansion logic to direct the flow of data

.

Logic Block Diagram

D0 − 8

Pin Configuration

PLCC

Top View

INPUT

D2

D3 D4 D5 D6 D7 D8

REGISTER

4

3

2

1 3231 30

D1

RS

5

29

D0

6

28

WEN1

WCLKWEN1 WEN2/LD

PAF

7

27

WCLK

PAE

8

26

WEN2/LD

GND

FLAG

9

25

VCC

REN1

PROGRAM

10

24

Q8

REGISTER

RCLK

11

23

Q7

WRITE

REN2

12

22

Q6

OE

13

21

Q5

CONTROL

14151617 181920

EF

0

1 2

3 4

42X1V–2

FLAG

PAE

EF FF Q Q Q Q Q

Dual Port

LOGIC

PAF

FF

TQFP

RAM Array

64 x 9

Top View

WRITE

READ

2

3

4

5

6

7

8

8Kx 9

D

D

D D D D D RS

POINTER

POINTER

32 31 30 29 28 27 26 25

RS

RESET

D1

1

24

WEN1

D0

2

23

WCLK

LOGIC

PAF

3

22

WEN2/LD

THREE-STATE

PAE

4

21

VCC

READ

GND

5

20

Q8

OUTPUTREGISTER

CONTROL

REN1

6

19

Q7

OE

RCLK

7

18

Q6

REN2

8

17

Q5

Q0 − 8

RCLK REN1 REN2

9 10 11 12 13 14 15 16

42X1V–3

42X1V–1

OE

EF

FF

0

1

2

3 4

Q

Q

Q

Q Q

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 October 14, 1999

CY7C4421V/4201V/4211V/4221V

CY7C4231V/4241V/4251V

Functional Description (continued)

The CY7C42X1V provides four status pins: Empty, Full, Almost Empty, Almost Full. The Almost Empty/Almost Full flags are programmable to single word granularity. The programmable flags default to Empty− 7 and Full− 7.

The flags are synchronous, i.e., they change state relative to either the Read Clock (RCLK) or the Write Clock (WCLK).

When entering or exiting the Empty and Almost Empty states, the flags are updated exclusively by the RCLK. The flags denoting Almost Full and Full states are updated exclusively by WCLK. The synchronous flag architecture guarantees that the flags maintain their status for at least one cycle

All configurations are fabricated using an advanced 0.65µ P-Well CMOS technology. Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings.

Selection Guide

		CY7C42X1V-15	CY7C42X1V-25	CY7C42X1V-35
Maximum Frequency (MHz)		66.7	40	28.6
Maximum Access Time (ns)		11	15	20
Minimum Cycle Time (ns)		15	25	35
Minimum Data or Enable Set-Up (ns)		4	6	7
Minimum Data or Enable Hold (ns)		1	1	2
Maximum Flag Delay (ns)		10	15	20
Active Power Supply	Commercial	20	20	20
Current (mA)

	CY7C4421V	CY7C4201V	CY7C4211V	CY7C4221V	CY7C4231V	CY7C4241V	CY7C4251V
Density	64 x 9	256 x 9	512 x 9	1K x 9	2K x 9	4K x 9	8K x 9

Pin Definitions

Signal Name

Description

I/O

Description

D0− 8

Data Inputs

I

Data Inputs for 9-bit bus.

Q0− 8

Data Outputs

O

Data Outputs for 9-bit bus.

WEN1

Write Enable 1

I

The only write enable when device is configured to have programmable flags. Data is

written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF is HIGH.

If the FIFO is configured to have two write enables, data is written on a LOW-to-HIGH transition

of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH.

Write Enable 2

I

If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this pin

WEN2/LD

Dual Mode Pin

operates as a control to write or read the programmable flag offsets. WEN1 must be

Load

I

LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO

if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW

to write or read the programmable flag offsets.

Read Enable

I

Enables the device for Read operation.

REN1,

REN2

Inputs

WCLK

Write Clock

I

The rising edge clocks data into the FIFO when

is HIGH

WEN1

is LOW and WEN2/LD

and the FIFO is not Full. When

LD

is asserted, WCLK writes data into the programmable flag-off-

set register.

RCLK

Read Clock

I

The rising edge clocks data out of the FIFO when

and

are LOW and the FIFO

REN1

REN2

is not Empty. When WEN2/LD is LOW, RCLK reads data out of the programmable flag offset

register.

Empty Flag

O

When

is LOW, the FIFO is empty.

is synchronized to RCLK.

EF

EF

EF

Full Flag

O

When

is LOW, the FIFO is full.

is synchronized to WCLK.

FF

FF

FF

Programmable

O

When

is LOW, the FIFO is almost empty based on the almost empty offset value pro-

PAE

PAE

Almost Empty

grammed into the FIFO.

Programmable

O

When

is LOW, the FIFO is almost full based on the almost full offset value programmed

PAF

PAF

Almost Full

into the FIFO.

2

									CY7C4421V/4201V/4211V/4221V
									CY7C4231V/4241V/4251V
Pin Definitions (continued)
	Signal Name			Description		I/O			Description
				Reset		I	Resets device to empty condition. A reset is required before an initial read or write
	RS
							operation after power-up.
				Output Enable		I	When		is LOW, the FIFO’s data outputs drive the bus to which they are connected. If		is
	OE							OE		OE
							HIGH, the FIFO’s outputs are in High Z (high-impedance) state.

Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested.)

Storage Temperature .......................................	− 65° C to +150°C
Ambient Temperature with	− 55° C to +125°C
Power Applied ....................................................
Supply Voltage to Ground Potential..................	− 0.5V to +5.0V
DC Voltage Applied to Outputs	− 0.5V to +5.0V
in High Z State .....................................................

Electrical Characteristics Over the Operating Range

DC Input Voltage .................................................	− 0.5V to +5.0V
Output Current into Outputs (LOW).............................	20 mA
Static Discharge Voltage ...........................................	>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................	>200 mA

Operating Range

Range	Ambient Temperature	VCC
Commercial	0°C to +70°C	3.3V ± 300mV

					7C42X1V-15		7C42X1V-25		7C42X1V-35
Parameter	Description		Test Conditions		Min.	Max.	Min.	Max.	Min.	Max.	Unit
VOH	Output HIGH Voltage		VCC = Min.,		2.4		2.4		2.4		V
			IOH = − 2.0 mA
VOL	Output LOW Voltage		VCC = Min.,			0.4		0.4		0.4	V
			IOL = 8.0 mA
VIH	Input HIGH Voltage				2.0	5.0	2.0	5.0	2.0	5.0	V
VIL	Input LOW Voltage				− 0.5	0.8	− 0.5	0.8	− 0.5	0.8	V
IIX	Input Leakage		VCC = Max.		− 10	+10	− 10	+10	− 10	+10	µ A
	Current
IOZL	Output OFF,			> VIH,	− 10	+10	− 10	+10	− 10	+10	µ A
			OE
IOZH	High Z Current		VSS < VO < VCC
[1]	Active Power Supply		Com’l			20		20		20	mA
ICC
	Current
[2]	Average Standby		Com’l			6		6		6	mA
ISB
	Current

Capacitance[3]

	Parameter	Description	Test Conditions	Max.	Unit
	CIN	Input Capacitance	TA = 25°C, f = 1 MHz,	5	pF
			VCC = 5.0V
	COUT	Output Capacitance		7	pF

Notes:

1.Outputs open. Tested at Frequency = 20 MHz.

2.All inputs = VCC – 0.2V, except WCLK and RCLK, which are switching at 20 MHz.

3.Tested initially and after any design or process changes that may affect these parameters.

3

		CY7C4421V/4201V/4211V/4221V
				CY7C4231V/4241V/4251V
AC Test Loads and Waveforms[4, 5]
3.3V	R1= 330 Ω			ALL INPUT PULSES
OUTPUT		3.0V		90%	90%
					10%
CL	R2=510 Ω	GND		10%
INCLUDING		≤	3 ns		≤	3 ns
JIG AND
SCOPE	42X1V–4					42X1V–5

Equivalent to:	THÉ VENIN EQUIVALENT
		Rth=200 Ω
	OUTPUT				Vth=2.0V

Switching Characteristics Over the Operating Range

		7C42X1V-15		7C42X1V-25		7C42X1V-35
Parameter	Description	Min.	Max.	Min.	Max.	Min.	Max.	Unit
tS	Clock Cycle Frequency		66.7		40		28.6	MHz
tA	Data Access Time	2	11	2	15	2	20	ns
tCLK	Clock Cycle Time	15		25		35		ns
tCLKH	Clock HIGH Time	6		10		14		ns
tCLKL	Clock LOW Time	6		10		14		ns
tDS	Data Set-Up Time	4		6		7		ns
tDH	Data Hold Time	1		2		2		ns
tENS	Enable Set-Up Time	4		6		7		ns
tENH	Enable Hold Time	1		2		2		ns
t	Reset Pulse Width[6]	15		25		35		ns
RS
tRSS	Reset Set-Up Time	10		15		20		ns
tRSR	Reset Recovery Time	10		15		20		ns
tRSF	Reset to Flag and Output Time		18		25		35	ns
t	Output Enable to Output in Low Z[7]	0		0		0		ns
OLZ
tOE	Output Enable to Output Valid	3	8	3	12	3	15	ns
t	Output Enable to Output in High Z[7]	3	8	3	12	3	15	ns
OHZ
tWFF	Write Clock to Full Flag		11		15		20	ns
tREF	Read Clock to Empty Flag		11		15		20	ns
tPAF	Clock to Programmable Almost-Full Flag		18		15		20	ns
tPAE	Clock to Programmable Almost-Full Flag		18		15		20	ns
tSKEW1	Skew Time between Read Clock and Write Clock	6		10		12		ns
	for Empty Flag and Full Flag
tSKEW2	Skew Time between Read Clock and Write Clock	15		18		20		ns
	for Almost-Empty Flag and Almost-Full Flag
Notes:

4.CL = 30 pF for all AC parameters except for tOHZ.

5.CL = 5 pF for tOHZ.

6.Pulse widths less than minimum values are not allowed.

7.Values guaranteed by design, not currently tested.

4

				CY7C4421V/4201V/4211V/4221V
				CY7C4231V/4241V/4251V
Switching Waveforms
Write Cycle Timing			tCLK
		tCLKH	tCLKL
	WCLK
			tDS	tDH
	D0 –D8
			tENS	tENH
	WEN1			NO OPERATION
	WEN2			NO OPERATION
		tWFF		tWFF
(if applicable)
	FF
		[8]
		tSKEW1
	RCLK
REN1,REN2
				42X1V–6
Read Cycle Timing			tCKL
		tCLKH	tCLKL
	RCLK
	tENS	tENH
REN1,REN2			NO OPERATION
		tREF		tREF
	EF
		tA
	Q0 –Q8			VALID DATA
	tOLZ	tOE		tOHZ
	OE
			[9]
			tSKEW1
	WCLK
	WEN1
	WEN2			42X1V–7
Notes:
8.	tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the
	rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge.
9.	tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between the
	rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF may not change state until the next RCLK rising edge.
			5