Loading...Cypress Semiconductor CY7C1041BL-17ZC, CY7C1041BL-17VC, CY7C1041BL-15ZC, CY7C1041BL-15VC, CY7C1041B-25ZI Datasheet
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CY7C1041B
Features
•High speed
—tAA = 12 ns
•Low active power
—1540 mW (max.)
•Low CMOS standby power (L version)
—2.75 mW (max.)
•2.0V Data Retention (400 W at 2.0V retention)
•Automatic power-down when deselected
•TTL-compatible inputs and outputs
•Easy memory expansion with CE and OE features
Functional Description
The CY7C1041B is a high-performance CMOS static RAM organized as 262,144 words by 16 bits.
Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
256K x 16 Static RAM
written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17).
Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes.
The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW).
The CY7C1041B is available in a standard 44-pin 400-mil-wide body width SOJ and 44-pin TSOP II package with center power and ground (revolutionary) pinout.
Logic Block Diagram |
Pin Configuration |
A0 
A1 
A2 
A3 
A4 
A5 
A6 
A7 
A8 
ROW DECODER
INPUT BUFFER
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256K x 16 |
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AMPS |
I/O0 |
– I/O7 |
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ARRAY |
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SENSE |
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1024 x 4096 |
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I/O8 |
– I/O15 |
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COLUMN |
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DECODER |
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9 |
10 |
11 |
12 13 |
14 |
15 |
16 |
17 |
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A A A A A A A A A |
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BHE |
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WE |
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CE |
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OE |
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BLE |
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1041B–1 |
SOJ
TSOP II
Top View
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A0 |
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1 |
44 |
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A17 |
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A1 |
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2 |
43 |
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A16 |
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A2 |
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3 |
42 |
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A15 |
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A3 |
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4 |
41 |
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OE |
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A4 |
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40 |
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BHE |
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CE |
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6 |
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BLE |
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I/O0 |
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38 |
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I/O15 |
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I/O1 |
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8 |
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I/O14 |
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I/O2 |
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36 |
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I/O13 |
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I/O3 |
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10 |
35 |
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I/O12 |
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VCC |
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11 |
34 |
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VSS |
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VSS |
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VCC |
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I/O4 |
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I/O11 |
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I/O5 |
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I/O10 |
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I/O6 |
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30 |
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I/O9 |
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I/O7 |
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I/O8 |
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WE |
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28 |
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NC |
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A5 |
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27 |
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A14 |
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A6 |
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19 |
26 |
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A13 |
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A7 |
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25 |
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A12 |
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A8 |
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A11 |
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A9 |
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A10 |
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1041B–2
Selection Guide
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7C1041B-12 |
7C1041B-15 |
7C1041B-17 |
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7C1041B-20 |
7C1041B-25 |
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Maximum Access Time (ns) |
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12 |
15 |
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17 |
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20 |
25 |
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Maximum Operating Current (mA) |
Com’l |
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200 |
190 |
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180 |
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170 |
160 |
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Ind’l |
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220 |
210 |
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200 |
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190 |
180 |
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Maximum CMOS Standby Current |
Com’l |
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3 |
3 |
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3 |
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3 |
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(mA) |
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Com’l |
L |
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0.5 |
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0.5 |
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0.5 |
0.5 |
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Ind’l |
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6 |
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6 |
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Cypress Semiconductor Corporation • |
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3901 North First Street • |
San Jose • |
CA 95134 • |
408-943-2600 |
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March 23, 2001 |
CY7C1041B
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature –65° C to +150° C
Ambient Temperature with Power Applied–55° C to +125° C
Supply Voltage on VCC to Relative GND[1]–0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State[1]–0.5V to VCC + 0.5V
Electrical Characteristics Over the Operating Range
DC Input Voltage[1]–0.5V to VCC + 0.5V
Current into Outputs (LOW)20 mA
Operating Range
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Ambient |
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Range |
Temperature[2] |
VCC |
Commercial |
0° C to +70° C |
5V ± 0.5 |
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Industrial |
–40° C to +85° C |
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7C1041B-12 |
7C1041B-15 |
7C1041B-17 |
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Parameter |
Description |
Test Conditions |
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Min. |
Max. |
Min. |
Max. |
Min. |
Max. |
Unit |
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VOH |
Output HIGH Voltage |
VCC = Min., IOH = –4.0 mA |
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2.4 |
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2.4 |
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2.4 |
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V |
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VOL |
Output LOW Voltage |
VCC = Min., IOL = 8.0 mA |
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0.4 |
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0.4 |
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0.4 |
V |
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VIH |
Input HIGH Voltage |
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2.2 |
VCC |
2.2 |
VCC |
2.2 |
VCC |
V |
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+ 0.5 |
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+ 0.5 |
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+ 0.5 |
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VIL |
Input LOW Voltage[1] |
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–0.5 |
0.8 |
–0.5 |
0.8 |
–0.5 |
0.8 |
V |
IIX |
Input Load Current |
GND < VI < VCC |
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–1 |
+1 |
–1 |
+1 |
–1 |
+1 |
A |
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IOZ |
Output Leakage |
GND < VOUT < VCC, |
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–1 |
+1 |
–1 |
+1 |
–1 |
+1 |
A |
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Current |
Output Disabled |
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ICC |
VCC Operating |
VCC = Max., |
Com’l |
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200 |
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190 |
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180 |
mA |
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Supply Current |
f = fMAX = 1/tRC |
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Ind’l |
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220 |
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210 |
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200 |
mA |
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ISB1 |
Automatic CE |
Max. VCC, |
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> VIH |
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40 |
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40 |
mA |
CE |
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Power-Down Current |
VIN > VIH or |
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—TTL Inputs |
VIN < VIL, f = fMAX |
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ISB2 |
Automatic CE |
Max. VCC, |
Com’l |
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3 |
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3 |
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3 |
mA |
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Power-Down Current |
CE > VCC – 0.3V, |
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Com’l |
L |
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0.5 |
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0.5 |
mA |
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—CMOS Inputs |
VIN > VCC – 0.3V, |
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or VIN < 0.3V, f = 0 |
Ind’l |
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6 |
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mA |
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Notes:
1.VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2.TA is the case temperature.
2
CY7C1041B
Electrical Characteristics Over the Operating Range (continued)
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Test Conditions |
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7C1041B-20 |
7C1041B-25 |
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Parameter |
Description |
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Min. |
Max. |
Min. |
Max. |
Unit |
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VOH |
Output HIGH Voltage |
VCC = Min., IOH = –4.0 mA |
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2.4 |
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2.4 |
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V |
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VOL |
Output LOW Voltage |
VCC = Min., IOL = 8.0 mA |
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0.4 |
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0.4 |
V |
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VIH |
Input HIGH Voltage |
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2.2 |
VCC |
2.2 |
VCC + 0.5 |
V |
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+ 0.5 |
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VIL |
Input LOW Voltage[1] |
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–0.5 |
0.8 |
–0.5 |
0.8 |
V |
IIX |
Input Load Current |
GND < VI < VCC |
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–1 |
+1 |
–1 |
+1 |
A |
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IOZ |
Output Leakage |
GND < VOUT < VCC, |
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–1 |
+1 |
–1 |
+1 |
A |
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Current |
Output Disabled |
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ICC |
VCC Operating |
VCC = Max., |
Com’l |
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170 |
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160 |
mA |
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Supply Current |
f = fMAX = 1/tRC |
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Ind’l |
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180 |
mA |
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ISB1 |
Automatic CE |
Max. VCC, |
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40 |
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40 |
mA |
CE |
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Power-Down Current |
VIN > VIH or |
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—TTL Inputs |
VIN < VIL, f = fMAX |
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ISB2 |
Automatic CE |
Max. VCC, |
Com’l |
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3 |
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3 |
mA |
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Power-Down Current |
CE > VCC – 0.3V, |
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Com’l |
L |
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0.5 |
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0.5 |
mA |
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—CMOS Inputs |
VIN > VCC – 0.3V, |
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Ind’l |
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6 |
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mA |
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or VIN < 0.3V, f = 0 |
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Capacitance[3]
Parameter |
Description |
Test Conditions |
Max. |
Unit |
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CIN |
Input Capacitance |
TA = 25° C, f = 1 MHz, |
8 |
pF |
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VCC = 5.0V |
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COUT |
I/O Capacitance |
8 |
pF |
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AC Test Loads and Waveforms |
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R1 481Ω |
R1 481Ω |
ALL INPUT PULSES |
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5V |
5V |
3.0V |
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OUTPUT |
OUTPUT |
90% |
90% |
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10% |
10% |
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30 pF |
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R2 |
5 pF |
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R2 |
GND |
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INCLUDING |
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255Ω |
INCLUDING |
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255Ω |
≤ 3 ns |
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≤ 3 ns |
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JIG AND |
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JIG AND |
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SCOPE |
(a) |
SCOPE |
(b) |
1041B–3 |
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1041B–4 |
Equivalent to: THÉ VENIN EQUIVALENT |
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OUTPUT |
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167Ω |
1.73V |
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Note:
3.Tested initially and after any design or process changes that may affect these parameters.
3
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