Cypress Semiconductor CY7C466A-25PTC, CY7C466A-25JC, CY7C460A-10PC, CY7C460A-10JC, CY7C462A-10PTC Datasheet

CY7C460A/CY7C462A

CY7C464A/CY7C466A

Asynchronous, Cascadable 8K/16K/32K/64K x9 FIFOs

Features

Functional Description

•High-speed, low-power, first-in first-out (FIFO) memories

•8K x 9 FIFO (CY7C460A)

•16K x 9 FIFO (CY7C462A)

•32K x 9 FIFO (CY7C464A)

•64K x 9 FIFO (CY7C466A)

•10-ns access times, 20-ns read/write cycle times

•High-speed 50-MHz read/write independent of depth/width

•Low operating power

—ICC= 60 mA

—ISB =8 mA

•Asynchronous read/write

•Empty and Full flags

•Half Full flag (in standalone mode)

•Retransmit (in standalone mode)

•TTL-compatible

•Width and Depth Expansion Capability

•5V ± 10% supply

•PLCC, LCC, 300-mil and 600-mil DIP packaging

•Three-state outputs

•Pin compatible density upgrade to CY7C42X/46X family

•Pin compatible and functionally equivalent to IDT7205, IDT7206, IDT7207, IDT7208

The CY7C460A, CY7C462A, CY7C464A, and CY7C466A are respectively, 8K, 16K, 32K, and 64K words by 9-bit wide first-in first-out (FIFO) memories. Each FIFO memory is organized such that the data is read in the same sequential order that it was written. Full and Empty flags are provided to prevent overrun and underrun. Three additional pins are also provided to facilitate unlimited expansion in width, depth, or both. The depth expansion technique steers the control signals from one device to another by passing tokens.

The read and write operations may be asynchronous; each can occur at a rate of up to 50 MHz. The write operation occurs when the Write (W) signal is LOW. Read occurs when Read

(R) goes LOW. The nine data outputs go to the high-imped- ance state when R is HIGH.

A Half Full (HF) output flag is provided that is valid in the standalone (single device) and width expansion configurations. In the depth expansion configuration, this pin provides the expansion out (XO) information that is used to tell the next FIFO that it will be activated.

In the standalone and width expansion configurations, a LOW on the Retransmit (RT) input causes the FIFOs to retransmit the data. Read Enable (R) and Write Enable (W) must both be HIGH during a retransmit cycle, and then R is used to access the data.

The CY7C460A, CY7C462A, CY7C464A, and CY7C466A are fabricated using Cypress’s advanced 0.5µ RAM3 CMOS technology. Input ESD protection is greater than 2000V and latch-up is prevented by careful layout and the use of guard rings.

Logic Block Diagram

DATAINPUTS

Pin Configurations

DIP

PLCC/LCC

(D0− D 8)

Top View

Top View

3

8

W

NC

cc

4

5

W

1

28

VCC

D

D

V

D

D

W

WRITE

D2

4

3

2

1

32 31 30

D8

2

27

D4

CONTROL

5

29

D6

D

3

26

D

DUAL PORT

D7

3

5

D1

6

28

D2

4

D6

RAM ARRAY

25

WRITE

8K x 9

READ

D0

7

27

NC

D1

5

24

D7

POINTER

16K x 9

POINTER

XI

7C460A

7C460A

32K x 9

8

26

FL/RT

D0

6

23

FL/RT

64K x 9

FF

9

7C462A

25

MR

XI

7C462A

22

MR

7C464A

7

7C464A

Q0

10

7C466A

24

EF

FF

8

7C466A 21

EF

THREE–

Q1

11

23

XO/HF

Q0

9

20

XO/HF

NC

12

22

Q7

Q1

10

19

Q7

STATE

Q2

13

21

Q6

BUFFERS

15 16 17

Q2

11

18

Q6

14

18 19 20

DATAOUTPUTS

3

8

GND

NC

R

4

5

Q3

12

17

Q5

Q8

13

Q4

Q

Q

Q

Q

16

(Q0-Q 8)

GND

14

15

R

RESET

MR

C46XA–2

R

READ

LOGIC

FL/RT

C46XA–3

CONTROL

FLAG

EF

LOGIC

FF

EXPANSION

XI

LOGIC

XO/HF

C46XA–1

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 October 4, 1999

CY7C460A/CY7C462A

CY7C464A/CY7C466A

Selection Guide

	7C460A-10	7C460A-15	7C460A-25
	7C462A-10	7C462A-15	7C462A-25
	7C464A-10	7C464A-15	7C464A-25
	7C466A-10	7C466A-15	7C466A-25
Frequency (MHz)	50	40	28.5
Maximum Access Time (ns)	10	15	25

Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested.)

Storage Temperature ..................................	–65° C to +150° C
Ambient Temperature with	–55° C to +125° C
Power Applied .............................................
Supply Voltage to Ground Potential ...............	–0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ...............................................	–0.5V to +7.0V
DC Input Voltage............................................	–0.5V to +7.0V
Power Dissipation ..........................................................	1.0W

Electrical Characteristics Over the Operating Range[2]

Output Current, into Outputs (LOW)	............................ 20 mA
Static Discharge Voltage ...........................................	>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................	>200 mA

Operating Range

	Ambient
Range	Temperature	VCC
Commercial	0° C to + 70° C	5V ±	10%
Industrial	–40° C to +85° C	5V ±	10%
Military[1]	–55° C to +125° C	5V ±	10%

					7C460A/462A/464A/466A
						(-10,-15,-25)
Parameter	Description			Test Conditions	Min.		Max.	Unit
VOH	Output HIGH Voltage		VCC = Min., IOH = − 2.0 mA		2.4			V
VOL	Output LOW Voltage		VCC = Min., IOL = 8.0 mA				0.4	V
VIH	Input HIGH Voltage				2.2		VCC	V
VIL	Input LOW Voltage				− 0.5		0.8	V
IIX	Input Leakage Current		GND < VI < VCC		–10		+10	µ A
IOZ	Output Leakage Current			> VIH, GND < VO < VCC	–10		+10	µ A
			R
ICC	Operating Current		VCC = Max.,				60	mA
			IOUT = 0 mA, Freq. = 20 MHz
ISB	Standby Current		All Inputs = VIH min.				8	mA

Capacitance[4]

	Parameter	Description	Test Conditions	Max.	Unit
	CIN	Input Capacitance	TA = 25° C, f = 1 MHz,	10	pF
			VCC = 4.5V
	COUT	Output Capacitance		12	pF

Notes:

1.TA is the “instant on” case temperature.

2.See the last page of this specification for Group A subgroup testing information.

3.For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 1 second.

4.Tested initially and after any design or process changes that may affect these parameters.

2

			CY7C460A/CY7C462A
			CY7C464A/CY7C466A
AC Test Loads and Waveforms
5V	R1 500Ω	R1 500Ω	ALL INPUT PULSES
	5V
OUTPUT	OUTPUT	3.0V	90%	90%

10%

30 pF

R2

5 pF

R2

GND

10%

INCLUDING

333Ω

INCLUDING

333Ω

≤ 5 ns

≤

5 ns

C460A–6

JIG AND

C460A–4

JIG AND

C460A–5

SCOPE

(a)

SCOPE

(b)

Equivalent to:

THÉ VENIN EQUIVALENT

OUTPUT

200Ω

2V

Switching Characteristics Over the Operating Range[2, 5]

7C460A-10

7C460A-15

7C460A-25

7C462A-10

7C462A-15

7C462A-25

7C464A-10

7C464A-15

7C464A-25

7C466A-10

7C466A-15

7C466A-25

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Unit

tRC

Read Cycle Time

20

25

35

ns

tA

Access Time

10

15

25

ns

tRR

Read Recovery Time

10

10

10

ns

tPR

Read Pulse Width

10

15

25

ns

tLZR

Read LOW to Low Z

3

3

3

ns

[6]

Data Valid After Read HIGH

3

3

3

ns

tDVR

[6]

Read HIGH to High Z

15

15

18

ns

tHZR

tWC

Write Cycle Time

20

25

35

ns

tPW

Write Pulse Width

10

15

25

ns

tHWZ

Write HIGH to Low Z

5

5

5

ns

tWR

Write Recovery Time

10

10

10

ns

tSD

Data Set-Up Time

9

9

9

ns

tHD

Data Hold Time

0

0

0

ns

tMRSC

Cycle Time

20

25

35

ns

MR

tPMR

Pulse Width

10

15

25

ns

MR

tRMR

Recovery Time

10

10

10

ns

MR

tRPW

Read HIGH to

HIGH

10

15

25

ns

MR

tWPW

Write HIGH to

HIGH

10

15

25

ns

MR

tRTC

Retransmit Cycle Time

20

25

35

ns

tPRT

Retransmit Pulse Width

10

15

25

ns

tRTR

Retransmit Recovery Time

10

10

10

ns

tEFL

to

LOW

20

25

35

ns

MR

EF

tHFH

to

HIGH

20

25

35

ns

MR

HF

tFFH

to

HIGH

20

25

35

ns

MR

FF

tREF

Read LOW to

LOW

10

15

25

ns

EF

tRFF

Read HIGH to

HIGH

10

15

25

ns

FF

Notes:

5.Test conditions assume signal transmission time of 5 ns or less, timing reference levels of 1.5V and output loading of the specified IOL/IOH and 30-pF load capacitance, as in part (a) of AC Test Loads, unless otherwise specified.

6.tHZR and tDVR use capacitance loading as in part (b) of AC Test Loads.

3

CY7C460A/CY7C462A

CY7C464A/CY7C466A

Switching Characteristics Over the Operating Range[2, 5] (continued)

7C460A-10

7C460A-15

7C460A-25

7C462A-10

7C462A-15

7C462A-25

7C464A-10

7C464A-15

7C464A-25

7C466A-10

7C466A-15

7C466A-25

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Unit

tWEF

Write HIGH to

HIGH

10

15

25

ns

EF

tWFF

Write LOW to

LOW

10

15

25

ns

FF

tWHF

Write LOW to

LOW

10

15

35

ns

HF

tRHF

Read HIGH to

HIGH

10

15

35

ns

HF

tRAE

Effective Read from Write

10

15

25

ns

HIGH

tRPE

Effective Read Pulse Width

10

15

25

ns

After EF HIGH

tWAF

Effective Write from Read

10

15

25

ns

HIGH

tWPF

Effective Write Pulse

10

15

25

ns

Width After FF HIGH

tXOL

Expansion Out LOW

10

15

25

ns

Delay from Clock

tXOH

Expansion Out HIGH

10

15

25

ns

Delay from Clock

4

CY7C460A/CY7C462A

CY7C464A/CY7C466A

Switching Waveforms[7]

Asynchronous Read and Write

tRC

tPR

tA

tRR

tA

R

Q0− Q 8

tLZR

tDVR

tHZR

DATA VALID

DATA VALID

tWC

tPW tWR tPW

	W
		tSD	tHD		tSD	tHD
	D0− D 8	DATA VALID			DATA VALID
						C460A–7
Master	Reset		tMRSC [9]
	MR		tPMR
	R, W [8]		tRPW
		tEFL
	EF		tWPW	tRMR
		tHFH
	HF
		tFFH
	FF					C460A–8
Half Full Flag
	HALF FULL		HALF FULL+1			HALF FULL
	W
						tRHF
	R
		tWHF
	HF
						C460A–9

Notes:

7.A HIGH-to-LOW transition of either the write or read strobe causes a HIGH-to-LOW transition of the responding flag. Correspondingly, a LOW-to-HIGH strobe transition causes a LOW-to-HIGH flag transition.

8.W and R = VIH around the rising edge of MR.

9.tMSRC = t PMR + t RMR

5