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CBM-202LA
User's Manual
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CITIZEN CBM-202LA User's Manual

CONTROL IC FOR LINE THERMAL PRINTER
(FOR LT SERIES)
SPECIFICATIONS
MODEL CBM-202LA
GATE ARRAY
Updated on Oct. 25, 1996
Japan CBM Corporation
Information Systems Div.
CONTENTS
1 OUTLINE.................................................................................................................................................................3
2 GENERAL SPECIFICATIONS ................................................................................................................................4
2.1 SHAPE AND DIMENSIONS............................................................................................................................................... 4
2.2 STRUCTURE...................................................................................................................................................................... 4
2.3 OPERATING VOLTAGE .................................................................................................................................................... 4
2.4 OPERATING FREQUENCY............................................................................................................................................... 4
2.5 ENVIRONMENTAL SPECIFICATIONS............................................................................................................................. 4
2.6 APPLICABLE MODELS ..................................................................................................................................................... 4
3 OUTLINE OF CIRCUITS.........................................................................................................................................5
3.1 THERMAL HYSTERESIS CONTROL................................................................................................................................ 5
3.2 HEAD STROBE CONTROL ............................................................................................................................................... 5
3.3 BIT DATA PROCESSING FUNCTION............................................................................................................................... 5
3.4 8-BIT PARALLEL INPUT CIRCUIT ...................................................................................................................................5
3.5 GENERAL PURPOSE I/O CIRCUITS ................................................................................................................................. 5
4 DETAILED SPECIFICATIONS OF HARDWARE...................................................................................................6
4.1 ABSOLUTE MAXIMUM RATINGS................................................................................................................................... 6
4.2 RECOMMENDED OPERATING RANGE .......................................................................................................................... 6
4.3 DIRECT CURRENT CHARACTERISTIC ........................................................................................................................... 6
4.4 TERMINALS AND THEIR FUNCTIONS............................................................................................................................ 8
4.5 POWER TERMINAL.........................................................................................................................................................10
4.6 INTERNAL ADDRESS MAP ............................................................................................................................................ 11
4.7 PRINT DATA TRANSFER METHOD............................................................................................................................... 12
4.8 RESET CIRCUIT............................................................................................................................................................... 14
4.9 SYSTEM CLOCK CIRCUIT.............................................................................................................................................. 15
4.10 HEAD VOLTAGE INTERRUPTING CIRCUIT ............................................................................................................... 15
4.11 HEAD BREAK-OFF DETECTING CIRCUIT .................................................................................................................. 15
4.12 PARALLEL INPUT CIRCUIT..........................................................................................................................................16
4.13 ADDRESS LATCH CIRCUIT.......................................................................................................................................... 16
4.14 GENERAL PURPOSE I/O OUTPUT CIRCUIT................................................................................................................ 17
4.15 BIT DATA PROCESSING METHOD.............................................................................................................................. 17
4.16 PSEUDO-SRAM CONNECTING METHOD ................................................................................................................... 19
4.17 OTHER CONTROL TERMINALS................................................................................................................................... 19
5 OPERATION TIMING...........................................................................................................................................20
6 PACKAGE SPECIFICATION................................................................................................................................21
6.1 SHAPE AND DIMENSIONS............................................................................................................................................. 21
6.2 MOUNT PAD DIMENSIONS............................................................................................................................................ 22
7 REFERENTIAL CIRCUIT DIAGRAM...................................................................................................................23
8 REMARKS FOR MOUNTING ............................................................................................................................... 25
8.1 TEMPERATURE CONDITIONS FOR MOUNTING ......................................................................................................... 25
8.2 STORAGE CONDITIONS................................................................................................................................................. 26
8.3 OTHERS........................................................................................................................................................................... 26
9 PACKING SPECIFICATIONS ...............................................................................................................................27
1 OUTLINE
In order to assure proper operation, be sure to use this Gate Array following the contents of this specifications.
Absolutely, do not carry out anything other than specified in this specifications.
This Gate Array has the following specifications.
x With thermal hysteresis control function being added, high quality printing is made available. x With strobe split control function being added, printing is performed in small current. x Strobe signal excursion function can protect Head safely. x With the head resistance value measurement circuit being mounted, head break-off error can be detected. x Parallel interface is available by use of the parallel input port. x Address latch function is provided. x The general purpose I/O port can serve for input of a DIP SW, etc.. x Data processing function can serve to facilitate various kinds of data processing.
2 GENERAL SPECIFICATIONS
2.1 SHAPE AND DIMENSIONS
100-pin plastic QFP package
23.6 u 17.6 u 2.7 (mm)
(See Section 6. PACKAGE SPECIFICATION.)
2.2 STRUCTURE
C-MOS LSI
2.3 OPERATING VOLTAGE
5V ur 10% DC
2.4 OPERATING FREQUENCY
16MHz r 5%
2.5 ENVIRONMENTAL SPECIFICATIONS
Temperature Operating temperature - 40ºC 㨪 + 85ºC
Storage temperature - 65ºC 㨪 + 150 ºC
2.6 APPLICABLE MODELS
LT280, LT380 series
Printing system: Thermal line dot system
3 OUTLINE OF CIRCUITS
3.1 THERMAL HYSTERESIS CONTROL
When Line Thermal Head performs printing at high speed, heat remaining from printing which is one dot line before
may give some influence, resulting in blurred prints or trailing. This gate array, therefore, can serve to control
printing to the best result through monitoring state of operation of the preceding stage.
For printing of one dot line, one-dot-line data are transferred twice. The first data perform logical operation with
preceding data, serving as data for processing of print data for hysteresis supply. The second data substantially serve
for printing. Hysteresis supply (pre-pulse) and normal supply (main pulse) together compose one dot line supply.
To transfer data of one dot line, carry it out at high speed from CPU to the gate array by DMA, etc..
3.2 HEAD STROBE CONTROL
As one system to drive Line Thermal Head, one dot line is split into two or more blocks and current is supplied to each
of these blocks. Supply current capacity, thus, can be reduced. Switching in timing of current supply to these split
blocks is automatically performed by the gate array.
This is also equipped with a circuit which serves to prevent the thermal head from being damaged on occurrence of
strobe signal control failure due to CPU excursion, etc..
3.3 BIT DATA PROCESSING FUNCTION
This product is further provided with data processing function which is effective in developing printing data in bits.
For example, 8-bit data 180° turning function, 90° turning function, and 16-bit conversion (double font letter) function
are easily realized.
3.4 8-BIT PARALLEL INPUT CIRCUIT
Receiving of signals from Host is carried out in 8-bit parallel system. Received data from Host are STB, 8-bit data,
while data sent to Host are BUSY, ACK. When data are sent from Host, BUSY is output automatically. When CPU
starts reading the data, ACK is automatically output and BUSY is cancelled.
Use a general purpose port or CPU to deal with other control signals.
3.5 GENERAL PURPOSE I/O CIRCUITS
This is provided with 8-bit I/O usable for various kinds of input/output. As some pins are shared with other functions,
confirm each application before using it.
4 DETAILED SPECIFICATIONS OF HARDWARE
4.1 ABSOLUTE MAXIMUM RATINGS
ITEM SYMBOL CONDITIONS RATINGS UNIT
Supply Voltage Vdd -0.5 to +6.5 V
I/O Voltage Vi/ Vo -0.5 to Vdd+0.5 V
Output Current Io Output current 9mA type 20 mA
Output Current Io Output current 13.5mA type 30 mA
Operating Temperature Topt -40 to +85 ºC
Storage Temperature Tstg -65 to +150 ºC
4.2 RECOMMENDED OPERATING RANGE
ITEM SYMBOL MIN. MAX. UNIT
Supply Voltage Vdd 4.5 5.5 V
Input Voltage Vi 0 Vdd V
Ambient Temperature Ta -40 +85 ºC
High Level Input Voltage Vih 0.7Vdd Vdd V
Low Level Input Voltage Vil 0 0.3Vdd V
Input Rise/ Fall Time tri, tfi 0 200 ns
Current Consumption Icc - 30 mA
4.3 DIRECT CURRENT CHARACTERISTIC
(Unless otherwise specified, Vdd=5V r10%, Ta=-40㨪+85ºC)
ITEM SYMBOL CONDITION MIN TYP. MAX UNIT
Static Current Consumption
Static Current Consumption
Off-State Output Current
Input Clamp Voltage
Output Short-Circuit Current
Input Leakage Current Ii Vi=GND Note 3 -45 -131 -320
Low Level Output Current
(CMOS) Note 1
Low Level Output Voltage Vol Iol=0mA 0.1 V
High Level Output Voltage Voh Ioh=0ma(CMOS) Note 1 Vdd-0.1 V
Idds
Idds
Ioz
Vic
Ios
Iol Vol=0.4V Note 4
Vi=Vdd
Vi=GND
Vo=VddorGND
Ii=18mA
V0=0V Note 2
Vol=0.4V Note 5
9.0
13.5
0.1 200
26440
10
-1.2
-250
PA PA PA
V
mA
PA
mA
mA
SWITCHING CHARACTERISTICS (Unless otherwise specified, Vdd=5V r10%, Ta=-40㨪+85 ºC)
ITEM SYMBOL CONDITION MIN TYP. MAX UNIT
Toggle Frequency ftog Internal togle F/F (F/O=2) 120 MHz
Internal gate
F/O=1, Wiring length 0mm
Transfer Delay Time
INPUT/ OUTPUT PIN CAPACITY (Unless otherwise specified, Vdd=Vi=0V, Ta=+25ºC)
ITEM SYMBOL CONDITION MIN TYP. MAX UNIT
Input Terminal Cin f=1MHz 10 20 pF
Output Terminal Cout 0V for those other than measured pins 10 20 pF
I/O Terminal Ci/o 10 20 pF
Note 1: CMOS level output buffer (Vdd=5Vr10%, Ta=-40㨪+85 ºC)
Note 2: Output short-circuit current is available only in 1 pin of LSI for 1 second or less.
Note 3: Provided with pull-up resistance (50K ǡ)
Note 4: CMOS level output buffer (9.0mA type)
Note 5: CMOS level output buffer (13.5 mA type)
* A code indicates direction, where the one into which current flows is "positive."
tpd
F/O=2, Wiring length 2mm
Internal gate (power gate)
F/O= 2, Wiring length 2mm 0.40 ns
Input buffer
F/O =2, Wiring length 2mm 1.00 ns
0.27
0.50
ns
ns
4.4 TERMINALS AND THEIR FUNCTIONS
PIN
NO.
SIGNAL
NAME
I/O
DIRECTION
PIN CHARACTERISTIC FUNCTION
1 GND - GND
2 RAMOE Output CMOS9mA type with pull-up OE/RFSH pin of PS-RAM
3 DRQ Output CMOS9mA type with pull-up DMA request
4 HVC Output CMOS9mA type Head voltage control
5 HRCHK Output CMOS9mA type Changeover of Head cut-off detect voltage
6 HODATA Input CMOS type with pull-up Input of preceding data
7 EHCLK Output CMOS13.5mA type with pull-up Head clock output
8 EHDATA Output CMOS13.5mA type with pull-up Head data output
9 STB1 Output CMOS 13.5mA type Head strobe signal
10 STB2 Output CMOS13.5mA type Head strobe signal
11 STB3 Output CMOS13.5mA type Head strobe signal
12 Vdd - Vdd
13 STBLOG Input CMOS type with pull-up Head strobe signal logic
14 PART2 Input CMOS type with pull-up 2/3 split drive changeover
15 GND - GND
16 GND - GND
17 D0 I/O CMOS type with pull-up Data bus
18 D1 I/O CMOS type with pull-up Data bus
19 D2 I/O CMOS type with pull-up Data bus
20 D3 I/O CMOS type with pull-up Data bus
21 D4 I/O CMOS type with pull-up Data bus
22 D5 I/O CMOS type with pull-up Data bus
23 D6 I/O CMOS type with pull-up Data bus
24 D7 I/O CMOS type with pull-up Data bus
25 Vdd - VDD
26 PA17 Input CMOS type with pull-up Preset SW input
27 PA16 Input CMOS type with pull-up Preset SW input
28 PA15 Input CMOS type with pull-up Preset SW input
29 PA14 Input CMOS type with pull-up Preset SW input
30 PA13 Input CMOS type with pull-up Preset SW input
31 PA12 Input CMOS type with pull-up Preset SW input
32 PAI1 Input CMOS type with pull-up Preset SW input
33 PAI0 Input CMOS type with pull-up Preset SW input
34 PB17 Input CMOS type with pull-up Preset SW input
35 PBI6 Input CMOS type with pull-up Preset SW input
36 PBI5 Input CMOS type with pull-up Preset SW input
37 PB14 Input CMOS type with pull-up Preset SW input
38 PB13 Input CMOS type with pull-up Preset SW input
39 PBI2 Input CMOS type with pull-up Preset SW input
40 GND - GND
41 Vdd - VDD
42 PBI1 Input CMOS type with pull-up Preset SW input
43 PBI0 Input CMOS type with pull-up Preset SW input
44 PC17 Input CMOS type with pull-up Preset & Centro-data input
45 PC16 Input CMOS type with pull-up Preset & Centro-data input
PIN
NO.
SIGNAL
NAME
I/O
DIRECTION
PIN CHARACTERISTIC FUNCTION
46 PC15 Input CMOS type with pull-up Preset & Centro-data input
47 PC14 Input CMOS type with pull-up Preset & Centro-data input
48 PC13 Input CMOS type with pull-up Preset & Centro-data input
49 PC12 Input CMOS type with pull-up Preset & Centro-data input
50 PCI1 Input CMOS type with pull-up Preset & Centro-data input
51 PCI0 Input CMOS type with pull-up Preset & Centro-data input
52 STB Input CMOS type with pull-up Head strobe ON signal
53 ASTB Input CMOS type with pull-up Address latch signal
54 GND - GND
55 BUSY Output CMOS13.5mA type with pull-up Centro BUSY output
56 INTR Output CMOS13.5mA type with pull-up Centro interrupt request
57 ACK Output CMOS13.5mA type with pull-up Centro ACK output
58 PA07 Output CMOS13.5mA type with pull-up Address latch output & general purpose output
59 PA06 Output CMOS13.5mA type with pull-up Address latch output & general purpose output
60 Vdd - VDD
61 PA05 Output CMOS13.5mA type with pull-up Address latch output & general purpose output
62 PA04 Output CMOS13.5mA type with pull-up Address latch output &general purpose output
63 PA03 Output CMOS13.5mA type with pull-up Address latch output &general purpose output
64 PA02 Output CMOS13.5mA type with pull-up Address latch output &general purpose output
65 PA01 Output CMOS13.5mA type with pull-up Address latch output &general purpose output
66 GND - GND
67 PA00 Output CMOS13.5mA type with pull-up Address latch output &general purpose output
68
69
70
71
72
73
74
75
76
77
78
79
80 GND - GND
81 A14 Input CMOS type with pull-up Address bus input
82 A13 Input CMOS type with pull-up Address bus input
83 A12 Input CMOS type with pull-up Address bus input
84 A11 Input CMOS type with pull-up Address bus input
85 A6 Input CMOS type with pull-up Address bus input
86 A5 Input CMOS type with pull-up Address bus input
87 A3 Input CMOS type with pull-up Address bus input
88 A2 Input CMOS type with pull-up Address bus input
89 A1 Input CMOS type with pull-up Address bus input
90 GND - GND
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