BSI BS62UV4000TI, BS62UV4000TC, BS62UV4000STI, BS62UV4000STC, BS62UV4000SI Datasheet

	BSI	Ultra Low Power/Voltage CMOS SRAM
		512K X 8 bit	BS62UV4000
FEATURES			DESCRIPTION
• Ultra low operation voltage : 1.8V ~ 3.6V			The BS62UV4000 is a high performance, ultra low power CMOS
• Ultra low power consumption :			Static Random Access Memory organized as 524,288 words by 8 bits
Vcc = 2.0V C-grade: 15mA (Max.) operating current			and operates from a wide range of 1.8V to 3.6V supply voltage.
	I -grade: 20mA (Max.) operating current		Advanced CMOS technology and circuit techniques provide both high
	0.2uA (Typ.) CMOS standby current		speed and low power features with a typical CMOS standby current of
Vcc = 3.0V C-grade: 20mA (Max.) operating current			0.2uA and maximum access time of 70ns in 2.0V operation.
	I -grade: 25mA (Max.) operating current		Easy memory expansion is provided by an active LOW chip
	0.25uA (Typ.) CMOS standby current		enable (CE), and active LOW output enable (OE) and three-state
• High speed access time :			output drivers.
-70	70ns (Max.) at Vcc = 2.0V		The BS62UV4000 has an automatic power down feature, reducing the
-10	100ns (Max.) at Vcc = 2.0V		power consumption significantly when chip is deselected.
• Automatic power down when chip is deselected			The BS62UV4000 is available in the JEDEC standard 32 pin SOP
• Three state outputs and TTL compatible			, TSOP, TSOP II and STSOP

•Fully static operation

•Data retention supply voltage as low as 1.5V

•Easy expansion with CE and OE options

PRODUCT FAMILY

				SPEED		POWER DISSIPATION
	PRODUCT	OPERATING	Vcc		STANDBY		Operating
				( ns )					PKG
					( I CCSB1	, Max )	( I CC , Max )
	FAMILY	TEMPERATURE	RANGE	Vcc = 2.0V	Vcc = 2.0V	Vcc =3.0V	Vcc = 2.0V	Vcc =3.0V	TYPE
	BS62UV4000TC								TSOP- 32
	BS62UV4000STC	+0 O C to +70O C							STSOP-32
	BS62UV4000SC		1.8V ~ 3.6V	70 / 100	1uA	1.5uA	15mA	20mA	SOP -32
	BS62UV4000EC								TSOP2-32
	BS62UV4000PC								PDIP -32
	BS62UV4000TI								TSOP-32
	BS62UV4000STI	-40 O C to +85O C							STSOP-32
	BS62UV4000SI		1.8V ~ 3.6V	70 / 100	2uA	3uA	20mA	25mA	SOP - 32
	BS62UV4000EI								TSOP2-32
	BS62UV4000PI								PDIP - 32

PIN CONFIGURATIONS

BLOCK DIAGRAM

		A18		•					VCC
		A16		1		32
				2		31			A15
		A14		3		30			A17
		A12		4		29			WE
		A7		5		28			A13
		A6		6		27			A8
		A5		7		26			A9
		A4		8	BS62UV4000SC	25			A11
		A3		9	BS62UV4000SI	24			OE
		A2		10	BS62UV4000EC	23			A10
		A1			BS62UV4000EI
		A0		11 BS62UV4000PC		22			CE
				12 BS62UV4000PI		21			DQ7
		DQ0		13		20			DQ6
		DQ1		14		19			DQ5
		DQ2		15		18			DQ4
		GND		16		17			DQ3
A11		1•					32						OE
A9		2					31						A10
A8		3					30						CE
A13		4					29						DQ7
WE		5					28						DQ6
A17		6		BS62UV4000TC			27						DQ5
A15		7					26						DQ4
VCC		8		BS62UV4000STC			25						DQ3
A18		9		BS62UV4000TI			24						GND
A16		10		BS62UV4000STI			23						DQ2
A14		11					22						DQ1
A12		12					21						DQ0
A7		13					20						A0
A6		14					19						A1
A5		15					18						A2
A4		16					17						A3

A13
A17
A15	Address
A18		22	Row		2048	Memory Array
A16	Input
A14
A12	Buffer		Decoder			2048 X 2048
A7
A6
A5
A4
						2048
DQ0	8		Data	8		Column I/O
DQ1			Input
DQ2			Buffer			Write Driver
DQ3					8	Sense Amp
DQ4	8		Data
DQ5						256
			Output
DQ6			Buffer
DQ7						Column Decoder
CE						16
	Control
WE						Address Input Buffer
OE
Vdd
GND						A11 A9 A8 A3 A2 A1 A0 A10

Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.

R0201-BS62UV4000	1	Revision 2.4
		April 2002

BSI

BS62UV4000

PIN DESCRIPTIONS

Name

Function

A0-A18 Address Input

These 19 address inputs select one of the 524,288 x 8-bit words in the RAM

Chip Enable Input

CE

CE

is active LOW. Chip enables must be active when data read from or write to the

device. if chip enable is not active, the device is deselected and is in a standby power

mode. The DQ pins will be in the high impedance state when the device is deselected.

WE Write Enable Input

The write enable input is active LOW and controls read and write operations. With the

chip selected, when

is HIGH and

is LOW, output data will be present on the

WE

OE

DQ pins; when

is LOW, the data present on the DQ pins will be written into the

WE

selected memory location.

OE Output Enable Input

The output enable input is active LOW. If the output enable is active while the chip is

selected and the write enable is inactive, data will be present on the DQ pins and they

will be enabled. The DQ pins will be in the high impedance state when

is inactive.

OE

DQ0-DQ7 Data Input/Output

These 8 bi-directional ports are used to read data from or write data into the RAM.

Ports

Vcc

Power Supply

GND

Ground

TRUTH TABLE

MODE	WE	CE	OE	I/O OPERATION	Vcc CURRENT
Not selected	X	H	X	High Z	ICCSB, ICCSB1
Output Disabled	H	L	H	High Z	ICC
Read	H	L	L	DOUT	ICC
Write	L	L	X	IN	ICC
				D

ABSOLUTE MAXIMUM RATINGS(1)

SYMBOL	PARAMETER	RATING	UNITS
VTERM	Terminal Voltage with	-0.5 to	V
	Respect to GND	Vcc+0.5
TBIAS	Temperature Under Bias	-40 to +125	O C
TSTG	Storage Temperature	-60 to +150	O C
PT	Power Dissipation	1.0	W
IOUT	DC Output Current	20	mA

1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

OPERATING RANGE

	RANGE	AMBIENT	Vcc
		TEMPERATURE
	Commercial	0 O C to +70 O C	1.8V ~ 3.6V
	Industrial	-40 O C to +85 O C	1.8V ~ 3.6V

CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)

SYMBOL	PARAMETER	CONDITIONS	MAX.	UNIT
CIN	Input	VIN=0V	6	pF
	Capacitance
CDQ	Input/Output	VI/O=0V	8	pF
	Capacitance

1. This parameter is guaranteed and not tested.

R0201-BS62UV4000	2	Revision 2.4
		April 2002

		BSI							BS62UV4000
	DC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC )
	PARAMETER		PARAMETER		TEST CONDITIONS			MIN. TYP. (1)		MAX.	UNITS
	NAME		Guaranteed Input Low							0.6
	VIL						Vcc = 2.0 V	-0.5	--		V
			Voltage(2)				Vcc = 3.0 V			0.8
	VIH		Guaranteed Input High				Vcc = 2.0 V	1.4	--	Vcc+0.2	V
			Voltage(2)				Vcc = 3.0 V	2.0
	IIL		Input Leakage Current	Vcc = Max, VIN = 0V to Vcc				--	--	1	uA
					IH	IH
	IOL		Output Leakage Current	Vcc = Max, CE = V , or OE = V ,				--	--	1	uA
				VI/O = 0V to Vcc
	V	OL	Output Low Voltage		OL		Vcc = 2.0 V	--	--	0.4	V
				Vcc = Max, I = 1mA			Vcc = 3.0 V
	VOH		Output High Voltage	Vcc = Min, IOH = -0.5mA			Vcc = 2.0 V	1.6	--	--	V
							Vcc = 3.0 V	2.4
										15
	ICC		Operating Power Supply	CE = VIL, IDQ = 0mA, F = Fmax(3)			Vcc = 2.0 V	--	--		mA
										20
			Current				Vcc = 3.0 V
	ICCSB		Standby Current-TTL	CE = VIH, IDQ = 0mA			Vcc = 2.0 V	--	--	0.6	mA
							Vcc = 3.0 V			1
	ICCSB1		Standby Current-CMOS	CE	Vcc-0.2V,		Vcc = 2.0 V	--	0.2	1	uA
				IN	IN	0.2V	Vcc = 3.0 V		0.25	1.5
				V	Vcc - 0.2V or V

1.Typical characteristics are at TA = 25oC.

2.These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.

3.Fmax = 1/tRC .

DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70oC )

SYMBOL

PARAMETER

TEST CONDITIONS

MIN.

TYP. (1)

MAX.

UNITS

Vcc - 0.2V

VDR

Vcc for Data Retention

CE

1.5

--

--

V

VIN

Vcc - 0.2V or VIN

0.2V

Vcc - 0.2V

ICCDR

Data Retention Current

CE

--

0.1

1

uA

VIN

Vcc - 0.2V or VIN

0.2V

tCDR

Chip Deselect to Data

0

--

--

ns

Retention Time

See Retention Waveform

tR

Operation Recovery Time

(2)

--

--

ns

TRC

1.Vcc = 1.5V, TA = + 25OC

2.tRC = Read Cycle Time

LOW VCC DATA RETENTION WAVEFORM ( CE Controlled )

				Data Retention Mode
Vcc			Vcc			VDR ≥ 1.5V	Vcc
			t CDR				t R
						≥ Vcc - 0.2V
			VIH		CE		VIH
	CE

R0201-BS62UV4000	3	Revision 2.4
		April 2002

BSI

BS62UV4000

AC TEST CONDITIONS

KEY TO SWITCHING WAVEFORMS

Input Pulse Levels

Vcc/0

Input Rise and Fall Times

5ns

WAVEFORM

INPUTS

OUTPUTS

Input and Output

0.5Vcc

MUST BE

MUST BE

Timing Reference Level

STEADY

STEADY

MAY CHANGE

WILL BE

AC TEST LOADS AND WAVEFORMS

FROM H TO L

CHANGE

FROM H TO L

2V

1333 Ω

2V

1333 Ω

MAY CHANGE

WILL BE

FROM L TO H

CHANGE

OUTPUT

OUTPUT

DON ,T CARE:

FROM L TO H

100PF

5PF

CHANGE :

INCLUDING

2000

Ω

INCLUDING

2000

Ω

ANY CHANGE

STATE

JIG AND

JIG AND

PERMITTED

UNKNOWN

SCOPE

SCOPE

DOES NOT

CENTER

FIGURE 1A

FIGURE 1B

APPLY

LINE IS HIGH

THEVENIN EQUIVALENT

IMPEDANCE

”OFF ”STATE

OUTPUT

800 Ω

1.2V

ALL INPUT PULSES

Vcc

10%

10%

90% 90%

GND

→

←

→

← 5ns

FIGURE 2

AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 2.0V ) READ CYCLE

JEDEC	PARAMETER			BS62UV4000-70		BS62UV4000-10
PARAMETER		DESCRIPTION							UNIT
	NAME			MIN. TYP. MAX.		MIN. TYP. MAX.
NAME
tAVAX	tRC	Read Cycle Time	70	--	--	100	--	--	ns
tAVQV	tAA	Address Access Time	--	--	70	--	--	100	ns
tELQV	tACS	Chip Select Access Time	--	--	70	--	--	100	ns
tGLQV	tOE	Output Enable to Output Valid	--	--	35	--	--	50	ns
tELQX	tCLZ	Chip Select to Output Low Z	10	--	--	15	--	--	ns
tGLQX	tOLZ	Output Enable to Output in Low Z	10	--	--	15	--	--	ns
tEHQZ	tCHZ	Chip Deselect to Output in High Z	0	--	35	0	--	40	ns
tGHQZ	tOHZ	Output Disable to Output in High Z	0	--	30	0	--	35	ns
tAXOX	tOH	Output Disable to Output Address Change	10	--	--	15	--	--	ns

R0201-BS62UV4000	4	Revision 2.4
		April 2002