BSI BS62LV4001TI, BS62LV4001TC, BS62LV4001STI, BS62LV4001STC, BS62LV4001SI Datasheet

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R0201-BS62LV4001

Revision 2.5

April 2002

BSI

Low Power/Voltage CMOS SRAM

512K X 8 bit

• Wide Vcc operation voltage : 2.4V ~ 5.5V

• Low power consumption

Vcc = 3.0V C-grade: 20mA (Max.) operating current

I -grade: 25mA (Max.) operating current

0.25uA (Typ.) CMOS standby current

Vcc = 5.0V C-grade: 45mA (Max.) operation current

I -grade: 50mA (Max.) operating current

1.5uA (Typ.) CMOS standby current

• High speed access time :

-70 70ns (Max.) at Vcc = 3.0V

-10 100ns (Max.) at Vcc = 3.0V

• Automatic power down when chip is deselected

• Three state outputs and TTL compatible

• Fully static operation

• Data retention supply voltage as low as 1.5V

• Easy expansion with CE and OE options

The BS62LV4001 is a high performance, low power CMOS

Static Random Access Memory organized as 524,288 words by 8 bits

and operates from a wide range of 2.4V to 5.5V supply voltage.

Advanced CMOS technology and circuit techniques provide both high

speed and low power features with maximum access time of 70/ 100ns

in 3.0V operation.

Easy memory expansion is provided by an active LOW chip

enable (CE), and active LOW output enable (OE) and three-state

output drivers.

The BS62LV4001 has an automatic power down feature, reducing the

power consumption significantly when chip is deselected.

The BS62LV4001 is available in DICE form, JEDEC standard 32 pin

SOP, 32 pin TSOPII, 32 pin TSOP and 32 pin Small SOP.

 FEATURES

 GENERAL DESCRIPTION

 FUNCTIONAL BLOCK DIAGRAM

 PRODUCT FAMILY

 PIN CONFIGURATIONS

Brilliance Semiconductor Inc

. reserves the right to modify document contents without notice.

Address

Input

Buffer

Row

Decoder

Memory Array

2048 X 2048

Column I/O

Sense Amp

Write Driver

Column Decoder

Data

Buffer

Output

Address Input Buffer

Data

Buffer

Input

Control

Gnd

Vdd

DQ5

DQ4

A13

A17

A15

A18

A16

A14

A12

DQ7

DQ6

DQ3

DQ2

DQ1

DQ0

256

2048

A11 A9 A8 A3 A2 A1 A0 A10

BS62LV4001

A18

A16

A14

A12

DQ0

DQ1

DQ2

GND

VCC

A15

A17

A13

A11

A10

DQ7

DQ6

DQ5

DQ4

DQ3

•

BS62LV4001SC

BS62LV4001SI

BS62LV4001EC

BS62LV4001EI

BS62LV4001PC

BS62LV4001PI

A10

DQ7

DQ6

DQ5

DQ4

DQ3

GND

DQ2

DQ1

DQ0

A11

A13

A17

A15

A18

A16

A14

A12

•

BS62LV4001TC

BS62LV4001STC

BS62LV4001TI

BS62LV4001STI

R0201-BS62LV4001

Revision 2.5

April 2002

Name Function

A0-A18 Address Input

These 19 address inputs select one of the 524,288 x 8-bit words in the RAM

CE Chip Enable Input

CE is active LOW. Chip enable must be active when data read from or write to the

device. if chip enable is not active, the device is deselected and is in a standby power

mode. The DQ pins will be in the high impedance state when the device is deselected.

WE Write Enable Input

The write enable input is active LOW and controls read and write operations. With the

chip selected, when WE is HIGH and OE is LOW, output data will be present on the

DQ pins; when WE is LOW, the data present on the DQ pins will be written into the

selected memory location.

OE Output Enable Input

The output enable input is active LOW. If the output enable is active while the chip is

selected and the write enable is inactive, data will be present on the DQ pins and they

will be enabled. The DQ pins will be in the high impedance state when OE is inactive.

DQ0-DQ7 Data Input/Output

Ports

These 8 bi-directional ports are used to read data from or write data into the RAM.

Vcc

Power Supply

Gnd

Ground

 TRUTH TABLE

 PIN DESCRIPTIONS

BSI

MODE WE CE OE I/O OPERATION Vcc CURRENT

Not selected X H X High Z I

CCSB

, I

CCSB1

Output Disabled H L H High Z I

Read H L L D

OUT

Write L L X D

SYMBOL PARAMETER CONDITIONS MAX. UNIT

Input

Capacitance

=0V 6 pF

Input/Output

Capacitance

I/O

=0V 8 pF

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these

or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

reliability.

1. This parameter is guaranteed and not tested.

 ABSOLUTE MAXIMUM RATINGS

(1)

 OPERATING RANGE

 CAPACITANCE

(1)

(TA = 25

C, f = 1.0 MHz)

SYMBOL PAR AMETER RATING UNITS

TERM

Terminal Voltage with

Respect to GND

-0.5 to

Vcc+0.5

BIAS

Temperature Under Bias -40 to +125

STG

Storage Temperature -60 to +150

Power Dissipation 1.0 W

OUT

DC Output Current 20 mA

BS62LV4001

RANGE

AMBIENT

TEMPERATURE

Vcc

Commercial 0

C to +70

C 2.4~5.5V

Industrial -40

C to +85

C 2.4~5.5V

R0201-BS62LV4001

Revision 2.5

April 2002

PAR AMETER

NAME

PAR AMETER TEST CONDITIONS MIN. TYP.

(1)

MAX.

UNITS

Vcc=3.0V

Guaranteed Input Low

Voltage

(2)

Vcc=5.0V

-0.5 -- 0.8 V

Vcc=3.0V

2.0

Guaranteed Input High

Voltage

(2)

Vcc=5.0V

2.2

-- Vcc+0.2 V

Input Leakage Current Vcc = Max, V

= 0V to Vcc -- -- 1 uA

Output Leakage Current

Vcc = Max, CE = V

, or OE = V

I/O

= 0V to Vcc

-- -- 1 uA

Vcc=3.0V

Output Low Voltage Vcc = Max, I

= 2mA

Vcc=5.0V

-- -- 0.4 V

Vcc=3.0V

Output High Voltage Vcc = Min, I

= -1mA

Vcc=5.0V

2.4 -- -- V

Vcc=3.0V

-- -- 20

Operating Power Supply

Current

CE = V

, I

= 0mA, F = Fmax

(3)

Vcc=5.0V

-- -- 45

Vcc=3.0V

-- -- 1

CCSB

Standby Current-TTL CE = V

, I

= 0mA

Vcc=5.0V

-- -- 2

Vcc=3.0V

-- 0.25 1.5

CCSB1

Standby Current-CMOS

Vcc-0.2V,

Vcc - 0.2V or V

0.2V

Vcc=5.0V

-- 1.5 15

1. Typical characteristics are at TA = 25

2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.

3. Fmax = 1/t

 DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70

C )

1. Vcc = 1.5V, T

= + 25

2. t

= Read Cycle Time

 DC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70

C )

BSI

 LOW V

DATA RETENTION WAVEFORM ( CE Controlled )

Data Retention Mode

Vcc

t CDR

Vcc

t R

VIHVIH

Vcc

VDR 1.5V

≥

CE Vcc - 0.2V

≥

BS62LV4001

SYMBOL PAR AME TER TEST CONDITIONS MIN. TYP.

(1)

MAX. UNITS

Vcc for Data Retention

CE Њ Vcc - 0.2V

Њ Vcc - 0.2V or V

Љ 0.2V

1.5 -- -- V

CCDR

Data Retention Current

Vcc - 0.2V

IN Њ

Vcc - 0.2V or V

IN Љ

0.2V

-- 0.1 1 uA

CDR

Chip Deselect to Data

Retention Time

0 -- -- ns

Operation Recovery Time

See Retention Waveform

(2)

-- -- ns

R0201-BS62LV4001

Revision 2.5

April 2002

JEDEC

PARAMETER

NAME

PARAMETER

NAME

DESCRIPTION

BS62LV4001-70

MIN. TYP. MAX.

BS62LV4001-10

MIN. TYP. MAX.

UNIT

AVAX

Read Cycle Time

70 -- -- 100 -- -- ns

AVQV

Address Access Time

-- -- 70 -- -- 100 ns

ELQV

ACS

Chip Select Access Time

-- -- 70 -- -- 100 ns

GLQV

Output Enable to Output Valid

-- -- 35 -- -- 50 ns

ELQX

CLZ

Chip Select to Output Low Z

10 -- -- 15 -- -- ns

GLQX

OLZ

Output Enable to Output in Low Z

10 -- -- 15 -- -- ns

EHQZ

CHZ

Chip Deselect to Output in High Z

0--350-4-0ns

GHQZ

OHZ

Output Disable to Output in High Z

0--300-3-5ns

AXOX

Output Disable to Output Address Change

10 -- -- 15 -- -- ns

Input Pulse Levels

Input Rise and Fall Times

Input and Output

Timing Reference Level

Vcc/0

5ns

0.5Vcc

 AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70

C , Vcc = 3.0V )

READ CYCLE

 AC TEST CONDITIONS

 AC TEST LOADS AND WAVEFORMS

 KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

MUST BE

STEADY

MAY CHANGE

FROM H TO L

DON T CAR

ANY CHANG

PERMITTED

E: CHANGE :

E STATE

DOES NOT

APPLY

MUST BE

STEADY

WILL BE

CHANGE

FROM H TO L

UNKNOWN

CENTER

LINE IS HIGH

IMPEDANCE

”OFF ”STATE

MAY CHANGE

FROM L TO H

WILL BE

CHANGE

FROM L TO H

BSI

BS62LV4001

Ω667

THEVENIN EQUIVALENT

ALL INPUT PULSES

→

10%

←

90%

Vcc

GND

→

←

5ns

90%

10%

1.73V

OUTPUT

FIGURE 2

3.3V

OUTPUT

INCLUDING

JIG AND

SCOPE

Ω

1269

Ω

1404

5PF

FIGURE 1B

3.3V

OUTPUT

INCLUDING

JIG AND

SCOPE

Ω

1269

Ω

100PF

FIGURE 1A

1404

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