BSI BS62LV2001TI-70, BS62LV2001DC-70, BS62LV2001DC-10, BS62LV2001TI-10, BS62LV2001TC-70 Datasheet
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BSI |
Very Low Power/Voltage CMOS SRAM |
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256K X 8 bit |
BS62LV2001 |
FEATURES
•Wide Vcc operation voltage : 2.4V ~ 5.5V
•Very low power consumption :
Vcc = 3.0V C-grade : 20mA (Max.) operating current I- grade : 25mA (Max.) operating current 0.1uA (Typ.) CMOS standby current
Vcc = 5.0V C-grade : 35mA (Max.) operating current I- grade : 40mA (Max.) operating current 0.6uA (Typ.) CMOS standby current
• High speed access time :
-70 70ns(Max.) at Vcc = 3.0V -10 100ns(Max.) at Vcc = 3.0V
•Automatic power down when chip is deselected
•Three state outputs and TTL compatible
•Fully static operation
•Data retention supply voltage as low as 1.5V
•Easy expansion with CE2, CE1, and OE options
•All I/O pins are 3V/5V tolerant
DESCRIPTION
The BS62LV2001 is a high performance, very low power |
CMOS |
Static Random Access Memory organized as 262,144 words |
by 8 bits |
and operates in a wide range of 2.4V to 5.5V supply voltage. |
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Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.1uA and maximum access time of 70ns in 3V operation.
Easy memory expansion is provided by an active LOW chip enable (CE1), an active HIGH chip enable (CE2), and active LOW output enable (OE) and three-state output drivers.
The BS62LV2001 has an automatic power down feature, reducing the power consumption significantly when chip is deselected.
The BS62LV2001 is available in DICE form, JEDEC standard 32 pin 450mil Plastic SOP, 8mmx13.4mm STSOP, and 8mmx20mm TSOP.
PRODUCT FAMILY
PIN CONFIGURATIONS |
BLOCK DIAGRAM |
A11 |
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1• |
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OE |
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A8 |
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CE1 |
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A13 |
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DQ7 |
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WE |
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DQ6 |
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CE2 |
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BS62LV2001TC |
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DQ5 |
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A15 |
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DQ4 |
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VCC |
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BS62LV2001STC |
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DQ3 |
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A17 |
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BS62LV2001TI |
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GND |
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A16 |
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BS62LV2001STI |
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DQ2 |
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A14 |
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DQ1 |
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A12 |
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DQ0 |
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A7 |
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A0 |
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A6 |
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A1 |
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A5 |
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A2 |
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A4 |
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A3 |
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A17 |
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1• |
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VCC |
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A16 |
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A15 |
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A14 |
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CE2 |
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A12 |
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WE |
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A7 |
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A13 |
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A6 |
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A8 |
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A5 |
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7 |
BS62LV2001SC 26 |
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A9 |
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A4 |
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BS62LV2001SI |
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A11 |
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A3 |
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OE |
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A2 |
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A10 |
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A1 |
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CE1 |
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A0 |
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DQ7 |
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DQ0 |
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DQ6 |
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DQ1 |
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DQ5 |
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DQ2 |
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DQ4 |
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GND |
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DQ3 |
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A13 |
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A17 |
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A15 |
Address |
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Memory Array |
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A16 |
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1024 |
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A14 |
Input |
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A12 |
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Decoder |
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1024 x 2048 |
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A7 |
Buffer |
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A6 |
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A5 |
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A4 |
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2048 |
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DQ0 |
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Data |
8 |
Column I/O |
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DQ1 |
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Input |
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DQ2 |
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Buffer |
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Write Driver |
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DQ3 |
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8 |
Sense Amp |
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DQ4 |
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Data |
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DQ5 |
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256 |
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Output |
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DQ6 |
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Buffer |
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DQ7 |
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Column Decoder |
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CE1 |
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16 |
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CE2 |
Control |
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Address Input Buffer |
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WE |
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OE |
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Vdd |
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Gnd |
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A11 A9 A8 A3 A2 A1 A0 |
A10 |
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
R0201-BS62LV2001 |
1 |
Revision 2.5 |
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April 2002 |
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BSI |
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BS62LV2001 |
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PIN DESCRIPTIONS |
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Name |
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Function |
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A0-A17 Address Input |
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These 18 address inputs select one of the 262,144 x 8-bit words in the RAM |
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Chip Enable 1 Input |
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is active LOW and CE2 is active HIGH. Both chip enables must be active when |
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CE1 |
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CE1 |
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CE2 Chip Enable 2 Input |
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data read from or write to the device. If either chip enable is not active, the device is |
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deselected and is in a standby power mode. The DQ pins will be in the high |
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impedance state when the device is deselected. |
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Write Enable Input |
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The write enable input is active LOW and controls read and write operations. With the |
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WE |
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chip selected, when |
WE |
is HIGH and |
OE |
is LOW, output data will be present on the |
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DQ pins; when |
WE |
is LOW, the data present on the DQ pins will be written into the |
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selected memory location. |
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Output Enable Input |
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The output enable input is active LOW. If the output enable is active while the chip is |
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OE |
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selected and the write enable is inactive, data will be present on the DQ pins and they |
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will be enabled. The DQ pins will be in the high impedance state when |
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is inactive. |
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OE |
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DQ0 – DQ7 Data Input/Output |
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These 8 bi-directional ports are used to read data from or write data into the RAM. |
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Ports |
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Vcc |
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Power Supply |
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Gnd |
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Ground |
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TRUTH TABLE
MODE |
WE |
CE1 |
CE2 |
OE |
I/O OPERATION |
Vcc CURRENT |
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Not selected |
X |
H |
X |
X |
High Z |
ICCSB, ICCSB1 |
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(Power Down) |
X |
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L |
X |
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Output Disabled |
H |
L |
H |
H |
High Z |
ICC |
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Read |
H |
L |
H |
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DOUT |
ICC |
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Write |
L |
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H |
X |
DIN |
ICC |
ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL |
PARAMETER |
RATING |
UNITS |
V TERM |
Terminal Voltage with |
-0.5 to |
V |
Respect to GND |
Vcc+0.5 |
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T BIAS |
Temperature Under Bias |
-40 to +125 |
O C |
T STG |
Storage Temperature |
-60 to +150 |
O C |
P T |
Power Dissipation |
1.0 |
W |
I OUT |
DC Output Current |
20 |
mA |
1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING RANGE
RANGE |
AMBIENT |
Vcc |
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TEMPERATURE |
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Commercial |
0 O C to +70 O C |
2.4V ~ 5.5V |
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Industrial |
-40 O C to +85 O C |
2.4V ~ 5.5V |
CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz) |
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SYMBOL |
PARAMETER |
CONDITIONS |
MAX. |
UNIT |
CIN |
Input |
VIN=0V |
6 |
pF |
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Capacitance |
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CDQ |
Input/Output |
VI/O=0V |
8 |
pF |
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Capacitance |
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1. This parameter is guaranteed and not tested.
R0201-BS62LV2001 |
2 |
Revision 2.5 |
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April 2002 |
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BSI |
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BS62LV2001 |
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DC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC ) |
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PARAMETER |
PARAMETER |
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TEST CONDITIONS |
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MIN. |
TYP. (1) |
MAX. |
UNITS |
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NAME |
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VIL |
Guaranteed |
Input |
Low |
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Vcc=3.0V |
-0.5 |
-- |
0.8 |
V |
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Voltage(2) |
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Vcc=5.0V |
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VIH |
Guaranteed |
Input |
High |
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Vcc=3.0V |
2.0 |
-- |
Vcc+0.2 |
V |
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Voltage(2) |
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Vcc=5.0V |
2.2 |
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IIL |
Input Leakage Current |
Vcc = Max, VIN = 0V to Vcc |
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1 |
uA |
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IOL |
Output Leakage Current |
Vcc = Max, CE1= VIH, CE2= VIL, or |
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1 |
uA |
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OE = VIH, VI/O = 0V to Vcc |
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VOL |
Output Low Voltage |
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Vcc = Max, IOL = 2mA |
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Vcc=3.0V |
-- |
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0.4 |
V |
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Vcc=5.0V |
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VOH |
Output High Voltage |
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Vcc = Min, IOH = -1mA |
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Vcc=3.0V |
2.4 |
-- |
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V |
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Vcc=5.0V |
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Operating Power Supply |
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= VIL, or CE2 = VIH, |
Vcc=3.0V |
-- |
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20 |
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ICC |
CE1 |
mA |
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Current |
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IDQ = 0mA, F = Fmax(3) |
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Vcc=5.0V |
-- |
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35 |
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ICCSB |
Standby Current-TTL |
CE1 = VIH, or CE2 = VIL, |
Vcc=3.0V |
-- |
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1 |
mA |
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IDQ = 0mA, F = Fmax(3) |
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Vcc=5.0V |
-- |
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2 |
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ICCSB1 |
Standby Current-CMOS |
CE1 |
Vcc-0.2V, CE2 |
0.2V, |
Vcc=3.0V |
-- |
0.1 |
0.7 |
uA |
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VIN |
Vcc-0.2V or VIN |
0.2V |
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Vcc=5.0V |
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0.6 |
6 |
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1.Typical characteristics are at TA = 25oC.
2.These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3.Fmax = 1/tRC .
DATA RETENTION CHARACTERISTICS ( TA = 0oC to + 70oC )
SYMBOL |
PARAMETER |
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TEST CONDITIONS |
MIN. |
TYP. (1) |
MAX. |
UNITS |
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VDR |
Vcc for Data Retention |
CE1 |
Vcc - 0.2V, CE2 |
0.2V, |
1.5 |
-- |
-- |
V |
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VIN |
Vcc - 0.2V or VIN |
0.2V |
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ICCDR |
Data Retention Current |
CE1 |
Vcc - 0.2V, CE2 |
0.2V, |
-- |
0.01 |
0.5 |
uA |
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VIN |
Vcc - 0.2V or VIN |
0.2V |
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tCDR |
Chip Deselect to Data |
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0 |
-- |
-- |
ns |
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Retention Time |
See Retention Waveform |
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tR |
Operation Recovery Time |
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TRC (2) |
-- |
-- |
ns |
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1.Vcc = 1.5V, TA = + 25OC
2.tRC = Read Cycle Time
LOW VCC DATA RETENTION WAVEFORM (1) ( CE1 Controlled )
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Data Retention Mode |
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Vcc |
Vcc |
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VDR ≥ 1.5V |
Vcc |
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t CDR |
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t R |
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≥ |
Vcc - 0.2V |
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VIH |
CE1 |
VIH |
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CE1 |
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LOW VCC DATA RETENTION WAVEFORM (2) ( CE2 Controlled ) |
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Data Retention Mode |
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Vcc |
Vcc |
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VDR |
1.5V |
Vcc |
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t CDR |
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t R |
CE2 |
VIL |
CE2 |
0.2V |
VIL |
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R0201-BS62LV2001 |
3 |
Revision 2.5 |
|
April 2002 |
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