BSI BS62LV8005BC, BS62LV4005TI, BS62LV8005EI, BS62LV8005EC, BS62LV8005BI Datasheet

BSI	Low Power/Voltage CMOS SRAM
	512K X 8 bit	BS62LV4005

FEATURES

•Vcc operation voltage : 4.5V ~ 5.5V

•Low power consumption

Vcc = 5.0V C-grade: 45mA (Max.) operating current I -grade: 50mA (Max.) operating current 1.5uA (Typ.) CMOS standby current

•High speed access time :

-70 70ns (Max.) at Vcc = 5.0V

-55 55ns (Max.) at Vcc = 5.0V

•Automatic power down when chip is deselected

•Three state outputs and TTL compatible

•Fully static operation

•Data retention supply voltage as low as 1.5V

•Easy expansion with CE and OE options

GENERAL DESCRIPTION

The BS62LV4005 is a high performance, low power CMOS Static Random Access Memory organized as 524,288 words by 8 bits and operates from a wide range of 4.5V to 5.5V supply voltage.

Advanced CMOS technology and circuit techniques provide both high speed and low power features with maximum access time of 55/ 70ns

in 5V operation.
Easy memory expansion	is provided by active	LOW chip
enable (CE), active LOW	output enable (OE) and	three-state

output drivers.

The BS62LV4005 has an automatic power down feature, reducing the power consumption significantly when chip is deselected.

The BS62LV4005 is available in the JEDEC standard 32 pin SOP , TSOP, TSOP II and STSOP .

PRODUCT FAMILY

				SPEED	POWER DISSIPATION
	PRODUCT	OPERATING	Vcc		STANDBY	Operating
				( ns )			PKG TYPE
					( ICCSB1 , Max )	( ICC, Max )
	FAMILY	TEMPERATURE	RANGE
				Vcc = 5.0V	Vcc = 5.0V	Vcc=5.0V
	BS62LV4005SC						SOP-32
	BS62LV4005EC						TSOP2-32
	BS62LV4005TC	+0O C to +70O C	4.5V ~ 5.5V	55 / 70	15uA	45mA	TSOP-32
	BS62LV4005STC						STSOP-32
	BS62LV4005PC						PDIP-32
	BS62LV4005SI						SOP-32
	BS62LV4005EI						TSOP2-32
	BS62LV4005TI	-40O C to +85O C	4.5V ~ 5.5V	55 / 70	25uA	50mA	TSOP-32
	BS62LV4005STI						STSOP-32
	BS62LV4005PI						PDIP-32

PIN CONFIGURATIONS

FUNCTIONAL BLOCK DIAGRAM

		A18		•					VCC
		A16		1		32
				2		31			A15
		A14		3		30			A17
		A12		4		29			WE
		A7		5		28			A13
		A6		6		27			A8
		A5		7		26			A9
		A4		8	BS62LV4005SC	25			A11
		A3		9	BS62LV4005SI	24			OE
		A2		10	BS62LV4005EC	23			A10
		A1			BS62LV4005EI
				11 BS62LV4005PC		22			CE
		A0
				12 BS62LV4005PI		21			DQ7
		DQ0		13		20			DQ6
		DQ1		14		19			DQ5
		DQ2		15		18			DQ4
	GND			16		17			DQ3
A11		1•					32					OE
A9		2					31					A10
A8		3					30					CE
A13		4					29					DQ7
WE		5					28					DQ6
A17		6			BS62LV4005TC		27					DQ5
A15		7					26					DQ4
VCC		8			BS62LV4005STC		25					DQ3
A18		9			BS62LV4005TI		24					GND
A16		10			BS62LV4005STI		23					DQ2
A14		11					22					DQ1
A12		12					21					DQ0
A7		13					20					A0
A6		14					19					A1
A5		15					18					A2
A4		16					17					A3

A13
A17
A15	Address
A18		22	Row		2048	Memory Array
A16	Input
A14
A12	Buffer		Decoder			2048 X 2048
A7
A6
A5
A4
						2048
DQ0	8		Data	8		Column I/O
DQ1			Input
DQ2			Buffer			Write Driver
DQ3					8	Sense Amp
DQ4	8		Data
DQ5						256
			Output
DQ6			Buffer
DQ7						Column Decoder
CE						16
	Control
WE						Address Input Buffer
OE
Vdd
Gnd						A11 A9 A8 A3 A2 A1 A0 A10

Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.

	R0201-BS62LV4005	1	Revision 2.4
			April 2002

BSI

BS62LV4005

PIN DESCRIPTIONS

Name

Function

A0-A18 Address Input

These 19 address inputs select one of the 524,288 x 8-bit words in the RAM

Chip Enable Input

CE

CE

is active LOW. Chip enable must be active when data read from or write to the

device. if chip enable is not active, the device is deselected and is in a standby power

mode. The DQ pins will be in the high impedance state when the device is deselected.

Write Enable Input

The write enable input is active LOW and controls read and write operations. With the

WE

chip selected, when

WE

is HIGH and

OE

is LOW, output data will be present on the

DQ pins; when

WE

is LOW, the data present on the DQ pins will be written into the

selected memory location.

Output Enable Input

The output enable input is active LOW. If the output enable is active while the chip is

OE

selected and the write enable is inactive, data will be present on the DQ pins and they

will be enabled. The DQ pins will be in the high impedance state when

is inactive.

OE

DQ0-DQ7 Data Input/Output

These 8 bi-directional ports are used to read data from or write data into the RAM.

Ports

Vcc

Power Supply

Gnd

Ground

TRUTH TABLE

MODE		WE		CE			OE			I/O OPERATION	Vcc CURRENT
Not selected		X			H			X		High Z	ICCSB, ICCSB1
Output Disabled		H			L			H		High Z	ICC
Read		H			L			L		DOUT	ICC
Write		L			L			X		DIN	ICC

ABSOLUTE MAXIMUM RATINGS(1)

SYMBOL	PARAMETER	RATING	UNITS
V TERM	Terminal Voltage with	-0.5 to 6.0	V
	Respect to GND
T BIAS	Temperature Under Bias	-40 to +125	O C
T STG	Storage Temperature	-60 to +150	O C
P T	Power Dissipation	1.0	W
I OUT	DC Output Current	20	mA

1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

OPERATING RANGE

	RANGE	AMBIENT	Vcc
		TEMPERATURE
	Commercial	0 O C to +70 O C	4.5~5.5V
	Industrial	-40 O C to +85 O C	4.5~5.5V

	CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
	SYMBOL	PARAMETER	CONDITIONS	MAX.	UNIT
	CIN	Input	VIN=0V	6	pF
		Capacitance
	CDQ	Input/Output	VI/O=0V	8	pF
		Capacitance

1. This parameter is guaranteed and not tested.

	R0201-BS62LV4005	2	Revision 2.4
			April 2002

BSI

BS62LV4005

DC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC )

PARAMETER

PARAMETER

TEST CONDITIONS

MIN.

TYP. (1)

MAX.

UNITS

NAME

VIL

Guaranteed

Input

Low

Vcc=5.0V

-0.5

--

0.8

V

Voltage(2)

VIH

Guaranteed

Input

High

Vcc=5.0V

2.2

--

Vcc+0.3

V

Voltage(2)

IIL

Input Leakage Current

Vcc = Max, VIN = 0V to Vcc

--

--

1

uA

IOL

Output Leakage Current

Vcc = Max, CE = VIH, or OE = VIH,

--

--

1

uA

VI/O = 0V to Vcc

VOL

Output Low Voltage

Vcc = Max, IOL = 2mA

Vcc=5.0V

--

--

0.4

V

VOH

Output High Voltage

Vcc = Min, IOH = -1mA

Vcc=5.0V

2.4

--

--

V

ICC

Operating Power Supply

IL

DQ

(3)

Vcc=5.0V

--

--

45

mA

Current

CE = V , I

= 0mA, F = Fmax

ICCSB

Standby Current-TTL

CE = VIH, IDQ = 0mA

Vcc=5.0V

--

--

2

mA

ICCSB1

Standby Current-CMOS

CE

Vcc-0.2V,

Vcc=5.0V

--

1.5

15

uA

VIN

Vcc - 0.2V or VIN

0.2V

1.Typical characteristics are at TA = 25oC.

2.These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.

3.Fmax = 1/tRC .

DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70oC )

	SYMBOL	PARAMETER		TEST CONDITIONS		MIN.	TYP. (1)	MAX.	UNITS
	VDR	Vcc for Data Retention	CE	Vcc - 0.2V		1.5	--	--	V
			VIN	Vcc - 0.2V or VIN	0.2V
	ICCDR	Data Retention Current	CE	Vcc - 0.2V		--	0.1	1.5	uA
			VIN	Vcc - 0.2V or VIN	0.2V
	tCDR	Chip Deselect to Data				0	--	--	ns
		Retention Time	See Retention Waveform
	tR	Operation Recovery Time				TRC (2)	--	--	ns

1.Vcc = 1.5V, TA = + 25OC

2.tRC = Read Cycle Time

LOW VCC DATA RETENTION WAVEFORM ( CE Controlled )

				Data Retention Mode
Vcc			Vcc			VDR ≥ 2.0V	Vcc
			t CDR				t R
						≥ Vcc - 0.2V
			VIH		CE		VIH
	CE

	R0201-BS62LV4005	3	Revision 2.4
			April 2002

BSI

BS62LV4005

AC TEST CONDITIONS

KEY TO SWITCHING WAVEFORMS

Input Pulse Levels

Vcc/0

Input Rise and Fall Times

5ns

WAVEFORM

INPUTS

OUTPUTS

Input and Output

0.5Vcc

MUST BE

MUST BE

Timing Reference Level

STEADY

STEADY

MAY CHANGE

WILL BE

AC TEST LOADS AND WAVEFORMS

FROM H TO L

CHANGE

FROM H TO L

5.0V

1928 Ω

5.0V

1928 Ω

MAY CHANGE

WILL BE

FROM L TO H

CHANGE

OUTPUT

OUTPUT

DON ,T CARE:

FROM L TO H

100PF

5PF

CHANGE :

INCLUDING

Ω

INCLUDING

Ω

ANY CHANGE

STATE

JIG AND

1020

JIG AND

1020

PERMITTED

UNKNOWN

SCOPE

SCOPE

DOES NOT

CENTER

FIGURE 1A

FIGURE 1B

APPLY

LINE IS HIGH

IMPEDANCE

THEVENIN EQUIVALENT

”OFF ”STATE

OUTPUT

667 Ω

1.73V

ALL INPUT PULSES

Vcc

10%

10%

90% 90%

GND

→

←

→

← 5ns

FIGURE 2

AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 5.0V ) READ CYCLE

	JEDEC	PARAMETER		BS62LV4005-55			BS62LV4005		-70
	PARAMETER		DESCRIPTION							UNIT
		NAME		MIN. TYP. MAX.			MIN. TYP. MAX.
	NAME
	tAVAX	t RC	Read Cycle Time	55	--	--	70	--	--	ns
	tAVQV	t AA	Address Access Time	--	--	55	--	--	70	ns
	tELQV	t ACS	Chip Select Access Time	--	--	55	--	--	70	ns
	tGLQV	t OE	Output Enable to Output Valid	--	--	30	--	--	35	ns
	tELQX	t CLZ	Chip Select to Output Low Z	10	--	--	10	--	--	ns
	tGLQX	t OLZ	Output Enable to Output in Low Z	10	--	--	10	--	--	ns
	tEHQZ	t CHZ	Chip Deselect to Output in High Z	0	--	30	0	--	35	ns
	tGHQZ	t OHZ	Output Disable to Output in High Z	0	--	25	0	--	30	ns
	tAXOX	t OH	Output Disable to Output Address Change	10	--	--	10	--	--	ns

	R0201-BS62LV4005	4	Revision 2.4
			April 2002