BSI BS62UV1024TI, BS62UV1024TC, BS62UV1024STI, BS62UV1024STC, BS62UV1024SI Datasheet

BSI	Ultra Low Power/Voltage CMOS SRAM
	128K X 8 bit	BS62UV1024

FEATURES

•Ultra low operation voltage : 1.8V ~ 3.6V

•Ultra low power consumption :

Vcc = 2.0V C-grade : 10mA (Max.) operating current I- grade : 15mA (Max.) operating current 0.01uA (Typ.) CMOS standby current

Vcc = 3.0V C-grade : 20mA (Max.) operating current I- grade : 25mA (Max.) operating current 0.02uA (Typ.) CMOS standby current

• High speed access time :

-15 150ns (Max.) at Vcc = 2.0V

•Automatic power down when chip is deselected

•Three state outputs and TTL compatible

•Fully static operation

•Data retention supply voltage as low as 1.5V

•Easy expansion with CE2, CE1, and OE options

DESCRIPTION

The BS62UV1024 is a high performance, ultra low power	CMOS
Static Random Access Memory organized as 131,072 words	by 8 bits

and operates from a wide range of 1.8V to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.01uA and maximum access time of 150ns in 2V operation.

Easy memory expansion is provided by an active LOW chip enable (CE1), an active HIGH chip enable (CE2), and active LOW output enable (OE) and three-state output drivers.

The BS62UV1024 has an automatic power down feature, reducing the power consumption significantly when chip is deselected.

The BS62UV1024 is available in the JEDEC standard 32 pin 450mil Plastic SOP, 8mmx13.4mm STSOP 300mil Plastic SOJ and 8mmx20mm TSOP.

PRODUCT FAMILY

			SPEED		POWER DISSIPATION
PRODUCT	OPERATING	Vcc		STANDBY		Operating
			(ns)					PKG TYPE
FAMILY	TEMPERATURE	RANGE		(ICCSB1, Max)		(ICC, Max)
			Vcc=
				Vcc=	Vcc=	Vcc=	Vcc=
BS62UV1024SC			2.0V	3.0V	2.0V	3.0V	2.0V	SOP-32
BS62UV1024TC								TSOP-32
BS62UV1024JC	+0 O C to +70 O C	1.8V ~ 3.6V	150	1.0uA	0.3uA	20mA	10mA	SOJ-32
BS62UV1024STC								STSOP -32
BS62UV1024PC								PDIP-32
BS62UV1024DC								DICE
BS62UV1024SI								SOP-32
BS62UV1024TI								TSOP-32
BS62UV1024JI	-40 O C to +85 O C	1.8V ~ 3.6V	150	1.5uA	1uA	25mA	15mA	SOJ-32
BS62UV1024STI								STSOP -32
BS62UV1024PI								PDIP32
BS62UV1024DI								DICE

PIN CONFIGURATIONS

BLOCK DIAGRAM

		NC		•					VCC
		A16		1		32
				2		31			A15
		A14		3		30			CE2
		A12		4		29			WE
		A7		5		28			A13
		A6		6	BS62UV1024SC 27				A8
		A5		7	BS62UV1024SI	26			A9
		A4		8	BS62UV1024PC	25			A11
		A3			BS62UV1024PI
		A2		9	BS62UV1024JC	24			OE
		A1		10	BS62UV1024JI	23			A10
				11		22			CE1
		A0		12		21			DQ7
		DQ0		13		20			DQ6
		DQ1		14		19			DQ5
		DQ2		15		18			DQ4
	GND			16		17			DQ3
A11		1•					32						OE
A9		2					31						A10
A8		3					30						CE1
A13		4					29						DQ7
WE		5					28						DQ6
CE2		6			BS62UV1024TC		27						DQ5
A15		7					26						DQ4
					BS62UV1024STC
VCC		8					25						DQ3
					BS62UV1024TI
NC		9					24						GND
					BS62UV1024STI
A16		10					23						DQ2
A14		11					22						DQ1
A12		12					21						DQ0
A7		13					20						A0
A6		14					19						A1
A5		15					18						A2
A4		16					17						A3

A6
A7
A12	Address					Memory Array
A14		20		1024
			Row
A16	Input
A15
			Decoder			1024 x 1024
A13	Buffer
A8
A9
A11
							1024
DQ0	8		Data	8		Column I/O
DQ1			Input
DQ2			Buffer			Write Driver
DQ3				8		Sense Amp
DQ4	8		Data
DQ5							128
			Output
DQ6			Buffer
DQ7					Column Decoder
CE2							14
CE1	Control				Address Input Buffer
WE
OE
Vdd
Gnd				A5	A4	A3 A2	A1	A0 A10

Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.

R0201-BS62UV1024	1	Revision 2.2
		April 2001

BSI

BS62UV1024

PIN DESCRIPTIONS

Name

Function

A0-A16 Address Input

These 17 address inputs select one of the 131,072 x 8-bit words in the RAM

CE1 Chip Enable 1 Input

CE1

is active LOW and CE2 is active HIGH. Both chip enables must be active when

CE2 Chip Enable 2 Input

data read from or write to the device. If either chip enable is not active, the device is

deselected and is in a standby power mode. The DQ pins will be in the high

impedance state when the device is deselected.

Write Enable Input

The write enable input is active LOW and controls read and write operations. With the

WE

chip selected, when

WE

is HIGH and

OE

is LOW, output data will be present on the

DQ pins; when

is LOW, the data present on the DQ pins will be written into the

WE

selected memory location.

Output Enable Input

The output enable input is active LOW. If the output enable is active while the chip is

OE

selected and the write enable is inactive, data will be present on the DQ pins and they

will be enabled. The DQ pins will be in the high impedance state when

is inactive.

OE

DQ0-DQ7 Data Input/Output

These 8 bi-directional ports are used to read data from or write data into the RAM.

Ports

Vcc

Power Supply

Gnd

Ground

TRUTH TABLE

MODE

CE2

OE

I/O OPERATION

Vcc CURRENT

WE

CE1

Not selected

X

H

X

X

High Z

ICCSB, ICCSB1

(Power Down)

X

X

L

X

Output Disabled

H

L

H

H

High Z

ICC

Read

H

L

H

L

DOUT

ICC

Write

L

L

H

X

DIN

ICC

ABSOLUTE MAXIMUM RATINGS(1)

SYMBOL	PARAMETER	RATING	UNITS
V TERM	Terminal Voltage with	-0.5 to	V
	Respect to GND	Vcc+0.5
T BIAS	Temperature Under Bias	-40 to +125	O C
T STG	Storage Temperature	-60 to +150	O C
P T	Power Dissipation	1.0	W
I OUT	DC Output Current	20	mA

1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

OPERATING RANGE

	RANGE	AMBIENT	Vcc
		TEMPERATURE
	Commercial	0 O C to +70 O C	1.8V ~ 3.6V
	Industrial	-40 O C to +85 O C	1.8V ~ 3.6V

	CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
	SYMBOL	PARAMETER	CONDITIONS	MAX.	UNIT
	CIN	Input	VIN=0V	6	pF
		Capacitance
	CDQ	Input/Output	VI/O=0V	8	pF
		Capacitance

1. This parameter is guaranteed and not tested.

R0201-BS62UV1024	2	Revision 2.2
		April 2001

BSI

BS62UV1024

DC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC )

PARAMETER

PARAMETER

TEST CONDITIONS

MIN.

TYP. (1)

MAX.

UNITS

NAME

VIL

Guaranteed

Input

Low

Vcc=2.0V

-0.5

--

0.6

V

Voltage(2)

Vcc=3.0V

0.8

VIH

Guaranteed

Input

High

Vcc=2.0V

1.4

--

Vcc+0.2

V

Voltage(2)

Vcc=3.0V

2.0

IIL

Input Leakage Current

Vcc = Max, VIN = 0V to Vcc

--

--

1

uA

Vcc = Max,

or

IOL

Output Leakage Current

CE1= VIH, CE2= VIL,

--

--

1

uA

OE = VIH, VI/O = 0V to Vcc

VOL

Output Low Voltage

Vcc = Max, IOL = 1mA

Vcc=2.0V

--

--

0.4

V

Vcc=3.0V

VOH

Output High Voltage

Vcc = Min, IOH = -0.5mA

Vcc=2.0V

1.6

--

--

V

Vcc=3.0V

2.4

Operating Power Supply

= VIL, or CE2 = VIH,

Vcc=2.0V

--

--

10

ICC

CE1

mA

Current

IDQ = 0mA, F = Fmax(3)

Vcc=3.0V

--

--

20

= VIH, or CE2 = VIL,

Vcc=2.0V

--

--

0.5

ICCSB

Standby Current-TTL

CE1

mA

IDQ = 0mA, F = Fmax(3)

Vcc=3.0V

--

--

1

Vcc-0.2V, CE2

0.2V,

--

0.01

0.3

ICCSB1

Standby Current-CMOS

CE1

Vcc=2.0V

uA

VIN

Vcc-0.2V or VIN

0.2V

Vcc=3.0V

--

0.02

1

1.Typical characteristics are at TA = 25oC.

2.These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.

3.Fmax = 1/tRC .

DATA RETENTION CHARACTERISTICS ( TA = 0oC to + 70oC )

SYMBOL

PARAMETER

TEST CONDITIONS

MIN.

TYP. (1)

MAX.

UNITS

VDR

Vcc for Data Retention

CE1

Vcc - 0.2V, CE2

0.2V,

1.5

--

--

V

VIN

Vcc - 0.2V or VIN

0.2V

Vcc - 0.2V, CE2

0.2V,

ICCDR

Data Retention Current

CE1

--

0.02

0.3

uA

VIN

Vcc - 0.2V or VIN

0.2V

tCDR

Chip Deselect to Data

0

--

--

ns

Retention Time

See Retention Waveform

tR

Operation Recovery Time

TRC (2)

--

--

ns

1.Vcc = 1.5V, TA = + 25OC

2.tRC = Read Cycle Time

LOW VCC DATA RETENTION WAVEFORM (1) ( CE1 Controlled )

				Data Retention Mode
Vcc			Vcc			VDR ≥ 1.5V		Vcc
			t CDR					t R
						≥	Vcc - 0.2V
			VIH		CE1			VIH
	CE1
LOW VCC DATA RETENTION WAVEFORM (2) ( CE2 Controlled )
				Data Retention Mode
Vcc			Vcc		VDR		1.5V	Vcc
			t CDR					t R
CE2			VIL	CE2			0.2V	VIL

R0201-BS62UV1024	3	Revision 2.2
		April 2001

BSI

BS62UV1024

AC TEST CONDITIONS

KEY TO SWITCHING WAVEFORMS

Input Pulse Levels

Vcc/0V

Input Rise and Fall Times

5ns

WAVEFORM

INPUTS

OUTPUTS

Input and Output

MUST BE

MUST BE

Timing Reference Level

0.5Vcc

STEADY

STEADY

MAY CHANGE

WILL BE

AC TEST LOADS AND WAVEFORMS

FROM H TO L

CHANGE

FROM H TO L

2V

1333 Ω

2V

1333 Ω

MAY CHANGE

WILL BE

FROM L TO H

CHANGE

OUTPUT

OUTPUT

DON ,T CARE:

FROM L TO H

100PF

5PF

CHANGE :

INCLUDING

2000

Ω

INCLUDING

2000

Ω

ANY CHANGE

STATE

JIG AND

JIG AND

PERMITTED

UNKNOWN

SCOPE

SCOPE

DOES NOT

CENTER

FIGURE 1A

FIGURE 1B

APPLY

LINE IS HIGH

THEVENIN EQUIVALENT

IMPEDANCE

”OFF ”STATE

OUTPUT

800 Ω

1.2V

ALL INPUT PULSES

Vcc

10%

10%

90% 90%

GND

→

←

→

← 5ns

AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC, Vcc=2.0V ) READ CYCLE

JEDEC	PARAMETER			BS62UV1024-15
PARAMETER		DESCRIPTION					UNIT
	NAME			MIN. TYP. MAX.
NAME
tAVAX	tRC	Read Cycle Time		150	--	--	ns
tAVQV	tAA	Address Access Time		--	--	150	ns
tE1LQV	tACS1	Chip Select Access Time	(CE1)	--	--	150	ns
tE2HOV	tACS2	Chip Select Access Time	(CE2)	--	--	150	ns
tGLQV	tOE	Output Enable to Output Valid		--	--	100	ns
tE1LQX	tCLZ1	Chip Select to Output Low Z	(CE1)	10	--	--	ns
tE2HOX	tCLZ2	Chip Select to Output Low Z	(CE2)	10	--	--	ns
tGLQX	tOLZ	Output Enable to Output in Low Z		10	--	--	ns
tE1HQZ	tCHZ1	Chip Deselect to Output in High Z	(CE1)	0	--	40	ns
tE2HQZ	t CHZ2	Chip Deselect to Output in High Z	(CE2)	0		40
tGHQZ	tOHZ	Output Disable to Output in High Z		0	--	35	ns
tAXOX	tOH	Output Disable to Output Address Change		10	--	--	ns

R0201-BS62UV1024	4	Revision 2.2
		April 2001