MT5C6408F-25L-IT
AUSTIN MT5C6408F-25L-IT, MT5C6408F-25L-XT, MT5C6408F-35L-883C, MT5C6408F-35L-IT, MT5C6408F-20L-XT Datasheet
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SRAM
MT5C6408
Austin Semiconductor, Inc.
MT5C6408
Rev. 3.0 2/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
FEATURES
• High Speed: 12, 15, 20, 25, 35, 45, 55, and 70ns
• Battery Backup: 2V data retention
• High-performance, low-power CMOS double-metal
process
• Single +5V (+10%) Power Supply
• Easy memory expansion with CE1\ and CE2
• All inputs and outputs are TTL compatible
OPTIONS MARKING
• Timing
12ns access -12
15ns access -15
20ns access -20
25ns access -2 5
35ns access -3 5
45ns access -4 5
55ns access -55*
70ns access -70*
• Package(s)
Ceramic DIP (300 mil) C No. 108
Ceramic LCC E C No. 204
Ceramic Flatpack F No. 302
• Operating T emperature Ranges
Industrial (-40oC to +85oC) IT
Military (-55oC to +125oC) XT
• 2V data retention/low power L
*Electrical characteristics identical to those provided for the
45ns access devices.
PIN ASSIGNMENT
(Top View)
AVAILABLE AS MILITARY
SPECIFICATIONS
• SMD 5962-38294
• MIL-STD-883
28-Pin DIP (C)
(300 MIL)
28-Pin Flat Pack (F)
28-Pin LCC (EC)
GENERAL DESCRIPTION
The MT5C6408, 8K x 8 SRAM, employs high-speed,
low-power CMOS technology, eliminating the need for clocks
or refreshing. These SRAM’s have equal access and cycle
times.
For flexibility in high-speed memory applications,
Austin Semiconductor offers dual chip enables (CE1\, CE2) and
output enable (OE\) capability. These enhancements can place
the outputs in High-Z for additional flexibility in system design.
Writing to these devices is accomplished when write
enable (WE\) and CE1\ inputs are both LOW and CE2 is HIGH.
Reading is accomplished when WE\ and CE2 remain HIGH and
CE1\ and OE\ go LOW. The device offers a reduced power
standby mode when disabled. This allows system designs to
achieve low standby power requirements.
These devices operate from a single +5V power supply and all inputs and outputs are fully TTL compatible.
8K x 8 SRAM
SRAM MEMORY ARRAY
For more products and information
please visit our web site at
www.austinsemiconductor .com
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
Vss
Vcc
WE\
CE2
A8
A9
A11
OE\
A10
CE1\
DQ8
DQ7
DQ6
DQ5
DQ4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
Vss
Vcc
WE\
CE2
A8
A9
A11
OE\
A10
CE1\
DQ8
DQ7
DQ6
DQ5
DQ4
4 3 2 1 28 27 26
12 13 14 15 16 17 18
5
6
7
8
9
10
11
25
24
23
22
21
20
19
A5
A4
A3
A2
A1
A0
DQ0
A8
A9
A11
OE\
A10
CE1\
DQ7
DQ6
DQ5
DQ4
DQ3
Vss
DQ2
DQ1
A6A7A12NCVcc
WE\
CE2\
SRAM
MT5C6408
Austin Semiconductor, Inc.
MT5C6408
Rev. 3.0 2/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
FUNCTIONAL BLOCK DIA GRAM
TRUTH TABLE
ROW DECODER
65,536-BIT
MEMORY ARRAY
I/O CONTROL
V
CC
Vss
DQ8
DQ1
CE1\
OE\
WE\
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
COLUMN DECODER
A8 A9 A
10 A11
A
12
POWER
DOWN
CE2
MODE CE1\ CE2 WE\ OE\ DQ POWER
STANDBY H X X X HIGH-Z STANDBY
STANDBY X L X X HIGH-Z STANDBY
READ L H H L Q ACTIVE
READ L H H H HIGH-Z ACTIVE
WRITE L H L X D ACTIVE
SRAM
MT5C6408
Austin Semiconductor, Inc.
MT5C6408
Rev. 3.0 2/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
ABSOLUTE MAXIMUM RATINGS*
V oltage on any Input or DQ Relative to Vss........-0.5V to +7.0V
V oltage on Vcc Supply Relative to Vss.................-0.5V to +7.0V
Storage Temperature….........................................-65oC to +150oC
Power Dissipation......................................................................1W
Max Junction T emperature..................................................+175°C
Lead T emperature (soldering 10 seconds)........................+260oC
Short Circuit Output Current................................................50mA
*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operation section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect reliability .
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55oC < TC < 125oC; VCC = 5V +10%)
CAPACITANCE
DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES
Input High (Logic 1) Voltage
V
IH
2.2 Vcc+0.5 V 1
Input Low (Logic 0) Voltage
V
IL
-0.5 0.8 V 1, 2
Input Leakage Current
0V ≤ V
IN
≤ Vcc IL
I
-10 10
µA
Output Leakage Current
Output(s) disabled
0V <
V
OUT
< Vcc
IL
O
-10 10
µA
Output High Voltage
I
OH
= -4.0mA V
OH
2.4 V 1
Output Low Voltage
I
OL
= 8.0mA V
OL
0.4 V 1
SYM -12 -15 -20 -25 -35 -45 UNITS NOTES
I
cc
180 170 160 155 155 145 mA 3
I
SBTSP
40 40 40 40 40 40 mA
I
SBTLP
30 30 30 30 30 30 mA
I
SBCSP
20 20 20 20 20 20 mA
I
SBCLP
10 10 10 10 10 10 mA
Power Supply
Current: Standby
MAX
CE\ >
VIH; All Other Inputs
<
VIL or > VIH, VCC = MAX
f = 0 Hz
CE\ >
(V
CC
-0.2); VCC = MAX
All Other Inputs <
0.2V
or >
(VCC - 0.2V), f = 0 Hz
CONDITIONS
CE\ <
VIL; VCC = MAX
f = MAX = 1/t
RC
(MIN)
Output Open
Power Supply
Current: Operating
PARAMETER
DESCRIPTION CONDITIONS SYM MAX
UNITS
NOTES
Input Capacitance
C
I
6pF 4
Output Capacitance
C
O
7pF 4
T
A
= 25oC, f = 1MHz
Vcc = 5V
SRAM
MT5C6408
Austin Semiconductor, Inc.
MT5C6408
Rev. 3.0 2/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 5) (-55oC < TC < 125oC; VCC = 5V +10%)
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES
READ CYCLE
READ cycle time
t
RC
12 15 20 25 35 45 ns
Address access time
t
AA
12 15 20 25 35 45 ns
Chip Enable access time
t
ACE
12 15 20 25 35 45 ns
Output hold from address change
t
OH
200033 ns
Chip Enable to output in Low-Z
t
LZCE
200000 ns7
Chip disable to output in High-Z
t
HZCE
7 1015151525ns6, 7
Output Enable access time
t
AOE
8 1215151520ns
Output Enable to output in Low-Z
t
LZOE
000000 ns
Output disable to output in High-Z
t
HZOE
7 1015153040ns6
WRITE CYCLE
WRITE cycle time
t
WC
12 15 20 25 35 45 ns
Chip Enable to end of write
t
CW
10 13 15 20 30 40 ns
Address valid to end of write
t
AW
10 13 15 20 30 40 ns
Address setup time
t
AS
000000 ns
Address hold from end of write
t
AH
000000 ns
WRITE pulse width
t
WP
10 13 15 20 30 40 ns
Data setup time
t
DS
7 1012151520 ns
Data hold time
t
DH
000055 ns
Write disable to output in Low-Z
t
LZWE
200000 ns7
Write Enable to output in High-Z
t
HZWE
0 7 0 10 0 10 0 15 0 15 0 25 ns 6, 7
DESCRIPTION
-12
SYMBOL
-45-35-25-20-15
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