AUSTIN MT5C1001F-70L-XT, MT5C1001F-70L-883C, MT5C1001F-55L-IT, MT5C1001F-55L-XT, MT5C1001F-35L-883C Datasheet

SRAM

MT5C1001

Austin Semiconductor, Inc.

Limited Availability

1M x 1 SRAM

PIN ASSIGNMENT

SRAM MEMORY ARRAY

(Top View)

AVAILABLE AS MILITARY

28-Pin DIP (C)

32-Pin LCC (EC)

SPECIFICATIONS

32-Pin SOJ (DCJ)

(400 MIL)

• SMD 5962-92316

A10

1

32

Vcc

• MIL-STD-883

A10

1

28

Vcc

A11

2

31

NC

A11

2

27

A9

A12

3

30

A9

FEATURES

A12

3

26

A8

NC

4

29

A8

A13

4

25

A7

A13

5

28

A7

A14

5

24

A6

A14

6

27

A6

•

High Speed: 20, 25, 35, and 45

A15

6

23

A5

A15

7

26

A5

NC

7

22

A4

NC

8

25

A4

• Battery Backup: 2V data retention

A16

8

21

NC

A16

9

24

A3

A17

10

•

Low power standby

A17

9

20

A3

23

NC

A18

10

19

A2

A18

11

22

A2

• Single +5V (+10%) Power Supply

A19

11

18

A1

A19

12

21

NC

Q

12

17

A0

NC

13

20

A1

• Easy memory expansion with CE\ and OE\ options.

WE\

13

16

D

Q

14

19

A0

•

All inputs and outputs are TTL compatible

Vss

14

15

CE\

WE\

15

18

D

Vss

16

17

CE\

•

Three-state output

32-Pin Flat Pack (F)

OPTIONS

MARKING

A10

1

3 2

Vcc

•

Timing

A11

2

3 1

NC

20ns access

-20

A12

3

3 0

A9

NC

4

2 9

A8

25ns access

-25

A13

5

2 8

A7

A14

6

2 7

A6

35ns access

-35

A15

7

2 6

A5

45ns access

-45

NC

8

2 5

A4

A16

9

2 4

A3

55ns access

-55*

A17

1 0

2 3

NC

A18

1 1

2 2

A2

70ns access

-70*

A19

1 2

2 1

NC

NC

1 3

2 0

A1

Q

1 4

1 9

A0

•

Package(s)

WE\

1 5

1 8

D

Vss

1 6

1 7

CE\

Ceramic DIP (400 mil)

C

No. 109

Ceramic LCC

EC

No. 207

Ceramic Flatpack

F

No. 303

GENERAL DESCRIPTION

Ceramic SOJ

DCJ

No. 501

The MT5C1001 employs low power, high-performance

•

Operating Temperature Ranges

silicon-gate CMOS technology. Static design eliminates the

need for external clocks or timing strobes while CMOS circuitry

Industrial (-40oC to +85oC)

IT

Military (-55oC to +125oC)

XT

reduces power consumption and provides for greater

reliability.

• 2V data retention/low power

L

For flexibility in high-speed memory applications, ASI

offers chip enable (CE\) and output enable (OE\) capability.

These enhancements can place the outputs in High-Z for addi-

*Electrical characteristics identical to those provided for the

tional flexibility in system design. Writing to these devices is

45ns access devices.

accomplished when write enable (WE|) and CE\ inputs are both

LOW. Reading is accomplished when WE\ remains HIGH while

CE\ and OE\ go LOW. The devices offer a reduced power

For more products and information

standby mode when disabled. This allows system designs to

achieve low standby power requirements.

please visit our web site at

The “L” version provides an approximate 50 percent

www.austinsemiconductor.com

reduction in CMOS standby current (ISBC2) over the standard

version.

All devices operation from a single +5V power supply and all inputs and outputs are fully TTL compatible.

MT5C1001	Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Rev. 2.0 2/00	1

SRAM

Austin Semiconductor, Inc.

MT5C1001

Limited Availability

FUNCTIONAL BLOCK DIAGRAM

VCC Vss

A6

A5

A4

DECODERROW

1,048,576-BIT

CONTROLI/O

A3

MEMORY ARRAY

A15

512 rows x 2048

A14

columns

A13

A8

POWER

A7

DOWN

COLUMN DECODER

A2 A1 A16 A0 A17 A18 A19 A10 A9 A12 A11

D

Q

CE\

WE\

TRUTHTABLE

MODE	CE\	WE\	OUTPUT	POWER
STANDBY	H	X	HIGH-Z	STANDBY
READ	L	H	Q	ACTIVE
WRITE	L	L	HIGH-Z	ACTIVE

PIN ASSIGNMENTS

PIN	ASSIGNMENT
A0-A19	Address Inputs
WE\	Write Enable
CE\	Chip Enable
D	Data Input
Q	Data Output
NC	No Connection
VCC	+5V Power Supply
VSS	Ground

MT5C1001	Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Rev. 2.0 2/00	2

SRAM

Austin Semiconductor, Inc.

MT5C1001

Limited Availability

ABSOLUTE MAXIMUM RATINGS*

Voltage on Any Input Relative to Vss................................	-.5V to +7V
Voltage on Vcc Supply Relative to Vss...............................	-.5V to +7V
Voltage Applied to Q............................................................	-.5V to +6V
Storage Temperature......................................................	-65oC to +150oC
Power Dissipation..............................................................................	1W
Short Circuit Output Current.........................................................	20mA
Lead Temperature (soldering 10 seconds)....................................	+260oC
Junction Temperature..................................................................	+175oC

*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS

(-55oC < T	C	< 125oC; V	= 5V +10%)
		CC
DESCRIPTION				CONDITIONS	SYMBOL	MIN	MAX	UNITS	NOTES
Input High (Logic 1) Voltage					VIH	2.2	VCC+0.5	V	1
Input Low (Logic 0) Voltage					VIL	-0.5	0.8	V	1, 2
Input Leakage Current				0V ≤ VIN ≤ VCC	ILI	-5	5	μA
Output Leakage Current				Output(s) disabled	ILO			μA
				0V < VOUT < VCC		-5	5
Output High Voltage				IOH = -4.0mA	VOH	2.4		V	1
Output Low Voltage				IOL = 8.0mA	VOL		0.4	V	1

						MAX
PARAMETER		CONDITIONS	SYM		-20	-25	-35	-45	UNITS	NOTES
Power Supply	CE\ < VIL; VCC = MAX
	f = MAX = 1/tRC (MIN)			Icc	125	120	115	110	mA	3
Current: Operating
		Output Open
Power Supply	CE\ > VIH; VCC = MAX
	f = MAX = 1/tRC (MIN)		I	SBT1	50	45	40	35	mA
Current: Standby
		Output Open
	CE\ > VIH; All Other Inputs
	< VIH or > VIH, VCC = MAX		ISBT2		25	25	25	25	mA
		f = 0 Hz
	CE\ > VCC -0.2V; VCC = MAX
		VIL < VSS +0.2V	ISBC2		10	10	10	10	mA
	VIH > VCC -0.2V; f = 0 Hz
		"L" Version Only	ISBC2		5	5	5	5	mA

CAPACITANCE

	PARAMETER	CONDITIONS	SYMBOL	MAXIMUM	UNITS	NOTES
	Input Capacitance (A3-A5, A15 -A17)		CI	10	pF	4
		TA = 25oC, f = 1MHz
	Output Capactiance (Q)		Co	8	pF	4
		VCC = 5V
	Input Capacitance: (All Other Inputs)		C I	8	pF	4

MT5C1001	Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Rev. 2.0 2/00	3

SRAM

Austin Semiconductor, Inc.

MT5C1001

Limited Availability

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

(Note 5) (-55oC < T	< 125oC; V	= 5V +10%)
C	CC
DESCRIPTION				-20		-25		-35		-45
			SYMBOL	MIN	MAX	MIN	MAX	MIN	MAX	MIN	MAX	UNITS	NOTES
READ CYCLE
READ cycle time			tRC	20		25		35		45		ns
Address access time			tAA		20		25		35		45	ns
Chip Enable access time			tACE		20		25		35		45	ns
Output hold from address change			tOH	3		3		3		3		ns
Chip Enable to output in Low-Z			tLZCE	3		3		3		3		ns	4, 6, 7
Chip disable to output in High-Z			tHZCE		8		10		15		15	ns	4, 6, 7
Chip Enable to power-up time			tPU	0		0		0		0		ns	4
Chip disable to power-down time			tPD		20		25		35		45	ns	4
WRITE CYCLE
WRITE cycle time			tWC	20		25		35		45		ns
Chip Enable to end of write			tCW	15		16		20		25		ns
Address valid to end of write			tAW	15		16		20		25		ns
Address setup time			tAS	0		0		0		0		ns
Address hold from end of write			tAH	1		1		1		1		ns
WRITE pulse width			tWP	15		16		20		25		ns
Data setup time			tDS	8		10		13		15		ns
Data hold time			tDH	0		0		0		0		ns
Write disable to output in Low-Z			tLZWE	3		3		3		3		ns	7
Write Enable to output in High-Z			tHZWE	0	9	0	10	0	13	0	13	ns	4, 6, 7

MT5C1001	Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Rev. 2.0 2/00	4