AUSTIN MT5C1005F-20L-883C, MT5C1005ECW-70L-XT, MT5C1005ECW-40L-IT, MT5C1005ECW-40L-XT, MT5C1005ECW-55L-883C Datasheet

												SRAM
		Austin Semiconductor, Inc.								MT5C1005
	256K x 4 SRAM
						PIN ASSIGNMENT
	SRAM MEMORY ARRAY								(Top View)
	AVAILABLE AS MILITARY		28-Pin DIP (C)						32-Pin LCC (EC)
	SPECIFICATIONS								32-Pin SOJ (DCJ)
			(400 MIL)
	•MIL-STD-883								A7	1		32			Vcc
			A7		1	28		Vcc	A8	2		31			A6
			A8		2	27		A6	A9		3	30			A5
	FEATURES		A9		3	26		A5	A12	4		29			A2
			A10		4	25		A4	A10	5		28			A4
			A11		5	24		A3	A11	6		27			A3
	• High Speed: 20, 25, 35, and 45		A12		6	23		A2	A13		7	26			A1
			A13		7	22		A1	NC	8		25			NC
	• Battery Backup: 2V data retention
			A14		8	21		A0	A14	9		24			NC
									A15	10
	• Low power standby		A15		9	20		NC				23			A0
			A16		10	19		DQ4	A16		11	22			NC
	• High-performance, low-power CMOS double-metal		A17		11	18		DQ3	A17		12	21			DQ4
			CE\		12	17		DQ2	NC	13		20			DQ3
	process		OE\		13	16		DQ1	CE\	14		19			DQ2
	• Single +5V (+10%) Power Supply		Vss		14	15		WE\	OE\		15	18			DQ1
									Vss		16	17			WE\
	• Easy memory expansion with CE\ and OE\ options.		32-Pin Flat Pack (F)
	• All inputs and outputs are TTL compatible

32-Pin LCC (ECW)

			A 7	1	3 2	Vcc			A9 A8 A7 NC Vcc A6	A5
			A 8	2	3 1	A 6
OPTIONS		MARKING	A 9	3	3 0	A 5			4 3 2 1 31 32 30
			A 1 2	4	2 9	A 2
•	Timing		A 1 0	5	2 8	A 4	A 1 0 5			2 9 A 2
				6
			A 1 1		2 7	A 3	A 1 1	6		2 8	A 4
	20ns access	-20	A 1 3	7	2 6	A 1	A 1 2 7			2 7 A 3
			N C	8	2 5	N C	A 1 3	8		2 6	A 1
	25ns access	-25	A 1 4	9	2 4	N C	A 1 4	9		2 5	A 0
							A 1 5 1 0			2 4	N C
	35ns access	-35	A 1 5	1 0	2 3	A 0	A 1 6 1 1			2 3 N C
			A 1 6	1 1	2 2	N C	A 1 7 1 2			2 2	N C
	45ns access	-45	A 1 7	1 2	2 1	DQ4	CE\ 1 3			2 1	DQ4
			N C	1 3	2 0	DQ3			14 15 16 17 18 19 20
	55ns access	-55*	CE\	1 4	1 9	DQ2
	70ns access	-70*	Vss	1 5	1 7	WE\			DQ2 DQ1 WE\ Vss OE\ NC	DQ3
			OE\		1 8	DQ1
				1 6

• Package(s)
Ceramic DIP (400 mil)	C	No. 109
Ceramic Quad LCC (contact factory) ECW		No. 206
Ceramic LCC	EC	No. 207
Ceramic Flatpack	F	No. 303
Ceramic SOJ	DCJ	No. 501

•	Operating Temperature Ranges
	Industrial (-40oC to +85oC)	IT
	Military (-55oC to +125oC)	XT
•	2V data retention/low power	L

*Electrical characteristics identical to those provided for the 45ns access devices.

GENERAL DESCRIPTION

The Austin Semiconductor SRAM family employs high-speed, low power CMOS designs fabricated using doublelayer metal, double-layer polysilicon technology.

For flexibility in high-speed memory applications, ASI offers chip enable (CE\) and output enable (OE\) capability. These enhancements can place the outputs in High-Z for additional flexibility in system design. Writing to these devices is accomplished when write enable (WE\) and CE\ inputs are both LOW. Reading is accomplished when WE\ remains HIGH while CE\ and OE\ go LOW. The devices offer a reduced power standby mode when disabled. This allows system designs to achieve low standby power requirements.

All devices operation from a single +5V power supply and all inputs and outputs are fully TTL compatible.

For more products and information please visit our web site at www.austinsemiconductor.com

MT5C1005	Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Rev. 3.1 1/01	1

SRAM

MT5C1005

Austin Semiconductor, Inc.

FUNCTIONAL BLOCK DIAGRAM

A A A A A A

A

A

A

A

VCC GND

DECODERROW	CONTROLI/O
	DQ4
	262,144 x 4-BIT
	MEMORY ARRAY
	DQ1

CE\

COLUMN DECODER

OE\

WE\

A A A A A A A A	POWER
	DOWN

TRUTHTABLE

MODE	OE\	CE\	WE\	DQ	POWER
STANDBY	X	H	X	HIGH-Z	STANDBY
READ	L	L	H	Q	ACTIVE
READ	H	L	H	HIGH-Z	ACTIVE
WRITE	X	L	L	D	ACTIVE

MT5C1005	Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Rev. 3.1 1/01	2

SRAM

MT5C1005

Austin Semiconductor, Inc.

ABSOLUTEMAXIMUMRATINGS*
Supply Voltage Range (Vcc)................................	-.5V to +7.0V
Storage Temperature......................................	-65°C to +150°C
Voltage on any Pin Relative to Vss................	-.5V to Vcc+.5V
Max Junction Temperature............................................	+175°C
Lead Temperature (soldering 10 seconds)..................	+260oC
Power Dissipation ...............................................................	1 W

*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS

(-55oC < T	C	< 125oC; V	= 5V +10%)
			CC
DESCRIPTION				CONDITIONS	SYM	MIN	MAX	UNITS	NOTES
Input High (Logic 1) Voltage					VIH	2.2	VCC+0.5	V	1
Input Low (Logic 0) Voltage					VIL	-0.5	0.8	V	1
Input Leakage Current				0V<VIN<VCC	ILI	-10	10	µA
Output Leakage Current				Output(s) disabled	ILO	-10	10	µA
				0V<VOUT<VCC
Output High Voltage				IOH = -4.0mA	VOH	2.4		V	1
Output Low Voltage				IOL = 8.0mA	VOL		0.4	V	1

MAX

PARAMETER

CONDITIONS

SYM

-20

-25

-35

-45

UNITS

NOTES

Power Supply

WE\, CE\ < VIL; VCC = MAX

Icc

180

180

180

180

mA

3

Current: Operating

Output Open

Power Supply

CE\ > VIH; All Other Inputs

ISBT2

25

25

25

25

mA

Current: Standby

< VIL or > VIH, VCC = MAX

CE\ > VCC -0.2V; VCC = MAX

VIL < VSS +0.2V

ISBC

16

16

16

16

mA

VIH > VCC -0.2V; f = 0 Hz*

* “L” version only.

CAPACITANCE

PARAMETER

CONDITIONS

SYM

MAX

UNITS

NOTES

Input Capacitance

VIN = 0V,

CI

12

pF

4

TA = 25°C, f = 1MHz

Output Capacitance (DQ1-DQ4)

CO

14

pF

4

V

CC

= 5V

MT5C1005	Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Rev. 3.1 1/01	3

SRAM

MT5C1005

Austin Semiconductor, Inc.

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

(Note 5) (-55oC < T < 125oC; V	= 5V +10%)
C	CC
DESCRIPTION			-20		-25		-35		-45
		SYMBOL	MIN	MAX	MIN	MAX	MIN	MAX	MIN	MAX	UNITS	NOTES
READ CYCLE
READ cycle time		tRC	20		25		35		45		ns
Address access time		tAA		20		25		35		45	ns
Chip Enable access time		tACE		20		25		35		45	ns
Output hold from address change		tOH	3		3		3		3		ns
Chip Enable to output in Low-Z		tLZCE	3		3		3		3		ns	4, 6, 7
Chip disable to output in High-Z		tHZCE		10		12		20		25	ns	4, 6, 7
Chip Enable to power-up time		tPU	0		0		0		0		ns	4
Chip disable to power-down time		tPD		20		25		35		45	ns	4
Output Enable access time		tAOE		8		10		20		25	ns
Output Enable to output in Low-Z		tLZOE	0		0		0		0		ns	4, 6, 7
Output disable to output in High-Z		tHZOE		8		10		20		25	ns	4, 6, 7
WRITE CYCLE
WRITE cycle time		tWC	20		25		35		45		ns
Chip Enable to end of write		tCW	15		20		30		35		ns
Address valid to end of write		tAW	15		20		30		35		ns
Address setup time		tAS	0		0		0		0		ns
Address hold from end of write		tAH	0		0		0		0		ns
WRITE pulse width		tWP	15		20		30		35		ns
Data setup time		tDS	12		15		20		25		ns
Data hold time		tDH	0		0		0		0		ns
Write disable to output in Low-Z		tLZWE	3		3		3		3		ns	4, 6, 7
Write Enable to output in High-Z		tHZWE	0	8	0	10	0	15	0	20	ns	4, 6, 7

MT5C1005	Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Rev. 3.1 1/01	4