AUSTIN MT5C2564EC-70L-IT, MT5C2564EC-70L-XT, MT5C2564EC-55L-883C, MT5C2564EC-55L-IT, MT5C2564EC-55L-XT Datasheet

SRAM

MT5C2564

Austin Semiconductor, Inc.

64K x 4 SRAM

SRAM MEMORY ARRAY

PIN ASSIGNMENT

AVAILABLE AS MILITARY					(Top View)
SPECIFICATIONS
• SMD 5962-88681
• MIL-STD-883		24-Pin DIP (C)				28-Pin LCC (EC)
FEATURES		(300 MIL)					A1	A0	NC Vcc	NC
							3	2	1 28 27
• High Speed: 15, 20, 25, 35, 45, 55, and 70		A0	1	24	Vcc
• Battery Backup: 2V data retention		A1	2	23	A15	A 2	4			2 6	A 1 5
		A2	3	22	A14	A 3	5			2 5	A 1 4
• Low power standby		A3	4	21	A13	A 4	6			2 4	A 1 3
						A 5	7			2 3	A 1 2
		A4	5	20	A12
• High-performance, low-power, CMOS double-metal						A 6	8			2 2	A 1 1
		A5	6	19	A11	A 7	9			2 1	A 1 0
process		A6	7	18	A10	A 8 1 0				2 0	DQ4
		A7	8	17	DQ4	A 9 1 1				1 9	DQ3
• Single +5V (+10%) Power Supply		A8	9	16	DQ3	CE\ 1 2				1 8	DQ2
		A9	10	15
					DQ2
• Easy memory expansion with CE\		CE\	11	14			13 14 15 16 17
					DQ1
• All inputs and outputs are TTL compatible		Vss	12	13	WE\		NC	Vss	WE\ NC	DQ1
OPTIONS	MARKING

•	Timing
	15ns access	-15
	20ns access	-20
	25ns access	-25		GENERAL DESCRIPTION
	35ns access	-35
	45ns access	-45		The Austin Semiconductor SRAM family employs
	55ns access	-55*		high-speed, low-power CMOS and are fabricated using double-
	70ns access	-70*		layer metal, double-layer polysilicon technology.
•	Package(s)			For flexibility in high-speed memory applications,
				Austin Semiconductor offers chip enable (CE\) on all organiza-
	Ceramic DIP (300 mil)	C	No. 106	tions. This enhancement can place the outputs in High-Z for
	Ceramic LCC	EC	No. 204	additional flexibility in system design. The x4 configuration
•	Operating Temperature Ranges			features common data input and output.
				Writing to these devices is accomplished when write
	Industrial (-40oC to +85oC)	IT		enable (WE\) and CE\ inputs are both LOW. Reading is accom-
	Military (-55oC to +125oC)	XT		plished when WE\ remains HIGH and CE\ goes LOW. The
• 2V data retention/low power		L		device offers a reduced power standby mode when disabled.
				This allows system designs to achieve low standby power re-
	*Electrical characteristics identical to those provided for the 45ns			quirements.
				These devices operate from a single +5V power sup-
	access devices.			ply and all inputs and outputs are fully TTL compatible.

For more products and information please visit our web site at www.austinsemiconductor.com

MT5C2564	Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Rev. 2.0 11/00	1

A0

A1

A2

A3

A4

A5

A13

A14

A15

SRAM

MT5C2564

Austin Semiconductor, Inc.

FUNCTIONAL BLOCK DIAGRAM

VCC GND

DECODERROW							DQ4
			262,144-BIT				CONTROLI/O
		MEMORY ARRAY
							DQ1
							CE\
		COLUMN DECODER
							WE\
A6	A7	A8	A9	A10	A11	A12	POWER
							DOWN

TRUTH TABLE

MODE	CE\	WE\	DQ	POWER
STANDBY	H	X	HIGH-Z	STANDBY
READ	L	H	Q	ACTIVE
WRITE	L	L	D	ACTIVE

MT5C2564	Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Rev. 2.0 11/00	2

SRAM

MT5C2564

Austin Semiconductor, Inc.

ABSOLUTE MAXIMUM RATINGS*

Voltage on Any Pin Relative to Vss..................................	-0.5V to +7V
Voltage on Vcc Supply Relative to Vss.............................	-0.5V to +7V
Storage Temperature......................................................	-65oC to +150oC
Power Dissipation..............................................................................	1W
Short Circuit Output Current.........................................................	50mA
Lead Temperature (soldering 10 seconds)....................................	+260oC
Junction Temperature..................................................................	+175oC

*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS

(-55oC < T

C

< 125oC; V

= 5V +10%)

CC

DESCRIPTION

CONDITIONS

SYM

MIN

MAX

UNITS

NOTES

Input High (Logic 1) Voltage

VIH

2.2

VCC+0.5

V

1

Input Low (Logic 0) Voltage

VIL

-0.5

0.8

V

1, 2

Input Leakage Current

0V<VIN<VCC

ILI

-10

10

µA

Output Leakage Current

Output(s) disabled

ILO

-10

10

µA

0V<VOUT<VCC

Output High Voltage

IOH=-4.0mA

VOH

2.4

V

1

Output Low Voltage

IOL=8.0mA

VOL

0.4

V

1

MAX

PARAMETER

CONDITIONS

SYM

-15

-20

-25

-35

-45

UNITS

NOTES

Power Supply

CE\ < VIL; VCC = MAX

f = MAX = 1/tRC (MIN)

Icc

165

150

140

120

120

mA

3

Current: Operating

Output Open

Power Supply

CE\ > VIH; All Other Inputs

< VIL or > VIH, VCC = MAX

ISBT2

45

45

40

25

25

mA

Current: Standby

f = 0 Hz

CE\ > VCC -0.2V; VCC = MAX

VIL < VSS +0.2V

ISBC2

20

20

20

20

20

mA

VIH > VCC -0.2V; f = 0 Hz

"L" Version Only

ISBC2

4

4

4

4

4

mA

CAPACITANCE

DESCRIPTION	CONDITIONS	SYM	MAX	UNITS	NOTES
Input Capacitance	TA = 25oC, f = 1MHz	CI	10	pF	4
Output Capacitance	VCC = 5V	C	12	pF	4
		O

MT5C2564	Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Rev. 2.0 11/00	3

SRAM

MT5C2564

Austin Semiconductor, Inc.

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

(Note 5) (-55oC < T < 125oC; V	CC	= 5V +10%)
C
DESCRIPTION				-15		-20		-25		-35		-45
			SYMBOL	MIN	MAX	MIN	MAX	MIN	MAX	MIN	MAX	MIN	MAX	UNITS	NOTES
READ CYCLE
READ cycle time			tRC	15		20		25		35		45		ns
Address access time			tAA		15		20		25		35		45	ns
Chip Enable access time			tACE		15		20		25		35		45	ns
Output hold from address change			tOH	3		3		3		3		3		ns
Chip Enable to output in Low-Z			tLZCE	3		3		3		3		3		ns	7
Chip disable to output in High-Z			tHZCE		8		10		10		20		20	ns	6, 7
Chip Enable to power-up time			tPU	0		0		0		0		0		ns	4
Chip disable to power-down time			tPD		15		20		25		35		45	ns	4
WRITE CYCLE
WRITE cycle time			tWC	15		20		25		35		45		ns
Chip Enable to end of write			tCW	12		15		18		30		40		ns
Address valid to end of write			tAW	12		15		18		30		40		ns
Address setup time			tAS	0		0		0		0		0		ns
Address hold from end of write			tAH	2		2		2		5		5		ns
WRITE pulse width			tWP	12		15		17		30		40		ns
Data setup time			tDS	7		10		12		20		20		ns
Data hold time			tDH	0		0		0		0		0		ns
Write disable to output in Low-Z			tLZWE	0		0		0		0		0		ns	7
Write Enable to output in High-Z			tHZWE	0	7	0	10	0	11	0	20	0	20	ns	6, 7

MT5C2564	Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Rev. 2.0 11/00	4