AUSTIN MT5C1008JOP-55L-883C, MT5C1008JOP-55L-IT, MT5C1008JOP-35L-IT, MT5C1008JOP-35L-XT, MT5C1008JOP-45L-883C Datasheet

SRAM

MT5C1008

Austin Semiconductor, Inc.

128K x 8 SRAM	PIN ASSIGNMENT
WITH DUAL CHIP ENABLE	(Top View)

AVAILABLE AS MILITARY

32-Pin DIP (C, CW)

32-Pin LCC (EC)

SPECIFICATIONS

32-Pin CSOJ (SOJ)

32-Pin SOJ (DCJ)

NC

1

32

VCC

•SMD 5962-89598

NC

1

32

VCC

A16

2

31

A15

A16

2

31

A15

•MIL-STD-883

A14

3

30

CE2

A12

4

29

WE\

A12

4

29

WE\

A14

3

30

CE2

A7

5

28

A13

A7

5

28

A13

FEATURES

A6

6

27

A8

A6

6

27

A8

A5

7

26

A9

A5

7

26

A9

• High Speed: 12, 15, 20, 25, 30, 35, 45, 55 and 70 ns

A4

8

25

A11

A4

8

25

A11

A3

9

24

OE\

A3

9

24

OE\

• Battery Backup: 2V data retention

A2

10

23

A10

A2

10

23

A10

A1

11

22

CE\

•

Low power standby

A1

11

22

CE\

A0

12

21

DQ8

A0

12

21

DQ8

DQ1

13

20

DQ7

•

High-performance, low-power CMOS process

DQ1

13

20

DQ7

DQ2

14

19

DQ6

DQ2

14

19

DQ6

DQ3

15

18

DQ5

•

Single +5V ( +10%) Power Supply

DQ3

15

18

DQ5

VSS

16

17

DQ4

•

Easy memory expansion with CE1\, CE2, and OE\

VSS

16

17

DQ4

32-Pin LCC (ECA)

options.

32-Pin Flat Pack (F)

•

All inputs and outputs are TTL compatible

A12

A14

A106

NC

CC

A15 CE2

V

4

3

2

1

32

31 30

NC

1

32 VCC

A16

2

31

A15

A14

3

30 CE2

A7

5

29

WE\

A12

4

29 WE\

A6

6

28

A13

A7

5

28

A13

OPTIONS

MARKING

A6

6

27

A8

A5

7

27

A8

A5

7

26

A9

A4

8

26

A9

A3

9

24

OE\

A2

10

24

OE \

A4

8

25

A11

A3

9

25

A11

•

Timing

A2 10

23

A10

A1

11

23

A10

A1 11

22

CE\

A0 12

21 DQ8

A0

12

22

CE1\

12ns access

-12 (contact factory)

DQ1 13

20 DQ7

DQ1

13

21

DQ8

DQ2 14

19 DQ6

DQ3 15

18 DQ5

15ns access

-15

VSS

16

17 DQ4

14 15 16 17 18 19 20

DQ2

DQ3

SS

DQ4

DQ5

DQ6 DQ7

20ns access

-20

V

25ns access

-25

35ns access

-35

45ns access

-45

GENERAL DESCRIPTION

55ns access

-55*

The MT5C1008 SRAM employs high-speed, low power

70ns access

-70*

CMOS designs using a four-transistor memory cell, and are

•

Package(s) •

fabricated using double-layer metal, double-layer polysilicon

technology.

Ceramic DIP (400 mil)

C

No. 111

For design flexibility in high-speed memory

Ceramic DIP (600 mil)

CW

No. 112

applications, this device offers dual chip enables (CE1\, CE2)

Ceramic LCC

EC

No. 207

and output enable (OE\). These control pins can place the

Ceramic LCC

ECA

No. 208

outputs in High-Z for additional flexibility in system design.

Ceramic Flatpack

F

No. 303

All devices operate from a single +5V power supply and all

Ceramic SOJ

DCJ

No. 501

inputs and outputs are fully TTL compatible.

Ceramic SOJ

SOJ

No. 507

Writing to these devices is accomplished when write

•

2V data retention/low power

L

enable (WE\) and CE1\ inputs are both LOW and CE2 is HIGH.

Reading is accomplished when WE\ and CE2 remain HIGH and

*Electrical characteristics identical to those provided for the 45ns

CE1\ and OE\ go LOW. The devices offer a reduced power

standby mode when disabled, allowing system designs to

access devices.

achieve low standby power requirements.

For more products and information

The “L” version offers a 2V data retention mode, re-

ducing current consumption to 1mA maximum.

please visit our web site at

www.austinsemiconductor.com

MT5C1008	Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Rev. 5.5 8/01	1

SRAM

MT5C1008

Austin Semiconductor, Inc.

FUNCTIONAL BLOCK DIAGRAM

A A A A A A A A A

VCC GND

	DECODER			MEMORY ARRAY
				1,048,576-BIT
	ROW
	(LSB)

COLUMN DECODER

A A A A A A A A

	DQ8
I/O CONTROL
	DQ1
	CE1\
	CE2
(LSB)	OE\
	WE\
	POWER
	DOWN

NOTE: The two least significant row address bits (A8 and A6) are encoded using gray code.

TRUTHTABLE

MODE	OE\	CE1\	CE2	WE\	DQ	POWER
STANDBY	X	H	X	X	HIGH-Z	STANDBY
STANDBY	X	X	L	X	HIGH-Z	STANDBY
READ	L	L	H	H	Q	ACTIVE
READ	H	L	H	H	HIGH-Z	ACTIVE
WRITE	X	L	H	L	D	ACTIVE

MT5C1008	Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Rev. 5.5 8/01	2

SRAM

MT5C1008

Austin Semiconductor, Inc.

ABSOLUTEMAXIMUMRATINGS*
Supply Voltage Range (Vcc)...............................	-.5V to +6.0V
Storage Temperature ....................................	-65°C to +150°C
Short Circuit Output Current (per I/O)….......................20mA
Voltage on any Pin Relative to Vss................	-.5V to Vcc+1 V
Max Junction Temperature**.......................................	+150°C
Power Dissipation .....................................................................	1 W

*Stresses at or greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods will affect reliability. Refer to page 17 of this datasheet for a technical note on this subject.

** Junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow, and humidity.

ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS

(-55oC < T

C

< 125oC & -45oC to +85oC; V = 5.0V +10%)

CC

DESCRIPTION

CONDITIONS

SYM

MIN

MAX

UNITS

NOTES

Input High (Logic 1) Voltage

VIH

2.2

VCC+0.5

V

1

Input Low (Logic 0) Voltage

VIL

-0.5

0.8

V

1, 2

Input Leakage Current

0V<VIN<VCC

ILI

-10

10

µA

Output Leakage Current

Output(s) disabled

ILO

-10

10

µA

0V<VOUT<VCC

Output High Voltage

IOH=-4.0mA

VOH

2.4

V

1

Output Low Voltage

IOL=8.0mA

VOL

0.4

V

1

MAX

PARAMETER

CONDITIONS

SYM

-12

-15

-20

-25

-35

-45

UNITS

NOTES

Power Supply

CE\ < VIL; OE\, WE\, and CE2>VIH

ICCSP

250

180

150

140

135

125

mA

3

VCC = MAX, f = MAX = 1/tRC (MIN)

Current: Operating

Output Open

*L version only

ICCLP *

250

180

140

130

125

115

mA

Power Supply

CE\=VIH, CE2=VIL; Other Inputs at

<V

, >V

, V

= MAX

ISBT

25

25

25

25

25

25

mA

Current: Standby

IH

CC

IL

f = 0 Hz

CE\ > VCC -0.2V; VCC = MAX

VIL < VSS -0.2V

ISBC

10

10

10

10

10

10

mA

VIH > VCC -0.2V; F = 0 Hz

CAPACITANCE

	DESCRIPTION	CONDITIONS	SYM	MAX	UNITS	NOTES
	Input Capacitance (A0-A16)	TA = 25oC, f = 1MHz	CI	12	pF	4
	Output Capacitance		CO	14	pF	4
		VCC = 5V
	Input Capacitance (CE\, WE\, OE\)		CI	20	pF	4

MT5C1008	Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Rev. 5.5 8/01	3

SRAM

MT5C1008

Austin Semiconductor, Inc.

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

(Note 5) (-55oC < TC < 125oC & -40oC to +85oC; VCC = 5.0V +10%)

	DESCRIPTION		-12		-15		-20		-25		-35		-45
		SYMBOL	MIN	MAX	MIN	MAX	MIN	MAX	MIN	MAX	MIN	MAX	MIN	MAX	UNITS	NOTES
	READ CYCLE
	READ cycle time	tRC	12		15		20		25		35		45		ns
	Address access time	tAA		12		15		20		25		35		45	ns
	Chip Enable access time	tACE		12		15		20		25		35		45	ns
	Output hold from address change	tOH	3		3		3		3		3		3		ns
	Chip Enable to output in Low-Z	tLZCE	3		3		3		3		3		3		ns	4, 6, 7
	Chip disable to output in High-Z	tHZCE		7		7		8		10		15		20	ns	4, 6, 7
	Output Enable access time	tAOE		7		7		7		10		15		20	ns	4, 6, 7
	Output Enable to output in Low-Z	tLZOE	0		0		0		0		0		0		ns
	Output disable to output in High-Z	tHZOE		7		7		8		10		15		20	ns	4, 6, 7
	WRITE CYCLE
	WRITE cycle time	tWC	12		15		20		25		35		45		ns
	Chip Enable to end of write	tCW	11		12		15		20		25		35		ns
	Address valid to end of write	tAW	11		12		15		20		25		35		ns
	Address setup time	tAS	0		0		0		0		0		0		ns
	Address hold from end of write	tAH	0		0		0		0		0		5		ns
	WRITE pulse width	tWP	11		12		15		20		25		35		ns
	Data setup time	tDS	8		8		10		15		20		20		ns
	Data hold time	tDH	0		0		0		0		0		0		ns
	Write disable to output in Low-Z	tLZWE	5		5		5		5		5		5		ns	4, 6, 7
	Write Enable to output in High-Z	tHZWE		7		7		9		10		15		20	ns	4, 6, 7

MT5C1008	Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Rev. 5.5 8/01	4

SRAM

MT5C1008

Austin Semiconductor, Inc.

+5V

+5V

ACTEST CONDITIONS

...................................Input pulse levels	Vss to 3.0V
Input rise and fall times .......................................	5ns
Input timing reference levels .............................	1.5V
Output reference levels .....................................	1.5V
Output load ..............................	See Figures 1 and 2

NOTES

1.All voltages referenced to VSS (GND).

2.-2V for pulse width < 20ns

3.ICC is dependent on output loading and cycle rates. The specified value applies with the outputs

unloaded, and f =

1

Hz.

tRC (MIN)

4.This parameter is guaranteed but not tested.

5.Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted.

6.tLZCE, tLZWE, tLZOE, t HZCE, tHZOE and tHZWE are specified with CL = 5pF as in Fig. 2. Transition is measured ±200mV typical from steady state voltage, allowing for actual tester RC time constant.

		480		480
	Q		Q
		30
	255		255	5 pF

	Fig. 1 Output Load	Fig. 2 Output Load
	Equivalent
		Equivalent

7.At any given temperature and voltage condition, tHZCE is less than tLZCE, and tHZWE is less than tLZWE and tHZOE is less than tLZOE.

8.WE\ is HIGH for READ cycle.

9.Device is continuously selected. Chip enables and

output enables are held in their active state.

10.Address valid prior to, or coincident with, latest occurring chip enable.

11.tRC = Read Cycle Time.

12.CE2 timing is the same as CE1\ timing. The waveform is inverted.

13.Chip enable (CE1\, CE2) and write enable (WE\) can initiate and terminate a WRITE cycle.

DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)

DESCRIPTION	CONDITIONS		SYMBOL	MIN	MAX	UNITS	NOTES
VCC for Retention Data			VDR	2	---	V
	CE\ > (VCC - 0.2V)
Data Retention Current	VIN > (VCC - 0.2V)	VCC = 2V	ICCDR		1.0	mA
	or < 0.2V, f=0
Chip Deselect to Data			tCDR	0	---	ns	4
Retention Time
Operation Recovery Time			tR	tRC		ns	4, 11

LOW Vcc DATA RETENTION WAVEFORM

VCC

CE1\	VIH
	V
	IL
CE2	VIH
	V
	IL

DATA RETENTION MODE

	4.5V	VDR	> 2V	4.5V
tCDR				tR

23456789	VDR
2345678
23456789
2345678
23456789
23456789	<VSS + 0.2V
23456789
23456789

2345678123

2345678112

2345678112

2345678123

2345678123

2345678112

2345678112

2345678123

123 DON’T CARE

123

123 4

123 4 UNDEFINED

123 4

1234

MT5C1008	Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Rev. 5.5 8/01	5

SRAM

MT5C1008

Austin Semiconductor, Inc.

		READ CYCLE NO. 1 8, 9
		tRC
ADDRESS		VALID
		tAA
	tOH
DQ	PREVIOUS DATA VALID	DATA VALID

READ CYCLE NO. 2 7, 8, 10, 12

tRC

CE\

tAOE

tHZOE

tLZOE

OE\

tLZCE
tACE	tHZCE
DQ	DATA VALID

tPU

tPD

Icc

MT5C1008	Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Rev. 5.5 8/01	6