AUSTIN MT5C6405C-55L-IT, MT5C6405C-55L-XT, MT5C6405C-45L-XT, MT5C6405C-45L-883C, MT5C6405C-25L-XT Datasheet

SRAM

MT5C6405

Austin Semiconductor, Inc.

16K x 4 SRAM

SRAM MEMORY ARRAY

AVAILABLE AS MILITARY

SPECIFICATIONS

•SMD 5962-86859

•MIL-STD-883

FEATURES

•High Speed: 12, 15, 20, 25, 35, 45, 55, and 70ns

•Battery Backup: 2V data retention

•High-performance, low-power CMOS double-metal process

•Single +5V (+10%) Power Supply

•Easy memory expansion with CE\

•All inputs and outputs are TTL compatible

OPTIONS		MARKING
•	Timing
	12ns access	-12
	15ns access	-15
	20ns access	-20
	25ns access	-25
	35ns access	-35
	45ns access	-45*
	55ns access	-55*
	70ns access	-70*
•	Package(s)
	Ceramic DIP (300 mil)	C	No. 106
	Ceramic LCC	E C	No. 204
•	Operating Temperature Ranges
	Industrial (-40oC to +85oC)	IT
	Military (-55oC to +125oC)	XT
• 2V data retention/low power		L

*Electrical characteristics identical to those provided for the 35ns access devices.

For more products and information please visit our web site at www.austinsemiconductor.com

PIN ASSIGNMENT

	(Top View)
	24-Pin DIP (C)
	(300 MIL)
	A5	1			24	Vcc
	A6	2			23	A4
	A7	3			22	A3
	A8	4			21	A2
	A9	5			20	A1
	A10	6			19	A0
	A11	7			18	NC
	A12	8			17	DQ4
	A13	9			16	DQ3
	CE\	10			15	DQ2
	OE\	11			14	DQ1
	Vss	12			13	WE\
	28-Pin LCC (EC)
		A5	NC	NC	Vcc NC
		3	2	1	28 27
A6	4					26	NC
A7	5					25	A4
A8	6					24	A3
A9	7					23	A2
A10	8					22	A1
A11	9					21	A0
A12	10					20	DQ4
A13	11					19	DQ3
CE\ 12						18	DQ2
		13	14 15 16 17
		NC Vss OE\			DQ1 WE\

GENERAL DESCRIPTION

The Austin Semiconductor SRAM family employs high-speed, low-power CMOS designs using a four-transistor memory cell. Austin Semiconductor SRAMs are fabricated using double-layer metal, double-layer polysilicon technology.

For flexibility in high-speed memory applications, Austin Semiconductor offers chip enable (CE\) and output enable (OE\) capability. These enhancements can place the outputs in High-Z for additional flexibility in system design.

Writing to these devices is accomplished when write enable (WE\) and CE\ inputs are both LOW. Reading is accomplished when WE\ remains HIGH and CE\ and OE\ go LOW. The device offers a reduced power standby mode when disabled. This allows system designs to achieve low standby power requirements.

All devices operate from a single +5V power supply and all inputs and outputs are fully TTL compatible.

MT5C6405	Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Rev. 2.0 5/01	1

A A A A A A A A A

SRAM

MT5C6405

Austin Semiconductor, Inc.

FUNCTIONAL BLOCK DIAGRAM

	VCC	GND
DECODERROW			CONTROLI/O	D
				Q
	1,048,576-BIT
	MEMORY ARRAY
				CE\
(LSB)				WE\
				OE\
	COLUMN DECODER			POWER
			(LSB)	DOWN

A A A A A A A A A A

TRUTHTABLE

MODE	OE\	CE\	WE\	DQ	POWER
STANDBY	X	H	X	HIGH-Z	STANDBY
READ	L	L	H	Q	ACTIVE
READ	H	L	H	HIGH-Z	ACTIVE
WRITE	X	L	L	D	ACTIVE

MT5C6405	Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Rev. 2.0 5/01	2

SRAM

MT5C6405

Austin Semiconductor, Inc.

ABSOLUTEMAXIMUMRATINGS*

Voltage on any Input or DQ Relative to Vss....-0.5V to +7.0V1

Storage Temperature…...................................-65	oC to +150oC
Power Dissipation.................................................................	1W
Max Junction Temperature..................................................	+175°C
Lead Temperature (soldering 10 seconds)........................	+260oC
Short Circuit Output Current...........................................	20mA

1 All voltage referenced to Vss.

*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS

(-55oC < T

C

< 125oC; V

= 5V +10%)

CC

DESCRIPTION

CONDITIONS

SYM

MIN

MAX

UNITS

NOTES

Input High (Logic 1) Voltage

VIH

2.2

Vcc+0.5V

V

1

Input Low (Logic 0) Voltage

VIL

-0.5

0.8

V

1, 2

Input Leakage Current

0V < VIN < VCC

ILI

-10

10

µA

Output Leakage Current

Outputs Disabled

ILO

-10

10

µA

0V < VOUT < VCC

Output High Voltage

IOH = -4.0mA

VOH

2.4

V

1

Output Low Voltage

IOL = 8.0mA

VOL

0.4

V

1

MAX

PARAMETER

CONDITIONS

SYM

-12

-15

-20

-25

-35

UNITS

NOTES

Power Supply

CE\ < VIL; VCC = MAX

Icc

140

125

110

100

90

mA

3

Current: Operating

Output Open

Power Supply

CE\ > VIH; VCC = MAX

ISBT1

50

45

40

35

30

mA

Current: Standby

f = 0 Hz

CE\ > (VCC -0.2); VCC = MAX

All Other Inputs < 0.2V

ISBC2

25

25

25

25

25

mA

or > (VCC - 0.2V), f = 0 Hz

CAPACITANCE

DESCRIPTION	CONDITIONS	SYM	MAX	UNITS	NOTES
Input Capacitance	TA = 25oC, f = 1MHz	CI	8	pF	4
Output Capacitance	Vcc = 5V	CO	10	pF	4

MT5C6405	Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Rev. 2.0 5/01	3

SRAM

MT5C6405

Austin Semiconductor, Inc.

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

(Note 5) (-55oC < T < 125oC; V	CC	= 5V +10%)
C
DESCRIPTION				-12		-15		-20		-25		-35
			SYMBOL	MIN	MAX	MIN	MAX	MIN	MAX	MIN	MAX	MIN	MAX	UNITS	NOTES
READ CYCLE
READ cycle time			tRC	12		15		20		25		35		ns
Address access time			tAA		12		15		20		25		35	ns
Chip Enable access time			tACE		12		15		20		25		35	ns
Output hold from address change			tOH	2		2		2		2		2		ns
Chip Enable to output in Low-Z			tLZCE	2		2		2		2		2		ns	7
Chip disable to output in High-Z			tHZCE		7		8		10		12		15	ns	6, 7
Chip Enable to power-up time			tPU	0		0		0		0		0		ns
Chip disable to power-down time			tPD		12		15		20		25		35	ns
Output Enable access time			tAOE		6		7		8		10		15	ns
Output Enable to output in Low-Z			tLZOE	0		0		0		0		8		ns
Output disable to output in High-Z			tHZOE		6		7		8		10		15	ns	6
WRITE CYCLE
WRITE cycle time			tWC	12		15		20		25		35		ns
Chip Enable to end of write			tCW	10		12		15		20		25		ns
Address valid to end of write			tAW	10		12		15		20		25		ns
Address setup time			tAS	0		0		0		0		0		ns
Address hold from end of write			tAH	0		0		0		0		0		ns
WRITE pulse width			tWP	10		12		15		20		25		ns
Data setup time			tDS	7		8		10		12		15		ns
Data hold time			tDH	0		0		0		0		0		ns
Write disable to output in Low-Z			tLZWE	2		2		2		2		2		ns	7
Write Enable to output in High-Z			tHZWE	0	6	0	7	0	8	0	10	0	15	ns	6, 7

MT5C6405	Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Rev. 2.0 5/01	4