AUSTIN MT5C2568F-12L-XT, MT5C2568F-12L-883C, MT5C2568F-100L-XT, MT5C2568ECW-70L-IT, MT5C2568ECW-70L-XT Datasheet

SRAM

MT5C2568

Austin Semiconductor, Inc.

32K x 8 SRAM

SRAM MEMORY ARRAY

AVAILABLE AS MILITARY SPECIFICATIONS

•SMD 5962-88662 •MIL-STD-883

FEATURES

•Access Times: 12, 15, 20, 25, 35, 45, 55, 70, & 100ns

•Battery Backup: 2V data retention

•Low power standby

•High-performance, low-power CMOS double-metal process

•Single +5V ( +10%) Power Supply

•Easy memory expansion with CE\

•All inputs and outputs are TTL compatible

OPTIONS	MARKING
• Timing
12ns access1	-12
15ns access1	-15
20ns access	-20
25ns access	-25
35ns access	-35
45ns access	-45
55ns access2	-55
70ns access2	-70
100ns access	-100

PIN ASSIGNMENT

(Top View)

	28-PIN SOJ (DCJ)	32-Pin LCC (ECW)
	28-Pin DIP (C, CW)

A14	1	28	VCC
A12	2	27	WE\
A7	3	26	A13
A6	4	25	A8
A5	5	24	A9
A4	6	23	A11
A3	7	22	OE\
A2	8	21	A10
A1	9	20	CE\
A0	10	19	DQ8
DQ1	11	18	DQ7
DQ2	12	17	DQ6
DQ3	13	16	DQ5
VSS	14	15	DQ4

							A7		A12	A14		NC V				WE\ A13
														CC
									3	2 1 32 31 30
							4
A6		5																						29
																											A8
A5		6																						28			A9
A4		7																						27			A11
A3		8																						26			NC
A2		9																						25			OE\
		10
A1																								24			A10
A0		11																						23			CE\
NC		12																						22			DQ8
DQ1		13																						21			DQ7

14 15 16 17 18 19 20

DQ2 DQ3	SS	NC DQ4 DQ5 DQ6
	V

28-Pin LCC (EC)

28-Pin Flat Pack (F)

A14	1								28	VCC
A12	2								27	WE\
A7	3								26	A13
A6	4								25	A8
A5	5								24	A9
A4	6								23	A11
A3	7								22	OE\
A2	8								21	A10
A1	9								20	CE\
A0	10								19	DQ8
DQ1 11									18	DQ7
DQ2 12									17	DQ6
DQ3 13									16	DQ5
VSS	14								15	DQ4

								A7		A12		A14	V			WE\
														CC
										2	1		28			27
								3
A6		4																				26
																									A13
A5		5																				25			A8
A4		6																				24			A9
		7
A3																						23			A11
A2		8																				22			OE\
A1		9																				21			A10
A0		10																				20			CE\
DQ1		11																				19			DQ8
DQ2		12																				18			DQ7

13 14 15 16 17

DQ3	SS	DQ4 DQ5 DQ6
	V

•	Package(s)3
	Ceramic DIP (300 mil)	C	No. 108
	Ceramic DIP (600 mil)	CW	No. 110
	Ceramic LCC (28 leads)	EC	No. 204
	Ceramic LCC (32 leads)	ECW	No. 208
	Ceramic LCC	ECJ	No. 605
	Ceramic Flat Pack	F	No. 302
	Ceramic SOJ	DCJ	No. 500
•	Operating Temperature Ranges
	Military -55oC to +125oC	XT
	Industrial -40oC to +85oC	IT
• 2V data retention/low power		L

NOTES:

1.-12 available in IT only.

2.Electrical characteristics identical to those provided for the 45ns access devices.

3.Plastic SOJ (DJ Package) is available on the AS5C2568 datasheet.

For more products and information please visit our web site at www.austinsemiconductor.com

GENERAL DESCRIPTION

The Austin Semiconductor SRAM family employs high-speed, low power CMOS designs using a four-transistor memory cell. These SRAMs are fabricated using double-layer metal, double-layer polysilicon technology.

For flexibility in high-speed memory applications, Austin Semiconductor offers chip enable (CE\) and output enable (OE\) capability. These enhancements can place the outputs in High-Z for additional flexibility in system design.

Writing to these devices is accomplished when write enable (WE\) and CE\ inputs are both LOW. Reading is accomplished when WE\ remains HIGH and CE\ and OE\ go LOW. The device offers a reduced power standby mode when disabled. This allows system designs to achieve low standby power requirements.

The “L” version provides a battery backup/low voltage data retention mode, offering 2mW maximum power dissipation at 2 volts. All devices operate from a single +5V power supply and all inputs and outputs are fully TTL compatible.

MT5C2568	Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Rev. 3.0 10/00	1

SRAM

MT5C2568

Austin Semiconductor, Inc.

FUNCTIONAL BLOCK DIAGRAM

A0

A14

I/O0

I/O7

CE\

OE\

WE\

		Vcc
DECODER	256 x 1024	GND
	MEMORY ARRAY

I/O	COLUMN I/O

DATA

CIRCUIT

9A128-1

CONTROL

CIRCUIT

TRUTHTABLE

MODE	OE\	CE\	WE\	DQ	POWER
STANDBY	X	H	X	HIGH-Z	STANDBY
READ	L	L	H	Q	ACTIVE
READ	H	L	H	HIGH-Z	ACTIVE
WRITE	X	L	L	D	ACTIVE

MT5C2568	Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Rev. 3.0 10/00	2

SRAM

MT5C2568

Austin Semiconductor, Inc.

ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Input or DQ Relative
to Vss..................................................................	-0.5V to Vcc +0.5V
Voltage on Vcc Supply Relative to Vss.......................	-1V to +7V
Storage Temperature..............................................	-65oC to +150oC
Power Dissipation.......................................................................	1W
Short Circuit Output Current.................................................	50mA
Lead Temperature (soldering 10 seconds)........................	+260oC
Max. Junction Temperature.................................................	+175oC

*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS

(-55oC < T < 125oC or -40oC to +85oC; V					CC	= 5.0V +10%)
C
DESCRIPTION					CONDITIONS						SYM				MIN				MAX				UNITS		NOTES
Input High (Logic 1) Voltage											VIH					2.2		VCC+0.5						V	1
Input Low (Logic 0) Voltage											VIL				-0.5			0.8						V	1,2
Input Leakage Current					0V<VIN<VCC						ILI				-10			10						µA
Output Leakage Current				Output(s) disabled							ILo				-10			10						µA
					0V<VOUT<VCC
Output High Voltage					IOH = -4.0mA						VOH					2.4								V	1
Output Low Voltage					IOL = 8.0mA						VOL							0.4						V	1
														MAX
DESCRIPTION		CONDITIONS					SYM		-12	-15			-20				-25		-35		-45			UNITS		NOTES
Power Supply		CE\<VIL; Vcc = MAX
				t			Icc		190	180			170				160		150		150			mA		3
Current: Operating
		f = MAX = 1/ RC (MIN)
		Output Open
	TTL	CE\<VIH; Outputs Open					ISBT		60	50			40				35		35		35			mA
		Vcc = MAX
Power Supply
		CE\>Vcc-0.2V; Vcc = MAX
Current: Standby	CMOS	VIN<+0.2V or >Vcc-0.2V;					ISBC		20	20			20				20		20		20			mA
		f = 0 Hz, Outputs Open
			"L" Version Only				ISBC2		4	4			4				4		4		4			mA

CAPACITANCE

PARAMETER	CONDITIONS	SYM	MAX	UNITS	NOTES
Input Capacitance	TA = 25oC, f = 1MHz	CIN	11	pF	4
Output Capacitance	Vcc = 5V	CIO	11	pF	4

MT5C2568	Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Rev. 3.0 10/00	3

SRAM

MT5C2568

Austin Semiconductor, Inc.

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

(Note 5) (-55oC < T < 125oC or -40oC to +85oC; V							CC		= 5.0V +10%)
C
DESCRIPTION	SYM	-12		-15			-20			-25			-35		-45		UNITS	NOTES
		MIN	MAX	MIN	MAX	MIN		MAX		MIN	MAX		MIN	MAX	MIN	MAX
READ CYCLE
READ cycle time	tRC	12		15		20				25			35		45		ns
Address access time	tAA		12		15				20		25			35		45	ns
Chip enable access time	tACE		12		15				20		25			35		45	ns
Output hold from address change	tOH	2		3		3				3			3		3		ns
Chip enable to output in Low-Z	tLZCE	2		3		3				3			3		3		ns	7
Chip disable to output in High-Z	tHZCE		7		10				10		15			35		20	ns	6, 7
Output enable to access time	tAOE		6		8				10		15			20		20	ns
Output enable to output in Low-Z	tLZOE	0		0		0				0			2		0		ns
Output disable to output in High-Z	tHZOE		7		10				10		15			35		20	ns	6
WRITE CYCLE
WRITE cycle time	tWC	12		15		20				25			35		45		ns
Chip enable to end of write	tCW	10		12		15				20			30		40		ns
Address valid to end of write	tAW	10		12		15				20			30		40		ns
Address setup time	tAS	0		0		0				0			0		0		ns
Address hold from end of write	tAH	2		0		0				0			0		0		ns
WRITE pulse width	tWP	10		12		15				20			30		40		ns
Data setup time	tDS	8		10		10				15			20		20		ns
Data hold time	tDH	0		0		0				0			0		3		ns
Write disable to output in Low-Z	tLZWE	0		0		0				3			3		3		ns	7
Write enable to output in High-Z	tHZWE		7		10				10		15			35		20	ns	6, 7

MT5C2568	Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Rev. 3.0 10/00	4

SRAM

Austin Semiconductor, Inc.

MT5C2568

AC TEST CONDITIONS

+5V

+5V

Input pulse levels

Vss to 3V

480

480

Input rise and fall times.....................................................

5ns

Input timing reference level.............................................

1.5V

Q

Q

Output reference level

1.5V

30 pF

255

255

5 pF

Output load

See figures 1 & 2

Fig. 1

Fig. 2

OUTPUT LOAD

OUTPUT LOAD

NOTES

EQUIVALENT

EQUIVALENT

1.All voltages referenced to VSS (GND).

2.-3V for pulse width < 20ns

3.ICC is dependent on output loading and cycle rates. The specified value applies with the outputs unloaded, and

f =

1

Hz.

tRC (MIN)

4.This parameter is guaranteed but not tested.

5.Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted.

6.t HZCE, tHZOE and tHZWE are specified with CL = 5pF as in Fig. 2. Transition is measured ±500mV typical from steady state voltage, allowing for actual tester RC time

constant.

7.At any given temperature and voltage condition, tHZCE is less than tLZCE, and tHZWE is less than tLZWE.

8.WE\ is HIGH for READ cycle.

9.Device is continuously selected. Chip enables and output enables are held in their active state.

10.Address valid prior to, or coincident with, latest occurring chip enable.

11.tRC = Read Cycle Time.

12.Chip enable (CE\) and write enable (WE\) can initiate and terminate a WRITE cycle.

DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)

DESCRIPTION	CONDITIONS				SYM	MIN	MAX	UNITS	NOTES
VCC for Retention Data					VDR	2		V
	CE\ > (VCC-0.2V)
Data Retention Current	V	> (V	CC	-0.2V)	ICCDR		1	mA
	IN
		or < 0.2V
Chip Deselect to Data					tCDR	0	--	ns	4
Retention Time
Operation Recovery Time					tR	tRC		ns	4, 11

LOW Vcc DATA RETENTION WAVEFORM

VCC				DATA RETENTION MODE
			4.5V	VDR	> 2V	4.5V
	tCDR							tR

CE\	V	IH	12345678	V	DR	12345678
			12345678			12345678
	VIL		12345678			12345678	123
							123 DON’T CARE
							123 4	UNDEFINED
							123 4
							123 4
							1234

MT5C2568	Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Rev. 3.0 10/00	5