Features
•Single Voltage for Read and Write: 2.7V to 3.6V (BV), 3.0V to 3.6V (LV)
•Fast Read Access Time - 120 ns
•Internal Program Control and Timer
•16K bytes Boot Block With Lockout
•Fast Chip Erase Cycle Time - 10 seconds
•Byte-by-Byte Programming - 30 μs/Byte Typical
•Hardware Data Protection
•DATA Polling For End Of Program Detection
•Low Power Dissipation
–25 mA Active Current
–50 μA CMOS Standby Current
•Typical 10,000 Write Cycles
•Small Packaging
–8 x 8 mm CBGA
–8 x 14 mm V-TSOP
Description
The AT49BV/LV040 are 3-volt-only, 4-megabit Flash memories organized as 524,288 words of 8-bits each. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to 120 ns with power dissipation of just 90 mW over the commercial temperature range. When the device is deselected, the CMOS standby current is less than 50 μA.
The device contains a user-enabled “boot block” protection feature. Two versions of the feature are available: the AT49BV/LV040 locates the boot block at lowest order addresses (“bottom boot”); the AT49BV/LV040T locates it at highest order addresses (“top boot”).
(continued)
Pin Configurations |
CBGA Top View |
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Pin Name |
Function |
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4 |
5 |
6 |
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A0 - A18 |
Addresses |
A |
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GND I/O6 VCC VCC I/O2 |
OE |
GND |
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CE |
Chip Enable |
B |
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A17 |
I/O7 |
I/O4 |
NC |
NC |
I/O0 |
CE |
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C |
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OE |
Output Enable |
A10 |
NC |
I/O5 |
NC |
I/O3 |
I/O1 |
A0 |
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D |
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WE |
Write Enable |
A14 |
A13 |
A9 |
NC |
NC |
A6 |
A3 |
E |
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I/O0 - I/O7 |
Data Inputs/Outputs |
A16 |
A11 |
WE |
NC |
A7 |
A4 |
A1 |
F |
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A15 |
A12 |
A8 |
NC |
A18 |
A5 |
A2 |
PLCC Top View
V - TSOP Top View (8 x 14 mm) or
T - TSOP Top View (8 x 20 mm)
4-Megabit |
(512K x 8) |
Single 2.7-volt |
Battery-Voltage™ |
Flash Memory |
AT49BV040 |
AT49BV040T |
AT49LV040 |
AT49LV040T |
AT49BV/LV040 |
0679AX-A–9/97 |
1 |
To allow for simple in-system reprogrammability, the AT49BV/LV040 does not require high input voltages for programming. Three-volt-only commands determine the read and programming operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT49BV/LV040 is performed by erasing the entire 4 megabits of memory and then programming on a byte-by-byte basis. The typical byte programming time is a fast 30 μs. The end of a program cycle can be
optionally detected by the DATA polling feature. Once the end of a byte program cycle has been detected, a new
access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000 cycles.
The optional 16K bytes boot block section includes a reprogramming write lock out feature to provide data integrity. The boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is permanently protected from being reprogrammed.
Block Diagram
VCC
GND
OE
WE
CE
ADDRESS
INPUTS
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AT49BV/LV040 |
AT49BV/LV040T |
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DATA INPUTS/OUTPUTS |
DATA INPUTS/OUTPUTS |
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I/O7 - I/O0 |
I/O7 - I/O0 |
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8 |
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8 |
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DATA LATCH |
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DATA LATCH |
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OE, CE, AND WE |
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LOGIC |
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INPUT/OUTPUT |
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INPUT/OUTPUT |
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BUFFERS |
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BUFFERS |
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Y DECODER |
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Y-GATING |
7FFFFH |
Y-GATING |
7FFFFH |
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X DECODER |
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MAIN MEMORY |
OPTIONAL BOOT |
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(496K BYTES) |
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BLOCK (16K BYTES) |
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03FFFH |
7C000H |
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OPTIONAL BOOT |
MAIN MEMORY |
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BLOCK (16K BYTES) |
00000H |
(496K BYTES) |
00000H |
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Device Operation
READ: The AT49BV/LV040 is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dualline control gives designers flexibility in preventing bus contention.
ERASURE: Before a byte can be reprogrammed, the 512K bytes memory array (or 496K bytes if the boot block featured is used) must be erased. The erased state of the memory bits is a logical “1”. The entire device can be erased at one time by using a 6-byte software code. The software chip erase code consists of 6-byte load commands to specific address locations with a specific data pattern (please refer to the Chip Erase Cycle Waveforms).
After the software chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time needed to erase the whole chip is tEC. If the boot block lockout feature has been enabled, the data in the boot sector will not be erased.
BYTE PROGRAMMING: Once the memory array is erased, the device is programmed (to a logical “0”) on a byte-by- byte basis. Please note that a data “0” cannot be programmed back to a “1”; only erase operations can convert
“0”s to “1”s. Programming is accomplished via the internal device command register and is a 4 bus cycle operation (please refer to the Command Definitions table). The device will automatically generate the required internal program pulses.
The program cycle has addresses latched on the falling edge of WE or CE, whichever occurs last, and the data latched on the rising edge of WE or CE, whichever occurs first. Programming is completed after the specified tBP
cycle time. The DATA polling feature may also be used to indicate the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block that has a programming lockout feature. This feature prevents programming of data in the designated block once the feature has been enabled. The size of the block is 16K bytes. This block, referred to as the boot block, can contain secure code that is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; the boot block's usage as a write protected region is optional to the us er . The addres s r ange of the AT49BV/LV040 boot block is 00000H to 03FFFH while the address range of the AT49BV/LV040T boot block is 7C000H to 7FFFFH.
2 AT49BV/LV040
AT49BV/LV040
Once the feature is enabled, the data in the boot block can no longer be erased or programmed. Data in the main memory block can still be changed through the regular programming method. To activate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. Please refer to the Command Definitions table.
BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine if programming of the boot block section is locked out. When the device is in the software product identification mode (see Software Product Identification Entry and Exit sections) a read from address location 00002H will show if programming the boot block is locked out. If the data on I/O0 is low, the boot block can be programmed; if the data on I/O0 is high, the program lockout feature has been activated and the block cannot be programmed. The software product identification code should be used to return to standard operation.
PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel.
It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product.
For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes.
DATA POLLING: The AT49BV/LV040 features DATA polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA polling may begin at any time during the program cycle.
TO G G L E B I T: In a dd i t io n t o D A T A p o l li n g th e AT49BV/LV040 provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle.
HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs to the AT49BV/LV040 in the following ways: (a) VCC sense: if VCC is below 1.8V (typical), the program function is inhibited. (b) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (c) Noise filter: pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle.
INPUT LEVELS: While operating with a 2.7V to 3.6V power supply, the address inputs and control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device. The I/O line s c an on ly be dr iv en fr om 0 to V CC + 0 . 6V .
3
Command Definition (in Hex)
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1st Bus |
2nd Bus |
3rd Bus |
4th Bus |
5th Bus |
6th Bus |
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Command |
Bus |
Cycle |
Cycle |
Cycle |
Cycle |
Cycle |
Cycle |
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Sequence |
Cycles |
Addr |
Data |
Addr |
Data |
Addr |
Data |
Addr |
Data |
Addr |
Data |
Addr |
Data |
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Read |
1 |
Addr |
DOUT |
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Chip Erase |
6 |
5555 |
AA |
2AAA |
55 |
5555 |
80 |
5555 |
AA |
2AAA |
55 |
5555 |
10 |
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Byte Program |
4 |
5555 |
AA |
2AAA |
55 |
5555 |
A0 |
Addr |
DIN |
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Boot Block Lockout(1) |
6 |
5555 |
AA |
2AAA |
55 |
5555 |
80 |
5555 |
AA |
2AAA |
55 |
5555 |
40 |
Product ID Entry |
3 |
5555 |
AA |
2AAA |
55 |
5555 |
90 |
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Product ID Exit(2) |
3 |
5555 |
AA |
2AAA |
55 |
5555 |
F0 |
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Product ID Exit(2) |
1 |
XXXX |
F0 |
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Notes: 1. The 16K byte boot sector has the address range 00000H to 03FFFH for the AT49BV/LV040 and 7C000H to 7FFFFH for the AT49BV/LV040T.
2.Either one of the Product ID exit commands can be used.
Absolute Maximum Ratings*
Temperature Under Bias |
................................ -55°C to +125°C |
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Storage Temperature ..................................... |
-65°C to +150°C |
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All Input Voltages |
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(including NC Pins) |
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*NOTICE: |
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with Respect to Ground ................................... |
-0.6V to +6.25V |
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All Output Voltages |
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with Respect to Ground ............................ |
- 0.6V to VCC + 0.6V |
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Voltage on |
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OE |
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with Respect to Ground .................................. |
-0.6V to + 13.5V |
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Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
4 AT49BV/LV040