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Features
•Fast Read Access Time – 45 ns
•Low-Power CMOS Operation
–100 µA Max Standby
–20 mA Max Active at 5 MHz
•JEDEC Standard Packages
–28-lead PDIP
–32-lead PLCC
–28-lead TSOP and SOIC
•5V ± 10% Supply
•High Reliability CMOS Technology
–2,000V ESD Protection
–200 mA Latchup Immunity
•Rapid Programming Algorithm – 100 µs/Byte (Typical)
•CMOS and TTL Compatible Inputs and Outputs
•Integrated Product Identification Code
•Industrial and Automotive Temperature Ranges
•Green (Pb/Halide-free) Packaging Option
1. Description
The AT27C256R is a low-power, high-performance 262,144-bit one-time programmable read-only memory (OTP EPROM) organized 32K by 8 bits. It requires only one 5V power supply in normal read mode operation. Any byte can be accessed in less than 45 ns, eliminating the need for speed reducing WAIT states on high-performance microprocessor systems.
Atmel’s scaled CMOS technology provides low-active power consumption, and fast programming. Power consumption is typically only 8 mA in Active Mode and less than 10 µA in Standby.
The AT27C256R is available in a choice of industry-standard JEDEC-approved one time programmable (OTP) plastic DIP, PLCC, SOIC, and TSOP packages. All devices feature two-line control (CE, OE) to give designers the flexibility to prevent bus contention.
With 32K byte storage capability, the AT27C256R allows firmware to be stored reliably and to be accessed by the system without the delays of mass storage media.
Atmel’s AT27C256R has additional features to ensure high quality and efficient production use. The Rapid Programming Algorithm reduces the time required to program the part and guarantees reliable programming. Programming time is typically only 100 µs/byte. The Integrated Product Identification Code electronically identifies the device and manufacturer. This feature is used by industry-standard programming equipment to select the proper programming algorithms and voltages.
256K (32K x 8) OTP EPROM
AT27C256R
0014K–EPROM–10/05
2. Pin Configurations
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Pin Name |
Function |
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A0 - A14 |
Addresses |
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O0 - O7 |
Outputs |
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Chip Enable |
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CE |
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Output Enable |
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OE |
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NC |
No Connect |
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2.128-lead PDIP/SOIC Top View
VPP |
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1 |
28 |
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VCC |
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A12 |
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2 |
27 |
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A14 |
A7 |
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3 |
26 |
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A13 |
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A6 |
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4 |
25 |
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A8 |
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A5 |
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5 |
24 |
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A9 |
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A4 |
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6 |
23 |
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A11 |
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A3 |
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7 |
22 |
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OE |
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A2 |
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8 |
21 |
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A10 |
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A1 |
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9 |
20 |
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CE |
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A0 |
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10 |
19 |
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O7 |
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O0 |
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11 |
18 |
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O6 |
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O1 |
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12 |
17 |
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O5 |
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O2 |
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13 |
16 |
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O4 |
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GND |
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14 |
15 |
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O3 |
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2.232-lead PLCC Top View
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A7 |
A12 |
VPP |
NC |
VCC |
A14 |
A13 |
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A6 |
4 |
3 |
2 |
1 |
32 |
31 |
30 |
A8 |
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5 |
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29 |
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A5 |
6 |
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28 |
A9 |
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A4 |
7 |
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27 |
A11 |
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A3 |
8 |
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26 |
NC |
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A2 |
9 |
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25 |
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OE |
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A1 |
10 |
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24 |
A10 |
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A0 |
11 |
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23 |
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CE |
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NC |
12 |
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22 |
O7 |
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O0 |
13 |
15 |
16 |
17 |
18 |
19 |
21 |
O6 |
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14 |
20 |
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O1 |
O2 |
GND |
NC |
O3 |
O4 |
O5 |
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Note: PLCC Package Pins 1 and 17 are Don’t Connect.
2.328-lead TSOP Top View – Type 1
OE |
1 |
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28 |
A10 |
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A11 |
2 |
27 |
CE |
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A9 |
3 |
26 |
O7 |
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A8 |
4 |
25 |
O6 |
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A13 |
5 |
24 |
O5 |
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A14 |
6 |
23 |
O4 |
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VCC |
7 |
22 |
O3 |
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VPP |
8 |
21 |
GND |
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A12 |
9 |
20 |
O2 |
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A7 |
10 |
19 |
O1 |
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A6 |
11 |
18 |
O0 |
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A5 |
12 |
17 |
A0 |
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A4 |
13 |
16 |
A1 |
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A3 |
14 |
15 |
A2 |
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2 AT27C256R
0014K–EPROM–10/05
AT27C256R
3. System Considerations
Switching between active and standby conditions via the Chip Enable pin may produce transient voltage excursions. Unless accommodated by the system design, these transients may exceed datasheet limits, resulting in device non-conformance. At a minimum, a 0.1 µF high frequency, low inherent inductance, ceramic capacitor should be utilized for each device. This capacitor should be connected between the VCC and Ground terminals of the device, as close to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit boards with large EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be utilized, again connected between the VCC and Ground terminals. This capacitor should be positioned as close as possible to the point where the power supply is connected to the array.
4. Block Diagram
5. |
Absolute Maximum Ratings* |
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Temperature Under Bias |
................................ -55°C to +125°C |
*NOTICE: Stresses beyond those listed under “Absolute Maxi- |
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mum Ratings” may cause permanent damage to |
Storage Temperature ..................................... |
-65°C to +150°C |
the device. This is a stress rating only and func- |
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tional operation of the device at these or any other |
Voltage on Any Pin with |
-2.0V to +7.0V(1) |
conditions beyond those indicated in the opera- |
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Respect to Ground ......................................... |
tional sections of this specification is not implied. |
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Voltage on A9 with |
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Exposure to absolute maximum rating conditions |
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-2.0V to +14.0V(1) |
for extended periods may affect device reliability. |
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Respect to Ground ...................................... |
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VPP Supply Voltage with |
-2.0V to +14.0V(1) |
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Respect to Ground ....................................... |
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Note: |
1. Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 ns.Maximum output pin voltage is |
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VCC + 0.75V dc which may overshoot to +7.0 volts for pulses of less than 20 ns. |
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3
0014K–EPROM–10/05
6. Operating Modes
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Mode/Pin |
CE |
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OE |
Ai |
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VPP |
Outputs |
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Read |
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VIL |
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VIL |
Ai |
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VCC |
DOUT |
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Output Disable |
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VIL |
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VIH |
X(1) |
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VCC |
High Z |
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Standby |
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V |
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X(1) |
X(1) |
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V |
CC |
High Z |
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IH |
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Rapid Program(2) |
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V |
IL |
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V |
IH |
Ai |
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V |
PP |
D |
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IN |
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PGM Verify(2) |
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X(1) |
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V |
IL |
Ai |
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V |
PP |
D |
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OUT |
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Optional PGM Verify(2) |
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V |
IL |
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V |
IL |
Ai |
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V |
CC |
D |
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OUT |
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PGM Inhibit(2) |
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VIH |
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VIH |
X(1) |
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VPP |
High Z |
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Product Identification(4) |
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A9 = VH(3) |
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V |
IL |
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IL |
A0 = V |
or V |
IL |
V |
CC |
Identification Code |
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IH |
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A1 - A14 = VIL |
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Notes: 1. X can be VIL or VIH.
2.Refer to Programming Characteristics.
3.VH = 12.0 ± 0.5V.
4.Two identifier bytes may be selected. All Ai inputs are held low (VIL), except A9 which is set to VH and A0 which is toggled low (VIL) to select the Manufacturer’s Identification byte and high (VIH) to select the Device Code byte.
7.DC and AC Operating Conditions for Read Operation
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AT27C256R |
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-45 |
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-70 |
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Operating Temp. (Case) |
Ind. |
-40°C - 85°C |
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-40°C - 85°C |
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Auto. |
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-40°C - 125°C |
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VCC Supply |
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5V ± 10% |
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5V ± 10% |
8. DC and Operating Characteristics for Read Operation
Symbol |
Parameter |
Condition |
Min |
Max |
Units |
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ILI |
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Input Load Current |
VIN |
= 0V to VCC |
Ind. |
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±1 |
µA |
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Auto. |
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±5 |
µA |
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ILO |
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Output Leakage Current |
VOUT = 0V to VCC |
Ind. |
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±5 |
µA |
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Auto. |
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±10 |
µA |
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I |
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(2) |
V |
(1) Read/Standby Current |
V |
= V |
CC |
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10 |
µA |
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PP1 |
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PP |
PP |
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ISB1 (CMOS), |
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= VCC ± 0.3V |
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100 |
µA |
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ISB |
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VCC(1) Standby Current |
CE |
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ISB2 (TTL), CE = 2.0 to VCC + 0.5V |
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mA |
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ICC |
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VCC Active Current |
f = 5 MHz, IOUT = 0 mA, |
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= VIL |
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20 |
mA |
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VIL |
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Input Low Voltage |
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-0.6 |
0.8 |
V |
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VIH |
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Input High Voltage |
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2.0 |
VCC + 0.5 |
V |
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VOL |
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Output Low Voltage |
IOL = 2.1 mA |
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0.4 |
V |
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VOH |
Output High Voltage |
IOH = -400 µA |
2.4 |
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V |
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Notes: 1. VCC must be applied simultaneously with or before VPP, and removed simultaneously with or after VPP..
2. VPP may be connected directly to VCC, except during programming. The supply current would then be the sum of ICC and IPP.
4 AT27C256R 
0014K–EPROM–10/05
AT27C256R
.
9. AC Characteristics for Read Operation
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AT27C256R |
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-45 |
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-70 |
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Symbol |
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Parameter |
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Condition |
Min |
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Max |
Min |
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Max |
Units |
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(1) |
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Address to Output Delay |
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CE = OE = VIL |
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45 |
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70 |
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tACC |
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(1) |
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CE to Output Delay |
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OE = VIL |
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45 |
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70 |
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tCE |
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(1) |
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OE to Output Delay |
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CE = VIL |
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20 |
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30 |
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tOE |
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or |
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High to Output |
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tDF(1) |
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OE |
CE |
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20 |
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25 |
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Float, Whichever Occurred First |
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Output Hold from Address, |
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or |
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tOH |
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CE |
OE, |
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7 |
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7 |
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Whichever Occurred First |
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Note: 1. |
See AC Waveforms for Read Operation. |
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10. AC Waveforms for Read Operation(1)
Notes: 1. Timing measurement reference level is 1.5V for -45 devices. Input AC drive levels are VIL = 0.0V and VIH = 3.0V. Timing measurement reference levels for all other speed grades are VOL = 0.8V and VOH = 2.0V. Input AC drive levels are VIL = 0.45V and VIH = 2.4V.
2.OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE.
3.OE may be delayed up to tACC - tOE after the address is valid without impact on tACC.
4.This parameter is only sampled and is not 100% tested.
5.Output float is defined as the point when data is no longer driven.
5
0014K–EPROM–10/05
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