– 135 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-Chip 2-cycle Multiplier
• Non-volatile Program and Data Memories
– 64K/128K/256K Bytes of In-System Self-Programmable Flash
Endurance: 10,000 Write/Erase Cycles
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– 4K Bytes EEPROM
Endurance: 100,000 Write/Erase Cycles
– 8K Bytes Internal SRAM
– Up to 64K Bytes Optional External Memory Space
– Programming Lock for Software Security
• JTAG (IEEE std. 1149.1 compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
• Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– Four 16-bit Timer/Counter with Separate Prescaler, Compare- and Capture Mode
– Real Time Counter with Separate Oscillator
– Four 8-bit PWM Channels
– Six/Twelve PWM Channels with Programmable Resolution from 2 to 16 Bits
(ATmega1281/2561, ATmega640/1280/2560)
– Output Compare Modulator
– 8/16-channel, 10-bit ADC (ATmega1281/2561, ATmega640/1280/2560)
– Two/Four Programmable Serial USART (ATmega1281/2561,ATmega640/1280/2560)
– Master/Slave SPI Serial Interface
– Byte Oriented 2-wire Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
• Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby,
Note:The large center pad underneath the QFN/MLF package is made of metal and internally
connected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen from the
board.
DisclaimerTypical values contained in this datasheet are based on simulations and characteriza-
tion of other AVR microcontrollers manufactured on the same process technology. Min.
and Max values will be available after the device is characterized.
4
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
ATmega640/1280/1281/2560/2561
Overview
The ATmega640/1280/1281/2560/2561 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC
architecture. By executing powerful instructions in a single clock cycle, the ATmega640/1280/1281/2560/2561 achieves
throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing
speed.
Block Diagram
Figure 4. Block Diagram
VCC
Powe r
RESET
GND
XTAL1
XTAL2
PA7..0
PG5..0PORT G (6)
Supervision
POR / BOD &
RESET
Watchdog
Timer
Watchdog
Oscillator
Oscillator
Circuits /
Clock
Generation
PORT A (8)
PF7..0
PORT F (8)
JTAG
EEPROM
XRAM
PK7..0
PORT K (8)
A/D
Converter
Internal
Bandgap reference
CPU
SRAMFLASH
PJ7..0
PORT J (8)
Analog
Comparator
16bit T/C 3
16bit T/C 5
16bit T/C 4
16bit T/C 1
PE7..0
PORT E (8)
USART 0
USART 3
USART 1
PC7..0PORT C (8)
2549K–AVR–01/07
NOTE:
Shaded parts only available
in the 100-pin version.
Complete functionality for
the ADC, T/C4, and T/C5 only
available in the 100-pin version.
TWISPI
PORT D (8)
PD7..0
PORT B (8)
PB7..0
8bit T/C 08bit T/C 2
PORT H (8)
PH7..0
USART 2
PORT L (8)
PL7..0
5
The AVR core combines a rich instruction set with 32 general purpose working registers.
All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing
two independent registers to be accessed in one single instruction executed in one clock
cycle. The resulting architecture is more code efficient while achieving throughputs up to
ten times faster than conventional CISC microcontrollers.
The ATmega640/1280/1281/2560/2561 provides the following features: 64K/128K/256K
bytes of In-System Programmable Flash with Read-While-Write capabilities, 4K bytes
EEPROM, 8K bytes SRAM, 54/86 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), six flexible Timer/Counters with compare
modes and PWM, 4 USARTs, a byte oriented 2-wire Serial Interface, a 16-channel, 10bit ADC with optional differential input stage with programmable gain, programmable
Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant
JTAG test interface, also used for accessing the On-chip Debug system and programming and six software selectable power saving modes. The Idle mode stops the CPU
while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue
functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In
Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction
mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator
Oscillator is running while the rest of the device is sleeping. This allows very fast start-up
combined with low power consumption. In Extended Standby mode, both the main
Oscillator and the Asynchronous Timer continue to run.
The device is manufactured using Atmel’s high-density nonvolatile memory technology.
The On-chip ISP Flash allows the program memory to be reprogrammed in-system
through an SPI serial interface, by a conventional nonvolatile memory programmer, or
by an On-chip Boot program running on the AVR core. The boot program can use any
interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is
updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU
with In-System Self-Programmable Flash on a monolithic chip, the Atmel
ATmega640/1280/1281/2560/2561 is a powerful microcontroller that provides a highly
flexible and cost effective solution to many embedded control applications.
The ATmega640/1280/1281/2560/2561 AVR is supported with a full suite of program
and system development tools including: C compilers, macro assemblers, program
debugger/simulators, in-circuit emulators, and evaluation kits.
6
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
ATmega640/1280/1281/2560/2561
Comparison Between ATmega1281/2561 and ATmega640/1280/2560
Each device in the ATmega640/1280/1281/2560/2561 family differs only in memory size
and number of pins. Table 2 summarizes the different configurations for the six devices.
Table 2. Configuration Summary
General
DeviceFlashEEPROMRAM
ATmega64064KB4KB8KB8612416
ATmega1280128KB4KB8KB8612416
ATmega1281128KB4KB8KB54628
ATmega2560256KB4KB8KB8612416
ATmega2561256KB4KB8KB54628
Purpose I/O pins
16 bits resolution
PWM channels
Serial
USARTs
ADC
Channels
Pin Descriptions
VCCDigital supply voltage.
GNDGround.
Port A (PA7..PA0)Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port A output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port A pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port A also serves the functions of various special features of the
ATmega640/1280/1281/2560/2561 as listed on page 91.
Port B (PB7..PB0)Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port B output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port B pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port B has better driving capabilities than the other ports.
Port B also serves the functions of various special features of the
ATmega640/1280/1281/2560/2561 as listed on page 92.
Port C (PC7..PC0)Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port C output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port C pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port C also serves the functions of special features of the
ATmega640/1280/1281/2560/2561 as listed on page 95.
Port D (PD7..PD0)Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port D output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port D pins that are externally pulled low will source
2549K–AVR–01/07
7
current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port D also serves the functions of various special features of the
ATmega640/1280/1281/2560/2561 as listed on page 97.
Port E (PE7..PE0)Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port E output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port E pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port E also serves the functions of various special features of the
ATmega640/1280/1281/2560/2561 as listed on page 99.
Port F (PF7..PF0)Port F serves as analog inputs to the A/D Converter.
Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used.
Port pins can provide internal pull-up resistors (selected for each bit). The Port F output
buffers have symmetrical drive characteristics with both high sink and source capability.
As inputs, Port F pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port F pins are tri-stated when a reset condition becomes
active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset
occurs.
Port F also serves the functions of the JTAG interface.
Port G (PG5..PG0)Port G is a 6-bit I/O port with internal pull-up resistors (selected for each bit). The Port G
output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port G pins that are externally pulled low will source current if the
pull-up resistors are activated. The Port G pins are tri-stated when a reset condition
becomes active, even if the clock is not running.
Port G also serves the functions of various special features of the
ATmega640/1280/1281/2560/2561 as listed on page 105.
Port H (PH7..PH0)Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port H output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port H pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port H pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port H also serves the functions of various special features of the
ATmega640/1280/2560 as listed on page 107.
Port J (PJ7..PJ0)Port J is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port J output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port J pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port J pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port J also serves the functions of various special features of the
ATmega640/1280/2560 as listed on page 109.
Port K (PK7..PK0)Port K serves as analog inputs to the A/D Converter.
8
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
ATmega640/1280/1281/2560/2561
Port K is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port K output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port K pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port K pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port K also serves the functions of various special features of the
ATmega640/1280/2560 as listed on page 111.
Port L (PL7..PL0)Port L is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port L output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port L pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port L pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port L also serves the functions of various special features of the
ATmega640/1280/2560 as listed on page 113.
RESET
XTAL1Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
XTAL2Output from the inverting Oscillator amplifier.
AVCCAVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally
AREFThis is the analog reference pin for the A/D Converter.
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table
26 on page 58. Shorter pulses are not guaranteed to generate a reset.
connected to V
nected to V
, even if the ADC is not used. If the ADC is used, it should be con-
CC
through a low-pass filter.
CC
Resources
A comprehensive set of development tools and application notes, and datasheets are
available for download on http://www.atmel.com/avr.
About Code Examples
This documentation contains simple code examples that briefly show how to use various
parts of the device. Be aware that not all C compiler vendors include bit definitions in the
header files and interrupt handling in C is compiler dependent. Please confirm with the
C compiler documentation for more details.
2549K–AVR–01/07
These code examples assume that the part specific header file is included before compilation. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC",
"CBI", and "SBI" instructions must be replaced with instructions that allow access to
extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and
"CBR".
9
AVR CPU Core
IntroductionThis section discusses the AVR core architecture in general. The main function of the
CPU core is to ensure correct program execution. The CPU must therefore be able to
access memories, perform calculations, control peripherals, and handle interrupts.
Architectural OverviewFigure 5. Block Diagram of the AVR Architecture
Data Bus 8-bit
Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Control Lines
Program
Counter
Direct Addressing
Status
and Control
32 x 8
General
Purpose
Registrers
ALU
Indirect Addressing
Data
SRAM
EEPROM
Interrupt
Unit
SPI
Unit
Watchdog
Timer
Analog
Comparator
I/O Module1
I/O Module 2
I/O Module n
10
I/O Lines
In order to maximize performance and parallelism, the AVR uses a Harvard architecture
– with separate memories and buses for program and data. Instructions in the program
memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept
enables instructions to be executed in every clock cycle. The program memory is InSystem Reprogrammable Flash memory.
The fast-access Register File contains 32 x 8-bit general purpose working registers with
a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU)
operation. In a typical ALU operation, two operands are output from the Register File,
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
ATmega640/1280/1281/2560/2561
the operation is executed, and the result is stored back in the Register File – in one
clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for
Data Space addressing – enabling efficient address calculations. One of the these
address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register,
described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After
an arithmetic operation, the Status Register is updated to reflect information about the
result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions,
able to directly address the whole address space. Most AVR instructions have a single
16-bit word format. Every program memory address contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot Program section and
the Application Program section. Both sections have dedicated Lock bits for write and
read/write protection. The SPM instruction that writes into the Application Flash memory
section must reside in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is
stored on the Stack. The Stack is effectively allocated in the general data SRAM, and
consequently the Stack size is only limited by the total SRAM size and the usage of the
SRAM. All user programs must initialize the SP in the Reset routine (before subroutines
or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O
space. The data SRAM can easily be accessed through the five different addressing
modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional
Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt
Vector in the Interrupt Vector table. The interrupts have priority in accordance with their
Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control
Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as
the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition,
the ATmega640/1280/1281/2560/2561 has Extended I/O space from 0x60 - 0x1FF in
SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.
ALU – Arithmetic Logic
Unit
The high-performance AVR ALU operates in direct connection with all the 32 general
purpose working registers. Within a single clock cycle, arithmetic operations between
general purpose registers or between a register and an immediate are executed. The
ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier
supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.
Status RegisterThe Status Register contains information about the result of the most recently executed
arithmetic instruction. This information can be used for altering program flow in order to
perform conditional operations. Note that the Status Register is updated after all ALU
operations, as specified in the Instruction Set Reference. This will in many cases
2549K–AVR–01/07
11
remove the need for using the dedicated compare instructions, resulting in faster and
more compact code.
The Status Register is not automatically stored when entering an interrupt routine and
restored when returning from an interrupt. This must be handled by software.
SREG – AVR Status RegisterThe AVR Status Register – SREG – is defined as:
Bit76543210
0x3F (0x5F)ITHSVNZCSREG
Read/WriteR/WR/WR/WR/WR/WR/WR/WR/W
Initial Value00000000
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global
Interrupt Enable Register is cleared, none of the interrupts are enabled independent of
the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt
has occurred, and is set by the RETI instruction to enable subsequent interrupts. The Ibit can also be set and cleared by the application with the SEI and CLI instructions, as
described in the instruction set reference.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or
destination for the operated bit. A bit from a register in the Register File can be copied
into T by the BST instruction, and a bit in T can be copied into a bit in a register in the
Register File by the BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is
useful in BCD arithmetic. See the “Instruction Set Description” for detailed information.
• Bit 4 – S: Sign Bit, S = N
⊕ V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See
the “Instruction Set Description” for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See
the “Instruction Set Description” for detailed information.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the
“Instruction Set Description” for detailed information.
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.
12
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
ATmega640/1280/1281/2560/2561
General Purpose
Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to
achieve the required performance and flexibility, the following input/output schemes are
supported by the Register File:
•One 8-bit output operand and one 8-bit result input
•Two 8-bit output operands and one 8-bit result input
•Two 8-bit output operands and one 16-bit result input
•One 16-bit output operand and one 16-bit result input
Figure 6 shows the structure of the 32 general purpose working registers in the CPU.
Figure 6. AVR CPU General Purpose Working Registers
70Addr.
R0 0x00
R10x01
R20x02
…
R130x0D
GeneralR140x0E
PurposeR150x0F
WorkingR160x10
RegistersR170x11
…
R260x1AX-register Low Byte
R270x1BX-register High Byte
R280x1CY-register Low Byte
R290x1DY-register High Byte
R300x1EZ-register Low Byte
R310x1FZ-register High Byte
Most of the instructions operating on the Register File have direct access to all registers,
and most of them are single cycle instructions.
As shown in Figure 6 on page 13, each register is also assigned a data memory
address, mapping them directly into the first 32 locations of the user Data Space.
Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer
registers can be set to index any register in the file.
2549K–AVR–01/07
13
The X-register, Y-register, and
Z-register
The registers R26..R31 have some added functions to their general purpose usage.
These registers are 16-bit address pointers for indirect addressing of the data space.
The three indirect address registers X, Y, and Z are defined as described in Figure 7.
Figure 7. The X-, Y-, and Z-registers
15XHXL0
X-register7070
R27 (0x1B)R26 (0x1A)
15YHYL0
Y-register7070
R29 (0x1D)R28 (0x1C)
15ZHZL0
Z-register7070
R31 (0x1F)R30 (0x1E)
In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set
reference for details).
Stack PointerThe Stack is mainly used for storing temporary data, for storing local variables and for
storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing
from higher memory locations to lower memory locations. This implies that a Stack
PUSH command decreases the Stack Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the
program before any subroutine calls are executed or interrupts are enabled. The Stack
Pointer must be set to point above 0x0200. The initial value of the stack pointer is the
last address of the internal SRAM. The Stack Pointer is decremented by one when data
is pushed onto the Stack with the PUSH instruction, and it is decremented by two for
ATmega640/1280/1281 and three for ATmega2560/2561 when the return address is
pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is
incremented by two for ATmega640/1280/1281 and three for ATmega2560/2561 when
data is popped from the Stack with return from subroutine RET or return from interrupt
RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some
implementations of the AVR architecture is so small that only SPL is needed. In this
case, the SPH Register will not be present.
Bit151413121110 9 8
0x3E (0x5E)SP15SP14SP13SP12SP11SP10SP9SP8SPH
0x3D (0x5D)SP7SP6SP5SP4SP3SP2SP1SP0SPL
76543210
Read/WriteR/WR/WR/WR/WR/WR/WR/WR/W
R/WR/WR/WR/WR/WR/WR/WR/W
Initial Value00100001
11111111
14
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
RAMPZ – Extended Z-pointer
Register for ELPM/SPM
ATmega640/1280/1281/2560/2561
Bit765432 1 0
0x3B (0x5B)
Read/WriteR/WR/WR/WR/WR/WR/WR/WR/W
Initial Value000000 0 0
For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as
shown in Figure 8. Note that LPM is not affected by the RAMPZ setting.
Figure 8. The Z-pointer used by ELPM and SPM
RAMPZ7RAMPZ6RAMPZ5RAMPZ4RAMPZ3RAMPZ2RAMPZ1RAMPZ0
RAMPZ
EIND – Extended Indirect
Register
Bit (
Individually)
Bit (Z-pointer)231615870
707070
RAMPZZHZL
The actual number of bits is implementation dependent. Unused bits in an implementation will always read as zero. For compatibility with future devices, be sure to write these
bits to zero.
For EICALL/EIJMP instructions, the Indirect-pointer to the subroutine/routine is a concatenation of EIND, ZH, and ZL, as shown in Figure 9. Note that ICALL and IJMP are
not affected by the EIND setting.
Figure 9. The Indirect-pointer used by EICALL and EIJMP
Bit (Individually)
Bit (Indirectpointer)
707070
EINDZHZL
231615870
2549K–AVR–01/07
The actual number of bits is implementation dependent. Unused bits in an implementation will always read as zero. For compatibility with future devices, be sure to write these
bits to zero.
15
Instruction Execution
Timing
This section describes the general access timing concepts for instruction execution. The
AVR CPU is driven by the CPU clock clk
, directly generated from the selected clock
CPU
source for the chip. No internal clock division is used.
Figure 10 shows the parallel instruction fetches and instruction executions enabled by
the Harvard architecture and the fast-access Register File concept. This is the basic
pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results
for functions per cost, functions per clocks, and functions per power-unit.
Figure 10. The Parallel Instruction Fetches and Instruction Executions
T1T2T3T4
clk
CPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 11 shows the internal timing concept for the Register File. In a single clock cycle
an ALU operation using two register operands is executed, and the result is stored back
to the destination register.
Figure 11. Single Cycle ALU Operation
T1T2T3T4
clk
CPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
16
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
ATmega640/1280/1281/2560/2561
Reset and Interrupt
Handling
The AVR provides several different interrupt sources. These interrupts and the separate
Reset Vector each have a separate program vector in the program memory space. All
interrupts are assigned individual enable bits which must be written logic one together
with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt.
Depending on the Program Counter value, interrupts may be automatically disabled
when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software
security. See the section “Memory Programming” on page 342 for details.
The lowest addresses in the program memory space are by default defined as the Reset
and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 69.
The list also determines the priority levels of the different interrupts. The lower the
address the higher is the priority level. RESET has the highest priority, and next is INT0
– the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of
the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR).
Refer to “Interrupts” on page 69 for more information. The Reset Vector can also be
moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see
“Memory Programming” on page 342.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts
are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is
automatically set when a Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that
sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the
actual Interrupt Vector in order to execute the interrupt handling routine, and hardware
clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a
logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the
corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or
more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt
Enable bit is set, and will then be executed by order of priority.
2549K–AVR–01/07
The second type of interrupts will trigger as long as the interrupt condition is present.
These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by
software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately
disabled. No interrupt will be executed after the CLI instruction, even if it occurs simulta-
17
neously with the CLI instruction. The following example shows how this can be used to
avoid interrupts during the timed EEPROM write sequence.
Assembly Code Example
in r16, SREG; store SREG value
cli ; disable interrupts during timed sequence
sbi EECR, EEMPE; start EEPROM write
sbi EECR, EEPE
out SREG, r16; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
__disable_interrupt();
EECR |= (1<<EEMPE); /* start EEPROM write */
EECR |= (1<<EEPE);
SREG = cSREG; /* restore SREG value (I-bit) */
When using the SEI instruction to enable interrupts, the instruction following SEI will be
executed before any pending interrupts, as shown in this example.
Assembly Code Example
sei; set Global Interrupt Enable
sleep ; enter sleep, waiting for interrupt
; note: will enter sleep before any pending
; interrupt(s)
C Code Example
__enable_interrupt(); /* set Global Interrupt Enable */
__sleep(); /*enter sleep, waiting for interrupt */
/* note: will enter sleep before any pending interrupt(s) */
Interrupt Response TimeThe interrupt execution response for all the enabled AVR interrupts is five clock cycles
minimum. After five clock cycles the program vector address for the actual interrupt handling routine is executed. During these five clock cycle period, the Program Counter is
pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this
jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle
instruction, this instruction is completed before the interrupt is served. If an interrupt
occurs when the MCU is in sleep mode, the interrupt execution response time is
increased by five clock cycles. This increase comes in addition to the start-up time from
the selected sleep mode.
A return from an interrupt handling routine takes five clock cycles. During these five
clock cycles, the Program Counter (three bytes) is popped back from the Stack, the
Stack Pointer is incremented by three, and the I-bit in SREG is set.
18
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
AVR Memor ies
ATmega640/1280/1281/2560/2561
This section describes the different memories in the ATmega640/1280/1281/2560/2561.
The AVR architecture has two main memory spaces, the Data Memory and the Program
Memory space. In addition, the ATmega640/1280/1281/2560/2561 features an
EEPROM Memory for data storage. All three memory spaces are linear and regular.
In-System
Reprogrammable Flash
Program Memory
The ATmega640/1280/1281/2560/2561 contains 64K/128K/256K bytes On-chip In-System Reprogrammable Flash memory for program storage, see Table 3 on page 19.
Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as
32K/64K/128K x 16. For software security, the Flash Program memory space is divided
into two sections, Boot Program section and Application Program section.
The Flash memory has an endurance of at least 10,000 write/erase cycles. The
ATmega640/1280/1281/2560/2561 Program Counter (PC) is 15/16/17 bits wide, thus
addressing the 32K/64K/128K program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in
detail in “Boot Loader Support – Read-While-Write Self-Programming” on page 323.
“Memory Programming” on page 342 contains a detailed description on Flash data
serial downloading using the SPI pins or the JTAG interface.
Constant tables can be allocated within the entire program memory address space (see
the LPM – Load Program Memory instruction description and ELPM - Extended Load
Program Memory instruction description).
Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Timing” on page 16.
Table 3. Program Flash Memory Map
Address (HEX)
0
Application Flash Section
2549K–AVR–01/07
0x7FFF/0xFFFF/0x1FFFF
Boot Flash Section
19
SRAM Data MemoryTable 4 on page 21 shows how the ATmega640/1280/1281/2560/2561 SRAM Memory
is organized.
The ATmega640/1280/1281/2560/2561 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in the Opcode for the IN
and OUT instructions. For the Extended I/O space from $060 - $1FF in SRAM, only the
ST/STS/STD and LD/LDS/LDD instructions can be used.
The first 4,608/8,704 Data Memory locations address both the Register File, the I/O
Memory, Extended I/O Memory, and the internal data SRAM. The first 32 locations
address the Register file, the next 64 location the standard I/O Memory, then 416 locations of Extended I/O memory and the next 8,192 locations address the internal data
SRAM.
An optional external data SRAM can be used with the
ATmega640/1280/1281/2560/2561. This SRAM will occupy an area in the remaining
address locations in the 64K address space. This area starts at the address following
the internal SRAM. The Register file, I/O, Extended I/O and Internal SRAM occupies the
lowest 4,608/8,704 bytes, so when using 64KB (65,536 bytes) of External Memory,
60,478/56,832 Bytes of External Memory are available. See “External Memory Interface” on page 26 for details on how to take advantage of the external memory map.
When the addresses accessing the SRAM memory space exceeds the internal data
memory locations, the external data SRAM is accessed using the same instructions as
for the internal data memory access. When the internal data memories are accessed,
the read and write strobe pins (PG0 and PG1) are inactive during the whole access
cycle. External SRAM operation is enabled by setting the SRE bit in the XMCRA
Register.
Accessing external SRAM takes one additional clock cycle per byte compared to access
of the internal SRAM. This means that the commands LD, ST, LDS, STS, LDD, STD,
PUSH, and POP take one additional clock cycle. If the Stack is placed in external
SRAM, interrupts, subroutine calls and returns take three clock cycles extra because the
three-byte program counter is pushed and popped, and external memory access does
not take advantage of the internal pipe-line memory access. When external SRAM interface is used with wait-state, one-byte external access takes two, three, or four additional
clock cycles for one, two, and three wait-states respectively. Interrupts, subroutine calls
and returns will need five, seven, or nine clock cycles more than specified in the instruction set manual for one, two, and three wait-states.
The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In
the Register file, registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base
address given by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and postincrement, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O registers, and the 4,196/8,192 bytes of
internal data SRAM in the ATmega640/1280/1281/2560/2561 are all accessible through
20
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
ATmega640/1280/1281/2560/2561
all these addressing modes. The Register File is described in “General Purpose Register File” on page 13.
Table 4. Data Memory Map
Address (HEX)
0 - 1F32 Registers
20 - 5F64 I/O Registers
60 - 1FF
200
21FF
2200
FFFF
416 External I/O Registers
Internal SRAM
(8192 x 8)
External SRAM
(0 - 64K x 8)
Data Memory Access TimesThis section describes the general access timing concepts for internal memory access.
The internal data SRAM access is performed in two clk
cycles as described in Figure
CPU
12.
Figure 12. On-chip Data SRAM Access Cycles
T1T2T3
clk
CPU
Address
Compute Address
Address valid
Data
WR
Write
2549K–AVR–01/07
Data
RD
Memory Access Instruction
Read
Next Instruction
21
EEPROM Data MemoryThe ATmega640/1280/1281/2560/2561 contains 4K bytes of data EEPROM memory. It
is organized as a separate data space, in which single bytes can be read and written.
The EEPROM has an endurance of at least 100,000 write/erase cycles. The access
between the EEPROM and the CPU is described in the following, specifying the
EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control
Register.
For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM,
see “Serial Downloading” on page 356, “Programming via the JTAG Interface” on page
361, and “Programming the EEPROM” on page 350 respectively.
EEPROM Read/Write AccessThe EEPROM Access Registers are accessible in the I/O space, see “Register Descrip-
tion” on page 32.
The write access time for the EEPROM is given in Table 5 on page 22. A self-timing
function, however, lets the user software detect when the next byte can be written. If the
user code contains instructions that write the EEPROM, some precautions must be
taken. In heavily filtered power supplies, V
up/down. This causes the device for some period of time to run at a voltage lower than
specified as minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page 24. for details on how to avoid problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. See the description of the EEPROM Control Register for details on this, “Register
Description” on page 32.
When the EEPROM is read, the CPU is halted for four clock cycles before the next
instruction is executed. When the EEPROM is written, the CPU is halted for two clock
cycles before the next instruction is executed.
is likely to rise or fall slowly on power-
CC
The calibrated Oscillator is used to time the EEPROM accesses. Table 5 lists the typical
programming time for EEPROM access from the CPU.
Table 5. EEPROM Programming Time
SymbolNumber of Calibrated RC Oscillator CyclesTyp Programming Time
EEPROM write
(from CPU)
The following code examples show one assembly and one C function for writing to the
EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The
examples also assume that no Flash Boot Loader is present in the software. If such
code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.
26,3683.3 ms
22
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
ATmega640/1280/1281/2560/2561
Assembly Code Example
EEPROM_write:
; Wait for completion of previous write
sbic EECR,EEPE
rjmp EEPROM_write
; Set up address (r18:r17) in address register
out EEARH, r18
out EEARL, r17
; Write data (r16) to Data Register
out EEDR,r16
; Write logical one to EEMPE
sbi EECR,EEMPE
; Start eeprom write by setting EEPE
sbi EECR,EEPE
ret
C Code Example
void EEPROM_write(unsigned int uiAddress, unsigned char ucData)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEPE))
;
/* Set up address and Data Registers */
EEAR = uiAddress;
EEDR = ucData;
/* Write logical one to EEMPE */
EECR |= (1<<EEMPE);
/* Start eeprom write by setting EEPE */
EECR |= (1<<EEPE);
}
(1)
()
2549K–AVR–01/07
Note:1. See “About Code Examples” on page 9.
23
The next code examples show assembly and C functions for reading the EEPROM. The
examples assume that interrupts are controlled so that no interrupts will occur during
execution of these functions.
Assembly Code Example
EEPROM_read:
; Wait for completion of previous write
sbic EECR,EEPE
rjmp EEPROM_read
; Set up address (r18:r17) in address register
out EEARH, r18
out EEARL, r17
; Start eeprom read by writing EERE
sbi EECR,EERE
; Read data from Data Register
in r16,EEDR
ret
C Code Example
unsigned char EEPROM_read(unsigned int uiAddress)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEPE))
;
/* Set up address register */
EEAR = uiAddress;
/* Start eeprom read by writing EERE */
EECR |= (1<<EERE);
/* Return data from Data Register */
return EEDR;
}
(1)
(1)
Preventing EEPROM
Corruption
24
ATmega640/1280/1281/2560/2561
Note:1. See “About Code Examples” on page 9.
During periods of low V
the EEPROM data can be corrupted because the supply volt-
CC,
age is too low for the CPU and the EEPROM to operate properly. These issues are the
same as for board level systems using EEPROM, and the same design solutions should
be applied.
An EEPROM data corruption can be caused by two situations when the voltage is too
low. First, a regular write sequence to the EEPROM requires a minimum voltage to
operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the
supply voltage is too low.
EEPROM data corruption can easily be avoided by following this design
recommendation:
Keep the AVR RESET active (low) during periods of insufficient power supply voltage.
This can be done by enabling the internal Brown-out Detector (BOD). If the detection
level of the internal BOD does not match the needed detection level, an external low
V
reset Protection circuit can be used. If a reset occurs while a write operation is in
CC
progress, the write operation will be completed provided that the power supply voltage is
sufficient.
2549K–AVR–01/07
ATmega640/1280/1281/2560/2561
I/O MemoryThe I/O space definition of the ATmega640/1280/1281/2560/2561 is shown in “Register
Summary” on page 416.
All ATmega640/1280/1281/2560/2561 I/Os and peripherals are placed in the I/O space.
All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions,
transferring data between the 32 general purpose working registers and the I/O space.
I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the
SBI and CBI instructions. In these registers, the value of single bits can be checked by
using the SBIS and SBIC instructions. Refer to the instruction set section for more
details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 0x3F must be used. When addressing I/O Registers as data space using LD and ST
instructions, 0x20 must be added to these addresses. The
ATmega640/1280/1281/2560/2561 is a complex microcontroller with more peripheral
units than can be supported within the 64 location reserved in Opcode for the IN and
OUT instructions. For the Extended I/O space from 0x60 - 0x1FF in SRAM, only the
ST/STS/STD and LD/LDS/LDD instructions can be used.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike
most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and
can therefore be used on registers containing such Status Flags. The CBI and SBI
instructions work with registers 0x00 to 0x1F only.
The I/O and peripherals control registers are explained in later sections.
General Purpose I/O Registers The ATmega640/1280/1281/2560/2561 contains three General Purpose I/O Registers.
These registers can be used for storing any information, and they are particularly useful
for storing global variables and Status Flags. General Purpose I/O Registers within the
address range 0x00 - 0x1F are directly bit-accessible using the SBI, CBI, SBIS, and
SBIC instructions. See “Register Description” on page 32.
2549K–AVR–01/07
25
External Memory
Interface
With all the features the External Memory Interface provides, it is well suited to operate
as an interface to memory devices such as External SRAM and Flash, and peripherals
such as LCD-display, A/D, and D/A. The main features are:
•
Four different wait-state settings (including no wait-state).
• Independent wait-state setting for different External Memory sectors (configurable sector
size)
• The number of bits dedicated to address high byte is selectable
• Bus keepers on data lines to minimize current consumption (optional)
OverviewWhen the eXternal MEMory (XMEM) is enabled, address space outside the internal
SRAM becomes available using the dedicated External Memory pins (see Figure 3 on
page 4, Table 39 on page 91, Table 45 on page 95, and Table 57 on page 105). The
memory configuration is shown in Figure 13.
Figure 13. External Memory with Sector Select
Memory Configuration A
0x0000
Internal memory
0x21FF
Lower sector
SRW01
SRW00
0x2200
Using the External Memory
Interface
SRL[2..0]
External Memory
(0-60K x 8)
Upper sector
SRW11
SRW10
0xFFFF
The interface consists of:
•AD7:0: Multiplexed low-order address bus and data bus.
•A15:8: High-order address bus (configurable number of bits).
•ALE: Address latch enable.
•RD
•WR
: Read strobe.
: Write strobe.
The control bits for the External Memory Interface are located in two registers, the External Memory Control Register A – XMCRA, and the External Memory Control Register B
– XMCRB.
When the XMEM interface is enabled, the XMEM interface will override the setting in the
data direction registers that corresponds to the ports dedicated to the XMEM interface.
26
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
ATmega640/1280/1281/2560/2561
For details about the port override, see the alternate functions in section “I/O-Ports” on
page 83. The XMEM interface will auto-detect whether an access is internal or external.
If the access is external, the XMEM interface will output address, data, and the control
signals on the ports according to Figure 15 (this figure shows the wave forms without
wait-states). When ALE goes from high-to-low, there is a valid address on AD7:0. ALE is
low during a data transfer. When the XMEM interface is enabled, also an internal access
will cause activity on address, data and ALE ports, but the RD
toggle during internal access. When the External Memory Interface is disabled, the normal pin and data direction settings are used. Note that when the XMEM interface is
disabled, the address space above the internal SRAM boundary is not mapped into the
internal SRAM. Figure 14 illustrates how to connect an external SRAM to the AVR using
an octal latch (typically “74 x 573” or equivalent) which is transparent when G is high.
Address Latch RequirementsDue to the high-speed operation of the XRAM interface, the address latch must be
selected with care for system frequencies above 8 MHz @ 4V and 4 MHz @ 2.7V.
When operating at conditions above these frequencies, the typical old style 74HC series
latch becomes inadequate. The External Memory Interface is designed in compliance to
the 74AHC series latch. However, most latches can be used as long they comply with
the main timing parameters. The main parameters for the address latch are:
•D to Q propagation delay (t
•Data setup time before G low (t
•Data (address) hold time after G low (
PD
).
).
SU
).
TH
The External Memory Interface is designed to guaranty minimum address hold time
after G is asserted low of t
= 5 ns. Refer to t
h
LAXX_LD/tLLAXX_ST
Timing” Tables 173 through Tables 180 on pages 385 - 387. The D-to-Q propagation
delay (t
) must be taken into consideration when calculating the access time require-
PD
ment of the external component. The data setup time before G low (t
exceed address valid to ALE low (t
) minus PCB wiring delay (dependent on the
AVLLC
capacitive load).
and WR strobes will not
in “External Data Memory
) must not
SU
Figure 14. External SRAM Connected to the AVR
AVR
AD7:0
ALE
A15:8
RD
WR
DQ
G
SRAM
D[7:0]
A[7:0]
A[15:8]
RD
WR
2549K–AVR–01/07
27
Pull-up and Bus-keeperThe pull-ups on the AD7:0 ports may be activated if the corresponding Port register is
written to one. To reduce power consumption in sleep mode, it is recommended to disable the pull-ups by writing the Port register to zero before entering sleep.
The XMEM interface also provides a bus-keeper on the AD7:0 lines. The bus-keeper
can be disabled and enabled in software as described in “XMCRB – External Memory
Control Register B” on page 36. When enabled, the bus-keeper will keep the previous
value on the AD7:0 bus while these lines are tri-stated by the XMEM interface.
TimingExternal Memory devices have different timing requirements. To meet these require-
ments, the XMEM interface provides four different wait-states as shown in Table 8. It is
important to consider the timing specification of the External Memory device before
selecting the wait-state. The most important parameters are the access time for the
external memory compared to the set-up requirement. The access time for the External
Memory is defined to be the time from receiving the chip select/address until the data of
this address actually is driven on the bus. The access time cannot exceed the time from
the ALE pulse must be asserted low until data is stable during a read sequence (See
t
LLRL
+ t
RLRH
- t
in Tables 173 through Tables 180 on pages 385 - 387). The different
DVRH
wait-states are set up in software. As an additional feature, it is possible to divide the
external memory space in two sectors with individual wait-state settings. This makes it
possible to connect two different memory devices with different timing requirements to
the same XMEM interface. For XMEM interface timing details, please refer to Table 173
to Table 180 and Figure 163 to Figure 166 in the “External Data Memory Timing” on
page 385.
Note that the XMEM interface is asynchronous and that the waveforms in the following
figures are related to the internal system clock. The skew between the internal and
external clock (XTAL1) is not guarantied (varies between devices temperature, and supply voltage). Consequently, the XMEM interface is not suited for synchronous operation.
Figure 15. External Data Memory Cycles without Wait-state (SRWn1=0 and SRWn0=0)
sector) or SRW00 (lower sector).
The ALE pulse in period T7 is only present if the next instruction accesses the RAM
(internal or external).
Since the external memory is mapped after the internal memory as shown in Figure 13,
the external memory is not addressed when addressing the first 8,704 bytes of data
space. It may appear that the first 8,704 bytes of the external memory are inaccessible
(external memory addresses 0x0000 to 0x21FF). However, when connecting an external memory smaller than 64 KB, for example 32 KB, these locations are easily accessed
simply by addressing from address 0x8000 to 0xA1FF. Since the External Memory
Address bit A15 is not connected to the external memory, addresses 0x8000 to 0xA1FF
will appear as addresses 0x0000 to 0x21FF for the external memory. Addressing above
address 0xA1FF is not recommended, since this will address an external memory location that is already accessed by another (lower) address. To the Application software,
the external 32 KB memory will appear as one linear 32 KB address space from 0x2200
to 0xA1FF. This is illustrated in Figure 19.
Write
Read
30
Figure 19. Address Map with 32 KB External Memory
AVR Memory Map
0x0000
Internal Memory
0x21FF
0x2200
0x7FFF
0x8000
External
Memory
0x90FF
0x9100
ATmega640/1280/1281/2560/2561
External 32K SRAM
0x0000
0x7FFF
2549K–AVR–01/07
ATmega640/1280/1281/2560/2561
Using all 64KB Locations of
External Memory
Since the External Memory is mapped after the Internal Memory as shown in Figure 13,
only 56KB of External Memory is available by default (address space 0x0000 to 0x21FF
is reserved for internal memory). However, it is possible to take advantage of the entire
External Memory by masking the higher address bits to zero. This can be done by using
the XMMn bits and control by software the most significant bits of the address. By setting Port C to output 0x00, and releasing the most significant bits for normal Port Pin
operation, the Memory Interface will address 0x0000 - 0x2FFF. See the following code
examples.
Care must be exercised using this option as most of the memory is masked away.
Assembly Code Example
; OFFSET is defined to 0x4000 to ensure
; external memory access
; Configure Port C (address high byte) to
; output 0x00 when the pins are released
; for normal Port Pin operation
These bits are reserved bits and will always read as zero.
• Bits 11:0 – EEAR8:0: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address
in the 4K bytes EEPROM space. The EEPROM data bytes are addressed linearly
between 0 and 4096. The initial value of EEAR is undefined. A proper value must be
written before the EEPROM may be accessed.
Bit76543210
0x20 (0x40)MSBLSBEEDR
Read/WriteR/WR/WR/WR/WR/WR/WR/WR/W
Initial Value00000000
EECR – The EEPROM Control
Register
• Bits 7:0 – EEDR7:0: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to
the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by
EEAR.
Bit76543210
0x1F (0x3F)––EEPM1EEPM0EERIEEEMPEEEPEEEREEECR
Read/WriteRRR/WR/WR/WR/WR/WR/W
Initial Value00XX00X0
• Bits 7:6 – Res: Reserved Bits
These bits are reserved bits and will always read as zero.
The EEPROM Programming mode bit setting defines which programming action that will
be triggered when writing EEPE. It is possible to program data in one atomic operation
(erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are
shown in Table 6. While EEPE is set, any write to EEPMn will be ignored. During reset,
the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.
32
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
ATmega640/1280/1281/2560/2561
Table 6. EEPROM Mode Bits
Programming
EEPM1EEPM0
003.4 msErase and Write in one operation (Atomic Operation)
011.8 msErase Only
101.8 msWrite Only
11–Reserved for future use
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set.
Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a
constant interrupt when EEPE is cleared.
• Bit 2 – EEMPE: EEPROM Master Programming Enable
The EEMPE bit determines whether setting EEPE to one causes the EEPROM to be
written. When EEMPE is set, setting EEPE within four clock cycles will write data to the
EEPROM at the selected address If EEMPE is zero, setting EEPE will have no effect.
When EEMPE has been written to one by software, hardware clears the bit to zero after
four clock cycles. See the description of the EEPE bit for an EEPROM write procedure.
• Bit 1 – EEPE: EEPROM Programming Enable
TimeOperation
The EEPROM Write Enable Signal EEPE is the write strobe to the EEPROM. When
address and data are correctly set up, the EEPE bit must be written to one to write the
value into the EEPROM. The EEMPE bit must be written to one before a logical one is
written to EEPE, otherwise no EEPROM write takes place. The following procedure
should be followed when writing the EEPROM (the order of steps 3 and 4 is not
essential):
1.Wait until EEPE becomes zero.
2.Wait until SPMEN in SPMCSR becomes zero.
3.Write new EEPROM address to EEAR (optional).
4.Write new EEPROM data to EEDR (optional).
5.Write a logical one to the EEMPE bit while writing a zero to EEPE in EECR.
6.Within four clock cycles after setting EEMPE, write a logical one to EEPE.
The EEPROM can not be programmed during a CPU write to the Flash memory. The
software must check that the Flash programming is completed before initiating a new
EEPROM write. Step 2 is only relevant if the software contains a Boot Loader allowing
the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2
can be omitted. See “Memory Programming” on page 342 for details about Boot
programming.
Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the
EEPROM Master Write Enable will time-out. If an interrupt routine accessing the
EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be
modified, causing the interrupted EEPROM access to fail. It is recommended to have
the Global Interrupt Flag cleared during all the steps to avoid these problems.
2549K–AVR–01/07
When the write access time has elapsed, the EEPE bit is cleared by hardware. The user
software can poll this bit and wait for a zero before writing the next byte. When EEPE
has been set, the CPU is halted for two cycles before the next instruction is executed.
33
General Purpose registers
• Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the
correct address is set up in the EEAR Register, the EERE bit must be written to a logic
one to trigger the EEPROM read. The EEPROM read access takes one instruction, and
the requested data is available immediately. When the EEPROM is read, the CPU is
halted for four cycles before the next instruction is executed.
The user should poll the EEPE bit before starting the read operation. If a write operation
is in progress, it is neither possible to read the EEPROM, nor to change the EEAR
Register.
GPIOR2 – General Purpose I/O
Register 2
GPIOR1 – General Purpose I/O
Register 1
GPIOR0 – General Purpose I/O
Register 0
External Memory registers
XMCRA – External Memory
Control Register A
Bit76543210
0x2B (0x4B)MSBLSBGPIOR2
Read/WriteR/WR/WR/WR/WR/WR/WR/WR/W
Initial Value00000000
Bit76543210
0x2A (0x4A)MSBLSBGPIOR1
Read/WriteR/WR/WR/WR/WR/WR/WR/WR/W
Initial Value00000000
Bit76543210
0x1E (0x3E)MSBLSBGPIOR0
Read/WriteR/WR/WR/WR/WR/WR/WR/WR/W
Initial Value00000000
Bit76543210
“(0x74)”SRESRL2SRL1SRL0SRW11SRW10SRW01SRW00XMCRA
Read/WriteR/WR/WR/WR/WR/WR/WR/WR/W
Initial Value00000000
34
• Bit 7 – SRE: External SRAM/XMEM Enable
Writing SRE to one enables the External Memory Interface.The pin functions AD7:0,
A15:8, ALE, WR
, and RD are activated as the alternate pin functions. The SRE bit overrides any pin direction settings in the respective data direction registers. Writing SRE to
zero, disables the External Memory Interface and the normal pin and data direction settings are used.
• Bit 6:4 – SRL2:0: Wait-state Sector Limit
It is possible to configure different wait-states for different External Memory addresses.
The external memory address space can be divided in two sectors that have separate
wait-state bits. The SRL2, SRL1, and SRL0 bits select the split of the sectors, see Table
7 and Figure 13. By default, the SRL2, SRL1, and SRL0 bits are set to zero and the
entire external memory address space is treated as one sector. When the entire SRAM
ATmega640/1280/1281/2560/2561
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ATmega640/1280/1281/2560/2561
address space is configured as one sector, the wait-states are configured by the
SRW11 and SRW10 bits.
Table 7. Sector limits with different settings of SRL2:0
• Bit 3:2 – SRW11, SRW10: Wait-state Select Bits for Upper Sector
The SRW11 and SRW10 bits control the number of wait-states for the upper sector of
the external memory address space, see Table 8.
• Bit 1:0 – SRW01, SRW00: Wait-state Select Bits for Lower Sector
The SRW01 and SRW00 bits control the number of wait-states for the lower sector of
the external memory address space, see Table 8.
Table 8. Wait States
SRWn1SRWn0Wait States
00No wait-states
01Wait one cycle during read/write strobe
10Wait two cycles during read/write strobe
11Wait two cycles during read/write and wait one cycle before driving out
Note:1. n = 0 or 1 (lower/upper sector).
For further details of the timing and wait-states of the External Memory Interface, see
Figures 15 through Figures 18 for how the setting of the SRW bits affects the timing.
(1)
new address
2549K–AVR–01/07
35
XMCRB – External Memory
Control Register B
Bit765 4 3 210
(0x75)XMBK––––XMM2XMM1XMM0XMCRB
Read/WriteR/WRR R RR/WR/WR/W
Initial Value00000000
• Bit 7– XMBK: External Memory Bus-keeper Enable
Writing XMBK to one enables the bus keeper on the AD7:0 lines. When the bus keeper
is enabled, AD7:0 will keep the last driven value on the lines even if the XMEM interface
has tri-stated the lines. Writing XMBK to zero disables the bus keeper. XMBK is not
qualified with SRE, so even if the XMEM interface is disabled, the bus keepers are still
activated as long as XMBK is one.
• Bit 6:3 – Res: Reserved Bits
These bits are reserved and will always read as zero. When writing to this address location, write these bits to zero for compatibility with future devices.
• Bit 2:0 – XMM2, XMM1, XMM0: External Memory High Mask
When the External Memory is enabled, all Port C pins are default used for the high
address byte. If the full 60KB address space is not required to access the External Memory, some, or all, Port C pins can be released for normal Port Pin function as described
in Table 9. As described in “Using all 64KB Locations of External Memory” on page 31,
it is possible to use the XMMn bits to access all 64KB locations of the External Memory.
Table 9. Port C Pins Released as Normal Port Pins when the External Memory is
Enabled
XMM2XMM1XMM0# Bits for External Memory AddressReleased Port Pins
0008 (Full 56KB space)None
0017PC7
0106PC7 - PC6
0115PC7 - PC5
1004PC7 - PC4
1013PC7 - PC3
1102PC7 - PC2
111No Address high bitsFull Port C
36
ATmega640/1280/1281/2560/2561
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ATmega640/1280/1281/2560/2561
System Clock and
This section describes the clock options for the AVR microcontroller.
Clock Options
OverviewFigure 20 presents the principal clock systems in the AVR and their distribution. All of
the clocks need not be active at a given time. In order to reduce power consumption, the
clocks to modules not being used can be halted by using different sleep modes, as
described in “Power Management and Sleep Modes” on page 50. The clock systems
are detailed below.
Figure 20. Clock Distribution
Asynchronous
Timer/Counter
General I/O
Modules
clk
I/O
clk
ASY
ADC
clk
AVR Clock
Control Unit
ADC
CPU CoreRAM
clk
CPU
clk
FLASH
Reset Logic
Watchdog Timer
Flash and
EEPROM
Timer/Counter
Oscillator
External Clock
Source clock
System Clock
Prescaler
Clock
Multiplexer
Oscillator
Crystal
Watchdog clock
Watchdog
Oscillator
Low-frequency
Crystal Oscillator
Calibrated RC
Oscillator
2549K–AVR–01/07
37
Clock Systems and their
Distribution
CPU Clock – clk
I/O Clock – clk
Flash Clock – clk
CPU
I/O
FLASH
Asynchronous Timer Clock –
clk
ASY
ADC Clock – clk
ADC
The CPU clock is routed to parts of the system concerned with operation of the AVR
core. Examples of such modules are the General Purpose Register File, the Status Register and the data memory holding the Stack Pointer. Halting the CPU clock inhibits the
core from performing general operations and calculations.
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and
USART. The I/O clock is also used by the External Interrupt module, but note that some
external interrupts are detected by asynchronous logic, allowing such interrupts to be
detected even if the I/O clock is halted. Also note that start condition detection in the USI
module is carried out asynchronously when clk
is halted, TWI address recognition in
I/O
all sleep modes.
The Flash clock controls operation of the Flash interface. The Flash clock is usually
active simultaneously with the CPU clock.
The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked
directly from an external clock or an external 32 kHz clock crystal. The dedicated clock
domain allows using this Timer/Counter as a real-time counter even when the device is
in sleep mode.
The ADC is provided with a dedicated clock domain. This allows halting the CPU and
I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results.
38
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ATmega640/1280/1281/2560/2561
Clock SourcesThe device has the following clock source options, selectable by Flash Fuse bits as
shown below. The clock from the selected source is input to the AVR clock generator,
and routed to the appropriate modules.
Table 10. Device Clocking Options Select
Device Clocking Option CKSEL3:0
Low Power Crystal Oscillator1111 - 1000
Full Swing Crystal Oscillator0111 - 0110
Low Frequency Crystal Oscillator0101 - 0100
Internal 128 kHz RC Oscillator0011
Calibrated Internal RC Oscillator0010
External Clock0000
Reserved0001
Note:1. For all fuses “1” means unprogrammed while “0” means programmed.
(1)
Default Clock SourceThe device is shipped with internal RC oscillator at 8.0 MHz and with the fuse CKDIV8
programmed, resulting in 1.0 MHz system clock. The startup time is set to maximum
and time-out period enabled. (CKSEL = "0010", SUT = "10", CKDIV8 = "0"). The default
setting ensures that all users can make their desired clock source setting using any
available programming interface.
Clock Start-up SequenceAny clock source needs a sufficient V
to start oscillating and a minimum number of
CC
oscillating cycles before it can be considered stable.
To ensure sufficient V
, the device issues an internal reset with a time-out delay (t
CC
TOUT
after the device reset is released by all other reset sources. “On-chip Debug System” on
page 53 describes the start conditions for the internal reset. The delay (t
TOUT
) is timed
from the Watchdog Oscillator and the number of cycles in the delay is set by the SUTx
and CKSELx fuse bits. The selectable delays are shown in Table 11. The frequency of
the Watchdog Oscillator is voltage dependent as shown in “Typical Characteristics” on
page 390.
)
2549K–AVR–01/07
Table 11. Number of Watchdog Oscillator Cycles
Typ Time-out (VCC = 5.0V)Typ Time-out (VCC = 3.0V)Number of Cycles
0 ms0 ms0
4.1 ms4.3 ms512
65 ms69 ms8K (8,192)
Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum
Vcc. The delay will not monitor the actual voltage and it will be required to select a delay
longer than the Vcc rise time. If this is not possible, an internal or external Brown-Out
Detection circuit should be used. A BOD circuit will ensure sufficient Vcc before it
releases the reset, and the time-out delay can be disabled. Disabling the time-out delay
without utilizing a Brown-Out Detection circuit is not recommended.
The oscillator is required to oscillate for a minimum number of cycles before the clock is
considered stable. An internal ripple counter monitors the oscillator output clock, and
keeps the internal reset active for a given number of clock cycles. The reset is then
released and the device will start to execute. The recommended oscillator start-up time
39
is dependent on the clock type, and varies from 6 cycles for an externally applied clock
to 32K cycles for a low frequency crystal.
The start-up sequence for the clock includes both the time-out delay and the start-up
time when the device starts up from reset. When starting up from Power-save or Powerdown mode, Vcc is assumed to be at a sufficient level and only the start-up time is
included.
Low Power Crystal
Oscillator
Pins XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier
which can be configured for use as an On-chip Oscillator, as shown in Figure 21. Either
a quartz crystal or a ceramic resonator may be used.
This Crystal Oscillator is a low power oscillator, with reduced voltage swing on the
XTAL2 output. It gives the lowest power consumption, but is not capable of driving other
clock inputs, and may be more susceptible to noise in noisy environments. In these
cases, refer to the “Full Swing Crystal Oscillator” on page 42.
C1 and C2 should always be equal for both crystals and resonators. The optimal value
of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. Some initial guidelines for
choosing capacitors for use with crystals are given in Table 12. For ceramic resonators,
the capacitor values given by the manufacturer should be used.
Figure 21. Crystal Oscillator Connections
C2
C1
XTAL2
XTAL1
GND
40
The Low Power Oscillator can operate in three different modes, each optimized for a
specific frequency range. The operating mode is selected by the fuses CKSEL3:1 as
shown in Table 12.
Table 12. Low Power Crystal Oscillator Operating Modes
Frequency Range
0.4 - 0.9100
0.9 - 3.010112 - 22
3.0 - 8.011012 - 22
8.0 - 16.0
Notes:1. The frequency ranges are preliminary values. Actual values are TBD.
2. This option should not be used with crystals, only with ceramic resonators.
3. If 8 MHz frequency exceeds the specification of the device (depends on V
CKDIV8 Fuse can be programmed in order to divide the internal frequency by 8. It
must be ensured that the resulting divided clock meets the frequency specification of
the device.
(1)
(MHz)CKSEL3:1
(4)
ATmega640/1280/1281/2560/2561
(3)
Recommended Range for Capacitors
C1 and C2 (pF)
(2)
11112 - 22
–
), the
CC
2549K–AVR–01/07
ATmega640/1280/1281/2560/2561
4. Max frequency when using ceramic oscillator is 10 MHz.
The CKSEL0 Fuse together with the SUT1:0 Fuses select the start-up times as shown
in Table 13.
Table 13. Start-up Times for the Low Power Crystal Oscillator Clock Selection
Oscillator Source /
Power Conditions
Ceramic resonator, fast
Start-up Time from
Power-down and
Power-save
258 CK14CK + 4.1 ms
Additional Delay
from Reset
= 5.0V)CKSEL0SUT1:0
(V
CC
(1)
000
rising power
Ceramic resonator,
258 CK14CK + 65 ms
(1)
001
slowly rising power
Ceramic resonator,
1K CK14CK
(2)
010
BOD enabled
Ceramic resonator, fast
1K CK14CK + 4.1 ms
(2)
011
rising power
Ceramic resonator,
1K CK14CK + 65 ms
(2)
100
slowly rising power
Crystal Oscillator, BOD
enabled
Crystal Oscillator, fast
rising power
Crystal Oscillator,
slowly rising power
16K CK14CK
16K CK14CK + 4.1 ms
16K CK14CK + 65 ms
1
1
1
01
10
11
Notes:1. These options should only be used when not operating close to the maximum fre-
quency of the device, and only if frequency stability at start-up is not important for the
application. These options are not suitable for crystals.
2. These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They can also be used with crystals when not operating
close to the maximum frequency of the device, and if frequency stability at start-up is
not important for the application.
2549K–AVR–01/07
41
Full Swing Crystal
Oscillator
Pins XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier
which can be configured for use as an On-chip Oscillator, as shown in Figure 21. Either
a quartz crystal or a ceramic resonator may be used.
This Crystal Oscillator is a full swing oscillator, with rail-to-rail swing on the XTAL2 output. This is useful for driving other clock inputs and in noisy environments. The current
consumption is higher than the “Low Power Crystal Oscillator” on page 40. Note that the
Full Swing Crystal Oscillator will only operate for Vcc = 2.7 - 5.5 volts.
C1 and C2 should always be equal for both crystals and resonators. The optimal value
of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. Some initial guidelines for
choosing capacitors for use with crystals are given in Table 15. For ceramic resonators,
the capacitor values given by the manufacturer should be used.
The operating mode is selected by the fuses CKSEL3:1 as shown in Table 14.
Table 14. Full Swing Crystal Oscillator operating modes
Frequency Range
Notes:1. The frequency ranges are preliminary values. Actual values are TBD.
2. If 8 MHz frequency exceeds the specification of the device (depends on V
CKDIV8 Fuse can be programmed in order to divide the internal frequency by 8. It
must be ensured that the resulting divided clock meets the frequency specification of
the device.
(1)
(MHz)CKSEL3:1
0.4 - 1601112 - 22
(2)
Recommended Range for Capacitors
C1 and C2 (pF)
Figure 22. Crystal Oscillator Connections
C2
C1
XTAL2
XTAL1
GND
CC
), the
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ATmega640/1280/1281/2560/2561
Table 15. Start-up Times for the Full Swing Crystal Oscillator Clock Selection
Oscillator Source /
Power Conditions
Ceramic resonator, fast
Start-up Time from
Power-down and
Power-save
258 CK14CK + 4.1 ms
Additional Delay
from Reset
= 5.0V)CKSEL0SUT1:0
(V
CC
(1)
000
rising power
Ceramic resonator,
258 CK14CK + 65 ms
(1)
001
slowly rising power
Ceramic resonator,
1K CK14CK
(2)
010
BOD enabled
Ceramic resonator, fast
1K CK14CK + 4.1 ms
(2)
011
rising power
Ceramic resonator,
1K CK14CK + 65 ms
(2)
100
slowly rising power
Crystal Oscillator, BOD
enabled
Crystal Oscillator, fast
rising power
Crystal Oscillator,
slowly rising power
16K CK14CK
16K CK14CK + 4.1 ms
16K CK14CK + 65 ms
1
1
1
01
10
11
Notes:1. These options should only be used when not operating close to the maximum fre-
quency of the device, and only if frequency stability at start-up is not important for the
application. These options are not suitable for crystals.
2. These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They can also be used with crystals when not operating
close to the maximum frequency of the device, and if frequency stability at start-up is
not important for the application.
2549K–AVR–01/07
43
Low Frequency Crystal
Oscillator
The device can utilize a 32.768 kHz watch crystal as clock source by a dedicated Low
Frequency Crystal Oscillator. The crystal should be connected as shown in Figure 21.
When this Oscillator is selected, start-up times are determined by the SUT Fuses and
CKSEL0 as shown in Table 16.
Table 16. Start-up Times for the Low Frequency Crystal Oscillator Clock Selection
Calibrated Internal RC
Oscillator
Start-up Time from
Power-down and
Power Conditions
BOD enabled1K CK14CK
Fast rising power1K CK14CK + 4.1 ms
Slowly rising power1K CK14CK + 65 ms
BOD enabled32K CK14CK100
Fast rising power32K CK14CK + 4.1 ms101
Slowly rising power32K CK14CK + 65 ms110
Note:1. These options should only be used if frequency stability at start-up is not important
for the application.
Power-save
Reserved011
Reserved111
Additional Delay
from Reset
(VCC = 5.0V)CKSEL0SUT1:0
(1)
(1)
(1)
000
001
010
By defaylt, the Internal RC Oscillator provides an approximate 8 MHz clock. Though voltage and temperature dependent, this clock can be very accurately calibrated by the
user. See Table 172 on page 384 and “Internal Oscillator Speed” on page 409 for more
details. The device is shipped with the CKDIV8 Fuse programmed. See “System Clock
Prescaler” on page 47 for more details.
This clock may be selected as the system clock by programming the CKSEL Fuses as
shown in Table 17. If selected, it will operate with no external components. During reset,
hardware loads the pre-programmed calibration value into the OSCCAL Register and
thereby automatically calibrates the RC Oscillator. The accuracy of this calibration is
shown as Factory calibration in Table 172 on page 384.
44
By changing the OSCCAL register from SW, see “OSCCAL – Oscillator Calibration Reg-
ister” on page 48, it is possible to get a higher calibration accuracy than by using the
factory calibration. The accuracy of this calibration is shown as User calibration in Table
172 on page 384.
When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be used
for the Watchdog Timer and for the Reset Time-out. For more information on the preprogrammed calibration value, see the section “Calibration Byte” on page 345.
Notes:1. The device is shipped with this option selected.
2. The frequency ranges are preliminary values. Actual values are TBD.
3. If 8 MHz frequency exceeds the specification of the device (depends on V
CKDIV8 Fuse can be programmed in order to divide the internal frequency by 8.
(2)
(MHz) CKSEL3:0
When this Oscillator is selected, start-up times are determined by the SUT Fuses as
shown in Table 18 on page 45.
ATmega640/1280/1281/2560/2561
(1)(3)
), the
CC
2549K–AVR–01/07
ATmega640/1280/1281/2560/2561
Table 18. Start-up times for the internal calibrated RC Oscillator clock selection
128 kHz Internal
Oscillator
Start-up Time from Power-
Power Conditions
BOD enabled6 CK14CK00
Fast rising power6 CK14CK + 4.1 ms01
Slowly rising power6 CK14CK + 65 ms
Note:1. The device is shipped with this option selected.
down and Power-save
Reserved11
Additional Delay from
Reset (VCC = 5.0V)SUT1:0
(1)
10
The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz.
The frequency is nominal at 3V and 25°C. This clock may be select as the system clock
by programming the CKSEL Fuses to “11” as shown in Table 19.
Note:1. The frequency is preliminary value. Actual value is TBD.
When this clock source is selected, start-up times are determined by the SUT Fuses as
shown in Table 20.
Table 20. Start-up Times for the 128 kHz Internal Oscillator
Start-up Time from Power-
Power Conditions
BOD enabled6 CK14CK00
Fast rising power6 CK14CK + 4 ms01
Slowly rising power6 CK14CK + 64 ms10
down and Power-save
Reserved11
Additional Delay from
ResetSUT1:0
External ClockTo drive the device from an external clock source, XTAL1 should be driven as shown in
Figure 23. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”.
Figure 23. External Clock Drive Configuration
NC
EXTERNAL
CLOCK
SIGNAL
XTAL2
XTAL1
GND
2549K–AVR–01/07
45
When this clock source is selected, start-up times are determined by the SUT Fuses as
shown in Table 23.
Table 21. Crystal Oscillator Clock Frequency
Nominal Frequency CKSEL3:0
0 - 16 MHz0000
Table 22. Start-up Times for the External Clock Selection
Start-up Time from Power-
Power Conditions
BOD enabled6 CK14CK00
Fast rising power6 CK14CK + 4.1 ms01
Slowly rising power6 CK14CK + 65 ms10
down and Power-save
Reserved11
Additional Delay from
Reset (VCC = 5.0V)SUT1:0
When applying an external clock, it is required to avoid sudden changes in the applied
clock frequency to ensure stable operation of the MCU. A variation in frequency of more
than 2% from one clock cycle to the next can lead to unpredictable behavior. If changes
of more than 2% is required, ensure that the MCU is kept in Reset during the changes.
Note that the System Clock Prescaler can be used to implement run-time changes of
the internal clock frequency while still ensuring stable operation. Refer to “System Clock
Prescaler” on page 47 for details.
Clock Output BufferThe device can output the system clock on the CLKO pin. To enable the output, the
CKOUT Fuse has to be programmed. This mode is suitable when the chip clock is used
to drive other circuits on the system. The clock also will be output during reset, and the
normal operation of I/O pin will be overridden when the fuse is programmed. Any clock
source, including the internal RC Oscillator, can be selected when the clock is output on
CLKO. If the System Clock Prescaler is used, it is the divided system clock that is
output.
Timer/Counter OscillatorThe device can operate its Timer/Counter2 from an external 32.768 kHz watch crystal or
a external clock source. See Figure 21 on page 40 for crystal connection.
Applying an external clock source to TOSC1 requires EXCLK in the ASSR Register written to logic one. See “Asynchronous Operation of Timer/Counter2” on page 188 for
further description on selecting external clock as input instead of a 32 kHz crystal.
46
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2549K–AVR–01/07
ATmega640/1280/1281/2560/2561
System Clock PrescalerThe ATmega640/1280/1281/2560/2561 has a system clock prescaler, and the system
clock can be divided by setting the “CLKPR – Clock Prescale Register” on page 48. This
feature can be used to decrease the system clock frequency and the power consumption when the requirement for processing power is low. This can be used with all clock
source options, and it will affect the clock frequency of the CPU and all synchronous
peripherals. clk
23.
When switching between prescaler settings, the System Clock Prescaler ensures that
no glitches occurs in the clock system. It also ensures that no intermediate frequency is
higher than neither the clock frequency corresponding to the previous setting, nor the
clock frequency corresponding to the new setting.
The ripple counter that implements the prescaler runs at the frequency of the undivided
clock, which may be faster than the CPU's clock frequency. Hence, it is not possible to
determine the state of the prescaler - even if it were readable, and the exact time it takes
to switch from one clock division to the other cannot be exactly predicted. From the time
the CLKPS values are written, it takes between T1 + T2 and T1 + 2 * T2 before the new
clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is
the previous clock period, and T2 is the period corresponding to the new prescaler
setting.
To avoid unintentional changes of clock frequency, a special write procedure must be
followed to change the CLKPS bits:
1.Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits
in CLKPR to zero.
2.Within four cycles, write the desired value to CLKPS while writing a zero to
CLKPCE.
I/O
, clk
ADC
, clk
, and clk
CPU
are divided by a factor as shown in Table
FLASH
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted.
2549K–AVR–01/07
47
Register Description
OSCCAL – Oscillator
Calibration Register
Bit76543210
(0x66)CAL7CAL6CAL5CAL4CAL3CAL2CAL1CAL0OSCCAL
Read/WriteR/WR/WR/WR/WR/WR/WR/WR/W
Initial ValueDevice Specific Calibration Value
• Bits 7:0 – CAL7:0: Oscillator Calibration Value
The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator
to remove process variations from the oscillator frequency. A pre-programmed calibration value is automatically written to this register during chip reset, giving the Factory
calibrated frequency as specified in Table 172 on page 384. The application software
can write this register to change the oscillator frequency. The oscillator can be calibrated
to frequencies as specified in Table 172 on page 384. Calibration outside that range is
not guaranteed.
Note that this oscillator is used to time EEPROM and Flash write accesses, and these
write times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more than 8.8 MHz. Otherwise, the EEPROM or Flash write may fail.
The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0
gives the lowest frequency range, setting this bit to 1 gives the highest frequency range.
The two frequency ranges are overlapping, in other words a setting of OSCCAL = 0x7F
gives a higher frequency than OSCCAL = 0x80.
The CAL6..0 bits are used to tune the frequency within the selected range. A setting of
0x00 gives the lowest frequency in that range, and a setting of 0x7F gives the highest
frequency in the range.
CLKPR – Clock Prescale
Register
Bit7 6543210
(0x61)
Read/WriteR/WRRRR/WR/WR/WR/W
Initial Value0000See Bit Description
CLKPCE–––CLKPS3CLKPS2CLKPS1CLKPS0CLKPR
• Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The
CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to
zero. CLKPCE is cleared by hardware four cycles after it is written or when CLKPS bits
are written. Rewriting the CLKPCE bit within this time-out period does neither extend the
time-out period, nor clear the CLKPCE bit.
These bits define the division factor between the selected clock source and the internal
system clock. These bits can be written run-time to vary the clock frequency to suit the
application requirements. As the divider divides the master clock input to the MCU, the
speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given in Table 23.
The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits
are reset to “0011”, giving a division factor of 8 at start up. This feature should be used if
the selected clock source has a higher frequency than the maximum frequency of the
48
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
ATmega640/1280/1281/2560/2561
device at the present operating conditions. Note that any value can be written to the
CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must
ensure that a sufficient division factor is chosen if the selected clock source has a higher
frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed.
Table 23. Clock Prescaler Select
CLKPS3CLKPS2CLKPS1CLKPS0Clock Division Factor
00001
00012
00104
00118
010016
010132
011064
0111128
1000256
1001Reserved
1010Reserved
1011Reserved
1100Reserved
1101Reserved
1110Reserved
1111Reserved
2549K–AVR–01/07
49
Power Management
and Sleep Modes
Sleep modes enable the application to shut down unused modules in the MCU, thereby
saving power. The AVR provides various sleep modes allowing the user to tailor the
power consumption to the application’s requirements.
Sleep ModesFigure 20 on page 37 presents the different clock systems in the
ATmega640/1280/1281/2560/2561, and their distribution. The figure is helpful in selecting an appropriate sleep mode. Table 24 shows the different sleep modes and their
wake-up sources.
Table 24. Active Clock Domains and Wake-up Sources in the Different Sleep Modes.
Active Clock DomainsOscillatorsWake-up Sources
CPU
FLASH
Sleep Mode
clk
clk
clkIOclk
IdleXXXXX
ADCNRMXXXX
Power-downX
Power-saveXX
Standby
(1)
Extended StandbyX
Notes:1. Only recommended with external crystal or resonator selected as clock source.
2. If Timer/Counter2 is running in asynchronous mode.
3. For INT7:4, only level interrupt.
ADC
ASY
clk
Main Clock
Source
Enabled
Timer Osc
Enabled
INT7:0 and
Pin Change
TWI Address
(2)
(2)
(2)
XX
(2)
XX
(2)
Match
XXXXXXX
(3)
X
(3)
(3)
X
(3)
(3)
X
XX
XX
XXX
XX
XXX
Timer2
SPM/
EEPROM Ready
(2)
XXX
ADC
WDT Interrupt
Other I/O
50
To enter any of the sleep modes, the SE bit in “SMCR – Sleep Mode Control Register”
on page 54 must be written to logic one and a SLEEP instruction must be executed. The
SM2, SM1, and SM0 bits in the SMCR Register select which sleep mode will be activated by the SLEEP instruction. See Table 25 on page 54 for a summary.
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up.
The MCU is then halted for four cycles in addition to the start-up time, executes the
interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from
sleep. If a reset occurs during sleep mode, the MCU wakes up and executes from the
Reset Vector.
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
ATmega640/1280/1281/2560/2561
Idle ModeWhen the SM2:0 bits are written to 000, the SLEEP instruction makes the MCU enter
Idle mode, stopping the CPU but allowing the SPI, USART, Analog Comparator, ADC,
2-wire Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continue
operating. This sleep mode basically halts clk
clocks to run.
Idle mode enables the MCU to wake up from external triggered interrupts as well as
internal ones like the Timer Overflow and USART Transmit Complete interrupts. If
wake-up from the Analog Comparator interrupt is not required, the Analog Comparator
can be powered down by setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will reduce power consumption in Idle mode. If the ADC is
enabled, a conversion starts automatically when this mode is entered.
CPU
and clk
, while allowing the other
FLASH
ADC Noise Reduction
Mode
When the SM2:0 bits are written to 001, the SLEEP instruction makes the MCU enter
ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, 2-wire Serial Interface address match, Timer/Counter2 and the Watchdog to
continue operating (if enabled). This sleep mode basically halts clkI/O, clkCPU, and clkFLASH, while allowing the other clocks to run.
This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is enabled, a conversion starts automatically when this mode is
entered. Apart form the ADC Conversion Complete interrupt, only an External Reset, a
Watchdog System Reset, a Watchdog interrupt, a Brown-out Reset, a 2-wire serial interface interrupt, a Timer/Counter2 interrupt, an SPM/EEPROM ready interrupt, an
external level interrupt on INT7:4 or a pin change interrupt can wakeup the MCU from
ADC Noise Reduction mode.
Power-down ModeWhen the SM2:0 bits are written to 010, the SLEEP instruction makes the MCU enter
Power-down mode. In this mode, the external Oscillator is stopped, while the external
interrupts, the 2-wire Serial Interface, and the Watchdog continue operating (if enabled).
Only an External Reset, a Watchdog Reset, a Brown-out Reset, 2-wire Serial Interface
address match, an external level interrupt on INT7:4, an external interrupt on INT3:0, or
a pin change interrupt can wake up the MCU. This sleep mode basically halts all generated clocks, allowing operation of asynchronous modules only.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the
changed level must be held for some time to wake up the MCU. Refer to “External Interrupts” on page 77 for details.
When waking up from Power-down mode, there is a delay from the wake-up condition
occurs until the wake-up becomes effective. This allows the clock to restart and become
stable after having been stopped. The wake-up period is defined by the same CKSEL
Fuses that define the Reset Time-out period, as described in “Clock Sources” on page
39.
Power-save ModeWhen the SM2:0 bits are written to 011, the SLEEP instruction makes the MCU enter
Power-save mode. This mode is identical to Power-down, with one exception:
If Timer/Counter2 is enabled, it will keep running during sleep. The device can wake up
from either Timer Overflow or Output Compare event from Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in TIMSK2, and the Global
Interrupt Enable bit in SREG is set.
If Timer/Counter2 is not running, Power-down mode is recommended instead of Powersave mode.
51
2549K–AVR–01/07
The Timer/Counter2 can be clocked both synchronously and asynchronously in Powersave mode. If the Timer/Counter2 is not using the asynchronous clock, the
Timer/Counter Oscillator is stopped during sleep. If the Timer/Counter2 is not using the
synchronous clock, the clock source is stopped during sleep. Note that even if the synchronous clock is running in Power-save, this clock is only available for the
Timer/Counter2.
Standby ModeWhen the SM2:0 bits are 110 and an external crystal/resonator clock option is selected,
the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to
Power-down with the exception that the Oscillator is kept running. From Standby mode,
the device wakes up in six clock cycles.
Extended Standby ModeWhen the SM2:0 bits are 111 and an external crystal/resonator clock option is selected,
the SLEEP instruction makes the MCU enter Extended Standby mode. This mode is
identical to Power-save mode with the exception that the Oscillator is kept running.
From Extended Standby mode, the device wakes up in six clock cycles.Power Reduction Register
The Power Reduction Register (PRR), see “PRR0 – Power Reduction Register 0” on
page 55 and “PRR1 – Power Reduction Register 1” on page 56, provides a method to
stop the clock to individual peripherals to reduce power consumption. The current state
of the peripheral is frozen and the I/O registers can not be read or written. Resources
used by the peripheral when stopping the clock will remain occupied, hence the peripheral should in most cases be disabled before stopping the clock. Waking up a module,
which is done by clearing the bit in PRR, puts the module in the same state as before
shutdown.
Module shutdown can be used in Idle mode and Active mode to significantly reduce the
overall power consumption. See “Supply Current of IO modules” on page 395 for examples. In all other sleep modes, the clock is already stopped.
Minimizing Power
Consumption
Analog to Digital ConverterIf enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should
Analog ComparatorWhen entering Idle mode, the Analog Comparator should be disabled if not used. When
There are several issues to consider when trying to minimize the power consumption in
an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device’s
functions are operating. All functions not needed should be disabled. In particular, the
following modules may need special consideration when trying to achieve the lowest
possible power consumption.
be disabled before entering any sleep mode. When the ADC is turned off and on again,
the next conversion will be an extended conversion. Refer to “ADC – Analog to Digital
Converter” on page 279 for details on ADC operation.
entering ADC Noise Reduction mode, the Analog Comparator should be disabled. In
other sleep modes, the Analog Comparator is automatically disabled. However, if the
Analog Comparator is set up to use the Internal Voltage Reference as input, the Analog
Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled, independent of sleep mode. Refer to “AC – Analog Comparator”
on page 275 for details on how to configure the Analog Comparator.
52
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
ATmega640/1280/1281/2560/2561
Brown-out DetectorIf the Brown-out Detector is not needed by the application, this module should be turned
off. If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in
all sleep modes, and hence, always consume power. In the deeper sleep modes, this
will contribute significantly to the total current consumption. Refer to “Brown-out Detection” on page 60 for details on how to configure the Brown-out Detector.
Internal Voltage ReferenceThe Internal Voltage Reference will be enabled when needed by the Brown-out Detec-
tion, the Analog Comparator or the ADC. If these modules are disabled as described in
the sections above, the internal voltage reference will be disabled and it will not be consuming power. When turned on again, the user must allow the reference to start up
before the output is used. If the reference is kept on in sleep mode, the output can be
used immediately. Refer to “Internal Voltage Reference” on page 61 for details on the
start-up time.
Watchdog TimerIf the Watchdog Timer is not needed in the application, the module should be turned off.
If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence,
always consume power. In the deeper sleep modes, this will contribute significantly to
the total current consumption. Refer to “Interrupts” on page 69 for details on how to configure the Watchdog Timer.
Port PinsWhen entering a sleep mode, all port pins should be configured to use minimum power.
The most important is then to ensure that no pins drive resistive loads. In sleep modes
where both the I/O clock (clk
ers of the device will be disabled. This ensures that no power is consumed by the input
logic when not needed. In some cases, the input logic is needed for detecting wake-up
conditions, and it will then be enabled. Refer to the section “Digital Input Enable and
Sleep Modes” on page 87 for details on which pins are enabled. If the input buffer is
enabled and the input signal is left floating or have an analog signal level close to V
the input buffer will use excessive power.
) and the ADC clock (clk
I/O
) are stopped, the input buff-
ADC
CC
/2,
For analog input pins, the digital input buffer should be disabled at all times. An analog
signal level close to V
/2 on an input pin can cause significant current even in active
CC
mode. Digital input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR2, DIDR1 and DIDR0). Refer to “DIDR2 – Digital Input Disable Register 2” on
page 300, “DIDR1 – Digital Input Disable Register 1” on page 278 and “DIDR0 – Digital
Input Disable Register 0” on page 300 for details.
On-chip Debug SystemIf the On-chip debug system is enabled by the OCDEN Fuse and the chip enters sleep
mode, the main clock source is enabled, and hence, always consumes power. In the
deeper sleep modes, this will contribute significantly to the total current consumption.
There are three alternative ways to disable the OCD system:
•Disable the OCDEN Fuse.
•Disable the JTAGEN Fuse.
•Write one to the JTD bit in MCUCR.
2549K–AVR–01/07
53
Register Description
SMCR – Sleep Mode Control
Register
The Sleep Mode Control Register contains control bits for power management.
These bits select between the five available sleep modes as shown in Table 25.
Table 25. Sleep Mode Select
SM2SM1SM0Sleep Mode
000Idle
001ADC Noise Reduction
010Power-down
011Power-save
100Reserved
101Reserved
110Standby
111Extended Standby
(1)
(1)
Note:1. Standby modes are only recommended for use with external crystals or resonators.
• Bit 1 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the
SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is
the programmer’s purpose, it is recommended to write the Sleep Enable (SE) bit to one
just before the execution of the SLEEP instruction and to clear it immediately after waking up.
Writing a logic one to this bit shuts down the TWI by stopping the clock to the module.
When waking up the TWI again, the TWI should be re initialized to ensure proper
operation.
• Bit 6 - PRTIM2: Power Reduction Timer/Counter2
Writing a logic one to this bit shuts down the Timer/Counter2 module in synchronous
mode (AS2 is 0). When the Timer/Counter2 is enabled, operation will continue like
before the shutdown.
• Bit 5 - PRTIM0: Power Reduction Timer/Counter0
Writing a logic one to this bit shuts down the Timer/Counter0 module. When the
Timer/Counter0 is enabled, operation will continue like before the shutdown.
• Bit 4 - Res: Reserved bit
This bit is reserved bit and will always read as zero.
• Bit 3 - PRTIM1: Power Reduction Timer/Counter1
Writing a logic one to this bit shuts down the Timer/Counter1 module. When the
Timer/Counter1 is enabled, operation will continue like before the shutdown.
• Bit 2 - PRSPI: Power Reduction Serial Peripheral Interface
Writing a logic one to this bit shuts down the Serial Peripheral Interface by stopping the
clock to the module. When waking up the SPI again, the SPI should be re initialized to
ensure proper operation.
• Bit 1 - PRUSART0: Power Reduction USART0
Writing a logic one to this bit shuts down the USART0 by stopping the clock to the module. When waking up the USART0 again, the USART0 should be re initialized to ensure
proper operation.
• Bit 0 - PRADC: Power Reduction ADC
Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before
shut down. The analog comparator cannot use the ADC input MUX when the ADC is
shut down.
These bits are reserved and will always read as zero.
• Bit 5 - PRTIM5: Power Reduction Timer/Counter5
Writing a logic one to this bit shuts down the Timer/Counter5 module. When the
Timer/Counter5 is enabled, operation will continue like before the shutdown.
• Bit 4 - PRTIM4: Power Reduction Timer/Counter4
Writing a logic one to this bit shuts down the Timer/Counter4 module. When the
Timer/Counter4 is enabled, operation will continue like before the shutdown.
• Bit 3 - PRTIM3: Power Reduction Timer/Counter3
Writing a logic one to this bit shuts down the Timer/Counter3 module. When the
Timer/Counter3 is enabled, operation will continue like before the shutdown.
• Bit 2 - PRUSART3: Power Reduction USART3
Writing a logic one to this bit shuts down the USART3 by stopping the clock to the module. When waking up the USART3 again, the USART3 should be re initialized to ensure
proper operation.
• Bit 1 - PRUSART2: Power Reduction USART2
Writing a logic one to this bit shuts down the USART2 by stopping the clock to the module. When waking up the USART2 again, the USART2 should be re initialized to ensure
proper operation.
• Bit 0 - PRUSART1: Power Reduction USART1
Writing a logic one to this bit shuts down the USART1 by stopping the clock to the module. When waking up the USART1 again, the USART1 should be re initialized to ensure
proper operation.
56
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
ATmega640/1280/1281/2560/2561
System Control
and Reset
Resetting the AVRDuring reset, all I/O Registers are set to their initial values, and the program starts exe-
cution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP
– Absolute Jump – instruction to the reset handling routine. If the program never
enables an interrupt source, the Interrupt Vectors are not used, and regular program
code can be placed at these locations. This is also the case if the Reset Vector is in the
Application section while the Interrupt Vectors are in the Boot section or vice versa. The
circuit diagram in Figure 24 shows the reset logic. Table 26 defines the electrical parameters of the reset circuitry.
The I/O ports of the AVR are immediately reset to their initial state when a reset source
goes active. This does not require any clock source to be running.
After all reset sources have gone inactive, a delay counter is invoked, stretching the
internal reset. This allows the power to reach a stable level before normal operation
starts. The time-out period of the delay counter is defined by the user through the SUT
and CKSEL Fuses. The different selections for the delay period are presented in “Clock
Sources” on page 39.
Reset SourcesThe ATmega640/1280/1281/2560/2561 has five sources of reset:
•Power-on Reset. The MCU is reset when the supply voltage is below the Power-on
Reset threshold (V
•External Reset. The MCU is reset when a low level is present on the RESET
longer than the minimum pulse length.
•Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and
the Watchdog is enabled.
•Brown-out Reset. The MCU is reset when the supply voltage V
Brown-out Reset threshold (V
•JTAG AVR Reset. The MCU is reset as long as there is a logic one in the Reset
Register, one of the scan chains of the JTAG system. Refer to the section “IEEE
1149.1 (JTAG) Boundary-scan” on page 308 for details.
POT
).
) and the Brown-out Detector is enabled.
BOT
is below the
CC
pin for
2549K–AVR–01/07
57
Figure 24. Reset Logic
Power-on Reset
Circuit
DATA BU S
MCU Status
Register (MCUSR)
JTRF
BORF
PORF
WDRF
EXTRF
BODLEVEL [2..0]
Pull-up Resistor
SPIKE
FILTER
JTAG Reset
Register
Table 26. Reset Characteristics
Brown-out
Reset Circuit
Watchdog
Oscillator
Clock
Generator
CKSEL[3:0]
SUT[1:0]
(1)
CK
Delay Counters
TIMEOUT
SymbolParameterConditionMinTypMaxUnits
Power-on Reset Threshold
Voltage (rising)
V
POT
Power-on Reset Threshold
Voltage (falling)
(2)
TBDTBDTBDV
TBDTBDTBDV
V
t
RST
RST
RESET Pin Threshold VoltageTBDTBDTBDV
Minimum pulse width on RESET
Pin
TBDTBDTBDns
Notes:1. Values are guidelines only. Actual values are TBD.
2. The Power-on Reset will not work unless the supply voltage has been below V
POT
(falling)
Power-on ResetA Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detec-
tion level is defined in Table 26. The POR is activated whenever V
is below the
CC
detection level. The POR circuit can be used to trigger the start-up Reset, as well as to
detect a failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset threshold voltage invokes the delay counter, which determines
58
how long the device is kept in RESET after V
again, without any delay, when V
External ResetAn External Reset is generated by a low level on the RESET
than the minimum pulse width (see Table 26) will generate a reset, even if the clock is
not running. Shorter pulses are not guaranteed to generate a reset. When the applied
signal reaches the Reset Threshold Voltage – V
counter starts the MCU after the Time-out period – t
– on its positive edge, the delay
RST
TOUT –
has expired.
Figure 27. External Reset During Operation
CC
pin. Reset pulses longer
2549K–AVR–01/07
59
Brown-out DetectionATmega640/1280/1281/2560/2561 has an On-chip Brown-out Detection (BOD) circuit
for monitoring the V
level during operation by comparing it to a fixed trigger level. The
CC
trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level
has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as V
Table 27. BODLEVEL Fuse Coding
BOT+
(1)
= V
BOT
+ V
HYST
/2 and V
BOT-
= V
BOT
- V
HYST
/2.
BODLEVEL 2:0 FusesMin V
BOT
Typ V
BOT
Max V
BOT
Units
111BOD Disabled
1101.71.82.0
1004.14.34.5
011
010
Reserved
001
000
Note:1. V
may be below nominal minimum operating voltage for some devices. For
BOT
devices where this is the case, the device is tested down to VCC = V
during the
BOT
production test. This guarantees that a Brown-Out Reset will occur before V
CC
to a voltage where correct operation of the microcontroller is no longer guaranteed.
The test is performed using BODLEVEL = 110 for 4 MHz operation of
ATmega640V/1280V/1281V/2560V/2561V, BODLEVEL = 101 for 8 MHz operation of
ATmega640V/1280V/1281V/2560V/2561V and ATmega640/1280/1281, and
BODLEVEL = 100 for 16 MHz operation of ATmega640/1280/1281/2560/2561.
Table 28. Brown-out Characteristics
SymbolParameterMinTypMaxUnits
V
t
BOD
HYST
Brown-out Detector Hysteresis50mV
Min Pulse Width on Brown-out Resetns
V1012.52.72.9
drops
60
When the BOD is enabled, and VCC decreases to a value below the trigger level (V
in Figure 28), the Brown-out Reset is immediately activated. When VCC increases above
the trigger level (V
out period t
has expired.
TOUT
in Figure 28), the delay counter starts the MCU after the Time-
BOT+
The BOD circuit will only detect a drop in V
for longer than t
given in Table 26.
BOD
Figure 28. Brown-out Reset During Operation
V
CC
RESET
TIME-OUT
INTERNAL
RESET
V
BOT-
ATmega640/1280/1281/2560/2561
if the voltage stays below the trigger level
CC
V
BOT+
t
TOUT
2549K–AVR–01/07
BOT-
ATmega640/1280/1281/2560/2561
Watchdog ResetWhen the Watchdog times out, it will generate a short reset pulse of one CK cycle dura-
tion. On the falling edge of this pulse, the delay timer starts counting the Time-out period
t
. See “Watchdog Timer” on page 53. for details on operation of the Watchdog
TOUT
Timer.
Figure 29. Watchdog Reset During Operation
CC
CK
Internal Voltage
Reference
Voltage Reference Enable
Signals and Start-up Time
ATmega640/1280/1281/2560/2561 features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog
Comparator or the ADC.
The voltage reference has a start-up time that may influence the way it should be used.
The start-up time is given in Table 29. To save power, the reference is not always turned
on. The reference is on during the following situations:
1.When the BOD is enabled (by programming the BODLEVEL [2:0] Fuse).
2.When the bandgap reference is connected to the Analog Comparator (by setting
the ACBG bit in ACSR).
3.When the ADC is enabled.
Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the
user must always allow the reference to start up before the output from the Analog Comparator or ADC is used. To reduce power consumption in Power-down mode, the user
can avoid the three conditions above to ensure that the reference is turned off before
entering Power-down mode.
Table 29. Internal Voltage Reference Characteristics
SymbolParameterConditionMinTypMaxUnits
V
BG
t
BG
I
BG
Bandgap reference voltageTBDTBD1.1TBDV
Bandgap reference start-up timeTBD4070µs
Bandgap reference current
consumption
(1)
TBD10TBDµA
2549K–AVR–01/07
Note:1. Values are guidelines only. Actual values are TBD.
61
Watchdog TimerATmega640/1280/1281/2560/2561 has an Enhanced Watchdog Timer (WDT). The
main features are:
Clocked from separate On-chip Oscillator
•
• 3 Operating modes
– Interrupt
– System Reset
– Interrupt and System Reset
• Selectable Time-out period from 16ms to 8s
• Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode
Figure 30. Watchdog Timer
128kHz
OSCILLATOR
OSC/2K
OSC/4K
OSC/8K
OSC/16K
OSC/32K
OSC/64K
OSC/128K
OSC/256K
OSC/512K
OSC/1024K
WDP0
WATCHDOG
RESET
WDP1
WDP2
WDP3
WDE
WDIF
WDIE
MCU RESET
INTERRUPT
The Watchdog Timer (WDT) is a timer counting cycles of a separate on-chip 128 kHz
oscillator. The WDT gives an interrupt or a system reset when the counter reaches a
given time-out value. In normal operation mode, it is required that the system uses the
WDR - Watchdog Timer Reset - instruction to restart the counter before the time-out
value is reached. If the system doesn't restart the counter, an interrupt or system reset
will be issued.
In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can
be used to wake the device from sleep-modes, and also as a general system timer. One
example is to limit the maximum time allowed for certain operations, giving an interrupt
when the operation has run longer than expected. In System Reset mode, the WDT
gives a reset when the timer expires. This is typically used to prevent system hang-up in
case of runaway code. The third mode, Interrupt and System Reset mode, combines the
other two modes by first giving an interrupt and then switch to System Reset mode. This
mode will for instance allow a safe shutdown by saving critical parameters before a system reset.
The Watchdog always on (WDTON) fuse, if programmed, will force the Watchdog Timer
to System Reset mode. With the fuse programmed the System Reset mode bit (WDE)
and Interrupt mode bit (WDIE) are locked to 1 and 0 respectively. To further ensure program security, alterations to the Watchdog set-up must follow timed sequences. The
sequence for clearing WDE and changing time-out configuration is as follows:
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1.In the same operation, write a logic one to the Watchdog change enable bit
(WDCE) and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit.
2.Within the next four clock cycles, write the WDE and Watchdog prescaler bits
(WDP) as desired, but with the WDCE bit cleared. This must be done in one
operation.
The following code example shows one assembly and one C function for turning off the
Watchdog Timer. The example assumes that interrupts are controlled (e.g. by disabling
interrupts globally) so that no interrupts will occur during the execution of these
functions.
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63
Assembly Code Example
WDT_off:
; Turn off global interrupt
cli
; Reset Watchdog Timer
wdr
; Clear WDRF in MCUSR
in r16, MCUSR
andi r16, (0xff & (0<<WDRF))
out MCUSR, r16
; Write logical one to WDCE and WDE
; Keep old prescaler setting to prevent unintentional time-out
ldi r16, WDTCSR
ori r16, (1<<WDCE) | (1<<WDE)
sts WDTCSR, r16
; Turn off WDT
ldi r16, (0<<WDE)
sts WDTCSR, r16
; Turn on global interrupt
sei
ret
C Code Example
(1)
(1)
void WDT_off(void)
{
__disable_interrupt();
__watchdog_reset();
/* Clear WDRF in MCUSR */
MCUSR &= ~(1<<WDRF);
/* Write logical one to WDCE and WDE */
/* Keep old prescaler setting to prevent unintentional time-out
*/
WDTCSR |= (1<<WDCE) | (1<<WDE);
/* Turn off WDT */
WDTCSR = 0x00;
__enable_interrupt();
}
Note:1. The example code assumes that the part specific header file is included.
Note: If the Watchdog is accidentally enabled, for example by a runaway pointer or
brown-out condition, the device will be reset and the Watchdog Timer will stay enabled.
If the code is not set up to handle the Watchdog, this might lead to an eternal loop of
time-out resets. To avoid this situation, the application software should always clear the
Watchdog System Reset Flag (WDRF) and the WDE control bit in the initialisation routine, even if the Watchdog is not in use.
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The following code example shows one assembly and one C function for changing the
time-out value of the Watchdog Timer.
Assembly Code Example
WDT_Prescaler_Change:
; Turn off global interrupt
cli
; Reset Watchdog Timer
wdr
; Start timed sequence
in r16, WDTCSR
ori r16, (1<<WDCE) | (1<<WDE)
out WDTCSR, r16
; -- Got four cycles to set the new values from here -
; Set new prescaler(time-out) value = 64K cycles (~0.5 s)
ldi r16, (1<<WDE) | (1<<WDP2) | (1<<WDP0)
out WDTCSR, r16
; -- Finished setting new values, used 2 cycles -
; Turn on global interrupt
sei
ret
C Code Example
void WDT_Prescaler_Change(void)
{
__disable_interrupt();
__watchdog_reset();
/* Start timed equence */
WDTCSR |= (1<<WDCE) | (1<<WDE);
/* Set new prescaler(time-out) value = 64K cycles (~0.5 s) */
WDTCSR = (1<<WDE) | (1<<WDP2) | (1<<WDP0);
__enable_interrupt();
}
(1)
(1)
2549K–AVR–01/07
Note:1. The example code assumes that the part specific header file is included.
Note: The Watchdog Timer should be reset before any change of the WDP bits, since a
change in the WDP bits can result in a time-out when switching to a shorter time-out
period.
65
Register Description
MCUSR – MCU Status
Register
The MCU Status Register provides information on which reset source caused an MCU
reset.
Bit76543210
0x35 (0x55)
Read/WriteRRRR/WR/WR/WR/WR/W
Initial Value000See Bit Description
–––JTRFWDRFBORFEXTRFPORFMCUSR
• Bit 4 – JTRF: JTAG Reset Flag
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register
selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or
by writing a logic zero to the flag.
• Bit 3 – WDRF: Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by
writing a logic zero to the flag.
• Bit 2 – BORF: Brown-out Reset Flag
This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by
writing a logic zero to the flag.
• Bit 1 – EXTRF: External Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by
writing a logic zero to the flag.
WDTCSR – Watchdog Timer
Control Register
• Bit 0 – PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to
the flag.
To make use of the Reset Flags to identify a reset condition, the user should read and
then Reset the MCUSR as early as possible in the program. If the register is cleared
before another reset occurs, the source of the reset can be found by examining the
Reset Flags.
Bit76543210
(0x60)WDIFWDIEWDP3WDCEWDEWDP2WDP1WDP0WDTCSR
Read/WriteR/WR/WR/WR/WR/WR/WR/WR/W
Initial Value0000X000
• Bit 7 - WDIF: Watchdog Interrupt Flag
This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is
configured for interrupt. WDIF is cleared by hardware when executing the corresponding
interrupt handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag.
When the I-bit in SREG and W DIE are set, the Watchdog Time-out Interrupt is
executed.
• Bit 6 - WDIE: Watchdog Interrupt Enable
When this bit is written to one and the I-bit in the Status Register is set, the Watchdog
Interrupt is enabled. If WDE is cleared in combination with this setting, the Watchdog
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Timer is in Interrupt Mode, and the corresponding interrupt is executed if time-out in the
Watchdog Timer occurs.
If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first
time-out in the Watchdog Timer will set WDIF. Executing the corresponding interrupt
vector will clear WDIE and WDIF automatically by hardware (the Watchdog goes to System Reset Mode). This is useful for keeping the Watchdog Timer security while using
the interrupt. To stay in Interrupt and System Reset Mode, WDIE must be set after each
interrupt. This should however not be done within the interrupt service routine itself, as
this might compromise the safety-function of the Watchdog System Reset mode. If the
interrupt is not executed before the next time-out, a System Reset will be applied.
Table 30. Watchdog Timer Configuration
WDTON
(1)
100StoppedNone
101Interrupt ModeInterrupt
110System Reset ModeReset
111
WDEWDIEModeAction on Time-out
Interrupt and System
Reset Mode
Interrupt, then go to
System Reset Mode
0xxSystem Reset ModeReset
Note:1. WDTON Fuse set to “0“ means programmed and “1” means unprogrammed.
• Bit 4 - WDCE: Watchdog Change Enable
This bit is used in timed sequences for changing WDE and prescaler bits. To clear the
WDE bit, and/or change the prescaler bits, WDCE must be set.
Once written to one, hardware will clear WDCE after four clock cycles.
• Bit 3 - WDE: Watchdog System Reset Enable
WDE is overridden by WDRF in MCUSR. This means that WDE is always set when
WDRF is set. To clear WDE, WDRF must be cleared first. This feature ensures multiple
resets during conditions causing failure, and a safe start-up after the failure.
• Bit 5, 2:0 - WDP3:0: Watchdog Timer Prescaler 3, 2, 1 and 0
The WDP3:0 bits determine the Watchdog Timer prescaling when the Watchdog Timer
is running. The different prescaling values and their corresponding time-out periods are
shown in Table 31 on page 68.
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67
.
Table 31. Watchdog Timer Prescale Select
Number of WDT Oscillator
WDP3WDP2WDP1WDP0
00002K (2048) cycles16 ms
00014K (4096) cycles32 ms
00108K (8192) cycles64 ms
001116K (16384) cycles0.125 s
010032K (32768) cycles0.25 s
010164K (65536) cycles0.5 s
0110128K (131072) cycles1.0 s
0111256K (262144) cycles2.0 s
1000512K (524288) cycles4.0 s
10011024K (1048576) cycles8.0 s
1010
1011
1100
1101
1110
1111
Cycles
Reserved
Typical Time-out at
VCC = 5.0V
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InterruptsThis section describes the specifics of the interrupt handling as performed in
ATmega640/1280/1281/2560/2561. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 17.
Interrupt Vectors in ATmega640/1280/1281/2560/2561
Notes:1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader
address at reset, see “Memory Programming” on page 342.
2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of
the Boot Flash Section. The address of each Interrupt Vector will then be the address
in this table added to the start address of the Boot Flash Section.
3. Only available in
ATmega640/1280/2560
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Reset and Interrupt
Vector placement
Table 33 on page 71 shows Reset and Interrupt Vectors placement for the various combinations of BOOTRST and IVSEL settings. If the program never enables an interrupt
source, the Interrupt Vectors are not used, and regular program code can be placed at
these locations. This is also the case if the Reset Vector is in the Application section
while the Interrupt Vectors are in the Boot section or vice versa.
Note:1. The Boot Reset Address is shown in Table 140 on page 335 through Table 148 on
page 339. For the BOOTRST Fuse “1” means unprogrammed while “0” means
programmed.
(1)
The most typical and general program setup for the Reset and Interrupt Vector
Addresses in ATmega640/1280/1281/2560/2561 is:
AddressLabelsCodeComments
0x0000jmpRESET; Reset Handler
0x0002jmpINT0; IRQ0 Handler
0x0004jmpINT1; IRQ1 Handler
0x0006jmpINT2; IRQ2 Handler
0x0008jmpINT3; IRQ3 Handler
0x000AjmpINT4; IRQ4 Handler
0x000CjmpINT5; IRQ5 Handler
0x000EjmpINT6; IRQ6 Handler
0x0010jmpINT7; IRQ7 Handler
0x0012jmpPCINT0; PCINT0 Handler
0x0014jmpPCINT1; PCINT1 Handler
0x0016jmpPCINT2; PCINT2 Handler
0X0018jmpWDT; Watchdog Timeout Handler
0x001AjmpTIM2_COMPA; Timer2 CompareA Handler
0x001CjmpTIM2_COMPB; Timer2 CompareB Handler
0x001EjmpTIM2_OVF; Timer2 Overflow Handler
0x0020jmpTIM1_CAPT; Timer1 Capture Handler
0x0022jmpTIM1_COMPA; Timer1 CompareA Handler
0x0024jmpTIM1_COMPB; Timer1 CompareB Handler
0x0026jmpTIM1_COMPC; Timer1 CompareC Handler
0x0028jmpTIM1_OVF; Timer1 Overflow Handler
0x002AjmpTIM0_COMPA; Timer0 CompareA Handler
0x002CjmpTIM0_COMPB; Timer0 CompareB Handler
0x002EjmpTIM0_OVF; Timer0 Overflow Handler
0x0030jmpSPI_STC; SPI Transfer Complete Handler
0x0032jmpUSART0_RXC; USART0 RX Complete Handler
0x0034jmpUSART0_UDRE; USART0,UDR Empty Handler
0x0036jmpUSART0_TXC; USART0 TX Complete Handler
0x0038jmpANA_COMP; Analog Comparator Handler
0x003AjmpADC; ADC Conversion Complete Handler
0x003CjmpEE_RDY; EEPROM Ready Handler
0x003EjmpTIM3_CAPT; Timer3 Capture Handler
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71
0x0040jmpTIM3_COMPA; Timer3 CompareA Handler
0x0042jmpTIM3_COMPB; Timer3 CompareB Handler
0x0044jmpTIM3_COMPC; Timer3 CompareC Handler
0x0046jmpTIM3_OVF; Timer3 Overflow Handler
0x0048jmpUSART1_RXC; USART1 RX Complete Handler
0x004AjmpUSART1_UDRE; USART1,UDR Empty Handler
0x004CjmpUSART1_TXC; USART1 TX Complete Handler
0x004EjmpTWI; 2-wire Serial Handler
0x0050jmpSPM_RDY; SPM Ready Handler
0x0052jmpTIM4_CAPT; Timer4 Capture Handler
0x0054jmpTIM4_COMPA; Timer4 CompareA Handler
0x0056jmpTIM4_COMPB; Timer4 CompareB Handler
0x0058jmpTIM4_COMPC; Timer4 CompareC Handler
0x005AjmpTIM4_OVF; Timer4 Overflow Handler
0x005CjmpTIM5_CAPT; Timer5 Capture Handler
0x005EjmpTIM5_COMPA; Timer5 CompareA Handler
0x0060jmpTIM5_COMPB; Timer5 CompareB Handler
0x0062jmpTIM5_COMPC; Timer5 CompareC Handler
0x0064jmpTIM5_OVF; Timer5 Overflow Handler
0x0066jmpUSART2_RXC; USART2 RX Complete Handler
0x0068jmpUSART2_UDRE; USART2,UDR Empty Handler
0x006AjmpUSART2_TXC; USART2 TX Complete Handler
0x006CjmpUSART3_RXC; USART3 RX Complete Handler
0x006EjmpUSART3_UDRE; USART3,UDR Empty Handler
0x0070jmpUSART3_TXC; USART3 TX Complete Handler
;
0x0072RESET:ldir16, high(RAMEND); Main program start
0x0073outSPH,r16; Set Stack Pointer to top of RAM
0x0074ldir16, low(RAMEND)
0x0075outSPL,r16
0x0076sei; Enable interrupts
0x0077<instr> xxx
............
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When the BOOTRST Fuse is unprogrammed, the Boot section size set to 8K bytes and
the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most
typical and general program setup for the Reset and Interrupt Vector Addresses is:
AddressLabels CodeComments
0x00000RESET: ldir16,high(RAMEND) ; Main program start
0x00001outSPH,r16; Set Stack Pointer to top of RAM
0x00002ldir16,low(RAMEND)
0x00003outSPL,r16
0x00004sei; Enable interrupts
0x00005<instr> xxx
;
.org 0x1F002
0x1F002jmpEXT_INT0; IRQ0 Handler
0x1F004jmpEXT_INT1; IRQ1 Handler
.........;
0x1FO70jmpUSART3_TXC; USART3 TX Complete Handler
When the BOOTRST Fuse is programmed and the Boot section size set to 8K bytes, the
most typical and general program setup for the Reset and Interrupt Vector Addresses is:
AddressLabels CodeComments
.org 0x0002
0x00002jmpEXT_INT0; IRQ0 Handler
0x00004jmpEXT_INT1; IRQ1 Handler
.........;
0x00070jmpUSART3_TXC; USART3 TX Complete Handler
;
.org 0x1F000
0x1F000RESET: ldir16,high(RAMEND) ; Main program start
0x1F001outSPH,r16; Set Stack Pointer to top of RAM
0x1F002ldir16,low(RAMEND)
0x1F003outSPL,r16
0x1F004sei; Enable interrupts
0x1F005<instr> xxx
2549K–AVR–01/07
73
When the BOOTRST Fuse is programmed, the Boot section size set to 8K bytes and the
IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is:
0x1F072RESET: ldir16,high(RAMEND) ; Main program start
0x1F073outSPH,r16; Set Stack Pointer to top of RAM
0x1F074ldir16,low(RAMEND)
0x1F075outSPL,r16
0x1F076sei; Enable interrupts
0x1FO77<instr> xxx
Moving Interrupts
Between Application and
Boot Section
The MCU Control Register controls the placement of the Interrupt Vector table, see
Code Example below. For more details, see “Reset and Interrupt Handling” on page 17.
Assembly Code Example
Move_interrupts:
; Get MCUCR
in r16, MCUCR
mov r17, r16
; Enable change of Interrupt Vectors
ori r16, (1<<IVCE)
out MCUCR, r16
; Move interrupts to Boot Flash section
ori r16, (1<<IVSEL)
out MCUCR, r17
ret
C Code Example
void Move_interrupts(void)
{
uchar temp;
/* Get MCUCR*/
temp = MCUCR;
/* Enable change of Interrupt Vectors */
MCUCR = temp|(1<<IVCE);
/* Move interrupts to Boot Flash section */
MCUCR = temp|(1<<IVSEL);
}
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Register Description
MCUCR – MCU Control
Register
Bit76543210
0x35 (0x55)
Read/WriteR/WRRR/WRRR/WR/W
Initial Value00000000
JTD––PUD––IVSELIVCEMCUCR
• Bit 1 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the
Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of the Flash. The actual address of the start of the Boot
Flash Section is determined by the BOOTSZ Fuses. Refer to the section “Memory Programming” on page 342 for details. To avoid unintentional changes of Interrupt Vector
tables, a special write procedure must be followed to change the IVSEL bit (see “Moving
Interrupts Between Application and Boot Section” on page 74):
1.Write the Interrupt Vector Change Enable (IVCE) bit to one.
2.Within four cycles, write the desired value to IVSEL while writing a zero to
IVCE.
Interrupts will automatically be disabled while this sequence is executed. Interrupts are
disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four
cycles. The I-bit in the Status Register is unaffected by the automatic disabling.
Note:If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is pro-
grammed, interrupts are disabled while executing from the Application section. If
Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to
the section “Memory Programming” on page 342 for details on Boot Lock bits.
• Bit 0 – IVCE: Interrupt Vector Change Enable
The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is
cleared by hardware four cycles after it is written or when IVSEL is written. Setting the
IVCE bit will disable interrupts, as explained in the IVSEL description.
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External InterruptsThe External Interrupts are triggered by the INT7:0 pin or any of the PCINT23:0 pins.
Observe that, if enabled, the interrupts will trigger even if the INT7:0 or PCINT23:0 pins
are configured as outputs. This feature provides a way of generating a software
interrupt.
The Pin change interrupt PCI2 will trigger if any enabled PCINT23:16 pin toggles, Pin
change interrupt PCI1 if any enabled PCINT15:8 toggles and Pin change interrupts
PCI0 will trigger if any enabled PCINT7:0 pin toggles. PCMSK2, PCMSK1 and PCMSK0
Registers control which pins contribute to the pin change interrupts. Pin change interrupts on PCINT23 :0 are detected asynchronously. This implies that these interrupts can
be used for waking the part also from sleep modes other than Idle mode.
The External Interrupts can be triggered by a falling or rising edge or a low level. This is
set up as indicated in the specification for the External Interrupt Control Registers –
EICRA (INT3:0) and EICRB (INT7:4). When the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Note
that recognition of falling or rising edge interrupts on INT7:4 requires the presence of an
I/O clock, described in “Overview” on page 37. Low level interrupts and the edge interrupt on INT3:0 are detected asynchronously. This implies that these interrupts can be
used for waking the part also from sleep modes other than Idle mode. The I/O clock is
halted in all sleep modes except Idle mode.
Note that if a level triggered interrupt is used for wake-up from Power-down, the
required level must be held long enough for the MCU to complete the wake-up to trigger
the level interrupt. If the level disappears before the end of the Start-up Time, the MCU
will still wake up, but no interrupt will be generated. The start-up time is defined by the
SUT and CKSEL Fuses as described in “System Clock and Clock Options” on page 37.
Pin Change Interrupt
Timing
An example of timing of a pin change interrupt is shown in Figure 31.
Figure 31. Normal pin change interrupt.
PCINT(0)
clk
LE
pin_lat
D Q
pin_sync
PCINT(0) in PCMSK(x)
pcint_in_(0)
0
x
clk
pcint_syn
clk
PCINT(n)
pin_lat
pin_sync
pcint_in_(n)
pcint_syn
pcint_setflag
pcint_setflag
PCIF
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PCIF
77
Register Description
EICRA – External Interrupt
Control Register A
The External Interrupt Control Register A contains control bits for interrupt sense
control.
• Bits 7:0 – ISC31, ISC30 – ISC00, ISC00: External Interrupt 3 - 0 Sense Control
Bits
The External Interrupts 3 - 0 are activated by the external pins INT3:0 if the SREG I-flag
and the corresponding interrupt mask in the EIMSK is set. The level and edges on the
external pins that activate the interrupts are defined in Table 34. Edges on INT3:0 are
registered asynchronously. Pulses on INT3:0 pins wider than the minimum pulse width
given in Table 35 will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the
completion of the currently executing instruction to generate an interrupt. If enabled, a
level triggered interrupt will generate an interrupt request as long as the pin is held low.
When changing the ISCn bit, an interrupt can occur. Therefore, it is recommended to
first disable INTn by clearing its Interrupt Enable bit in the EIMSK Register. Then, the
ISCn bit can be changed. Finally, the INTn interrupt flag should be cleared by writing a
logical one to its Interrupt Flag bit (INTFn) in the EIFR Register before the interrupt is reenabled.
Table 34. Interrupt Sense Control
(1)
ISCn1ISCn0Description
00The low level of INTn generates an interrupt request.
01Any edge of INTn generates asynchronously an interrupt request.
10The falling edge of INTn generates asynchronously an interrupt request.
11The rising edge of INTn generates asynchronously an interrupt request.
Note:1. n = 3, 2, 1or 0.
When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its
Interrupt Enable bit in the EIMSK Register. Otherwise an interrupt can occur when
the bits are changed.
• Bits 7:0 – ISC71, ISC70 - ISC41, ISC40: External Interrupt 7 - 4 Sense Control
Bits
The External Interrupts 7 - 4 are activated by the external pins INT7:4 if the SREG I-flag
and the corresponding interrupt mask in the EIMSK is set. The level and edges on the
external pins that activate the interrupts are defined in Table 36. The value on the
INT7:4 pins are sampled before detecting edges. If edge or toggle interrupt is selected,
pulses that last longer than one clock period will generate an interrupt. Shorter pulses
are not guaranteed to generate an interrupt. Observe that CPU clock frequency can be
lower than the XTAL frequency if the XTAL divider is enabled. If low level interrupt is
selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an
interrupt request as long as the pin is held low.
EIMSK – External Interrupt
Mask Register
Table 36. Interrupt Sense Control
ISCn1ISCn0Description
00The low level of INTn generates an interrupt request.
01Any logical change on INTn generates an interrupt request
10
11
Note:1. n = 7, 6, 5 or 4.
When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its
Interrupt Enable bit in the EIMSK Register. Otherwise an interrupt can occur when
the bits are changed.
Bit76543210
0x1D (0x3D)INT7INT6INT5INT4INT3INT2INT1INT0EIMSK
Read/WriteR/WR/WR/WR/WR/WR/WR/WR/W
Initial Value00000000
The falling edge between two samples of INTn generates an interrupt
request.
The rising edge between two samples of INTn generates an interrupt
request.
When an INT7:0 bit is written to one and the I-bit in the Status Register (SREG) is set
(one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control
bits in the External Interrupt Control Registers – EICRA and EICRB – defines whether
the external interrupt is activated on rising or falling edge or level sensed. Activity on any
of these pins will trigger an interrupt request even if the pin is enabled as an output. This
provides a way of generating a software interrupt.
When an edge or logic change on the INT7:0 pin triggers an interrupt request, INTF7:0
becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit,
INT7:0 in EIMSK, are set (one), the MCU will jump to the interrupt vector. The flag is
cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by
writing a logical one to it. These flags are always cleared when INT7:0 are configured as
level interrupt. Note that when entering sleep mode with the INT3:0 interrupts disabled,
the input buffers on these pins will be disabled. This may cause a logic change in internal signals which will set the INTF3:0 flags. See “Digital Input Enable and Sleep Modes”
on page 87 for more information.
PCICR – Pin Change Interrupt
Control Register
Bit76543210
(0x68)
Read/WriteRRRRRR/WR/WR/W
Initial Value00000000
–––––PCIE2PCIE1PCIE0PCICR
• Bit 2 – PCIE2: Pin Change Interrupt Enable 1
When the PCIE2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
pin change interrupt 2 is enabled. Any change on any enabled PCINT23:16 pin will
cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI2 Interrupt Vector. PCINT23:16 pins are enabled individually by the
PCMSK2 Register.
• Bit 1 – PCIE1: Pin Change Interrupt Enable 1
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
pin change interrupt 1 is enabled. Any change on any enabled PCINT15:8 pin will cause
an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed
from the PCI1 Interrupt Vector. PCINT15:8 pins are enabled individually by the PCMSK1
Register.
• Bit 0 – PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
pin change interrupt 0 is enabled. Any change on any enabled PCINT7:0 pin will cause
an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed
from the PCI0 Interrupt Vector. PCINT7:0 pins are enabled individually by the PCMSK0
Register.
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ATmega640/1280/1281/2560/2561
PCIFR – Pin Change Interrupt
Flag Register
Bit76543210
0x1B (0x3B)
Read/WriteRRRRRR/WR/WR/W
Initial Value00000000
–––––PCIF2PCIF1PCIF0PCIFR
• Bit 2 – PCIF2: Pin Change Interrupt Flag 1
When a logic change on any PCINT23:16 pin triggers an interrupt request, PCIF2
becomes set (one). If the I-bit in SREG and the PCIE2 bit in PCICR are set (one), the
MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to
it.
• Bit 1 – PCIF1: Pin Change Interrupt Flag 1
When a logic change on any PCINT15:8 pin triggers an interrupt request, PCIF1
becomes set (one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the
MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to
it.
• Bit 0 – PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT7:0 pin triggers an interrupt request, PCIF0
becomes set (one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the
MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to
it.
• Bit 7:0 – PCINT23:16: Pin Change Enable Mask 23:16
Each PCINT23:16-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT23:16 is set and the PCIE2 bit in PCICR is set, pin change
interrupt is enabled on the corresponding I/O pin. If PCINT23:16 is cleared, pin change
interrupt on the corresponding I/O pin is disabled.
• Bit 7:0 – PCINT15:8: Pin Change Enable Mask 15:8
Each PCINT15:8-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT15:8 is set and the PCIE1 bit in EIMSK is set, pin change interrupt is
enabled on the corresponding I/O pin. If PCINT15:8 is cleared, pin change interrupt on
the corresponding I/O pin is disabled.
Each PCINT7:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7:0 is set and the PCIE0 bit in PCICR is set, pin change interrupt is
enabled on the corresponding I/O pin. If PCINT7:0 is cleared, pin change interrupt on
the corresponding I/O pin is disabled.
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I/O-Ports
IntroductionAll AVR ports have true Read-Modify-Write functionality when used as general digital
I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The
same applies when changing drive value (if configured as output) or enabling/disabling
of pull-up resistors (if configured as input). Each output buffer has symmetrical drive
characteristics with both high sink and source capability. The pin driver is strong enough
to drive LED displays directly. All port pins have individually selectable pull-up resistors
with a supply-voltage invariant resistance. All I/O pins have protection diodes to both
V
and Ground as indicated in Figure 32. Refer to “Electrical Characteristics” on page
CC
374 for a complete list of parameters.
Figure 32. I/O Pin Equivalent Schematic
R
pu
Pxn
C
pin
All registers and bit references in this section are written in general form. A lower case
“x” represents the numbering letter for the port, and a lower case “n” represents the bit
number. However, when using the register or bit defines in a program, the precise form
must be used. For example, PORTB3 for bit no. 3 in Port B, here documented generally
as PORTxn. The physical I/O Registers and bit locations are listed in “Table 70 and
Table 71 relates the alternate functions of Port L to the overriding signals shown in Figure 36 on page 89.” on page 114.
Three I/O memory address locations are allocated for each port, one each for the Data
Register – PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The
Port Input Pins I/O location is read only, while the Data Register and the Data Direction
Register are read/write. However, writing a logic one to a bit in the PINx Register, will
result in a toggle in the corresponding bit in the Data Register. In addition, the Pull-up
Disable – PUD bit in MCUCR disables the pull-up function for all pins in all ports when
set.
See Figure
"General Digital I/O" for
Logic
Details
2549K–AVR–01/07
Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” on
page 84. Most port pins are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes with the port pin is described
in “Alternate Port Functions” on page 89. Refer to the individual module sections for a
full description of the alternate functions.
83
Note that enabling the alternate function of some of the port pins does not affect the use
of the other pins in the port as general digital I/O.
Ports as General Digital
I/O
The ports are bi-directional I/O ports with optional internal pull-ups. Figure 33 shows a
functional description of one I/O-port pin, here generically called Pxn.
Figure 33. General Digital I/O
Pxn
(1)
SLEEP
SYNCHRONIZER
DLQ
D
PINxn
Q
PUD
Q
D
DDxn
Q
CLR
RESET
D
Q
PORTxn
Q
CLR
RESET
Q
Q
RRx
WDx
RDx
RPx
1
0
DATA BUS
WRx
WPx
clk
I/O
WDx:WRITE DDRx
PUD:PULLUP DISABLE
SLEEP:SLEEP CONTROL
:I/O CLOCK
clk
I/O
RDx:READ DDRx
WRx:WRITE PORTx
RRx:READ PORTx REGISTER
RPx:READ PORTx PIN
WPx:WRITE PINx REGISTER
Note:1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port.
clk
, SLEEP, and PUD are common to all ports.
I/O
Configuring the PinEach port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in
“Table 70 and Table 71 relates the alternate functions of Port L to the overriding signals
shown in Figure 36 on page 89.” on page 114, the DDxn bits are accessed at the DDRx
I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx
I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written
logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up
resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic
zero or the pin has to be configured as an output pin. The port pins are tri-stated when
reset condition becomes active, even if no clocks are running.
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is
driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero).
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Toggli n g t h e P i nWriting a logic one to PINxn toggles the value of PORTxn, independent on the value of
DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port.
Switching Between Input and
Output
When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn,
PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} =
0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up
enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in
the MCUCR Register can be set to disable all pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The
user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state
({DDxn, PORTxn} = 0b11) as an intermediate step.
Table 37 summarizes the control signals for the pin value.
Table 37. Port Pin Configurations
DDxn
00XInputNoTri-state (Hi-Z)
010InputYesPxn will source current if ext. pulled low.
011 Input NoTri-state (Hi-Z)
10XOutputNoOutput Low (Sink)
11XOutputNoOutput High (Source)
PORTxn
PUD
(in MCUCR)
I/OPull-upComment
Reading the Pin ValueIndependent of the setting of Data Direction bit DDxn, the port pin can be read through
the PINxn Register bit. As shown in Figure 33, the PINxn Register bit and the preceding
latch constitute a synchronizer. This is needed to avoid metastability if the physical pin
changes value near the edge of the internal clock, but it also introduces a delay. Figure
34 shows a timing diagram of the synchronization when reading an externally applied
pin value. The maximum and minimum propagation delays are denoted t
pd,max
and t
pd,min
respectively.
2549K–AVR–01/07
85
Figure 34. Synchronization when Reading an Externally Applied Pin value
SYSTEM CLK
INSTRUCTIONS
XXXin r17, PINx
XXX
SYNC LATCH
PINxn
r17
0x000xFF
t
pd, max
t
pd, min
Consider the clock period starting shortly after the first falling edge of the system clock.
The latch is closed when the clock is low, and goes transparent when the clock is high,
as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is
latched when the system clock goes low. It is clocked into the PINxn Register at the suc-
ceeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a
single signal transition on the pin will be delayed between ½ and 1½ system clock
period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as
indicated in Figure 35. The out instruction sets the “SYNC LATCH” signal at the positive
edge of the clock. In this case, the delay tpd through the synchronizer is 1 system clock
period.
Figure 35. Synchronization when Reading a Software Assigned Pin Value
SYSTEM CLK
r16
INSTRUCTIONS
out PORTx, r16nopin r17, PINx
0xFF
SYNC LATCH
PINxn
r17
0x000xFF
t
pd
The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and
define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The
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ATmega640/1280/1281/2560/2561
resulting pin values are read back again, but as previously discussed, a nop instruction
is included to be able to read back the value recently assigned to some of the pins.
Assembly Code Example
...
; Define pull-ups and set outputs high
; Define directions for port pins
ldir16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0)
ldir17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)
outPORTB,r16
outDDRB,r17
; Insert nop for synchronization
nop
; Read port pins
inr16,PINB
...
(1)
C Code Example
unsigned char i;
...
/* Define pull-ups and set outputs high */
/* Define directions for port pins */
PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0);
DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);
/* Insert nop for synchronization*/
__no_operation();
/* Read port pins */
i = PINB;
...
Digital Input Enable and Sleep
Modes
2549K–AVR–01/07
Note:1. For the assembly program, two temporary registers are used to minimize the time
from pull-ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set,
defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers.
As shown in Figure 33, the digital input signal can be clamped to ground at the input of
the schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep
Controller in Power-down mode, Power-save mode, and Standby mode to avoid high
power consumption if some input signals are left floating, or have an analog signal level
close to V
CC
/2.
SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt request is not enabled, SLEEP is active also for these pins. SLEEP is also
overridden by various other alternate functions as described in “Alternate Port Functions” on page 89.
If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as “Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the
external interrupt is not enabled, the corresponding External Interrupt Flag will be set
when resuming from the above mentioned Sleep mode, as the clamping in these sleep
mode produces the requested logic change.
87
Unconnected PinsIf some pins are unused, it is recommended to ensure that these pins have a defined
level. Even though most of the digital inputs are disabled in the deep sleep modes as
described above, floating inputs should be avoided to reduce current consumption in all
other modes where the digital inputs are enabled (Reset, Active mode and Idle mode).
The simplest method to ensure a defined level of an unused pin, is to enable the internal
pull-up. In this case, the pull-up will be disabled during reset. If low power consumption
during reset is important, it is recommended to use an external pull-up or pull-down.
Connecting unused pins directly to V
cause excessive currents if the pin is accidentally configured as an output.
or GND is not recommended, since this may
CC
88
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ATmega640/1280/1281/2560/2561
Alternate Port FunctionsMost port pins have alternate functions in addition to being general digital I/Os. Figure
36 shows how the port pin control signals from the simplified Figure 33 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but
the figure serves as a generic description applicable to all port pins in the AVR microcontroller family.
Figure 36. Alternate Port Functions
PUOExn
1
0
1
0
Pxn
1
0
1
0
PUOVxn
DDOExn
DDOVxn
PVOExn
PVOVxn
DIEOExn
DIEOVxn
SLEEP
(1)
SYNCHRONIZER
SET
DLQ
Q
CLR
D
PINxn
CLR
Q
PORTxn
Q
CLR
RESET
Q
Q
RESET
D
Q
Q
DDxn
PUD
D
CLR
WDx
RDx
1
0
RRx
RPx
clk
I/O
WRx
PTOExn
WPx
DATA B U S
DIxn
AIOxn
PUOExn: Pxn PULL-UP OVERRIDE ENABLE
PUOVxn: Pxn PULL-UP OVERRIDE VALUE
DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE
DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE
PVOExn: Pxn PORT VALUE OVERRIDE ENABLE
PVOVxn: Pxn PORT VALUE OVERRIDE VALUE
DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE
DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE
SLEEP:SLEEP CONTROL
PTOExn: Pxn, PORT TOGGLE OVERRIDE ENABLE
DIxn: DIGITAL INPUT PIN n ON PORTx
AIOxn: ANALOG INPUT/OUTPUT PIN n ON PORTx
Note:1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port.
clk
, SLEEP, and PUD are common to all ports. All other signals are unique for each
I/O
pin.
2549K–AVR–01/07
89
Table 38 summarizes the function of the overriding signals. The pin and port indexes
from Figure 36 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function.
Table 38. Generic Description of Overriding Signals for Alternate Functions
Signal NameFull NameDescription
PUOEPull-up Override
Enable
PUOVPull-up Override
Valu e
DDOEData Direction
Override Enable
DDOVData Direction
Override Value
PVOEPort Value
Override Enable
PVOVPort Value
Override Value
PTOEPort Toggle
Override Enable
DIEOEDigital Input
Enable Override
Enable
DIEOVDigital Input
Enable Override
Valu e
DIDigital InputThis is the Digital Input to alternate functions. In the
If this signal is set, the pull-up enable is controlled by the
PUOV signal. If this signal is cleared, the pull-up is
enabled when {DDxn, PORTxn, PUD} = 0b010.
If PUOE is set, the pull-up is enabled/disabled when
PUOV is set/cleared, regardless of the setting of the
DDxn, PORTxn, and PUD Register bits.
If this signal is set, the Output Driver Enable is controlled
by the DDOV signal. If this signal is cleared, the Output
driver is enabled by the DDxn Register bit.
If DDOE is set, the Output Driver is enabled/disabled
when DDOV is set/cleared, regardless of the setting of
the DDxn Register bit.
If this signal is set and the Output Driver is enabled, the
port value is controlled by the PVOV signal. If PVOE is
cleared, and the Output Driver is enabled, the port Value
is controlled by the PORTxn Register bit.
If PVOE is set, the port value is set to PVOV, regardless
of the setting of the PORTxn Register bit.
If PTOE is set, the PORTxn Register bit is inverted.
If this bit is set, the Digital Input Enable is controlled by
the DIEOV signal. If this signal is cleared, the Digital Input
Enable is determined by MCU state (Normal mode, sleep
mode).
If DIEOE is set, the Digital Input is enabled/disabled when
DIEOV is set/cleared, regardless of the MCU state
(Normal mode, sleep mode).
figure, the signal is connected to the output of the schmitt
trigger but before the synchronizer. Unless the Digital
Input is used as a clock source, the module with the
alternate function will use its own synchronizer.
90
AIOAnalog
Input/Output
This is the Analog Input/output to/from alternate
functions. The signal is connected directly to the pad, and
can be used bi-directionally.
The following subsections shortly describe the alternate functions for each port, and
relate the overriding signals to the alternate function. Refer to the alternate function
description for further details.
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ATmega640/1280/1281/2560/2561
Alternate Functions of Port AThe Port A has an alternate function as the address low byte and data lines for the
External Memory Interface.
Table 39. Port A Pins Alternate Functions
Port PinAlternate Function
PA7AD7 (External memory interface address and data bit 7)
PA6AD6 (External memory interface address and data bit 6)
PA5AD5 (External memory interface address and data bit 5)
PA4AD4 (External memory interface address and data bit 4)
PA3AD3 (External memory interface address and data bit 3)
PA2AD2 (External memory interface address and data bit 2)
PA1AD1 (External memory interface address and data bit 1)
PA0AD0 (External memory interface address and data bit 0)
Table 40 and Table 41 relates the alternate functions of Port A to the overriding signals
shown in Figure 36 on page 89.
Table 40. Overriding Signals for Alternate Functions in PA7:PA4
Signal
NamePA7/AD7PA6/AD6PA5/AD5PA4/AD4
PUOESRESRESRESRE
PUOV~(WR | ADA
PORTA7 • PUD
DDOESRESRESRESRE
DDOVWR
PVOESRESRESRESRE
PVOVA7 • ADA | D7
DIEOE0000
DIEOV0000
DID7 INPUTD6 INPUTD5 INPUTD4 INPUT
AIO––––
Note:1. ADA is short for ADdress Active and represents the time when address is output. See
| ADAWR | ADAWR | ADAWR | ADA
OUTPUT • WR
“External Memory Interface” on page 26 for details.
(1)
) •
~(WR | ADA) •
PORTA6 • PUD
A6 • ADA | D6
OUTPUT • WR
~(WR | ADA) •
PORTA5 • PUD
A5 • ADA | D5
OUTPUT • WR
~(WR | ADA) •
PORTA4 • PUD
A4 • ADA | D4
OUTPUT • WR
2549K–AVR–01/07
91
Table 41. Overriding Signals for Alternate Functions in PA3:PA0
Signal
NamePA3/AD3PA2/AD2PA1/AD1PA0/AD0
PUOESRESRESRESRE
PUOV~(WR | ADA) •
PORTA3 • PUD
DDOESRESRESRESRE
DDOVWR
PVOESRESRESRESRE
PVOVA3 • ADA | D3
DIEOE0000
DIEOV0000
DID3 INPUTD2 INPUTD1 INPUTD0 INPUT
AIO––––
| ADAWR | ADAWR | ADAWR | ADA
OUTPUT • WR
~(WR | ADA) •
PORTA2 • PUD
A2• ADA | D2
OUTPUT • WR
~(WR | ADA) •
PORTA1 • PUD
A1 • ADA | D1
OUTPUT • WR
Alternate Functions of Port BThe Port B pins with alternate functions are shown in Table 42.
Table 42. Port B Pins Alternate Functions
Port PinAlternate Functions
PB7
PB6
OC0A/OC1C/PCINT7 (Output Compare and PWM Output A for Timer/Counter0,
Output Compare and PWM Output C for Timer/Counter1 or Pin Change Interrupt 7)
OC1B/PCINT6 (Output Compare and PWM Output B for Timer/Counter1 or Pin
Change Interrupt 6)
~(WR | ADA) •
PORTA0 • PUD
A0 • ADA | D0
OUTPUT • WR
PB5
PB4
PB3MISO/PCINT3 (SPI Bus Master Input/Slave Output or Pin Change Interrupt 3)
PB2MOSI/PCINT2 (SPI Bus Master Output/Slave Input or Pin Change Interrupt 2)
PB1SCK/PCINT1 (SPI Bus Serial Clock or Pin Change Interrupt 1)
PB0SS
OC1A/PCINT5 (Output Compare and PWM Output A for Timer/Counter1 or Pin
Change Interrupt 5)
OC2A/PCINT4 (Output Compare and PWM Output A for Timer/Counter2 or Pin
Change Interrupt 4)
/PCINT0 (SPI Slave Select input or Pin Change Interrupt 0)
The alternate pin configuration is as follows:
• OC0A/OC1C/PCINT7, Bit 7
OC0A, Output Compare Match A output: The PB7 pin can serve as an external output
for the Timer/Counter0 Output Compare. The pin has to be configured as an output
(DDB7 set “one”) to serve this function. The OC0A pin is also the output pin for the PWM
mode timer function.
OC1C, Output Compare Match C output: The PB7 pin can serve as an external output
for the Timer/Counter1 Output Compare C. The pin has to be configured as an output
(DDB7 set (one)) to serve this function. The OC1C pin is also the output pin for the
PWM mode timer function.
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PCINT7, Pin Change Interrupt source 7: The PB7 pin can serve as an external interrupt
source.
• OC1B/PCINT6, Bit 6
OC1B, Output Compare Match B output: The PB6 pin can serve as an external output
for the Timer/Counter1 Output Compare B. The pin has to be configured as an output
(DDB6 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM
mode timer function.
PCINT6, Pin Change Interrupt source 6: The PB6 pin can serve as an external interrupt
source.
• OC1A/PCINT5, Bit 5
OC1A, Output Compare Match A output: The PB5 pin can serve as an external output
for the Timer/Counter1 Output Compare A. The pin has to be configured as an output
(DDB5 set (one)) to serve this function. The OC1A pin is also the output pin for the PWM
mode timer function.
PCINT5, Pin Change Interrupt source 5: The PB5 pin can serve as an external interrupt
source.
• OC2A/PCINT4, Bit 4
OC2A, Output Compare Match output: The PB4 pin can serve as an external output for
the Timer/Counter2 Output Compare. The pin has to be configured as an output (DDB4
set (one)) to serve this function. The OC2A pin is also the output pin for the PWM mode
timer function.
PCINT4, Pin Change Interrupt source 4: The PB4 pin can serve as an external interrupt
source.
• MISO/PCINT3 – Port B, Bit 3
MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is
enabled as a master, this pin is configured as an input regardless of the setting of
DDB3. When the SPI is enabled as a slave, the data direction of this pin is controlled by
DDB3. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB3 bit.
PCINT3, Pin Change Interrupt source 3: The PB3 pin can serve as an external interrupt
source.
• MOSI/PCINT2 – Port B, Bit 2
MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is
enabled as a slave, this pin is configured as an input regardless of the setting of DDB2.
When the SPI is enabled as a master, the data direction of this pin is controlled by
DDB2. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB2 bit.
2549K–AVR–01/07
PCINT2, Pin Change Interrupt source 2: The PB2 pin can serve as an external interrupt
source.
• SCK/PCINT1 – Port B, Bit 1
SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is
enabled as a slave, this pin is configured as an input regardless of the setting of DDB1.
93
When the SPI0 is enabled as a master, the data direction of this pin is controlled by
DDB1. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB1 bit.
PCINT1, Pin Change Interrupt source 1: The PB1 pin can serve as an external interrupt
source.
•SS
/PCINT0 – Port B, Bit 0
SS
: Slave Port Select input. When the SPI is enabled as a slave, this pin is configured
as an input regardless of the setting of DDB0. As a slave, the SPI is activated when this
pin is driven low. When the SPI is enabled as a master, the data direction of this pin is
controlled by DDB0. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 bit.
Table 43 and Table 44 relate the alternate functions of Port B to the overriding signals
shown in Figure 36 on page 89. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute
the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE
INPUT.
PCINT0, Pin Change Interrupt source 0: The PB0 pin can serve as an external interrupt
source.
Table 43. Overriding Signals for Alternate Functions in PB7:PB4
Alternate Functions of Port DThe Port D pins with alternate functions are shown in Table 48.
Table 48. Port D Pins Alternate Functions
Port PinAlternate Function
PD7T0 (Timer/Counter0 Clock Input)
PD6T1 (Timer/Counter1 Clock Input)
PD5XCK1 (USART1 External Clock Input/Output)
PD4ICP1 (Timer/Counter1 Input Capture Trigger)
PD3INT3/TXD1 (External Interrupt3 Input or USART1 Transmit Pin)
PD2INT2/RXD1 (External Interrupt2 Input or USART1 Receive Pin)
PD1INT1/SDA (External Interrupt1 Input or TWI Serial DAta)
PD0INT0/SCL (External Interrupt0 Input or TWI Serial CLock)
The alternate pin configuration is as follows:
• T0 – Port D, Bit 7
T0, Timer/Counter0 counter source.
• T1 – Port D, Bit 6
T1, Timer/Counter1 counter source.
• XCK1 – Port D, Bit 5
XCK1, USART1 External clock. The Data Direction Register (DDD5) controls whether
the clock is output (DDD5 set) or input (DDD5 cleared). The XCK1 pin is active only
when the USART1 operates in Synchronous mode.
• ICP1 – Port D, Bit 4
ICP1 – Input Capture Pin 1: The PD4 pin can act as an input capture pin for
Timer/Counter1.
• INT3/TXD1 – Port D, Bit 3
INT3, External Interrupt source 3: The PD3 pin can serve as an external interrupt source
to the MCU.
TXD1, Transmit Data (Data output pin for the USART1). When the USART1 Transmitter
is enabled, this pin is configured as an output regardless of the value of DDD3.
• INT2/RXD1 – Port D, Bit 2
INT2, External Interrupt source 2. The PD2 pin can serve as an External Interrupt
source to the MCU.
2549K–AVR–01/07
RXD1, Receive Data (Data input pin for the USART1). When the USART1 receiver is
enabled this pin is configured as an input regardless of the value of DDD2. When the
USART forces this pin to be an input, the pull-up can still be controlled by the PORTD2
bit.
97
• INT1/SDA – Port D, Bit 1
INT1, External Interrupt source 1. The PD1 pin can serve as an external interrupt source
to the MCU.
SDA, 2-wire Serial Interface Data: When the TWEN bit in TWCR is set (one) to enable
the 2-wire Serial Interface, pin PD1 is disconnected from the port and becomes the
Serial Data I/O pin for the 2-wire Serial Interface. In this mode, there is a spike filter on
the pin to suppress spikes shorter than 50 ns on the input signal, and the pin is driven by
an open drain driver with slew-rate limitation.
•INT0/SCL – Port D, Bit 0
INT0, External Interrupt source 0. The PD0 pin can serve as an external interrupt source
to the MCU.
SCL, 2-wire Serial Interface Clock: When the TWEN bit in TWCR is set (one) to enable
the 2-wire Serial Interface, pin PD0 is disconnected from the port and becomes the
Serial Clock I/O pin for the 2-wire Serial Interface. In this mode, there is a spike filter on
the pin to suppress spikes shorter than 50 ns on the input signal, and the pin is driven by
an open drain driver with slew-rate limitation.
Table 49 and Table 50 relates the alternate functions of Port D to the overriding signals
shown in Figure 36 on page 89.
Table 49. Overriding Signals for Alternate Functions PD7:PD4
Signal NamePD7/T0PD6/T1PD5/XCK1PD4/ICP1
PUOE0000
PUOV0000
DDOE00XCK1 OUTPUT ENABLE0
DDOV0010
PVOE00XCK1 OUTPUT ENABLE0
PVOV00XCK1 OUTPUT0
DIEOE0000
DIEOV0000
DIT0 INPUTT1 INPUTXCK1 INPUTICP1 INPUT
AIO––––
98
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
ATmega640/1280/1281/2560/2561
Table 50. Overriding Signals for Alternate Functions in PD3:PD0
Signal NamePD3/INT3/TXD1PD2/INT2/RXD1PD1/INT1/SDAPD0/INT0/SCL
PUOETXEN1RXEN1TWENTWEN
(1)
PUOV0PORTD2 • PUD
DDOETXEN1RXEN1TWENTWEN
DDOV10SDA_OUTSCL_OUT
PVOETXEN10TWENTWEN
PVOVTXD1000
DIEOEINT3 ENABLEINT2 ENABLEINT1 ENABLEINT0 ENABLE
DIEOV1111
DIINT3 INPUTINT2 INPUT/RXD1INT1 INPUTINT0 INPUT
AIO––SDA INPUTSCL INPUT
Note:1. When enabled, the 2-wire Serial Interface enables Slew-Rate controls on the output
pins PD0 and PD1. This is not shown in this table. In addition, spike filters are connected between the AIO outputs shown in the port figure and the digital logic of the
TWI module.
PORTD1 • PUDPORTD0 • PUD
Alternate Functions of Port EThe Port E pins with alternate functions are shown in Table 51.
Table 51. Port E Pins Alternate Functions
Port PinAlternate Function
PE7
PE6INT6/ T3 (External Interrupt 6 Input or Timer/Counter3 Clock Input)
PE5
PE4
INT7/ICP3/CLK0 (External Interrupt 7 Input, Timer/Counter3 Input Capture Trigger
or Divided System Clock)
INT5/OC3C (External Interrupt 5 Input or Output Compare and PWM Output C for
Timer/Counter3)
INT4/OC3B (External Interrupt4 Input or Output Compare and PWM Output B for
Timer/Counter3)
2549K–AVR–01/07
PE3
PE2
PE1PDO
PE0
Note:1. Only for ATmega1281/2561. For ATmega640/1280/2560 these functions are
AIN1/OC3A (Analog Comparator Negative Input or Output Compare and PWM
Output A for Timer/Counter3)
AIN0/XCK0 (Analog Comparator Positive Input or USART0 external clock
input/output)
(1)
/TXD0 (Programming Data Output or USART0 Transmit Pin)
(1)
/RXD0/PCINT8 (Programming Data Input, USART0 Receive Pin or Pin
PDI
Change Interrupt 8)
placed on MISO/MOSI pins.
• INT7/ICP3/CLKO – Port E, Bit 7
INT7, External Interrupt source 7: The PE7 pin can serve as an external interrupt
source.
ICP3, Input Capture Pin 3: The PE7 pin can act as an input capture pin for
Timer/Counter3.
99
CLKO - Divided System Clock: The divided system clock can be output on the PE7 pin.
The divided system clock will be output if the CKOUT Fuse is programmed, regardless
of the PORTE7 and DDE7 settings. It will also be output during reset.
• INT6/T3 – Port E, Bit 6
INT6, External Interrupt source 6: The PE6 pin can serve as an external interrupt
source.
T3, Timer/Counter3 counter source.
• INT5/OC3C – Port E, Bit 5
INT5, External Interrupt source 5: The PE5 pin can serve as an External Interrupt
source.
OC3C, Output Compare Match C output: The PE5 pin can serve as an External output
for the Timer/Counter3 Output Compare C. The pin has to be configured as an output
(DDE5 set “one”) to serve this function. The OC3C pin is also the output pin for the
PWM mode timer function.
• INT4/OC3B – Port E, Bit 4
INT4, External Interrupt source 4: The PE4 pin can serve as an External Interrupt
source.
OC3B, Output Compare Match B output: The PE4 pin can serve as an External output
for the Timer/Counter3 Output Compare B. The pin has to be configured as an output
(DDE4 set (one)) to serve this function. The OC3B pin is also the output pin for the PWM
mode timer function.
• AIN1/OC3A – Port E, Bit 3
AIN1 – Analog Comparator Negative input. This pin is directly connected to the negative
input of the Analog Comparator.
OC3A, Output Compare Match A output: The PE3 pin can serve as an External output
for the Timer/Counter3 Output Compare A. The pin has to be configured as an output
(DDE3 set “one”) to serve this function. The OC3A pin is also the output pin for the PWM
mode timer function.
• AIN0/XCK0 – Port E, Bit 2
AIN0 – Analog Comparator Positive input. This pin is directly connected to the positive
input of the Analog Comparator.
XCK0, USART0 External clock. The Data Direction Register (DDE2) controls whether
the clock is output (DDE2 set) or input (DDE2 cleared). The XCK0 pin is active only
when the USART0 operates in Synchronous mode.
• PDO/TXD0 – Port E, Bit 1
PDO, SPI Serial Programming Data Output. During Serial Program Downloading, this
pin is used as data output line for the ATmega1281/2561. For ATmega640/1280/2560
this function is placed on MISO.
TXD0, USART0 Transmit pin.
100
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
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