ATMEL ATmega640, ATmega640V, ATmega1280V, ATmega1281V, ATmega2560V User Manual
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Features
• High Performance, Low Power AVR
• Advanced RISC Architecture
– 135 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-Chip 2-cycle Multiplier
• Non-volatile Program and Data Memories
– 64K/128K/256K Bytes of In-System Self-Programmable Flash
Endurance: 10,000 Write/Erase Cycles
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– 4K Bytes EEPROM
Endurance: 100,000 Write/Erase Cycles
– 8K Bytes Internal SRAM
– Up to 64K Bytes Optional External Memory Space
– Programming Lock for Software Security
• JTAG (IEEE std. 1149.1 compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
• Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– Four 16-bit Timer/Counter with Separate Prescaler, Compare- and Capture Mode
– Real Time Counter with Separate Oscillator
– Four 8-bit PWM Channels
– Six/Twelve PWM Channels with Programmable Resolution from 2 to 16 Bits
(ATmega1281/2561, ATmega640/1280/2560)
– Output Compare Modulator
– 8/16-channel, 10-bit ADC (ATmega1281/2561, ATmega640/1280/2560)
– Two/Four Programmable Serial USART (ATmega1281/2561,ATmega640/1280/2560)
– Master/Slave SPI Serial Interface
– Byte Oriented 2-wire Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
• Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby,
and Extended Standby
• I/O and Packages
– 54/86 Programmable I/O Lines (ATmega1281/2561, ATmega640/1280/2560)
– 64-pad QFN/MLF, 64-lead TQFP (ATmega1281/2561)
– 100-lead TQFP, 100-ball CBGA (ATmega640/1280/2560)
– RoHS/Fully Green
• Temperature Range:
–-40°C to 85°C Industrial
• Ultra-Low Power Consumption
– Active Mode: 1 MHz, 1.8V: 510 µA
– Power-down Mode: 0.1 µA at 1.8V
• Speed Grade (see “Maximum speed vs. VCC” on page 377):
– ATmega640V/ATmega1280V/ATmega1281V:
0 - 4 MHz @ 1.8 - 5.5V, 0 - 8 MHz @ 2.7 - 5.5V
– ATmega2560V/ATmega2561V:
0 - 2 MHz @ 1.8 - 5.5V, 0 - 8 MHz @ 2.7 - 5.5V
– ATmega640/ATmega1280/ATmega1281:
0 - 8 MHz @ 2.7 - 5.5V, 0 - 16 MHz @ 4.5 - 5.5V
– ATmega2560/ATmega2561:
0 - 16 MHz @ 4.5 - 5.5V
®
8-Bit Microcontroller
8-bit
Microcontroller
with
64K/128K/256K
Bytes In-System
Programmable
Flash
ATmega640/V
ATmega1280/V
ATmega1281/V
ATmega2560/V
ATmega2561/V
Preliminary
2549K–AVR–01/07
Pin Configurations
Figure 1. TQFP-pinout ATmega640/1280/2560
8/PCINT16)
(OC0B) PG5
(RXD0/PCINT8) PE0
(TXD0) PE1
(XCK0/AIN0) PE2
(OC3A/AIN1) PE3
(OC3B/INT4) PE4
(OC3C/INT5) PE5
(T3/INT6) PE6
(CLKO/ICP3/INT7) PE7
VCC
GND
(RXD2) PH0
(TXD2) PH1
(XCK2) PH2
(OC4A) PH3
(OC4B) PH4
(OC4C) PH5
(OC2B) PH6
(SS/PCINT0) PB0
(SCK/PCINT1) PB1
(MOSI/PCINT2) PB2
(MISO/PCINT3) PB3
(OC2A/PCINT4) PB4
(OC1A/PCINT5) PB5
(OC1B/PCINT6) PB6
C
AVC
GND
AREF
PF1 (ADC1)
PF2 (ADC2)
PF3 (ADC3)
PF4 (ADC4/TCK)
PF0 (ADC0)
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 807978 77 76
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 28 29 3127 3630 32 35 3733 34 38 39 40 41 42 43 44 45 46 47 48 49 50
(T4) PH7
(TOSC2) PG3
INDEX CORNER
RESET
(TOSC1) PG4
PF5 (ADC5/TMS)
ATm ega640/1280/2560
VCC
GND
XTAL2
XTAL1
PK0 (ADC
PF6 (ADC6/TDO)
PF7 (ADC7/TDI)
(T5) PL2
(ICP4) PL0
(ICP5) PL1
PK1 (ADC9/PCINT17)
(OC5A) PL3
8)
PK2 (ADC10/PCINT1
PK3 (ADC11/PCINT19)
PK4 (ADC12/PCINT20)
PK5 (ADC13/PCINT21)
PL6
PL7
(OC5B) PL4
(OC5C) PL5
INT23)
GND
PK6 (ADC14/PCINT22)
PK7 (ADC15/PC
(SCL/INT0) PD0
(SDA/INT1) PD1
(RXD1/INT2) PD2
PJ7
VCC
PA0 (AD0)
(ICP1) PD4
(XCK1) PD5
(TXD1/INT3) PD3
PA1 (AD1)
PA2 (AD2)
(T1) PD6
(T0) PD7
PA3 (AD3)
75
PA4 (AD4)
74
PA5 (AD5)
73
PA6 (AD6)
72
PA7 (AD7)
71
PG2 (ALE)
70
69
PJ6 (PCINT15)
PJ5 (PCINT14)
68
PJ4 (PCINT13)
67
PJ3 (PCINT12)
66
PJ2 (XCK3/PCINT11)
65
PJ1 (TXD3/PCINT10)
64
PJ0 (RXD3/PCINT9)
63
62
GND
61
VCC
60
PC7 (A15)
PC6 (A14)
59
PC5 (A13)
58
PC4 (A12)
57
PC3 (A11)
56
PC2 (A10)
55
PC1 (A9)
54
PC0 (A8)
53
PG1 (RD)
52
PG0 (WR)
51
(OC0A/OC1C/PCINT7) PB7
2
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
ATmega640/1280/1281/2560/2561
Figure 2. CBGA-pinout ATmega640/1280/2560
1 2345678910
Top view
A
B
C
D
E
F
G
H
J
K
10987654321
Bottom view
A
B
C
D
E
F
G
H
J
K
Table 1. CBGA-pinout ATmega640/1280/2560.
12 345678910
A GND AREF PF0 PF2 PF5 PK0 PK3 PK6 GNDVCC
B AVCC PG5 PF1 PF3 PF6 PK1 PK4 PK7 PA0 PA2
C PE2 PE0 PE1 PF4 PF7 PK2 PK5 PJ7 PA1 PA3
D PE3 PE4 PE5 PE6 PH2 PA4 PA5 PA6 PA7 PG2
E PE7 PH0 PH1 PH3 PH5 PJ6 PJ5 PJ4 PJ3 PJ2
F VCC PH4 PH6 PB0 PL4 PD1 PJ1 PJ0 PC7 GND
G GND PB1 PB2 PB5 PL2 PD0 PD5 PC5 PC6 VCC
H PB3 PB4 RESET PL1 PL3 PL7 PD4 PC4 PC3 PC2
J PH7 PG3 PB6 PL0 XTAL2 PL6 PD3 PC1 PC0 PG1
K PB7 PG4 VCC GND XTAL1 PL5 PD2 PD6 PD7 PG0
2549K–AVR–01/07
3
Figure 3. Pinout ATmega1281/2561
AVCC
AREF
GND
PF0 (ADC0)
64
62
63
61
(OC0B) PG5
(RXD0/PCINT8/PDI) PE0
(TXD0/PDO) PE1
(XCK0/AIN0) PE2
(OC3A/AIN1) PE3
(OC3B/INT4) PE4
(OC3C/INT5) PE5
(T3/INT6) PE6
(ICP3/CLKO/INT7) PE7
(SS/PCINT0) PB0
(SCK/ PCINT1) PB1
(MOSI/ PCINT2) PB2
(MISO/ PCINT3) PB3
(OC2A/ PCINT4) PB4
(OC1A/PCINT5) PB5
(OC1B/PCINT6) PB6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
19
18
20
PF1 (ADC1)
PF2 (ADC2)
60
59
INDEX CORNER
ATmega1281/2561
21
22
PF3 (ADC3)
PF5 (ADC5/TMS)
PF4 (ADC4/TCK)
58
57
23
24
PF6 (ADC6/TDO)
PF7 (ADC7/TDI)
56
55
54
25
26
27
GND
53
28
VCC
52
29
(AD1)
PA 1
PA0 (AD0)
50
51
31
30
(AD2)
PA 2
49
32
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PA3 (AD3)
PA4 (AD4)
PA5 (AD5)
PA6 (AD6)
PA7 (AD7)
PG2 (ALE)
PC7 (A15)
PC6 (A14)
PC5 (A13)
PC4 (A12)
PC3 (A11)
PC2 (A10)
PC1 (A9)
PC0 (A8)
PG1 (RD)
PG0 (WR)
VCC
) PB7
PCINT7
(TOSC1) PG4
(TOSC2) PG3
(OC0A/OC1C/
RESET
GND
XTAL2
XTAL1
(SCL/INT0) PD0
(SDA/INT1) PD1
(TXD1/INT3) PD3
(RXD1/INT2) PD2
(ICP1) PD4
(XCK1) PD5
(T1) PD6
(T0) PD7
Note: The large center pad underneath the QFN/MLF package is made of metal and internally
connected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen from the
board.
Disclaimer Typical values contained in this datasheet are based on simulations and characteriza-
tion of other AVR microcontrollers manufactured on the same process technology. Min.
and Max values will be available after the device is characterized.
4
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
ATmega640/1280/1281/2560/2561
Overview
The ATmega640/1280/1281/2560/2561 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC
architecture. By executing powerful instructions in a single clock cycle, the ATmega640/1280/1281/2560/2561 achieves
throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing
speed.
Block Diagram
Figure 4. Block Diagram
VCC
Powe r
RESET
GND
XTAL1
XTAL2
PA7..0
PG5..0 PORT G (6)
Supervision
POR / BOD &
RESET
Watchdog
Timer
Watchdog
Oscillator
Oscillator
Circuits /
Clock
Generation
PORT A (8)
PF7..0
PORT F (8)
JTAG
EEPROM
XRAM
PK7..0
PORT K (8)
A/D
Converter
Internal
Bandgap reference
CPU
SRAMFLASH
PJ7..0
PORT J (8)
Analog
Comparator
16bit T/C 3
16bit T/C 5
16bit T/C 4
16bit T/C 1
PE7..0
PORT E (8)
USART 0
USART 3
USART 1
PC7..0 PORT C (8)
2549K–AVR–01/07
NOTE:
Shaded parts only available
in the 100-pin version.
Complete functionality for
the ADC, T/C4, and T/C5 only
available in the 100-pin version.
TWI SPI
PORT D (8)
PD7..0
PORT B (8)
PB7..0
8bit T/C 0 8bit T/C 2
PORT H (8)
PH7..0
USART 2
PORT L (8)
PL7..0
5
The AVR core combines a rich instruction set with 32 general purpose working registers.
All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing
two independent registers to be accessed in one single instruction executed in one clock
cycle. The resulting architecture is more code efficient while achieving throughputs up to
ten times faster than conventional CISC microcontrollers.
The ATmega640/1280/1281/2560/2561 provides the following features: 64K/128K/256K
bytes of In-System Programmable Flash with Read-While-Write capabilities, 4K bytes
EEPROM, 8K bytes SRAM, 54/86 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), six flexible Timer/Counters with compare
modes and PWM, 4 USARTs, a byte oriented 2-wire Serial Interface, a 16-channel, 10bit ADC with optional differential input stage with programmable gain, programmable
Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant
JTAG test interface, also used for accessing the On-chip Debug system and programming and six software selectable power saving modes. The Idle mode stops the CPU
while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue
functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In
Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction
mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator
Oscillator is running while the rest of the device is sleeping. This allows very fast start-up
combined with low power consumption. In Extended Standby mode, both the main
Oscillator and the Asynchronous Timer continue to run.
The device is manufactured using Atmel’s high-density nonvolatile memory technology.
The On-chip ISP Flash allows the program memory to be reprogrammed in-system
through an SPI serial interface, by a conventional nonvolatile memory programmer, or
by an On-chip Boot program running on the AVR core. The boot program can use any
interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is
updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU
with In-System Self-Programmable Flash on a monolithic chip, the Atmel
ATmega640/1280/1281/2560/2561 is a powerful microcontroller that provides a highly
flexible and cost effective solution to many embedded control applications.
The ATmega640/1280/1281/2560/2561 AVR is supported with a full suite of program
and system development tools including: C compilers, macro assemblers, program
debugger/simulators, in-circuit emulators, and evaluation kits.
6
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
ATmega640/1280/1281/2560/2561
Comparison Between ATmega1281/2561 and ATmega640/1280/2560
Each device in the ATmega640/1280/1281/2560/2561 family differs only in memory size
and number of pins. Table 2 summarizes the different configurations for the six devices.
Table 2. Configuration Summary
General
Device Flash EEPROM RAM
ATmega640 64KB 4KB 8KB 86 12 4 16
ATmega1280 128KB 4KB 8KB 86 12 4 16
ATmega1281 128KB 4KB 8KB 54 6 2 8
ATmega2560 256KB 4KB 8KB 86 12 4 16
ATmega2561 256KB 4KB 8KB 54 6 2 8
Purpose I/O pins
16 bits resolution
PWM channels
Serial
USARTs
ADC
Channels
Pin Descriptions
VCC Digital supply voltage.
GND Ground.
Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port A output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port A pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port A also serves the functions of various special features of the
ATmega640/1280/1281/2560/2561 as listed on page 91.
Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port B output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port B pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port B has better driving capabilities than the other ports.
Port B also serves the functions of various special features of the
ATmega640/1280/1281/2560/2561 as listed on page 92.
Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port C output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port C pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port C also serves the functions of special features of the
ATmega640/1280/1281/2560/2561 as listed on page 95.
Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port D output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port D pins that are externally pulled low will source
2549K–AVR–01/07
7
current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port D also serves the functions of various special features of the
ATmega640/1280/1281/2560/2561 as listed on page 97.
Port E (PE7..PE0) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port E output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port E pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port E also serves the functions of various special features of the
ATmega640/1280/1281/2560/2561 as listed on page 99.
Port F (PF7..PF0) Port F serves as analog inputs to the A/D Converter.
Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used.
Port pins can provide internal pull-up resistors (selected for each bit). The Port F output
buffers have symmetrical drive characteristics with both high sink and source capability.
As inputs, Port F pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port F pins are tri-stated when a reset condition becomes
active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset
occurs.
Port F also serves the functions of the JTAG interface.
Port G (PG5..PG0) Port G is a 6-bit I/O port with internal pull-up resistors (selected for each bit). The Port G
output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port G pins that are externally pulled low will source current if the
pull-up resistors are activated. The Port G pins are tri-stated when a reset condition
becomes active, even if the clock is not running.
Port G also serves the functions of various special features of the
ATmega640/1280/1281/2560/2561 as listed on page 105.
Port H (PH7..PH0) Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port H output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port H pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port H pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port H also serves the functions of various special features of the
ATmega640/1280/2560 as listed on page 107.
Port J (PJ7..PJ0) Port J is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port J output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port J pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port J pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port J also serves the functions of various special features of the
ATmega640/1280/2560 as listed on page 109.
Port K (PK7..PK0) Port K serves as analog inputs to the A/D Converter.
8
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
ATmega640/1280/1281/2560/2561
Port K is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port K output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port K pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port K pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port K also serves the functions of various special features of the
ATmega640/1280/2560 as listed on page 111.
Port L (PL7..PL0) Port L is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port L output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port L pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port L pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port L also serves the functions of various special features of the
ATmega640/1280/2560 as listed on page 113.
RESET
XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
XTAL2 Output from the inverting Oscillator amplifier.
AVCC AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally
AREF This is the analog reference pin for the A/D Converter.
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table
26 on page 58. Shorter pulses are not guaranteed to generate a reset.
connected to V
nected to V
, even if the ADC is not used. If the ADC is used, it should be con-
CC
through a low-pass filter.
CC
Resources
A comprehensive set of development tools and application notes, and datasheets are
available for download on http://www.atmel.com/avr.
About Code Examples
This documentation contains simple code examples that briefly show how to use various
parts of the device. Be aware that not all C compiler vendors include bit definitions in the
header files and interrupt handling in C is compiler dependent. Please confirm with the
C compiler documentation for more details.
2549K–AVR–01/07
These code examples assume that the part specific header file is included before compilation. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC",
"CBI", and "SBI" instructions must be replaced with instructions that allow access to
extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and
"CBR".
9
AVR CPU Core
Introduction This section discusses the AVR core architecture in general. The main function of the
CPU core is to ensure correct program execution. The CPU must therefore be able to
access memories, perform calculations, control peripherals, and handle interrupts.
Architectural Overview Figure 5. Block Diagram of the AVR Architecture
Data Bus 8-bit
Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Control Lines
Program
Counter
Direct Addressing
Status
and Control
32 x 8
General
Purpose
Registrers
ALU
Indirect Addressing
Data
SRAM
EEPROM
Interrupt
Unit
SPI
Unit
Watchdog
Timer
Analog
Comparator
I/O Module1
I/O Module 2
I/O Module n
10
I/O Lines
In order to maximize performance and parallelism, the AVR uses a Harvard architecture
– with separate memories and buses for program and data. Instructions in the program
memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept
enables instructions to be executed in every clock cycle. The program memory is InSystem Reprogrammable Flash memory.
The fast-access Register File contains 32 x 8-bit general purpose working registers with
a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU)
operation. In a typical ALU operation, two operands are output from the Register File,
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
ATmega640/1280/1281/2560/2561
the operation is executed, and the result is stored back in the Register File – in one
clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for
Data Space addressing – enabling efficient address calculations. One of the these
address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register,
described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After
an arithmetic operation, the Status Register is updated to reflect information about the
result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions,
able to directly address the whole address space. Most AVR instructions have a single
16-bit word format. Every program memory address contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot Program section and
the Application Program section. Both sections have dedicated Lock bits for write and
read/write protection. The SPM instruction that writes into the Application Flash memory
section must reside in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is
stored on the Stack. The Stack is effectively allocated in the general data SRAM, and
consequently the Stack size is only limited by the total SRAM size and the usage of the
SRAM. All user programs must initialize the SP in the Reset routine (before subroutines
or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O
space. The data SRAM can easily be accessed through the five different addressing
modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional
Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt
Vector in the Interrupt Vector table. The interrupts have priority in accordance with their
Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control
Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as
the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition,
the ATmega640/1280/1281/2560/2561 has Extended I/O space from 0x60 - 0x1FF in
SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.
ALU – Arithmetic Logic
Unit
The high-performance AVR ALU operates in direct connection with all the 32 general
purpose working registers. Within a single clock cycle, arithmetic operations between
general purpose registers or between a register and an immediate are executed. The
ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier
supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.
Status Register The Status Register contains information about the result of the most recently executed
arithmetic instruction. This information can be used for altering program flow in order to
perform conditional operations. Note that the Status Register is updated after all ALU
operations, as specified in the Instruction Set Reference. This will in many cases
2549K–AVR–01/07
11
remove the need for using the dedicated compare instructions, resulting in faster and
more compact code.
The Status Register is not automatically stored when entering an interrupt routine and
restored when returning from an interrupt. This must be handled by software.
SREG – AVR Status Register The AVR Status Register – SREG – is defined as:
Bit 76543210
0x3F (0x5F) I T H S V N Z C SREG
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global
Interrupt Enable Register is cleared, none of the interrupts are enabled independent of
the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt
has occurred, and is set by the RETI instruction to enable subsequent interrupts. The Ibit can also be set and cleared by the application with the SEI and CLI instructions, as
described in the instruction set reference.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or
destination for the operated bit. A bit from a register in the Register File can be copied
into T by the BST instruction, and a bit in T can be copied into a bit in a register in the
Register File by the BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is
useful in BCD arithmetic. See the “Instruction Set Description” for detailed information.
• Bit 4 – S: Sign Bit, S = N
⊕ V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See
the “Instruction Set Description” for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See
the “Instruction Set Description” for detailed information.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the
“Instruction Set Description” for detailed information.
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.
12
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
ATmega640/1280/1281/2560/2561
General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to
achieve the required performance and flexibility, the following input/output schemes are
supported by the Register File:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
Figure 6 shows the structure of the 32 general purpose working registers in the CPU.
Figure 6. AVR CPU General Purpose Working Registers
7 0 Addr.
R0 0x00
R1 0x01
R2 0x02
…
R13 0x0D
General R14 0x0E
Purpose R15 0x0F
Working R16 0x10
Registers R17 0x11
…
R26 0x1A X-register Low Byte
R27 0x1B X-register High Byte
R28 0x1C Y-register Low Byte
R29 0x1D Y-register High Byte
R30 0x1E Z-register Low Byte
R31 0x1F Z-register High Byte
Most of the instructions operating on the Register File have direct access to all registers,
and most of them are single cycle instructions.
As shown in Figure 6 on page 13, each register is also assigned a data memory
address, mapping them directly into the first 32 locations of the user Data Space.
Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer
registers can be set to index any register in the file.
2549K–AVR–01/07
13
The X-register, Y-register, and Z-register
The registers R26..R31 have some added functions to their general purpose usage.
These registers are 16-bit address pointers for indirect addressing of the data space.
The three indirect address registers X, Y, and Z are defined as described in Figure 7.
Figure 7. The X-, Y-, and Z-registers
15 XH XL 0
X-register 707 0
R27 (0x1B) R26 (0x1A)
15 YH YL 0
Y-register 707 0
R29 (0x1D) R28 (0x1C)
15 ZH ZL 0
Z-register 70 7 0
R31 (0x1F) R30 (0x1E)
In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set
reference for details).
Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for
storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing
from higher memory locations to lower memory locations. This implies that a Stack
PUSH command decreases the Stack Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the
program before any subroutine calls are executed or interrupts are enabled. The Stack
Pointer must be set to point above 0x0200. The initial value of the stack pointer is the
last address of the internal SRAM. The Stack Pointer is decremented by one when data
is pushed onto the Stack with the PUSH instruction, and it is decremented by two for
ATmega640/1280/1281 and three for ATmega2560/2561 when the return address is
pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is
incremented by two for ATmega640/1280/1281 and three for ATmega2560/2561 when
data is popped from the Stack with return from subroutine RET or return from interrupt
RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some
implementations of the AVR architecture is so small that only SPL is needed. In this
case, the SPH Register will not be present.
Bit 151413121110 9 8
0x3E (0x5E) SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH
0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL
76543210
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 1 0 0 0 0 1
11111111
14
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
RAMPZ – Extended Z-pointer
Register for ELPM/SPM
ATmega640/1280/1281/2560/2561
Bit 765432 1 0
0x3B (0x5B)
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value000000 0 0
For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as
shown in Figure 8. Note that LPM is not affected by the RAMPZ setting.
Figure 8. The Z-pointer used by ELPM and SPM
RAMPZ7 RAMPZ6 RAMPZ5 RAMPZ4 RAMPZ3 RAMPZ2 RAMPZ1 RAMPZ0
RAMPZ
EIND – Extended Indirect
Register
Bit (
Individually)
Bit (Z-pointer) 23 16 15 8 7 0
707070
RAMPZ ZH ZL
The actual number of bits is implementation dependent. Unused bits in an implementation will always read as zero. For compatibility with future devices, be sure to write these
bits to zero.
Bit 765432 1 0
0x3C (0x5C) EIND7 EIND6 EIND5 EIND4 EIND3 EIND2 EIND1 EIND0 EIND
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value000000 0 0
For EICALL/EIJMP instructions, the Indirect-pointer to the subroutine/routine is a concatenation of EIND, ZH, and ZL, as shown in Figure 9. Note that ICALL and IJMP are
not affected by the EIND setting.
Figure 9. The Indirect-pointer used by EICALL and EIJMP
Bit (Individually)
Bit (Indirectpointer)
707070
EIND ZH ZL
23 16 15 8 7 0
2549K–AVR–01/07
The actual number of bits is implementation dependent. Unused bits in an implementation will always read as zero. For compatibility with future devices, be sure to write these
bits to zero.
15
Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The
AVR CPU is driven by the CPU clock clk
, directly generated from the selected clock
CPU
source for the chip. No internal clock division is used.
Figure 10 shows the parallel instruction fetches and instruction executions enabled by
the Harvard architecture and the fast-access Register File concept. This is the basic
pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results
for functions per cost, functions per clocks, and functions per power-unit.
Figure 10. The Parallel Instruction Fetches and Instruction Executions
T1 T2 T3 T4
clk
CPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 11 shows the internal timing concept for the Register File. In a single clock cycle
an ALU operation using two register operands is executed, and the result is stored back
to the destination register.
Figure 11. Single Cycle ALU Operation
T1 T2 T3 T4
clk
CPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
16
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
ATmega640/1280/1281/2560/2561
Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate
Reset Vector each have a separate program vector in the program memory space. All
interrupts are assigned individual enable bits which must be written logic one together
with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt.
Depending on the Program Counter value, interrupts may be automatically disabled
when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software
security. See the section “Memory Programming” on page 342 for details.
The lowest addresses in the program memory space are by default defined as the Reset
and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 69.
The list also determines the priority levels of the different interrupts. The lower the
address the higher is the priority level. RESET has the highest priority, and next is INT0
– the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of
the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR).
Refer to “Interrupts” on page 69 for more information. The Reset Vector can also be
moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see
“Memory Programming” on page 342.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts
are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is
automatically set when a Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that
sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the
actual Interrupt Vector in order to execute the interrupt handling routine, and hardware
clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a
logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the
corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or
more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt
Enable bit is set, and will then be executed by order of priority.
2549K–AVR–01/07
The second type of interrupts will trigger as long as the interrupt condition is present.
These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by
software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately
disabled. No interrupt will be executed after the CLI instruction, even if it occurs simulta-
17
neously with the CLI instruction. The following example shows how this can be used to
avoid interrupts during the timed EEPROM write sequence.
Assembly Code Example
in r16, SREG ; store SREG value
cli ; disable interrupts during timed sequence
sbi EECR, EEMPE ; start EEPROM write
sbi EECR, EEPE
out SREG, r16 ; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
__disable_interrupt();
EECR |= (1<<EEMPE); /* start EEPROM write */
EECR |= (1<<EEPE);
SREG = cSREG; /* restore SREG value (I-bit) */
When using the SEI instruction to enable interrupts, the instruction following SEI will be
executed before any pending interrupts, as shown in this example.
Assembly Code Example
sei ; set Global Interrupt Enable
sleep ; enter sleep, waiting for interrupt
; note: will enter sleep before any pending
; interrupt(s)
C Code Example
__enable_interrupt(); /* set Global Interrupt Enable */
__sleep(); /* enter sleep, waiting for interrupt */
/* note: will enter sleep before any pending interrupt(s) */
Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is five clock cycles
minimum. After five clock cycles the program vector address for the actual interrupt handling routine is executed. During these five clock cycle period, the Program Counter is
pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this
jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle
instruction, this instruction is completed before the interrupt is served. If an interrupt
occurs when the MCU is in sleep mode, the interrupt execution response time is
increased by five clock cycles. This increase comes in addition to the start-up time from
the selected sleep mode.
A return from an interrupt handling routine takes five clock cycles. During these five
clock cycles, the Program Counter (three bytes) is popped back from the Stack, the
Stack Pointer is incremented by three, and the I-bit in SREG is set.
18
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
AVR Memor ies
ATmega640/1280/1281/2560/2561
This section describes the different memories in the ATmega640/1280/1281/2560/2561.
The AVR architecture has two main memory spaces, the Data Memory and the Program
Memory space. In addition, the ATmega640/1280/1281/2560/2561 features an
EEPROM Memory for data storage. All three memory spaces are linear and regular.
In-System Reprogrammable Flash Program Memory
The ATmega640/1280/1281/2560/2561 contains 64K/128K/256K bytes On-chip In-System Reprogrammable Flash memory for program storage, see Table 3 on page 19.
Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as
32K/64K/128K x 16. For software security, the Flash Program memory space is divided
into two sections, Boot Program section and Application Program section.
The Flash memory has an endurance of at least 10,000 write/erase cycles. The
ATmega640/1280/1281/2560/2561 Program Counter (PC) is 15/16/17 bits wide, thus
addressing the 32K/64K/128K program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in
detail in “Boot Loader Support – Read-While-Write Self-Programming” on page 323.
“Memory Programming” on page 342 contains a detailed description on Flash data
serial downloading using the SPI pins or the JTAG interface.
Constant tables can be allocated within the entire program memory address space (see
the LPM – Load Program Memory instruction description and ELPM - Extended Load
Program Memory instruction description).
Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Timing” on page 16.
Table 3. Program Flash Memory Map
Address (HEX)
0
Application Flash Section
2549K–AVR–01/07
0x7FFF/0xFFFF/0x1FFFF
Boot Flash Section
19
SRAM Data Memory Table 4 on page 21 shows how the ATmega640/1280/1281/2560/2561 SRAM Memory
is organized.
The ATmega640/1280/1281/2560/2561 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in the Opcode for the IN
and OUT instructions. For the Extended I/O space from $060 - $1FF in SRAM, only the
ST/STS/STD and LD/LDS/LDD instructions can be used.
The first 4,608/8,704 Data Memory locations address both the Register File, the I/O
Memory, Extended I/O Memory, and the internal data SRAM. The first 32 locations
address the Register file, the next 64 location the standard I/O Memory, then 416 locations of Extended I/O memory and the next 8,192 locations address the internal data
SRAM.
An optional external data SRAM can be used with the
ATmega640/1280/1281/2560/2561. This SRAM will occupy an area in the remaining
address locations in the 64K address space. This area starts at the address following
the internal SRAM. The Register file, I/O, Extended I/O and Internal SRAM occupies the
lowest 4,608/8,704 bytes, so when using 64KB (65,536 bytes) of External Memory,
60,478/56,832 Bytes of External Memory are available. See “External Memory Interface” on page 26 for details on how to take advantage of the external memory map.
When the addresses accessing the SRAM memory space exceeds the internal data
memory locations, the external data SRAM is accessed using the same instructions as
for the internal data memory access. When the internal data memories are accessed,
the read and write strobe pins (PG0 and PG1) are inactive during the whole access
cycle. External SRAM operation is enabled by setting the SRE bit in the XMCRA
Register.
Accessing external SRAM takes one additional clock cycle per byte compared to access
of the internal SRAM. This means that the commands LD, ST, LDS, STS, LDD, STD,
PUSH, and POP take one additional clock cycle. If the Stack is placed in external
SRAM, interrupts, subroutine calls and returns take three clock cycles extra because the
three-byte program counter is pushed and popped, and external memory access does
not take advantage of the internal pipe-line memory access. When external SRAM interface is used with wait-state, one-byte external access takes two, three, or four additional
clock cycles for one, two, and three wait-states respectively. Interrupts, subroutine calls
and returns will need five, seven, or nine clock cycles more than specified in the instruction set manual for one, two, and three wait-states.
The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In
the Register file, registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base
address given by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and postincrement, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O registers, and the 4,196/8,192 bytes of
internal data SRAM in the ATmega640/1280/1281/2560/2561 are all accessible through
20
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
ATmega640/1280/1281/2560/2561
all these addressing modes. The Register File is described in “General Purpose Register File” on page 13.
Table 4. Data Memory Map
Address (HEX)
0 - 1F 32 Registers
20 - 5F 64 I/O Registers
60 - 1FF
200
21FF
2200
FFFF
416 External I/O Registers
Internal SRAM
(8192 x 8)
External SRAM
(0 - 64K x 8)
Data Memory Access Times This section describes the general access timing concepts for internal memory access.
The internal data SRAM access is performed in two clk
cycles as described in Figure
CPU
12.
Figure 12. On-chip Data SRAM Access Cycles
T1 T2 T3
clk
CPU
Address
Compute Address
Address valid
Data
WR
Write
2549K–AVR–01/07
Data
RD
Memory Access Instruction
Read
Next Instruction
21
EEPROM Data Memory The ATmega640/1280/1281/2560/2561 contains 4K bytes of data EEPROM memory. It
is organized as a separate data space, in which single bytes can be read and written.
The EEPROM has an endurance of at least 100,000 write/erase cycles. The access
between the EEPROM and the CPU is described in the following, specifying the
EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control
Register.
For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM,
see “Serial Downloading” on page 356, “Programming via the JTAG Interface” on page
361, and “Programming the EEPROM” on page 350 respectively.
EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space, see “Register Descrip-
tion” on page 32.
The write access time for the EEPROM is given in Table 5 on page 22. A self-timing
function, however, lets the user software detect when the next byte can be written. If the
user code contains instructions that write the EEPROM, some precautions must be
taken. In heavily filtered power supplies, V
up/down. This causes the device for some period of time to run at a voltage lower than
specified as minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page 24. for details on how to avoid problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. See the description of the EEPROM Control Register for details on this, “Register
Description” on page 32.
When the EEPROM is read, the CPU is halted for four clock cycles before the next
instruction is executed. When the EEPROM is written, the CPU is halted for two clock
cycles before the next instruction is executed.
is likely to rise or fall slowly on power-
CC
The calibrated Oscillator is used to time the EEPROM accesses. Table 5 lists the typical
programming time for EEPROM access from the CPU.
Table 5. EEPROM Programming Time
Symbol Number of Calibrated RC Oscillator Cycles Typ Programming Time
EEPROM write
(from CPU)
The following code examples show one assembly and one C function for writing to the
EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The
examples also assume that no Flash Boot Loader is present in the software. If such
code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.
26,368 3.3 ms
22
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
ATmega640/1280/1281/2560/2561
Assembly Code Example
EEPROM_write:
; Wait for completion of previous write
sbic EECR,EEPE
rjmp EEPROM_write
; Set up address (r18:r17) in address register
out EEARH, r18
out EEARL, r17
; Write data (r16) to Data Register
out EEDR,r16
; Write logical one to EEMPE
sbi EECR,EEMPE
; Start eeprom write by setting EEPE
sbi EECR,EEPE
ret
C Code Example
void EEPROM_write(unsigned int uiAddress, unsigned char ucData)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEPE))
;
/* Set up address and Data Registers */
EEAR = uiAddress;
EEDR = ucData;
/* Write logical one to EEMPE */
EECR |= (1<<EEMPE);
/* Start eeprom write by setting EEPE */
EECR |= (1<<EEPE);
}
(1)
()
2549K–AVR–01/07
Note: 1. See “About Code Examples” on page 9.
23
The next code examples show assembly and C functions for reading the EEPROM. The
examples assume that interrupts are controlled so that no interrupts will occur during
execution of these functions.
Assembly Code Example
EEPROM_read:
; Wait for completion of previous write
sbic EECR,EEPE
rjmp EEPROM_read
; Set up address (r18:r17) in address register
out EEARH, r18
out EEARL, r17
; Start eeprom read by writing EERE
sbi EECR,EERE
; Read data from Data Register
in r16,EEDR
ret
C Code Example
unsigned char EEPROM_read(unsigned int uiAddress)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEPE))
;
/* Set up address register */
EEAR = uiAddress;
/* Start eeprom read by writing EERE */
EECR |= (1<<EERE);
/* Return data from Data Register */
return EEDR;
}
(1)
(1)
Preventing EEPROM Corruption
24
ATmega640/1280/1281/2560/2561
Note: 1. See “About Code Examples” on page 9.
During periods of low V
the EEPROM data can be corrupted because the supply volt-
CC,
age is too low for the CPU and the EEPROM to operate properly. These issues are the
same as for board level systems using EEPROM, and the same design solutions should
be applied.
An EEPROM data corruption can be caused by two situations when the voltage is too
low. First, a regular write sequence to the EEPROM requires a minimum voltage to
operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the
supply voltage is too low.
EEPROM data corruption can easily be avoided by following this design
recommendation:
Keep the AVR RESET active (low) during periods of insufficient power supply voltage.
This can be done by enabling the internal Brown-out Detector (BOD). If the detection
level of the internal BOD does not match the needed detection level, an external low
V
reset Protection circuit can be used. If a reset occurs while a write operation is in
CC
progress, the write operation will be completed provided that the power supply voltage is
sufficient.
2549K–AVR–01/07
ATmega640/1280/1281/2560/2561
I/O Memory The I/O space definition of the ATmega640/1280/1281/2560/2561 is shown in “Register
Summary” on page 416.
All ATmega640/1280/1281/2560/2561 I/Os and peripherals are placed in the I/O space.
All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions,
transferring data between the 32 general purpose working registers and the I/O space.
I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the
SBI and CBI instructions. In these registers, the value of single bits can be checked by
using the SBIS and SBIC instructions. Refer to the instruction set section for more
details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 0x3F must be used. When addressing I/O Registers as data space using LD and ST
instructions, 0x20 must be added to these addresses. The
ATmega640/1280/1281/2560/2561 is a complex microcontroller with more peripheral
units than can be supported within the 64 location reserved in Opcode for the IN and
OUT instructions. For the Extended I/O space from 0x60 - 0x1FF in SRAM, only the
ST/STS/STD and LD/LDS/LDD instructions can be used.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike
most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and
can therefore be used on registers containing such Status Flags. The CBI and SBI
instructions work with registers 0x00 to 0x1F only.
The I/O and peripherals control registers are explained in later sections.
General Purpose I/O Registers The ATmega640/1280/1281/2560/2561 contains three General Purpose I/O Registers.
These registers can be used for storing any information, and they are particularly useful
for storing global variables and Status Flags. General Purpose I/O Registers within the
address range 0x00 - 0x1F are directly bit-accessible using the SBI, CBI, SBIS, and
SBIC instructions. See “Register Description” on page 32.
2549K–AVR–01/07
25
External Memory Interface
With all the features the External Memory Interface provides, it is well suited to operate
as an interface to memory devices such as External SRAM and Flash, and peripherals
such as LCD-display, A/D, and D/A. The main features are:
•
Four different wait-state settings (including no wait-state).
• Independent wait-state setting for different External Memory sectors (configurable sector
size)
• The number of bits dedicated to address high byte is selectable
• Bus keepers on data lines to minimize current consumption (optional)
Overview When the eXternal MEMory (XMEM) is enabled, address space outside the internal
SRAM becomes available using the dedicated External Memory pins (see Figure 3 on
page 4, Table 39 on page 91, Table 45 on page 95, and Table 57 on page 105). The
memory configuration is shown in Figure 13.
Figure 13. External Memory with Sector Select
Memory Configuration A
0x0000
Internal memory
0x21FF
Lower sector
SRW01
SRW00
0x2200
Using the External Memory Interface
SRL[2..0]
External Memory
(0-60K x 8)
Upper sector
SRW11
SRW10
0xFFFF
The interface consists of:
• AD7:0: Multiplexed low-order address bus and data bus.
• A15:8: High-order address bus (configurable number of bits).
• ALE: Address latch enable.
•RD
• WR
: Read strobe.
: Write strobe.
The control bits for the External Memory Interface are located in two registers, the External Memory Control Register A – XMCRA, and the External Memory Control Register B
– XMCRB.
When the XMEM interface is enabled, the XMEM interface will override the setting in the
data direction registers that corresponds to the ports dedicated to the XMEM interface.
26
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
ATmega640/1280/1281/2560/2561
For details about the port override, see the alternate functions in section “I/O-Ports” on
page 83. The XMEM interface will auto-detect whether an access is internal or external.
If the access is external, the XMEM interface will output address, data, and the control
signals on the ports according to Figure 15 (this figure shows the wave forms without
wait-states). When ALE goes from high-to-low, there is a valid address on AD7:0. ALE is
low during a data transfer. When the XMEM interface is enabled, also an internal access
will cause activity on address, data and ALE ports, but the RD
toggle during internal access. When the External Memory Interface is disabled, the normal pin and data direction settings are used. Note that when the XMEM interface is
disabled, the address space above the internal SRAM boundary is not mapped into the
internal SRAM. Figure 14 illustrates how to connect an external SRAM to the AVR using
an octal latch (typically “74 x 573” or equivalent) which is transparent when G is high.
Address Latch Requirements Due to the high-speed operation of the XRAM interface, the address latch must be
selected with care for system frequencies above 8 MHz @ 4V and 4 MHz @ 2.7V.
When operating at conditions above these frequencies, the typical old style 74HC series
latch becomes inadequate. The External Memory Interface is designed in compliance to
the 74AHC series latch. However, most latches can be used as long they comply with
the main timing parameters. The main parameters for the address latch are:
• D to Q propagation delay (t
• Data setup time before G low (t
• Data (address) hold time after G low (
PD
).
).
SU
).
TH
The External Memory Interface is designed to guaranty minimum address hold time
after G is asserted low of t
= 5 ns. Refer to t
h
LAXX_LD/tLLAXX_ST
Timing” Tables 173 through Tables 180 on pages 385 - 387. The D-to-Q propagation
delay (t
) must be taken into consideration when calculating the access time require-
PD
ment of the external component. The data setup time before G low (t
exceed address valid to ALE low (t
) minus PCB wiring delay (dependent on the
AVLLC
capacitive load).
and WR strobes will not
in “External Data Memory
) must not
SU
Figure 14. External SRAM Connected to the AVR
AVR
AD7:0
ALE
A15:8
RD
WR
DQ
G
SRAM
D[7:0]
A[7:0]
A[15:8]
RD
WR
2549K–AVR–01/07
27
Pull-up and Bus-keeper The pull-ups on the AD7:0 ports may be activated if the corresponding Port register is
written to one. To reduce power consumption in sleep mode, it is recommended to disable the pull-ups by writing the Port register to zero before entering sleep.
The XMEM interface also provides a bus-keeper on the AD7:0 lines. The bus-keeper
can be disabled and enabled in software as described in “XMCRB – External Memory
Control Register B” on page 36. When enabled, the bus-keeper will keep the previous
value on the AD7:0 bus while these lines are tri-stated by the XMEM interface.
Timing External Memory devices have different timing requirements. To meet these require-
ments, the XMEM interface provides four different wait-states as shown in Table 8. It is
important to consider the timing specification of the External Memory device before
selecting the wait-state. The most important parameters are the access time for the
external memory compared to the set-up requirement. The access time for the External
Memory is defined to be the time from receiving the chip select/address until the data of
this address actually is driven on the bus. The access time cannot exceed the time from
the ALE pulse must be asserted low until data is stable during a read sequence (See
t
LLRL
+ t
RLRH
- t
in Tables 173 through Tables 180 on pages 385 - 387). The different
DVRH
wait-states are set up in software. As an additional feature, it is possible to divide the
external memory space in two sectors with individual wait-state settings. This makes it
possible to connect two different memory devices with different timing requirements to
the same XMEM interface. For XMEM interface timing details, please refer to Table 173
to Table 180 and Figure 163 to Figure 166 in the “External Data Memory Timing” on
page 385.
Note that the XMEM interface is asynchronous and that the waveforms in the following
figures are related to the internal system clock. The skew between the internal and
external clock (XTAL1) is not guarantied (varies between devices temperature, and supply voltage). Consequently, the XMEM interface is not suited for synchronous operation.
Figure 15. External Data Memory Cycles without Wait-state (SRWn1=0 and SRWn0=0)
T1 T2 T3
System Clock (CLK
DA7:0 (XMBK = 0)
DA7:0 (XMBK = 1)
CPU
ALE
A15:8
DA7:0
WR
RD
)
AddressPrev. addr.
Address DataPrev. data XX
DataPrev. data Address
XXXXX
DataPrev. data Address
Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper
sector) or SRW00 (lower sector). The ALE pulse in period T4 is only present if the
next instruction accesses the RAM (internal or external).
T4
XXXXXXXX
Write
Read
28
ATmega640/1280/1281/2560/2561
2549K–AVR–01/07
ATmega640/1280/1281/2560/2561
Figure 16. External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1
System Clock (CLK
DA7:0 (XMBK = 0)
DA7:0 (XMBK = 1)
CPU
ALE
A15:8
DA7:0
WR
RD
T1 T2 T3
)
AddressPrev. addr.
Address DataPrev. data XX
DataPrev. data Address
DataPrev. data Address
T4
(1)
T5
Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper
sector) or SRW00 (lower sector).
The ALE pulse in period T5 is only present if the next instruction accesses the RAM
(internal or external).
Figure 17. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 0
System Clock (CLK
CPU
T1 T2 T3
)
T4 T5
(1)
T6
Write
Read
ALE
A15:8
DA7:0
WR
DA7:0 (XMBK = 0)
DA7:0 (XMBK = 1)
Address DataPrev. data XX
RD
AddressPrev. addr.
DataPrev. data Address
DataPrev. data Address
Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper
sector) or SRW00 (lower sector).
The ALE pulse in period T6 is only present if the next instruction accesses the RAM
(internal or external).
Write
Read
2549K–AVR–01/07
29
Figure 18. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 1
System Clock (CLK
CPU
)
T1 T2 T3
ALE
T4 T5 T6
(1)
T7
Using all Locations of External Memory Smaller than 64 KB
A15:8
DA7:0
DA7:0 (XMBK = 0)
DA7:0 (XMBK = 1)
Address DataPrev. data XX
WR
RD
AddressPrev. addr.
DataPrev. data Address
DataPrev. data Address
Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper
sector) or SRW00 (lower sector).
The ALE pulse in period T7 is only present if the next instruction accesses the RAM
(internal or external).
Since the external memory is mapped after the internal memory as shown in Figure 13,
the external memory is not addressed when addressing the first 8,704 bytes of data
space. It may appear that the first 8,704 bytes of the external memory are inaccessible
(external memory addresses 0x0000 to 0x21FF). However, when connecting an external memory smaller than 64 KB, for example 32 KB, these locations are easily accessed
simply by addressing from address 0x8000 to 0xA1FF. Since the External Memory
Address bit A15 is not connected to the external memory, addresses 0x8000 to 0xA1FF
will appear as addresses 0x0000 to 0x21FF for the external memory. Addressing above
address 0xA1FF is not recommended, since this will address an external memory location that is already accessed by another (lower) address. To the Application software,
the external 32 KB memory will appear as one linear 32 KB address space from 0x2200
to 0xA1FF. This is illustrated in Figure 19.
Write
Read
30
Figure 19. Address Map with 32 KB External Memory
AVR Memory Map
0x0000
Internal Memory
0x21FF
0x2200
0x7FFF
0x8000
External
Memory
0x90FF
0x9100
ATmega640/1280/1281/2560/2561
External 32K SRAM
0x0000
0x7FFF
2549K–AVR–01/07
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