– 130 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers + Peripheral Control Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-chip 2-cycle Multiplier
• Non-volatile Program and Data Memories
– 64K Bytes of In-System Reprogrammable Flash
Endurance: 10,000 Write/Erase Cycles
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– 2K Bytes EEPROM
Endurance: 100,000 Write/Erase Cycles
– 4K Bytes Internal SRAM
– Up to 64K Bytes Optional External Memory Space
– Programming Lock for Software Security
– SPI Interface for In-System Programming
• JTAG (IEEE std. 1149.1 Compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
• Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– Two Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode, and
Capture Mode
– Real Time Counter with Separate Oscillator
– Two 8-bit PWM Channels
– 6 PWM Channels with Programmable Resolution from 1 to 16 Bits
– 8-channel, 10-bit ADC
8 Single-ended Channels
7 Differential Channels
2 Differential Channels with Programmable Gain (1x, 10x, 200x)
– Byte-oriented Two-wire Serial Interface
– Dual Programmable Serial USARTs
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with On-chip Oscillator
– On-chip Analog Comparator
• Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby
and Extended Standby
– Software Selectable Clock Frequency
– ATmega103 Compatibility Mode Selected by a Fuse
– Global Pull-up Disable
Note:The bottom pad under the MLF package should be soldered to ground.
DisclaimerTypical values contained in this data sheet are based on simulations and characteriza-
tion of other AVR microcontrollers manufactured on the same process technology. Min
and Max values will be available after the device is characterized.
2
ATmega64(L)
2490I–AVR–11/04
ATmega64(L)
Overview
The ATmega64 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing
powerful instructions in a single clock cycle, the ATmega64 achieves throughputs approaching 1 MIPS per MHz, allowing
the system designer to optimize power consumption versus processing speed.
Block Diagram
Figure 2. Block Diagram
VCC
GND
AVCC
AGND
AREF
PEN
DATAREGISTER
JTAG TAP
ON-CHIP DEBUG
BOUNDARY-
SCAN
PROGRAMMING
LOGIC
PORTF
PORTF DRIVERS
ADC
PROGRAM
COUNTER
PROGRAM
FLASH
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
DATADIR.
REG. PORTF
DATAREGISTER
PORTA
STACK
POINTER
SRAM
GENERAL
PURPOSE
REGISTERS
X
Y
Z
PA0 - PA7PF0 - PF7
PORTA DRIVERS
DATADIR.
REG. PORTA
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
MCU CONTROL
REGISTER
TIMER/
COUNTERS
INTERRUPT
UNIT
DATAREGISTER
PORTC DRIVERS
PORTC
CALIB. OSC
OSCILLATOR
OSCILLATOR
TIMING AND
CONTROL
PC0 - PC7
DATADIR.
REG. PORTC
8-BIT DATA BUS
XTAL1
XTAL2
RESET
ANALOG
COMPARATOR
DATAREGISTER
+
-
USART0
PORTE
CONTROL
LINES
REG. PORTE
PORTE DRIVERS
DATADIR.
ALU
STATUS
REGISTER
DATAREGISTER
PORTB
PORTB DRIVERS
PB0 - PB7PE0 - PE7
EEPROM
DATADIR.
REG. PORTB
SPI
USART1
DATAREGISTER
PORTD
2-WIRE SERIAL
PORTD DRIVERS
PD0 - PD7
INTERFACE
DATADIR.
REG. PORTD
DATAREG.
PORTG
PORTG DRIVERS
PG0 - PG4
DATADIR.
REG. PORTG
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly
connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction
executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times
faster than conventional CISC microcontrollers.
2490I–AVR–11/04
3
The ATmega64 provides the following features: 64K bytes of In-System Programmable
Flash with Read-While-Write capabilities, 2K bytes EEPROM, 4K bytes SRAM, 53 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC),
four flexible Timer/Counters with compare modes and PWM, two USARTs, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input
stage with programmable gain, programmable Watchdog Timer with internal Oscillator,
an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for
accessing the On-chip Debug system and programming, and six software selectable
power saving modes. The Idle mode stops the CPU while allowing the SRAM,
Timer/Counters, SPI port, and interrupt system to continue functioning. The Powerdown mode saves the register contents but freezes the Oscillator, disabling all other
chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the
rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all
I/O modules except asynchronous timer and ADC, to minimize switching noise during
ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the
rest of the device is sleeping. This allows very fast start-up combined with low power
consumption. In Extended Standby mode, both the main Oscillator and the asynchronous timer continue to run.
The device is manufactured using Atmel’s high-density non-volatile memory technology.
The On-chip ISP Flash allows the program memory to be reprogrammed In-System
through an SPI serial interface, by a conventional non-volatile memory programmer, or
by an On-chip Boot program running on the AVR core. The Boot Program can use any
interface to download the Application Program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is
updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU
with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega64 is
a powerful microcontroller that provides a highly-flexible and cost-effective solution to
many embedded control applications.
ATmega103 and
ATmega64 Compatibility
The ATmega64 AVR is supported with a full suite of program and system development
tools including: C compilers, macro assemblers, program debugger/simulators, In-Circuit Emulators, and evaluation kits.
The ATmega64 is a highly complex microcontroller where the number of I/O locations
supersedes the 64 I/O location reserved in the AVR instruction set. To ensure backward
compatibility with the ATmega103, all I/O locations present in ATmega103 have the
same location in ATmega64. Most additional I/O locations are added in an Extended I/O
space starting from 0x60 to 0xFF (i.e., in the ATmega103 internal RAM space). These
location can be reached by using LD/LDS/LDD and ST/STS/STD instructions only, not
by using IN and OUT instructions. The relocation of the internal RAM space may still be
a problem for ATmega103 users. Also, the increased number of Interrupt Vectors might
be a problem if the code uses absolute addresses. To solve these problems, an
ATmega103 compatibility mode can be selected by programming the fuse M103C. In
this mode, none of the functions in the Extended I/O space are in use, so the internal
RAM is located as in ATmega103. Also, the extended Interrupt Vectors are removed.
The ATmega64 is 100% pin compatible with ATmega103, and can replace the
ATmega103 on current printed circuit boards. The application notes “Replacing
ATmega103 by ATmega128” and “Migration between ATmega64 and ATmega128”
describes what the user should be aware of replacing the ATmega103 by an
ATmega128 or ATmega64.
4
ATmega64(L)
2490I–AVR–11/04
ATmega64(L)
ATmega103 Compatibility
Mode
By programming the M103C Fuse, the ATmega64 will be compatible with the
ATmega103 regards to RAM, I/O pins and Interrupt Vectors as described above. However, some new features in ATmega64 are not available in this compatibility mode,
these features are listed below:
•One USART instead of two, asynchronous mode only. Only the eight least
significant bits of the Baud Rate Register is available.
•One 16 bits Timer/Counter with two compare registers instead of two 16 bits
Timer/Counters with three compare registers.
•Two-wire serial interface is not supported.
•Port G serves alternate functions only (not a general I/O port).
•Port F serves as digital input only in addition to analog input to the ADC.
•Boot Loader capabilities is not supported.
•It is not possible to adjust the frequency of the internal calibrated RC Oscillator.
•The External Memory Interface can not release any Address pins for general I/O,
neither configure different wait states to different External Memory Address
sections.
•Only EXTRF and PORF exist in the MCUCSR Register.
•No timed sequence is required for Watchdog Timeout change.
•Only low-level external interrupts can be used on four of the eight External Interrupt
sources.
•Port C is output only.
•USART has no FIFO buffer, so Data OverRun comes earlier.
•The user must have set unused I/O bits to 0 in ATmega103 programs.
Pin Descriptions
VCCDigital supply voltage.
GNDGround.
Port A (PA7..PA0)Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port A output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port A pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port A also serves the functions of various special features of the ATmega64 as listed
on page 72.
Port B (PB7..PB0)Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port B output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port B pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port B also serves the functions of various special features of the ATmega64 as listed
on page 73.
2490I–AVR–11/04
5
Port C (PC7..PC0)Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port C output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port C pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port C also serves the functions of special features of the ATmega64 as listed on page
76. In ATmega103 compatibility mode, Port C is output only, and the port C pins are not
tri-stated when a reset condition becomes active.
Port D (PD7..PD0)Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port D output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port D pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port D also serves the functions of various special features of the ATmega64 as listed
on page 77.
Port E (PE7..PE0)Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port E output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port E pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port E also serves the functions of various special features of the ATmega64 as listed
on page 80.
Port F (PF7..PF0)Port F serves as the analog inputs to the A/D Converter.
Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used.
Port pins can provide internal pull-up resistors (selected for each bit). The Port F output
buffers have symmetrical drive characteristics with both high sink and source capability.
As inputs, Port F pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port F pins are tri-stated when a reset condition becomes
active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS) and PF4(TCK) will be activated even if a reset occurs.
The TDO pin is tri-stated unless TAP states that shift out data are entered.
Port F also serves the functions of the JTAG interface.
In ATmega103 compatibility mode, Port F is an input port only.
Port G (PG4..PG0)Port G is a 5-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port G output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port G pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port G also serves the functions of various special features.
In ATmega103 compatibility mode, these pins only serves as strobes signals to the
external memory as well as input to the 32 kHz Oscillator, and the pins are initialized to
PG0 = 1, PG1 = 1, and PG2 = 0 asynchronously when a reset condition becomes
active, even if the clock is not running. PG3 and PG4 are Oscillator pins.
6
ATmega64(L)
2490I–AVR–11/04
ATmega64(L)
RESETReset input. A low level on this pin for longer than the minimum pulse length will gener-
ate a reset, even if the clock is not running. The minimum pulse length is given in Table
19 on page 51. Shorter pulses are not guaranteed to generate a reset.
XTAL1Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
XTAL2Output from the inverting Oscillator amplifier.
AVCCAVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally
connected to V
nected to V
AREFAREF is the analog reference pin for the A/D Converter.
PENThis is a programming enable pin for the SPI Serial Programming mode. By holding this
pin low during a Power-on Reset, the device will enter the SPI Serial Programming
mode. PEN
, even if the ADC is not used. If the ADC is used, it should be con-
CC
through a low-pass filter.
CC
has no function during normal operation.
About Code
Examples
This datasheet contains simple code examples that briefly show how to use various
parts of the device. These code examples assume that the part specific header file is
included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please
confirm with the C compiler documentation for more details.
2490I–AVR–11/04
7
AVR CPU Core
IntroductionThis section discusses the AVR core architecture in general. The main function of the
CPU core is to ensure correct program execution. The CPU must therefore be able to
access memories, perform calculations, control peripherals, and handle interrupts.
Architectural OverviewFigure 3. Block Diagram of the AVR MCU Architecture
Data Bus 8-bit
Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Control Lines
Program
Counter
Direct Addressing
Status
and Control
32 x 8
General
Purpose
Registrers
ALU
Indirect Addressing
Data
SRAM
EEPROM
Interrupt
Unit
SPI
Unit
Watchdog
Timer
Analog
Comparator
I/O Module1
I/O Module 2
I/O Module n
I/O Lines
In order to maximize performance and parallelism, the AVR uses a Harvard architecture
– with separate memories and buses for program and data. Instructions in the program
memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept
enables instructions to be executed in every clock cycle. The program memory is InSystem Reprogrammable Flash memory.
The fast-access Register File contains 32 x 8-bit general purpose working registers with
a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU)
operation. In a typical ALU operation, two operands are output from the Register File,
the operation is executed, and the result is stored back in the Register File – in one
clock cycle.
8
ATmega64(L)
2490I–AVR–11/04
ATmega64(L)
Six of the 32 registers can be used as three 16-bit indirect address register pointers for
Data Space addressing – enabling efficient address calculations. One of the these
address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register,
described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After
an arithmetic operation, the Status Register is updated to reflect information about the
result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions,
able to directly address the whole address space. Most AVR instructions have a single
16-bit word format. Every program memory address contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot program section and
the Application program section. Both sections have dedicated Lock bits for write and
read/write protection. The SPM instruction that writes into the Application Flash memory
section must reside in the Boot program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is
stored on the Stack. The Stack is effectively allocated in the general data SRAM, and
consequently the Stack size is only limited by the total SRAM size and the usage of the
SRAM. All user programs must initialize the SP in the reset routine (before subroutines
or interrupts are executed). The Stack Pointer SP is read/write accessible in the I/O
space. The data SRAM can easily be accessed through the five different addressing
modes supported in the AVR architecture.
ALU – Arithmetic Logic
Unit
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional
Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt
Vector in the Interrupt Vector table. The interrupts have priority in accordance with their
Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses which can be accessed directly, or as the
Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the
ATmega64 has Extended I/O space from 0x60 - 0xFF in SRAM where only the
ST/STS/STD and LD/LDS/LDD instructions can be used.
The high-performance AVR ALU operates in direct connection with all the 32 general
purpose working registers. Within a single clock cycle, arithmetic operations between
general purpose registers or between a register and an immediate are executed. The
ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier
supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.
2490I–AVR–11/04
9
Status RegisterThe Status Register contains information about the result of the most recently executed
arithmetic instruction. This information can be used for altering program flow in order to
perform conditional operations. Note that the Status Register is updated after all ALU
operations, as specified in the Instruction Set Reference. This will in many cases
remove the need for using the dedicated compare instructions, resulting in faster and
more compact code.
The Status Register is not automatically stored when entering an interrupt routine and
restored when returning from an interrupt. This must be handled by software.
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global
Interrupt Enable Register is cleared, none of the interrupts are enabled independent of
the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt
has occurred, and is set by the RETI instruction to enable subsequent interrupts. The Ibit can also be set and cleared in software with the SEI and CLI instructions, as
described in the instruction set reference.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or
destination for the operated bit. A bit from a register in the Register File can be copied
into T by the BST instruction, and a bit in T can be copied into a bit in a register in the
Register File by the BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is
useful in BCD arithmetic. See the “Instruction Set Description” for detailed information.
• Bit 4 – S: Sign Bit, S = N
⊕ V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See
the “Instruction Set Description” for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See
the “Instruction Set Description” for detailed information.
10
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the
“Instruction Set Description” for detailed information.
ATmega64(L)
2490I–AVR–11/04
ATmega64(L)
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.
General Purpose
Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to
achieve the required performance and flexibility, the following input/output schemes are
supported by the Register File:
•One 8-bit output operand and one 8-bit result input.
•Two 8-bit output operands and one 8-bit result input.
•Two 8-bit output operands and one 16-bit result input.
•One 16-bit output operand and one 16-bit result input.
Figure 4 shows the structure of the 32 general purpose working registers in the CPU.
Figure 4. AVR CPU General Purpose Working Registers
…
R260x1AX-register Low Byte
R270x1BX-register High Byte
R280x1CY-register Low Byte
R290x1DY-register High Byte
R300x1EZ-register Low Byte
R310x1FZ-register High Byte
2490I–AVR–11/04
Most of the instructions operating on the Register File have direct access to all registers,
and most of them are single cycle instructions.
As shown in Figure 4, each register is also assigned a data memory address, mapping
them directly into the first 32 locations of the user data space. Although not being physically implemented as SRAM locations, this memory organization provides great
flexibility in access of the registers, as the X-, Y-, and Z-pointer registers can be set to
index any register in the file.
11
X-, Y-, and Z-registerThe registers R26..R31 have some added functions to their general purpose usage.
These registers are 16-bit address pointers for indirect addressing of the data space.
The three indirect address registers X, Y, and Z are defined as described in Figure 5.
Figure 5. The X-, Y-, and Z-Registers
15XHXL0
X - register7070
R27 (0x1B)R26 (0x1A)
15YHYL0
Y - register7070
R29 (0x1D)R28 (0x1C)
15ZHZL0
Z - register7070
R31 (0x1F)R30 (0x1E)
In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the Instruction Set
Reference for details).
Stack PointerThe Stack is mainly used for storing temporary data, for storing local variables and for
storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing
from higher memory locations to lower memory locations. This implies that a Stack
PUSH command decreases the Stack Pointer. If software reads the Program Counter
from the Stack after a call or an interrupt, unused bits (bit 15) should be masked out.
The Stack Pointer points to the data SRAM Stack area where the subroutine and interrupt Stacks are located. This Stack space in the data SRAM must be defined by the
program before any subroutine calls are executed or interrupts are enabled. The Stack
Pointer must be set to point above 0x60. The Stack Pointer is decremented by one
when data is pushed onto the Stack with the PUSH instruction, and it is decremented by
two when the return address is pushed onto the Stack with subroutine call or interrupt.
The Stack Pointer is incremented by one when data is popped from the Stack with the
POP instruction, and it is incremented by two when data is popped from the Stack with
return from subroutine RET or return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some
implementations of the AVR architecture is so small that only SPL is needed. In this
case, the SPH Register will not be present.
Bit151413121110 9 8
SP15SP14SP13SP12SP11SP10SP9SP8SPH
SP7SP6SP5SP4SP3SP2SP1SP0SPL
76543210
Read/WriteR/WR/WR/WR/WR/WR/WR/WR/W
R/WR/WR/WR/WR/WR/WR/WR/W
Initial Value00000000
00000000
12
ATmega64(L)
2490I–AVR–11/04
ATmega64(L)
Instruction Execution
Timing
This section describes the general access timing concepts for instruction execution. The
AVR CPU is driven by the CPU clock clk
, directly generated from the selected clock
CPU
source for the chip. No internal clock division is used.
Figure 6 shows the parallel instruction fetches and instruction executions enabled by the
Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for
functions per cost, functions per clocks, and functions per power-unit.
Figure 6. The Parallel Instruction Fetches and Instruction Executions
T1T2T3T4
clk
CPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 7 shows the internal timing concept for the Register File. In a single clock cycle
an ALU operation using two register operands is executed, and the result is stored back
to the destination register.
Reset and Interrupt
Handling
Figure 7. Single Cycle ALU Operation
T1T2T3T4
clk
CPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
The AVR provides several different interrupt sources. These interrupts and the separate
Reset Vector each have a separate program vector in the program memory space. All
interrupts are assigned individual enable bits which must be written logic one together
with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt.
Depending on the Program Counter value, interrupts may be automatically disabled
when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software
security. See the section “Memory Programming” on page 291 for details.
The lowest addresses in the program memory space are by default defined as the Reset
and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 60.
The list also determines the priority levels of the different interrupts. The lower the
address the higher is the priority level. RESET has the highest priority, and next is INT0
– the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of
the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR).
Refer to “Interrupts” on page 60 for more information. The Reset Vector can also be
2490I–AVR–11/04
13
moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see
“Boot Loader Support – Read-While-Write Self-programming” on page 278.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts
are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is
automatically set when a Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that
sets the interrupt flag. For these interrupts, the Program Counter is vectored to the
actual Interrupt Vector in order to execute the interrupt handling routine, and hardware
clears the corresponding interrupt flag. Interrupt flags can also be cleared by writing a
logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the
corresponding interrupt enable bit is cleared, the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or
more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the Global Interrupt Enable
bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present.
These interrupts do not necessarily have interrupt flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by
software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately
disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to
avoid interrupts during the timed EEPROM write sequence.
Assembly Code Example
in r16, SREG; store SREG value
cli ; disable interrupts during timed sequence
sbi EECR, EEMWE; start EEPROM write
sbi EECR, EEWE
out SREG, r16; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1<<EEMWE); /* start EEPROM write */
EECR |= (1<<EEWE);
SREG = cSREG; /* restore SREG value (I-bit) */
14
ATmega64(L)
2490I–AVR–11/04
ATmega64(L)
When using the SEI instruction to enable interrupts, the instruction following SEI will be
executed before any pending interrupts, as shown in this example.
Assembly Code Example
sei; set global interrupt enable
sleep ; enter sleep, waiting for interrupt
; note: will enter sleep before any pending
; interrupt(s)
C Code Example
_SEI(); /* set global interrupt enable */
_SLEEP(); /*enter sleep, waiting for interrupt */
/* note: will enter sleep before any pending interrupt(s) */
Interrupt Response TimeThe interrupt execution response for all the enabled AVR interrupts is four clock cycles
minimum. After four clock cycles the program vector address for the actual interrupt
handling routine is executed. During this four clock cycle period, the Program Counter is
pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this
jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle
instruction, this instruction is completed before the interrupt is served. If an interrupt
occurs when the MCU is in sleep mode, the interrupt execution response time is
increased by four clock cycles. This increase comes in addition to the start-up time from
the selected sleep mode.
A return from an interrupt handling routine takes four clock cycles. During these four
clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack
Pointer is incremented by two, and the I-bit in SREG is set.
2490I–AVR–11/04
15
AVR ATme ga 64
Memories
This section describes the different memories in the ATmega64. The AVR architecture
has two main memory spaces, the Data Memory and the Program Memory space. In
addition, the ATmega64 features an EEPROM Memory for data storage. All three memory spaces are linear and regular.
In-System
Reprogrammable Flash
Program Memory
The ATmega64 contains 64K bytes On-chip In-System Reprogrammable Flash memory
for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 32K x 16. For software security, the Flash Program memory space is divided
into two sections, Boot Program section and Application Program section.
The Flash memory has an endurance of at least 10,000 write/erase cycles. The
ATmega64 Program Counter (PC) is 15 bits wide, thus addressing the 32K program
memory locations. The operation of Boot Program section and associated Boot Lock
bits for software protection are described in detail in “Boot Loader Support – ReadWhile-Write Self-programming” on page 278. “Memory Programming” on page 291 contains a detailed description on Flash programming in SPI, JTAG, or Parallel
Programming mode.
Constant tables can be allocated within the entire program memory address space (see
the LPM – Load Program Memory instruction description).
Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Timing” on page 13.
Figure 8. Program Memory Map
$0000
16
Application Flash Section
Boot Flash Section
$7FFF
ATmega64(L)
2490I–AVR–11/04
ATmega64(L)
SRAM Data MemoryThe ATmega64 supports two different configurations for the SRAM data memory as
listed in Table 1.
Table 1. Memory Configurations
Internal SRAM
Configuration
Normal mode4096up to 64K
ATmega103 compatibility mode4000up to 64K
Figure 9 on page 18 shows how the ATmega64 SRAM Memory is organized.
The ATmega64 is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions.
For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and
LD/LDS/LDD instructions can be used. The Extended I/O space does not exist when the
ATmega64 is in the ATmega103 compatibility mode.
The first 4,352 data memory locations address both the Register File, the I/O memory,
Extended I/O memory, and the internal data SRAM. The first 32 locations address the
Register File, the next 64 location the standard I/O memory, then 160 locations of
Extended I/O memory, and the next 4,096 locations address the internal data SRAM.
In ATmega103 compatibility mode, the first 4,096 data memory locations address both
the Register File, the I/O memory and the internal data SRAM. The first 32 locations
address the Register File, the next 64 location the standard I/O memory, and the next
4,000 locations address the internal data SRAM.
An optional external data SRAM can be used with the ATmega64. This SRAM will
occupy an area in the remaining address locations in the 64K address space. This area
starts at the address following the internal SRAM. The Register File, I/O, Extended I/O
and internal SRAM occupy the lowest 4,352 bytes in Normal mode, and the lowest
4,096 bytes in the ATmega103 compatibility mode (Extended I/O not present), so when
using 64KB (65,536 bytes) of External memory, 61,184 Bytes of External memory are
available in Normal mode, and 61,440 Bytes in ATmega103 compatibility mode. See
“External Memory Interface” on page 25 for details on how to take advantage of the
external memory map.
Data Memory
External SRAM
Data Memory
2490I–AVR–11/04
When the addresses accessing the SRAM memory space exceeds the internal data
memory locations, the external data SRAM is accessed using the same instructions as
for the internal data memory access. When the internal data memories are accessed,
the read and write strobe pins (PG0 and PG1) are inactive during the whole access
cycle. External SRAM operation is enabled by setting the SRE bit in the MCUCR
Register.
Accessing external SRAM takes one additional clock cycle per byte compared to access
of the internal SRAM. This means that the commands LD, ST, LDS, STS, LDD, STD,
PUSH, and POP take one additional clock cycle. If the Stack is placed in external
SRAM, interrupts, subroutine calls and returns take three clock cycles extra because the
2-byte Program Counter is pushed and popped, and external memory access does not
take advantage of the internal pipeline memory access. When external SRAM interface
is used with wait state, one-byte external access takes two, three, or four additional
clock cycles for one, two, and three wait states respectively. Interrupt, subroutine calls
and returns will need five, seven, or nine clock cycles more than specified in the AVR
Instruction Set manual for one, two, and three waitstates.
17
The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In
the Register File, registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base
address given by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and postincrement, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O Registers, 160 extended I/O Registers, and the 4,096 bytes of internal data SRAM in the ATmega64 are all accessible
through all these addressing modes. The Register File is described in “General Purpose
Register File” on page 11.
Figure 9. Data Memory Map
Memory Configuration A
Data Memory
32 Registers
64 I/O Registers
160 Ext I/O Reg.
Internal SRAM
(4096 x 8)
External SRAM
(0 - 64K x 8)
$0000 - $001F
$0020 - $005F
$0060 - $00FF
$0100
$10FF
$1100
Memory Configuration B
Data Memory
32 Registers
64 I/O Registers
Internal SRAM
(4000 x 8)
External SRAM
(0 - 64K x 8)
$0000 - $001F
$0020 - $005F
$0060
$0FFF
$1000
18
ATmega64(L)
$FFFF
$FFFF
2490I–AVR–11/04
ATmega64(L)
Data Memory Access TimesThis section describes the general access timing concepts for internal memory access.
The internal data SRAM access is performed in two clk
10.
Figure 10. On-chip Data SRAM Access Cycles
T1T2T3
clk
CPU
Address
Compute Address
Address Valid
Data
cycles as described in Figure
CPU
WR
Write
Data
RD
Memory Access Instruction
Next Instruction
Read
EEPROM Data MemoryThe ATmega64 contains 2K bytes of data EEPROM memory. It is organized as a sepa-
rate data space, in which single bytes can be read and written. The EEPROM has an
endurance of at least 100,000 write/erase cycles. The access between the EEPROM
and the CPU is described in the following, specifying the EEPROM Address Registers,
the EEPROM Data Register, and the EEPROM Control Register.
“Memory Programming” on page 291 contains a detailed description on EEPROM programming in SPI, JTAG, or Parallel Programming mode.
EEPROM Read/Write AccessThe EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in Table 2 on page 22. A self-timing
function, however, lets the user software detect when the next byte can be written. If the
user code contains instructions that write the EEPROM, some precautions must be
taken. In heavily filtered power supplies, V
up/down. This causes the device for some period of time to run at a voltage lower than
specified as minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page 24. for details on how to avoid problems in these situations.
is likely to rise or fall slowly on Power-
CC
2490I–AVR–11/04
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next
instruction is executed. When the EEPROM is written, the CPU is halted for two clock
cycles before the next instruction is executed.
19
EEPROM Address Register –
EEARH and EEARL
Bit151413121110 9 8
–––––EEAR10EEAR9EEAR8EEARH
EEAR7EEAR6EEAR5EEAR4EEAR3EEAR2EEAR1EEAR0EEARL
76543210
Read/WriteRRRRRR/WR/WR/W
R/WR/WR/WR/WR/WR/WR/WR/W
Initial Value00000XXX
XXXXXXXX
• Bits 15..11 – Res: Reserved Bits
These are reserved bits and will always read as zero. When writing to this address location, write these bits to zero for compatibility with future devices.
• Bits 10..0 – EEAR10..0: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address
in the 2K bytes EEPROM space. The EEPROM data bytes are addressed linearly
between 0 and 2,048. The Initial Value of EEAR is undefined. A proper value must be
written before the EEPROM may be accessed.
For the EEPROM write operation, the EEDR Register contains the data to be written to
the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by
EEAR.
Bit76543210
––––EERIEEEMWEEEWEEEREEECR
Read/WriteRRRRR/WR/WR/WR/W
Initial Value000000X0
• Bits 7..4 – Res: Reserved Bits
These bits are reserved bits in the ATmega64 and will always read as zero.
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set.
Writing EERIE to zero disables the interrupt. The EEPROM Ready Interrupt generates a
constant interrupt when EEWE is cleared.
20
ATmega64(L)
2490I–AVR–11/04
ATmega64(L)
• Bit 2 – EEMWE: EEPROM Master Write Enable
The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be
written. When EEMWE is written to one, writing EEWE to one within four clock cycles
will write data to the EEPROM at the selected address. If EEMWE is zero, writing EEWE
to one will have no effect. When EEMWE has been written to one by software, hardware
clears the bit to zero after four clock cycles. See the description of the EEWE bit for an
EEPROM write procedure.
• Bit 1 – EEWE: EEPROM Write Enable
The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When
address and data are correctly set up, the EEWE bit must be set to write the value into
the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE,
otherwise no EEPROM write takes place. The following procedure should be followed
when writing the EEPROM (the order of steps 3 and 4 is not essential):
1. Wait until EEWE becomes zero.
2. Wait until SPMEN in SPMCSR becomes zero.
3. Write new EEPROM address to EEAR (optional).
4. Write new EEPROM data to EEDR (optional).
5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.
6. Within four clock cycles after setting EEMWE, write a logical one to EEWE.
The EEPROM can not be programmed during a CPU write to the Flash memory. The
software must check that the Flash programming is completed before initiating a new
EEPROM write. Step 2 is only relevant if the software contains a Boot Loader allowing
the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2
can be omitted. See “Boot Loader Support – Read-While-Write Self-programming” on
page 278 for details about Boot programming.
Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the
EEPROM Master Write Enable will time-out. If an interrupt routine accessing the
EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be
modified, causing the interrupted EEPROM access to fail. It is recommended to have
the Global Interrupt Flag cleared during the four last steps to avoid these problems.
When the write access time has elapsed, the EEWE bit is cleared by hardware. The
user software can poll this bit and wait for a zero before writing the next byte. When
EEWE has been set, the CPU is halted for two cycles before the next instruction is
executed.
• Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the
correct address is set up in the EEAR Register, the EERE bit must be written to a logic
one to trigger the EEPROM read. The EEPROM read access takes one instruction, and
the requested data is available immediately. When the EEPROM is read, the CPU is
halted for four cycles before the next instruction is executed.
The user should poll the EEWE bit before starting the read operation. If a write operation
is in progress, it is neither possible to read the EEPROM, nor to change the EEAR
Register.
2490I–AVR–11/04
The calibrated Oscillator is used to time the EEPROM accesses. Table 2 lists the typical
programming time for EEPROM access from the CPU.
21
Table 2. EEPROM Programming Time
(1)
Number of Calibrated RC
Symbol
Oscillator CyclesTyp Programming Time
EEPROM write (from CPU)84488.4 ms
Note:1. Uses 1 MHz clock, independent of CKSEL Fuse settings.
The following code examples show one assembly and one C function for writing to the
EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The
examples also assume that no Flash boot loader is present in the software. If such code
is present, the EEPROM write function must also wait for any ongoing SPM command to
finish.
Assembly Code Example
EEPROM_write:
; Wait for completion of previous write
sbic EECR,EEWE
rjmp EEPROM_write
; Set up address (r18:r17) in address register
out EEARH, r18
out EEARL, r17
; Write data (r16) to data register
out EEDR,r16
; Write logical one to EEMWE
sbi EECR,EEMWE
; Start eeprom write by setting EEWE
sbi EECR,EEWE
ret
C Code Example
void EEPROM_write(unsigned int uiAddress, unsigned char ucData)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEWE))
;
/* Set up address and data registers */
EEAR = uiAddress;
EEDR = ucData;
/* Write logical one to EEMWE */
EECR |= (1<<EEMWE);
/* Start eeprom write by setting EEWE */
EECR |= (1<<EEWE);
}
22
ATmega64(L)
2490I–AVR–11/04
ATmega64(L)
The next code examples show assembly and C functions for reading the EEPROM. The
examples assume that interrupts are controlled so that no interrupts will occur during
execution of these functions.
Assembly Code Example
EEPROM_read:
; Wait for completion of previous write
sbic EECR,EEWE
rjmp EEPROM_read
; Set up address (r18:r17) in address register
out EEARH, r18
out EEARL, r17
; Start eeprom read by writing EERE
sbi EECR,EERE
; Read data from data register
in r16,EEDR
ret
C Code Example
unsigned char EEPROM_read(unsigned int uiAddress)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEWE))
;
/* Set up address register */
EEAR = uiAddress;
/* Start eeprom read by writing EERE */
EECR |= (1<<EERE);
/* Return data from data register */
return EEDR;
}
EEPROM Write During Powerdown Sleep Mode
2490I–AVR–11/04
When entering Power-down Sleep mode while an EEPROM write operation is active,
the EEPROM write operation will continue, and will complete before the Write Access
time has passed. However, when the write operation is completed, the oscillator continues running, and as a consequence, the device does not enter Power-down entirely. It is
therefore recommended to verify that the EEPROM write operation is completed before
entering Power-down.
23
Preventing EEPROM
Corruption
During periods of low V
age is too low for the CPU and the EEPROM to operate properly. These issues are the
same as for board level systems using EEPROM, and the same design solutions should
be applied.
An EEPROM data corruption can be caused by two situations when the voltage is too
low. First, a regular write sequence to the EEPROM requires a minimum voltage to
operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the
supply voltage is too low.
EEPROM data corruption can easily be avoided by following this design
recommendation:
Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD). If the
detection level of the internal BOD does not match the needed detection level, an
external low V
operation is in progress, the write operation will be completed provided that the
power supply voltage is sufficient.
CC
the EEPROM data can be corrupted because the supply volt-
CC,
Reset Protection circuit can be used. If a reset occurs while a write
I/O MemoryThe I/O space definition of the ATmega64 is shown in “Register Summary” on page 372.
All ATmega64 I/Os and peripherals are placed in the I/O space. All I/O locations may be
accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between
the 32 general purpose working registers and the I/O space. I/O Registers within the
address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and
SBIC instructions. Refer to the instruction set section for more details. When using the
I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used.
When addressing I/O Registers as data space using LD and ST instructions, 0x20 must
be added to these addresses. The ATmega64 is a complex microcontroller with more
peripheral units than can be supported within the 64 location reserved in Opcode for the
IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only
the ST/STS/STD and LD/LDS/LDD instructions can be used. The Extended I/O space is
replaced with SRAM locations when the ATmega64 is in the ATmega103 compatibility
mode.
24
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the status flags are cleared by writing a logical one to them. Note that the CBI
and SBI instructions will operate on all bits in the I/O Register, writing a one back into
any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
The I/O and peripherals control registers are explained in later sections.
ATmega64(L)
2490I–AVR–11/04
ATmega64(L)
External Memory
Interface
With all the features that the External Memory Interface provides, it is well suited to
operate as an interface to memory devices such as external SRAM and Flash, and
peripherals such as LCD-display, A/D, and D/A. The main features are:
•Four different wait-state settings (Including no wait-state).
•Independent wait-state setting for different external memory sectors (configurable
sector size).
•The number of bits dedicated to address high byte is selectable.
•Bus Keepers on data lines to minimize current consumption (optional).
OverviewWhen the eXternal MEMory (XMEM) is enabled, address space outside the internal
SRAM becomes available using the dedicated external memory pins (see Figure 1 on
page 2, Table 27 on page 72, Table 33 on page 76, and Table 45 on page 84). The
memory configuration is shown in Figure 11.
Figure 11. External Memory with Sector Select
Memory Configuration A
0x0000
Internal Memory
0x10FF
0x1100
Lower Sector
SRW01
SRW00
(1)
Memory Configuration B
0x0000
Internal Memory
0x0FFF
0x1000
SRL[2..0]
External Memory
(0-60K x 8)
Note:1. ATmega64 in non ATmega103 compatibility mode: Memory Configuration A is avail-
able (Memory Configuration B N/A).
ATmega64 in mega103 compatibility mode: Memory Configuration B is available
(Memory Configuration A N/A).
Upper Sector
SRW11
SRW10
0xFFFF
External Memory
(0-60K x 8)
SRW10
0xFFFF
2490I–AVR–11/04
25
ATmega103 CompatibilityBoth External Memory Control Registers, XMCRA and XMCRB, are placed in Extended
I/O space. In ATmega103 compatibility mode, these registers are not available, and the
features selected by these registers are not available. The device is still ATmega103
compatible, as these features did not exist in ATmega103. The limitations in
ATmega103 compatibility mode are:
•Only two wait-state settings are available (SRW1n = 0b00 and SRW1n = 0b01).
•The number of bits that are assigned to address high byte are fixed.
•The external memory section cannot be divided into sectors with different wait-state
settings.
•Bus Keeper is not available.
•RD
, WR, and ALE pins are output only (Port G in ATmega64).
Using the External Memory
Interface
The interface consists of:
•AD7:0: Multiplexed low-order address bus and data bus.
•A15:8: High-order address bus (configurable number of bits).
•ALE: Address latch enable.
•RD
•WR
: Read strobe.
: Write strobe.
The control bits for the External Memory Interface are located in three registers, the
MCU Control Register – MCUCR, the External Memory Control Register A – XMCRA,
and the External Memory Control Register B – XMCRB.
When the XMEM interface is enabled, the XMEM interface will override the setting in the
Data Direction Registers that corresponds to the ports dedicated to the XMEM interface.
For details about the port override, see the alternate functions in section “I/O Ports” on
page 65. The XMEM interface will auto-detect whether an access is internal or external.
If the access is external, the XMEM interface will output address, data, and the control
signals on the ports according to Figure 13 (this figure shows the wave forms without
wait states). When ALE goes from high-to-low, there is a valid address on AD7:0. ALE is
low during a data transfer. When the XMEM interface is enabled, also an internal access
will cause activity on address-, data- and ALE ports, but the RD
and WR strobes will not
toggle during internal access. When the external memory interface is disabled, the normal pin and data direction settings are used. Note that when the XMEM interface is
disabled, the address space above the internal SRAM boundary is not mapped into the
internal SRAM. Figure 12 illustrates how to connect an external SRAM to the AVR using
an octal latch (typically 74 x 573 or equivalent) which is transparent when G is high.
Address Latch RequirementsDue to the high-speed operation of the XRAM interface, the address latch must be
selected with care for system frequencies above 8 MHz @ 4V and 4 MHz @ 2.7V.
When operating at conditions above these frequencies, the typical old style 74HC series
latch becomes inadequate. The external memory interface is designed in compliance to
the 74AHC series latch. However, most latches can be used as long they comply with
the main timing parameters. The main parameters for the address latch are:
•D to Q propagation delay (t
•Data setup time before G low (t
•Data (address) hold time after G low (
).
pd
).
su
).
th
The external memory interface is designed to guaranty minimum address hold time after
G is asserted low of t
page 339). The D to Q propagation delay (t
= 5 ns (refer to t
h
LAXX_LD/tLLAXX_ST
) must be taken into consideration when
pd
in Table 137 to Table 144 on
calculating the access time requirement of the external component. The data setup time
26
ATmega64(L)
2490I–AVR–11/04
ATmega64(L)
before G low (tsu) must not exceed address valid to ALE low (t
delay (dependent on the capacitive load).
Figure 12. External SRAM Connected to the AVR
) minus PCB wiring
AVLLC
D[7:0]
AD7:0
ALE
DQ
G
A[7:0]
SRAM
AVR
A15:8
RD
WR
Pull-up and Bus KeeperThe pull-ups on the AD7:0 ports may be activated if the corresponding Port Register is
written to one. To reduce power consumption in sleep mode, it is recommended to disable the pull-ups by writing the Port Register to zero before entering sleep.
The XMEM interface also provides a Bus Keeper on the AD7:0 lines. The Bus Keeper
can be disabled and enabled in software as described in “External Memory Control Register B – XMCRB” on page 32. When enabled, the Bus Keeper will ensure a defined
logic level (zero or one) on the AD7:0 bus when these lines would otherwise be tri-stated
by the XMEM interface.
A[15:8]
RD
WR
TimingExternal memory devices have different timing requirements. To meet these require-
ments, the ATmega64 XMEM interface provides four different wait states as shown in
Table 4. It is important to consider the timing specification of the external memory
device before selecting the wait-state. The most important parameters are the access
time for the external memory compared to the set-up requirement of the ATmega64.
The access time for the external memory is defined to be the time from receiving the
chip select/address until the data of this address actually is driven on the bus. The
access time cannot exceed the time from the ALE pulse is asserted low until data must
be stable during a read sequence (t
339). The different wait states are set up in software. As an additional feature, it is possible to divide the external memory space in two sectors with individual wait-state
settings. This makes it possible to connect two different memory devices with different
timing requirements to the same XMEM interface. For XMEM interface timing details,
please refer to Figure 159 to Figure 162, and Table 137 to Table 144.
Note that the XMEM interface is asynchronous and that the waveforms in the following
figures are related to the internal system clock. The skew between the internal and
external clock (XTAL1) is not guaranteed (varies between devices, temperature, and
supply voltage). Consequently the XMEM interface is not suited for synchronous
operation.
LLRL
+ t
RLRH
- t
in Table 137 to Table 144 on page
DVRH
2490I–AVR–11/04
27
Figure 13. External Data Memory Cycles without Wait State
Writing SRE to one enables the External Memory Interface.The pin functions AD7:0,
A15:8, ALE, WR
, and RD are activated as the alternate pin functions. The SRE bit overrides any pin direction settings in the respective data direction registers. Writing SRE to
zero, disables the External Memory Interface and the normal pin and data direction settings are used.
• Bit 6 – SRW10: Wait State Select Bit
For a detailed description in non ATmega103 compatibility mode, see common description for the SRWn bits below (XMRA description). In ATmega103 compatibility mode,
writing SRW10 to one enables the wait state and one extra cycle is added during
read/write strobe as shown in Figure 14.
This is a reserved bit and will always read as zero. When writing to this address location,
write this bit to zero for compatibility with future devices.
• Bit 6..4 – SRL2, SRL1, SRL0: Wait State Sector Limit
It is possible to configure different wait states for different external memory addresses.
The external memory address space can be divided in two sectors that have separate
wait-state bits. The SRL2, SRL1, and SRL0 bits select the split of the sectors, see Table
3 and Figure 11. By default, the SRL2, SRL1, and SRL0 bits are set to zero and the
entire external memory address space is treated as one sector. When the entire SRAM
address space is configured as one sector, the wait states are configured by the SRW11
and SRW10 bits.
30
ATmega64(L)
2490I–AVR–11/04
Table 3. Sector Limits with Different Settings of SRL2..0
SRL2SRL1SRL0Sector Limits
000Lower sector = N/A
Upper sector = 0x1100 - 0xFFFF
001Lower sector = 0x1100 - 0x1FFF
Upper sector = 0x2000 - 0xFFFF
010Lower sector = 0x1100 - 0x3FFF
Upper sector = 0x4000 - 0xFFFF
011Lower sector = 0x1100 - 0x5FFF
Upper sector = 0x6000 - 0xFFFF
100Lower sector = 0x1100 - 0x7FFF
Upper sector = 0x8000 - 0xFFFF
101Lower sector = 0x1100 - 0x9FFF
Upper sector = 0xA000 - 0xFFFF
110Lower sector = 0x1100 - 0xBFFF
Upper sector = 0xC000 - 0xFFFF
111Lower sector = 0x1100 - 0xDFFF
Upper sector = 0xE000 - 0xFFFF
ATmega64(L)
• Bit 1 and Bit 6 MCUCR – SRW11, SRW10: Wait State Select Bits for Upper
Sector
The SRW11 and SRW10 bits control the number of wait states for the upper sector of
the external memory address space, see Table 4.
• Bit 3..2 – SRW01, SRW00: Wait State Select Bits for Lower Sector
The SRW01 and SRW00 bits control the number of wait states for the lower sector of
the external memory address space, see Table 4.
Table 4. Wait States
SRWn1SRWn0Wait States
00No wait states
01Wait one cycle during read/write strobe
10Wait two cycles during read/write strobe
11
Note:1. n = 0 or 1 (lower/upper sector).
For further details of the timing and wait states of the External Memory Interface, see
Figure 13 to Figure 16 how the setting of the SRW bits affects the timing.
(1)
Wait two cycles during read/write and wait one cycle before driving out
new address
• Bit 0 – Res: Reserved Bit
2490I–AVR–11/04
This is a reserved bit and will always read as zero. When writing to this address location,
write this bit to zero for compatibility with future devices.
31
External Memory Control
Register B – XMCRB
Bit76543210
XMBK––––XMM2XMM1XMM0XMCRB
Read/WriteR/WRRRRR/WR/WR/W
Initial Value00000000
• Bit 7 – XMBK: External Memory Bus Keeper Enable
Writing XMBK to one enables the Bus Keeper on the AD7:0 lines. When the Bus Keeper
is enabled, it will ensure a defined logic level (zero or one) on AD7:0 when they would
otherwise be tri-stated. Writing XMBK to zero disables the Bus Keeper. XMBK is not
qualified with SRE, so even if the XMEM interface is disabled, the Bus Keepers are still
activated as long as XMBK is one.
• Bit 6..3 – Res: Reserved Bits
These are reserved bits and will always read as zero. When writing to this address location, write these bits to zero for compatibility with future devices.
• Bit 2..0 – XMM2, XMM1, XMM0: External Memory High Mask
When the External Memory is enabled, all Port C pins are default used for the high
address byte. If the full 60KB address space is not required to access the external memory, some, or all, Port C pins can be released for normal port pin function as described in
Table 5. As described in “Using all 64KB Locations of External Memory” on page 34, it is
possible to use the XMMn bits to access all 64KB locations of the external memory.
Table 5. Port C Pins Released as Normal Port Pins when the External Memory is
Enabled
XMM2XMM1XMM0# Bits for External Memory AddressReleased Port Pins
0008 (Full 60 KB space)None
0017PC7
0106PC7 - PC6
0115PC7 - PC5
1004PC7 - PC4
1013PC7 - PC3
1102PC7 - PC2
111No Address high bitsFull Port C
32
ATmega64(L)
2490I–AVR–11/04
ATmega64(L)
Using all Locations of
External Memory Smaller than
64 KB
Since the external memory is mapped after the internal memory as shown in Figure 11,
the external memory is not addressed when addressing the first 4,352 bytes of data
space. It may appear that the first 4,352 bytes of the external memory are inaccessible
(external memory addresses 0x0000 to 0x10FF). However, when connecting an external memory smaller than 64 KB, for example 32 KB, these locations are easily accessed
simply by addressing from address 0x8000 to 0x90FF. Since the External Memory
Address bit A15 is not connected to the external memory, addresses 0x8000 to 0x90FF
will appear as addresses 0x0000 to 0x10FF for the external memory. Addressing above
address 0x90FF is not recommended, since this will address an external memory location that is already accessed by another (lower) address. To the Application software,
the external 32 KB memory will appear as one linear 32 KB address space from 0x1100
to 0x90FF. This is illustrated in Figure 17. Memory configuration B refers to the
ATmega103 compatibility mode, configuration A to the non-compatible mode.
When the device is set in ATmega103 compatibility mode, the internal address space is
4,096 bytes. This implies that the first 4,096 bytes of the external memory can be
accessed at addresses 0x8000 to 0x8FFF. To the Application software, the external 32
KB memory will appear as one linear 32 KB address space from 0x1000 to 0x8FFF.
Figure 17. Address Map with 32 KB External Memory
Memory Configuration B
AVR Memory Map
Internal Memory
External 32K SRAM
0x0000
0x0FFF
0x1000
0x0000
0x10FF
0x1100
Memory Configuration A
AVR Memory Map
Internal Memory
External 32K SRAM
0x0000
0x10FF
0x1100
0x0000
0x0FFF
0x1000
0x7FFF
0x8000
0x90FF
0x9100
0xFFFF
External
Memory
(Unused)
0x7FFF
0x7FFF
0x8000
0x8FFF
0x9000
0xFFFF
External
Memory
(Unused)
0x7FFF
2490I–AVR–11/04
33
Using all 64KB Locations of
External Memory
Since the external memory is mapped after the internal memory as shown in Figure 11,
only 60KB of external memory is available by default (address space 0x0000 to 0x10FF
is reserved for internal memory). However, it is possible to take advantage of the entire
external memory by masking the higher address bits to zero. This can be done by using
the XMMn bits and controlled by software the most significant bits of the address. By
setting Port C to output 0x00, and releasing the most significant bits for normal Port Pin
operation, the Memory Interface will address 0x0000 - 0x1FFF. See code examples
below.
Assembly Code Example
; OFFSET is defined to 0x2000 to ensure
; external memory access
; Configure Port C (address high byte) to
; output 0x00 when the pins are released
; for normal Port Pin operation
Note:1. The example code assumes that the part specific header file is included.
Care must be exercised using this option as most of the memory is masked away.
ATmega64(L)
2490I–AVR–11/04
System Clock and
Clock Options
ATmega64(L)
Clock Systems and their
Distribution
Figure 18 presents the principal clock systems in the AVR and their distribution. All of
the clocks need not be active at a given time. In order to reduce power consumption, the
clocks to modules not being used can be halted by using different sleep modes, as
described in “Power Management and Sleep Modes” on page 45. The clock systems
are detailed below.
Figure 18. Clock Distribution
Asynchronous
Timer/Counter
General I/O
Modules
clk
clk
ASY
ADCCPU CoreRAM
clk
ADC
I/O
AVR Clock
Control Unit
Source Clock
Clock
Multiplexer
clk
clk
Reset Logic
CPU
FLASH
Watchdog Clock
Watchdog Timer
Watchdog
Oscillator
Flash and
EEPROM
CPU Clock – clk
I/O Clock – clk
I/O
Flash Clock – clk
2490I–AVR–11/04
CPU
FLASH
Timer/Counter
Oscillator
External RC
Oscillator
External Clock
Crystal
Oscillator
Low-frequency
Crystal Oscillator
Calibrated RC
Oscillator
The CPU clock is routed to parts of the system concerned with operation of the AVR
core. Examples of such modules are the General Purpose Register File, the Status Register and the data memory holding the Stack Pointer. Halting the CPU clock inhibits the
core from performing general operations and calculations.
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and
USART. The I/O clock is also used by the External Interrupt module, but note that some
external interrupts are detected by asynchronous logic, allowing such interrupts to be
detected even if the I/O clock is halted. Also note that address recognition in the TWI
module is carried out asynchronously when clk
is halted, enabling TWI address recep-
I/O
tion in all sleep modes.
The Flash clock controls operation of the Flash interface. The Flash clock is usually
active simultaneously with the CPU clock.
35
Asynchronous Timer Clock –
clk
ASY
The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked
directly from an external 32 kHz clock crystal. The dedicated clock domain allows using
this Timer/Counter as a real-time counter even when the device is in sleep mode.
ADC Clock – clk
ADC
The ADC is provided with a dedicated clock domain. This allows halting the CPU and
I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results.
Clock SourcesThe device has the following clock source options, selectable by Flash Fuse bits as
shown below. The clock from the selected source is input to the AVR clock generator,
and routed to the appropriate modules.
Table 6. Device Clocking Options Select
Device Clocking Option CKSEL3..0
External Crystal/Ceramic Resonator1111 - 1010
External Low-frequency Crystal1001
External RC Oscillator1000 - 0101
Calibrated Internal RC Oscillator0100 - 0001
External Clock0000
Note:1. For all fuses “1” means unprogrammed while “0” means programmed.
The various choices for each clocking option is given in the following sections. When the
CPU wakes up from Power-down or Power-save, the selected clock source is used to
time the start-up, ensuring stable Oscillator operation before instruction execution starts.
When the CPU starts from reset, there is as an additional delay allowing the power to
reach a stable level before commencing normal operation. The Watchdog Oscillator is
used for timing this real-time part of the start-up time. The number of WDT Oscillator
cycles used for each time-out is shown in Table 7. The frequency of the Watchdog Oscillator is voltage dependent as shown in the “ATmega64 Typical Characteristics” on page
342.
(1)
36
Table 7. Number of Watchdog Oscillator Cycles
Typ Time-out (VCC = 5.0V)Typ Time-out (VCC = 3.0V)Number of Cycles
4.1 ms4.3 ms4K (4,096)
65 ms69 ms64K (65,536)
ATmega64(L)
2490I–AVR–11/04
ATmega64(L)
XTAL Divide Control Register
– XDIV
The XTAL Divide Control Register is used to divide the source clock frequency by a
number in the range 2 - 129. This feature can be used to decrease power consumption
when the requirement for processing power is low.
These bits define the division factor that applies when the XDIVEN bit is set (one). If the
value of these bits is denoted d, the following formula defines the resulting CPU and
peripherals clock frequency f
clk
:
f
CLK
Source clock
----------------------------------=
129 d–
The value of these bits can only be changed when XDIVEN is zero. When XDIVEN is
written to one, the value written simultaneously into XDIV6..XDIV0 is taken as the division factor. When XDIVEN is written to zero, the value written simultaneously into
XDIV6..XDIV0 is rejected. As the divider divides the master clock input to the MCU, the
speed of all peripherals is reduced when a division factor is used.
Note:When the system clock is divided, Timer/Counter0 can be used with Asynchronous clock
only. The frequency of the asynchronous clock must be lower than 1/4th of the frequency
of the scaled down Source clock. Otherwise, interrupts may be lost, and accessing the
Timer/Counter0 registers may fail.
Default Clock Source The device is shipped with CKSEL = “0001” and SUT = “10”. The default clock source
setting is therefore the Internal RC Oscillator with longest startup time. This default setting ensures that all users can make their desired clock source setting using an InSystem or Parallel Programmer.
Crystal OscillatorXTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can
be configured for use as an On-chip Oscillator, as shown in Figure 19. Either a quartz
crystal or a ceramic resonator may be used. The CKOPT Fuse selects between two different Oscillator amplifier modes. When CKOPT is programmed, the Oscillator output
will oscillate a full rail-to-rail swing on the output. This mode is suitable when operating
in a very noisy environment or when the output from XTAL2 drives a second clock
buffer. This mode has a wide frequency range. When CKOPT is unprogrammed, the
Oscillator has a smaller output swing. This reduces power consumption considerably.
This mode has a limited frequency range and it cannot be used to drive other clock
buffers.
For resonators, the maximum frequency is 8 MHz with CKOPT unprogrammed and
16 MHz with CKOPT programmed. C1 and C2 should always be equal for both crystals
and resonators. The optimal value of the capacitors depends on the crystal or resonator
in use, the amount of stray capacitance, and the electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for use with crystals are given in
37
2490I–AVR–11/04
Table 8. For ceramic resonators, the capacitor values given by the manufacturer should
be used.
Figure 19. Crystal Oscillator Connections
C2
C1
XTAL2
XTAL1
GND
The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..1 as shown in
Table 8.
Table 8. Crystal Oscillator Operating Modes
Frequency Range
CKOPTCKSEL3..1
1101
11100.9 - 3.012 - 22
11113.0 - 8.012 - 22
0101, 110, 1111.0 -12 - 22
Note:1. This option should not be used with crystals, only with ceramic resonators.
(1)
(MHz)
0.4 - 0.9–
Recommended Range for Capacitors
C1 and C2 for Use with Crystals (pF)
The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown
in Table 9.
38
ATmega64(L)
2490I–AVR–11/04
ATmega64(L)
Table 9. Start-up Times for the Crystal Oscillator Clock Selection
Start-up Time from
Power-down and
CKSEL0SUT1..0
000258 CK
001258 CK
010 1K CK
011 1K CK
100 1K CK
10116K CK–
11016K CK4.1 ms
11116K CK65 ms
Notes: 1. These options should only be used when not operating close to the maximum fre-
quency of the device, and only if frequency stability at start-up is not important for the
application. These options are not suitable for crystals.
2. These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They can also be used with crystals when not operating
close to the maximum frequency of the device, and if frequency stability at start-up is
not important for the application.
Power-save
(1)
(1)
(2)
(2)
(2)
Additional Delay
from Reset
(VCC = 5.0V)Recommended Usage
4.1 ms
65 ms
–
4.1 ms
65 ms
Ceramic resonator, fast
rising power
Ceramic resonator,
slowly rising power
Ceramic resonator, BOD
enabled
Ceramic resonator, fast
rising power
Ceramic resonator,
slowly rising power
Crystal Oscillator, BOD
enabled
Crystal Oscillator, fast
rising power
Crystal Oscillator, slowly
rising power
Low-frequency Crystal
Oscillator
To use a 32.768 kHz watch crystal as the clock source for the device, the Low-frequency crystal Oscillator must be selected by setting the CKSEL Fuses to “1001”. The
crystal should be connected as shown in Figure 19. By programming the CKOPT Fuse,
the user can enable internal capacitors on XTAL1 and XTAL2, thereby removing the
need for external capacitors. The internal capacitors have a nominal value of 36 pF.
When this Oscillator is selected, start-up times are determined by the SUT Fuses as
shown in Table 10.
Table 10. Start-up Times for the Low-frequency Crystal Oscillator Clock Selection
Start-up Time
from Power-down
SUT1..0
001K CK
011K CK
1032K CK65 msStable frequency at start-up
11Reserved
Note:1. These options should only be used if frequency stability at start-up is not important
and Power-save
(1)
(1)
for the application.
Additional Delay
from Reset
(VCC = 5.0V)Recommended Usage
4.1 msFast rising power or BOD enabled
65 msSlowly rising power
2490I–AVR–11/04
39
External RC OscillatorFor timing insensitive applications, the external RC configuration shown in Figure 20
can be used. The frequency is roughly estimated by the equation f = 1/(3RC). C should
be at least 22 pF. By programming the CKOPT Fuse, the user can enable an internal 36
pF capacitor between XTAL1 and GND, thereby removing the need for an external
capacitor. For more information on Oscillator operation and details on how to choose R
and C, refer to the External RC Oscillator application note.
Figure 20. External RC Configuration
V
CC
R
NC
XTAL2
XTAL1
C
GND
The Oscillator can operate in four different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..0 as shown in
Table 11.
Table 11. External RC Oscillator Operating Modes
CKSEL3..0 Frequency Range (MHz)
01010.1 - 0.9
01100.9 - 3.0
01113.0 - 8.0
10008.0 - 12.0
When this Oscillator is selected, start-up times are determined by the SUT Fuses as
shown in Table 12.
40
ATmega64(L)
Table 12. Start-up Times for the External RC Oscillator Clock Selection
Start-up Time from
Power-down and
SUT1..0
0018 CK–BOD enabled
0118 CK4.1 msFast rising power
1018 CK65 msSlowly rising power
116 CK
Note:1. This option should not be used when operating close to the maximum frequency of
Power-save
(1)
the device.
Additional Delay
from Reset
(VCC = 5.0V)Recommended Usage
4.1 msFast rising power or BOD enabled
2490I–AVR–11/04
ATmega64(L)
Calibrated Internal RC
Oscillator
The calibrated internal RC Oscillator provides a fixed 1.0, 2.0, 4.0, or 8.0 MHz clock. All
frequencies are nominal values at 5V and 25°C. This clock may be selected as the system clock by programming the CKSEL Fuses as shown in Table 13. If selected, it will
operate with no external components. The CKOPT Fuse should always be unprogrammed when using this clock option. During reset, hardware loads the calibration byte
into the OSCCAL Register and thereby automatically calibrates the RC Oscillator. At 5V,
25°C and 1.0 MHz Oscillator frequency selected, this calibration gives a frequency
within ± 3% of the nominal frequency. Using run-time calibration methods as described
in application notes available at www.atmel.com/avr it is possible to achieve ± 1% accuracy at any given V
and Temperature. When this Oscillator is used as the chip clock,
CC
the Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset
Time-out. For more information on the preprogrammed calibration value, see the section
“Calibration Byte” on page 294.
Note:1. The device is shipped with this option selected.
1.0
When this Oscillator is selected, start-up times are determined by the SUT Fuses as
shown in Table 14. XTAL1 and XTAL2 should be left unconnected (NC).
Oscillator Calibration Register
– OSCCAL
(1)
Table 14. Start-up Times for the Internal Calibrated RC Oscillator Clock Selection
Start-up Time from Power-
SUT1..0
006 CK–BOD enabled
016 CK4.1 msFast rising power
(1)
10
11Reserved
Note:1. The device is shipped with this option selected.
Bit76543210
Read/WriteR/WR/WR/WR/WR/WR/WR/WR/W
Initial ValueDevice Specific Calibration Value
Note:1. The OSCCAL Register is not available in ATmega103 compatibility mode.
down and Power-save
6 CK65 msSlowly rising power
CAL7CAL6CAL5CAL4CAL3CAL2CAL1CAL0OSCCAL
Additional Delay from
Reset (VCC = 5.0V)Recommended Usage
• Bits 7..0 – CAL7..0: Oscillator Calibration Value
Writing the calibration byte to this address will trim the internal Oscillator to remove process variations from the Oscillator frequency. During Reset, the 1 MHz calibration value
which is located in the signature row high byte (address 0x00) is automatically loaded
into the OSCCAL Register. If the internal RC is used at other frequencies, the calibration
values must be loaded manually. This can be done by first reading the signature row by
a programmer, and then store the calibration values in the Flash or EEPROM. Then the
2490I–AVR–11/04
41
value can be read by software and loaded into the OSCCAL Register. When OSCCAL is
zero, the lowest available frequency is chosen. Writing non-zero values to this register
will increase the frequency of the internal Oscillator. Writing 0xFF to the register gives
the highest available frequency. The calibrated Oscillator is used to time EEPROM and
Flash access. If EEPROM or Flash is written, do not calibrate to more than 10% above
the nominal frequency. Otherwise, the EEPROM or Flash write may fail. Note that the
Oscillator is intended for calibration to 1.0, 2.0, 4.0, or 8.0 MHz. Tuning to other values is
not guaranteed, as indicated in Table 15.
Table 15. Internal RC Oscillator Frequency Range
Min Frequency in Percentage of
OSCCAL Value
0x0050100
0x7F75150
0xFF100200
Nominal Frequency (%)
Max Frequency in Percentage of
Nominal Frequency (%)
External ClockTo drive the device from an external clock source, XTAL1 should be driven as shown in
Figure 21. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”. By programming the CKOPT Fuse, the user can enable an internal
36 pF capacitor between XTAL1 and GND.
Figure 21. External Clock Drive Configuration
EXTERNAL
CLOCK
SIGNAL
42
ATmega64(L)
When this clock source is selected, start-up times are determined by the SUT Fuses as
shown in Table 16.
Table 16. Start-up Times for the External Clock Selection
Start-up Time from Power-
SUT1..0
006 CK–BOD enabled
016 CK4.1 msFast rising power
106 CK65 msSlowly rising power
11Reserved
down and Power-save
Additional Delay from
Reset (VCC = 5.0V)Recommended Usage
When applying an external clock, it is required to avoid sudden changes in the applied
clock frequency to ensure stable operation of the MCU. A variation in frequency of more
than 2% from one clock cycle to the next can lead to unpredictable behavior. It is
2490I–AVR–11/04
ATmega64(L)
required to ensure that the MCU is kept in Reset during such changes in the clock
frequency.
2490I–AVR–11/04
43
Timer/Counter OscillatorFor AVR microcontrollers with Timer/Counter Oscillator pins (TOSC1 and TOSC2), the
crystal is connected directly between the pins. No external capacitors are needed. The
Oscillator is optimized for use with a 32.768 kHz watch crystal. Applying an external
clock source to TOSC1 is not recommended.
44
ATmega64(L)
2490I–AVR–11/04
ATmega64(L)
Power Management
and Sleep Modes
MCU Control Register –
MCUCR
Sleep modes enable the application to shut down unused modules in the MCU, thereby
saving power. The AVR provides various sleep modes allowing the user to tailor the
power consumption to the application’s requirements.
To enter any of the six sleep modes, the SE-bit in MCUCR must be written to logic one
and a SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the
MCUCR Register select which sleep mode (Idle, ADC Noise Reduction, Power-down,
Power-save, Standby, or Extended Standby) will be activated by the SLEEP instruction.
See Table 17 for a summary. If an enabled interrupt occurs while the MCU is in a sleep
mode, the MCU wakes up. The MCU is then halted for four cycles in addition to the
start-up time, it executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the Register File and SRAM are unaltered when
the device wakes up from sleep. If a reset occurs during sleep mode, the MCU wakes
up and executes from the Reset Vector.
Figure 18 on page 35 presents the different clock systems in the ATmega64, and their
distribution. This figure is helpful in selecting an appropriate sleep mode.
The MCU Control Register contains control bits for power management.
The SE bit must be written to logic one to make the MCU enter the sleep mode when the
SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is
the programmers purpose, it is recommended to write the Sleep Enable (SE) bit to one
just before the execution of the SLEEP instruction and to clear it immediately after waking up.
These bits select between the six available sleep modes as shown in Table 17.
Table 17. Sleep Mode Select
SM2SM1SM0Sleep Mode
000Idle
001ADC Noise Reduction
010Power-down
011Power-save
100Reserved
101Reserved
110Standby
111Extended Standby
Note:1. Standby mode and Extended Standby mode are only available with external crystals
or resonators.
(1)
(1)
2490I–AVR–11/04
45
Idle ModeWhen the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter
Idle mode, stopping the CPU but allowing SPI, USART, Analog Comparator, ADC, Twowire Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continue
operating. This sleep mode basically halts clk
clocks to run.
Idle mode enables the MCU to wake up from external triggered interrupts as well as
internal ones like the Timer Overflow and USART Transmit Complete interrupts. If
wake-up from the Analog Comparator interrupt is not required, the Analog Comparator
can be powered down by setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will reduce power consumption in Idle mode. If the ADC is
enabled, a conversion starts automatically when this mode is entered.
CPU
and clk
, while allowing the other
FLASH
ADC Noise Reduction
Mode
When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter
ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, the Two-wire Serial Interface address watch, Timer/Counter0 and the Watchdog
to continue operating (if enabled). This sleep mode basically halts clk
clk-
This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is enabled, a conversion starts automatically when this mode is
entered. Apart form the ADC Conversion Complete interrupt, only an External Reset, a
Watchdog Reset, a Brown-out Reset, a Two-wire Serial Interface address match interrupt, a Timer/Counter0 interrupt, an SPM/EEPROM ready interrupt, an external level
interrupt on INT7:4, or an External Interrupt on INT3:0 can wake up the MCU from ADC
Noise Reduction mode.
, while allowing the other clocks to run.
FLASH
I/O
, clk
CPU
, and
Power-down ModeWhen the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter
Power-down mode. In this mode, the external Oscillator is stopped, while the external
interrupts, the Two-wire Serial Interface address watch, and the Watchdog continue
operating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-out Reset, a
Two-wire Serial Interface address match interrupt, an external level interrupt on INT7:4,
or an External Interrupt on INT3:0 can wake up the MCU. This sleep mode basically
halts all generated clocks, allowing operation of asynchronous modules only.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the
changed level must be held for some time to wake up the MCU. Refer to “External Interrupts” on page 89 for details.
When waking up from Power-down mode, there is a delay from the wake-up condition
occurs until the wake-up becomes effective. This allows the clock to restart and become
stable after having been stopped. The wake-up period is defined by the same CKSEL
Fuses that define the Reset Time-out period, as described in “Clock Sources” on page
36.
Power-save ModeWhen the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter
Power-save mode. This mode is identical to Power-down, with one exception:
If Timer/Counter0 is clocked asynchronously (i.e., the AS0 bit in ASSR is set),
Timer/Counter0 will run during sleep. The device can wake up from either Timer Overflow or Output Compare event from Timer/Counter0 if the corresponding
Timer/Counter0 interrupt enable bits are set in TIMSK, and the Global Interrupt Enable
bit in SREG is set.
If the asynchronous timer is NOT clocked asynchronously, Power-down mode is recommended instead of Power-save mode because the contents of the registers in the
46
ATmega64(L)
2490I–AVR–11/04
ATmega64(L)
asynchronous timer should be considered undefined after wake-up in Power-save mode
if AS0 is 0.
This sleep mode basically halts all clocks except clk
, allowing operation only of asyn-
ASY
chronous modules, including Timer/Counter0 if clocked asynchronously.
Standby ModeWhen the SM2..0 bits are 110 and an external crystal/resonator clock option is selected,
the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to
Power-down with the exception that the Oscillator is kept running. From Standby mode,
the device wakes up in six clock cycles.
Extended Standby ModeWhen the SM2..0 bits are 111 and an external crystal/resonator clock option is selected,
the SLEEP instruction makes the MCU enter Extended Standby mode. This mode is
identical to Power-save mode with the exception that the Oscillator is kept running.
From Extended Standby mode, the device wakes up in six clock cycles.
Table 18. Active Clock Domains and Wake Up Sources in the Different Sleep Modes
Active Clock DomainsOscillatorsWake Up Sources
Main
Sleep
Modeclk
CPU
clk
FLASH
clkIOclk
ADC
clk
ASY
Clock
Source
Enabled
Timer
Enabled
IdleXXXXX
ADC
Noise
XX X X
Reduction
Osc
(2)
(2)
I
N
T
7:0
TWI
Address
MatchTimer0
SPM/
EEPROM
Ready
A
DCOther
I/O
XX X XXX
(3)
X
XX XX
Powerdown
Powersave
Standby
Extended
Standby
(1)
(1)
(2)
X
XX
(2)
X
XX
Notes: 1. External Crystal or resonator selected as clock source.
2. If AS
0 bit in ASSR is set.
3. Only INT3:0 or level interrupt INT7:4.
(3)
X
(2)
X
(2)
(3)
X
(3)
(3)
X
X
XX
(2)
X
XX
(2)
2490I–AVR–11/04
47
Minimizing Power
Consumption
Analog to Digital ConverterIf enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should
Analog ComparatorWhen entering Idle mode, the Analog Comparator should be disabled if not used. When
Brown-out DetectorIf the Brown-out Detector is not needed in the application, this module should be turned
There are several issues to consider when trying to minimize the power consumption in
an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device’s
functions are operating. All functions not needed should be disabled. In particular, the
following modules may need special consideration when trying to achieve the lowest
possible power consumption.
be disabled before entering any sleep mode. When the ADC is turned off and on again,
the next conversion will be an extended conversion. Refer to “Analog to Digital Converter” on page 231 for details on ADC operation.
entering ADC Noise Reduction mode, the Analog Comparator should be disabled. In the
other sleep modes, the Analog Comparator is automatically disabled. However, if the
Analog Comparator is set up to use the internal voltage reference as input, the Analog
Comparator should be disabled in all sleep modes. Otherwise, the internal voltage reference will be enabled, independent of sleep mode. Refer to “Analog Comparator” on
page 228 for details on how to configure the Analog Comparator.
off. If the Brown-out Detector is enabled by the BODEN Fuse, it will be enabled in all
sleep modes, and hence, always consume power. In the deeper sleep modes, this will
contribute significantly to the total current consumption. Refer to “Brown-out Detector”
on page 48 for details on how to configure the Brown-out Detector.
Internal Voltage ReferenceThe internal voltage reference will be enabled when needed by the Brown-out Detector,
the Analog Comparator or the ADC. If these modules are disabled as described in the
sections above, the internal voltage reference will be disabled and it will not be consuming power. When turned on again, the user must allow the reference to start up before
the output is used. If the reference is kept on in sleep mode, the output can be used
immediately. Refer to “Internal Voltage Reference” on page 55 for details on the start-up
time.
Watchdog TimerIf the Watchdog Timer is not needed in the application, this module should be turned off.
If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence,
always consume power. In the deeper sleep modes, this will contribute significantly to
the total current consumption. Refer to “Watchdog Timer” on page 55 for details on how
to configure the Watchdog Timer.
Port PinsWhen entering a sleep mode, all port pins should be configured to use minimum power.
The most important thing is then to ensure that no pins drive resistive loads. In sleep
modes where the both the I/O clock (clk
input buffers of the device will be disabled. This ensures that no power is consumed by
the input logic when not needed. In some cases, the input logic is needed for detecting
wake-up conditions, and it will then be enabled. Refer to the section “Digital Input
Enable and Sleep Modes” on page 69 for details on which pins are enabled. If the input
buffer is enabled and the input signal is left floating or have an analog signal level close
to V
/2, the input buffer will use excessive power.
CC
) and the ADC clock (clk
I/O
) are stopped, the
ADC
48
ATmega64(L)
2490I–AVR–11/04
ATmega64(L)
JTAG Interface and
On-chip Debug System
If the On-chip debug system is enabled by the OCDEN Fuse and the chip enter Power
down or Power save sleep mode, the main clock source remains enabled. In these
sleep modes, this will contribute significantly to the total current consumption. There are
three alternative ways to avoid this:
•Disable OCDEN Fuse.
•Disable JTAGEN Fuse.
•Write one to the JTD bit in MCUCSR.
The TDO pin is left floating when the JTAG interface is enabled while the JTAG TAP
controller is not shifting data. If the hardware connected to the TDO pin does not pull up
the logic level, power consumption will increase. Note that the TDI pin for the next
device in the scan chain contains a pull-up that avoids this problem. Writing the JTD bit
in the MCUCSR register to one or leaving the JTAG fuse unprogrammed disables the
JTAG interface.
2490I–AVR–11/04
49
System Control and
Reset
Resetting the AVRDuring Reset, all I/O Registers are set to their initial values, and the program starts exe-
cution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP
– absolute jump – instruction to the Reset handling routine. If the program never
enables an interrupt source, the Interrupt Vectors are not used, and regular program
code can be placed at these locations. This is also the case if the Reset Vector is in the
Application section while the Interrupt Vectors are in the Boot section or vice versa. The
circuit diagram in Figure 22 shows the Reset logic. Table 19 defines the electrical
parameters of the Reset circuitry.
The I/O ports of the AVR are immediately Reset to their initial state when a reset source
goes active. This does not require any clock source to be running.
After all reset sources have gone inactive, a delay counter is invoked, stretching the
Internal Reset. This allows the power to reach a stable level before normal operation
starts. The Time-out period of the delay counter is defined by the user through the
CKSEL Fuses. The different selections for the delay period are presented in “Clock
Sources” on page 36.
Reset SourcesThe ATmega64 has five sources of reset:
•Power-on Reset. The MCU is reset when the supply voltage is below the Power-on
Reset threshold (V
•External Reset. The MCU is reset when a low level is present on the RESET
longer than the minimum pulse length.
•Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and
the Watchdog is enabled.
•Brown-out Reset. The MCU is reset when the supply voltage V
Brown-out Reset threshold (V
•JTAG AVR Reset. The MCU is reset as long as there is a logic one in the Reset
Register, one of the scan chains of the JTAG system. Refer to the section “IEEE
1149.1 (JTAG) Boundary-scan” on page 255 for details.
POT
).
pin for
is below the
) and the Brown-out Detector is enabled.
BOT
CC
50
ATmega64(L)
2490I–AVR–11/04
Figure 22. Reset Logic
ATmega64(L)
DATA BU S
PEN
BODEN
BODLEVEL
RESET
DQ
L
Pull-up Resistor
Power-On Reset
Circuit
Pull-up Resistor
SPIKE
FILTER
JTAG Reset
Register
MCU Control and Status
Q
Brown-Out
Reset Circuit
Reset Circuit
Watchdog
Timer
Watchdog
Oscillator
Clock
Generator
CKSEL[3:0]
SUT[1:0]
Register (MCUCSR)
BORF
PORF
EXTRF
CK
Delay Counters
JTRF
WDRF
COUNTER RESET
TIMEOUT
Table 19. Reset Characteristics
SymbolParameterConditionMinTypMaxUnits
Power-on Reset
V
V
V
V
POT
RST
t
RST
BOT
t
BOD
HYST
Threshold Voltage
(rising)
Power-on Reset
Threshold Voltage
(1)
(falling)
RESET Pin Threshold
Voltag e
Minimum pulse width on
RESET
Pin
Brown-out Reset
Threshold Voltage
(2)
Minimum low voltage
period for Brown-out
Detection
Brown-out Detector
hysteresis
0.2 V
BODLEVEL = 12.52.72.9
BODLEVEL = 03.64.04.2
BODLEVEL = 12µs
BODLEVEL = 02µs
1.42.3V
1.32.3V
CC
0.85 V
1.5µs
120mV
CC
V
V
2490I–AVR–11/04
51
Notes: 1. The Power-on Reset will not work unless the supply voltage has been below V
POT
(falling).
2. V
may be below nominal minimum operating voltage for some devices. For
BOT
devices where this is the case, the device is tested down to V
CC
= V
BOT
during the
production test. This guarantees that a Brown-out Reset will occur before VCC drops
to a voltage where correct operation of the microcontroller is no longer guaranteed.
The test is performed using BODLEVEL=1 for ATmega64L and BODLEVEL=0 for
ATmega64. BODLEVEL=1 is not applicable for ATmega64.
Power-on ResetA Power-on Reset (POR) pulse is generated by an On-chip Detection circuit. The detec-
tion level is defined in Table 19. The POR is activated whenever V
is below the
CC
detection level. The POR circuit can be used to trigger the Start-up Reset, as well as to
detect a failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset threshold voltage invokes the delay counter, which determines
how long the device is kept in RESET after V
again, without any delay, when V
External ResetAn External Reset is generated by a low level on the RESET pin. Reset pulses longer
than the minimum pulse width (see Table 19) will generate a reset, even if the clock is
not running. Shorter pulses are not guaranteed to generate a reset. When the applied
signal reaches the Reset Threshold Voltage – V
counter starts the MCU after the Time-out period t
Figure 25. External Reset during Operation
CC
on its positive edge, the delay
RST
has expired.
TOUT
Brown-out DetectionATmega64 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V
level during operation by comparing it to a fixed trigger level. The trigger level for the
BOD can be selected by the fuse BODLEVEL to be 2.7V (BODLEVEL unprogrammed),
or 4.0V (BODLEVEL programmed). The trigger level has a hysteresis to ensure spike
free Brown-out Detection. The hysteresis on the detection level should be interpreted as
V
BOT+
= V
BOT
+ V
HYST
/2 and V
BOT-
= V
BOT
- V
HYST
/2.
The BOD circuit can be enabled/disabled by the fuse BODEN. When the BOD is
enabled (BODEN programmed), and V
(V
in Figure 26), the Brown-out Reset is immediately activated. When VCC increases
BOT-
above the trigger level (V
Time-out period t
has expired.
TOUT
in Figure 26), the delay counter starts the MCU after the
BOT+
The BOD circuit will only detect a drop in V
for longer than t
given in Table 19.
BOD
decreases to a value below the trigger level
CC
if the voltage stays below the trigger level
CC
Figure 26. Borwn-out Reset During Operation
V
CC
V
BOT-
V
BOT+
RESET
CC
2490I–AVR–11/04
TIME-OUT
INTERNAL
RESET
t
TOUT
53
Watchdog ResetWhen the Watchdog times out, it will generate a short reset pulse of one CK cycle dura-
tion. On the falling edge of this pulse, the delay timer starts counting the Time-out period
t
. Refer to page 55 for details on operation of the Watchdog Timer.
TOUT
Figure 27. Watchdog Reset During Operation
CC
CK
MCU Control and Status
Register – MCUCSR
(1)
The MCU Control and Status Register provides information on which reset source
caused an MCU Reset.
Bit76543210
JTD––JTRFWDRFBORFEXTRFPORFMCUCSR
Read/WriteR/WRRR/WR/WR/WR/WR/W
Initial Value000See Bit Description
Note:1. Only EXTRF and PORF are available in mega103 compatibility mode.
• Bit 4 – JTRF: JTAG Reset Flag
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register
selected by the JTAG instruction AVR_RESET. This bit is reset by a Brown-out Reset,
or by writing a logic zero to the flag.
• Bit 3 – WDRF: Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by
writing a logic zero to the flag.
• Bit 2 – BORF: Brown-out Reset Flag
This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by
writing a logic zero to the flag.
• Bit 1 – EXTRF: External Reset Flag
54
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by
writing a logic zero to the flag.
ATmega64(L)
2490I–AVR–11/04
ATmega64(L)
• Bit 0 – PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to
the flag.
To make use of the reset flags to identify a reset condition, the user should read and
then reset the MCUCSR as early as possible in the program. If the register is cleared
before another reset occurs, the source of the reset can be found by examining the
Reset Flags.
Internal Voltage
Reference
Voltage Reference Enable
Signals and Start-up Time
ATmega64 features an internal bandgap reference. This reference is used for Brownout Detection, and it can be used as an input to the Analog Comparator or the ADC. The
2.56V reference to the ADC is generated from the internal bandgap reference.
The voltage reference has a start-up time that may influence the way it should be used.
The start-up time is given in Table 20. To save power, the reference is not always turned
on. The reference is on during the following situations:
1. When the BOD is enabled (by programming the BODEN Fuse).
2. When the bandgap reference is connected to the Analog Comparator (by setting
the ACBG bit in ACSR).
3. When the ADC is enabled.
Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the
user must always allow the reference to start up before the output from the Analog Comparator or ADC is used. To reduce power consumption in Power-down mode, the user
can avoid the three conditions above to ensure that the reference is turned off before
entering Power-down mode.
Table 20. Internal Voltage Reference Characteristics
SymbolParameterMinTypMaxUnits
V
BG
t
BG
I
BG
Bandgap reference voltage1.151.231.35V
Bandgap reference start-up time4070µs
Bandgap reference current consumption10µA
Watchdog TimerThe Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 Mhz.
2490I–AVR–11/04
This is the typical value at V
V
levels. By controlling the Watchdog Timer prescaler, the Watchdog Reset interval
CC
can be adjusted as shown in Table 22 on page 57. The WDR – Watchdog Reset –
instruction resets the Watchdog Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Eight different clock cycle periods can be selected
to determine the reset period. If the reset period expires without another Watchdog
Reset, the ATmega64 resets and executes from the Reset Vector. For timing details on
the Watchdog Reset, refer to page 54.
To prevent unintentional disabling of the Watchdog or unintentional change of Time-out
period, three different safety levels are selected by the fuses M103C and WDTON as
shown in Table 21. Safety level 0 corresponds to the setting in ATmega103. There is no
restriction on enabling the WDT in any of the safety levels. Refer to “Timed Sequences
for Changing the Configuration of the Watchdog Timer” on page 59 for details.
= 5V. See characterization data for typical values at other
CC
55
Table 21. WDT Configuration as a Function of the Fuse Settings of M103C and
These bits are reserved bits in the ATmega64 and will always read as zero.
• Bit 4 – WDCE: Watchdog Change Enable
This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog
will not be disabled. Once written to one, hardware will clear this bit after four clock
cycles. Refer to the description of the WDE bit for a Watchdog disable procedure. In
Safety Level 1 and 2, this bit must also be set when changing the prescaler bits. See
“Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 59.
2490I–AVR–11/04
ATmega64(L)
• Bit 3 – WDE: Watchdog Enable
When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is
written to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared
if the WDCE bit has logic level one. To disable an enabled Watchdog Timer, the following procedure must be followed:
1. In the same operation, write a logic one to WDCE and WDE. A logic one must be
written to WDE even though it is set to one before the disable operation starts.
2. Within the next four clock cycles, write a logic 0 to WDE. This disables the
Watchdog.
In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm described above. See “Timed Sequences for Changing the Configuration of the
Watchdog Timer” on page 59.
The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the
Watchdog Timer is enabled. The different prescaling values and their corresponding
Timeout Periods are shown in Table 22.
Table 22. Watchdog Timer Prescale Select
Number of WDT
WDP2WDP1WDP0
00016K (16,384)17.1 ms16.3 ms
00132K (32,768)34.3 ms32.5 ms
01064K (65,536)68.5 ms65 ms
011128K (131,072)0.14 s0.13 s
100256K (262,144)0.27 s0.26 s
101512K (524,288)0.55 s0.52 s
1101,024K (1,048,576)1.1 s1.0 s
1112,048K (2,097,152)2.2 s2.1 s
Oscillator Cycles
Typical Time-out
at VCC = 3.0V
Typical Time-out
at VCC = 5.0V
2490I–AVR–11/04
57
The following code examples show one assembly and one C function for turning off the
WDT. The examples assume that interrupts are controlled (e.g., by disabling interrupts
globally) so that no interrupts will occur during execution of these functions.
Assembly Code Example
WDT_off:
; reset WDT
wdr
in r16, WDTCR
ldi r16, (1<<WDCE)|(1<<WDE)
; Write logical one to WDCE and WDE
ori r16, (1<<WDCE)|(1<<WDE)
out WDTCR, r16
; Turn off WDT
ldi r16, (0<<WDE)
out WDTCR, r16
ret
C Code Example
void WDT_off(void)
{
/* Reset WDT*/
_WDRC();
/* Write logical one to WDCE and WDE */
WDTCR |= (1<<WDCE) | (1<<WDE);
/* Turn off WDT */
WDTCR = 0x00;
}
58
ATmega64(L)
2490I–AVR–11/04
ATmega64(L)
Timed Sequences for
Changing the
The sequence for changing configuration differs slightly between the three safety levels.
Separate procedures are described for each level.
Configuration of the
Watchdog Timer
Safety Level 0This mode is compatible with the Watchdog operation found in ATmega103. The Watch-
dog Timer is initially disabled, but can be enabled by writing the WDE bit to 1 without
any restriction. The Time-out period can be changed at any time without restriction. To
disable an enabled Watchdog Timer, the procedure described on page 57 (WDE bit
description) must be followed.
Safety Level 1In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the
WDE bit to 1 without any restriction. A timed sequence is needed when changing the
Watchdog Time-out period or disabling an enabled Watchdog Timer. To disable an
enabled Watchdog Timer, and/or changing the Watchdog Time-out, the following procedure must be followed:
1. In the same operation, write a logic one to WDCE and WDE. A logic one must be
written to WDE regardless of the previous value of the WDE bit.
2. Within the next four clock cycles, in the same operation, write the WDE and WDP
bits as desired, but with the WDCE bit cleared.
Safety Level 2In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read
as one. A timed sequence is needed when changing the Watchdog Time-out period. To
change the Watchdog Time-out, the following procedure must be followed:
1. In the same operation, write a logical one to WDCE and WDE. Even though the
WDE always is set, the WDE must be written to one to start the timed sequence.
2. Within the next four clock cycles, in the same operation, write the WDP bits as
desired, but with the WDCE bit cleared. The value written to the WDE bit is
irrelevant.
2490I–AVR–11/04
59
InterruptsThis section describes the specifics of the interrupt handling as performed in
ATmega64. For a general explanation of the AVR interrupt handling, refer to “Reset and
Interrupt Handling” on page 13.
Interrupt Vectors in
ATmega64
Table 23. Reset and Interrupt Vectors
Vector
No.
10x0000
20x0002INT0External Interrupt Request 0
30x0004INT1External Interrupt Request 1
40x0006INT2External Interrupt Request 2
50x0008INT3External Interrupt Request 3
60x000AINT4External Interrupt Request 4
70x000CINT5External Interrupt Request 5
80x000EINT6External Interrupt Request 6
90x0010INT7External Interrupt Request 7
100x0012TIMER2 COMPTimer/Counter2 Compare Match
110x0014TIMER2 OVFTimer/Counter2 Overflow
120x0016TIMER1 CAPTTimer/Counter1 Capture Event
130x0018TIMER1 COMPATimer/Counter1 Compare Match A
140x001ATIMER1 COMPBTimer/Counter1 Compare Match B
Notes: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader
address at reset, see “Boot Loader Support – Read-While-Write Self-programming”
on page 278.
2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of
the Boot Flash section. The address of each Interrupt Vector will then be address in
this table added to the start address of the Boot Flash section.
3. The Interrupts on address 0x0030 - 0x0044 do not exist in ATmega103 compatibility
mode.
Table 24 shows Reset and Interrupt Vectors placement for the various combinations of
BOOTRST and IVSEL settings. If the program never enables an interrupt source, the
Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the
Interrupt Vectors are in the Boot section or vice versa.
Note:1. The Boot Reset Address is shown in Table 112 on page 290. For the BOOTRST
Fuse “1” means unprogrammed while “0” means programmed.
The most typical and general program setup for the Reset and Interrupt Vector
Addresses in ATmega64 is:
Address Labels CodeComments
0x0000jmpRESET; Reset Handler
0x0002jmpEXT_INT0; IRQ0 Handler
0x0004jmpEXT_INT1; IRQ1 Handler
0x0006jmpEXT_INT2; IRQ2 Handler
0x0008jmpEXT_INT3; IRQ3 Handler
0x000AjmpEXT_INT4; IRQ4 Handler
0x000CjmpEXT_INT5; IRQ5 Handler
0x000EjmpEXT_INT6; IRQ6 Handler
0x0010jmpEXT_INT7; IRQ7 Handler
0x0012jmpTIM2_COMP; Timer2 Compare Handler
0x0014jmpTIM2_OVF; Timer2 Overflow Handler
0x0016jmpTIM1_CAPT; Timer1 Capture Handler
0x0018jmpTIM1_COMPA; Timer1 CompareA Handler
0x001AjmpTIM1_COMPB; Timer1 CompareB Handler
0x001CjmpTIM1_OVF; Timer1 Overflow Handler
2490I–AVR–11/04
61
0x001EjmpTIM0_COMP; Timer0 Compare Handler
0x0020jmpTIM0_OVF; Timer0 Overflow Handler
0x0022jmpSPI_STC; SPI Transfer Complete Handler
0x0024jmpUSART0_RXC; USART0 RX Complete Handler
0x0026jmpUSART0_DRE; USART0,UDR Empty Handler
0x0028jmpUSART0_TXC; USART0 TX Complete Handler
0x002AjmpADC; ADC Conversion Complete Handler
0x002CjmpEE_RDY; EEPROM Ready Handler
0x002EjmpANA_COMP; Analog Comparator Handler
0x0030jmpTIM1_COMPC; Timer1 CompareC Handler
0x0032jmpTIM3_CAPT; Timer3 Capture Handler
0x0034jmpTIM3_COMPA; Timer3 CompareA Handler
0x0036jmpTIM3_COMPB; Timer3 CompareB Handler
0x0038jmpTIM3_COMPC; Timer3 CompareC Handler
0x003AjmpTIM3_OVF; Timer3 Overflow Handler
0x003CjmpUSART1_RXC; USART1 RX Complete Handler
0x003EjmpUSART1_DRE; USART1,UDR Empty Handler
0x0040jmpUSART1_TXC; USART1 TX Complete Handler
0x0042jmpTWI; Two-wire Serial Interface Handler
0x0044jmpSPM_RDY; SPM Ready Handler
;
0x0046 RESET: ldir16, high(RAMEND); Main program start
0x0047out SPH,r16; Set Stack Pointer to top of RAM
0x0048ldi r16, low(RAMEND)
0x0049out SPL,r16
0x004Asei; Enable interrupts
0x004B<instr> xxx
... ... ... ...
When the BOOTRST Fuse is unprogrammed, the Boot section size set to 8K bytes and
the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most
typical and general program setup for the Reset and Interrupt Vector Addresses is:
Address Labels CodeComments
0x0000 RESET: ldir16,high(RAMEND); Main program start
0x0001outSPH,r16; Set Stack Pointer to top of RAM
0x0002ldir16,low(RAMEND)
0x0003outSPL,r16
0x0004sei; Enable interrupts
0x0005<instr> xxx
;
.org 0x7002
0x7002jmpEXT_INT0; IRQ0 Handler
0x7004jmpEXT_INT1; IRQ1 Handler
.........;
0x7044jmpSPM_RDY; Store Program Memory Ready Handler
62
ATmega64(L)
2490I–AVR–11/04
ATmega64(L)
When the BOOTRST Fuse is programmed and the Boot section size set to 8K bytes, the
most typical and general program setup for the Reset and Interrupt Vector Addresses is:
Address Labels CodeComments
.org 0x0002
0x0002jmpEXT_INT0 ; IRQ0 Handler
0x0004jmpEXT_INT1 ; IRQ1 Handler
.........;
0x0044jmpSPM_RDY; Store Program Memory Ready Handler
;
.org 0x7000
0x7000 RESET: ldir16,high(RAMEND); Main program start
0x7001outSPH,r16; Set Stack Pointer to top of RAM
0x7002ldir16,low(RAMEND)
0x7003outSPL,r16
0x7004sei; Enable interrupts
0x7005<instr> xxx
When the BOOTRST Fuse is programmed, the Boot section size set to 8K bytes and the
IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is:
When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the
Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of the Flash. The actual address of the start of the Boot
Flash section is determined by the BOOTSZ Fuses. Refer to the section “Boot Loader
Support – Read-While-Write Self-programming” on page 278 for details. To avoid unintentional changes of Interrupt Vector tables, a special write procedure must be followed
to change the IVSEL bit:
63
1. Write the Interrupt Vector Change Enable (IVCE) bit to one.
2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
Interrupts will automatically be disabled while this sequence is executed. Interrupts are
disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four
cycles. The I-bit in the Status Register is unaffected by the automatic disabling.
Note:If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is pro-
grammed, interrupts are disabled while executing from the Application section. If
Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to
the section “Boot Loader Support – Read-While-Write Self-programming” on page 278
for details on Boot Lock bits.
• Bit 0 – IVCE: Interrupt Vector Change Enable
The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is
cleared by hardware four cycles after it is written or when IVSEL is written. Setting the
IVCE bit will disable interrupts, as explained in the IVSEL description above. See code
examples below.
Assembly Code Example
Move_interrupts:
; Enable change of Interrupt Vectors
ldi r16, (1<<IVCE)
out MCUCR, r16
; Move interrupts to boot Flash section
ldi r16, (1<<IVSEL)
out MCUCR, r16
ret
C Code Example
void Move_interrupts(void)
{
/* Enable change of Interrupt Vectors */
MCUCR = (1<<IVCE);
/* Move interrupts to boot Flash section */
MCUCR = (1<<IVSEL);
}
64
ATmega64(L)
2490I–AVR–11/04
ATmega64(L)
I/O Ports
IntroductionAll AVR ports have true Read-Modify-Write functionality when used as general digital
I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The
same applies when changing drive value (if configured as output) or enabling/disabling
of pull-up resistors (if configured as input). Each output buffer has symmetrical drive
characteristics with both high sink and source capability. The pin driver is strong enough
to drive LED displays directly. All port pins have individually selectable pull-up resistors
with a supply voltage invariant resistance. All I/O pins have protection diodes to both
V
and Ground as indicated in Figure 29. Refer to “Electrical Characteristics” on page
CC
327 for a complete list of parameters.
Figure 29. I/O Pin Equivalent Schematic
R
pu
Pxn
C
pin
All registers and bit references in this section are written in general form. A lower case
“x” represents the numbering letter for the port, and a lower case “n” represents the bit
number. However, when using the register or bit defines in a program, the precise form
must be used (i.e., PORTB3 for bit no. 3 in Port B, here documented generally as
PORTxn). The physical I/O Registers and bit locations are listed in “Register Description
for I/O Ports” on page 86.
Three I/O memory address locations are allocated for each port, one each for the Data
Register – PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The
Port Input Pins I/O location is read only, while the Data Register and the Data Direction
Register are read/write. In addition, the Pull-up Disable – PUD bit in SFIOR disables the
pull-up function for all pins in all ports when set.
Using the I/O port as general digital I/O is described in “Ports as General Digital I/O” on
page 66. Most port pins are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes with the port pin is described
in “Alternate Port Functions” on page 70. Refer to the individual module sections for a
full description of the alternate functions.
See Figure
"General Digital I/O" for
Logic
Details
2490I–AVR–11/04
Note that enabling the alternate function of some of the port pins does not affect the use
of the other pins in the port as general digital I/O.
65
Ports as General Digital
I/O
The ports are bi-directional I/O ports with optional internal pull-ups. Figure 30 shows a
functional description of one I/O-port pin, here generically called Pxn.
Figure 30. General Digital I/O
Pxn
(1)
SLEEP
SYNCHRONIZER
DLQ
D
PINxn
Q
PUD
Q
D
DDxn
Q
CLR
RESET
Q
D
PORTxn
Q
CLR
RESET
Q
Q
WDx
RDx
WPx
RRx
RPx
clk
DATA B U S
I/O
PUD:PULLUP DISABLE
SLEEP:SLEEP CONTROL
clk
:I/O CLOCK
I/O
Note:1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk
Configuring the PinEach port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in
“Register Description for I/O Ports” on page 86, the DDxn bits are accessed at the DDRx
I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx
I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written
logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up
resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic
zero or the pin has to be configured as an output pin. The port pins are tri-stated when a
reset condition becomes active, even if no clocks are running.
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is
driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero).
,
66
ATmega64(L)
2490I–AVR–11/04
ATmega64(L)
When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn,
PORTxn} = 0b11), an intermediate state with either pull-up enabled ({DDxn, PORTxn} =
0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up
enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in
the SFIOR Register can be written to one to disable all pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The
user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state
({DDxn, PORTxn} = 0b11) as an intermediate step.
Table 25 summarizes the control signals for the pin value.
Table 25. Port Pin Configurations
PUD
DDxnPORTxn
00XInputNoTri-state (Hi-Z)
010InputYesPxn will source current if ext. pulled
011InputNoTri-state (Hi-Z)
(in SFIOR)I/OPull-upComment
low.
10XOutputNoOutput Low (Sink)
11XOutputNoOutput High (Source)
Reading the Pin ValueIndependent of the setting of Data Direction bit DDxn, the port pin can be read through
the PINxn Register bit. As shown in Figure 30, the PINxn Register bit and the preceding
latch constitute a synchronizer. This is needed to avoid metastability if the physical pin
changes value near the edge of the internal clock, but it also introduces a delay. Figure
31 shows a timing diagram of the synchronization when reading an externally applied
pin value. The maximum and minimum propagation delays are denoted t
pd,max
and t
pd,min
respectively.
Figure 31. Synchronization when Reading an Externally Applied Pin Value
SYSTEM CLK
INSTRUCTIONS
SYNC LATCH
PINxn
r17
0x00
t
pd, max
XXXXXX
in r17, PINx
0xFF
2490I–AVR–11/04
t
pd, min
67
Consider the clock period starting shortly after the first falling edge of the system clock.
The latch is closed when the clock is low, and goes transparent when the clock is high,
as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is
latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indicated by the two arrows t
pd,max
and t
pd,min
, a single
signal transition on the pin will be delayed between ½ and 1-½ system clock period
depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as
indicated in Figure 32. The out instruction sets the “SYNC LATCH” signal at the positive
edge of the clock. In this case, the delay t
through the synchronizer is one system
pd
clock period.
Figure 32. Synchronization when Reading a Software Assigned Pin Value
SYSTEM CLK
r16
INSTRUCTIONS
SYNC LATCH
PINxn
r17
out PORTx, r16
0xFF
nopin r17, PINx
0x00
t
pd
0xFF
68
ATmega64(L)
2490I–AVR–11/04
ATmega64(L)
The following code example show how to set Port B pins 0 and 1 high, 2 and 3 low, and
define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The
resulting pin values are read back again, but as previously discussed, a nop instruction
is included to be able to read back the value recently assigned to some of the pins.
Assembly Code Example
...
; Define pull-ups and set outputs high
; Define directions for port pins
ldir16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0)
ldir17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)
outPORTB,r16
outDDRB,r17
; Insert nop for synchronization
nop
; Read port pins
inr16,PINB
...
(1)
C Code Example
unsigned char i;
...
/* Define pull-ups and set outputs high */
/* Define directions for port pins */
PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0);
DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);
/* Insert nop for synchronization*/
_NOP();
/* Read port pins */
i = PINB;
...
Digital Input Enable and Sleep
Modes
2490I–AVR–11/04
Note:1. For the assembly program, two temporary registers are used to minimize the time
from pull-ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set,
defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers.
As shown in Figure 30, the digital input signal can be clamped to ground at the input of
the Schmitt Trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep
Controller in Power-down mode, Power-save mode, Standby mode, and Extended
Standby mode to avoid high power consumption if some input signals are left floating, or
have an analog signal level close to V
CC
/2.
SLEEP is overridden for port pins enabled as External Interrupt pins. If the External
Interrupt request is not enabled, SLEEP is active also for these pins. SLEEP is also
overridden by various other alternate functions as described in “Alternate Port Functions” on page 70.
If a logic high level (“one”) is present on an asynchronous External Interrupt pin configured as “Interrupt on Any Logic Change on Pin” while the External Interrupt is not
enabled, the corresponding External Interrupt Flag will be set when resuming from the
above mentioned sleep modes, as the clamping in these sleep modes produces the
requested logic change.
69
Unconnected PinsIf some pins are unused, it is recommended to ensure that these pins have a defined
level. Even though most of the digital inputs are disabled in the deep sleep modes as
described above, floating inputs should be avoided to reduce current consumption in all
other modes where the digital inputs are enabled (Reset, Active mode and Idle mode).
The simplest method to ensure a defined level of an unused pin, is to enable the internal
pull-up. In this case, the pull-up will be disabled during reset. If low power consumption
during reset is important, it is recommended to use an external pull-up or pull-down.
Connecting unused pins directly to VCC or GND is not recommended, since this may
cause excessive currents if the pin is accidentally configured as an output.
Alternate Port FunctionsMost port pins have alternate functions in addition to being general digital I/Os. Figure
33 shows how the port pin control signals from the simplified Figure 30 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but
the figure serves as a generic description applicable to all port pins in the AVR microcontroller family.
Figure 33. Alternate Port Functions
1
0
1
0
Pxn
1
0
1
0
(1)
PUOExn
PUOVxn
DDOExn
DDOVxn
PVOExn
PVOVxn
DIEOExn
DIEOVxn
SLEEP
SYNCHRONIZER
SET
DLQ
Q
CLR
D
PINxn
PUD
Q
D
DDxn
Q
CLR
RESET
Q
PORTxn
Q
CLR
RESET
Q
Q
CLR
WDx
RDx
D
WPx
RRx
RPx
clk
DIxn
AIOxn
DATA BU S
I/O
70
ATmega64(L)
PUOExn: Pxn PULL-UP OVERRIDE ENABLE
PUOVxn: Pxn PULL-UP OVERRIDE VALUE
DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE
DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE
PVOExn: Pxn PORT VALUE OVERRIDE ENABLE
PVOVxn: Pxn PORT VALUE OVERRIDE VALUE
DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE
DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE
SLEEP: SLEEP CONTROL
Note:1. WPx, WDx, RLx, RPx, and RDx are common to all pins within the same port. clk
DIxn: DIGITAL INPUT PIN n ON PORTx
AIOxn: ANALOG INPUT/OUTPUT PIN n ON PORTx
I/O
SLEEP, and PUD are common to all ports. All other signals are unique for each pin.
Table 26 summarizes the function of the overriding signals. The pin and port indexes
from Figure 33 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function.
2490I–AVR–11/04
,
ATmega64(L)
Table 26. Generic Description of Overriding Signals for Alternate Functions
Signal
NameFull NameDescription
PUOEPull-up Override
Enable
PUOVPull-up Override
Valu e
DDOEData Direction
Override Enable
DDOVData Direction
Override Value
PVOEPort Value Override
Enable
PVOVPort Value Override
Valu e
DIEOEDigital Input Enable
Override Enable
DIEOVDigital Input Enable
Override Value
DIDigital InputThis is the Digital Input to alternate functions. In the figure,
AIOAnalog Input/outputThis is the Analog Input/output to/from alternate functions.
If this signal is set, the pull-up enable is controlled by the
PUOV signal. If this signal is cleared, the pull-up is enabled
when {DDxn, PORTxn, PUD} = 0b010.
If PUOE is set, the pull-up is enabled/disabled when PUOV
is set/cleared, regardless of the setting of the DDxn,
PORTxn, and PUD Register bits.
If this signal is set, the Output Driver Enable is controlled by
the DDOV signal. If this signal is cleared, the Output driver is
enabled by the DDxn Register bit.
If DDOE is set, the Output Driver is enabled/disabled when
DDOV is set/cleared, regardless of the setting of the DDxn
Register bit.
If this signal is set and the Output Driver is enabled, the port
value is controlled by the PVOV signal. If PVOE is cleared,
and the Output Driver is enabled, the port Value is controlled
by the PORTxn Register bit.
If PVOE is set, the port value is set to PVOV, regardless of
the setting of the PORTxn Register bit.
If this bit is set, the Digital Input Enable is controlled by the
DIEOV signal. If this signal is cleared, the Digital Input
Enable is determined by MCU state (Normal mode, sleep
modes).
If DIEOE is set, the Digital Input is enabled/disabled when
DIEOV is set/cleared, regardless of the MCU state (Normal
mode, sleep modes).
the signal is connected to the output of the Schmitt Trigger
but before the synchronizer. Unless the Digital Input is used
as a clock source, the module with the alternate function will
use its own synchronizer.
The signal is connected directly to the pad, and can be used
bi-directionally.
Special Function IO Register –
SFIOR
2490I–AVR–11/04
The following subsections shortly describe the alternate functions for each port, and
relate the overriding signals to the alternate function. Refer to the alternate function
description for further details.
When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn
and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01).
See “Configuring the Pin” on page 66 for more details about this feature.
71
Alternate Functions of Port AThe Port A has an alternate function as the address low byte and data lines for the
External Memory Interface.
Table 27. Port A Pins Alternate Functions
Port PinAlternate Function
PA7AD7 (External memory interface address and data bit 7)
PA6AD6 (External memory interface address and data bit 6)
PA5AD5 (External memory interface address and data bit 5)
PA4AD4 (External memory interface address and data bit 4)
PA3AD3 (External memory interface address and data bit 3)
PA2AD2 (External memory interface address and data bit 2)
PA1AD1 (External memory interface address and data bit 1)
PA0AD0 (External memory interface address and data bit 0)
Table 28 and Table 29 relates the alternate functions of Port A to the overriding signals
shown in Figure 33 on page 70.
Table 28. Overriding Signals for Alternate Functions in PA7..PA4
Signal
NamePA7/AD7PA6/AD6PA5/AD5PA4/AD4
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
SRESRESRESRE
~(WR | ADA
PORTA7 • PUD
WR | ADAWR | ADAWR | ADAWR | ADA
A7 • ADA | D7
OUTPUT • WR
D7 INPUTD6 INPUTD5 INPUTD4 INPUT
(1)
) •
SRESRESRESRE
SRESRESRESRE
0000
0000
––––
~(WR | ADA) •
PORTA6 • PUD
A6 • ADA | D6
OUTPUT • WR
~(WR | ADA) •
PORTA5 • PUD
A5 • ADA | D5
OUTPUT • WR
~(WR | ADA) •
PORTA4 • PUD
A4 • ADA | D4
OUTPUT • WR
72
ATmega64(L)
2490I–AVR–11/04
ATmega64(L)
Table 29. Overriding Signals for Alternate Functions in PA3..PA0
Signal
NamePA3/AD3PA2/AD2PA1/AD1PA0/AD0
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
SRESRESRESRE
~(WR | ADA) •
PORTA3 • PUD
SRESRESRESRE
WR | ADAWR | ADAWR | ADAWR | ADA
SRESRESRESRE
A3 • ADA | D3
OUTPUT • WR
0000
0000
D3 INPUTD2 INPUTD1 INPUTD0 INPUT
––––
~(WR | ADA) •
PORTA2 • PUD
A2• ADA | D2
OUTPUT • WR
~(WR | ADA) •
PORTA1 • PUD
A1 • ADA | D1
OUTPUT • WR
Note:1. ADA is short for ADdress Active and represents the time when address is output. See
“External Memory Interface” on page 25 for details.
Alternate Functions of Port BThe Port B pins with alternate functions are shown in Table 30.
(1)
~(WR | ADA) •
PORTA0 • PUD
A0 • ADA | D0
OUTPUT • WR
Table 30. Port B Pins Alternate Functions
Port PinAlternate Functions
(1)
PB7OC2/OC1C
(Output Compare and PWM Output for Timer/Counter2 or Output
Compare and PWM Output C for Timer/Counter1)
PB6OC1B (Output Compare and PWM Output B for Timer/Counter1)
PB5OC1A (Output Compare and PWM Output A for Timer/Counter1)
PB4OC0 (Output Compare and PWM Output for Timer/Counter0)
PB3MISO (SPI Bus Master Input/Slave Output)
PB2MOSI (SPI Bus Master Output/Slave Input)
PB1SCK (SPI Bus Serial Clock)
PB0SS
(SPI Slave Select input)
Note:1. OC1C not applicable in ATmega103 compatibility mode.
The alternate pin configuration is as follows:
• OC2/OC1C, Bit 7
OC2, Output Compare Match output: The PB7 pin can serve as an external output for
the Timer/Counter2 Output Compare. The pin has to be configured as an output (DDB7
set (one)) to serve this function. The OC2 pin is also the output pin for the PWM mode
timer function.
2490I–AVR–11/04
OC1C, Output Compare Match C output: The PB7 pin can serve as an external output
for the Timer/Counter1 Output Compare C. The pin has to be configured as an output
(DDB7 set (one)) to serve this function. The OC1C pin is also the output pin for the
PWM mode timer function.
73
• OC1B, Bit 6
OC1B, Output Compare Match B output: The PB6 pin can serve as an external output
for the Timer/Counter1 Output Compare B. The pin has to be configured as an output
(DDB6 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM
mode timer function.
• OC1A, Bit 5
OC1A, Output Compare Match A output: The PB5 pin can serve as an external output
for the Timer/Counter1 Output Compare A. The pin has to be configured as an output
(DDB5 set (one)) to serve this function. The OC1A pin is also the output pin for the PWM
mode timer function.
• OC0, Bit 4
OC0, Output Compare Match output: The PB4 pin can serve as an external output for
the Timer/Counter0 Output Compare. The pin has to be configured as an output (DDB4
set (one)) to serve this function. The OC0 pin is also the output pin for the PWM mode
timer function.
• MISO – Port B, Bit 3
MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is
enabled as a Master, this pin is configured as an input regardless of the setting of
DDB3. When the SPI is enabled as a Slave, the data direction of this pin is controlled by
DDB3. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB3 bit.
• MOSI – Port B, Bit 2
MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is
enabled as a Slave, this pin is configured as an input regardless of the setting of DDB2.
When the SPI is enabled as a Master, the data direction of this pin is controlled by
DDB2. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB2 bit.
• SCK – Port B, Bit 1
SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is
enabled as a Slave, this pin is configured as an input regardless of the setting of DDB1.
When the SPI is enabled as a Master, the data direction of this pin is controlled by
DDB1. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB1 bit.
•SS
– Port B, Bit 0
SS
: Slave Port Select input. When the SPI is enabled as a Slave, this pin is configured
as an input regardless of the setting of DDB0. As a Slave, the SPI is activated when this
pin is driven low. When the SPI is enabled as a Master, the data direction of this pin is
controlled by DDB0. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 bit.
Table 31 and Table 32 relate the alternate functions of Port B to the overriding signals
shown in Figure 33 on page 70. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute
the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE
INPUT.
74
ATmega64(L)
2490I–AVR–11/04
ATmega64(L)
Table 31. Overriding Signals for Alternate Functions in PB7..PB4
Signal
NamePB7/OC2/OC1CPB6/OC1BPB5/OC1APB4/OC0
PUOE0000
PUOV0000
DDOE0000
DDOV0000
(1)
PVOEOC2/OC1C ENABLE
PVOVOC2/OC1C
DIEOE0000
DIEOV0000
DI––––
AIO––––
Note:1. See “Output Compare Modulator (OCM1C2)” on page 160 for details. OC1C does
not exist in ATmega103 compatibility mode.
(1)
OC1B ENABLEOC1A ENABLEOC0 ENABLE
OC1BOC1AOC0B
Table 32. Overriding Signals for Alternate Functions in PB3..PB0
Alternate Functions of Port DThe Port D pins with alternate functions are shown in Table 36.
Table 36. Port D Pins Alternate Functions
Port PinAlternate Function
(1)
PD7T2 (Timer/Counter2 Clock Input)
PD6T1 (Timer/Counter1 Clock Input)
(1)
PD5XCK1
PD4ICP1 (Timer/Counter1 Input Capture Pin)
PD3INT3/TXD1
PD2INT2/RXD1
PD1INT1/SDA
PD0INT0/SCL
Note:1. XCK1, TXD1, RXD1, SDA, and SCL not applicable in ATmega103 compatibility
mode.
(USART1 External Clock Input/Output)
(1)
(External Interrupt3 Input or UART1 Transmit Pin)
(1)
(External Interrupt2 Input or UART1 Receive Pin)
(1)
(External Interrupt1 Input or TWI Serial DAta)
(1)
(External Interrupt0 Input or TWI Serial CLock)
The alternate pin configuration is as follows:
• T2 – Port D, Bit 7
T2, Timer/Counter2 Counter Source.
• T1 – Port D, Bit 6
T1, Timer/Counter1 Counter Source.
• XCK1 – Port D, Bit 5
2490I–AVR–11/04
XCK1, USART1 External Clock. The Data Direction Register (DDD5) controls whether
the clock is output (DDD5 set) or input (DDD5 cleared). The XCK1 pin is active only
when the USART1 operates in synchronous mode.
77
• ICP1 – Port D, Bit 4
ICP1 – Input Capture Pin1: The PD4 pin can act as an Input Capture pin for
Timer/Counter1.
• INT3/TXD1 – Port D, Bit 3
INT3, External Interrupt Source 3: The PD3 pin can serve as an External Interrupt
source to the MCU.
TXD1, Transmit Data (Data output pin for the USART1). When the USART1 transmitter
is enabled, this pin is configured as an output regardless of the value of DDD3.
• INT2/RXD1 – Port D, Bit 2
INT2, External Interrupt source 2. The PD2 pin can serve as an External Interrupt
source to the MCU.
RXD1, Receive Data (Data input pin for the USART1). When the USART1 receiver is
enabled this pin is configured as an input regardless of the value of DDD2. When the
USART forces this pin to be an input, the pull-up can still be controlled by the PORTD2
bit.
• INT1/SDA – Port D, Bit 1
INT1, External Interrupt Source 1. The PD1 pin can serve as an External Interrupt
source to the MCU.
SDA, Two-wire Serial Interface Data: When the TWEN bit in TWCR is set (one) to
enable the Two-wire Serial Interface, pin PD1 is disconnected from the port and
becomes the serial data I/O pin for the Two-wire Serial Interface. In this mode, there is a
spike filter on the pin to suppress spikes shorter than 50 ns on the input signal, and the
pin is driven by an open drain driver with slew-rate limitation.
•INT0/SCL – Port D, Bit 0
INT0, External Interrupt Source 0. The PD0 pin can serve as an External Interrupt
source to the MCU.
SCL, Two-wire Serial Interface Clock: When the TWEN bit in TWCR is set (one) to
enable the Two-wire Serial Interface, pin PD0 is disconnected from the port and
becomes the serial clock I/O pin for the Two-wire Serial Interface. In this mode, there is
a spike filter on the pin to suppress spikes shorter than 50 ns on the input signal, and the
pin is driven by an open drain driver with slew-rate limitation.
Table 37 and Table 38 relates the alternate functions of Port D to the overriding signals
shown in Figure 33 on page 70.
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Table 37. Overriding Signals for Alternate Functions PD7..PD4
Signal NamePD7/T2PD6/T1PD5/XCK1PD4/ICP1
PUOE0000
PUOV0000
DDOE0000
DDOV0000
PVOE00UMSEL10
PVOV00XCK1 OUTPUT0
DIEOE0000
DIEOV0000
DIT2 INPUTT1 INPUTXCK1 INPUTICP1 INPUT
AIO––––
Table 38. Overriding Signals for Alternate Functions in PD3..PD0
Signal NamePD3/INT3/TXD1PD2/INT2/RXD1PD1/INT1/SDAPD0/INT0/SCL
PUOETXEN1RXEN1TWENTWEN
PUOV0PORTD2 • PUD
PORTD1 • PUDPORTD0 • PUD
(1)
DDOETXEN1RXEN1TWENTWEN
DDOV10SDA_OUTSCL_OUT
PVOETXEN10TWENTWEN
PVOVTXD1000
DIEOEINT3 ENABLEINT2 ENABLEINT1 ENABLEINT0 ENABLE
DIEOV1111
DIINT3 INPUTINT2 INPUT/RXD1INT1 INPUTINT0 INPUT
AIO––SDA INPUTSCL INPUT
Note:1. When enabled, the Two-wire Serial Interface enables Slew-rate controls on the output
pins PD0 and PD1. This is not shown on the figure. In addition, spike filters are connected between the AIO outputs shown in the port figure and the digital logic of the
TWI module.
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79
Alternate Functions of Port EThe Port E pins with alternate functions are shown in Table 39.
Table 39. Port E Pins Alternate Functions
Port PinAlternate Function
PE7INT7/ICP3
PE6INT6/ T3
PE5INT5/OC3C
for Timer/Counter3)
PE4INT4/OC3B
Timer/Counter3)
PE3AIN1/OC3A
Output A for Timer/Counter3)
PE2AIN0/XCK0
input/output)
PE1PDO/TXD0 (Programming Data Output or UART0 Transmit Pin)
PE0PDI/RXD0 (Programming Data Input or UART0 Receive Pin)
Note:1. ICP3, T3, OC3C, OC3B, OC3B, OC3A, and XCK0 not applicable in ATmega103 com-
patibility mode.
(1)
(External Interrupt 7 Input or Timer/Counter3 Input Capture Pin)
(1)
(External Interrupt 6 Input or Timer/Counter3 Clock Input)
(1)
(External Interrupt 5 Input or Output Compare and PWM Output C
(1)
(External Interrupt 4 Input or Output Compare and PWM Output B for
(1)
(Analog Comparator Negative Input or Output Compare and PWM
(1)
(Analog Comparator Positive Input or USART0 external clock
• INT7/ICP3 – Port E, Bit 7
INT7, External Interrupt Source 7: The PE7 pin can serve as an External Interrupt
source.
ICP3 – Input Capture Pin3: The PE7 pin can act as an Input Capture pin for
Timer/Counter3.
• INT6/T3 – Port E, Bit 6
INT6, External Interrupt Source 6: The PE6 pin can serve as an External Interrupt
source.
T3, Timer/Counter3 Counter Source.
• INT5/OC3C – Port E, Bit 5
INT5, External Interrupt Source 5: The PE5 pin can serve as an External Interrupt
source.
OC3C, Output Compare Match C output: The PE5 pin can serve as an external output
for the Timer/Counter3 Output Compare C. The pin has to be configured as an output
(DDE5 set – one) to serve this function. The OC3C pin is also the output pin for the
PWM mode timer function.
• INT4/OC3B – Port E, Bit 4
INT4, External Interrupt Source 4: The PE4 pin can serve as an External Interrupt
source.
80
OC3B, Output Compare Match B output: The PE4 pin can serve as an external output
for the Timer/Counter3 Output Compare B. The pin has to be configured as an output
(DDE4 set – one) to serve this function. The OC3B pin is also the output pin for the
PWM mode timer function.
ATmega64(L)
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ATmega64(L)
• AIN1/OC3A – Port E, Bit 3
AIN1 – Analog Comparator Negative input. This pin is directly connected to the negative
input of the Analog Comparator.
OC3A, Output Compare Match A output: The PE3 pin can serve as an external output
for the Timer/Counter3 Output Compare A. The pin has to be configured as an output
(DDE3 set – one) to serve this function. The OC3A pin is also the output pin for the
PWM mode timer function.
• AIN0/XCK0 – Port E, Bit 2
AIN0 – Analog Comparator Positive input. This pin is directly connected to the positive
input of the Analog Comparator.
XCK0, USART0 External Clock. The Data Direction Register (DDE2) controls whether
the clock is output (DDE2 set) or input (DDE2 cleared). The XCK0 pin is active only
when the USART0 operates in synchronous mode.
• PDO/TXD0 – Port E, Bit 1
PDO, SPI Serial Programming Data output. During Serial Program Downloading, this
pin is used as data output line for the ATmega64.
TXD0, UART0 Transmit Pin.
• PDI/RXD0 – Port E, Bit 0
PDI, SPI Serial Programming Data input. During serial program downloading, this pin is
used as data input line for the ATmega64.
RXD0, USART0 Receive pin. Receive Data (Data Input pin for the USART0). When the
USART0 Receiver is enabled this pin is configured as an input regardless of the value of
DDRE0. When the USART0 forces this pin to be an input, a logical one in PORTE0 will
turn on the internal pull-up.
Table 40 and Table 41 relates the alternate functions of Port E to the overriding signals
shown in Figure 33 on page 70.
Table 40. Overriding Signals for Alternate Functions PE7..PE4
Signal
NamePE7/INT7/ICP3PE6/INT6/T3PE5/INT5/OC3CPE4/INT4/OC3B
PUOE0000
PUOV0000
DDOE0000
DDOV0000
PVOE00OC3C ENABLEOC3B ENABLE
PVOV00OC3COC3B
DIEOEINT7 ENABLEINT6 ENABLEINT5 ENABLEINT4 ENABLE
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DIEOV1111
DIINT7 INPUT/ICP3
INPUT
AIO––––
INT7 INPUT/T3
INPUT
INT5 INPUTINT4 INPUT
81
Table 41. Overriding Signals for Alternate Functions in PE3..PE0
Signal
NamePE3/AIN1/OC3APE2/AIN0/XCK0PE1/PDO/TXD0PE0/PDI/RXD0
PUOE00TXEN0RXEN0
PUOV000PORTE0 • PUD
DDOE00TXEN0RXEN0
DDOV0010
PVOEOC3B ENABLEUMSEL0TXEN00
PVOVOC3BXCK0 OUTPUTTXD00
DIEOE0000
DIEOV0000
DI0XCK0 INPUT–RXD0
AIOAIN1 INPUTAIN0 INPUT––
Alternate Functions of Port FThe Port F has an alternate function as analog input for the ADC as shown in Table 42.
If some Port F pins are configured as outputs, it is essential that these do not switch
when a conversion is in progress. This might corrupt the result of the conversion. In
ATmega103 compatibility mode Port F is input only. If the JTAG interface is enabled, the
pull-up resistors on pins PF7(TDI), PF5(TMS) and PF4(TCK) will be activated even if a
reset occurs.
Table 42. Port F Pins Alternate Functions
Port PinAlternate Function
PF7ADC7/TDI (ADC input channel 7 or JTAG Test Data Input)
PF6ADC6/TDO (ADC input channel 6 or JTAG Test Data Output)
PF5ADC5/TMS (ADC input channel 5 or JTAG Test mode Select)
PF4ADC4/TCK (ADC input channel 4 or JTAG Test Clock)
PF3ADC3 (ADC input channel 3)
PF2ADC2 (ADC input channel 2)
PF1ADC1 (ADC input channel 1)
PF0ADC0 (ADC input channel 0)
• TDI, ADC7 – Port F, Bit 7
ADC7, Analog to Digital Converter, Channel 7
.
TDI, JTAG Test Data In: Serial input data to be shifted in to the Instruction Register or
Data Register (scan chains). When the JTAG interface is enabled, this pin can not be
used as an I/O pin.
• TDO, ADC6 – Port F, Bit 6
ADC6, Analog to Digital Converter, Channel 6
.
82
TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Register. When the JTAG interface is enabled, this pin can not be used as an I/O pin.
The TDO pin is tri-stated unless TAP states that shift out data are entered.
ATmega64(L)
2490I–AVR–11/04
• TMS, ADC5 – Port F, Bit 5
ATmega64(L)
ADC5, Analog to Digital Converter, Channel 5
.
TMS, JTAG Test mode Select: This pin is used for navigating through the TAP-controller
state machine. When the JTAG interface is enabled, this pin can not be used as an I/O
pin.
• TCK, ADC4 – Port F, Bit 4
ADC4, Analog to Digital Converter, Channel 4
.
TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG interface is enabled, this pin can not be used as an I/O pin.
• ADC3 - ADC0 – Port F, Bit 3..0
Analog to Digital Converter, Channel 3..0.
Table 43. Overriding Signals for Alternate Functions in PF7..PF4
Signal
NamePF7/ADC7/TDIPF6/ADC6/TDOPF5/ADC5/TMSPF4/ADC4/TCK
PUOEJTAGENJTAGENJTAGENJTAGEN
PUOV1011
DDOEJTAGENJTAGENJTAGENJTAGEN
DDOV0SHIFT_IR +
SHIFT_DR
PVOE0JTAGEN00
00
PVOV0TDO00
DIEOEJTAGENJTAGENJTAGENJTAGEN
DIEOV0000
DI––––
AIOTDI/ADC7 INPUTADC6 INPUTTMS/ADC5
INPUT
TCKADC4 INPUT
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83
Table 44. Overriding Signals for Alternate Functions in PF3..PF0
Signal
NamePF3/ADC3PF2/ADC2PF1/ADC1PF0/ADC0
PUOE0000
PUOV0000
DDOE0000
DDOV0000
PVOE0000
PVOV0000
DIEOE0000
DIEOV0000
DI––––
AIOADC3 INPUTADC2 INPUTADC1 INPUTADC0 INPUT
Alternate Functions of Port GIn ATmega103 compatibility mode, only the alternate functions are the defaults for Port
G, and Port G cannot be used as General Digital Port Pins. The alternate pin configuration is as follows:
Table 45. Port G Pins Alternate Functions
Port PinAlternate Function
PG4TOSC1 (RTC Oscillator Timer/Counter0)
PG3TOSC2 (RTC Oscillator Timer/Counter0)
PG2ALE (Address Latch Enable to external memory)
PG1RD (Read strobe to external memory)
PG0WR
(Write strobe to external memory)
• TOSC1 – Port G, Bit 4
TOSC2, Timer Oscillator pin 1: When the AS0 bit in ASSR is set (one) to enable asynchronous clocking of Timer/Counter0, pin PG4 is disconnected from the port, and
becomes the inverting output of the Oscillator amplifier. In this mode, a crystal Oscillator
is connected to this pin, and the pin can not be used as an I/O pin.
• TOSC2 – Port G, Bit 3
TOSC2, Timer Oscillator pin 2: When the AS0 bit in ASSR is set (one) to enable asynchronous clocking of Timer/Counter0, pin PG3 is disconnected from the port, and
becomes the input of the inverting Oscillator amplifier. In this mode, a crystal Oscillator
is connected to this pin, and the pin cannot be used as an I/O pin.
• ALE – Port G, Bit 2
ALE is the external data memory Address Latch Enable signal.
84
ATmega64(L)
•RD
– Port G, Bit 1
RD
is the external data memory read control strobe.
2490I–AVR–11/04
ATmega64(L)
•WR – Port G, Bit 0
WR
is the external data memory write control strobe.
Table 46 and Table 47 relates the alternate functions of Port G to the overriding signals
shown in Figure 33 on page 70.
Table 46. Overriding Signals for Alternate Functions in PG4..PG1
Signal NamePG4/TOSC1PG3/TOSC2PG2/ALEPG1/RD
PUOEAS0AS0SRESRE
PUOV0000
DDOEAS0AS0SRESRE
DDOV0011
PVOE00SRESRE
PVOV00ALERD
DIEOEAS0AS000
DIEOV0000
DI––––
AIOT/C0 OSC INPUTT/C0 OSC OUTPUT––
Table 47. Overriding Signals for Alternate Functions in PG0
In ATmega103 compatibility mode, DDRC and PINC Registers are initialized to being
Push-pull Zero Output. The port pins assumes their Initial Value, even if the clock is not
running. Note that the DDRC and PINC registers are available in ATmega103 compatibility mode, and should not be used for 100% backward compatibility.
Note that PORTG, DDRG, and PING are not available in ATmega103 compatibility
mode. In the ATmega103 compatibility mode Port G serves its alternate functions only
(TOSC1, TOSC2, WR
, RD and ALE).
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ATmega64(L)
External InterruptsThe External Interrupts are triggered by the INT7:0 pins. Observe that, if enabled, the
interrupts will trigger even if the INT7:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external interrupts can be triggered
by a falling or rising edge or a low level. This is set up as indicated in the specification for
the External Interrupt Control Registers – EICRA (INT3:0) and EICRB (INT7:4). When
the External Interrupt is enabled and is configured as level triggered, the interrupt will
trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT7:4 requires the presence of an I/O clock, described in “Clock Systems and
their Distribution” on page 35. Low level interrupts and the edge interrupt on INT3:0 are
detected asynchronously. This implies that these interrupts can be used for waking the
part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep
modes except Idle mode.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the
changed level must be held for some time to wake up the MCU. This makes the MCU
less sensitive to noise. The changed level is sampled twice by the Watchdog Oscillator
clock. The period of the Watchdog Oscillator is 1 µs (nominal) at 5.0V and 25°C. The
frequency of the Watchdog Oscillator is voltage dependent as shown in the “Electrical
Characteristics” on page 327. The MCU will wake up if the input has the required level
during this sampling or if it is held until the end of the start-up time. The start-up time is
defined by the SUT Fuses as described in “Clock Systems and their Distribution” on
page 35. If the level is sampled twice by the Watchdog Oscillator clock but disappears
before the end of the start-up time, the MCU will still wake up, but no interrupt will be
generated. The required level must be held long enough for the MCU to complete the
wake up to trigger the level interrupt.
This Register can not be reached in ATmega103 compatibility mode, but the Initial
Value defines INT3:0 as low level interrupts, as in ATmega103.
• Bits 7..0 – ISC31, ISC30 - ISC00, ISC00: External Interrupt 3 - 0 Sense Control
Bits
The External Interrupts 3 - 0 are activated by the external pins INT3:0 if the SREG I-flag
and the corresponding interrupt mask in the EIMSK is set. The level and edges on the
external pins that activate the interrupts are defined in Table 48. Edges on INT3..INT0
are registered asynchronously. Pulses on INT3:0 pins wider than the minimum pulse
width given in Table 49 will generate an interrupt. Shorter pulses are not guaranteed to
generate an interrupt. If low level interrupt is selected, the low level must be held until
the completion of the currently executing instruction to generate an interrupt. If enabled,
a level triggered interrupt will generate an interrupt request as long as the pin is held
low. When changing the ISCn bit, an interrupt can occur. Therefore, it is recommended
to first disable INTn by clearing its Interrupt Enable bit in the EIMSK Register. Then, the
ISCn bit can be changed. Finally, the INTn interrupt flag should be cleared by writing a
logical one to its Interrupt Flag bit (INTFn) in the EIFR Register before the interrupt is reenabled.
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89
Table 48. Interrupt Sense Control
ISCn1ISCn0Description
00The low level of INTn generates an interrupt request.
01Reserved
10The falling edge of INTn generates asynchronously an interrupt request.
11The rising edge of INTn generates asynchronously an interrupt request.
Note:1. n = 3, 2, 1or 0.
When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its
Interrupt Enable bit in the EIMSK Register. Otherwise an interrupt can occur when
the bits are changed.
Minimum pulse width for
asynchronous External Interrupt
ISC71ISC70ISC61ISC60ISC51ISC50ISC41ISC40EICRB
50ns
• Bits 7..0 – ISC71, ISC70 - ISC41, ISC40: External Interrupt 7 - 4 Sense Control
Bits
The External Interrupts 7 - 4 are activated by the external pins INT7:4 if the SREG I-flag
and the corresponding interrupt mask in the EIMSK is set. The level and edges on the
external pins that activate the interrupts are defined in Table 50. The value on the
INT7:4 pins are sampled before detecting edges. If edge or toggle interrupt is selected,
pulses that last longer than one clock period will generate an interrupt. Shorter pulses
are not guaranteed to generate an interrupt. Observe that CPU clock frequency can be
lower than the XTAL frequency if the XTAL divider is enabled. If low level interrupt is
selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an
interrupt request as long as the pin is held low.
Table 50. Interrupt Sense Control
ISCn1ISCn0Description
00The low level of INTn generates an interrupt request.
(1)
90
01Any logical change on INTn generates an interrupt request
10The falling edge between two samples of INTn generates an interrupt
request.
11The rising edge between two samples of INTn generates an interrupt
request.
Note:1. n = 7, 6, 5 or 4.
When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its
Interrupt Enable bit in the EIMSK Register. Otherwise an interrupt can occur when
the bits are changed.
When an INT7 - INT4 bit is written to one and the I-bit in the Status Register (SREG) is
set (one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the External Interrupt Control Registers – EICRA and EICRB defines whether
the External Interrupt is activated on rising or falling edge or level sensed. Activity on
any of these pins will trigger an interrupt request even if the pin is enabled as an output.
This provides a way of generating a software interrupt.
When an edge or logic change on the INT7:0 pin triggers an interrupt request, INTF7:0
becomes set (one). If the I-bit in SREG and the corresponding Interrupt Enable bit,
INT7:0 in EIMSK, are set (one), the MCU will jump to the Interrupt Vector. The flag is
cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by
writing a logical one to it. These flags are always cleared when INT7:0 are configured as
level interrupt. Note that when entering sleep mode with the INT3:0 interrupts disabled,
the input buffers on these pins will be disabled. This may cause a logic change in internal signals which will set the INTF3:0 flags. See “Digital Input Enable and Sleep Modes”
on page 69 for more information.
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91
8-bit Timer/Counter0
with PWM and
Asynchronous
Operation
Timer/Counter0 is a general purpose, single-channel, 8-bit Timer/Counter module. The
main features are:
• Overflow and Compare Match Interrupt Sources (TOV0 and OCF0)
• Allows Clocking from External 32 kHz Watch Crystal Independent of the I/O Clock
OverviewA simplified block diagram of the 8-bit Timer/Counter is shown in Figure 34. For the
actual placement of I/O pins, refer to “Pin Configuration” on page 2. CPU accessible I/O
Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O
Register and bit locations are listed in the “8-bit Timer/Counter Register Description” on
page 103.
Figure 34. 8-bit Timer/Counter Block Diagram
TCCRn
Timer/Counter
TCNTn
=
OCRn
count
clear
direction
= 0
Control Logic
TOPBOTTOM
=
0xFF
clk
Tn
Prescaler
OCn
(Int. Req.)
Wavefor m
Generation
T/C
Oscillator
TOVn
(Int. Req.)
clk
I/O
OCn
TOSC1
TOSC2
DATA B U S
clk
I/O
clk
ASY
Status Flags
Synchronized Status Flags
ASSRn
Asynchronous Mode
Select (ASn)
Synchronization Unit
RegistersThe Timer/Counter (TCNT0) and Output Compare Register (OCR0) are 8-bit registers.
Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag
Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask
Register (TIMSK). TIFR and TIMSK are not shown in the figure since these registers are
shared by other timer units.
The Timer/Counter can be clocked internally, via the prescaler, or asynchronously
clocked from the TOSC1/2 pins, as detailed later in this section. The asynchronous
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operation is controlled by the Asynchronous Status Register (ASSR). The Clock Select
logic block controls which clock source the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The
output from the Clock Select logic is referred to as the timer clock (clk
The double buffered Output Compare Register (OCR0) is compared with the
Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare
pin (OC0). See “Output Compare Unit” on page 94. for details. The Compare Match
event will also set the Compare Flag (OCF0) which can be used to generate an Output
Compare interrupt request.
DefinitionsMany register and bit references in this datasheet are written in general form. A lower
case “n” replaces the Timer/Counter number, in this case 0. However, when using the
register or bit defines in a program, the precise form must be used i.e. TCNT0 for
accessing Timer/Counter0 counter value and so on.
The definitions in Table 51 are also used extensively throughout this section.
Table 51. Definitions
BOTTOMThe counter reaches the BOTTOM when it becomes zero (0x00).
MAXThe counter reaches its MAXimum when it becomes 0xFF (decimal 255).
T0
).
Timer/Counter Clock
Sources
TOPThe counter reaches the TOP when it becomes equal to the highest
value in the count sequence. The TOP value can be assigned to be the
fixed value 0xFF (MAX) or the value stored in the OCR0 Register. The
assignment is dependent on the mode of operation.
The Timer/Counter can be clocked by an internal synchronous or an external asynchronous clock source. The clock source clk
When the AS0 bit in the ASSR Register is written to logic one, the clock source is taken
from the Timer/Counter Oscillator connected to TOSC1 and TOSC2. For details on
asynchronous operation, see “Asynchronous Status Register – ASSR” on page 106. For
details on clock sources and prescaler, see “Timer/Counter Prescaler” on page 109.
is by default equal to the MCU clock, clk
T0
I/O
.
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93
Counter UnitThe main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.
Figure 35 shows a block diagram of the counter and its surrounding environment.
Figure 35. Counter Unit Block Diagram
TOVn
DATA B US
(Int.Req.)
clk
TOSC1
TOSC2
I/O
count
TCNTnControl Logic
clear
direction
clk
Tn
Prescaler
topbottom
T/C
Oscillator
Signal description (internal signals):
countIncrement or decrement TCNT0 by 1.
directionSelects between increment and decrement.
clearClear TCNT0 (set all bits to zero).
clk
T0
Timer/Counter clock.
topSignalizes that TCNT0 has reached maximum value.
bottomSignalizes that TCNT0 has reached minimum value (zero).
Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk
). clkT0 can be generated from an external or internal
T0
clock source, selected by the Clock Select bits (CS02:0). When no clock source is
selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed
by the CPU, regardless of whether clk
is present or not. A CPU write overrides (has
T0
priority over) all counter clear or count operations.
The counting sequence is determined by the setting of the WGM01 and WGM00 bits
located in the Timer/Counter Control Register (TCCR0). There are close connections
between how the counter behaves (counts) and how waveforms are generated on the
Output Compare output OC0. For more details about advanced counting sequences
and waveform generation, see “Modes of Operation” on page 97.
The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation
selected by the WGM01:0 bits.
TOV0 can be used for generating a CPU interrupt.
Output Compare UnitThe 8-bit comparator continuously compares TCNT0 with the Output Compare Register
(OCR0). Whenever TCNT0 equals OCR0, the comparator signals a match. A match will
set the Output Compare Flag (OCF0) at the next timer clock cycle. If enabled (OCIE0 =
1), the Output Compare Flag generates an Output Compare interrupt. The OCF0 flag is
automatically cleared when the interrupt is executed. Alternatively, the OCF0 flag can
be cleared by software by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by
the WGM01:0 bits and Compare Output mode (COM01:0) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme
values in some modes of operation (“Modes of Operation” on page 97). Figure 36 shows
a block diagram of the Output Compare unit.
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Figure 36. Output Compare Unit, Block Diagram
DATA B US
ATmega64(L)
OCRn
TCNTn
= (8-bit Comparator )
OCFn (Int.Req.)
top
bottom
FOCn
Waveform Generator
WGMn1:0
COMn1:0
OCxy
The OCR0 Register is double buffered when using any of the Pulse Width Modulation
(PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation,
the double buffering is disabled. The double buffering synchronizes the update of the
OCR0 Compare Register to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby
making the output glitch-free.
The OCR0 Register access may seem complex, but this is not case. When the double
buffering is enabled, the CPU has access to the OCR0 Buffer Register, and if double
buffering is disabled the CPU will access the OCR0 directly.
Force Output CompareIn non-PWM waveform generation modes, the match output of the comparator can be
forced by writing a one to the Force Output Compare (FOC0) bit. Forcing Compare
Match will not set the OCF0 flag or reload/clear the timer, but the OC0 pin will be
updated as if a real Compare Match had occurred (the COM01:0 bits settings define
whether the OC0 pin is set, cleared or toggled).
Compare Match Blocking by
TCNT0 Write
All CPU write operations to the TCNT0 Register will block any Compare Match that
occurs in the next timer clock cycle, even when the timer is stopped. This feature allows
OCR0 to be initialized to the same value as TCNT0 without triggering an interrupt when
the Timer/Counter clock is enabled.
Using the Output Compare
Unit
Since writing TCNT0 in any mode of operation will block all Compare Matches for one
timer clock cycle, there are risks involved when changing TCNT0 when using the Output
Compare channel, independently of whether the Timer/Counter is running or not. If the
value written to TCNT0 equals the OCR0 value, the Compare Match will be missed,
resulting in incorrect waveform generation. Similarly, do not write the TCNT0 value
equal to BOTTOM when the counter is downcounting.
The setup of the OC0 should be performed before setting the Data Direction Register for
the port pin to output. The easiest way of setting the OC0 value is to use the Force Output Compare (FOC0) strobe bit in Normal mode. The OC0 Register keeps its value even
when changing between waveform generation modes.
Be aware that the COM01:0 bits are not double buffered together with the compare
value. Changing the COM01:0 bits will take effect immediately.
2490I–AVR–11/04
95
Compare Match Output
Unit
The Compare Output mode (COM01:0) bits have two functions. The Waveform Generator uses the COM01:0 bits for defining the Output Compare (OC0) state at the next
Compare Match. Also, the COM01:0 bits control the OC0 pin output source. Figure 37
shows a simplified schematic of the logic affected by the COM01:0 bit setting. The I/O
Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the
general I/O port control registers (DDR and PORT) that are affected by the COM01:0
bits are shown. When referring to the OC0 state, the reference is for the internal OC0
Register, not the OC0 pin.
Figure 37. Compare Match Output Unit, Schematic
COMn1
COMn0
FOCn
Waveform
Generator
DQ
OCn
1
0
OCn
Pin
DQ
PORT
DATA BUS
DQ
DDR
clk
I/O
The general I/O port function is overridden by the Output Compare (OC0) from the
Waveform Generator if either of the COM01:0 bits are set. However, the OC0 pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port
pin. The Data Direction Register bit for the OC0 pin (DDR_OC0) must be set as output
before the OC0 value is visible on the pin. The port override function is independent of
the Waveform Generation mode.
Compare Output Mode and
Waveform Generation
96
ATmega64(L)
The design of the Output Compare pin logic allows initialization of the OC0 state before
the output is enabled. Note that some COM01:0 bit settings are reserved for certain
modes of operation. See “8-bit Timer/Counter Register Description” on page 103.
The Waveform Generator uses the COM01:0 bits differently in Normal, CTC, and PWM
modes. For all modes, setting the COM01:0 = 0 tells the Waveform Generator that no
action on the OC0 Register is to be performed on the next Compare Match. For compare output actions in the non-PWM modes refer to Table 53 on page 104. For fast
PWM mode, refer to Table 54 on page 104, and for phase correct PWM refer to Table
55 on page 104.
2490I–AVR–11/04
ATmega64(L)
A change of the COM01:0 bits state will have effect at the first Compare Match after the
bits are written. For non-PWM modes, the action can be forced to have immediate effect
by using the FOC0 strobe bits.
Modes of OperationThe mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare
pins, is defined by the combination of the Waveform Generation mode (WGM01:0) and
Compare Output mode (COM01:0) bits. The Compare Output mode bits do not affect
the counting sequence, while the Waveform Generation mode bits do. The COM01:0
bits control whether the PWM output generated should be inverted or not (inverted or
non-inverted PWM). For non-PWM modes the COM01:0 bits control whether the output
should be set, cleared, or toggled at a Compare Match (See “Compare Match Output
Unit” on page 96.).
For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 101.
Normal ModeThe simplest mode of operation is the Normal mode (WGM01:0 = 0). In this mode the
counting direction is always up (incrementing), and no counter clear is performed. The
counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then
restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag
(TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero. The
TOV0 flag in this case behaves like a ninth bit, except that it is only set, not cleared.
However, combined with the timer overflow interrupt that automatically clears the TOV0
flag, the timer resolution can be increased by software. There are no special cases to
consider in the Normal mode, a new counter value can be written anytime.
Clear Timer on Compare
Match (CTC) Mode
The Output Compare unit can be used to generate interrupts at some given time. Using
the Output Compare to generate waveforms in Normal mode is not recommended,
since this will occupy too much of the CPU time.
In Clear Timer on Compare or CTC mode (WGM01:0 = 2), the OCR0 Register is used to
manipulate the counter resolution. In CTC mode the counter is cleared to zero when the
counter value (TCNT0) matches the OCR0. The OCR0 defines the top value for the
counter, hence also its resolution. This mode allows greater control of the Compare
Match output frequency. It also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in Figure 38. The counter value
(TCNT0) increases until a Compare Match occurs between TCNT0 and OCR0, and then
counter (TCNT0) is cleared.
Figure 38. CTC Mode, Timing Diagram
OCn Interrupt Flag Set
TCNTn
OCn
(Toggle)
(COMn1:0 = 1)
2490I–AVR–11/04
Period
14
23
97
An interrupt can be generated each time the counter value reaches the TOP value by
using the OCF0 flag. If the interrupt is enabled, the interrupt handler routine can be used
for updating the TOP value. However, changing the TOP to a value close to BOTTOM
when the counter is running with none or a low prescaler value must be done with care
since the CTC mode does not have the double buffering feature. If the new value written
to OCR0 is lower than the current value of TCNT0, the counter will miss the Compare
Match. The counter will then have to count to its maximum value (0xFF) and wrap
around starting at 0x00 before the Compare Match can occur.
For generating a waveform output in CTC mode, the OC0 output can be set to toggle its
logical level on each Compare Match by setting the Compare Output mode bits to toggle
mode (COM01:0 = 1). The OC0 value will not be visible on the port pin unless the data
direction for the pin is set to output. The waveform generated will have a maximum frequency of f
OC0
= f
/2 when OCR0 is set to zero (0x00). The waveform frequency is
clk_I/O
defined by the following equation:
f
f
OCn
clk_I/O
-----------------------------------------------=
2 N1OCRn+()⋅⋅
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
As for the Normal mode of operation, the TOV0 flag is set in the same timer clock cycle
that the counter counts from MAX to 0x00.
Fast PWM ModeThe fast Pulse Width Modulation or fast PWM mode (WGM01:0 = 3) provides a high fre-
quency PWM waveform generation option. The fast PWM differs from the other PWM
option by its single-slope operation. The counter counts from BOTTOM to MAX then
restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare
(OC0) is cleared on the Compare Match between TCNT0 and OCR0, and set at BOTTOM. In inverting Compare Output mode, the output is set on Compare Match and
cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the
fast PWM mode can be twice as high as the phase correct PWM mode that uses dualslope operation. This high frequency makes the fast PWM mode well suited for power
regulation, rectification, and DAC applications. High frequency allows physically small
sized external components (coils, capacitors), and therefore reduces total system cost.
98
In fast PWM mode, the counter is incremented until the counter value matches the MAX
value. The counter is then cleared at the following timer clock cycle. The timing diagram
for the fast PWM mode is shown in Figure 39. The TCNT0 value is in the timing diagram
shown as a histogram for illustrating the single-slope operation. The diagram includes
non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0
slopes represent Compare Matches between OCR0 and TCNT0.
ATmega64(L)
2490I–AVR–11/04
Figure 39. Fast PWM Mode, Timing Diagram
TCNTn
ATmega64(L)
OCRn Interrupt Flag Set
OCRn Update and
TOVn Interrupt Flag Set
OCn
OCn
Period
1
23
4567
(COMn1:0 = 2)
(COMn1:0 = 3)
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If
the interrupt is enabled, the interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0
pin. Setting the COM01:0 bits to two will produce a non-inverted PWM and an inverted
PWM output can be generated by setting the COM01:0 to three (See Table 54 on page
104). The actual OC0 value will only be visible on the port pin if the data direction for the
port pin is set as output. The PWM waveform is generated by setting (or clearing) the
OC0 Register at the Compare Match between OCR0 and TCNT0, and clearing (or setting) the OC0 Register at the timer clock cycle the counter is cleared (changes from
MAX to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
f
f
OCnPWM
clk_I/O
------------------=
N 256⋅
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
2490I–AVR–11/04
The extreme values for the OCR0 Register represent special cases when generating a
PWM waveform output in the fast PWM mode. If the OCR0 is set equal to BOTTOM, the
output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0 equal
to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM01:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved
by setting OC0 to toggle its logical level on each Compare Match (COM01:0 = 1). The
waveform generated will have a maximum frequency of f
oc0
= f
/2 when OCR0 is set
clk_I/O
to zero. This feature is similar to the OC0 toggle in CTC mode, except the double buffer
feature of the Output Compare unit is enabled in the fast PWM mode.
99
Phase Correct PWM ModeThe phase correct PWM mode (WGM01:0 = 1) provides a high resolution phase correct
PWM waveform generation option. The phase correct PWM mode is based on a dualslope operation. The counter counts repeatedly from BOTTOM to MAX and then from
MAX to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC0)
is cleared on the Compare Match between TCNT0 and OCR0 while upcounting, and set
on the Compare Match while downcounting. In inverting Output Compare mode, the
operation is inverted. The dual-slope operation has lower maximum operation frequency
than single slope operation. However, due to the symmetric feature of the dual-slope
PWM modes, these modes are preferred for motor control applications.
The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase
correct PWM mode the counter is incremented until the counter value matches MAX.
When the counter reaches MAX, it changes the count direction. The TCNT0 value will
be equal to MAX for one timer clock cycle. The timing diagram for the phase correct
PWM mode is shown on Figure 40. The TCNT0 value is in the timing diagram shown as
a histogram for illustrating the dual-slope operation. The diagram includes non-inverted
and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Compare Matches between OCR0 and TCNT0.
Figure 40. Phase Correct PWM Mode, Timing Diagram
OCn Interrupt
Flag Set
OCRn Update
TOVn Interrupt
Flag Set
TCNTn
OCn
OCn
Period
123
(COMn1:0 = 2)
(COMn1:0 = 3)
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The interrupt flag can be used to generate an interrupt each time the counter
reaches the BOTTOM value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on
the OC0 pin. Setting the COM01:0 bits to two will produce a non-inverted PWM. An
inverted PWM output can be generated by setting the COM01:0 to three (See Table 55
on page 104). The actual OC0 value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or
setting) the OC0 Register at the Compare Match between OCR0 and TCNT0 when the
counter increments, and setting (or clearing) the OC0 Register at Compare Match
100
ATmega64(L)
2490I–AVR–11/04
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