ATMEL ATmega603L-4AI, ATmega603L-4AC, ATmega603-6AI, ATmega603-6AC, ATmega103L-4AI Datasheet

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Features

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Utilizes the AVR® Enhanced RISC Architecture

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121 Powerful Instructions - Most Single Clock Cycle Execution

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128K bytes of In-System Reprogrammable Flash ATmega103/L 64K bytes of In-System Reprogrammable Flash ATmega603/L

– SPI Interface for In-System Programming – Endurance: 1,000 Write/Eras e Cycles

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4K bytes EEPROM ATmega103/L 2K bytes of EEPROM ATmega603/L

– Endurance: 100,000 Write/Erase Cycles

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4K bytes Internal SRAM

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32 x 8 General Purpose Working Registers + Peripheral Control Registers

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32 Programmable I/O Lines, 8 Output Lines, 8 Input Lines

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Programmable Serial UART + SPI Serial Interface

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Supply

– 2.7 - 3.6V ATmega603L/ATmega103L – 4.0 - 5.5V ATmega603/ATmega103

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Fully Static Operation

– 0 - 6 MHz ATmega603/ATmega103 – 0 - 4 MHz ATmega603L/ATmega103L

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Up to 6 MIPS Throughput at 6 MHz

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RTC with Separate Oscillator

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Two 8-Bit Timer/Counters with Separate Prescaler and PWM

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One 16-Bit Timer/Counter with Separate Prescaler, Compare, Capture Modes and Dual 8-, 9- or 10-Bit PWM

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Programmable Watchdog Timer with On-Chip Oscillator

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On-Chip Analog Comparator

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8-Channel, 10-Bit ADC

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Low Power Idle, Power Save and Power Down Modes

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Software Selectable Clock Frequency

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Programming Lock for Software Security

8-Bit Microcontroller with 64K/128K Bytes In-System Programmable Flash

ATmega603 ATmega603L ATmega103

Pin Configuration

ATmega103L

TQFP

Preliminary

A Tmega103/L

Rev. 0945BS–09/98

Note: This is a summ ary document. F or the co mplete 9 2

page document, please visit our web site at

www.atmel.com

and request literature #0945B.

or e-mail at

literature@atmel .com

Block Diagram

Figure 1.

AVCC

AGND

AREF

The ATmega603/103 Block Diagram

VCC

GND

PORTF BUFFERS

ANALOG MUX ADC

PROGRAM COUNTER

PROGRAM

FLASH

INSTRUCTION

DECODER

CONTROL

LINES

PORTA DRIVER/BUFFERS

DATAREGISTER

PORTA

STACK

POINTER

SRAM

GENERAL PURPOSE

REGISTERS

X Y Z

ALU

STATUS

PA0 - PA7PF0 - PF7

DATADIR.

REG. PORTA

INTERNAL

OSCILLATOR

WATCHDOG

MCU CONTROL

COUNTERS

INTERRUPT

EEPROM

PROGRAMMING

TIMER

TIMER/

UNIT

LOGIC

8-BIT DATA BUS

OSCILLATOR

TIMING AND

PC0 - PC7

PORTC DRIVERS

DATAREGISTER

PORTC

CONTROL

XTAL1

TOSC2

TOSC1

RESET

ALE WR

PEN

SPI

ANALOG

COMPARATOR

DATAREGISTER

PORTE

DATADIR.

REG. PORTE

DATAREGISTER

PORTB

PORTB DRIVER/BUFFERSPORTE DRIVER/BUFFERS

PB0 - PB7PE0 - PE7

Description

The ATmega603/103 is a low-power CMOS 8-bit microcon-

AVR

troller based on the executing powerful instructions in a single clock cycle, the ATmega603/103 achieves th roughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

The AVR core is b ased o n an enh anced RISC ar chite ctur e that combines a rich instruction set with 32 general purpose working regist ers. All the 32 regi sters are directl y connected to the Arithmetic Logic Unit (ALU), allowing two independent regist ers to be accessed in one single instruction executed in one c lock cycl e. The resu lting archite ctu re

enhanced RISC architecture. By

UART

DATADIR.

REG. PORTB

DATAREGISTER

PORTD

PORTD DRIVER/BUFFERS

PD0 - PD7

DATADIR.

REG. PORTD

VCC

GND

is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The ATmega603/103 provides the following features: 64K/128K bytes of In-system Programmable Flash, 2K/4K bytes EEPROM, 4K bytes SRAM , 32 general purpos e I/O lines, 8 Input lines , 8 Output lines , 32 general pur pose working registers, 4 flexible timer/counters with compare modes and PWM, UART, programmable Watchdog Timer with internal oscillator, an SPI serial port and three software selectable pow er saving modes. T he Idle M ode sto ps the CPU while allowing the SRAM, timer/counters, SPI port and interrupt system to continue func tioning. The Power

ATmega603(L) and ATmega103(L)

Down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power Save mode, the timer oscillator continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping.

The device is manufactured using A tmel’s high-density non-volatile memory technology. The on-chip ISP Flash allows the program memory to be reprogrammed in-system through a serial interface or by a co nventional non volatile memory programmer. By combining an 8-bit RISC CPU with a large array of ISP Flash on a monolithic chip, the Atmel ATmega603/103 is a powerful microcontroller that provides a h ighly flexibl e and cost effective solution to many embedded control appl ic ati on s.

The ATmega603/103 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.

Comparison Between ATmega 603 and ATmega 103

The ATmega603 h as 64K bytes o f In-Sys tem Pro gramm able Flash, 2K bytes o f EEPROM, an d 4K bytes o f internal SRAM. The ATmega603 does not have the ELPM instruction.

The ATmega103 has 128K bytes of In-System Programmable Flash, 4K bytes of EEPROM, and 4K bytes of internal SRAM. The ATmega10 3 has the ELPM instruct ion, necessary to reach the upper half of the Flash memory for constant table lookup.

Table 1 summarizes the dif ferent memory size s for the two devices.

Table 1.

Part Flash EEPROM SRAM

ATmega603 64K bytes 2K bytes 4K bytes ATmega103 128K bytes 4K bytes 4K bytes

Memory Size Summary

Pin Descriptions

VCC Supply voltage

GND

Ground

Port A (PA7..PA0)

Port A is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors (selected for each bit). The Port A output buffers can sink 20 mA and can drive LED displays directly. When pins PA0 to PA7 are used as inputs and are externally pull ed low, they will source c urrent if the internal pull-up resistors are activated.

Port A serves as Multiplexed Address/Data bus when using external SRAM.

Port B (PB7..PB0)

Port B is an 8-bi t b i-di r ect ion al I/O pin s wit h i nte rn al pu ll -up resistors. The Port B output buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low, will source current if the pull-up resistors are activated.

Port B also serves the functions of various special features.

Port C (PC7..PC0)

Port C is an 8- bi t Outp ut port . The Port C out put buf fer s can sink 20 mA.

Port C also serv es as Ad dress ou tput wh en using extern al SRAM.

Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port D output buffers can sink 20 mA. As inputs, Port D pins that are external ly pul le d low will s our ce current if the pull-up resistors are activated.

Port D also serves the functions of various special features.

Port E (PE7..PE0)

Port E is an 8-bit bi- directi onal I/O port with internal pull -up resistors. The Port E output buffers can sink 20 mA. As inputs, Port E pins t hat a re ex ter na lly p ull ed l ow w il l sour ce current if the pull-up resistors are activated.

Port E also serves the functions of various special features.

Port F (PF7..PF0)

Port F is an 8-bi t Input port. P ort F al so serv es as the a nalog inputs for the ADC.

RESET

input. A low on this pin for two machine cy cles while the oscillator is running resets the device.

XTAL1

Input to the inverting os cillator ampli fier and input to th e internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier

TOSC1

Input to the inverting Timer/Counter oscillator amplifier

TOSC2

Output from the inverting Timer/Counter oscillator amplifier

External SRAM Write Strobe.

External SRAM Read Strobe.

ALE

ALE is the Address Latch Enable used when the Ex ternal Memory is enabled. The ALE strob e is used to latch the low-order address (8 bits) into an address latch during the

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