BDTIC www.bdtic.com/ATMEL
Features
• High Performance, Low Power AVR
• Advanced RISC Architecture
– 124 Powerful Instructions - Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 1 MIPS Throughput at 1 MHz
• Nonvolatile Program and Data Memories
– 40K Bytes of In-System Self-Programmable Flash, Endurance: 10,000 Write/Erase
Cycles
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– 512 bytes EEPROM, Endurance: 100,000 Write/Erase Cycles
– 2K Bytes Internal SRAM
– Programming Lock for Software Security
• On-chip Debugging
– Extensive On-chip Debug Support
– Available through JTAG interface
• Battery Management Features
– Two, Three, or Four Cells in Series
– Deep Under-voltage Protection
– Over-current Protection (Charge and Discharge)
– Short-circuit Protection (Discharge)
– Integrated Cell Balancing FETs
– High Voltage Outputs to Drive Charge/Precharge/Discharge FETs
• Peripheral Features
– One 8-bit Timer/Counter with Separate Prescaler, Compare Mode, and PWM
– One 16-bit Timer/Counter with Separate Prescaler and Compare Mode
– 12-bit Voltage ADC, Eight External and Two Internal ADC Inputs
– High Resolution Coulomb Counter ADC for Current Measurements
– TWI Serial Interface for SM-Bus
– Programmable Wake-up Timer
– Programmable Watchdog Timer
• Special Microcontroller Features
– Power-on Reset
– On-chip Voltage Regulator
– External and Internal Interrupt Sources
– Four Sleep Modes: Idle, Power-save, Power-down, and Power-off
• Packages
– 48-pin LQFP
• Operating Voltage: 4.0 - 25V
• Maximum Withstand Voltage (High-voltage pins): 28V
• Temperature Range: -30°C to 85°C
– Speed Grade: 1 MHz
®
8-bit Microcontroller
8-bit
Microcontroller
with 40K Bytes
In-System
Programmable
Flash
ATmega406
Preliminary
Summary
2548ES–AVR–07/06
1. Pin Configurations
Figure 1-1. Pinout ATmega406.
Top View
(ADC0
(ADC1
(ADC2
(ADC3
(ADC4/INT0
(INT1
(INT2
(INT3/PCINT7) PA7
SGND
/PCINT0) PA0
/PCINT1) PA1
/PCINT2) PA2
/PCINT3) PA3
VREG
VCC
GND
/PCINT4) PA4
/PCINT5) PA5
/PCINT6) PA6
1
2
3
4
5
6
7
8
9
10
11
12
NNINIPI
48
47
13
14
XTAL1
RESET
PPI
VREFGND
VREFNVPV1
46
45
44
43
15
16
17
18
GND
XTAL2
(TDI/PCINT9) PB1
(TDO/PCINT8) PB0
PV2
PV3
PV4
GND
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
19
20
21
22
23
24
SCL
SDA
(PCINT13) PB5
(PCINT12) PB4
(TCK/PCINT11) PB3
(TMS/PCINT10) PB2
PVT
OD
VFET
OC
OPC
BATT
PC0
GND
PD1
PD0 (T0)
PB7 (OC0B/PCINT15)
PB6 (OC0A/PCINT14)
1.1 Disclaimer
2
ATmega406
Typical values contained in this datasheet are based on simulations and characterization of
other AVR microcontrollers manufactured on the same process technology. Min and Max values
will be available after the device is characterized.
2548ES–AVR–07/06
2. Overview
The ATmega406 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC
architecture. By executing powerful instructions in a single clock cycle, the ATmega406
achieves throughputs approaching 1 MIPS at 1 MHz.
2.1 Block Diagram
Figure 2-1. Block Diagram
ATmega406
RESET
VFET
VREG
XTAL1
XTAL2
BATT
VCC
GND
Oscillator
Circuits /
Clock
Generation
Watchdog
Oscillator
Watchdog
Timer
Powe r
Supervision
POR &
RESET
Charger
Detect
Voltage
Regulator
PD1..0
PORTD (2)
Wake-Up
Timer
CPU
JTAG
SRAMFlash
DATA BU S
PORTC (1)
PB7..0
PORTB (8)
8 bit T/C0
16 bit T/C1
EEPROM
PORTA (8)TWI
FET
Control
Battery
Protection
Cell
Balancing
Voltage
ADC
Voltage
Reference
Coulumb
Counter ADC
PA3..0
OPC
OC
OD
PPI
NNI
PVT
PV4
PV3
PV2
PV1
NV
SGND
VREF
VREFGND
PI
NI
2548ES–AVR–07/06
PC0SCASCL
PA7..0
The ATmega406 provides the following features: a Voltage Regulator, dedicated Battery Protection Circuitry, integrated cell balancing FETs, high-voltage analog front-end, and an MCU with
two ADCs with On-chip voltage reference for battery fuel gauging.
The voltage regulator operates at a wide range of voltages, 4.0 - 25 volts. This voltage is regulated to a constant supply voltage of nominally 3.3 volts for the integrated logic and analog
functions.
The battery protection monitors the battery voltage and charge/discharge current to detect illegal
conditions and protect the battery from these when required. The illegal conditions are deep
under-voltage during discharging, short-circuit during discharging and over-current during charging and discharging.
3
The integrated cell balancing FETs allow cell balancing algorithms to be implemented in
software.
The MCU provides the following features: 40K bytes of In-System Programmable Flash with
Read-While-Write capabilities, 512 bytes EEPROM, 2K byte SRAM, 32 general purpose working
registers, 18 general purpose I/O lines, 11 high-voltage I/O lines, a JTAG Interface for On-chip
Debugging support and programming, two flexible Timer/Counters with PWM and compare
modes, one Wake-up Timer, an SM-Bus compliant TWI module, internal and external interrupts,
a 12-bit Sigma Delta ADC for voltage and temperature measurements, a high resolution Sigma
Delta ADC for Coulomb Counting and instantaneous current measurements, a programmable
Watchdog Timer with internal Oscillator, and four software selectable power saving modes.
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The Idle mode stops the CPU while allowing the other chip function to continue functioning. The
Power-down mode allows the voltage regulator, battery protection, regulator current detection,
Watchdog Timer, and Wake-up Timer to operate, while disabling all other chip functions until the
next Interrupt or Hardware Reset. In Power-save mode, the Wake-up Timer and Coulomb
Counter ADC continues to run.
The device is manufactured using Atmel’s high voltage high density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System, by
a conventional non-volatile memory programmer or by an On-chip Boot program running on the
AVR core. The Boot program can use any interface to download the application program in the
Application Flash memory. Software in the Boot Flash section will continue to run while the
Application Flash section is updated, providing true Read-While-Write operation. By combining
an 8-bit RISC CPU with In-System Self-Programmable Flash, fuel gauging ADCs, dedicated battery protection circuitry, Cell Balancing FETs, and a voltage regulator on a monolithic chip, the
Atmel ATmega406 is a powerful microcontroller that provides a highly flexible and cost effective
solution for Li-ion Smart Battery applications.
The ATmega406 AVR is supported with a full suite of program and system development tools
including: C Compilers, Macro Assemblers, Program Debugger/Simulators, and On-chip
Debugger.
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ATmega406
2548ES–AVR–07/06
2.2 Pin Descriptions
2.2.1 VFET
High voltage supply pin. This pin is used as supply for the internal voltage regulator, described in
”Voltage Regulator” on page 114. In addition the voltage level on this pin is monitored by the bat-
tery protection circuit, for deep-under-voltage protection. For details, see ”Battery Protection” on
page 125.
2.2.2 VCC
Digital supply voltage. Normally connected to VREG.
2.2.3 VREG
Output from the internal Voltage Regulator. Used for external decoupling to ensure stable regulator operation. For details, see ”Voltage Regulator” on page 114.
2.2.4 VREF
Internal Voltage Reference for external decoupling. For details, see ”Voltage Reference and
Temperature Sensor” on page 121.
ATmega406
2.2.5 VREFGND
Ground for decoupling of Internal Voltage Reference. For details, see ”Voltage Reference and
Temperature Sensor” on page 121.
2.2.6 GND
Ground
2.2.7 SGND
Signal ground pin, used as reference for Voltage-ADC conversions. For details, see ”Voltage
ADC – 10-channel General Purpose 12-bit Sigma-Delta ADC” on page 116.
2.2.8 Port A (PA7:PA0)
PA3:PA0 serves as the analog inputs to the Voltage A/D Converter.
Port A also serves as a low-voltage 8-bit bi-directional I/O port with internal pull-up resistors
(selected for each bit). As inputs, Port A pins that are externally pulled low will source current if
the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes
active, even if the clock is not running.
Port A also serves the functions of various special features of the ATmega406 as listed in ”Alter-
nate Functions of Port A” on page 68.
2.2.9 Port B (PB7:PB0)
Port B is a low-voltage 8-bit bi-directional I/O port with internal pull-up resistors (selected for
each bit). As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
2548ES–AVR–07/06
Port B also serves the functions of various special features of the ATmega406 as listed in ”Alter-
nate Functions of Port B” on page 70.
5
2.2.10 Port C (PC0)
Port C is a high voltage Open Drain output port.
2.2.11 Port D (PD1:PD0)
Port D is a low-voltage 2-bit bi-directional I/O port with internal pull-up resistors (selected for
each bit). As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port D also serves the functions of various special features of the ATmega406 as listed in ”Alter-
nate Functions of Port D” on page 72.
2.2.12 SCL
SMBUS clock, Open Drain bidirectional pin.
2.2.13 SDA
SMBUS data, Open Drain bidirectional pin.
2.2.14 OC/OD/OPC
High voltage output to drive external Charge/Discharge/Pre-charge FETs. For details, see ”FET
Control” on page 133.
2.2.15 PI/NI
Unfiltered positive/negative input from external current sense resistor, used by the battery protection circuit, for over-current and short-circuit detection. For details, see ”Battery Protection” on
page 125.
2.2.16 PPI/NNI
Filtered positive/negative input from external current sense resistor, used to by the Coulomb
Counter ADC to measure charge/discharge currents flowing in the battery pack. For details, see
”Coulomb Counter - Dedicated Fuel Gauging Sigma-delta ADC” on page 106.
2.2.17 NV/PV1/PV2/PV3/PV4
NV, PV1, PV2, PV3, and PV4 are the inputs for battery cells 1, 2, 3 and 4, used by the Voltage
ADC to measure each cell voltage. For details, see ”Voltage ADC – 10-channel General Pur-
pose 12-bit Sigma-Delta ADC” on page 116.
2.2.18 PVT
PVT defines the pull-up level for the OD output.
2.2.19 BATT
Input for detecting when a charger is connected. This pin also defines the pull-up level for OC
and OPC outputs.
2.2.20 RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in Table 11 on page
38. Shorter pulses are not guaranteed to generate a reset.
6
ATmega406
2548ES–AVR–07/06
2.2.21 XTAL1
2.2.22 XTAL2
3. Resources
ATmega406
Input to the inverting Oscillator amplifier.
Output from the inverting Oscillator amplifier.
A comprehensive set of development tools, application notes and datasheets are available for
download on http://www.atmel.com/avr.
2548ES–AVR–07/06
7
4. Register Summary
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
(0xFF) Reserved – – – – – – – –
(0xFE) Reserved – – – – – – – –
(0xFD) Reserved – – – – – – – –
(0xFC) Reserved – – – – – – – –
(0xFB) Reserved – – – – – – – –
(0xFA) Reserved – – – – – – – –
(0xF9) Reserved – – – – – – – –
(0xF8) BPPLR – – – – – – BPPLE BPPL 128
(0xF7) BPCR – – – – DUVD SCD DCD CCD 128
(0xF6) CBPTR SCPT[3:0] OCPT[3:0] 129
(0xF5) BPOCD DCDL[3:0] CCDL[3:0] 130
(0xF4) BPSCD – – – – SCDL[3:0] 130
(0xF3) BPDUV – – DUVT1 DUVT0 DUDL[3:0] 131
(0xF2) BPIR DUVIF COCIF DOCIF SCIF DUVIE COCIE DOCIE SCIE 132
(0xF1) CBCR – – – – CBE4 CBE3 CBE2 CBE1 137
(0xF0) FCSR – – PWMOC PWMOPC CPS DFE CFE PFD 134
(0xEF) Reserved
(0xEE) Reserved
(0xED) Reserved – – – – – – – –
(0xEC) Reserved – – – – – – – –
(0xEB) Reserved – – – – – – – –
(0xEA) Reserved – – – – – – – –
(0xE9) CADICH CADIC[15:8] 111
(0xE8) CADICL CADIC[7:0] 111
(0xE7) CADRDC CADRDC[7:0] 112
(0xE6) CADRCC CADRCC[7:0] 112
(0xE5) CADCSRB – CADACIE CADRCIE CADICIE – CADACIF CADRCIF CADICIF 110
(0xE4) CADCSRA CADEN – CADUB CADAS1 CADAS0 CADSI1 CADSI0 CADSE 109
(0xE3) CADAC3 CADAC[31:24] 111
(0xE2) CADAC2 CADAC[23:16] 111
(0xE1) CADAC1 CADAC[15:8] 111
(0xE0) CADAC0 CADAC[7:0] 111
(0xDF) Reserved – – – – – – – –
(0xDE) Reserved – – – – – – – –
(0xDD) Reserved – – – – – – – –
(0xDC) Reserved – – – – – – – –
(0xDB) Reserved – – – – – – – –
(0xDA) Reserved – – – – – – – –
(0xD9) Reserved – – – – – – – –
(0xD8) Reserved – – – – – – – –
(0xD7) Reserved
(0xD6) Reserved
(0xD5) Reserved – – – – – – – –
(0xD4) Reserved
(0xD3) Reserved
(0xD2) Reserved
(0xD1) BGCRR BGCR7 BGCR6 BGCR5 BGCR4 BGCR3 BGCR2 BGCR1 BGCR0 123
(0xD0) BGCCR BGEN – BGCC5 BGCC4 BGCC3 BGCC2 BGCC1 BGCC0 123
(0xCF) Reserved – – – – – – – –
(0xCE) Reserved – – – – – – – –
(0xCD) Reserved
(0xCC) Reserved
(0xCB) Reserved – – – – – – – –
(0xCA) Reserved
(0xC9) Reserved
(0xC8) Reserved – – – – – – – –
(0xC7) Reserved
(0xC6) Reserved – – – – – – – –
(0xC5) Reserved
(0xC4) Reserved
(0xC3) Reserved – – – – – – – –
(0xC2) Reserved
(0xC1) Reserved
(0xC0) CCSR – – – – – –XOEACS 29
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
8
ATmega406
2548ES–AVR–07/06
ATmega406
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
(0xBF) Reserved – – – – – – – –
(0xBE) TWBCSR TWBCIF TWBCIE – – – TWBDT1 TWBDT0 TWBCIP 169
(0xBD) TWAMR TWAM[6:0] –150
(0xBC) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN –TWIE 147
(0xBB) TWDR 2–wire Serial Interface Data Register 149
(0xBA) TWAR TWA[6:0] TWGCE 149
(0xB9) TWSR TWS[7:3] – TWPS1 TWPS0 148
(0xB8) TWBR 2–wire Serial Interface Bit Rate Register 147
(0xB7) Reserved – – – – – – –
(0xB6) Reserved – – – – – – – –
(0xB5) Reserved – – – – – – – –
(0xB4) Reserved – – – – – – – –
(0xB3) Reserved – – – – – – – –
(0xB2) Reserved – – – – – – – –
(0xB1) Reserved – – – – – – – –
(0xB0) Reserved – – – – – – – –
(0xAF) Reserved – – – – – – – –
(0xAE) Reserved
(0xAD) Reserved
(0xAC) Reserved – – – – – – – –
(0xAB) Reserved – – – – – – – –
(0xAA) Reserved – – – – – – – –
(0xA9) Reserved – – – – – – – –
(0xA8) Reserved – – – – – – – –
(0xA7) Reserved – – – – – – – –
(0xA6) Reserved – – – – – – – –
(0xA5) Reserved – – – – – – – –
(0xA4) Reserved – – – – – – – –
(0xA3) Reserved – – – – – – – –
(0xA2) Reserved – – – – – – – –
(0xA1) Reserved – – – – – – – –
(0xA0) Reserved – – – – – – – –
(0x9F) Reserved – – – – – – – –
(0x9E) Reserved – – – – – – – –
(0x9D) Reserved – – – – – – – –
(0x9C) Reserved – – – – – – – –
(0x9B) Reserved – – – – – – – –
(0x9A) Reserved – – – – – – – –
(0x99) Reserved – – – – – – – –
(0x98) Reserved – – – – – – – –
(0x97) Reserved – – – – – – – –
(0x96) Reserved – – – – – – – –
(0x95) Reserved – – – – – – – –
(0x94) Reserved – – – – – – – –
(0x93) Reserved
(0x92) Reserved
(0x91) Reserved – – – – – – – –
(0x90) Reserved
(0x8F) Reserved
(0x8E) Reserved
(0x8D) Reserved – – – – – – – –
(0x8C) Reserved
(0x8B) Reserved
(0x8A) Reserved – – – – – – – –
(0x89) OCR1AH Timer/Counter1 – Output Compare Register A High Byte 101
(0x88) OCR1AL Timer/Counter1 – Output Compare Register A Low Byte 101
(0x87) Reserved – – – – – – – –
(0x86) Reserved
(0x85) TCNT1H Timer/Counter1 – Counter Register High Byte 101
(0x84) TCNT1L Timer/Counter1 – Counter Register Low Byte 101
(0x83) Reserved – – – – – – – –
(0x82) Reserved – – – – – – – –
(0x81) TCCR1B
(0x80) Reserved
(0x7F) Reserved – – – – – – – –
(0x7E) DIDR0
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – CTC1 CS12 CS11 CS10 100
– – – – – – – –
– – – – VADC3D VADC2D VADC1D VADC0D 120
2548ES–AVR–07/06
9
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