ATMEL ATmega32HVB User Manual

BDTIC www.bdtic.com/ATMEL

Features

• High Performance, Low Power AVR

• Advanced RISC Architecture

– 124 Powerful Instructions - Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 8 MIPS Throughput at 8 MHz

• High Endurance Non-volatile Memory Segments

– 16K/32K Bytes of In-System Self-Programmable Flash (ATmeg a1 6 H VB/32HVB)
– 512/1K Bytes EEPROM
– 1K/2K Bytes Internal SRAM
– Write/Erase Cycles 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program
True Read-While-Write Operation

– Programming Lock for Software Security

• Battery Management Features

– Two, three or Four Cells in Series
– High-current Protection (Charge and Discharge)
– Over-current Protection (Charge and Discharge)
– Short-circuit Protection (Discharge)
– High Voltage Outputs to Drive N-Channel Charge/Discharge FETs
– High Voltage Output to drive P-Channel Precharge FET
– Integrated Cell Balancing FETs

• Peripheral Features

– Two configurable 8- or 16-bit Timers with Separate Prescaler, Optional Input

Capture (IC), Compare Mode and CTC
– SPI - Serial Programmabl e Interface
– 12-bit Voltage ADC, Six External and One Internal ADC Input
– High Resolution Coulomb Counter ADC for Current Measurements
– TWI Serial Interface for SM-Bus
– Programmable Watchdog Timer

• Special Microcontroller Features

– debugWIRE On-chip Debug System
– In-System Programmable via SPI ports
– Power-on Reset
– On-chip Voltage Regulator with Short-circuit Monitoring Interface
– External and Internal Interrupt Sources
– Sleep Modes: Idle, ADC Noise Reduction, Power-save, and Power-off

• Additional Secure Authentication Features available only under ND A

• Packages

– 44-lead TSSOP

• Operating Voltage: 4 - 25V

• Maximum Withstand Voltage (High-voltage pins): 35V

• Temperature Range: -30°C to 85°C

• Speed Grade: 1-8 MHz

®

8-bit Microcontroller

(1)

8-bit

Microcontroller
with 16K/32K
Bytes In-System
Programmable
Flash

ATmega16HVB
ATmega32HVB

Advance
Information

Summary

8042AS–AVR–09/08

1. Pin Configurations

1

44

3

NI

NNI

VREFGND

VREF

GND

VREG

PA0(ADC0/SGND/PCINT0)

PA1(ADC1/SGND/PCINT1)

PA2(PCINT2/T0)

PA3(PCINT3/T1)

NC

VFET

BATT

VCC

GND

OD

NC

OC

RESET/dw

PB0(PCINT4/ICP00)

PB1(PCINT5/CKOUT)

PB2(PCINT6)

PI

PPI

NV

PV1

PV2

PV3

PV4

PVT

VCC

GND

PC5

PC4(SCL)

PC3(INT3/SDA)

PC2(INT2)

PC1(INT1)

PC0(INTO/EXTPROT)

PB7(MISO/PCINT11)

NC

PB6(MOSI/PCINT10)

PB5(SCK/PCINT9)

PB4(SS/PCINT8)

PB3(PCINT7)

2

4
5
6
7

8

9
10
11
12
13
14
15
16
17
18
19
20
21
22

43
42
41
40

39

38
37
36
35
34

33
32
31
30

29
28
27
26
25
24
23

1.1 TSSOP

Figure 1-1. TSSOP - pinout ATmega16HVB/32HVB

1.2 Pin Descriptions

1.2.1 VFET

1.2.2 VCC

1.2.3 VREG

2

ATmega16HVB/32HVB

High voltage supply pin. This pin is used as supply for th e internal voltage regulator, descri bed in

”Voltage Regulator” on page 132.

Digital supply voltage. Normally connected to VREG.

Output from the internal Voltage Regulator. Used for external decoupling to ensure stable regu­lator operation. For details, see ”Voltage Regulator” on page 132.

8042AS–AVR–09/08

1.2.4 VREF

Internal Voltage Reference for external d ecoupling. For details, see ”Voltage Reference and

Temperature Sensor” on page 124.

1.2.5 VREFGND

Ground for decoupling of Internal Voltage Reference. For details, see ”Voltage Reference and

Temperature Sensor” on page 124. Do not connect to GND or SGND on PCB.

1.2.6 GND

Ground

1.2.7 Port A (PA3..PA0)

Port A serves as a low-voltage 4-bit bi-direct ional I/O po rt with intern al pull-up resistors (selected
for each bit). As inputs, Port A pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port A pins are tri-stated when a reset co ndition becomes active,
even if the clock is not running.

Port A also serves the functions of various special features of the ATmega16HVB/32HVB as
listed in ”Alternate Functions of Port A” on page 76.

ATmega16HVB/32HVB

1.2.8 Port B (PB7..PB0)

Port B is a low-voltage 8-bit bi-directional I/O port with internal pull-up resistors (selected for
each bit). As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset co ndition becomes active,
even if the clock is not running.

Port B also serves the functions of various special features of the ATmega16HVB/32HVB as
listed in ”Alternate Functions of Port B” on page 77.

1.2.9 Port C (PC5)

Port C (PC5) is a high voltage Open Drain output port. Port C serves the functions of various
special features of the ATmega16HVB/32HVB as listed in ”Alternate Functions of Port C” on

page 67.

1.2.10 Port C (PC4..PC0)

Port C is a 5-bit high voltage Open Drain bi-directional I/O port. Port C serves the functions of
various special features of the ATmega16HVB/32HVB as listed in ”Alternate Functions of Port

C” on page 67.

1.2.11 OC/OD

High voltage output to drive Charge/Discharge. For details, see ”FET Driver” on page 147.

1.2.12 PI/NI

8042AS–AVR–09/08

Filtered positive/negative input from external current sense resistor, used to by the Coulomb
Counter ADC to measure charge/discharge currents flowing in the battery pack. For details, see

”Coulomb Counter - Dedicated Fuel Gauging Sigma-delta ADC” on page 110.

3

1.2.13 PPI/NNI

Unfiltered positive/negative input from external current sense resistor, used by the battery pro ­tection circuit, for over-current and short-circuit detection. For details, see ”Battery Protection” on

page 135.

1.2.14 NV/PV1/PV2/PV3/PV4

NV, PV1, PV2, PV3, and PV4 are the inputs for battery cells 1, 2, 3 and 4, used by the Voltage
ADC to measure each cell voltage. For details, see ”Voltage ADC – 7-channel General Purpose

12-bit Sigma-Delta ADC” on page 118.

1.2.15 PVT

Defines the source voltage level for the Charge FET driver. F or details, see ”FET Driver” on

page 147.

1.2.16 BATT

Input for detecting when a charger is connected. Defines the source voltage level for the Dis­charge FET driver. For details, see ”FET Driver” on page 147.

1.2.17 RESET

/dw

Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in Table 11 on page

38. Shorter pulses are not guaranteed to generate a reset. This pin is also used as debugWIRE
communication pin.

4

ATmega16HVB/32HVB

8042AS–AVR–09/08

2. Overview

PORTA (4)

SRAMFlash

CPU

EEPROM

PV2
NV

OC
OD

FET

Control

Voltage

ADC

Voltage

Reference

Coulumb

Counter ADC

GND

VCC

RESET/dW

Power

Supervision

POR &

RESET

Watchdog

Oscillator

Watchdog

Timer

Oscillator

Circuits /

Clock

Generation

VREF
VREFGND

PI
NI

PA3..0

PA1..0

8/16-bit T/C1

8/16-bit T/C0

PORTB (8)

PB7..0

SPI

Voltage

Regulator

Charger

Detect

VFET
VREG

BATT

PV1

DATA BUS

VPTAT

Current

Protection

Security

Module

PORTC (6)

PC5..0

Voltage Regulator
Monitor Interface

PB0

Oscillator
Sampling

Interface

Program

Logic

debugWIRE

Cell

Balancing

PV3

PV4

OPC

TWI

PPI
NNI

PORTA (4)

SRAMFlash

CPU

EEPROM

PV2
NV

OC
OD

FET

Control

Voltage

ADC

Voltage

Reference

Coulumb

Counter ADC

GND

VCC

RESET/dW

Power

Supervision

POR &

RESET

Watchdog

Oscillator

Watchdog

Timer

Oscillator

Circuits /

Clock

Generation

VREF
VREFGND

PI
NI

PA3..0

PA1..0

8/16-bit T/C1

8/16-bit T/C0

PORTB (8)

PB7..0

SPI

Voltage

Regulator

Charger

Detect

VFET
VREG

BATT

PV1

DATA BUS

VPTAT

Current

Protection

Security

Module

PORTC (6)

PC5..0

Voltage Regulator
Monitor Interface

PB0

Oscillator
Sampling

Interface

Program

Logic

debugWIRE

Cell

Balancing

PV3

PV4

OPC

TWI

PPI
NNI

The ATmega16HVB/32HVB is a monitoring and protection circuit for 3 and 4-cell Li-ion applica­tions with focus on high security/authentication, low cost and high utilization of the cell energy.
The device contains secure authentication features as well as autonomous battery protection
during charging and discharging. The External Protection Input can be used to implement othe r
battery protection mechanisms using external comp onent s, e.g. p rotectio n against char gers with
too high charge voltage can be easily implemented with a few low cost passive components.
The feature set makes the ATmega 16HVB/32HVB a k ey component in an y system focu sing on
high security, battery protection, high system utilization and low cost.

Figure 2-1. Block Diagram

ATmega16HVB/32HVB

8042AS–AVR–09/08

ATmega16HVB/32HVB provides the necessary redundancy on-chip to make sure that the bat­tery is protected in critical failure modes. The chip is specifically des igned to provide safety for
the battery cells in case of pin shorting, loss of power (either caused by battery pack short or V

CC

5

short), illegal charger connection or software runaway. This makes ATmega16HVB/32HVB the
ideal 1-chip solution for applications with focus on high safety.

The ATmega16HVB/32HVB features an integrated voltage regulator that operates at a wide
range of input voltages, 4 - 25 volts. This voltage is regulated to a constant supply voltage of
nominally 3.3 volts for the integrated logic and analog functions. The regulator capabilities, com­bined with a extremely low power consumption in the power saving modes, greatly enh ances the
cell energy utilization compared to existing solutions.

The chip utilizes Atmel's patented Deep Under-voltage Recovery (DUVR) mode that supports
pre-charging of deeply discharged ba ttery cells without using a se parate Pre-charge FET.
Optionally, Pre-charge FETs are supported for integration into many existing battery charging
schemes.

The battery protection monitors the charge and discharge current to detect illegal conditions and
protect the battery from these when required. A 12-bit Voltage ADC allows software to monitor
each cell voltage individually with high accuracy. The ADC also provides one interna l input chan­nel to measure on-chip temperature and two input channels intended for external thermistors.
An 18-bit ADC optimized for Coulomb Counting accumu lates charge an d discharg e currents and
reports accumulated current with high resolution and accuracy. It can also be used to provide
instantaneous current measurements with 13 bit resolution. Integrated Cell Balancing FETs
allow cell balancing algorithms to be implemented in software.

The MCU provides the following features: 16K/32K bytes of In -System Programma ble Flash with
Read-While-Write capabilities, 512/1K bytes EEPROM, 1K/2K bytes SRAM. 32 general purpose
working registers, 12 general purpose I/O lines, 5 general purpose high voltage open drain I/O
lines, one general purpose super high voltage open drain output, debugWIRE for On-chip
debugging and SPI for In-system Programming, a SM-Bus compliant TWI module, two flexible
Timer/Counters with Input Capture and compare modes.

Internal and external interrupts, a 12-bit Sigma Delta ADC for voltage an d temperature measur e­ments, a high resolution Sigma Delta ADC for Coulomb Counting and instan taneous current
measurements, integrated cell balancing FETs, Additional Secure Authentication Features, an
autonomous Battery Protection module, a programmable Watchdog Timer with internal Oscilla­tor, and software selectable power saving modes.

The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con­ventional CISC microcontrollers.

The device is manufactured using Atmel’s high voltage high density non-volatile memo ry tech­nology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System,
through an SPI serial interface, by a conven tional no n-volatile memory progr ammer or by a n On­chip Boot program running on the AVR core. The Boot program can use any interface to down­load the application program in the Application Flash memory. Software in the Boot Flash
section will continue to run while the Application Flash section is updated, providing true Read­While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable­Flash and highly accurate analog front-end in a monolithic chip.

The Atmel ATmega16HVB/32HVB is a powerful microcontroller that provides a highly flexible
and cost effective solution. It is part of the AVR Smart Battery family that provides secure

6

ATmega16HVB/32HVB

8042AS–AVR–09/08