Features
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• High Performance, Low Power AVR
• Advanced RISC Architecture
– 130 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Throughput at 20 MHz
– On-Chip 2-cycle Multiplier
• Non-volatile Program and Data Memories
– In-System Self-Programmable Flash, Endurance: 10,000 Write/Erase Cycles
32K bytes
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– EEPROM, Endurance: 100,000 Write/Erase Cycles
1K bytes
– Internal SRAM
2K bytes
– Programming Lock for Software Security
• JTAG (IEEE std. 1149.1 compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
• Peripheral Features
– 4 x 25 Segment LCD Driver (ATmega329P)
– 4 x 40 Segment LCD Driver (ATmega3290P)
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode
– Real Time Counter with Separate Oscillator
–Four PWM Channels
– 8-channel, 10-bit ADC
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Universal Serial Interface with Start Condition Detector
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
• Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and
Standby
• I/O and Packages
– 54/69 Programmable I/O Lines
– 64-lead TQFP, 64-pad QFN/MLF, and 100-lead TQFP
• Speed Grade:
– ATmega329PV/ATmega3290PV:
0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V
– ATmega329P/3290P:
0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V
• Temperature range:
– -40°C to 85°C Industrial
• Ultra-Low Power Consumption
– Active Mode:
420µA at 1 MHz, 1.8V
– Power-down Mode:
40 nA at 1.8V
– Power-save Mode:
750 nA at 1.8V
®
8-Bit Microcontroller
8-bit
Microcontroller
with 32K Bytes
In-System
Programmable
Flash
ATmega329P/V
ATmega3290P/V
Preliminary
8021A–AVR–12/06
1. Pin Configurations
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Figure 1-1. Pinout ATmega3290P
LCDCAP
(RXD/PCINT0) PE0
(TXD/PCINT1) PE1
(XCK/AIN0/PCINT2) PE2
(AIN1/PCINT3) PE3
(USCK/SCL/PCINT4) PE4
(DI/SDA/PCINT5) PE5
(DO/PCINT6) PE6
(CLKO/PCINT7) PE7
VCC
GND
DNC
(PCINT24/SEG35) PJ0
(PCINT25/SEG34) PJ1
DNC
DNC
DNC
DNC
(SS/PCINT8) PB0
(SCK/PCINT9) PB1
(MOSI/PCINT10) PB2
(MISO/PCINT11) PB3
(OC0A/PCINT12) PB4
(OC1A/PCINT13) PB5
(OC1B/PCINT14) PB6
TQFP
AVCC
AGND
AREF
PF0 (ADC0)
PF1 (ADC1)
PF2 (ADC2)
PF3 (ADC3)
PF4 (ADC4/TCK)
PF5 (ADC5/TMS)
PF6 (ADC6/TDO)
PF7 (ADC7/TDI)
DNC
DNC
PH7 (PCINT23/SEG36)
PH6 (PCINT22/SEG37)
PH5 (PCINT21/SEG38)
PH4 (PCINT20/SEG39)
DNC
DNC
GND
9998979695949392919089888786858483828180797877
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
INDEX CORNER
ATm ega3290
26272829303132333435363738394041424344454647484950
VCC
DNC
PA0 (COM0)
PA1 (COM1)
PA2 (COM2)
76
75
PA3 (COM3)
74
PA4 (SEG0)
73
PA5 (SEG1)
72
PA6 (SEG2)
71
PA7 (SEG3)
70
PG2 (SEG4)
69
PC7 (SEG5)
68
PC6 (SEG6)
67
DNC
66
PH3 (PCINT19/SEG7)
65
PH2 (PCINT18/SEG8)
64
PH1 (PCINT17/SEG9)
63
PH0 (PCINT16/SEG10)
62
DNC
61
DNC
60
DNC
59
DNC
58
PC5 (SEG11)
57
PC4 (SEG12)
56
PC3 (SEG13)
55
PC2 (SEG14)
54
PC1 (SEG15)
53
PC0 (SEG16)
52
PG1 (SEG17)
51
PG0 (SEG18)
DNC
RESET/PG5
(T1/SEG33) PG3
(T0/SEG32) PG4
(OC2A/PCINT15) PB7
VCC
GND
DNC
DNC
(TOSC2) XTAL2
(TOSC1) XTAL1
(PCINT26/SEG31) PJ2
(PCINT27/SEG30) PJ3
(PCINT28/SEG29) PJ4
(PCINT29/SEG28) PJ5
(PCINT30/SEG27) PJ6
DNC
(INT0/SEG25) PD1
(ICP1/SEG26) PD0
(SEG24) PD2
(SEG23) PD3
(SEG22) PD4
(SEG21) PD5
(SEG20) PD6
(SEG19) PD7
2
ATmega329P/3290P
8021A–AVR–12/06
Figure 1-2. Pinout ATmega329P
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GND
AVCC
64
63
LCDCAP
(RXD/PCINT0) PE0
(TXD/PCINT1) PE1
(XCK/AIN0/PCINT2) PE2
(AIN1/PCINT3) PE3
(USCK/SCL/PCINT4) PE4
(DI/SDA/PCINT5) PE5
(DO/PCINT6) PE6
(CLKO/PCINT7) PE7
(SS/PCINT8) PB0
(SCK/PCINT9) PB1
(MOSI/PCINT10) PB2
(MISO/PCINT11) PB3
(OC0A/PCINT12) PB4
(OC1A/PCINT13) PB5
(OC1B/PCINT14) PB6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
INDEX CORNER
17
AREF
62
19
PF0 (ADC0)
PF1 (ADC1)
61
6018592058
21
PF2 (ADC2)
PF3 (ADC3)
PF4 (ADC4/TCK)
PF5 (ADC5/TMS)
57225623552454255326522751
ATmega329
ATmega329P/3290P
VCC
GND
PF7 (ADC7/TDI)
PF6 (ADC6/TDO)
PA0 (COM0)
PA1 (COM1)
PA2 (COM2)
50
49
PA3 (COM3)
48
PA4 (SEG0)
47
PA5 (SEG1)
46
PA6 (SEG2)
45
PA7 (SEG3)
44
43
PG2 (SEG4)
42
PC7 (SEG5)
41
PC6 (SEG6)
40
PC5 (SEG7)
PC4 (SEG8)
39
PC3 (SEG9)
38
PC2 (SEG10)
37
PC1 (SEG11)
36
PC0 (SEG12)
35
34
PG1 (SEG13)
33
PG0 (SEG14)
29
28
32
31
30
VCC
GND
RESET/PG5
(T1/SEG24) PG3
(T0/SEG23) PG4
(OC2A/PCINT15) PB7
(TOSC2) XTAL2
(TOSC1) XTAL1
(ICP1/SEG22) PD0
(SEG18) PD4
(SEG19) PD3
(SEG20) PD2
(INT0/SEG21) PD1
(SEG16) PD6
(SEG17) PD5
(SEG15) PD7
Note: The large center pad underneath the QFN/MLF packages is made of metal and internally con-
nected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If
the center pad is left unconnected, the package might loosen from the board.
1.1 Disclaimer
Typical values contained in this datasheet are based on simulations and characterization of
other AVR microcontrollers manufactured on the same process technology. Min and Max values
will be available after the device is characterized.
2. Overview
The ATmega329P/3290P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By
executing powerful instructions in a single clock cycle, the ATmega329P/3290P achieves throughputs approaching 1 MIPS
per MHz allowing the system designer to optimize power consumption versus processing speed.
8021A–AVR–12/06
3
2.1 Block Diagram
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Figure 2-1. Block Diagram
AVCC
AGND
AREF
PH0 - PH7
PORTH DRIVERS
VCCGND
DATADIR.
REG. PORTH
PORTH
DATA REGISTER
DATADIR.
REG. PORTJ
DATA REGISTER
JTAG TAP
ON-CHIP DEBUG
BOUNDARY-
SCAN
PROGRAMMING
LOGIC
PORTF DRIVERS
PORTF
AVR CPU
DATADIR.
REG. PORTF
ADC
PROGRAM
COUNTER
PROGRAM
FLASH
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
CONTROL
LINES
DATA REGISTER
PORTA
STACK
POINTER
SRAM
GENERAL
PURPOSE
REGISTERS
X
Y
Z
ALU
STATUS
REGISTER
PA0 - PA7PF0 - PF7
PORTA DRIVERS
DATADIR.
REG. PORTA
8-BIT DATA BUS
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
MCU CONTROL
REGISTER
TIMER/
COUNTERS
INTERRUPT
UNIT
EEPROM
PORTC DRIVERS
DATAREGISTER
PORTC
CALIB. OSC
OSCILLATOR
TIMING AND
CONTROL
PC0 - PC7
DATADIR.
REG. PORTC
CONTROLLER/
LCD
DRIVER
XTAL1
XTAL2
RESET
4
PJ0 - PJ6
PORTJ DRIVERS
PORTJ
DATAREGISTER
ANALOG
COMPARATOR
DATA REGISTER
+
-
USART
PORTE
UNIVERSAL
SERIAL INTERFACE
REG. PORTE
PORTE DRIVERS
DATA DIR.
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
ATmega329P/3290P
DATA REGISTER
PORTB
PORTB DRIVERS
PB0 - PB7PE0 - PE7
DATADIR.
REG. PORTB
SPI
DATAREGISTER
PORTD
PORTD DRIVERS
PD0 - PD7
DATADIR.
REG. PORTD
DATAREG.
PORTG
PORTG DRIVERS
DATADIR.
REG. PORTG
PG0 - PG4
8021A–AVR–12/06
ATmega329P/3290P
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The ATmega329P/3290P provides the following features: 32K bytes of In-System Programmable Flash with Read-While-Write capabilities, 1K bytes EEPROM, 2K byte SRAM, 54/69 general
purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundary-scan,
On-chip Debugging support and programming, a complete On-chip LCD controller with internal
contrast control, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, Universal Serial Interface with Start Condition Detector,
an 8-channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, an SPI
serial port, and five software selectable power saving modes. The Idle mode stops the CPU
while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all
other chip functions until the next interrupt or hardware reset. In Power-save mode, the asynchronous timer and the LCD controller continues to run, allowing the user to maintain a timer
base and operate the LCD display while the rest of the device is sleeping. The ADC Noise
Reduction mode stops the CPU and all I/O modules except asynchronous timer, LCD controller
and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast
start-up combined with low-power consumption.
The device is manufactured using Atmel’s high density non-volatile memory technology. The
On-chip In-System re-Programmable (ISP) Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory
programmer, or by an On-chip Boot program running on the AVR core. The Boot program can
use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated,
providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System
Self-Programmable Flash on a monolithic chip, the Atmel ATmega329P/3290P is a powerful
microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.
The ATmega329P/3290P AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit
Emulators, and Evaluation kits.
2.2 Comparison between ATmega329P and ATmega3290P
The ATmega329P and ATmega3290P differs only in pin count and pinout. Table 2-1 on page 5
summarizes the different configurations for the four devices.
Table 2-1. Configuration Summary
Device Flash EEPROM RAM
ATmega329P 32K bytes 1K bytes 2K bytes 4 x 25 54
ATmega3290P 32K bytes 1K bytes 2K bytes 4 x 40 69
LCD
Segments
General Purpose
I/O Pins
8021A–AVR–12/06
5
2.3 Pin Descriptions
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The following section describes the I/O-pin special functions.
2.3.1 V
2.3.2 GND
2.3.3 Port A (PA7..PA0)
2.3.4 Port B (PB7..PB0)
CC
Digital supply voltage.
Ground.
Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port A output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port A also serves the functions of various special features of the ATmega329P/3290P as listed
on page 72.
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B has better driving capabilities than the other ports.
Port B also serves the functions of various special features of the ATmega329P/3290P as listed
on page 73.
2.3.5 Port C (PC7..PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port C also serves the functions of special features of the ATmega329P/3290P as listed on page
76.
2.3.6 Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port D also serves the functions of various special features of the ATmega329P/3290P as listed
on page 77.
6
ATmega329P/3290P
8021A–AVR–12/06
2.3.7 Port E (PE7..PE0)
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Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port E output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port E also serves the functions of various special features of the ATmega329P/3290P as listed
on page 79.
2.3.8 Port F (PF7..PF0)
Port F serves as the analog inputs to the A/D Converter.
Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins
can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port F
pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the
JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will
be activated even if a reset occurs.
ATmega329P/3290P
Port F also serves the functions of the JTAG interface.
2.3.9 Port G (PG5..PG0)
Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port G output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port G pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port G also serves the functions of various special features of the ATmega329P/3290P as listed
on page 79.
2.3.10 Port H (PH7..PH0)
Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port H output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port H pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port H pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port H also serves the functions of various special features of the ATmega3290P as listed on
page 79.
2.3.11 Port J (PJ6..PJ0)
Port J is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port J output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port J pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port J pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port J also serves the functions of various special features of the ATmega3290P as listed on
page 79.
8021A–AVR–12/06
7
2.3.12 RESET
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2.3.13 XTAL1
2.3.14 XTAL2
2.3.15 AVCC
2.3.16 AREF
2.3.17 LCDCAP
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in ”System and Reset
Characteristics” on page 332. Shorter pulses are not guaranteed to generate a reset.
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
Output from the inverting Oscillator amplifier.
AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to V
, even if the ADC is not used. If the ADC is used, it should be connected to V
CC
CC
through a low-pass filter.
This is the analog reference pin for the A/D Converter.
An external capacitor (typical > 470 nF) must be connected to the LCDCAP pin as shown in Fig-
ure 21-2. This capacitor acts as a reservoir for LCD power (V
ripple on V
but increases the time until V
LCD
reaches its target value.
LCD
). A large capacitance reduces
LCD
8
ATmega329P/3290P
8021A–AVR–12/06
3. Resources
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ATmega329P/3290P
A comprehensive set of development tools, application notes and datasheets are available for
download on http://www.atmel.com/avr.
8021A–AVR–12/06
9
4. About Code Examples
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This documentation contains simple code examples that briefly show how to use various parts of
the device. These code examples assume that the part specific header file is included before
compilation. Be aware that not all C compiler vendors include bit definitions in the header files
and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”
instructions must be replaced with instructions that allow access to extended I/O. Typically
“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
10
ATmega329P/3290P
8021A–AVR–12/06
5. AVR CPU Core
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5.1 Overview
This section discusses the AVR core architecture in general. The main function of the CPU core
is to ensure correct program execution. The CPU must therefore be able to access memories,
perform calculations, control peripherals, and handle interrupts.
5.2 Architectural Overview
Figure 5-1. Block Diagram of the AVR Architecture
ATmega329P/3290P
Data Bus 8-bit
Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Control Lines
Program
Counter
Direct Addressing
Status
and Control
32 x 8
General
Purpose
Registrers
ALU
Indirect Addressing
Data
SRAM
EEPROM
Interrupt
Unit
SPI
Unit
Watchdog
Timer
Analog
Comparator
I/O Module1
I/O Module 2
I/O Module n
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with
separate memories and buses for program and data. Instructions in the program memory are
executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed
in every clock cycle. The program memory is In-System Reprogrammable Flash memory.
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-
8021A–AVR–12/06
I/O Lines
11
ical ALU operation, two operands are output from the Register File, the operation is executed,
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and the result is stored back in the Register File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data
Space addressing – enabling efficient address calculations. One of the these address pointers
can also be used as an address pointer for look up tables in Flash program memory. These
added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and
a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to
directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot Program section and the
Application Program section. Both sections have dedicated Lock bits for write and read/write
protection. The SPM instruction that writes into the Application Flash memory section must
reside in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the
Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack
size is only limited by the total SRAM size and the usage of the SRAM. All user programs must
initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack
Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed
through the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global
Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the
Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data
Space locations following those of the Register File, 0x20 - 0x5F. In addition, the
ATmega329P/3290P has Extended I/O space from 0x60 - 0xFF in SRAM where only the
ST/STS/STD and LD/LDS/LDD instructions can be used.
5.3 ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose
working registers. Within a single clock cycle, arithmetic operations between general purpose
registers or between a register and an immediate are executed. The ALU operations are divided
into three main categories – arithmetic, logical, and bit-functions. Some implementations of the
architecture also provide a powerful multiplier supporting both signed/unsigned multiplication
and fractional format. See the “Instruction Set” section for a detailed description.
5.4 AVR Status Register
The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform
conditional operations. Note that the Status Register is updated after all ALU operations, as
12
ATmega329P/3290P
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specified in the Instruction Set Reference. This will in many cases remove the need for using the
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dedicated compare instructions, resulting in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored
when returning from an interrupt. This must be handled by software.
5.4.1 SREG – AVR Status Register
The AVR Status Register – SREG – is defined as:
Bit 76543210
0x3F (0x5F) I T H S V N Z C SREG
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable
Register is cleared, none of the interrupts are enabled independent of the individual interrupt
enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by
the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by
the application with the SEI and CLI instructions, as described in the instruction set reference.
ATmega329P/3290P
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the
BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the
BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful
in BCD arithmetic. See the “Instruction Set Description” for detailed information.
• Bit 4 – S: Sign Bit, S = N
⊕ V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement
Overflow Flag V. See the “Instruction Set Description” for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the
“Instruction Set Description” for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the
“Instruction Set Description” for detailed information.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction
Set Description” for detailed information.
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set
Description” for detailed information.
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13
5.5 General Purpose Register File
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The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve
the required performance and flexibility, the following input/output schemes are supported by the
Register File:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
Figure 5-2 shows the structure of the 32 general purpose working registers in the CPU.
Figure 5-2. AVR CPU General Purpose Working Registers
General R14 0x0E
Purpose R15 0x0F
Working R16 0x10
Registers R17 0x11
7 0 Addr.
R0 0x00
R1 0x01
R2 0x02
…
R13 0x0D
…
R26 0x1A X-register Low Byte
R27 0x1B X-register High Byte
R28 0x1C Y-register Low Byte
R29 0x1D Y-register High Byte
R30 0x1E Z-register Low Byte
R31 0x1F Z-register High Byte
Most of the instructions operating on the Register File have direct access to all registers, and
most of them are single cycle instructions.
As shown in Figure 5-2, each register is also assigned a data memory address, mapping them
directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the
registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.
5.5.1 The X-register, Y-register, and Z-register
The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect
address registers X, Y, and Z are defined as described in Figure 1.
Figure 1. The X-, Y-, and Z-registers
15 XH XL 0
X-register 707 0
R27 (0x1B) R26 (0x1A)
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5.6 Stack Pointer
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ATmega329P/3290P
15 YH YL 0
Y-register 707 0
R29 (0x1D) R28 (0x1C)
15 ZH ZL 0
Z-register 70 7 0
R31 (0x1F) R30 (0x1E)
In the different addressing modes these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the instruction set reference for details).
The Stack is mainly used for storing temporary data, for storing local variables and for storing
return addresses after interrupts and subroutine calls. The Stack Pointer Register always points
to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack
Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt
Stacks are located. This Stack space in the data SRAM must be defined by the program before
any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to
point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack
with the PUSH instruction, and it is decremented by two when the return address is pushed onto
the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is
popped from the Stack with the POP instruction, and it is incremented by two when data is
popped from the Stack with return from subroutine RET or return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of
bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register
will not be present.
5.6.1 SPH and SPL – Stack pointer High and Stack Pointer Low
Bit 151413121110 9 8
0x3E (0x5E) SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH
0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL
76543210
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
R/WR/WR/WR/WR/WR/WR/WR/W
Initial Value 00000000
00000000
5.7 Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
chip. No internal clock division is used.
Figure 2 shows the parallel instruction fetches and instruction executions enabled by the Har-
vard architecture and the fast-access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
, directly generated from the selected clock source for the
CPU
8021A–AVR–12/06
15
Figure 2. The Parallel Instruction Fetches and Instruction Executions
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T1 T2 T3 T4
clk
CPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 3 shows the internal timing concept for the Register File. In a single clock cycle an ALU
operation using two register operands is executed, and the result is stored back to the destination register.
Figure 3. Single Cycle ALU Operation
T1 T2 T3 T4
clk
CPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
5.8 Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset
Vector each have a separate program vector in the program memory space. All interrupts are
assigned individual enable bits which must be written logic one together with the Global Interrupt
Enable bit in the Status Register in order to enable the interrupt. Depending on the Program
Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12
are programmed. This feature improves software security. See the section ”Memory Program-
ming” on page 295 for details.
The lowest addresses in the program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in ”Interrupts” on page 54. The list also
determines the priority levels of the different interrupts. The lower the address the higher is the
priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request
0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL
bit in the MCU Control Register (MCUCR). Refer to ”Interrupts” on page 54 for more information.
The Reset Vector can also be moved to the start of the Boot Flash section by programming the
BOOTRST Fuse, see ”Boot Loader Support – Read-While-Write Self-Programming” on page
280.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled
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interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a
Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the
Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding
Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s)
to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is
cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is
cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt
Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the
Global Interrupt Enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These
interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the
interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one
more instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor
restored when returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.
No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the
CLI instruction. The following example shows how this can be used to avoid interrupts during the
timed EEPROM write sequence.
Assembly Code Example
in r16, SREG ; store SREG value
cli ; disable interrupts during timed sequence
sbi EECR, EEMWE ; start EEPROM write
sbi EECR, EEWE
out SREG, r16 ; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
__disable_interrupt();
EECR |= (1<<EEMWE); /* start EEPROM write */
EECR |= (1<<EEWE);
SREG = cSREG; /* restore SREG value (I-bit) */
8021A–AVR–12/06
17
When using the SEI instruction to enable interrupts, the instruction following SEI will be exe-
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cuted before any pending interrupts, as shown in this example.
Assembly Code Example
sei ; set Global Interrupt Enable
sleep; enter sleep, waiting for interrupt
; note: will enter sleep before any pending
; interrupt(s)
C Code Example
__enable_interrupt(); /* set Global Interrupt Enable */
__sleep(); /* enter sleep, waiting for interrupt */
/* note: will enter sleep before any pending interrupt(s) */
5.8.1 Interrupt Response Time
The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles the program vector address for the actual interrupt handling routine
is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack.
The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If
an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed
before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt
execution response time is increased by four clock cycles. This increase comes in addition to the
start-up time from the selected sleep mode.
A return from an interrupt handling routine takes four clock cycles. During these four clock
cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is
incremented by two, and the I-bit in SREG is set.
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ATmega329P/3290P
8021A–AVR–12/06
6. AVR Memories
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6.1 Overview
This section describes the different memories in the ATmega329P/3290P. The AVR architecture
has two main memory spaces, the Data Memory and the Program Memory space. In addition,
the ATmega329P/3290P features an EEPROM Memory for data storage. All three memory
spaces are linear.
6.2 In-System Reprogrammable Flash Program Memory
The ATmega329P/3290P contains 32K bytes On-chip In-System Reprogrammable Flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized
as 16K x 16. For software security, the Flash Program memory space is divided into two sections, Boot Program section and Application Program section.
The Flash memory has an endurance of at least 10,000 write/erase cycles. The
ATmega329P/3290P Program Counter (PC) is 14 bits wide, thus addressing the 16K program
memory locations. The operation of Boot Program section and associated Boot Lock bits for
software protection are described in detail in ”Boot Loader Support – Read-While-Write Self-Pro-
gramming” on page 280. ”Memory Programming” on page 295 contains a detailed description
on Flash data serial downloading using the SPI pins or the JTAG interface.
ATmega329P/3290P
Constant tables can be allocated within the entire program memory address space (see the LPM
– Load Program Memory instruction description).
Timing diagrams for instruction fetch and execution are presented in ”Instruction Execution Tim-
ing” on page 15.
8021A–AVR–12/06
19
Figure 6-1. Program Memory Map
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Program Memory
Application Flash Section
Boot Flash Section
0x0000
0x3FFF
6.3 SRAM Data Memory
Figure 6-2 shows how the ATmega329P/3290P SRAM Memory is organized.
The ATmega329P/3290P is a complex microcontroller with more peripheral units than can be
supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For
the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD
instructions can be used.
The lower 2304 data memory locations address both the Register File, the I/O memory,
Extended I/O memory, and the internal data SRAM. The first 32 locations address the Register
File, the next 64 location the standard I/O memory, then 160 locations of Extended I/O memory,
and the next 2048 locations address the internal data SRAM.
The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register
File, registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base address given
by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and
the 2,048 bytes of internal data SRAM in the ATmega329P/3290P are all accessible through all
these addressing modes. The Register File is described in ”General Purpose Register File” on
page 14.
20
ATmega329P/3290P
8021A–AVR–12/06
Figure 6-2. Data Memory Map
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6.3.1 Data Memory Access Times
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
Figure 6-3. On-chip Data SRAM Access Cycles
Address
clk
CPU
ATmega329P/3290P
Data Memory
32 Registers
64 I/O Registers
160 Ext I/O Reg.
Internal SRAM
(2048 x 8)
T1 T2 T3
Compute Address
0x0000 - 0x001F
0x0020 - 0x005F
0x0060 - 0x00FF
0x0100
0x08FF
cycles as described in Figure 6-3.
CPU
Address valid
Data
WR
Data
RD
6.4 EEPROM Data Memory
The ATmega329P/3290P contains 1K bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an
endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the
CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM
Data Register, and the EEPROM Control Register.
For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see
page 309, page 315, and page 298 respectively.
6.4.1 EEPROM Write During Power-down Sleep Mode
Memory Access Instruction
Write
Read
Next Instruction
When entering Power-down sleep mode while an EEPROM write operation is active, the
EEPROM write operation will continue, and will complete before the Write Access time has
passed. However, when the write operation is completed, the clock continues running, and as a
consequence, the device does not enter Power-down entirely. It is therefore recommended to
verify that the EEPROM write operation is completed before entering Power-down.
8021A–AVR–12/06
21
6.4.2 Preventing EEPROM Corruption
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6.5 I/O Memory
During periods of low V
too low for the CPU and the EEPROM to operate properly. These issues are the same as for
board level systems using EEPROM, and the same design solutions should be applied.
An EEPROM data corruption can be caused by two situations when the voltage is too low. First,
a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.
EEPROM data corruption can easily be avoided by following this design recommendation:
Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can
be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal
BOD does not match the needed detection level, an external low V
be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient.
The I/O space definition of the ATmega329P/3290P is shown in ”Register Summary” on page
338.
All ATmega329P/3290P I/Os and peripherals are placed in the I/O space. All I/O locations may
be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the
32 general purpose working registers and the I/O space. I/O Registers within the address range
0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the
value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the
instruction set section for more details. When using the I/O specific commands IN and OUT, the
I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using
LD and ST instructions, 0x20 must be added to these addresses. The ATmega329P/3290P is a
complex microcontroller with more peripheral units than can be supported within the 64 location
reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
the EEPROM data can be corrupted because the supply voltage is
CC,
reset Protection circuit can
CC
22
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most
other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore
be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
The I/O and peripherals control registers are explained in later sections.
The ATmega329P/3290P contains three General Purpose I/O Registers. These registers can be
used for storing any information, and they are particularly useful for storing global variables and
Status Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F are directly
bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
ATmega329P/3290P
8021A–AVR–12/06
6.6 Register Description
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6.6.1 EEPROM Read/Write Access
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in Table 6-1. A self-timing function, however,
lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power
supplies, V
period of time to run at a voltage lower than specified as minimum for the clock frequency used.
See Section “6.4.2” on page 22. for details on how to avoid problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
6.6.2 EEARH and EEARL – The EEPROM Address Register
Bit 151413121110 9 8
0x22 (0x42) –––––-EEAR9EEAR8EEARH
0x21 (0x41) EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL
Read/WriteRRRRRR/WR/WR/W
Initial Value00000XXX
is likely to rise or fall slowly on power-up/down. This causes the device for some
CC
76543210
R/W R/W R/W R/W R/W R/W R/W R/W
XXXXXXXX
ATmega329P/3290P
• Bits 15:10 – Res: Reserved Bits
These bits are reserved bits in the ATmega329P/3290P and will always read as zero.
• Bits 9:0 – EEAR9:0: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 1K
bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 1023.
The initial value of EEAR is undefined. A proper value must be written before the EEPROM may
be accessed.
6.6.3 EEDR – The EEPROM Data Register
Bit 76543210
0x20 (0x40) MSB LSB EEDR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
• Bits 7:0 – EEDR7:0: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to the
EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEAR.
8021A–AVR–12/06
23
6.6.4 EECR – The EEPROM Control Register
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Bit 76543210
0x1F (0x3F) – – – – EERIE EEMWE EEWE EERE EECR
Read/Write R R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 X 0
• Bits 7:4 – Res: Reserved Bits
These bits are reserved bits and will always read as zero.
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing
EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared.
• Bit 2 – EEMWE: EEPROM Master Write Enable
The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written.
When EEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM at
the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has
been written to one by software, hardware clears the bit to zero after four clock cycles. See the
description of the EEWE bit for an EEPROM write procedure.
• Bit 1 – EEWE: EEPROM Write Enable
The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address
and data are correctly set up, the EEWE bit must be written to one to write the value into the
EEPROM. The EEMWE bit must be written to one before a logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing
the EEPROM (the order of steps 3 and 4 is not essential):
1. Wait until EEWE becomes zero.
2. Wait until SPMEN in SPMCSR becomes zero.
3. Write new EEPROM address to EEAR (optional).
4. Write new EEPROM data to EEDR (optional).
5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.
6. Within four clock cycles after setting EEMWE, write a logical one to EEWE.
The EEPROM can not be programmed during a CPU write to the Flash memory. The software
must check that the Flash programming is completed before initiating a new EEPROM write.
Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the
Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See ”Boot Loader
Support – Read-While-Write Self-Programming” on page 280 for details about Boot
programming.
Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the
EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is
interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the
interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared
during all the steps to avoid these problems.
When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set,
the CPU is halted for two cycles before the next instruction is executed.
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• Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct
address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the
EEPROM read. The EEPROM read access takes one instruction, and the requested data is
available immediately. When the EEPROM is read, the CPU is halted for four cycles before the
next instruction is executed.
The user should poll the EEWE bit before starting the read operation. If a write operation is in
progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.
The calibrated Oscillator is used to time the EEPROM accesses. Table 6-1 lists the typical programming time for EEPROM access from the CPU.
Table 6-1. EEPROM Programming Time
Number of Calibrated
Symbol
EEPROM write (from CPU) 27,072 3.4 ms
The following code examples show one assembly and one C function for writing to the
EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The examples also
assume that no Flash Boot Loader is present in the software. If such code is present, the
EEPROM write function must also wait for any ongoing SPM command to finish.
RC Oscillator Cycles Typical Programming Time
8021A–AVR–12/06
25
Assembly Code Example
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EEPROM_write:
; Wait for completion of previous write
sbic EECR,EEWE
rjmp EEPROM_write
; Set up address (r18:r17) in address register
out EEARH, r18
out EEARL, r17
; Write data (r16) to Data Register
out EEDR,r16
; Write logical one to EEMWE
sbi EECR,EEMWE
; Start eeprom write by setting EEWE
sbi EECR,EEWE
ret
C Code Example
void EEPROM_write(unsigned int uiAddress, unsigned char ucData)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEWE))
;
/* Set up address and Data Registers */
EEAR = uiAddress;
EEDR = ucData;
/* Write logical one to EEMWE */
EECR |= (1<<EEMWE);
/* Start eeprom write by setting EEWE */
EECR |= (1<<EEWE);
}
The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of
these functions.
26
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Assembly Code Example
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EEPROM_read:
; Wait for completion of previous write
sbic EECR,EEWE
rjmp EEPROM_read
; Set up address (r18:r17) in address register
out EEARH, r18
out EEARL, r17
; Start eeprom read by writing EERE
sbi EECR,EERE
; Read data from Data Register
in r16,EEDR
ret
C Code Example
unsigned char EEPROM_read(unsigned int uiAddress)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEWE))
;
/* Set up address register */
EEAR = uiAddress;
/* Start eeprom read by writing EERE */
EECR |= (1<<EERE);
/* Return data from Data Register */
return EEDR;
}
ATmega329P/3290P
6.6.5 GPIOR2 – General Purpose I/O Register 2
Bit 76543210
0x2B (0x4B) MSB LSB GPIOR2
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
6.6.6 GPIOR1 – General Purpose I/O Register 1
Bit 76543210
0x2A (0x4A) MSB LSB GPIOR1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
6.6.7 GPIOR0 – General Purpose I/O Register 0
Bit 76543210
0x1E (0x3E) MSB LSB GPIOR0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
8021A–AVR–12/06
27
7. System Clock and Clock Options
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7.1 Clock Systems and their Distribution
Figure 7-1 presents the principal clock systems in the AVR and their distribution. All of the clocks
need not be active at a given time. In order to reduce power consumption, the clocks to modules
not being used can be halted by using different sleep modes, as described in ”Power Manage-
ment and Sleep Modes” on page 38. The clock systems are detailed below.
Figure 7-1. Clock Distribution
LCD Controller
Asynchronous
Timer/Counter
General I/O
Modules
CPU Core RAM
Flash and
EEPROM
7.1.1 CPU Clock – clk
The CPU clock is routed to parts of the system concerned with operation of the AVR core.
Examples of such modules are the General Purpose Register File, the Status Register and the
data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing
general operations and calculations.
7.1.2 I/O Clock – clk
I/O
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART.
The I/O clock is also used by the External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O
clock is halted. Also note that start condition detection in the USI module is carried out asynchronously when clk
7.1.3 Flash Clock – clk
CPU
FLASH
clk
I/O
clk
ASY
Timer/Counter
Oscillator
is halted, enabling USI start condition detection in all sleep modes.
I/O
External Clock
AVR Clock
Control Unit
Source clock
Clock
Multiplexer
Oscillator
Crystal
clk
CPU
clk
FLASH
Reset Logic
Watchdog Timer
Watchdog clock
Watchdog
Oscillator
Low-frequency
Crystal Oscillator
Calibrated RC
Oscillator
The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock.
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7.1.4 Asynchronous Timer Clock – clk
The Asynchronous Timer clock allows the Asynchronous Timer/Counter and the LCD controller
to be clocked directly from an external clock or an external 32 kHz clock crystal. The dedicated
clock domain allows using this Timer/Counter as a real-time counter even when the device is in
sleep mode. It also allows the LCD controller output to continue while the rest of the device is in
sleep mode.
7.1.5 ADC Clock – clk
ADC
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks
in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion
results.
7.2 Clock Sources
The device has the following clock source options, selectable by Flash Fuse bits as shown
below. The clock from the selected source is input to the AVR clock generator, and routed to the
appropriate modules.
Table 7-1. Device Clocking Options Select
Device Clocking Option CKSEL3..0
External Crystal/Ceramic Resonator 1111 - 1000
External Low-frequency Crystal 0111 - 0110
ASY
(1)
Calibrated Internal RC Oscillator 0010
External Clock 0000
Reserved 0011, 0001, 0101, 0100
Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.
The various choices for each clocking option is given in the following sections. When the CPU
wakes up from Power-down or Power-save, the selected clock source is used to time the startup, ensuring stable Oscillator operation before instruction execution starts. When the CPU starts
from reset, there is an additional delay allowing the power to reach a stable level before commencing normal operation. The Watchdog Oscillator is used for timing this real-time part of the
start-up time. The number of WDT Oscillator cycles used for each time-out is shown in Table 7-
2. The frequency of the Watchdog Oscillator is voltage dependent as shown in ”Typical Characteristics – Preliminary Data – TBD” on page 337.
Table 7-2. Number of Watchdog Oscillator Cycles
Typ Time-out (VCC = 5.0V) Typ Time-out (VCC = 3.0V) Number of Cycles
7.3 Default Clock Source
The device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 programmed. The default
clock source setting is the Internal RC Oscillator with longest start-up time and an initial system
clock prescaling of 8. This default setting ensures that all users can make their desired clock
source setting using an In-System or Parallel programmer.
4.1 ms 4.3 ms 4K (4,096)
65 ms 69 ms 64K (65,536)
8021A–AVR–12/06
29
7.4 Crystal Oscillator
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XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 7-2. Either a quartz crystal or a
ceramic resonator may be used.
C1 and C2 should always be equal for both crystals and resonators. The optimal value of the
capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the
electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for
use with crystals are given in Table 7-3. For ceramic resonators, the capacitor values given by
the manufacturer should be used.
Figure 7-2. Crystal Oscillator Connections
C2
C1
XTAL2
XTAL1
GND
The Oscillator can operate in three different modes, each optimized for a specific frequency
range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 7-3.
Table 7-3. Crystal Oscillator Operating Modes
Frequency Range
CKSEL3..1
(1)
100
101 0.9 - 3.0 12 - 22
110 3.0 - 8.0 12 - 22
111 8.0 - 12 - 22
Note: 1. This option should not be used with crystals, only with ceramic resonators.
(MHz)
0.4 - 0.9 –
Recommended Range for Capacitors C1 and
C2 for Use with Crystals (pF)
The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table
7-4.
Table 7-4. Start-up Times for the Crystal Oscillator Clock Selection
CKSEL0 SUT1..0
30
ATmega329P/3290P
Start-up Time from
Power-down and
Power-save
0 00 258 CK
0 01 258 CK
010 1K CK
(1)
(1)
(2)
Additional Delay
from Reset
(VCC = 5.0V) Recommended Usage
14CK + 4.1 ms
14CK + 65 ms
14CK
Ceramic resonator, fast
rising power
Ceramic resonator,
slowly rising power
Ceramic resonator,
BOD enabled
8021A–AVR–12/06
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