Asus 60-NK3MB1000-A01P(z96s) Schematics

5

4

3

2

1

01_Block Diagram

02_System Setting

03_Merom CPU (1)

ITP CONN.

P30

04_Merom CPU (2)

CPU

Z96S

DDR2 16Mx16 x4

05_CPU CAPS.

MEROM

CLOCK GEN

06_965PM--CPU (1)

P.23

34W

07_965PM--DDR2/PEG (2)

P.3~5

ICS 9LPR364BGLF-T P.25

D

08_965PM--DDR2 BUS (3)

D

09_965PM--POWER (4)

DDR2 16Mx16 x4

THERMAL CONTROL

10_965PM--POWER (5)

P.24

11_965PM--GND/STRAPPING (6)

G781

P.28

12_ICH8M(1)

LCDP.27

13_ICH8M(2)

nVIDIA

NORTH

DDR2 SO-DIMM0

14_ICH8M(3)

BRIDGE

15_ICH8M--PEW/GND (4)

GPU

CRTP.26

667MHz

P.16~18

16_DDR2 SO-DIMM0

Intel

NB8P-SE

17_DDR2 SO-DIMM1

CRESTLINE

18_DDR2 ADDRESS/TERMINATION

TV-OUT

820 BGA

965PM

DDR2 SO-DIMM1

19_VGA_nVIDIA_NB8P_MAIN(1)

P.19~24

20_VGA_nVIDIA_NB8P_Mem/LVDS1(2)

P.29

1299 FCBGA

667MHz

P.16~18

P.6~11

21_VGA_nVIDIA_NB8P_Mem/LVDS2(3)

22_VGA_nVIDIA_NB8P_PCI-E&PWR(4)

C

23_VGA_nVIDIA_NB8P_VRAM_A(5)

Debug Conn. P.50

C

24_VGA_nVIDIA_NB8P_VRAM_B(6)

25_CLOCK GEN-ICS9LPR364AGLF-T

ODD

26_CRT CONNECTOR

P.51

27_LVDS & INVERTER CONNECTOR

TPM 1.2 P.53

SOUTH

28_THER SENSOR & FAN

INFINEON SLB9635

BRIDGE

SATA HDD P.51

29_TV OUT CONN

30_G-SENSOR & ITP

ICH8-M

AUDIO AMPP.43

31_MINI CARD -- ROBSON

EC

32_SWITCH

ISA ROM

Earphon/SPDIF

ITE IT8511E P.44

33_DISCHARGE

P.47

676 BGA

AZALIA CODEC

P.43

34_GIGALAN-RTL8110SCL

P.12~14

Realtek ALC883

35_MDC&RJ45&RJ11

P.42

EXT MIC P.43

Internal KB

Touch Pad

36_MINI CARD -- WLAN

37_RICOH-R5C833_PCI

P.45

P.45

INT MIC1*2

B

38_RICOH-R5C833_1394/SD

MDC

P.35

P.43

B

39_4 in 1 CARD READER

4 in 1 Card

40_NEWCARD

Card Reader

Reader P.39

G-Sensor P.30

41_Port Bar

1394

42_AUDIO-CODEC-ALC882

MINICARD(ROBSON) P.31

Ricoh

43_AUDIO AMP & JACK

1394 P.38

P.37

44_EC-IT8511E

R5C833

45_Touch Pad/ KB

46_USB CONN

LAN

MINICARD(WLAN) P.36

47_ISA ROM

Realtek

48_LED

RTL8110SCL

P.34

49_DCIN & BAT CONN

61_POWER_CHARGER

NEWCARD P.40

50_Debug CONN.

62_POWER_DETECT

51_SATA-HDD & ODD

63_POWER_PROTECT

USB Port X4 P.46

52_SREW HOLE

64_POWER_LOAD SWITCH

53_TPM CONNECTOR

65_POWER_FLOWCHART

A

54_BT CONNECTOR

66_POWER_SIGNAL

A

Bluetooth

55_POWER_VCORE

67_HISTORY

P.54

56_POWER_SYSTEM_+3VO & +5VO

1.1

57_POWER_1.5VS&1.05VS

CMOS Camera P.43

Title : Block Diagram

58_POWER_I/O_DDR & VTT

Engineer:

Alan Chen

59_POWER_+3VAO

ASUSTek Computer INC.

Size

Project Name

Rev

60_POWER_VGA_CORE

Custom

Z96S

2.0

Date:

, 30, 2007

Sheet

1

of

67

5

4

3

2

1

5

4

3

2

1

EC GPIO SETTING

Pin

Pin Name

Signal Name

Type

Pin

Pin Name

Signal Name

Type

48

GPH0

VSUS_ON

O

54

GPH1

VSUS_GD#

I

PCI Device

IDSEL#

REQ/GNT#

Interrupts

32

PWM0/GPA0

BL_PWM_DA

O

33

PWM1/GPA1

FAN_PWM

O

55

GPH2

CPUPWR_GD#

I

69

GPH3

PM_PWRBTN#

O

36

PWM2/GPA2

CLK_PWRSAVE#

O

CARD READER

AD17

REQ#0/GNT#0

INTB-->INTB

70

GPH4

SUSC_ON

O

37

PWM3/GPA3

N/A

1394

AD17

REQ#0/GNT#0

INTA-->INTA

38

PWM4/GPA4

CHG_LED_UP#

O

75

GPH5

SUSB_ON

O

LAN

AD23

REQ#2/GNT#2

INTA-->INTC

D

39

PWM5/GPA5

PWR_LED_UP#

O

76

GPH6

CPU_VRON

O

D

105

GPH7

PM_RSMRST#

O

40

PWM6/GPA6

N/A

SM-Bus Device

SM-Bus Address

43

PWM7/GPA7

LCD_BACKOFF#

O

148

GPI0

SB_PWRGD

O

Clock Generator

1101001x

( D2 )

149

GPI1

N/A

153

RXD/GPB0

NUM_LED

O

SO-DIMM 0

1010000x

( A0 )

154

TXD/GPB1

CAP_LED

O

152

GPI2

MCHOK

I

SO-DIMM 1

1010001x

( A2 )

155

GPI3

CHG_EN#

O

162

GPB2

SCRL_LED

O

Thermal Sensor

0101110x

( 5C )

156

GPI4

PRECHG

O

163

SMCLK0/GPB3

SMB0_CLK

I/0

168

GPI5

BAT_LL#

O

164

SMDAT0GPB4

SMB0_DAT

I/0

174

GPI6

BAT_LEARN

O

5

GA20/GPB5

A20GATE

O

6

KBRST#/GPB6

RC_IN#

O

ICH8-M GPIO SETTING

165

GPB7

THRO_CPU

O

47

CLKOUT/GPC0

N/A

Pin

Pin Name

Signal Name

Type

Power_Well

Default

Pin

Pin Name

Signal Name

Type

Power_Well

Default

169

SMCLK1/GPC1

SMB1_CLK

I/0

AG12

GPIO0/BMBUSY#

PM_BMBUSY#

I/O

Core(To:3.3V)

GPI

AD16

GPIO42/OC3#

USB_CON_OC23#

I/O

SUS(To:3.3V)

Native

170

SMDAT1/GPC2

SMB1_DAT

I/0

AJ8

GPIO1/TACH1

VDDR_SEL0

I/O

Core(To:3.3V)

GPI

AG17

GPIO43/OC4#

USB_CON_OC4#

I/O

SUS(To:3.3V)

Native

171

GPC3

Mail_LED

O

F8

GPIO2/PIRQE#

INT_SHIFT_LOW#

I(OD)

Core(To:5V)

GPI

N/A

GPIO44

N/A

I/O

N/A

N/A

172

TMRI0/WUI2/GPC4

AC_OK#

I

G11

GPIO3/PIRQF#

INT_SHIFT_HIGH#

I(OD)

Core(To:5V)

GPI

N/A

GPIO45

N/A

I/O

N/A

N/A

C

C

F12

GPIO4/PIRQG#

PCI_INTG#

I(OD)

Core(To:5V)

GPI

N/A

GPIO46

N/A

I/O

N/A

N/A

175

GPC5

OP_SD#

O

176

TMRI1/WUI3/GPC6

BAT_IN_OC#

I

B3

GPIO5/PIRQH#

PCI_INTH#

I(OD)

Core(To:5V)

GPI

N/A

GPIO47

N/A

I/O

N/A

N/A

1

CK32KOUT/GPC7

N/A

AJ9

GPIO6/TACH2

VDDR_SEL1

I/O

Core(To:3.3V)

GPI

AD10

GPIO48/SDATAOUT1

TP

I/O

Core(To:3.3V)

GPI

26

RI1#/WUI0/GPD0

SUSB#

I

AH9

GPIO7/TACH3

VDDR_SEL2

I/O

Core(To:3.3V)

GPI

AG29

GPIO49/CPUPWRGD

H_PWRGD

I/O

V_CPU_IO

Native

29

RI2#/WUI1/GPD1

SUSC#

I

AE16

GPIO08

EXT_SMI#

I/O

SUS(To:3.3V)

GPI

E18

GPIO50/REQ1#

PCI_REQ#1

I/O

Core(To:5.5V)

Native

30

LPCRST#/WUI4//GPD2

PLT_RST#

I

AG19

GPIO09/WOL_EN

TP

I/O

SUS(To:3.3V)

GPI

C18

GPIO51/GNT1#

TP

I/O

Core(To:3.3V)

Native

31

ECSCI#/GPD3

EXT_SCI#

O

AJ24

GPIO10/CLGPIO1

TP

I/O

SUS(To:3.3V)

GPI

B19

GPIO52/REQ2#

PCI_REQ#2

I/O

Core(To:5.5V)

Native

AG22

SMBALERT#/GPIO11

NC

I/O

SUS(To:3.3V)

Native

F18

GPIO53/GNT2#

PCI_GNT#2

I/O

Core(To:3.3V)

Native

41

GPD4

RF_ON_SW#

O

42

GINT/GPD5

N/A

AC19

GPIO12

EXT_SCI#

I/O

SUS(To:3.3V)

GPI

A11

GPIO54/REQ3#

PCI_REQ#3

I/O

Core(To:5.5V)

Native

62

TACH0/GPD6

FAN0_TACH

I

AH21

GPIO13/GLAN_DOCL#

NC

I/O

SUS(To:3.3V)

Native

C10

GPIO55/GNT3#

NC

I/O

Core(To:3.3V)

Native

63

TACH1/GPD7

N/A

AF22

GPIO14/CLGPIO2

TP

I/O

SUS(To:3.3V)

GPI

87

ADC4/GPE0

EMAIL_SW#

I

AE20

GPIO15/STP_PCI#

STP_PCI#

I/O

SUS(To:3.3V)

Native

88

ADC5/GPE1

INTERNET#

I

AJ14

GPIO16/DPRSLPVR

PM_DPRSLPVR

I/O

Core(To:3.3V)

Native

89

ADC6/GPE2

EXPLORE_SW#

I

AG8

GPIO17/TACH0

PM_EXTTS#0

I/O

Core(To:3.3V)

GPI

90

ADC7/GPE3

DISTP_SW#

I

AH12

GPIO18

VCORE_SEL0

I/O

Core(To:3.3V)

GPO

B

2

PWRSW/GPE4

PWR_SW#

I

AJ10

GPIO19/SATA1GP

CB_SD#

I/O

Core(To:3.3V)

GPI

B

44

WUI5/GPE5

N/A

AE11

GPIO20

VCORE_SEL1

I/O

Core(To:3.3V)

GPO

24

LPCPD#/WUI6/GPE6

N/A

AJ12

GPIO21/SATA0GP

WLAN_BT_LED_EN#

I/O

Core(To:3.3V)

GPI

25

CLKRUN#/WUI7/GPE7

N/A

AG10

GPIO22/SCLOCK

TP

I/O

Core(To:3.3V)

GPI

101

GPJ2/DAC2

BL_DA

O

E6

GPIO23/LDRQ1#

TP

I/O

Core(To:3.3V)

Native

102

GPJ3/DAC3

BATSEL_2P#

O

AJ27

GPIO24/CLGPIO0

TP

I/O

SUS(To:3.3V)

GPO

81

GPK0/ADC0

P_PMON

I

AG18

GPIO25/STP_CPU#

STP_CPU#

I/O

SUS(To:3.3V)

Native

22

ECSMI#/GPM0

EXT_SMI#

O

AH27

GPIO26/S4_STATE#

TP

I/O

SUS(To:3.3V)

Native

116

PS2CLK2/GPF4

TP_CLK

I/0

AH25

GPIO27/QRT_STATE0

VGMCH_SEL0

I/O

SUS(To:3.3V)

GPO

117

PS2DAT2/GPF5

TP_DAT

I/0

AD16

GPIO28/QRT_STATE1

VGMCH_SEL1

I/O

SUS(To:3.3V)

GPO

118

PS2CLK3/GPF6

N/A

AG17

GPIO29/OC#5

USB_OC#5

I/O

SUS(To:3.3V)

Native

119

PS2DAT3/GPF7

N/A

AD12

GPIO30/OC#6

NEWCARD_OC#

I/O

SUS(To:3.3V)

Native

113

FA16/GPG0

FA16

O

AJ18

GPIO31/OC#7

USB_OC#7

I/O

SUS(To:3.3V)

Native

/

112

FA17/GPG1

FA17

O

AH11

GPIO32/CLKRUN#

PM_CLKRUN#

I/O

Core(To:3.3V)

Native

104

FA18/GPG2

FA18

O

AE10

GPIO33/HDA_DOCK_EN#

TP

I/O

Core(To:3.3V)

GPO

A

103

FA19/GPG3

N/A

AG14

GPIO34/HDA_DOCK_RST#

TP

I/O

Core(To:3.3V)

GPO

A

3

FA20/GPG4

LID_EC#

I

AG13

GPIO35/SATACLKREQ#

VGPU_SEL1

I/O

Core(To:3.3V)

GPO

4

FA21/GPG5

PMTHERM#

O

AF11

GPIO36/SATA2GP

WLAN_ON#

I/O

Core(To:3.3V)

GPI

1.1

AG11

GPIO37/SATA3GP

BT_ON#

I/O

Core(To:3.3V)

GPI

27

LPC80HL/GPG6

THRM_CPU#

I

28

LPC80LL/GPG7

AC_APR_UC#

I

AF9

GPIO38/SLOAD

PM_EXTTS#1

I/O

Core(To:3.3V)

GPI

Title : System Setting

AJ11

GPIO39/SDATAOUT0

CLK_PWRSAVE#

I/O

Core(To:3.3V)

GPI

ASUSTek Computer INC.

Engineer:

Alan Chen

AG16

GPIO40/OC1#

USB_CON_OC01#

I/O

SUS(To:3.3V)

Native

Size

Project Name

Rev

Custom

Z96S

2.0

AG15

GPIO41/OC2#

USB_CON_OC23#

I/O

SUS(To:3.3V)

Native

Date:

, 30, 2007

Sheet

2

of 67

5

4

3

2

1

D

C

B

A

5

4

3

2

1

CPU1A

<6>

H_D#[63:0]

H_D#[63:0]

H_A#3

J4

A[3]#

ADS#

H1

H_ADS#

<6>

<6>

H_A#[35:3]

H_A#[35:3]

H_A#4

L5

E2

A[4]#

BNR#

H_BNR#

<6>

H_A#5

L4

G5

A[5]#

BPRI#

H_BPRI#

<6>

H_A#6

K5

H_REQ#[4:0]

A[6]#

<6>

H_REQ#[4:0]

H_A#7

M3

H5

A[7]#

DEFER#

H_DEFER#

<6>

H_A#8

N2

F21

A[8]#

DRDY#

H_DRDY#

<6>

H_A#9

J1

E1

A[9]#

DBSY#

H_DBSY#

<6>

H_A#10

N3

A[10]#

H_A#11

P5

F1

D

A[11]#

BR0#

H_BREQ#0

<6>

+VCCP_CPU

H_A#12

P2

CPU1B

H_A#14

P4

A[14]#

INIT#

B3

H_INIT#

/X <12>

H_A#13

L2

A[12]#

D20

H_IERR#

R164

1

2

Do Not Stuff

A[13]#

IERR#

H_A#15

P1

A[15]#

H_D#0

E22

D[0]#

D[32]#

Y22

H_D#32

H_A#16

R1

H4

H_D#1

F24

AB24

H_D#33

A[16]#

LOCK#

H_LOCK#

<6>

D[1]#

D[33]#

M1

H_D#2

E26

V24

H_D#34

<6>

H_ADSTB#0

ADSTB[0]#

D[2]#

D[34]#

C1

H_D#3

G22

V26

H_D#35

RESET#

H_CPURST#

<6,30>

D[3]#

D[35]#

H_REQ#0

K3

F3

H_RS#0

H_D#4

F23

V23

H_D#36

REQ[0]#

RS[0]#

H_RS#0

<6>

D[4]#

D[36]#

H_REQ#1

H2

F4

H_RS#1

H_D#5

G25

T22

H_D#37

REQ[1]#

RS[1]#

H_RS#1

<6>

D[5]#

D[37]#

H_REQ#2

K2

G3

H_RS#2

H_D#6

E25

U25

H_D#38

REQ[2]#

RS[2]#

H_RS#2

<6>

D[6]#

D[38]#

H_REQ#3

J3

G2

H_D#7

E23

U23

H_D#39

REQ[3]#

TRDY#

H_TRDY#

<6>

D[7]#

D[39]#

H_REQ#4

L1

H_D#8

K24

Y25

H_D#40

REQ[4]#

D[8]#

D[40]#

G6

H_D#9

G24

W22

H_D#41

HIT#

H_HIT#

<6>

D[9]#

D[41]#

H_A#17

Y2

E4

H_D#10

J24

Y23

H_D#42

A[17]#

HITM#

H_HITM#

<6>

D[10]#

D[42]#

H_A#18

U5

H_D#11

J23

W24

H_D#43

A[18]#

D[11]#

D[43]#

H_A#19

R3

AD4

H_D#12

H22

W25

H_D#44

A[19]#

BPM[0]#

XDP_BPM#0 <30>

D[12]#

D[44]#

H_A#20

W6

AD3

H_D#13

F26

AA23

H_D#45

A[20]#

BPM[1]#

XDP_BPM#1

<30>

D[13]#

D[45]#

H_A#21

U4

AD1

H_D#14

K22

AA24

H_D#46

A[21]#

BPM[2]#

XDP_BPM#2

<30>

D[14]#

D[46]#

H_A#22

Y5

AC4

H_D#15

H23

AB25

H_D#47

A[22]#

BPM[3]#

XDP_BPM#3 <30>

D[15]#

D[47]#

H_A#23

U1

AC2

J26

Y26

A[23]#

PRDY#

XDP_BPM#4

<30>

<6> H_DSTBN#0

DSTBN[0]#

DSTBN[2]#

H_DSTBN#2

<6>

H_A#24

R4

AC1

XDP_BPM#5

H26

AA26

A[24]#

PREQ#

XDP_BPM#5

<30>

<6> H_DSTBP#0

DSTBP[0]#

DSTBP[2]#

H_DSTBP#2

<6>

H_A#25

T5

AC5

XDP_TCK

H25

U22

A[25]#

TCK

XDP_TCK

<30>

<6>

H_DINV#0

DINV[0]#

DINV[2]#

H_DINV#2

<6>

H_A#26

T3

AA6

XDP_TDI

A[26]#

TDI

XDP_TDI

<30>

H_A#27

W2

AB3

A[27]#

TDO

XDP_TDO

<30>

H_A#28

W5

AB5

XDP_TMS

H_D#16

N22

AE24

H_D#48

A[28]#

TMS

XDP_TMS

<30>

D[16]#

D[48]#

H_A#29

Y4

AB6

XDP_TRST#

H_D#17

K25

AD24

H_D#49

A[29]#

TRST#

XDP_TRST#

<30>

D[17]#

D[49]#

H_A#30

U2

C20

H_DBR#

H_D#18

P26

AA21

H_D#50

A[30]#

DBR#

D[18]#

D[50]#

H_A#31

V4

H_D#19

R23

AB22

H_D#51

C

A[31]#

D[19]#

D[51]#

H_A#32

W3

1

H_D#20

L23

AB21

H_D#52

A[32]#

D[20]#

D[52]#

H_A#33

AA4

THERMAL

T122

H_D#21

M24

AC26

H_D#53

A[33]#

D[21]#

D[53]#

H_A#34

AB2

/X

H_D#22

L22

AD20

H_D#54

A[34]#

D[22]#

D[54]#

H_A#35

AA3

D21 H_PROCHOT_S#

H_D#23

M23

AE22

H_D#55

A[35]#

PROCHOT#

D[23]#

D[55]#

V1

A24

H_D#24

P25

AF23

H_D#56

<6> H_ADSTB#1

ADSTB[1]#

THRMDA

H_THERMDA

<28>

D[24]#

D[56]#

B25

H_D#25

P23

AC25

H_D#57

THRMDC

H_THERMDC

<28>

D[25]#

D[57]#

A6

H_D#26

P22

AE21

H_D#58

<12>

H_A20M#

A20M#

+VCCP_CPU

D[26]#

D[58]#

A5

C7

PM_THRMTRIP# <7,12>

H_D#27

T24

AD21

H_D#59

<12>

H_FERR#

C4

FERR#

THERMTRIP#

H_D#28

R24

D[27]#

D[59]#

AC22

H_D#60

<12>

H_IGNNE#

IGNNE#

D[28]#

D[60]#

H_D#29

L25

AD23

H_D#61

D[29]#

D[61]#

D5

H_D#30

T25

AF22

H_D#62

Comp0,2 connect with Zo=27.4 ohm,

<12>

H_STPCLK#

STPCLK#

D[30]#

D[62]#

C6

H CLK

R165

H_D#31

N25

AC23

H_D#63

make trace length shorter than 0.5".

<12>

H_INTR

LINT0

D[31]#

D[63]#

B4

A22

1KOhm

L26

AE25

Comp 1,3 connect with Z0=55 ohm,

<12>

H_NMI

LINT1

BCLK[0]

CLK_CPU_BCLK <25>

<6>

H_DSTBN#1

DSTBN[1]#

DSTBN[3]#

H_DSTBN#3

<6>

A3

A21

1%

M26

AF24

<12>

H_SMI#

SMI#

BCLK[1]

CLK_CPU_BCLK# <25>

<6>

H_DSTBP#1

DSTBP[1]#

DSTBP[3]#

H_DSTBP#3

<6>

make trace length shorter than 0.5".

N24

AC20

T129

CPU_RSVD1

<6>

H_DINV#1

DINV[1]#

DINV[3]#

H_DINV#3

<6>

1

M4

RSVD1

T130

1

CPU_RSVD2

N5

CPU_GTLREF

AD26

R26

H_COMP0

R166

1

2

27.4Ohm 1%

RSVD2

GTLREF

COMP[0]

T132

1

CPU_RSVD3

T2

CPU_TEST1

C23

MISC

U26

H_COMP1

R167

1

2

54.9Ohm

RSVD3

TEST1

COMP[1]

T134

1

CPU_RSVD4

V3

CPU_TEST2

D25

AA1

H_COMP2

R168

1

2

27.4Ohm 1%

RSVD4

TEST2

COMP[2]

T136

1

CPU_RSVD5

B2

R169

T124

1

CPU_TEST3

C24

Y1

H_COMP3

R171

1

2

54.9Ohm

RSVD5

TEST3

COMP[3]

T137

1

CPU_RSVD6

C3

C294

2KOhm

CPU_TEST4

AF26

RSVD6

TEST4

T138

1

CPU_RSVD7

D2

0.1UF/10V

1%

T127

1

CPU_TEST5

AF1

E5

RSVD7

TEST5

DPRSTP#

H_DPRSTP#

<7,12>

T139

1

CPU_RSVD8

D22

T128

1

CPU_TEST6

A26

B5

GND

RSVD8

TEST6

DPSLP#

H_DPSLP#

<12>

T140

1

CPU_RSVD9

D3

Zo=55 ohm, 0.5" max

D24

RSVD9

DPWR#

H_DPWR#

<6>

T141

1

CPU_RSVD10

F6

for GTLREF

B22

D6

RSVD10

<25> CPU_BSEL0

BSEL[0]

PWRGOOD

H_PWRGD

<12>

GND

GND

B23

D7

<25> CPU_BSEL1

BSEL[1]

SLP#

H_CPUSLP#

<6>

C21

AE6

<25> CPU_BSEL2

BSEL[2]

PSI#

PM_PSI#

<55>

SOCKET478B

SOCKET478B

B

12G010594786

12G010594786

2

1

XDP_PWRGD

<30>

R437

+VCCP_CPU

1KOhm

1%

+VCCP_CPU

R436		Do Not Stuff
XDP_TDO	1	/X2		R173
				68Ohm	T304
R438		Do Not Stuff
XDP_TMS	1	/X2	H_PROCHOT_S#		CPU_TEST1	R170			Do Not Stuff1%	/X
				T4Q7			2	1
R439		Do Not Stuff	D 3	H2N7002
XDP_TDI	1	/X2			CPU_TEST2	R172	2	1	Do Not Stuff1%	/X
R440		Do Not Stuff		11	THRO_CPU <44>
				G
			S 2
XDP_BPM#5	1	/X2			CPU_TEST4	C618	1	2	Do Not Stuff	/X
R441		Do Not Stuff								A
XDP_TCK	1	/X2
			GND							GND

R100		Do Not Stuff		1.1
XDP_TRST#	1	/X2
							Title : MEROM CPU (1)
		GND		ASUSTeK COMPUTER INC			Engineer:	Alan Chen
				Size	Project Name					Rev
				Custom		Z96S				2.0
				Date:	,	30, 2007	Sheet	3	of	67
	5	4	3	2			1

D

C

B

A

5

4

3

2

1

CPU1D

A4

VSS1

VSS82

P6

A8

P21

+VCORE

+VCORE

VSS2

VSS83

A11

P24

VSS3

VSS84

CPU1C

A14

R2

D

VSS4

VSS85

A19

R22

A16

VSS5

VSS86

R5

A7

AB20

A23

VSS6

VSS87

R25

VCC1

VCC68

VSS7

VSS88

A9

AB7

AF2

T1

VCC2

VCC69

VSS8

VSS89

A10

AC7

B6

T4

VCC3

VCC70

VSS9

VSS90

A12

AC9

B8

T23

VCC4

VCC71

VSS10

VSS91

A13

AC12

B11

T26

VCC5

VCC72

VSS11

VSS92

A15

AC13

B13

U3

VCC6

VCC73

VSS12

VSS93

A17

AC15

B16

U6

VCC7

VCC74

VSS13

VSS94

A18

AC17

B19

U21

VCC8

VCC75

VSS14

VSS95

A20

AC18

B21

U24

VCC9

VCC76

VSS15

VSS96

B7

AD7

B24

V2

VCC10

VCC77

VSS16

VSS97

B9

AD9

C5

V5

VCC11

VCC78

VSS17

VSS98

B10

AD10

C8

V22

VCC12

VCC79

VSS18

VSS99

B12

AD12

C11

V25

VCC13

VCC80

VSS19

VSS100

B14

AD14

C14

W1

VCC14

VCC81

VSS20

VSS101

B15

AD15

C16

W4

VCC15

VCC82

VSS21

VSS102

B17

AD17

C19

W23

VCC16

VCC83

VSS22

VSS103

B18

AD18

C2

W26

VCC17

VCC84

VSS23

VSS104

B20

AE9

C22

Y3

VCC18

VCC85

VSS24

VSS105

C9

AE10

C25

Y6

VCC19

VCC86

VSS25

VSS106

C10

AE12

D1

Y21

VCC20

VCC87

VSS26

VSS107

C12

AE13

D4

Y24

VCC21

VCC88

VSS27

VSS108

C13

AE15

D8

AA2

VCC22

VCC89

VSS28

VSS109

C15

AE17

D11

AA5

VCC23

VCC90

VSS29

VSS110

C17

AE18

D13

AA8

VCC24

VCC91

VSS30

VSS111

C18

AE20

D16

AA11

VCC25

VCC92

VSS31

VSS112

D9

AF9

D19

AA14

C

VCC26

VCC93

VSS32

VSS113

D10

AF10

D23

AA16

VCC27

VCC94

VSS33

VSS114

D12

AF12

D26

AA19

VCC28

VCC95

VSS34

VSS115

D14

AF14

E3

AA22

VCC29

VCC96

VSS35

VSS116

D15

AF15

E6

AA25

VCC30

VCC97

VSS36

VSS117

D17

AF17

E8

AB1

VCC31

VCC98

VSS37

VSS118

D18

AF18

E11

AB4

VCC32

VCC99

VSS38

VSS119

E7

AF20

E14

AB8

VCC33

VCC100

VSS39

VSS120

E9

E16

AB11

VCC34

VSS40

VSS121

E10

G21

E19

AB13

VCC35

VCCP1

+VCCP_CPU

VSS41

VSS122

E12

V6

E21

AB16

VCC36

VCCP2

VSS42

VSS123

E13

J6

E24

AB19

VCC37

VCCP3

VSS43

VSS124

E15

K6

F5

AB23

VCC38

VCCP4

VSS44

VSS125

E17

M6

F8

AB26

VCC39

VCCP5

VSS45

VSS126

E18

J21

F11

AC3

VCC40

VCCP6

VSS46

VSS127

E20

K21

F13

AC6

VCC41

VCCP7

+1.5VS

VSS47

VSS128

F7

M21

F16

AC8

VCC42

VCCP8

+VCCA_CPU

VSS48

VSS129

F9

N21

F19

AC11

VCC43

VCCP9

VSS49

VSS130

F10

N6

120 mA

R176

F2

AC14

VCC44

VCCP10

VSS50

VSS131

F12

R21

1

2

F22

AC16

VCC45

VCCP11

VSS51

VSS132

F14

R6

F25

AC19

VCC46

VCCP12

0Ohm

VSS52

VSS133

F15

T21

G4

AC21

VCC47

VCCP13

VSS53

VSS134

F17

T6

C295

C296

r0603_h24

G1

AC24

VCC48

VCCP14

VSS54

VSS135

F18

V21

G23

AD2

VCC49

VCCP15

VSS55

VSS136

F20

W21

0.1UF/25V

10UF/6.3V

G26

AD5

VCC50

VCCP16

VSS56

VSS137

AA7

H3

AD8

VCC51

VSS57

VSS138

AA9

B26

H6

AD11

VCC52

VCCA1

VSS58

VSS139

AA10

C26

H21

AD13

VCC53

VCCA2

GND

VSS59

VSS140

AA12

H24

AD16

VCC54

AD6 H_VID0

VSS60

VSS141

B

AA13

1

2

RN107A

J2

AD19

VCC55

VID[0]

0Ohm

VR_VID0

<55>

VSS61

VSS142

AA15

AF5

H_VID1

3

4

RN107B

J5

AD22

VCC56

VID[1]

0Ohm

VR_VID1

<55>

VSS62

VSS143

AA17

AE5

H_VID2

5

6

RN107C

J22

AD25

VCC57

VID[2]

0Ohm

VR_VID2

<55>

VSS63

VSS144

AA18

AF4

H_VID3

7

8

RN107D

J25

AE1

VCC58

VID[3]

0Ohm

VR_VID3

<55>

VSS64

VSS145

AA20

AE3

H_VID4

1

2

RN108A

K1

AE4

VCC59

VID[4]

0Ohm

VR_VID4

<55>

VSS65

VSS146

AB9

AF3

H_VID5

3

4

RN108B

K4

AE8

VCC60

VID[5]

0Ohm

VR_VID5

<55>

VSS66

VSS147

AC10

AE2

H_VID6

5

6

RN108C

K23

AE11

VCC61

VID[6]

0Ohm

VR_VID6

<55>

VSS67

VSS148

AB10

7

8

RN108D

K26

AE14

VCC62

0Ohm

VSS68

VSS149

AB12

L3

AE16

VCC63

VSS69

VSS150

AB14

AF7

1

2

L6

AE19

VCC64

VCCSENSE

+VCORE

VSS70

VSS151

AB15

R177

100Ohm 1%

L21

AE23

VCC65

VSS71

VSS152

AB17

L24

AE26

VCC66

VCCSENSE <55>

VSS72

VSS153

AB18

AE7

M2

A2

VCC67

VSSSENSE

VSSSENSE <55>

VSS73

VSS154

M5

AF6

VSS74

VSS155

SOCKET478B

M22

AF8

VSS75

VSS156

M25

AF11

R178

VCCSENSE, VSSSENSE trace at 27.4

VSS76

VSS157

12G010594786

N1

AF13

VSS77

VSS158

100Ohm

ohm with 50 mils spacing. Place PU

N4

AF16

VSS78

VSS159

1%

N23

AF19

and PD within 1" of CPU.

VSS79

VSS160

N26

AF21

VSS80

VSS161

P3

A25

VSS81

VSS162

AF25

VSS163

GND

SOCKET478B

GND

12G010594786

GND

A

1.1

Title : MEROM CPU (2)

ASUSTeK COMPUTER INC

Engineer:

Alan Chen

Size

Project Name

Rev

Custom

Z96S

2.0

Date:

,

30, 2007

Sheet

4

of

67

5

4

3

2

1

5

4

3

2

1

D

D

+VCORE

44A for Merom

+VCCP Decoupling Capacitor

+VCCP

(Place near CPU)

+VCCP_CPU

R179

C297

C298

C299

C300

C301

C302

C303

1

2

C

C

Do Not Stuff

Do Not Stuff

10UF/6.3V

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

0Ohm

+

/X

/X

/X

/X

/X

/X

r0805_h24

CE21

C307

C308

C309

C310

C311

C312

C313

Do Not Stuff

0.1UF/25V

Do Not Stuff

Do Not Stuff

10UF/6.3V

150UF/4V

X7R

X7R

X7R

X7R

X7R

X7R

0.1UF/25V

/X

/X

/X

0.1UF/25V

Decoupling guide from INTEL

GND

VCORE 22uF/10V

* 32pcs

330uF/2V

* 6pcs

VCCP

0.1uF

* 6pcs for CPU

C324

C325

C326

C130

C304

C305

C306

150uF

* 1pcs for CPU

10UF/6.3V

Do Not Stuff

10UF/6.3V

Do Not Stuff

10UF/6.3V

Do Not Stuff

Do Not Stuff

/X

/X

/X

/X

GND

B

B

A

A

			1.1
						Title :CPU CAP and HOLES
			ASUSTek COMPUTER INC. NB1			Engineer:	Alan Chen
			Size	Project Name					Rev
			Custom		Z96S				2.0
			Date:	,	30, 2007	Sheet	5	of	67
5	4	3	2			1

5

4

3

2

1

U2A

H_A#_3

J13

H_A#3

H_D#0

E2

B11

H_A#4

H_D#_0

H_A#_4

H_D#1

G2

C11

H_A#5

H_D#_1

H_A#_5

H_D#2

G7

M11

H_A#6

H_D#_2

H_A#_6

D

H_D#3

M6

C15

H_A#7

D

H_D#_3

H_A#_7

H_D#4

H7

F16

H_A#8

H_D#_4

H_A#_8

H_D#5

H3

L13

H_A#9

H_D#_5

H_A#_9

H_D#6

G4

G17

H_A#10

H_D#_6

H_A#_10

H_D#7

F3

C14

H_A#11

H_D#_7

H_A#_11

H_D#8

N8

K16

H_A#12

H_D#_8

H_A#_12

H_D#9

H2

B13

H_A#13

H_D#_9

H_A#_13

H_D#10

M10

L16

H_A#14

H_D#_10

H_A#_14

H_D#11

N12

J17

H_A#15

H_D#_11

H_A#_15

H_D#12

N9

B14

H_A#16

H_D#_12

H_A#_16

H_D#13

H5

K19

H_A#17

H_D#_13

H_A#_17

NR1

H_D#14

P13

P15

H_A#18

H_D#_14

H_A#_18

H_A#[35:3]

1

2

H_RCOMP

H_D#15

K9

R17

H_A#19

<3>

H_A#[35:3]

H_D#_15

H_A#_19

H_D#16

M2

B16

H_A#20

H_D#_16

H_A#_20

24.9Ohm

1%

H_D#17

W10

H20

H_A#21

H_D#_17

H_A#_21

H_REQ#[4:0]

H_D#18

Y8

L19

H_A#22

<3> H_REQ#[4:0]

H_D#_18

H_A#_22

H_D#19

V4

D17

H_A#23

H_D#_19

H_A#_23

H_D#20

M3

M17

H_A#24

H_D#_20

H_A#_24

H_D#[63:0]

H_D#21

J1

N16

H_A#25

<3>

H_D#[63:0]

H_D#_21

H_A#_25

GND

H_D#22

N5

J19

H_A#26

H_D#_22

H_A#_26

H_D#23

N3

B18

H_A#27

H_D#_23

H_A#_27

H_D#24

W6

E19

H_A#28

H_D#_24

H_A#_28

H_D#25

W9

B17

H_A#29

H_D#_25

H_A#_29

H_D#26

N2

B15

H_A#30

H_D#_26

H_A#_30

H_D#27

Y7

E17

H_A#31

H_D#_27

H_A#_31

H_D#28

Y9

C18

H_A#32

H_D#_28

H_A#_32

+VCCP

H_D#29

P4

A19

H_A#33

H_D#_29

H_A#_33

H_D#30

W3

B19

H_A#34

H_D#_30

H_A#_34

C

H_D#31

N1

N19

H_A#35

C

H_D#_31

H_A#_35

H_D#32

AD12

H_D#_32

H_D#33

AE3

G12

H_ADS#

H_D#_33

H_ADS#

H_ADS#

<3>

NR2

H_D#34

AD9

H17

H_ADSTB#0

H_D#_34

H_ADSTB#_0

H_ADSTB#0

<3>

2

1

H_SCOMP

H_D#35

AC9

G20

H_ADSTB#1

H_D#_35

H_ADSTB#_1

H_ADSTB#1

<3>

H_D#36

AC7

C8

H_BNR#

H_D#_36

H_BNR#

H_BNR#

<3>

54.9Ohm

1%

H_D#37

AC14

E8

H_BPRI#

H_D#_37

H_BPRI#

H_BPRI#

<3>

H_D#38

AD11

F12

H_BREQ#0

H_D#_38

H_BREQ#

H_BREQ#0

<3>

2

NR3

1

H_SCOMP#

H_D#39

AC11

D6

H_DEFER#

H_D#_39

H_DEFER#

H_DEFER#

<3>

H_D#40

AB2

C10

H_DBSY#

H_D#_40

H_DBSY#

H_DBSY#

<3>

54.9Ohm

1%

H_D#41

AD7

AM5

H_D#_41

HPLL_CLK

CLK_MCH_BCLK

<25>

H_D#42

AB1

AM7

H_D#_42

HPLL_CLK#

CLK_MCH_BCLK# <25>

H_D#43

Y3

H8

H_DPWR#

H_D#_43

H_DPWR#

H_DPWR#

<3>

H_D#44

AC6

K7

H_DRDY#

H_D#_44

H_DRDY#

H_DRDY#

<3>

+VCCP

H_D#45

AE2

E4

H_D#_45

H_HIT#

H_HIT#

<3>

H_D#46

AC5

C6

H_D#_46

H_HITM#

H_HITM#

<3>

H_D#47

AG3

G10

H_D#_47

H_LOCK#

H_LOCK#

<3>

H_D#48

AJ9

B7

H_D#_48

H_TRDY#

H_TRDY#

<3>

NR4

H_D#49

AH8

H_D#_49

221Ohm

H_D#50

AJ14

H_D#_50

H_D#51

AE9

H_D#_51

H_D#52

AE11

H_D#_52

H_D#53

AH12

K5

H_D#_53

H_DINV#_0

H_DINV#0

<3>

H_SWING

H_D#54

AJ5

L2

H_D#_54

H_DINV#_1

H_DINV#1

<3>

H_D#55

AH5

AD13

H_D#_55

H_DINV#_2

H_DINV#2

<3>

H_D#56

AJ6

AE13

H_D#_56

H_DINV#_3

H_DINV#3

<3>

NR5

H_D#57

AE7

H_D#_57

100Ohm

NC1

H_D#58

AJ7

M7

H_D#_58

H_DSTBN#_0

H_DSTBN#0

<3>

1%

0.1UF/10V

H_D#59

AJ2

K3

B

H_D#_59

H_DSTBN#_1

H_DSTBN#1

<3>

B

H_D#60

AE5

AD2

H_D#_60

H_DSTBN#_2

H_DSTBN#2

<3>

H_D#61

AJ3

AH11

H_D#_61

H_DSTBN#_3

H_DSTBN#3

<3>

H_D#62

AH2

H_D#_62

H_D#63

AH13

L7

GND

GND

H_D#_63

H_DSTBP#_0

H_DSTBP#0

<3>

K2

H_DSTBP#_1

H_DSTBP#1

<3>

AC2

H_SWING

H_DSTBP#_2

H_DSTBP#2

<3>

B3

AJ10

H_SWING

H_DSTBP#_3

H_DSTBP#3 <3>

H_RCOMP

C2

H_RCOMP

H_REQ#0

M14

H_REQ#_0

H_SCOMP

W1

E13

H_REQ#1

H_SCOMP

H_REQ#_1

H_SCOMP#

W2

A11

H_REQ#2

H_SCOMP#

H_REQ#_2

H13

H_REQ#3

H_REQ#_3

B6

B12

H_REQ#4

<3,30> H_CPURST#

H_CPURST#

H_REQ#_4

2

1

E5

<3> H_CPUSLP#

H_CPUSLP#

H_RS#0

NR6

0Ohm

E12

H_RS#_0

H_RS#0

<3>

D7

H_RS#1

+VCCP

H_RS#_1

H_RS#1

<3>

D8

H_RS#2

H_RS#_2

H_RS#2

<3>

B9

H_AVREF

A9

H_DVREF

NR7

CRESTLINE_965PM

1KOhm

1%

H_VREF

NC2

A

NR8

A

0.1UF/10V

2KOhm

1%

1.1

GND

GND

Title :965PM -- CPU (1)

ASUSTeK COMPUTER INC

Engineer:

Alan Chen

Size

Project Name

Rev

Custom

Z96S

2.0

Date:

,

30, 2007

Sheet

6

of

67

5

4

3

2

1

5

4

3

2

1

+1.8V

U2B

+VCCP

+1.25VS

P36

RSVD1

P37

AV29

RSVD2

SM_CK_0

DCLK0

<16>

R35

BB23

NR9

RSVD3

SM_CK_1

DCLK1

<16>

NR10

NR11

N35

BA25

RSVD4

SM_CK_3

DCLK2

<17>

1KOhm

AR12

AV23

24.9Ohm Do Not Stuff

RSVD5

SM_CK_4

DCLK3

<17>

AR13

U2C

1%

1%

RSVD6

AM12

AW30

/X

SM_RCOMP_VOH

RSVD7

SM_CK#_0

DCLK0#

<16>

AN13

BA23

J40

RSVD8

SM_CK#_1

DCLK1#

<16>

L_BKLT_CTRL

J12

AW25

H39

N43

NC3

NC4

RSVD9

SM_CK#_3

DCLK2#

<17>

L_BKLT_EN

PEG_COMPI

AR37

AW23

E39

M43

RSVD10

SM_CK#_4

DCLK3#

<17>

L_CTRL_CLK

PEG_COMPO

D

2.2UF/6.3V

0.01UF/16V

AM36

E40

D

RSVD11

L_CTRL_DATA

AL36

BE29

C37

RSVD12

SM_CKE_0

SCKE0

<16,18>

L_DDC_CLK

PEG_RXN0

PEG_RXN[0..15]

<22>

NR13

AM37

AY32

D35

J51

RSVD13

SM_CKE_1

SCKE1

<16,18>

L_DDC_DATA

PEG_RX#_0

3.01KOHM

D20

BD39

K40

L51

PEG_RXN1

RSVD14

SM_CKE_3

SCKE2

<17,18>

L_VDD_EN

PEG_RX#_1

BG37

N47

PEG_RXN2

SM_CKE_4

SCKE3

<17,18>

PEG_RX#_2

L41

T45

PEG_RXN3

LVDS_IBG

PEG_RX#_3

BG20

L43

T50

PEG_RXN4

SM_CS#_0

SCS0#

<16,18>

LVDS_VBG

PEG_RX#_4

GND

BK16

N41

U40

PEG_RXN5

SM_CS#_1

SCS1#

<16,18>

LVDS_VREFH

PEG_RX#_5

SM_RCOMP_VOL

BG16

N40

Y44

PEG_RXN6

SM_CS#_2

SCS2#

<17,18>

LVDS_VREFL

PEG_RX#_6

H10

BE13

D46

Y40

PEG_RXN7

RSVD20

SM_CS#_3

SCS3#

<17,18>

LVDSA_CLK#

PEG_RX#_7

B51

C45

AB51

PEG_RXN8

RSVD21

LVDSA_CLK

PEG_RX#_8

NC5

NC6

BJ20

BH18

D44

W49

PEG_RXN9

RSVD22

SM_ODT_0

ODT0

<16,18>

LVDSB_CLK#

PEG_RX#_9

NR14

2.2UF/6.3V

0.01UF/16V

BK22

BJ15

E42

AD44

PEG_RXN10

RSVD23

SM_ODT_1

ODT1

<16,18>

LVDSB_CLK

PEG_RX#_10

1KOhm

BF19

BJ14

AD40

PEG_RXN11

RSVD24

SM_ODT_2

ODT2

<17,18>

+1.8V

PEG_RX#_11

BH20

BE16

G51

AG46

PEG_RXN12

RSVD25

SM_ODT_3

ODT3

<17,18>

LVDSA_DATA#_0

PEG_RX#_12

BK18

E51

AH49

PEG_RXN13

RSVD26

LVDSA_DATA#_1

PEG_RX#_13

BJ18

BL15

NR15 1

20Ohm

2

1%

F49

AG45

PEG_RXN14

RSVD27

SM_RCOMP

LVDSA_DATA#_2

PEG_RX#_14

BF23

BK14

NR16 1

20Ohm

2

1%

AG41

PEG_RXN15

RSVD28

SM_RCOMP#

PEG_RX#_15

GND

GND

BG23

RSVD29

SM_RCOMP_VOH

PEG_RXP0

PEG_RXP[0..15]

<22>

BC23

BK31

G50

J50

RSVD30

SM_RCOMP_VOH

LVDSA_DATA_0

PEG_RX_0

BD24

BL31

SM_RCOMP_VOL

GND

E50

L50

PEG_RXP1

RSVD31

SM_RCOMP_VOL

LVDSA_DATA_1

PEG_RX_1

BJ29

VTT_REF

F48

M47

PEG_RXP2

RSVD32

LVDSA_DATA_2

PEG_RX_2

BE24

AR49

U44

PEG_RXP3

RSVD33

SM_VREF_0

PEG_RX_3

BH39

AW4

T49

PEG_RXP4

RSVD34

SM_VREF_1

PEG_RX_4

AW20

NC7

NC8

G44

T41

PEG_RXP5

RSVD35

LVDSB_DATA#_0

PEG_RX_5

BK20

0.01UF/16V

B47

W45

PEG_RXP6

RSVD36

LVDSB_DATA#_1

PEG_RX_6

C48

2.2UF/6.3V

B45

W41

PEG_RXP7

RSVD37

LVDSB_DATA#_2

PEG_RX_7

D47

B42

DREFCLK

AB50

PEG_RXP8

RSVD38

DPLL_REF_CLK

PEG_RX_8

C

B44

C42 DREFCLK#

Y48

PEG_RXP9

C

RSVD39

DPLL_REF_CLK#

PEG_RX_9

C44

H48

1

E44

AC45

PEG_RXP10

RSVD40

DPLL_REF_SSCLK

LVDSB_DATA_0

PEG_RX_10

A35

H47

1

T143

A47

AC41

PEG_RXP11

RSVD41

DPLL_REF_SSCLK#

LVDSB_DATA_1

PEG_RX_11

B37

T144

GND

A45

AH47

PEG_RXP12

RSVD42

LVDSB_DATA_2

PEG_RX_12

B36

K44

AG49

PEG_RXP13

RSVD43

PEG_CLK

CLK_MCH_3GPLL <25>

PEG_RX_13

+1.25VS

B34

K45

AH45

PEG_RXP14

RSVD44

PEG_CLK#

CLK_MCH_3GPLL#

<25>

PEG_RX_14

C34

AG42

PEG_RXP15

NR17

RSVD45

PEG_RX_15

10KOhm DREFCLK

E27

TVA_DAC

PEG_TX#_0

N45

C_PEG_TXN0

1

2

PEG_TXN0

10KOhm DREFCLK#

AN47

G27

U39

C_PEG_TXN1NC9

0.1UF/16V

2

PEG_TXN1

DMI_RXN_0

DMI_TXN0 <13>

TVB_DAC

PEG_TX#_1

AJ38

K27

U47

C_PEG_TXN2

1

2

NC10

0.1UF/16V

PEG_TXN2

DMI_RXN_1

DMI_TXN1 <13>

TVC_DAC

PEG_TX#_2

NR18

AN42

N51

C_PEG_TXN3 NC11

0.1UF/16V

2

PEG_TXN3

DMI_RXN_2

DMI_TXN2 <13>

PEG_TX#_3

AN46

F27

R50

C_PEG_TXN4

1

2

NC12

0.1UF/16V

PEG_TXN4

DMI_RXN_3

DMI_TXN3 <13>

TVA_RTN

PEG_TX#_4

GND

J27

T42

C_PEG_TXN5 NC13

0.1UF/16V

2

PEG_TXN5

TVB_RTN

PEG_TX#_5

AM47

L27

Y43

C_PEG_TXN6

1

2

NC14

0.1UF/16V

PEG_TXN6

DMI_RXP_0

DMI_TXP0 <13>

TVC_RTN

PEG_TX#_6

P27

AJ39

W46

C_PEG_TXN7 NC15

0.1UF/16V

2

PEG_TXN7

<25> MCH_BSEL0

CFG_0

DMI_RXP_1

DMI_TXP1 <13>

PEG_TX#_7

N27

AN41

M35

W38

C_PEG_TXN8

1

2

NC16

0.1UF/16V

PEG_TXN8

<25> MCH_BSEL1

CFG_1

DMI_RXP_2

DMI_TXP2 <13>

TV_DCONSEL_0

PEG_TX#_8

N24

AN45

P33

AD39C_PEG_TXN9 NC17

0.1UF/16V

2

PEG_TXN9

<25> MCH_BSEL2

CFG_2

DMI_RXP_3

DMI_TXP3 <13>

TV_DCONSEL_1

PEG_TX#_9

T145

1

C21

AC46C_PEG_TXN10 1

2

NC18

0.1UF/16V

PEG_TXN10

CFG_3

PEG_TX#_10

T146

1

C23

AJ46

AC49C_PEG_TXN11NC19

0.1UF/16V

2

PEG_TXN11

CFG_4

DMI_TXN_0

DMI_RXN0

<13>

PEG_TX#_11

F23

AJ41

GND

AC42C_PEG_TXN12 1

2

NC20

0.1UF/16V

PEG_TXN12

<11> MCH_CFG_5

CFG_5

DMI_TXN_1

DMI_RXN1

<13>

PEG_TX#_12

T147

1

N23

AM40

AH39C_PEG_TXN13NC21

0.1UF/16V

2

PEG_TXN13

CFG_6

DMI_TXN_2

DMI_RXN2

<13>

PEG_TX#_13

G23

AM44

AE49 C_PEG_TXN14 1

2

NC22

0.1UF/16V

PEG_TXN14

<11> MCH_CFG_7

CFG_7

DMI_TXN_3

DMI_RXN3

<13>

PEG_TX#_14

T148

1

J20

AH44C_PEG_TXN15NC23

0.1UF/16V

2

PEG_TXN15

CFG_8

PEG_TX#_15

C20

AJ47

NC24

0.1UF/16V

<11> MCH_CFG_9

T149

CFG_9

DMI_TXP_0

DMI_RXP0 <13>

M45 C_PEG_TXP0

PEG_TXP0

1

R24

AJ42

H32

1

2

CFG_10

DMI_TXP_1

DMI_RXP1 <13>

CRT_BLUE

PEG_TX_0

T150

1

L23

AM39

G32

T38

C_PEG_TXP1 NC25

0.1UF/16V

2

PEG_TXP1

CFG_11

DMI_TXP_2

DMI_RXP2 <13>

CRT_BLUE#

PEG_TX_1

J23

AM43

K29

T46

C_PEG_TXP2

1

2

NC26

0.1UF/16V

PEG_TXP2

<11> MCH_CFG_12

CFG_12

DMI_TXP_3

DMI_RXP3 <13>

CRT_GREEN

PEG_TX_2

E23

J29

N50

C_PEG_TXP3 NC27

0.1UF/16V

2

PEG_TXP3

B

<11> MCH_CFG_13

CFG_13

CRT_GREEN#

PEG_TX_3

B

T151

1

E20

F29

R51

C_PEG_TXP4

1

2

NC28

0.1UF/16V

PEG_TXP4

CFG_14

CRT_RED

PEG_TX_4

T152

1

K23

E29

U43

C_PEG_TXP5 NC29

0.1UF/16V

2

PEG_TXP5

CFG_15

CRT_RED#

PEG_TX_5

M20

W42

C_PEG_TXP6

1

2

NC30

0.1UF/16V

PEG_TXP6

<11> MCH_CFG_16

CFG_16

PEG_TX_6

T153

1

M24

Y47

C_PEG_TXP7 NC31

0.1UF/16V

2

PEG_TXP7

CFG_17

PEG_TX_7

T154

1

L32

GND

K33

Y39

C_PEG_TXP8

1

2

NC32

0.1UF/16V

PEG_TXP8

CFG_18

CRT_DDC_CLK

PEG_TX_8

N33

G35

AC38C_PEG_TXP9 NC33

0.1UF/16V

2

PEG_TXP9

<11> MCH_CFG_19

CFG_19

CRT_DDC_DATA

PEG_TX_9

L35

F33

AD47C_PEG_TXP10 1

2

NC34

0.1UF/16V

PEG_TXP10

<11> MCH_CFG_20

CFG_20

CRT_HSYNC

PEG_TX_10

C32

AC50C_PEG_TXP11NC35

0.1UF/16V

2

PEG_TXP11

CRT_TVO_IREF

PEG_TX_11

E33

AD43C_PEG_TXP12 1

2

NC36

0.1UF/16V

PEG_TXP12

CRT_VSYNC

PEG_TX_12

E35

DFGT_VID_0

1

T63

AG39C_PEG_TXP13NC37

0.1UF/16V

2

PEG_TXP13

GFX_VID_0

PEG_TX_13

G41

A39

DFGT_VID_1

1

T64

NR19

AE50 C_PEG_TXP14 1

2

NC38

0.1UF/16V

PEG_TXP14

<14> PM_BMBUSY#

PM_BM_BUSY#

GFX_VID_1

PEG_TX_14

L39

C38

DFGT_VID_2

1

T65

AH43C_PEG_TXP15NC39

0.1UF/16V

2

PEG_TXP15

<3,12> H_DPRSTP#

PM_EXTTS#0

PM_DPRSTP#

GFX_VID_2

1.3KOhm

PEG_TX_15

L36

B39

DFGT_VID_3

1

T66

NC40

0.1UF/16V

<14> PM_EXTTS#0

PM_EXT_TS#_0

GFX_VID_3

PM_EXTTS#1

J36

E36

VCCGFX_EN

1

T67

<14> PM_EXTTS#1

PM_EXT_TS#_1

GFX_VR_EN

PWROK

AW49

CRESTLINE_965PM

VRM_PWRGD

PWROK

NR20

0Ohm

1

100Ohm 2 1% AV20

ICH8_PWROK

RSTIN#

CL_CLK0

<14>

NR21

N20

NR22

/X

Do Not Stuff

THERMTRIP#

CL_DATA0

<14>

GND

G36

DPRSLPVR

NR23 2 VRM_PWRGD

0Ohm 1

VRM_PWRGD

<14,44,55,63>

AM49

ICH8_PWROK

CL_CLK

ICH8_PWROK

<14,44>

AK50

Do Not StuffNR24

CL_DATA

BJ51

AT43

/X

,14,22,31,36,40,44,51,53>

BUF_PLT_RST#

NC_1

CL_PWROK

BK51

AN49

NC_2

CL_RST#

CL_RST#

<14>

CL_VREF0

BK50

AM50

<3,12> PM_THRMTRIP#

NC_3

CL_VREF

+1.25VS

BL50

<14,55> PM_DPRSLPVR

NC_4

+3VS

NC41

BL49

PEG_TXN[15:0] <22>

NC_5

BL3

0.1UF/16V

NC_6

BL2

A

+3VS

NC_7

A

BK1

NC_8

NR25

NR26

BJ1

H35

PM_EXTTS#0

NC_9

SDVO_CTRL_CLK

PEG_TXP[15:0] <22>

NR27

2

1

10KOhm

E1

K36

10KOhm

1KOhm

NC_10

SDVO_CTRL_DATA

A5

G39

GND

PM_EXTTS#1

NC_11

CLK_REQ#

1.1

NR28

2

1

10KOhm

C51

G40

NC_12

ICH_SYNC#

MCH_SYNC#

<14>

B50

NC_13

Title :

A50

965PM--DDR2/PEG (2)

NC_14

A37

GND

NR30

NR29

A49

NC_15

TEST_1

BK2

R32

1

2

392Ohm

Engineer:

Alan Chen

NC_16

TEST_2

ASUSTeK COMPUTER INC

CRESTLINE_965PM

20KOhm

Size

Project Name

Rev

Custom

Z96S

2.0

GND

GND

Date:

,

30, 2007

Sheet

7

of

67

5

4

3

2

1

5

4

3

2

1

D

<16>

M_A_DQ[0:63]

D

U2D

<17>

M_B_DQ[0:63]

M_A_DQ0

AR43

BB19

U2E

SA_DQ_0

SA_BS_0

M_A_BS#0

<16,18>

M_A_DQ1

AW44

BK19

M_B_DQ0

AP49

AY17

SA_DQ_1

SA_BS_1

M_A_BS#1

<16,18>

SB_DQ_0

SB_BS_0

M_B_BS#0

<17,18>

M_A_DQ2

BA45

BF29

M_B_DQ1

AR51

BG18

SA_DQ_2

SA_BS_2

M_A_BS#2

<16,18>

SB_DQ_1

SB_BS_1

M_B_BS#1

<17,18>

M_A_DQ3

AY46

M_B_DQ2

AW50

BG36

SA_DQ_3

M_A_CAS#

<16,18>

SB_DQ_2

SB_BS_2

M_B_BS#2

<17,18>

M_A_DQ4

AR41

BL17

M_B_DQ3

AW51

SA_DQ_4

SA_CAS#

SB_DQ_3

M_B_CAS#

<17,18>

M_A_DQ5

AR45

M_B_DQ4

AN51

BE17

SA_DQ_5

M_A_DM[0..7]

<16>

SB_DQ_4

SB_CAS#

M_A_DQ6

AT42

AT45 M_A_DM0

M_B_DQ5

AN50

SA_DQ_6

SA_DM_0

SB_DQ_5

M_B_DM[0:7] <17>

M_A_DQ7

AW47

BD44

M_A_DM1

M_B_DQ6

AV50

AR50 M_B_DM0

SA_DQ_7

SA_DM_1

SB_DQ_6

SB_DM_0

M_A_DQ8

BB45

BD42

M_A_DM2

M_B_DQ7

AV49

BD49

M_B_DM1

SA_DQ_8

SA_DM_2

SB_DQ_7

SB_DM_1

M_A_DQ9

BF48

AW38

M_A_DM3

M_B_DQ8

BA50

BK45

M_B_DM2

SA_DQ_9

SA_DM_3

SB_DQ_8

SB_DM_2

M_A_DQ10

BG47

AW13

M_A_DM4

M_B_DQ9

BB50

BL39

M_B_DM3

SA_DQ_10

SA_DM_4

SB_DQ_9

SB_DM_3

M_A_DQ11

BJ45

BG8

M_A_DM5

M_B_DQ10

BA49

BH12

M_B_DM4

SA_DQ_11

SA_DM_5

SB_DQ_10

SB_DM_4

M_A_DQ12

BB47

AY5

M_A_DM6

M_B_DQ11

BE50

BJ7

M_B_DM5

SA_DQ_12

SA_DM_6

SB_DQ_11

SB_DM_5

M_A_DQ13

BG50

AN6

M_A_DM7

M_B_DQ12

BA51

BF3

M_B_DM6

SA_DQ_13

SA_DM_7

SB_DQ_12

SB_DM_6

M_A_DQ14

BH49

M_B_DQ13

AY49

AW2

M_B_DM7

SA_DQ_14

M_A_DQS[0:7]

<16>

SB_DQ_13

SB_DM_7

M_A_DQ15

BE45

AT46 M_A_DQS0

M_B_DQ14

BF50

SA_DQ_15

SA_DQS_0

SB_DQ_14

M_B_DQS[0:7] <17>

M_A_DQ16

AW43

BE48

M_A_DQS1

M_B_DQ15

BF49

AT50 M_B_DQS0

SA_DQ_16

SA_DQS_1

SB_DQ_15

SB_DQS_0

M_A_DQ17

BE44

BB43

M_A_DQS2

M_B_DQ16

BJ50

BD50

M_B_DQS1

SA_DQ_17

SA_DQS_2

SB_DQ_16

SB_DQS_1

M_A_DQ18

BG42

BC37

M_A_DQS3

M_B_DQ17

BJ44

BK46

M_B_DQS2

SA_DQ_18

SA_DQS_3

SB_DQ_17

SB_DQS_2

M_A_DQ19

BE40

BB16

M_A_DQS4

M_B_DQ18

BJ43

BK39

M_B_DQS3

SA_DQ_19

SA_DQS_4

SB_DQ_18

SB_DQS_3

M_A_DQ20

BF44

BH6

M_A_DQS5

M_B_DQ19

BL43

BJ12

M_B_DQS4

SA_DQ_20

SA_DQS_5

SB_DQ_19

SB_DQS_4

M_A_DQ21

BH45

BB2

M_A_DQS6

M_B_DQ20

BK47

BL7

M_B_DQS5

SA_DQ_21

SA_DQS_6

SB_DQ_20

SB_DQS_5

M_A_DQ22

BG40

AP3

M_A_DQS7

M_B_DQ21

BK49

BE2

M_B_DQS6

SA_DQ_22

SA_DQS_7

M_A_DQS#[0:7] <16>

SB_DQ_21

SB_DQS_6

M_A_DQ23

BF40

AT47

M_A_DQS#0

M_B_DQ22

BK43

AV2

M_B_DQS7

SA_DQ_23

SA_DQS#_0

SB_DQ_22

SB_DQS_7

M_B_DQS#[0:7] <17>

M_A_DQ24

AR40

BD47

M_A_DQS#1

M_B_DQ23

BK42

AU50

M_B_DQS#0

SA_DQ_24

SA_DQS#_1

SB_DQ_23

SB_DQS#_0

M_A_DQ25

AW40

BC41

M_A_DQS#2

M_B_DQ24

BJ41

BC50

M_B_DQS#1

SA_DQ_25

SA_DQS#_2

SB_DQ_24

SB_DQS#_1

C

M_A_DQ26

AT39

BA37

M_A_DQS#3

M_B_DQ25

BL41

BL45

M_B_DQS#2

C

SA_DQ_26

SA_DQS#_3

SB_DQ_25

SB_DQS#_2

M_A_DQ27

AW36

BA16

M_A_DQS#4

M_B_DQ26

BJ37

BK38

M_B_DQS#3

SA_DQ_27

SA_DQS#_4

SB_DQ_26

SB_DQS#_3

M_A_DQ28

AW41

BH7

M_A_DQS#5

M_B_DQ27

BJ36

BK12

M_B_DQS#4

SA_DQ_28

SA_DQS#_5

SB_DQ_27

SB_DQS#_4

M_A_DQ29

AY41

BC1

M_A_DQS#6

M_B_DQ28

BK41

BK7

M_B_DQS#5

SA_DQ_29

SA_DQS#_6

SB_DQ_28

SB_DQS#_5

M_A_DQ30

AV38

AP2

M_A_DQS#7

M_B_DQ29

BJ40

BF2

M_B_DQS#6

SA_DQ_30

SA_DQS#_7

SB_DQ_29

SB_DQS#_6

M_A_DQ31

AT38

M_B_DQ30

BL35

AV3

M_B_DQS#7

SA_DQ_31

M_A_A[0:13] <16,18>

SB_DQ_30

SB_DQS#_7

M_A_DQ32

AV13

BJ19 M_A_A0

M_B_DQ31

BK37

SA_DQ_32

SA_MA_0

SB_DQ_31

M_B_A[0:13] <17,18>

M_A_DQ33

AT13

BD20

M_A_A1

M_B_DQ32

BK13

BC18 M_B_A0

SA_DQ_33

SA_MA_1

SB_DQ_32

SB_MA_0

M_A_DQ34

AW11

BK27

M_A_A2

M_B_DQ33

BE11

BG28

M_B_A1

SA_DQ_34

SA_MA_2

SB_DQ_33

SB_MA_1

M_A_DQ35

AV11

BH28

M_A_A3

M_B_DQ34

BK11

BG25

M_B_A2

SA_DQ_35

SA_MA_3

SB_DQ_34

SB_MA_2

M_A_DQ36

AU15

BL24

M_A_A4

M_B_DQ35

BC11

AW17

M_B_A3

SA_DQ_36

SA_MA_4

SB_DQ_35

SB_MA_3

M_A_DQ37

AT11

BK28

M_A_A5

M_B_DQ36

BC13

BF25

M_B_A4

SA_DQ_37

SA_MA_5

SB_DQ_36

SB_MA_4

M_A_DQ38

BA13

BJ27

M_A_A6

M_B_DQ37

BE12

BE25

M_B_A5

SA_DQ_38

SA_MA_6

SB_DQ_37

SB_MA_5

M_A_DQ39

BA11

BJ25

M_A_A7

M_B_DQ38

BC12

BA29

M_B_A6

SA_DQ_39

SA_MA_7

SB_DQ_38

SB_MA_6

M_A_DQ40

BE10

BL28

M_A_A8

M_B_DQ39

BG12

BC28

M_B_A7

SA_DQ_40

SA_MA_8

SB_DQ_39

SB_MA_7

M_A_DQ41

BD10

BA28

M_A_A9

M_B_DQ40

BJ10

AY28

M_B_A8

SA_DQ_41

SA_MA_9

SB_DQ_40

SB_MA_8

M_A_DQ42

BD8

BC19

M_A_A10

M_B_DQ41

BL9

BD37

M_B_A9

SA_DQ_42

SA_MA_10

SB_DQ_41

SB_MA_9

M_A_DQ43

AY9

BE28

M_A_A11

M_B_DQ42

BK5

BG17

M_B_A10

SA_DQ_43

SA_MA_11

SB_DQ_42

SB_MA_10

M_A_DQ44

BG10

BG30

M_A_A12

M_B_DQ43

BL5

BE37

M_B_A11

SA_DQ_44

SA_MA_12

SB_DQ_43

SB_MA_11

M_A_DQ45

AW9

BJ16

M_A_A13

M_B_DQ44

BK9

BA39

M_B_A12

SA_DQ_45

SA_MA_13

SB_DQ_44

SB_MA_12

M_A_DQ46

BD7

M_B_DQ45

BK10

BG13

M_B_A13

SA_DQ_46

SB_DQ_45

SB_MA_13

M_A_DQ47

BB9

M_B_DQ46

BJ8

SA_DQ_47

SB_DQ_46

M_A_DQ48

BB5

BE18

M_B_DQ47

BJ6

AV16

SA_DQ_48

SA_RAS#

M_A_RAS#

<16,18>

SB_DQ_47

SB_RAS#

M_B_RAS#

<17,18>

M_A_DQ49

AY7

AY20

1

T155

M_B_DQ48

BF4

AY18

1

T156

SA_DQ_49

SA_RCVEN#

SB_DQ_48

SB_RCVEN#

M_A_DQ50

AT5

M_B_DQ49

BH5

SA_DQ_50

SB_DQ_49

M_A_DQ51

AT7

BA19

M_B_DQ50

BG1

BC17

SA_DQ_51

SA_WE#

M_A_WE#

<16,18>

SB_DQ_50

SB_WE#

M_B_WE#

<17,18>

M_A_DQ52

AY6

M_B_DQ51

BC2

SA_DQ_52

SB_DQ_51

M_A_DQ53

BB7

M_B_DQ52

BK3

SA_DQ_53

SB_DQ_52

M_A_DQ54

AR5

M_B_DQ53

BE4

B

SA_DQ_54

SB_DQ_53

B

M_A_DQ55

AR8

M_B_DQ54

BD3

SA_DQ_55

SB_DQ_54

M_A_DQ56

AR9

M_B_DQ55

BJ2

SA_DQ_56

SB_DQ_55

M_A_DQ57

AN3

M_B_DQ56

BA3

SA_DQ_57

SB_DQ_56

M_A_DQ58

AM8

M_B_DQ57

BB3

SA_DQ_58

SB_DQ_57

M_A_DQ59

AN10

M_B_DQ58

AR1

SA_DQ_59

SB_DQ_58

M_A_DQ60

AT9

M_B_DQ59

AT3

SA_DQ_60

SB_DQ_59

M_A_DQ61

AN9

M_B_DQ60

AY2

SA_DQ_61

SB_DQ_60

M_A_DQ62

AM9

M_B_DQ61

AY3

SA_DQ_62

SB_DQ_61

M_A_DQ63

AN11

M_B_DQ62

AU2

SA_DQ_63

SB_DQ_62

M_B_DQ63

AT2

CRESTLINE_965PM

SB_DQ_63

CRESTLINE_965PM

A

A

1.1

Title :965PM--DDR2 bus (3)

ASUSTeK COMPUTER INC

Engineer:

Alan Chen

Size

Project Name

Rev

Custom

Z96S

2.0

Date:

,

30, 2007

Sheet

8

of

67

5

4

3

2

1

5

4

3

2

1

1310 mA for External GFX

+VCC_GMCH

U2G

+VCCGFX

AT35

VCC_1

AT34

T17

VCC_2

VCC_AXG_NCTF_1

+VCCP

AH28

T18

VCC_3

VCC_AXG_NCTF_2

+VCC_GMCH

AC32

T19

U2F

VCC_5

VCC_AXG_NCTF_3

AC31

T21

VCC_4

VCC_AXG_NCTF_4

AK32

T22

AB33

VCC_6

VCC_AXG_NCTF_5

VCC_NCTF_1

AJ31

T23

AB36

VCC_7

VCC_AXG_NCTF_6

VCC_NCTF_2

AJ28

T25

+

AB37

VCC_8

VCC_AXG_NCTF_7

VCC_NCTF_3

D

AH32

U15

NCE1

AC33

T27

D

VCC_9

VCC_AXG_NCTF_8

VCC_NCTF_4

VSS_NCTF_1

AH31

U16

NC42

NC43

NC44

NC45

AC35

T37

VCC_10

VCC_AXG_NCTF_9

Do Not Stuff

VCC_NCTF_5

VSS_NCTF_2

AH29

U17

22UF/6.3V

Do Not Stuff

Do Not Stuff

0.1UF/10V

AC36

U24

AF32

VCC_11

VCC_AXG_NCTF_10

U19

/X

/X

/X

AD35

VCC_NCTF_6

VSS_NCTF_3

U28

VCC_12

VCC_AXG_NCTF_11

VCC_NCTF_7

VSS_NCTF_4

U20

AD36

V31

VCC_AXG_NCTF_12

VCC_NCTF_8

VSS_NCTF_5

U21

AF33

V35

VCC_AXG_NCTF_13

VCC_NCTF_9

VSS_NCTF_6

U23

AF36

AA19

VCC_AXG_NCTF_14

GND

VCC_NCTF_10

VSS_NCTF_7

R30

U26

AH33

AB17

VCC_13

VCC_AXG_NCTF_15

VCC_NCTF_11

VSS_NCTF_8

V16

AH35

AB35

VCC_AXG_NCTF_16

+VCCP

VCC_NCTF_12

VSS_NCTF_9

V17

AH36

AD19

VCC_AXG_NCTF_17

+VCCGFX

VCC_NCTF_13

VSS_NCTF_10

V19

AH37

AD37

VCC_AXG_NCTF_18

VCC_NCTF_14

VSS_NCTF_11

V20

AJ33

AF17

VCC_AXG_NCTF_19

VCC_NCTF_15

VSS_NCTF_12

V21

AJ35

AF35

VCC_AXG_NCTF_20

VCC_NCTF_16

VSS_NCTF_13

V23

AK33

AK17

VCC_AXG_NCTF_21

VCC_NCTF_17

VSS_NCTF_14

3138 mA

V24

AK35

AM17

VCC_AXG_NCTF_22

VCC_NCTF_18

VSS_NCTF_15

+1.8V_GMCH

POWER

VCC_AXG_NCTF_23

Y15

AK36

VCC_NCTF_19

VSS_NCTF_16

AM24

Y16

AK37

AP26

VCC_AXG_NCTF_24

Y17

AD33

VCC_NCTF_20

VSS_NCTF_17

AP28

VCC_AXG_NCTF_25

VCC_NCTF_21

VSS_NCTF_18

AU32

Y19

AJ36

AR15

VCC_SM_1

VCC_AXG_NCTF_26

NC46

NC47

NC48

NC49

NC50

NC51

VCC_NCTF_22

VSS_NCTF_19

AU33

Y20

AM35

AR19

VCC_SM_2

VCC_AXG_NCTF_27

VCC_NCTF_23

VSS_NCTF_20

AU35

Y21

0.22UF/6.3V

Do Not Stuff

10UF/10V

Do Not Stuff

0.1UF/10V

Do Not Stuff

AL33

AR28

VCC_SM_3

VCC_AXG_NCTF_28

VCC_NCTF_24

VSS_NCTF_21

AV33

Y23

/X

/X

/X

AL35

VCC_SM_4

VCC_AXG_NCTF_29

VCC_NCTF_25

AW33

Y24

AA33

VCC_SM_5

VCC_AXG_NCTF_30

VCC_NCTF_26

AW35

Y26

AA35

VCC_SM_6

VCC_AXG_NCTF_31

VCC_NCTF_27

AY35

Y28

AA36

VCC_SM_7

VCC_AXG_NCTF_32

VCC_NCTF_28

BA32

Y29

AP35

VCC_SM_8

VCC_AXG_NCTF_33

VCC_NCTF_29

BA33

AA16

GND

AP36

VCC_SM_9

VCC_AXG_NCTF_34

VCC_NCTF_30

BA35

AA17

AR35

VCC_SM_10

VCC_AXG_NCTF_35

VCC_NCTF_31

C

BB33

AB16

AR36

C

VCC_SM_11

VCC_AXG_NCTF_36

VCC_NCTF_32

BC32

AB19

Y32

VCC_SM_12

VCC_AXG_NCTF_37

VCC_NCTF_33

BC33

AC16

Y33

VCC_SM_13

VCC_AXG_NCTF_38

VCC_NCTF_34

POWER

BC35

AC17

Y35

BD32

VCC_SM_14

VCC_AXG_NCTF_39

AC19

Y36

VCC_NCTF_35

VCC_SM_15

VCC_AXG_NCTF_40

VCC_NCTF_36

BD35

AD15

Y37

A3

VCC_SM_16

VCC_AXG_NCTF_41

VCC_NCTF_37

VSS_SCB1

BE32

AD16

T30

B2

VCC_SM_17

VCC_AXG_NCTF_42

+1.8V

+1.8V_GMCH

VCC_NCTF_38

VSS_SCB2

BE33

AD17

T34

C1

VCC_SM_18

VCC_AXG_NCTF_43

VCC_NCTF_39

VSS_SCB3

BE35

AF16

T35

BL1

VCC_SM_19

VCC_AXG_NCTF_44

VCC_NCTF_40

VSS_SCB4

BF33

AF19

U29

BL51

VCC_SM_20

VCC_AXG_NCTF_45

VCC_NCTF_41

VSS_SCB5

BF34

AH15

U31

A51

VCC_SM_21

VCC_AXG_NCTF_46

VCC_NCTF_42

VSS_SCB6

BG32

AH16

U32

VCC_SM_22

VCC_AXG_NCTF_47

VCC_NCTF_43

BG33

AH17

U33

VCC_SM_23

VCC_AXG_NCTF_48

NC52

NC53

NC54

VCC_NCTF_44

BG35

AH19

U35

VCC_SM_24

VCC_AXG_NCTF_49

VCC_NCTF_45

BH32

AJ16

Do Not Stuff

22UF/6.3V

0.1UF/10V

U36

VCC_SM_25

VCC_AXG_NCTF_50

VCC_NCTF_46

BH34

AJ17

/X

V32

GND

VCC_SM_26

VCC_AXG_NCTF_51

VCC_NCTF_47

BH35

AJ19

V33

VCC_SM_27

VCC_AXG_NCTF_52

VCC_NCTF_48

BJ32

AK16

V36

VCC_SM_28

VCC_AXG_NCTF_53

VCC_NCTF_49

BJ33

AK19

V37

VCC_SM_29

VCC_AXG_NCTF_54

VCC_NCTF_50

BJ34

AL16

VCC_SM_30

VCC_AXG_NCTF_55

GND

BK32

AL17

AT33

VCC_SM_31

VCC_AXG_NCTF_56

VCC_AXM_1

+VCC_AXM

BK33

AL19

AT31

VCC_SM_32

VCC_AXG_NCTF_57

VCC_AXM_2

BK34

AL20

AK29

VCC_SM_33

VCC_AXG_NCTF_58

VCC_AXM_3

BK35

AL21

+VCCP

+VCC_AXM

AK24

VCC_SM_34

VCC_AXG_NCTF_59

VCC_AXM_4

BL33

AL23

AK23

540 mA

VCC_SM_35

VCC_AXG_NCTF_60

VCC_AXM_5

AU30

AM15

AL24

AJ26

VCC_SM_36

VCC_AXG_NCTF_61

VCC_AXM_NCTF_1

VCC_AXM_6

AM16

AL26

AJ23

VCC_AXG_NCTF_62

VCC_AXM_NCTF_2

VCC_AXM_7

AM19

AL28

+VCCGFX

VCC_AXG_NCTF_63

VCC_AXM_NCTF_3

AM20

AM26

B

VCC_AXG_NCTF_64

NC55

NC56

NC57

NC58

NC59

NC60

VCC_AXM_NCTF_4

B

AM21

AM28

VCC_AXG_NCTF_65

VCC_AXM_NCTF_5

R20

AM23

22UF/6.3V

0.22UF/6.3V

Do Not Stuff

0.1UF/10V

0.1UF/10V

Do Not Stuff

AM29

VCC_AXG_1

VCC_AXG_NCTF_66

VCC_AXM_NCTF_6

T14

AP15

/X

/X

AM31

VCC_AXG_2

VCC_AXG_NCTF_67

VCC_AXM_NCTF_7

W13

AP16

AM32

VCC_AXG_3

VCC_AXG_NCTF_68

VCC_AXM_NCTF_8

W14

AP17

AM33

VCC_AXG_4

VCC_AXG_NCTF_69

VCC_AXM_NCTF_9

Y12

AP19

AP29

VCC_AXG_5

VCC_AXG_NCTF_70

VCC_AXM_NCTF_10

AA20

AP20

AP31

VCC_AXG_6

VCC_AXG_NCTF_71

VCC_AXM_NCTF_11

AA23

AP21

AP32

VCC_AXG_7

VCC_AXG_NCTF_72

GND

VCC_AXM_NCTF_12

AA26

AP23

AP33

VCC_AXG_8

VCC_AXG_NCTF_73

VCC_AXM_NCTF_13

AA28

AP24

AL29

VCC_AXG_9

VCC_AXG_NCTF_74

VCC_AXM_NCTF_14

AB21

AR20

AL31

VCC_AXG_10

VCC_AXG_NCTF_75

VCC_AXM_NCTF_15

AB24

AR21

AL32

VCC_AXG_11

VCC_AXG_NCTF_76

VCC_AXM_NCTF_16

AB29

AR23

AR31

VCC_AXG_12

VCC_AXG_NCTF_77

VCC_AXM_NCTF_17

AC20

AR24

AR32

VCC_AXG_13

VCC_AXG_NCTF_78

VCC_AXM_NCTF_18

AC21

AR26

AR33

VCC_AXG_14

VCC_AXG_NCTF_79

VCC_AXM_NCTF_19

AC23

V26

VCC_AXG_15

VCC_AXG_NCTF_80

AC24

V28

VCC_AXG_16

VCC_AXG_NCTF_81

AC26

V29

VCC_AXG_17

VCC_AXG_NCTF_82

AC28

Y31

VCC_AXG_18

VCC_AXG_NCTF_83

AC29

VCC_AXG_19

AD20

CRESTLINE_965PM

VCC_AXG_20

AD23

VCC_AXG_21

AD24

AW45

VCC_AXG_22

VCC_SM_LF1

AD28

BC39

VCC_AXG_23

VCC_SM_LF2

AF21

BE39

VCC_AXG_24

VCC_SM_LF3

AF26

BD17

VCC_AXG_25

VCC_SM_LF4

AA31

BD4

VCC_AXG_26

VCC_SM_LF5

AH20

AW8

A

VCC_AXG_27

VCC_SM_LF6

A

AH21

AT6

VCC_AXG_28

VCC_SM_LF7

AH23

VCC_AXG_29

AH24

VCC_AXG_30

AH26

NC61

NC62

NC63

NC64

NC65

NC66

NC67

1.1

VCC_AXG_31

AD31

0.1UF/10V

0.1UF/10V

0.22UF/6.3V

0.22UF/6.3V

0.47UF/10V

1UF/6.3V

1UF/6.3V

VCC_AXG_32

AJ20

Title :965PM--POWER (4)

VCC_AXG_33

AN14

VCC_AXG_34

7700 mA

GND

GND

GND

GND

GND

GND

GND

ASUSTeK COMPUTER INC

Engineer:

Alan Chen

Size

Project Name

Rev

Custom

Z96S

2.0

CRESTLINE_965PM

Date:

,

30, 2007

Sheet

9

of

67

5

4

3

2

1

5

4

3

2

1

NOTE:0.1uF caps in

1.5VS_XPLL need to be

located as edge caps

within 200 mils.

0Ohm

+VCCP

r0805_h24 NR31

U2H

1

2

D

+

D

J32

VCCSYNC

VTT_1

U13

NC68

NC69

NC70

NC71

NCE2

U12

4.7UF/6.3V

4.7UF/6.3V

2.2UF/6.3V Do Not Stuff

A33

VTT_2

U11

/X

Do Not Stuff

VCCA_CRT_DAC_1

VTT_3

/X

B33

U9

VCCA_CRT_DAC_2

VTT_4

U8

VTT_5

U7

VTT_6

A30

U5

VCCA_DAC_BG

VTT_7

U3

GND

VTT_8

NL1

B32

U2

+1.25VS

VSSA_DAC_BG

VTT_9

+1.25VS

1

2

U1

NR32

+1.25VS_DPLLA

VTT_10

T13

1

2

GND

VTT_11

Do Not Stuff

+

B49

T11

+1.25VS_DPLLA

VCCA_DPLLA

VTT_12

/X

NCE3

T10

0Ohm

VTT_13

NC72

H49

T9

r0805_h24

Do Not Stuff

+1.25VS_DPLLB

VCCA_DPLLB

VTT_14

Do Not Stuff

T7

NC73

NC74

/X

VTT_15

/X

NR44

AL2

T6

1UF/6.3V

Do Not Stuff

+1.25VS_HPLL

VCCA_HPLL

VTT_16

NR45

T5

/X

NL2

GND

GND

0Ohm

VTT_17

AM2

T3

0Ohm

+1.25VS_MPLL

VCCA_MPLL

VTT_18

1

2

T2

+1.25VS_DPLLB

VTT_19

R3

+1.25VS

VTT_20

Do Not Stuff

+

A41

R2

NR33

VCCA_LVDS

VTT_21

/X

NCE4

GND

R1

GND

1

2

NC75

VTT_22

B41

Do Not Stuff

VSSA_LVDS

Do Not Stuff

GND

0Ohm

/X

+3VS

/X

VCC_AXD_1

AT23

r0603_h24

AU28

NC76

NC77

VCC_AXD_2

NL3

GND

GND

GND

K50

AU24

1UF/6.3V

Do Not Stuff

VCCA_PEG_BG

VCC_AXD_3

C

1

2

AT29

/X

C

+1.25VS_PEGPLL

NC78

VCC_AXD_4

K49

AT25

VSSA_PEG_BG

VCC_AXD_5

120Ohm/100Mhz

0.1UF/10V

AT30

VCC_AXD_6

+1.25VS

+1.25VS

NC79

NC80

GND

U51

VCCA_PEG_PLL

VCC_AXD_NCTF

AR29

0.1UF/10V

Do Not Stuff

GND +1.25VS_PEGPLL

GND

GND

GND

AW18

VCCA_SM_1

VCC_AXF_1

B23

NC81

AV19

B21

VCCA_SM_2

POWER

VCC_AXF_2

+

AU19

A21

0.1UF/10V

NL4

AU18

VCCA_SM_3

VCC_AXF_3

VCCA_SM_4

1

2

NCE5

NC82

NC83

AU17

AJ50

+1.8V_GMCH

+1.25VS_HPLL

VCCA_SM_5

VCC_DMI

Do Not Stuff

22UF/6.3V

Do Not Stuff

NL5

120Ohm/100Mhz

/X

/X

AT22

VCCA_SM_7

GND

80Ohm/100Mhz

AT21

BK24

1

2

NC84

NC85

VCCA_SM_8

VCC_SM_CK_1

AT19

BK23

VCCA_SM_9

VCC_SM_CK_2

0.1UF/10V

Do Not Stuff

AT18

BJ24

VCCA_SM_10

VCC_SM_CK_3

GND

AT17

BJ23

+1.25VS

VCCA_SM_11

VCC_SM_CK_4

AR17

NC86

NC87

NC88

VCCA_SM_NCTF_1

NL6

GND

GND

AR16

+3VS_HV

0.1UF/10V

Do Not Stuff10UF/10V

VCCA_SM_NCTF_2

1

2

/X

+1.25VS_MPLL

A43

VCC_TX_LVDS

120Ohm/100Mhz

BC29

NC89

VCCA_SM_CK_1

BB29

0.1UF/10V

VCCA_SM_CK_2

NC90

NC91

C40

GND

VCC_HV_1

0.1UF/10V

Do Not Stuff

NC92

NC93

C25

B40

GND

VCCA_TVA_DAC_1

VCC_HV_2

22UF/6.3V

1UF/6.3V

B25

NL7

+VCCP

VCCA_TVA_DAC_2

C27

GND

80Ohm/100Mhz

GND

GND

VCCA_TVB_DAC_1

B27

AD51

1

2

B

VCCA_TVB_DAC_2

VCC_PEG_1

B

B28

W50

VCCA_TVC_DAC_1

VCC_PEG_2

A28

W51

VCCA_TVC_DAC_2

VCC_PEG_3

GND

V49

+

VCC_PEG_4

+1.5VS

V50

NC94

NCE6

VCC_PEG_5

M32

10UF/10V

VCCD_CRT

Do Not Stuff

L29

VCCD_TVDAC

/X

AH50

VCC_RXR_DMI_1

N28

AH51

+VCCP

VCCD_QDAC

VCC_RXR_DMI_2

GND

GND

NC95

NC96

+1.25VS

AN2

VCCD_HPLL

A7

VTTLF1

0.1UF/10V

Do Not Stuff

+1.25VS_PEGPLL

U48

F2

VCCD_PEG_PLL

VTTLF2

/X

AH1

INTEL CRB 1.2

+VCCP

VTTLF3

J41

VCCD_LVDS_1

+

H42

NC97

NCE7

VCCD_LVDS_2

NC98

10UF/10V

Do Not Stuff

GND

0.1UF/10V

/X

CRESTLINE_965PM

NC99

NC100

NC101

ND1

0.47UF/6.3V

0.47UF/6.3V

0.47UF/6.3VGND

GND

BAT54C

GND

GND

GND

GND

GND

A

+3VS

NR34

A

10Ohm

NR35

1.1

1

2

+3VS_HV

Title : 965PM--POWER (5)

0Ohm

ASUSTeK COMPUTER INC

Engineer:

Alan Chen

Size

Project Name

Rev

Custom

Z96S

2.0

Date:

,

30, 2007

Sheet

10 of

67

5

4

3

2

1

HIGH = LANES REVERSED

5

4

3

2

1

GND

U2I

CRESTLINE_965PM

D

D

GND

U2J

CRESTLINE_965PM

C

C

GND

<7> MCH_CFG_13

CFG [13:12] : XOR/ALL-Z

NR36

00 = Reserved

Do Not Stuff

01= XOR Mode Enabled

+3VS

/X

<7> MCH_CFG_5

CFG19 : DMI LANE REVERSAL

10= All-Z Mode Enabled

B

CFG5 : DMI STRAP

B

LOW = NORMAL (default)

NR37

HIGH = DMI X 4 (Default)

GND

11= Normal Operation (Default)

Do Not Stuff

HIGH = LANES REVERSED

/X

LOW = DMI X 2

NR38

Do Not Stuff

/X

GND

<7> MCH_CFG_7

CFG7 : CPU STRAP

<7> MCH_CFG_12

<7> MCH_CFG_19

NR39

HIGH = Mobile CPU (Default)

+3VS

Do Not Stuff

CFG20 : SDVO/PCIE CONCURRENT MODE

NR40

/X

LOW = Reserved

Do Not Stuff

LOW = ONLY SDVO or PCIE is Operational

GND

NR41

HIGH = SDVO and PCIE are operating simultaneously via the PEG port

<7> MCH_CFG_9

CFG9 : PCIE GRAPHIC LANE

Do Not Stuff

GND

/X

LOW = REVERSE LANE

NR42

HIGH = Normal Operation (Default)

<7> MCH_CFG_20

Do Not Stuff

/X

A

GND

A

<7> MCH_CFG_16

CFG16 : Dynamic ODT STRAP

1.1

NR43

Low = Dynamic ODT Disabled

Title : GND/Strapping (6)

Do Not Stuff

HIGH = Dyanamic ODT Enabled

/X

ASUSTeK COMPUTER INC

Engineer:

Alan Chen

(default)

Size

Project Name

Rev

GND

Custom

Z96S

2.0

Date:

,

30, 2007

Sheet

11

of

67

5

4

3

2

1

5

4

3

2

1

RTC CMOS

U3A

RTC_X1

CLEAR

AG25

RTCX1

FWH0/LAD0

E5

LPC_AD0

<44,50,53>

RTC_X2

AF24

F5

RTCX2

FWH1/LAD1

LPC_AD1

<44,50,53>

SR1

G8

RTCRST#

FWH2/LAD2

LPC_AD2

<44,50,53>

1

2

AF23

F6

+VCC_RTC

RTCRST#

FWH3/LAD3

LPC_AD3

<44,50,53>

20KOhm

+VCC_RTC

SR2

1

1MOhm 2

AD22

INTRUDER#

FWH4/LFRAME#

C4

LPC_FRAME#

<44,50,53>

D

1%

D

SC1

SR3

1

332KOhm2

1%

AF25

INTVRMEN

LDRQ0#

G9

1

+VCCP_ICH

1

2

AD21

E6

1

T208

LAN100_SLP

LDRQ1#/GPIO23

1UF/6.3V

SR4

332KOhm

1%

T158

+3VSUS

SR6

B24

GLAN_CLK

A20GATE

AF13

A20GATE

<44>

AG26

A20M#

H_A20M#

<3>

Do Not Stuff

D22

SR5

LAN_RSTSYNC

1

/X

2

AF26

56Ohm

DPRSTP#

H_DPRSTP#

<3,7>

C21

AE26

LAN_RXD0

DPSLP#

H_DPSLP#

<3>

B21

SR7

LAN_RXD1

C22

AD24

LAN_RXD2

FERR#

H_FERR#

<3>

1

2

GND

+1.5VS

D21

AG29

LAN_TXD0

CPUPWRGD/GPIO49

H_PWRGD

<3>

24.9Ohm

E20

LAN_TXD1

C20

AF27

+VCCP_ICH

LAN_TXD2

IGNNE#

T159

H_IGNNE#

<3>

1

AH21

GLAN_DOCK#/GPIO13

INIT#

AE24

H_INIT#

<3>

AC20

INTR

H_INTR

<3>

D25

AH14

GLAN_COMPI

RCIN#

T160

RC_IN#

<44>

C25

1

GLAN_COMPO

AD23

SR8

ACZ_BCLK

NMI

H_NMI

<3>

AJ16

AG28

56Ohm

<35,42> ACZ_BCLK

HDA_BIT_CLK

SMI#

H_SMI#

<3>

ACZ_SYNC

AJ15

1

<35,42> ACZ_SYNC

HDA_SYNC

AA24

T161

ACZ_RST#

STPCLK#

H_STPCLK#

<3>

AE14

<35,42,43> ACZ_RST#

HDA_RST#

AE27

2

1

THRMTRIP#

PM_THRMTRIP# <3,7>

AJ17

SR9

24.9Ohm 1%

<42> ACZ_SDIN0

HDA_SDIN0

AH17

AA23

1

T163

<35> ACZ_SDIN1

T162

ACZ_SDIN2

HDA_SDIN1

TP8

C

1

AH15

C

HDA_SDIN2

T164

1

ACZ_SDIN3

AD13

V1

IDE_PDD0

HDA_SDIN3

DD0

U2

IDE_PDD1

DD1

ACZ_SDOUT

AE13

V3

IDE_PDD2

<35,42> ACZ_SDOUT

HDA_SDOUT

DD2

T1

IDE_PDD3

DD3

T212

1

AE10

V4

IDE_PDD4

HDA_DOCK_EN#/GPIO33

DD4

AG14

T5

IDE_PDD5

HDA_DOCK_RST#/GPIO34

DD5

T165

1

AB2

IDE_PDD6

DD6

AF10

T6

IDE_PDD7

<48> SATA_LED#

SATALED#

DD7

T3

IDE_PDD8

DD8

SC2

2

1

3900PF/25V

SATA0RXN

AF6

R2

IDE_PDD9

<51> SATA_RXN0

SATA0RXN

DD9

SATA:

SC3

2

1

3900PF/25V

SATA0RXP

AF5

T4

IDE_PDD10

<51> SATA_RXP0

SATA0RXP

DD10

Distance between the ICH7 and cap on

SC4

2

1

3900PF/25V

SATA0TXN

AH5

V6

IDE_PDD11

<51> SATA_TXN0

SATA0TXN

DD11

the "P" signal should be identical

SC5

2

1

3900PF/25V

SATA0TXP

AH6

V5

IDE_PDD12

<51>

SATA_TXP0

SATA0TXP

DD12

U1

IDE_PDD13

distance between the ICH7 and cap on

DD13

IDE_PDD[0..15]

AG3

V2

IDE_PDD14

IDE_PDD[0..15]

<51>

the "N" signal for same pair.

AG4

SATA1RXN

DD14

U6

IDE_PDD15

SATA1RXP

DD15

Clost to SB

T166

1

AJ4

SATA1TXN

T167

1

AJ3

AA4

IDE_PDA0

<51>

SATA1TXP

DA0

GND

AA1

DA1

IDE_PDA1

<51>

AF2

AB3

SATA2RXN

DA2

IDE_PDA2

<51>

AF1

SATA2RXP

T168

1

AE4

Y6

SATA2TXN

DCS1#

IDE_PDCS1#

<51>

T169

1

AE3

Y5

SATA2TXP

DCS3#

IDE_PDCS3#

<51>

GND

<25> CLK_PCIE_SATA#

AB7

SATA_CLKN

DIOR#

W4

IDE_PDIOR# <51>

AC6

W3

<25> CLK_PCIE_SATA

SATA_CLKP

DIOW#

IDE_PDIOW#

<51>

Y2

DDACK#

IDE_PDDACK#

<51>

AG1

Y3

B

SATABIAS

SATARBIAS#

IDEIRQ

INT_IRQ14

<14,51>

B

2

1

AG2

Y1

SATARBIAS

IORDY

IDE_PIORDY

<14,51>

Place R1092 within 500 mils

GND

SR10

24.9Ohm 1%

W5

DDREQ

IDE_PDDREQ

<51>

of ICH ball

ICH8-M

SATA if it non-used,

SC6

1)SATA[0:3]RXpn SATABIAS,SATABIAS# and SATA_CLKpn should be PD.

1

2

RTC_X1

2)SATA[0:3]TXpn and SATALED# NO connect.

15PF/50V

RTC BAT

SY1

+3VA

1

1

SR11

3

SIDE

+VCC_RTC

2

10MOhm

2

T170

T171

CN10

+RTCBAT

SD1

SC7

32.768KHZ

1

RTC_X2

SIDE1

3

3

1

2

1

2

1

SR12

1KOhm

15PF/50V

2

2

4

SC8

BAT54C

SIDE2

Do Not Stuff

SC9

GND

A

WTOB_CON_2P

1UF/10V

A

RTC Battery

GND

GND

GND

1.1

P/N=07-016322032

Title : ICH8-M (1)

ASUSTeK COMPUTER INC

Engineer:

Alan Chen

Size

Project Name

Rev

Custom

Z96S

2.0

Date:

,

30, 2007

Sheet

12

of

67

5

4

3

2

1

5

4

3

2

1

<34,37>

PCI_AD[0..31]

PCI_AD[0..31]

U3B

PCI_AD0

D20

AD0

REQ0#

A4

PCI_REQ#0

<14,37>

U3D

PCI_AD1

E19

AD1

PCI

GNT0#

D7

PCI_GNT#0

PCI_GNT#0

<37>

P27

PERN1

DMI0RXN

V27

DMI_RXN0

<7>

PCI_AD2

D19

E18

P26

V26

PCI_AD3

A20

AD2

REQ1#/GPIO50

C18

PCI_REQ#1

<14>

T172

N29

PERP1

DMI0RXP

U29

DMI_RXP0 <7>

AD3

GNT1#/GPIO51

1

PETN1

DMI0TXN

DMI_TXN0 <7>

D

PCI_AD4

D17

B19

N28

U28

D

PCI_AD5

A21

AD4

REQ2#/GPIO52

F18

PCI_REQ#2

<14,34>

PETP1

DMI0TXP

DMI_TXP0 <7>

PCI_AD6

A19

AD5

GNT2#/GPIO53

A11

PCI_GNT#2

<34>

M27

Y27

PCI_AD7

AD6

REQ3#/GPIO54

PCI_REQ#3

<14>

<36> PCIE_RXN2_MINICARD

PERN2

DMI1RXN

DMI_RXN1

<7>

C19

AD7

GNT3#/GPIO55

C10

1

/X

2

WLAN CARD<36> PCIE_RXP2_MINICARD

M26

PERP2

DMI1RXP

Y26

DMI_RXP1 <7>

PCI_AD8

A18

AD8

SR13

Do Not

StuffGND

<36> PCIE_TXN2_MINICARD

SC12

1

2

0.1UF/10V

PCIE_TXN2_SB L29

PETN2

DMI1TXN

W29

DMI_TXN1 <7>

PCI_AD9

B16

AD9

C/BE0#

C17

PCI_C/BE#0

<34,37>

<36> PCIE_TXP2_MINICARD

SC13

1

2

0.1UF/10V

PCIE_TXP2_SB L28

PETP2

DMI1TXP

W28

DMI_TXP1 <7>

PCI_AD10

A12

E15

PCI_AD11

E16

AD10

C/BE1#

F16

PCI_C/BE#1

<34,37>

K27

AB26

PCI_AD12

A14

AD11

C/BE2#

E17

PCI_C/BE#2

<34,37>

<40> PCIE_RXN3_NEWCARD

K26

PERN3

DMI2RXN

AB25

DMI_RXN2

<7>

AD12

C/BE3#

PCI_C/BE#3

<34,37> NEW CARD<40> PCIE_RXP3_NEWCARD

PERP3

DMI2RXP

DMI_RXP2 <7>

PCI_AD13

G16

SC14

1

2

0.1UF/10V

PCIE_TXN3_SB J29

AA29

AD13

<40> PCIE_TXN3_NEWCARD

PETN3

DMI2TXN

DMI_TXN2 <7>

PCI_AD14

A15

AD14

IRDY#

C8

PCI_IRDY#

<14,34,37>

<40> PCIE_TXP3_NEWCARD

SC15

1

2

0.1UF/10V

PCIE_TXP3_SB J28

PETP3

DMI2TXP

AA28

DMI_TXP2 <7>

PCI_AD15

B6

D9

AD15

PAR

PCI_PAR

<34,37>

PCI_AD16

C11

AD16

PCIRST#

G6

PCI_RST#_ICH

<31> PCIE_RXN4_ROBSON

H27

PERN4

DMI3RXN

AD27

DMI_RXN3 <7>

PCI_AD17

A9

D16

H26

AD26

AD17

DEVSEL#

PCI_DEVSEL#

<14,34,37>

<31> PCIE_RXP4_ROBSON

PERP4

DMI3RXP

DMI_RXP3 <7>

PCI_AD18

D11

AD18

PERR#

A7

PCI_PERR#

<14,34,37>

ROBSON<31> PCIE_TXN4_ROBSON

SC10

1

2 0.1UF/10V PCIE_TXN4_SBG29

PETN4

DMI3TXN

AC29

DMI_TXN3 <7>

PCI_AD19

B12

AD19

PLOCK#

B7

PCI_LOCK#

<14>

<31> PCIE_TXP4_ROBSON

SC11

1

2

0.1UF/10V

PCIE_TXP4_SBG28

PETP4

DMI3TXP

AC28

DMI_TXP3 <7>

PCI_AD20

C12

F10

PCI_AD21

D10

AD20

SERR#

C16

PCI_SERR#

<14,34,37>

F27

T26

PCI_AD22

C7

AD21

STOP#

C9

PCI_STOP#

<14,34,37>

F26

PERN5

DMI_CLKN

T25

CLK_PCIE_ICH# <25>

PCI_AD23

F13

AD22

TRDY#

A17

PCI_TRDY#

<14,34,37>

ROBSON from PER1 change to PER4 by 2.0G

E29

PERP5

DMI_CLKP

CLK_PCIE_ICH

<25>

PCI_AD24

E11

AD23

FRAME#

PCI_FRAME#

<14,34,37>

E28

PETN5

Y23

Place within 500 mils of ICH

PCI_AD25

E13

AD24

AG24

PLT_RST#_SB

PETP5

DMI_ZCOMP

Y24

2

1%

1

+1.5VS

AD25

PLTRST#

DMI_IRCOMP

PCI_AD26

E12

AD26

PCICLK

B10

CLK_ICHPCI

<25>

D27

PERN6/GLAN_RXN

SR14

24.9Ohm

PCI_AD27

D8

AD27

PME#

G7

PCI_PME#

<14,34>

D26

PERP6/GLAN_RXP

USBP0N

G3

USB_PN0

<46>

USB 0

USB Conn.

PCI_AD28

A6

C29

G2

PCI_AD29

E8

AD28

C28

PETN6/GLAN_TXN

USBP0P

H5

USB_PP0

<46>

USB 1

USB Conn.

PCI_AD30

D6

AD29

PETP6/GLAN_TXP

USBP1N

H4

USB_PN1

<46>

PCI_AD31

A3

AD30

C23

USBP1P

H2

USB_PP1

<46>

USB 2

USB Conn.

C

AD31

B23

SPI_CLK

USBP2N

H1

USB_PN2

<46>

C

Interrupt I/F

SPI_CS1#

E22

SPI_CS0#

USBP2P

J3

USB_PP2

<46>

USB 3

USB Conn.

F9

F8

SPI_CS1#

USBP3N

J2

USB_PN3

<46>

<14,37> PCI_INTA#

B5

PIRQA#

PIRQE#/GPIO2

G11

D23

USBP3P

K5

USB_PP3

<46>

USB 4

Bluetooth

<14,37> PCI_INTB#

C5

PIRQB#

PIRQF#/GPIO3

F12

F21

SPI_MOSI

USBP4N

K4

USB_PN4

<54>

<14,34> PCI_INTC#

A10

PIRQC#

PIRQG#/GPIO4

B3

PCI_INTG#

<14>

SPI_MISO

USBP4P

K2

USB_PP4

<54>

USB 5

CMOS Camera

<14> PCI_INTD#

PIRQD#

PIRQH#/GPIO5

PCI_INTH#

<14>

USB_CON_OC01#

USBP5N

USB_PN5

<43>

<46> USB_CON_OC01#

AJ19

OC0#

USBP5P

K1

USB_PP5

<43>

ICH8-M

AG16

OC1#/GPIO40

USBP6N

L3

USB_PN6

<40>

USB 6

New Card

USB_CON_OC23#

AG15

USB

L2

<46> USB_CON_OC23#

AE15

OC2#/GPIO41

USBP6P

M5

USB_PP6

<40>

USB 7

Port_Bar

USB_OC#4

AF15

OC3#/GPIO42

USBP7N

M4

USB_PN7

<41>

USB_OC#5

AG17

OC4#/GPIO43

USBP7P

M2

USB_PP7

<41>

USB 8

Robson

NEWCARD_OC#

AD12

OC5#/GPIO29

USBP8N

M1

USB_PN8

<31>

<40> NEWCARD_OC#

USB_OC#7

AJ18

OC6#/GPIO30

USBP8P

N3

USB_PP8

<31>

USB 9

WLAN Card

USB_OC#8

AD14

OC7#/GPIO31

USBP9N

N2

USB_PN9

<36>

USB_OC#9

AH18

OC8#

USBP9P

USB_PP9

<36>

OC9#

USBBIAS

USBRBIAS#

F2

SR15 from 22.6

USBRBIAS

F3

1

2

SR15

22Ohm

ohm change to

ICH8-M

Place within 500 mils of ICH

GND

22 ohm by 2.0G

+3V

+3VSUS

SR16

10KOhm

NEWCARD_OC#

1

2

B

SU1

B

1

A

5

SR17

10KOhm

VCC

USB_OC#4

PLT_RST#_SB

2

B

1

2

USB_OC#5

3

GND

4

BUF_PLT_RST# <7,14,22,31,36,40,44,51,53>

USB_OC#7

Y

NC7SZ08P5X

PLT_RST#

<7,14,22,31,36,40,44,51,53>

USB_OC#8

USB_OC#9

GND

+3VSUS

+3V

SR18

SPI_CS1#

ICH8 Boot BIOS select

2

1

Do Not Stuff

GNT#0

CS#1

/X

PCI_GNT#0

LPC

11

1

1

(default)

PCI

10

1

0

SPI

01

0

1

SU2

SR19

1

A

VCC

5

Do Not Stuff

PCI_RST#_ICH

2

B

/X

A

3

4

A

GND

Y

PCI_RST#

<34,37>

NC7SZ08P5X

GND

1.1

GND

Title : ICH8-M (1)

ASUSTeK COMPUTER INC

Engineer:

Alan Chen

Size

Project Name

Rev

Custom

Z96S

2.0

Date:

,

30, 2007

Sheet

13

of

67

5

4

3

2

1

5

4

3

2

1

+3VS

PM_CLKRUN# SRN1A

1

5

8.2KOhm

SRN1B

10

<13,34,37>

PCI_FRAME#

2

5

8.2KOhm

SRN1C

10

3

5

+3VSUS

U3C

<13,34,37>

PCI_IRDY#

8.2KOhm

SMB_CLK

10

AJ26

SMBCLK

SATA0GP/GPIO21

AJ12

WLAN_BT_LED_EN#

<48>

<13,34,37> PCI_TRDY#

SRN1D

4

5

SMB_DAT

AD19

AJ10

8.2KOhm

SMBDATA

SATA1GP/GPIO19

CB_SD#

<37>

10

LINKALERT#

AG21

AF11

SRN1E

6

5

SM_LINK0

AC17

LINKALERT#

SATA2GP/GPIO36

AG11

WLAN_ON#

<36>

<13,34,37>

PCI_STOP#

8.2KOhm

SMLINK0

SATA3GP/GPIO37

BT_ON#

<54>

10

D

SR20

SM_LINK1

AE19

SRN1F

7

5

D

SMLINK1

AG9

<13,34,37>

PCI_SERR#

8.2KOhm

10KOhm

PM_RI#

CLK14

CLK_ICH14

<25>

10

AF17

G5

SRN1G

8

5

RI#

CLK48

CLK_USB48

<25>

<13,34,37>

PCI_DEVSEL#

8.2KOhm

SUSCLK

SRN1H

10

<53> PM_SUS_STAT#

F4

SUS_STAT#/LPCPD#

SUSCLK

D3

SUSCLK

<53>

<13,34,37> PCI_PERR#

9

5

AD15

8.2KOhm

SYS_RESET#

10

SLP_S3#

AG23

SUSB#

<27,44>

AG12

AF21

<30> XDP_DBR#

<7> PM_BMBUSY#

BMBUSY#/GPIO0

SLP_S4#

SUSC#

<34,44>

AD18

1

T185

SR22

SLP_S5#

+3VSUS

1

2

AG22

0Ohm 1

2

SRN2A

1

5

SR21

10KOhm

SMBALERT#/GPIO11

AH27

1

T186

/X

VRM_PWRGD <7,44,55,63>

<13> PCI_LOCK#

8.2KOhm

S4_STATE#/GPIO26

SR23

SRN2B

10

<25> STP_PCI#

AE20

STP_PCI#/GPIO15

<13,37> PCI_REQ#0

2

5

STP_CPU#

AG18

AE23

ICH8_PWROK_R

Do Not1Stuff

2

8.2KOhm

<25,55> STP_CPU#

STP_CPU#/GPIO25

PWROK

ICH8_PWROK <7,44>

10

SRN2C

3

5

PM_CLKRUN#

AH11

AJ14

<13> PCI_REQ#1

8.2KOhm

<34,37,53> PM_CLKRUN#

CLKRUN#/GPIO32

DPRSLPVR/GPIO16

PM_DPRSLPVR

<7,55>

SRN2D

10

<13,34> PCI_REQ#2

4

5

PCIE_WAKE#

AE17

AE21

BAT_LL#

8.2KOhm

<36,40> PCIE_WAKE#

WAKE#

BATLOW#

BAT_LL#

<44>

10

INT_SERIRQ

AF12

SRN2E

6

5

<37,44,53>

INT_SERIRQ

SERIRQ

<13> PCI_REQ#3

PM_THERM#

AC13

C2

8.2KOhm

<44> PM_THERM#

THRM#

PWRBTN#

PM_PWRBTN# <44>

PM_THERM# SRN2F

10

7

5

VR_PWRGD_CLKEN

AJ20

AH20

8.2KOhm

VRMPWRGD

LAN_RST#

BUF_PLT_RST#

<7,13,22,31,36,40,44,51,53>

INT_SERIRQ SRN2G

10

8

5

T187

1

AJ22

AG27

8.2KOhm

TP7

RSMRST#

SR24PM_RSMRST# <44>

STP_CPU#

SRN2H

10

9

5

T114

1

AJ8

E1

0Ohm 1

2

8.2KOhm

TACH1/GPIO1

CK_PWRGD

CLK_PWRGD

<25>

VRM_PWRGD

<7,44,55,63>

10

T115

1

AJ9

TACH2/GPIO6

T116

1

AH9

E3

SR25

SRN3A

1

5

TACH3/GPIO7

CLPWROK

<13,37> PCI_INTB#

EXT_SMI#

AE16

Do Not1Stuff

2

8.2KOhm

<44> EXT_SMI#

GPIO8

ICH8_PWROK

<7,44>

10

C

EXT_SCI#

AC19

AJ25

1

T190

/X

SRN3B

2

5

C

<44> EXT_SCI#

GPIO12

SLP_M#

<13,34> PCI_INTC#

T120

1

AG8

8.2KOhm

TACH0/GPIO17

CL_CLK0_R

10

T125

1

AH12

F23

1

2

SRN3C

3

5

GPIO18

CL_CLK0

CL_CLK0

<7>

<13> PCI_INTD#

T126

1

AE11

AE18

0Ohm SR26 1

T192

8.2KOhm

GPIO20

CL_CLK1

INT_IRQ14

10

T230

1

AG10

SRN3D

4

5

SCLOCK/GPIO22

<12,51> INT_IRQ14

T117

1

AH25

F22

CL_DATA0_R1

2

8.2KOhm

QRT_STATE0/GPIO27

CL_DATA0

CL_DATA0

<7>

10

T118

1

AD16

AF19

0Ohm SR27 1

T195

SRN3E

6

5

QRT_STATE1/GPIO28

CL_DATA1

<13,37> PCI_INTA#

T119

1

VGPU_SEL1

AG13

8.2KOhm

PM_TS#

SATACLKREQ#/GPIO35

CL_VREF0

SRN3F

10

AF9

D24

7

5

SLOAD/GPIO38

CL_VREF0

<13> PCI_INTG#

AJ11

AH23

CL_VREF1

8.2KOhm

<25,44> CLK_PWRSAVE#

SDATAOUT0/GPIO39

CL_VREF1

10

T231

1

AD10

SRN3G

8

5

SDATAOUT1/GPIO48

<13> PCI_INTH#

AJ23

8.2KOhm

CL_RST#

CL_RST#

<7>

SRN3H

10

AD9

9

5

<42> SB_SPKR

SPKR

<12,51> IDE_PIORDY

AJ27

1

T232

8.2KOhm

CLGPIO0/GPIO24

10

AJ13

AJ24

1

T233

<7> MCH_SYNC#

MCH_SYNC#

CLGPIO1/GPIO10

AF22

1

T199

CLGPIO2/GPIO14

VRM_PWRGD

T200

1

AJ21

AG19

1

T201

SR48 1

2

10KOhm

TP3

WOL_EN/GPIO9

ICH8-M

+3VS

SB_SPKR

SR49 1

2

1KOhm

+3VS

D1

Modify by V2.0G

SQ1

SMB_CLK_S

SR29 1

2

2.2KOhm

SR50

1

<16> DDR_EXTTS#0

SMB_DAT_S

SR30 1

2

2.2KOhm

3

H2N7002

10KOhm

PM_EXTTS#0

<7>

SMB_CLK

2

B

SR31

10KOhm

3

2

SMB_CLK_S

<16,17,25,30,36,40>

BAT54AW

B

PM_RSMRST#

1

2

PM_TS#

+12VS

D2

1

3

PM_EXTTS#1

<7>

GND

SMB_DAT

<17> DDR_EXTTS#1

2

3

2

SMB_DAT_S <16,17,25,30,36,40>

BAT54AW

+3VSUS

Modify by V2.0G

LINKALERT#

1

10KOhm2 SRN5A

SQ2

SM_LINK0

3

10KOhm4 SRN5B

H2N7002

SM_LINK1

5

10KOhm6 SRN5C

EXT_SCI#

7

10KOhm8 SRN5D

SMB_CLK

SR32 1

2

2.2KOhm

+3VS

SMB_DAT

SR33 1

2

2.2KOhm

Modify by V2.0G

PM_PWRBTN#

SR28 1

2

10KOhm

SR34

PM_RI#

SR35 1

2

10KOhm

+3VS

+3VS

BAT_LL#

SR36 1

2

8.2KOhm

10KOhm

EXT_SMI#

SR37 1

2

10KOhm

PCIE_WAKE# SR38 1

2

1KOhm

VR_PWRGD_CLKEN

<13,34>

PCI_PME#

SR39 1

2

Do Not Stuff

/X

SQ3

SR40

SR41

A

Do Not Stuff

3.24KOhm

D 3

H2N7002

A

/X

CL_VREF1

CL_VREF0

11

CLK_EN#

<55>

G

1.1

S 2

SC22

SC23

Do Not Stuff

SR42

0.1UF/16V

SR43

Title : ICH8-M (3)

/X

Do Not Stuff

453Ohm

/X

ASUSTeK COMPUTER INC

Engineer:

Alan Chen

GND

Size

Project Name

Rev

GND

GND

Custom

Z96S

2.0

GND

GND

Date:

,

30, 2007

Sheet

14

of

67

5

4

3

2

1

5

4

3

2

1

+VCC_RTC

U3F

+VCCP_ICH

U3E

AD25

A13

SC24

VCCRTC

VCC1_05[01]

A23

K7

B13

VSS[001]

VSS[099]

VCC1_05[02]

A5

L1

0.1uF/10V

A16

C13

VSS[002]

VSS[100]

SR44

V5REF[1]

VCC1_05[03]

AA2

L13

T7

C14

VSS[003]

VSS[101]

V5REF[2]

VCC1_05[04]

SC25

SC26

AA7

L15

+5VS

1

2

D14

VSS[004]

VSS[102]

+5VREFSUS G4

VCC1_05[05]

A25

L26

GND

E14

22UF/6.3V

0.1uF/10V

VSS[005]

VSS[103]

V5REF_SUS

VCC1_05[06]

AB1

L27

100Ohm

F14

VSS[006]

VSS[104]

VCC1_05[07]

AB24

L4

AA25

G14

VSS[007]

VSS[105]

VCC1_5_B[01]

VCC1_05[08]

AC11

L5

SC27

AA26

L11

VSS[008]

VSS[106]

VCC1_5_B[02]

VCC1_05[09]

AC14

M12

SD2

2

0.1uF/10V

SC28

AA27

L12

VSS[009]

VSS[107]

VCC1_5_B[03]

VCC1_05[10]

AC25

M13

+3VS

0.1uF/10V

AB27

L14

GND

GND

VSS[010]

VSS[108]

VCC1_5_B[04]

VCC1_05[11]

D

AC26

M14

3

AB28

L16

D

VSS[011]

VSS[109]

VCC1_5_B[05]

VCC1_05[12]

AC27

M15

GND

AB29

L17

VSS[012]

VSS[110]

VCC1_5_B[06]

VCC1_05[13]

AD17

M16

1

GND

D28

L18

VSS[013]

VSS[111]

VCC1_5_B[07]

VCC1_05[14]

+1.5VS

AD20

M17

D29

M11

VSS[014]

VSS[112]

BAT54A

VCC1_5_B[08]

VCC1_05[15]

AD28

M23

E25

M18

VSS[015]

VSS[113]

VCC1_5_B[09]

VCC1_05[16]

AD29

M28

E26

P11

VSS[016]

VSS[114]

+1.5VS_PCIE_ICH

VCC1_5_B[10]

VCC1_05[17]

AD3

M29

E27

P18

1

2

VSS[017]

VSS[115]

VCC1_5_B[11]

VCC1_05[18]

AD4

M3

F24

T11

VSS[018]

VSS[116]

+1.5VS_PCIE_ICH

VCC1_5_B[12]

VCC1_05[19]

AD6

N1

1

2

F25

T18

SL1

VSS[019]

VSS[117]

+1.5VS

VCC1_5_B[13]

VCC1_05[20]

AE1

N11

G24

U11

80Ohm/100Mhz

VSS[020]

VSS[118]

SL2

SC29

SC30

VCC1_5_B[14]

VCC1_05[21]

SC33

SC34

AE12

N12

+

H23

U18

VSS[021]

VSS[119]

SCE1

SC31

SC32

VCC1_5_B[15]

VCC1_05[22]

AE2

VSS[022]

VSS[120]

N13

80Ohm/100Mhz

H24

VCC1_5_B[16]

VCC1_05[23]

V11

+1.25VS

AE22

N14

Do Not Stuff10UF/6.3V

10UF/6.3V

1UF/6.3V

Do Not Stuff

J23

V12

10UF/6.3V

0.01UF/16V

VSS[023]

VSS[121]

VCC1_5_B[17]

VCC1_05[24]

AD1

N15

/X

/X

J24

V14

VSS[024]

VSS[122]

VCC1_5_B[18]

VCC1_05[25]

AE25

N16

K24

V16

VSS[025]

VSS[123]

VCC1_5_B[19]

VCC1_05[26]

AE5

N17

K25

V17

VSS[026]

VSS[124]

VCC1_5_B[20]

VCC1_05[27]

GND

GND

AE6

N18

L23

V18

VSS[027]

VSS[125]

GND

VCC1_5_B[21]

VCC1_05[28]

0.1uF/10V

AE9

N26

L24

VSS[028]

VSS[126]

VCC1_5_B[22]

SC35

SC36

AF14

N27

L25

R29

VSS[029]

VSS[127]

VCC1_5_B[23]

VCCDMIPLL

AF16

N4

M24

22UF/6.3V

VSS[030]

VSS[128]

+3VSUS

VCC1_5_B[24]

+VCCP_ICH

AF18

N5

M25

AE28

VSS[031]

VSS[129]

VCC1_5_B[25]

VCC_DMI[1]

AF3

N6

N23

AE29

VSS[032]

VSS[130]

VCC1_5_B[26]

VCC_DMI[2]

AF4

P12

N24

GND

GND

VSS[033]

VSS[131]

SD3

VCC1_5_B[27]

AG5

P13

N25

AC23

VSS[034]

VSS[132]

BAT54A

VCC1_5_B[28]

V_CPU_IO[1]

SC37

AG6

P14

P24

AC24

VSS[035]

VSS[133]

VCC1_5_B[29]

V_CPU_IO[2]

AH10

P15

P25

SC38

SC39

VSS[036]

VSS[134]

VCC1_5_B[30]

AH13

P16

R24

AF29

4.7UF/6.3V Do Not Stuff0.1uF/10V

VSS[037]

VSS[135]

VCC1_5_B[31]

VCC3_3[01]

AH16

P17

R25

/X

VSS[038]

VSS[136]

VCC1_5_B[32]

C

AH19

P23

R26

AD2

C

VSS[039]

VSS[137]

+5VREFSUS

VCC1_5_B[33]

VCC3_3[02]

AH2

P28

+5VSUS

1

2

R27

SC40

GND

GND

GND

+3VS

VSS[040]

VSS[138]

VCC1_5_B[34]

AF28

P29

SR45

100Ohm

T23

AC8

0.1uF/10V

VSS[041]

VSS[139]

VCC1_5_B[35]

VCC3_3[03]

SC41

AH22

R11

T24

AD8

VSS[042]

VSS[140]

VCC1_5_B[36]

VCC3_3[04]

AH24

R12

T27

AE8

Do Not Stuff

VSS[043]

VSS[141]

VCC1_5_B[37]

VCC3_3[05]

AH26

R13

T28

AF8

/X

GND

VSS[044]

VSS[142]

VCC1_5_B[38]

VCC3_3[06]

AH3

R14

SL3

120Ohm/100Mhz

T29

VSS[045]

VSS[143]

VCC1_5_B[39]

GND

AH4

R15

1

2

U24

AA3

VSS[046]

VSS[144]

+1.5VS

VCC1_5_B[40]

VCC3_3[07]

SC42

AH8

R16

U25

U7

VSS[047]

VSS[145]

VCC1_5_B[41]

VCC3_3[08]

AJ5

R17

SC43

V23

V7

0.1uF/10V

VSS[048]

VSS[146]

VCC1_5_B[42]

VCC3_3[09]

B11

R18

SC44

V24

W1

VSS[049]

VSS[147]

VCC1_5_B[43]

VCC3_3[10]

B14

R28

Do Not Stuff

1UF/6.3V

V25

W6

VSS[050]

VSS[148]

VCC1_5_B[44]

VCC3_3[11]

B17

R4

/X

W25

W7

GND

VSS[051]

VSS[149]

VCC1_5_B[45]

VCC3_3[12]

B2

T12

Y25

Y7

VSS[052]

VSS[150]

VCC1_5_B[46]

VCC3_3[13]

SC45

B20

T13

VSS[053]

VSS[151]

B22

T14

AJ6

A8

VSS[054]

VSS[152]

+1.5VS

GND

GND

VCCSATAPLL

VCC3_3[14]

0.01UF/16V

B8

T15

B15

VSS[055]

VSS[153]

VCC3_3[15]

C24

T16

SR46

AE7

B18

VSS[056]

VSS[154]

VCC1_5_A[01]

VCC3_3[16]

C26

T17

1

2

AF7

B4

VSS[057]

VSS[155]

VCC1_5_A[02]

VCC3_3[17]

C27

T2

r0805_h24

AG7

B9

GND

VSS[058]

VSS[156]

VCC1_5_A[03]

VCC3_3[18]

C6

U12

AH7

C15

VSS[059]

VSS[157]

+VCCP

+VCCP_ICH

0Ohm

SC46

VCC1_5_A[04]

VCC3_3[19]

D12

U13

AJ7

D13

VSS[060]

VSS[158]

VCC1_5_A[05]

VCC3_3[20]

D15

U14

1UF/6.3V

D5

SC47

SC48

SC49

VSS[061]

VSS[159]

VCC3_3[21]

D18

U15

AC1

E10

Do Not Stuff

0.1uF/10V

0.1uF/10V

VSS[062]

VSS[160]

VCC1_5_A[06]

VCC3_3[22]

D2

U16

AC2

E7

/X

VSS[063]

VSS[161]

GND

VCC1_5_A[07]

VCC3_3[23]

D4

U17

AC3

F11

VSS[064]

VSS[162]

VCC1_5_A[08]

VCC3_3[24]

GND

GND

GND

E21

U23

AC4

VSS[065]

VSS[163]

SC50

VCC1_5_A[09]

+3VS

E24

U26

AC5

AC12

VSS[066]

VSS[164]

VCC1_5_A[10]

VCCHDA

E4

U27

1UF/6.3V

B

VSS[067]

VSS[165]

+3VSUS

B

E9

U3

AC10

AD11

VSS[068]

VSS[166]

VCC1_5_A[11]

VCCSUSHDA

F15

U5

AC9

SC51

VSS[069]

VSS[167]

VCC1_5_A[12]

E23

V13

GND

J6

0.1uF/10V

VSS[070]

VSS[168]

VCCSUS1_05[1]

SC52

F28

V15

AA5

AF20

VSS[071]

VSS[169]

VCC1_5_A[13]

VCCSUS1_05[2]

F29

V28

AA6

SC53

0.1uF/10V

VSS[072]

VSS[170]

VCC1_5_A[14]

F7

V29

AC16

SC54

0.1uF/10V

GND

VSS[073]

VSS[171]

VCCSUS1_5[1]

G1

W2

G12

0.1uF/10V

VSS[074]

VSS[172]

VCC1_5_A[15]

E2

W26

G17

J7

GND

GND

VSS[075]

VSS[173]

VCC1_5_A[16]

VCCSUS1_5[2]

GND

G10

W27

H7

VSS[076]

VSS[174]

VCC1_5_A[17]

+3VSUS

G13

Y28

C3

VSS[077]

VSS[175]

VCCSUS3_3[01]

G19

Y29

AC7

VSS[078]

VSS[176]

+1.5VS

VCC1_5_A[18]

G23

Y4

AD7

AC18

VSS[079]

VSS[177]

VCC1_5_A[19]

VCCSUS3_3[02]

SC55

SC56

G25

AB4

AC21

VSS[080]

VSS[178]

VCCSUS3_3[03]

G26

AB23

D1

AC22

VSS[081]

VSS[179]

VCCUSBPLL

VCCSUS3_3[04]

G27

AB5

AG20

0.01UF/16V

0.01UF/16V

VSS[082]

VSS[180]

VCCSUS3_3[05]

H25

AB6

F1

AH28

VSS[083]

VSS[181]

VCC1_5_A[20]

VCCSUS3_3[06]

H28

AD5

L6

VSS[084]

VSS[182]

VCC1_5_A[21]

GND

GND

H29

U4

L7

P6

VSS[085]

VSS[183]

VCC1_5_A[22]

VCCSUS3_3[07]

H3

W24

+3VS

SC57

SC58

M6

P7

VSS[086]

VSS[184]

VCC1_5_A[23]

VCCSUS3_3[08]

H6

0.1uF/10V

0.1uF/10V

M7

C1

VSS[087]

VCC1_5_A[24]

VCCSUS3_3[09]

J1

A1

N7

SC59

VSS[088]

VSS_NCTF[01]

SR47

0Ohm

VCCSUS3_3[10]

J25

A2

W23

P1

VSS[089]

VSS_NCTF[02]

GND

GND

VCC1_5_A[25]

VCCSUS3_3[11]

10UF/6.3V

J26

A28

1

2

P2

VSS[090]

VSS_NCTF[03]

VCCSUS3_3[12]

J27

A29

r0603_h24

T203

1

F17

P3

VSS[091]

VSS_NCTF[04]

VCCLAN1_05[1]

VCCSUS3_3[13]

J4

AH1

T204

1

G18

P4

VSS[092]

VSS_NCTF[05]

SC60

VCCLAN1_05[2]

VCCSUS3_3[14]

GND

J5

AH29

P5

VSS[093]

VSS_NCTF[06]

VCCSUS3_3[15]

K23

AJ1

0.1uF/10V

F19

R1

VSS[094]

VSS_NCTF[07]

VCCLAN3_3[1]

VCCSUS3_3[16]

K28

AJ2

G20

R3

A

VSS[095]

VSS_NCTF[08]

SL4

120Ohm/100Mhz

VCCLAN3_3[2]

VCCSUS3_3[17]

A

K29

AJ28

R5

VSS[096]

VSS_NCTF[09]

VCCSUS3_3[18]

K3

AJ29

1GND

2

A24

R6

VSS[097]

VSS_NCTF[10]

+1.5VS

VCCGLANPLL

VCCSUS3_3[19]

K6

VSS[098]

VSS_NCTF[11]

B1

B29

SC61

A26

G22

VSS_NCTF[12]

VCCGLAN1_5[1]

VCCCL1_05

1.1

SC62

SC63

A27

VCCGLAN1_5[2]

ICH8-M

Do Not Stuff

1UF/6.3V

B26

A22

VCCGLAN1_5[3]

VCCCL1_5

Title : ICH8-M (1)

GND

GND

/X

10UF/6.3V

B27

+3VS

VCCGLAN1_5[4]

F20

+3VS

B28

VCCGLAN1_5[5]

VCCCL3_3[1]

GND

GND

G21

SC64

SC65

Engineer:

Alan Chen

VCCCL3_3[2]

ASUSTeK COMPUTER INC

GND

B25

VCCGLAN3_3

1UF/6.3V

0.1uF/10V

Size

Project Name

Rev

ICH8-M

GND

GND

Custom

Z96S

2.0

Date:

,

30, 2007

Sheet

15

of

67

5

4

3

2

1

GND

5

4

3

2

1

D

D

REV Type

DCLK0

C154

DIMM1A

10PF/50V

<8,18> M_A_A[0..13]

M_A_DQ[0..63]

<8>

DCLK0#

M_A_A0

102

A0

DQ0

5

M_A_DQ5

M_A_A1

101

7

M_A_DQ0

DCLK1

M_A_A2

100

A1

DQ1

17

M_A_DQ7

M_A_A3

99

A2

DQ2

19

M_A_DQ2

C155

M_A_A4

98

A3

DQ3

4

M_A_DQ4

10PF/50V

M_A_A5

97

A4

DQ4

6

M_A_DQ6

M_A_A6

94

A5

DQ5

14

M_A_DQ1

DCLK1#

M_A_A7

92

A6

DQ6

16

M_A_DQ3

M_A_A8

93

A7

DQ7

23

M_A_DQ8

M_A_A9

91

A8

DQ8

25

M_A_DQ9

M_A_A10

105

A9

DQ9

35

M_A_DQ10

+1.8V

DIMM1B

M_A_A12

89

A10/AP

DQ10

20

M_A_DQ12

M_A_A11

90

A11

DQ11

37

M_A_DQ11

M_A_A13

116

A12

DQ12

22

M_A_DQ15

112

18

86

A13

DQ13

36

M_A_DQ13

111

VDD1

VSS16

24

84

A14

DQ14

38

M_A_DQ14

1

2

CN1A

117

VDD2

VSS17

41

A15

DQ15

M_A_DQ16

0.1UF/25V

VDD3

VSS18

85

43

C766

C156

3

4

CN1B

96

53

<8,18> M_A_BS#2

A16_BA2

DQ16

M_A_DQ17

0.1UF/25V

VDD4

VSS19

45

10UF/10V

5

6

CN1C

95

42

DQ17

M_A_DQ20

0.1UF/25V

VDD5

VSS20

107

55

Do Not Stuff

7

8

CN1D

118

54

<8,18> M_A_BS#0

106

BA0

DQ18

57

M_A_DQ21

/X

0.1UF/25V

81

VDD6

VSS21

59

C

<8,18> M_A_BS#1

110

BA1

DQ19

44

M_A_DQ18

82

VDD7

VSS22

65

C

<7,18> SCS0#

115

S0#

DQ20

46

M_A_DQ19

GND

GND

GND

87

VDD8

VSS23

60

<7,18> SCS1#

30

S1#

DQ21

56

M_A_DQ23

103

VDD9

VSS24

66

<7> DCLK0

32

CK0

DQ22

58

M_A_DQ22

88

VDD10

VSS25

127

<7> DCLK0#

164

CK0#

DQ23

61

M_A_DQ29

+3VS

104

VDD11

VSS26

139

<7> DCLK1

166

CK1

DQ24

63

M_A_DQ28

VDD12

VSS27

128

<7>

DCLK1#

79

CK1#

DQ25

73

M_A_DQ24

199

VSS28

145

<7,18> SCKE0

80

CKE0

DQ26

75

M_A_DQ25

VDDSPD

VSS29

165

<7,18> SCKE1

113

CKE1

DQ27

62

M_A_DQ26

C157

83

VSS30

171

<8,18> M_A_CAS#

108

CAS#

DQ28

64

M_A_DQ31

0.1UF/16V

120

NC1

VSS31

172

<8,18> M_A_RAS#

109

RAS#

DQ29

74

M_A_DQ30

50

NC2

VSS32

177

<8,18> M_A_WE#

198

WE#

DQ30

76

M_A_DQ27

<14> DDR_EXTTS#0

69

NC3

VSS33

187

200

SA0

DQ31

123

M_A_DQ37

VTT_REF

163

NC4

VSS34

178

<14,17,25,30,36,40> SMB_CLK_S

197

SA1

DQ32

125

M_A_DQ35

GND

NCTEST

VSS35

190

195

SCL

DQ33

135

M_A_DQ34

1

VSS36

9

<14,17,25,30,36,40>

SMB_DAT_S

SDA

DQ34

137

M_A_DQ39

VREF

VSS37

21

<7,18> ODT0

114

DQ35

124

M_A_DQ33

C158

C159

201

VSS38

33

119

ODT0

DQ36

126

M_A_DQ36

1UF/10V

0.1UF/16V

202

GND0

VSS39

155

<7,18> ODT1

ODT1

DQ37

134

M_A_DQ32

GND1

VSS40

34

<8>

M_A_DM[0:7]

M_A_DM0

10

DQ38

136

M_A_DQ38

203

VSS41

132

M_A_DM1

26

DM0

DQ39

141

M_A_DQ46

204

NP_NC1

VSS42

144

GND

M_A_DM2

52

DM1

DQ40

143

M_A_DQ47

GND

GND

NP_NC2

VSS43

156

M_A_DM3

67

DM2

DQ41

151

M_A_DQ43

47

VSS44

168

M_A_DM4

130

DM3

DQ42

153

M_A_DQ45

133

VSS1

VSS45

2

M_A_DM5

147

DM4

DQ43

140

M_A_DQ41

183

VSS2

VSS46

3

M_A_DM6

170

DM5

DQ44

142

M_A_DQ44

77

VSS3

VSS47

15

M_A_DM7

185

DM6

DQ45

152

M_A_DQ40

12

VSS4

VSS48

27

<8>

M_A_DQS[0..7]

DM7

DQ46

154

M_A_DQ42

48

VSS5

VSS49

39

M_A_DQS0

13

DQ47

157

M_A_DQ51

184

VSS6

VSS50

149

M_A_DQS1

31

DQS0

DQ48

159

M_A_DQ55

78

VSS7

VSS51

161

B

M_A_DQS2

51

DQS1

DQ49

173

M_A_DQ50

71

VSS8

VSS52

28

B

M_A_DQS3

70

DQS2

DQ50

175

M_A_DQ54

72

VSS9

VSS53

40

M_A_DQS4

131

DQS3

DQ51

158

M_A_DQ53

121

VSS10

VSS54

138

M_A_DQS5

148

DQS4

DQ52

160

M_A_DQ48

122

VSS11

VSS55

150

M_A_DQS6

169

DQS5

DQ53

174

M_A_DQ52

196

VSS12

VSS56

162

<8>

M_A_DQS#[0..7]

M_A_DQS7

188

DQS6

DQ54

176

M_A_DQ49

193

VSS13

VSS57

M_A_DQS#0

11

DQS7

DQ55

179

M_A_DQ61

8

VSS14

M_A_DQS#1

29

DQS#0

DQ56

181

M_A_DQ62

VSS15

M_A_DQS#2

49

DQS#1

DQ57

189

M_A_DQ59

GND

M_A_DQS#3

68

DQS#2

DQ58

191

M_A_DQ63

DDR_DIMM_200P

M_A_DQS#4

129

DQS#3

DQ59

180

M_A_DQ56

GND

M_A_DQS#5

146

DQS#4

DQ60

182

M_A_DQ60

12G025332003

M_A_DQS#6

167

DQS#5

DQ61

192

M_A_DQ58

M_A_DQS#7

186

DQS#6

DQ62

194

M_A_DQ57

DQS#7

DQ63

DDR_DIMM_200P

12G025332003

A

A

1.1

Title : DDR2 SO-DIMM0

ASUSTeK COMPUTER INC.

Engineer:

Alan Chen

Size

Project Name

Rev

Custom

Z96S

2.0

Date:

,

30, 2007

Sheet

16

of

67

5

4

3

2

1

5

4

3

2

1

D								D
						STD Type
		DCLK2						M_B_DQ[63:0] <8>
		C160
		10PF/50V	<8,18>	M_B_A[0..13]		DIMM2A
		DCLK2#

DCLK3

M_B_A0

102

A0

DQ0

5

M_B_DQ4

M_B_A1

101

7

M_B_DQ1

A1

DQ1

M_B_A2

100

17

M_B_DQ2

A2

DQ2

C161

M_B_A3

99

19

M_B_DQ7

A3

DQ3

10PF/50V

M_B_A4

98

4

M_B_DQ5

A4

DQ4

M_B_A5

97

6

M_B_DQ0

DCLK3#

A5

DQ5

M_B_A6

94

14

M_B_DQ6

A6

DQ6

M_B_A7

92

16

M_B_DQ3

A7

DQ7

M_B_A8

93

23

M_B_DQ8

A8

DQ8

M_B_A9

91

25

M_B_DQ10

A9

DQ9

+1.8V

M_B_A10

105

35

M_B_DQ9

DIMM2B

M_B_A12

89

A10/AP

DQ10

20

M_B_DQ12

M_B_A11

90

A11

DQ11

37

M_B_DQ11

M_B_A13

116

A12

DQ12

22

M_B_DQ13

A13

DQ13

86

36

M_B_DQ15

112

18

A14

DQ14

VDD1

VSS16

84

38

M_B_DQ14

1

2 CN2A

111

24

A15

DQ15

VDD2

VSS17

85

43

M_B_DQ21

C162

3

0.1UF/25V

CN2B

117

41

<8,18> M_B_BS#2

A16_BA2

DQ16

4

VDD3

VSS18

45

M_B_DQ16

10UF/10V

5

0.1UF/25V

CN2C

96

53

DQ17

6

VDD4

VSS19

107

55

M_B_DQ18

7

0.1UF/25V

CN2D

95

42

<8,18> M_B_BS#0

BA0

DQ18

8

VDD5

VSS20

106

57

M_B_DQ22

0.1UF/25V

118

54

C

<8,18> M_B_BS#1

BA1

DQ19

VDD6

VSS21

C

110

44

M_B_DQ20

81

59

<7,18> SCS2#

S0#

DQ20

VDD7

VSS22

<7,18> SCS3#

115

S1#

DQ21

46

M_B_DQ17

GND

GND

82

VDD8

VSS23

65

30

56

M_B_DQ23

87

60

<7> DCLK2

CK0

DQ22

VDD9

VSS24

32

58

M_B_DQ19

103

66

<7> DCLK2#

CK0#

DQ23

+3VS

VDD10

VSS25

164

61

M_B_DQ24

88

127

<7> DCLK3

CK1

DQ24

VDD11

VSS26

166

63

M_B_DQ25

104

139

<7> DCLK3#

CK1#

DQ25

VDD12

VSS27

79

73

M_B_DQ26

128

<7,18> SCKE2

CKE0

DQ26

VSS28

80

75

M_B_DQ31

199

145

<7,18> SCKE3

CKE1

DQ27

VDDSPD

VSS29

+3VS

113

62

M_B_DQ28

C163

165

<8,18> M_B_CAS#

CAS#

DQ28

VSS30

108

64

M_B_DQ29

0.1UF/16V

83

171

<8,18> M_B_RAS#

RAS#

DQ29

NC1

VSS31

109

74

M_B_DQ30

120

172

<8,18> M_B_WE#

WE#

DQ30

NC2

VSS32

198

76

M_B_DQ27

50

177

SA0

DQ31

<14> DDR_EXTTS#1

NC3

VSS33

200

123

M_B_DQ37

69

187

SA1

DQ32

NC4

VSS34

197

125

M_B_DQ36

GND

VTT_REF

163

178

<14,16,25,30,36,40>

SMB_CLK_S

SCL

DQ33

NCTEST

VSS35

195

135

M_B_DQ34

190

<14,16,25,30,36,40> SMB_DAT_S

SDA

DQ34

VSS36

137

M_B_DQ35

1

9

DQ35

VREF

VSS37

114

124

M_B_DQ32

21

<7,18> ODT2

ODT0

DQ36

VSS38

119

126

M_B_DQ33

C164

C165

201

33

<7,18> ODT3

ODT1

DQ37

GND0

VSS39

134

M_B_DQ39

1UF/10V

0.1UF/16V

202

155

<8> M_B_DM[0..7]

DQ38

GND1

VSS40

M_B_DM0

10

136

M_B_DQ38

34

DM0

DQ39

VSS41

M_B_DM1

26

141

M_B_DQ40

203

132

DM1

DQ40

NP_NC1

VSS42

M_B_DM2

52

DM2

DQ41

143

M_B_DQ41

204

NP_NC2

VSS43

144

M_B_DM3

67

151

M_B_DQ46

GND

GND

156

DM3

DQ42

VSS44

GND

M_B_DM4

130

153

M_B_DQ42

47

168

DM4

DQ43

VSS1

VSS45

M_B_DM5

147

140

M_B_DQ44

133

2

DM5

DQ44

VSS2

VSS46

M_B_DM6

170

142

M_B_DQ45

183

3

DM6

DQ45

VSS3

VSS47

M_B_DM7

185

152

M_B_DQ43

77

15

DM7

DQ46

VSS4

VSS48

154

M_B_DQ47

12

27

<8>

M_B_DQS[0..7]

DQ47

VSS5

VSS49

M_B_DQS0

13

157

M_B_DQ53

48

39

DQS0

DQ48

VSS6

VSS50

M_B_DQS1

31

159

M_B_DQ49

184

149

DQS1

DQ49

VSS7

VSS51

B

M_B_DQS2

51

173

M_B_DQ51

78

161

B

DQS2

DQ50

VSS8

VSS52

M_B_DQS3

70

175

M_B_DQ50

71

28

DQS3

DQ51

VSS9

VSS53

M_B_DQS4

131

158

M_B_DQ48

72

40

DQS4

DQ52

VSS10

VSS54

M_B_DQS5

148

160

M_B_DQ52

121

138

DQS5

DQ53

VSS11

VSS55

M_B_DQS6

169

174

M_B_DQ55

122

150

DQS6

DQ54

VSS12

VSS56

M_B_DQS7

188

176

M_B_DQ54

196

162

<8> M_B_DQS#[0..7]

DQS7

DQ55

VSS13

VSS57

M_B_DQS#0

11

179

M_B_DQ60

193

DQS#0

DQ56

VSS14

M_B_DQS#1

29

181

M_B_DQ61

8

DQS#1

DQ57

VSS15

M_B_DQS#2

49

189

M_B_DQ62

GND

DQS#2

DQ58

M_B_DQS#3

68

191

M_B_DQ63

DDR_DIMM_200P

DQS#3

DQ59

M_B_DQS#4

129

180

M_B_DQ57

GND

DQS#4

DQ60

M_B_DQS#5

146

182

M_B_DQ56

12G025122000

DQS#5

DQ61

M_B_DQS#6

167

192

M_B_DQ58

DQS#6

DQ62

M_B_DQS#7

186

194

M_B_DQ59

DQS#7

DQ63

DDR_DIMM_200P

12G025122000

A

A

1.1

					Title :	DDR2 SO-DIMM1
			ASUSTeK COMPUTER INC. NB1		Engineer:	Alan Chen
			Size	Project Name		Rev
			Custom	Z96S		2.0
			Date:	, 30, 2007	Sheet	17 of 67
5	4	3	2		1

5

4

3

2

1

+0.9VS

D

D

SCKE0

7

56Ohm

10

RN15G

SCKE2

3

56Ohm

14

RN11C

SCKE3

2

56Ohm

15

RN11B

1

2

CN3A

ODT0

3

56Ohm

14

RN12C

3

0.1UF/25V

4

CN3B

ODT1

4

56Ohm

13

RN12D

5

0.1UF/25V

6

CN3C

+0.9VS

ODT2

5

56Ohm

12

RN13E

7

0.1UF/25V

8

CN3D

ODT3

8

56Ohm

9

RN13H

0.1UF/25V

VTT_REF

M_A_A8

5

56Ohm

12

RN15E

L13

GND

120Ohm/100Mhz

1

2

M_A_BS#1

56Ohm

RN12G

7

10

C767

M_A_A13

1

56Ohm

16

RN12A

<8,16> M_A_RAS#

1

56Ohm

16

RN15A

1

2

CN4A

10UF/10V

M_A_A7

6

56Ohm

11

RN15F

3

0.1UF/25V

4

CN4B

M_B_BS#0

2

56Ohm

15

RN13B

5

0.1UF/25V

6

CN4C

M_B_BS#1

1

56Ohm

16

RN13A

7

0.1UF/25V

8

CN4D

M_B_BS#2

8

56Ohm

9

RN11H

0.1UF/25V

<8,17> M_B_CAS#

4

56Ohm

13

RN13D

GND

GND

<8,17> M_B_RAS#

8

56Ohm

9

RN16H

+1.8V

<8,17> M_B_WE#

3

56Ohm

14

RN13C

SCS0#

2

56Ohm

15

RN15B

1

2

CN5A

C

<7,16>

SCS0#

SCS1#

2

56Ohm

15

RN12B

3

0.1UF/25V

C

<7,16>

SCS1#

4

CN5B

SCS2#

6

56Ohm

11

RN13F

5

0.1UF/25V

<7,17>

SCS2#

6

CN5C

SCS3#

7

56Ohm

10

RN13G

7

0.1UF/25V

<7,17>

SCS3#

8

CN5D

5

56Ohm

12

RN12E

0.1UF/25V

<8,16> M_A_CAS#

R5778

6

56Ohm

11

RN12F

<8,16> M_A_WE#

Do Not Stuff

1%

GND

/X

VTT_REF

M_A_A10 56Ohm

2

1

R78

0.1UF/16V

1

2

C166

M_A_BS#0 56Ohm

2

1

R79

R5779

Do Not Stuff

1%

GND

/X

GND

M_A_A1

8

56Ohm

9

RN14H

M_A_A3

7

56Ohm

10

RN14G

M_A_A5

5

56Ohm

12

RN14E

1

2

CN6A

M_A_A9

4

56Ohm

13

RN14D

3

0.1UF/25V

4

CN6B

M_A_A12

3

56Ohm

14

RN14C

5

0.1UF/25V

6

CN6C

M_A_BS#2

1

56Ohm

16

RN14A

7

0.1UF/25V

8

CN6D

B

M_A_A11

2

56Ohm

15

RN14B

0.1UF/25V

B

M_A_A[0..13]

<8,16>

M_A_A6

6

56Ohm

11

RN14F

GND

M_A_BS#[0..2]

<8,16>

M_A_A2

4

56Ohm

13

RN15D

M_B_A[0..13]

<8,17>

M_A_A4

3

56Ohm

14

RN15C

M_A_A0

8

56Ohm

9

RN12H

1

2

CN7A

SCKE1

8

56Ohm

9

RN15H

3

0.1UF/25V

4

CN7B

M_B_A7

1

56Ohm

16

RN16A

5

0.1UF/25V

M_B_BS#[0..2]

<8,17>

6

CN7C

M_B_A4

3

56Ohm

14

RN16C

7

0.1UF/25V

8

CN7D

M_B_A11

1

56Ohm

16

RN11A

0.1UF/25V

SCKE[0:3]

<7,16,17>

M_B_A6

4

56Ohm

13

RN11D

GND

ODT[0:3]

<7,16,17>

M_B_A2

2

56Ohm

15

RN16B

M_B_A0

7

56Ohm

10

RN16G

M_B_A12

7

56Ohm

10

RN11G

1

2

CN8A

M_B_A9

6

56Ohm

11

RN11F

3

0.1UF/25V

4

CN8B

M_B_A8

5

56Ohm

12

RN11E

5

0.1UF/25V

6

CN8C

M_B_A5

6

56Ohm

11

RN16F

7

0.1UF/25V

8

CN8D

M_B_A3

5

56Ohm

12

RN16E

0.1UF/25V

M_B_A1

4

56Ohm

13

RN16D

GND

A

M_B_A10

56Ohm

2

1

R80

0.1UF/16V

1

2

C167

A

M_B_A13

56Ohm

2

1

R81

GND

1.1

Title : DDR2 TERMINATION

ASUSTeK COMPUTER INC. NB1

Engineer:

Alan Chen

Size

Project Name

Rev

Custom

Z96S

2.0

Date:

,

30, 2007

Sheet

18

of

67

5

4

3

2

1

E

D

C

B

A

GPU NB8P-SE

Place beside GPU

+3VS

GPU_THER M

GR1

1

2

2KOhm

1%

GR2

2

1

CRT_RED

+3VS

+3VS

150Ohm

1%

U5L

U5F

GC1

2

1

GPU_CLAMP

L_BKLT EN_V

GR3

1

2

2KOhm

1%

GL1

DACA_VDD_10MIL

5.6PF/50V

NC

F6

1

2

130mA

AD10

DACA_VDD

I2CA_SCL

K2

CRT_DDC_CLK <26>

DACA_VREF

I2CA_SDA

J3

CRT_DDC_DATA

<26>

GPU_THERM -

P/H or P/D R must be 2K or less

GND

120Ohm/10 0Mhz

AH10

DACA_VREF

J1

THERMDN

I2CC_SCL

G2

EDID_CLK

<27>

GPU_GPIO

I/O

ACTIVE

FUNCTION(NB8x)

G1

DACA_RSET

AH9

AF10

GR4

2

1

CRT_GREEN

GPU_THE RM+ K1

I2CC_SDA

EDID_DAT

<27>

0

IN

H(FAE)

PRI DVI Hot Plug

DACA_RSET

DACA_HSYNC

AK10

CRT_HSYNC

<26>

150Ohm

1%

THERMDP

1

IN

H(FAE)

2nd DVI Hot Plug

DACA_VSYNC

CRT_VSYNC

<26>

GPU_HP_DET 0

D

GC2

GC3

GC4

2

1

GPU_JTAG_ TCK

AJ11

GPIO0

K3

1

GT1

2

OUT

H

LCD backlight Bri.

D

JTAG_TCK

GPIO1

H1

GPU_HP_DET 1

1

GT2

3

OUT

L

LCD Power

4.7UF/6.3V

0.1UF/10V

AH11

5.6PF/50V

GT3

1GPU_J TAG_TMS

AK11

K5

GPU_L_ BL_PWM 1

GT4

4

OUT

H

LCD BL enable

DACA_RED

CRT_RED

<26>

GT5

1GPU_JTAG_TDI

AK12

JTAG_TMS

GPIO2

G5

5

OUT

H

GPU voltage selection

JTAG_TDI

GPIO3

L_VDD_EN

<27>

DACA_GREEN

AJ12

CRT_GREEN

<26>

GT6

1GPU_JTAG_ TDO

AL12

JTAG_TDO

GPIO4

E2

L_BKLT EN_V

<27>

6

OUT

H

GPU voltage selection

GPU_JTAG_T RST_N AL13

J5

GPU_VS0

1

GT7

7

OUT

H

GPU/MEM voltage selection(for GDDR3)

GND

GND

AH12

JTAG_TRST_N

GPIO5

G6

GPU_VS1

1

GT8

8

IN

L

THRM alert I/O

DACA_BLUE

CRT_BLUE

<26>

GR5

2

1

CRT_BLUE

GPIO6

K6

GPU_ VS_MEM 1

GT9

9

OUT

L

FAN_PWM

GPIO7

150Ohm

1%

GR6

GR7

GPIO8

E1

GPU_THER M

GR68 1

2

Do Not /XStuffFORCE_OFF#

10

I/O

N/A

SLI raster sync

GR8

AG9

10KOhm

10KOhm

D2

GPU_FAN_PW M

GR69 1

2

Do Not /XStuffTHRM_A LERT#

11

OUT

H

MEM Vref switch

110Ohm

DACA_IDUMP

GC5

2

1

GPIO9

H5

GPU_SLI_SYNC 1

GT11

12

I/O

N/A

AC power detect input

NB8P-SE

5.6PF/50V

GPIO10

F4

GPU_MVREF_ SW 1

GT12

13

OUT

?

PWR_CTRL0

GPIO11

GPIO12

E3

GPU_AC_DET

1

GT13

14

OUT

?

PWR_CTRL1

DACA_REST

GND

GND

NB8P-SE

=124 ohm

GND

GND

NB8P-GS

0x0407

+3VS

GND

Power by +3VS

G3 Strapping Options

NB8P-SE

0x0425

NB8M-GS

0x0427

GL2

for MIO function

Multiuse Input/Output Interface

(check

NB8M-SE

0x0428

1

2

Power by +2.5V

+3VS

DG-01694-001_v02 for

U5K

No Fuction in G3-64

Board Strap

Board Strap

For SLI function

detail)

120Ohm/10 0Mhz

Z96S

Hardware

(BIOS

(BIOS Not

U5H

10mA

M7

P2

PEX_PLL_EN_TERM

PIN Name

Function

MIOA_VDDQ1

MIOAD0

Setting

default

Present)

Present)

DACB_VDD

M8

MIOA_VDDQ2

MIOAD1

N2

SUB_VENDOR

180mA

V8

R8

N1

0

MIOAD1

SUB_VENDOR

1

Not Require

2K P/D Require

DACB_VDD

MIOA_VDDQ3

MIOAD2

DACB_VREF

T8

MIOA_VDDQ4

MIOAD3

N3

MIOBD0

RAMCFG0

-

Check FAE

Check FAE

R5

DACB_VREF

Place beside GPU

U9

MIOA_VDDQ5

MIOAD4

M1

MIOBD1

RAMCFG1

-

2K P/U,P/D

2K P/U,P/D

M3

MIOBD8

RAMCFG2

-

Recommand

Recommand

R7

GC7

MIOAD5

P5

3GIO_PADCFG0

MIOBD9

RAMCFG3

-

DACB_RSET

TV_C

MIOAD6

GC6

GR9

2

1

TV_C

<29>

MIOAD7

N6

3GIO_PADCFG1

MIOBD2

CRYSTAL

0(27M)

Not Require

Not Require

4.7UF/6.3V

150Oh m

1%

0.1UF/10V

MIOAD8

N5

MIOBD6

TVMODE2

0

Not Require

Not Require

GC8

M4

3GIO_PADCFG2

MIOAD7

TVMODE0

1

0.1UF/10V

R6

TV_C

GC9

2

1

MIOAD9

L4

MIOAD10

TVMODE1

0

DACB_RED

MIOAD10

TV_Y

Do Not Stuff

/X

GT20

1

L1

MIOACAL_PD_VDDQ

MIOAD11

L5

1

GT21

MIOBD4

PCI_DEVID0

0

2K P/U

DACB_GREEN

T5

GND

MIOBD5

PCI_DEVID1

0

Not Require

Recommand

GND

GT22

1

L3

MIOBD3

PCI_DEVID2

0

GND

GR10

T6

TV_C VBS

MIOACAL_PU_GND

MIOBD11

PCI_DEVID3

0

DACB_BLUE

127Oh m

MIOB_CTL3 PCI_DEVID4

0

1%

GR11

2

1

TV_Y

TV_Y

<29>

MIOAD2

USER0

-

If LCD

If LCD

DACB_IDUMP

V7

150Oh m

1%

GT23

1

L2

MIOA_VREF

MIOAD3

USER1

-

no EDID

no EDID

C

MIOAD4

USER2

-

C

NB8P-SE

GC10

2

1

MIOAD5

USER3

-

10K P/U

10K P/U

Do Not Stuff

/X

MIOBD10

ROMTYPE0

1

orNo P/DRequire if

orNo P/Drequire

GR10 from 124 ohm change to 127 ohm

MIOB_VSYNC

ROMTYPE1

1

SPI ROM used

GND

for Macrovision test

GND

MIOAD6

3GIO_PADCFG0

0

Not Require

2K P/U

MIOAD8

3GIO_PADCFG1

0

Require

TV_CV BS

MIOA_HSYNC

R3

SLOT_CLOCK_CFG

MIOAD9

3GIO_PADCFG2

0

GR12

2

1

R1

1

GT24

MIOB_HSYNC

3GIO_PADCFG3

0

TV_CV BS

<29>

MIOA_VSYNC

+1.25VS

150Oh m

1%

MIOA_DE

P1

1

GT25

MIOAD0

PEX_PLL_EN_TERM

0

2K P/U Recommand2K P/U Recommand

MIOA_CTL3

P3

1

GT26

MIOA_HSYNC

SLOT_CLOCK_CFG

1(Share) Not Require

Not Require GPU & MCD share CLOCK

GL3

GC11

2

1

MIOBD7

PCI_IOBAR

1

Not Require

Not Require

1

2

GPU_PLVDD

139mA

U5M

Do Not Stuff

/X

R4

1

GT27

MIOB_DE

BAR2_SIZE

0

Not Require

Not Require

MIOA_CLKOUT

RAM_CFG[3:0] Config FB Bus Width Definitions

120Ohm/10 0Mhz

GND

MIOA_CLKOUT_N

P4

1

GT28

NC

M5

2

1

T9

PLLVDD

0001 16Mx16 DDR2 128-bit Samsung, Micron

T10

DISP_PLLVDD

GPU_XTALOU TBUFF

GR13

GR57

GC12

2

1 10KOhm

NB8P-SE

10KOhm

0010 16Mx16 DDR2 128-bit Qimonda

0.1UF/10V

U10

PLLGND

GND

0011 16Mx16 DDR2 128-bit Hynix

Power by +3VS

+3VS

GND

for MIO function

U5N

GND

GND

1001 16Mx16 DDR2 64-bit Samsung, Micron

RAMCFG0

Power by +2.5V

10mA

AA8

MIOB_VDDQ1

MIOBD0

AC3

1010 16Mx16 DDR2 64-bit Qimonda

T1

T2

RAMCFG1

<25> CLK_27M_G PU_SS

XTALSSIN

XTALOUTBUFF

For SLI function

AB7

MIOB_VDDQ2

MIOBD1

AC1

1011 16Mx16 DDR2 64-bit Hynix

AB8

AC2

1

GT29

+1.25VS

AC6

MIOB_VDDQ3

MIOBD2

AB2

PCI_DEVID2

U1

U2

GPU_XTALOUT

1

GT30

MIOB_VDDQ4

MIOBD3

<25> CLK_27M_ GPU

XTALIN

XTALOUT

AC7

MIOB_VDDQ5

MIOBD4

AB1

PCI_DEVID0

GL4

GPU_DISP_PLVDD

MIOBD5

AA1

PCI_DEVID1

1

2

36mA

NB8P-SE

AB3

GC13

MIOBD6

PCI_IOBAR

+3VS

+3VS

+3VS

+3VS

120Ohm/10 0Mhz

MIOBD7

AA3

0.1UF/10V

MIOBD8

AC5

RAMCFG2

CLK_27M_GP U_SS

MIOBD9

AB5

RAMCFG3

GC14

MIOBD10

AB4

PCI_DEVID3

0.1UF/10V

GT34

1

Y1

AA5

MIOBCAL_PD_VDDQ

MIOBD11

GR22

This stuff is for using internal SS

GND

NC24

W3

GR14

GR15

GR16

GR17

Do Not Stuff

instead of external.

GT35

1

Y3

MIOBCAL_PU_GND

NC25

V1

Do Not Stuff

10KOhm

Do Not Stuff

Do Not Stuff

/X

NC26

Y5

/X

/X

/X

GND

W1

NC27

RAMCFG0

RAMCFG1

RAMCFG2

RAMCFG3

B

Serial ROM Access Signals

GT36

1

Y2

MIOB_VREF

B

GND

W4

U5E

NC28

W5

GR18

GR19

GR20

GR21

NC29

NC30

V5

10KOhm

Do Not Stuff

10KOh m

10KOhm

ROMCS_N

AA4

Integrated Single-Link TMDS Transmitter Interface, Link C

NC31

Y6

/X

F1

NC14

AA6

ROM_SO

AE26

NC15

ROM_SI

W2

1

GT40

U5J

MIOB_VSYNC

AE3

3GIO_PADCFG3

AD26

NC16

ROM_SCLK

AA7

1

GT41

GC15

0.01UF/16V

MIOB_HSYNC

AF3

GND

GND

GND

GND

AH31

1

2

AK3

AM3

AD1

BAR2_SIZE

AH32

NC17

IFPCD_VPROBE

IFPC_TXC_N

AM2

MIOB_DE

AD3

PCI_DEVID4

Check stuff before BOM release

NC18

G3 N.C. IF HDCP is

IFPC_TXC

MIOB_CTL3

I2CH_SCL

I2CH_SDA

H3

not used

+3VS

GR23 2

1

AH3

IFPCD_RSET

AE1

AD4

1

GT38

+3VS

1KOhm 1%

IFPC_TXD0_N

AE2

MIOB_CLKOUT

AD5

1

GT39

IFPC_TXD0

MIOB_CLKOUT_N

U3

GPIO13

MIOB_CLKIN

AE4

GPU_MIOB_CLKIN

PEX_ PLL_EN_TERM GR24 1

V3

NC19

F3

GR34

GND

90mA

AF2

2

Do Not Stuff1%

/X

U6

NC20

BUFRST_N

GPU_IFPCD_PLLVDD

AA10

IFPCD_PLLVDD

IFPC_TXD1_N

PCI_DEVID0

U5

DACB_CSYNC

10KOh m

IFPC_TXD1

AF1

NB8P-SE

GR27

GR25 1

2

2KOhm

1%

U4

GPIO14

STEREO

T3

Internal

10KOhm

PCI_DEVID1

V4

GR26 1

2

Do Not Stuff1%

/X

NC21

GPU_SWAPRDY

test

V6

NC22

SWAPRDY_A

M6

only

GR29

IFPC_TXD2_N

AH1

PCI_DEVID2

GR55

GPU_ TESTMEMCLK

10KOhm

IFPC_TXD2

AG1

GR28 1

2

2KOhm

1%

Do Not Stuff

NC23

A26

/X

H2

GPU_T ESTMODE

AB10

PCI_DEVID3

GR30 1

2

Do Not Stuff1%

/X

TESTMODE

AL10

IFPCD_PLLGND

GND

GND152

PCI_DEVID4

GND153

AG13

GR31 1

2

Do Not Stuff1%

/X

GR40

GR59

GND

GND

10KOhm

10KOhm

+3VS

3GIO_PADCFG0

GR32 1

2

2KOhm

1%

GND

NB8P-SE

IFPD_TXC_N

AH2

Spread Spectrum

IFPD_TXC

AG3

GPU Temperature

3GIO_PADCFG1

GR33 1

2

Do Not Stuff1%

/X

GND

50mA

GR37

200 ohm for

3GIO_PADCFG2

GR35 1

Do Not Stuff1%

/X

2

+3VS

+3VS_SS

GPU_IFPC_IOVDD

AD6

IFPC_IOVDD

IFPD_TXD4_N

AJ1

MAXIM 6657

3GIO_PADCFG3

GND

GND

IFPD_TXD4

AK1

0Ohm

GR36 1

2

Do Not Stuff1%

/X

GL12

/X

Down Spread

AE7

IFPD_IOVDD

Do Not Stuff

Spectrum for EMI

-----SRS

:

0

/ 1

/ NC.

GU1

Default 0;DG-01649-001_V02

1

2

Attenuation

P1819B

: -1.25

-1.75

x.

GR38

IFPD_TXD5_N

AL1

1KOhm

IFPD_TXD5

AL2

<21,28,4 4>

SMB1_ CLK

8

SMBCLK

VCC

1

GPU_THE RM+

GC16

2200PF/50V

MK1726

:

-1.8

-2.5

-0.6.

1%

<21,28,4 4>

SMB1_DAT

7

SMBDATA

DXP

2

1

2

GC151

GC152

6

3

GPU_THERM -

BAR2_SIZE

GR39 1

2

Do Not Stuff1%

/X

Do Not Stuff

Do Not Stuff

AJ3

<28,44> THRM_AL ERT#

5

ALERT#

DXN

4

FORCE_OFF#

A

IFPD_TXD6_N

GND

THERM#

FORCE_OFF#

<28,32,44,49,63>

PCI_IOBAR

A

/X

/X

IFPD_TXD6

AJ2

GR58 1

2

Do Not Stuff1%

/X

GR62

Do Not Stuff/X

GND

G781

1

2

+3VS_SS

50mA

3.0V~5.5V

To EC

SUB_VENDOR

GND

GND

VGA_SRS

1

2

GPU_IFPD_IOVDD

GND

GC17

GR41 1

2

2KOhm

1%

GND

Max: 1mA

SLOT_CLOCK_CFG GR42 1

2

Do Not Stuff1%

/X

0.1UF/10V

GR67

GR63

Do Not Stuff/X

NB8P-SE

Do Not Stuff/X

GR43

GPU_XTALOU TBUFF

1

2

+3VS_SS

1KOhm

NO TMDS--

GR64

GU2

1%

IFPx_IOVDD

1.1

GND

Do Not Stuff/X

1K ohm

to

GND

CLK_27M_ GPU

1

2

1

VSS

VDD

8

GND

Title : GPU_MAIN(1)

2

7

XIN

XOUT

CLK_27M_GP U_SS

VGA_SRS

3

SRS

PD#

6

CLK_27M_ GPU

GND

ASUSTek COMPUTER INC

Engineer:

Alan Chen

2

1

4

5

1

2

ModOUT REF

GR65

Do Not Stuff

GR66

Size

Project Name

Rev

Do Not Stuff

GND

/X

Do Not Stuff

Custom

Z96S

2.0

/X

/X

Date:

,

30, 2007

Sheet

19

of

67

YAGEO/RC0603FR-07121RL

<G>

E

D

C

B

A

5

4

3

2

1

<23> GMAA[12..0]

<23>

QSA#[7..0]

MDA[63..32]

<23>

GMBA[5:2]

<23>

FBVDD/Q/VTT 4820mA

<23> QSA[7..0]

<23> DQMA#[7..0]

MDA[31..0]

<23>

GMABA[2:0]

<23>

+1.8VS

U5B

MDA0

N27

FBAD0

FBVDD1

A12

MDA1

M27

A15

2

1

FBAD1

FBVDD2

MDA2

N28

FBAD2

FBVDD3

A18

GR60

0Ohm

MDA3

L29

FBAD3

FBVDD4

A21

MDA4

K27

A24

FBAD4

FBVDD5

CHECK FAE for delete (OUTPUT)

MDA5

K28

FBAD5

FBVDD6

A27

MDA6

J29

FBAD6

FBVDD7

A3

MDA7

J28

A30

FBAD7

FBVDD8

D

MDA8

P30

FBAD8

FBVDD9

A6

D

MDA9

N31

A9

MLCC 0.01UF/16V (0402) X7R 10%

U5I

MDA10

N30

FBAD9

FBVDD10

AA32

/X

Do Not Stuff

GC23

FBAD10

FBVDD11

MDA11

N32

FBAD11

FBVDD12

AD32

2

1

IFPAB_VPROBE

AM4

IFPAB_VPROBE

IFPA_TXC_N

AJ9

LVDS_LCLKN

<27>

MDA12

L31

AG32

AK9

FBAD12

FBVDD13

IFPA_TXC

LVDS_LCLKP

<27>

MDA13

L30

FBAD13

FBVDD14

AK32

IFPAB_REST

MDA14

J30

FBAD14

FBVDD15

C32

GND

1

2

AL5

IFPAB_RSET

MDA15

L32

F32

AJ6

FBAD15

FBVDD16

IFPA_TXD0_N

LVDS_L0N

<27>

MDA16

H30

FBAD16

FBVDD17

J32

GR44 1KOhm

1%

IFPA_TXD0

AH6

LVDS_L0P

<27>

MDA17

K30

M32

+1.8VS

+1.8VS

GND

MDA18

FBAD17

FBVDD18

+1.8VS

GL5

H31

R32

MDA19

F30

FBAD18

FBVDD19

V32

2

1

2

1

IFPAB_PLLVDD_15MIL

80mA

AC9

AH7

LVDS_L1N

<27>

MDA20

FBAD19

FBA_CMD28

IFPAB_PLLVDD

IFPA_TXD1_N

H32

FBAD20

GR61

0Ohm

IFPA_TXD1

AH8

LVDS_L1P

<27>

MDA21

E31

120Ohm/100Mhz

GC97

FBAD21

MDA22

D30

FBAD22

FBVDDQ1

AA25

GC24

MDA23

E30

AA26

GC108

GC111

GC95

GC94

GC93

GC19

0.1UF/10V

1UF/6.3V

AK8

MDA24

H28

FBAD23

FBVDDQ2

AB25

GC91

IFPA_TXD2_N

AJ8

LVDS_L2N

<27>

FBAD24

FBVDDQ3

IFPA_TXD2

LVDS_L2P

<27>

MDA25

H29

FBAD25

FBVDDQ4

AB26

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not StuffDo Not Stuff

Do Not Stuff

Do Not Stuff

MDA26

E29

G11

/X

/X

/X

/X

/X

/X

/X

AD9

FBAD26

FBVDDQ5

IFPAB_PLLGND

MDA27

J27

FBAD27

FBVDDQ6

G12

+1.8VS

GND

GND

IFPA_TXD3_N

AH5

MDA28

F27

FBAD28

FBVDDQ7

G15

IFPA_TXD3

AJ5

MDA29

E27

G18

FBAD29

FBVDDQ8

GL10

MDA30

E28

FBAD30

FBVDDQ9

G21

GND

MDA31

F28

FBAD31

FBVDDQ10

G22

GND

2

1

IFPB_TXC_N

AL4

LVDS_UCLKN

<27>

MDA32

AD29

H11

AK4

FBAD32

FBVDDQ11

IFPB_TXC

LVDS_UCLKP

<27>

MDA33

AE29

H12

120Ohm/100Mhz

MDA34

FBAD33

FBVDDQ12

GC27

AD28

FBAD34

FBVDDQ13

H15

MDA35

AC28

FBAD35

FBVDDQ14

H18

0.1UF/10V

45mA

AF9

IFPA_IOVDD

IFPB_TXD4_N

AM5

LVDS_U0N

<27>

MDA36

+1.8VS

AB29

FBAD36

FBVDDQ15

H21

IFPB_TXD4

AM6

LVDS_U0P

<27>

MDA37

AA30

FBAD37

FBVDDQ16

H22

45mA

AF8

IFPB_IOVDD

MDA38

Y28

FBAD38

FBVDDQ17

L25

GL11

MDA39

AB30

L26

GND

AL7

LVDS_U1N

<27>

MDA40

AM30

FBAD39

FBVDDQ18

M25

2

1

IFPB_TXD5_N

AM7

MDA41

AF30

FBAD40

FBVDDQ19

M26

IFPB_TXD5

LVDS_U1P

<27>

FBAD41

FBVDDQ20

MDA42

AJ31

FBAD42

FBVDDQ21

R25

120Ohm/100Mhz

MDA43

AJ30

R26

GC98

AK5

MDA44

AJ32

FBAD43

FBVDDQ22

V25

0.1UF/10V

IFPB_TXD6_N

AK6

LVDS_U2N

<27>

FBAD44

FBVDDQ23

IFPB_TXD6

LVDS_U2P

<27>

MDA45

AK29

FBAD45

FBVDDQ24

V26

MDA46

AM31

FBAD46

MDA47

AL30

FBAD47

IFPB_TXD7_N

AL8

C

MDA48

AE32

FBAD48

GND

IFPB_TXD7

AK7

C

MDA49

AE30

+1.8VS

FBAD49

NB8P-SE

MDA50

AE31

FBAD50

MDA51

AD30

MDA52

AC31

FBAD51

P32

GMAA3

FBAD52

FBA_CMD0

MDA53

AC32

FBAD53

FBA_CMD1

U27

GMAA0

MDA54

AB32

P31

GMAA2

MDA55

AB31

FBAD54

FBA_CMD2

U30

GMAA1

GC25

GC109

GC110

GC26

GC112

MDA56

AG27

FBAD55

FBA_CMD3

Y31

GMBA3

FBAD56

FBA_CMD4

GMBA3

<23>

MDA57

AF28

W32

GMBA4

1UF/6.3V

1UF/6.3V

1UF/6.3V

1UF/6.3V

1UF/6.3V

MDA58

AH28

FBAD57

FBA_CMD5

W31

GMBA5

GMBA4

<23>

FBAD58

FBA_CMD6

GMBA5

<23>

MDA59

AG28

FBAD59

FBA_CMD7

T32

GMABA2

GMABA2

<23>

MDA60

AG29

V27

CSA0#

MDA61

AD27

FBAD60

FBA_CMD8

T28

WEA0#

CSA0#

<23>

FBAD61

FBA_CMD9

WEA0#

<23>

MDA62

AF27

FBAD62

FBA_CMD10

T31

GMABA0

GMABA0

<23>

MDA63

AE28

U32

CKEA0

FBAD63

FBA_CMD11

W29

VMA_ODT0_R

CKEA0

<23>

GND

FBA_CMD12

W30

GMBA2

DQMA#0

M29

FBA_CMD13

T27

GMAA12

GMBA2

<23>

DQMA#1

M30

FBADQM0

FBA_CMD14

V28

RASA0#

FBADQM1

FBA_CMD15

RASA0#

<23>

DQMA#2

G30

V30

GMAA11

DQMA#3

F29

FBADQM2

FBA_CMD16

U31

GMAA10

FBADQM3

FBA_CMD17

DQMA#4

AA29

FBADQM4

FBA_CMD18

R27

GMABA1

GMABA1

<23>

DQMA#5

AK30

V29

GMAA8

GR45

0Ohm

DQMA#6

AC30

FBADQM6

FBA_CMD20

T30

GMAA9

VMA_ODT0_R

2

1

ODTA0

<23>

DQMA#7

AG30

FBADQM7

FBA_CMD21

W28

GMAA6

R29

GMAA5

FBA_CMD22

FBA_CMD23

R30

GMAA7

QSA0

L28

FBADQS_WP0

FBA_CMD24

P29

GMAA4

GR46

Do Not Stuff

QSA1

K31

U28

CASA0#

GPU_FBA_DEBUG

2

1/X

QSA2

G32

FBADQS_WP1

FBA_CMD25

Y32

VMA_CMD26 1

CASA0#

<23>

FBADQS_WP2

FBA_CMD26

QSA3

G28

FBADQS_WP3

GT43

QSA4

AB28

FBADQS_WP4

QSA5

AL32

FBADQS_WP5

FBA_CLK0

P28

CLKA0

CLKA0

<23>

NB8P Sample Version

QSA6

AF32

FBADQS_WP6

FBA_CLK0_N

R28

CLKA0#

CLKA0#

<23>

(ref E463 demo

QSA7

AH30

Y27

CLKA1

FBADQS_WP7

FBA_CLK1

CLKA1

<23>

FBA_CLK1_N

AA27

CLKA1#

CLKA1#

<23>

circuit)

QSA#0

M28

FBADQS_RN0

QSA#1

K32

FBADQS_RN1

QSA#2

G31

FBADQS_RN2

B

QSA#3

G27

FBADQS_RN3

B

QSA#4

AA28

FBADQS_RN4

QSA#5

AL31

FBADQS_RN5

QSA#6

AF31

FBADQS_RN6

QSA#7

AH29

FBADQS_RN7

Y30

1

FBA_CMD27

NC6

AC26

GT44

FBA_DEBUG

AC27 GPU_FBA_DEBUG

NC7

D32

NC8

D31

+1.25VS

GL6

+1.8VS

H_PLLVDD

G23

15mA

GPU_H_PLVDD+1.2V

1

2

FB_PLLAVDD

G25 GPU_FBA_PLAVDD+1.2V

GC28

GC29

120Ohm/100Mhz

GR47

FB_PLLGND

G24

0.1UF/10V

1UF/6.3V

1KOhm

1%

GND

GND

+1.25VS

GND

GPU_MVREF

E32

FB_VREF

GL7

GR48

42mA

1

2

1KOhm

120Ohm/100Mhz

1%

GC30

GC31

GC32

0.1UF/10V

0.1UF/10V

1UF/6.3V

NB8P-SE

GND

GND

GND

GND

A

A

1.1

Title : GPU_Memory(2)

ASUSTek COMPUTER INC

Engineer:

Alan Chen

Size

Project Name

Rev

Custom

Z96S

2.0

Date:

,

30, 2007

Sheet

20

of

67

5

4

3

2

1

5

4

3

2

1

<24>

GMAB[12..0]

<24>

QSB[7..0]

MDB[31..0]

<24>

<24>

DQMB#[7..0]

<24>

QSB#[7..0]

MDB[63..32]

<24>

FBVDD/Q/VTT 4820mA

+1.8VS

D

U5C

MDB0

B7

AA23

+1.8VS

MDB1

A7

FBCD0

FBVTT1

AB23

MDB2

C7

FBCD1

FBVTT2

H16

MDB3

A2

FBCD2

FBVTT3

H17

MDB4

B2

FBCD3

FBVTT4

J10

MDB5

C4

FBCD4

FBVTT5

J23

GC114

GC34

GC35

GC36

GC116

MDB6

A5

FBCD5

FBVTT6

J24

130mA

MDB7

B5

FBCD6

FBVTT7

J9

0.1UF/10V

1UF/6.3V

1UF/6.3V

1UF/6.3V

1UF/6.3V

MDB8

F9

FBCD7

FBVTT8

K11

MDB9

F10

FBCD8

FBVTT9

K12

DACB_VDD

MDB1 0

D12

FBCD9

FBVTT10

K21

MDB1 1

D9

FBCD10

FBVTT11

K22

MDB1 2

E12

FBCD11

FBVTT12

K24

FBCD12

FBVTT13

MDB1 3

D11

FBCD13

FBVTT14

K9

GR49

MDB1 4

E8

L23

GND

10KOhm

MDB1 5

D8

FBCD14

FBVTT15

M23

MDB1 6

E7

FBCD15

FBVTT16

T25

MDB1 7

F7

FBCD16

FBVTT17

U25

MDB1 8

D6

FBCD17

FBVTT18

FBCD18

MDB1 9

D5

FBCD19

MDB2 0

D3

GND

MDB2 1

E4

FBCD20

+1.8VS

FBCD21

MDB2 2

C3

FBCD22

MDB2 3

B4

MDB2 4

C10

FBCD23

MDB2 5

B10

FBCD24

MDB2 6

C8

FBCD25

FBCD26

MDB2 7

A10

GC113

GC33

GC115

GC37

FBCD27

MDB2 8

C11

FBCD28

MDB2 9

C12

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

MDB3 0

A11

FBCD29

/X

/X

MDB3 1

B11

FBCD30

FBCD31

MDB3 2

B28

MDB3 3

C27

FBCD32

FBCD33

MDB3 4

C26

FBCD34

MDB3 5

B26

MDB3 6

C30

FBCD35

GND

MDB3 7

B31

FBCD36

C

MDB3 8

C29

FBCD37

FBCD38

MDB3 9

A31

FBCD39

MDB4 0

D28

MDB4 1

D27

FBCD40

FBCD41

MDB4 2

F26

MDB4 3

D24

FBCD42

FBCD43

MDB4 4

E23

MDB4 5

E26

FBCD44

MDB4 6

E24

FBCD45

MDB4 7

F23

FBCD46

FBCD47

MDB4 8

B23

MDB4 9

A23

FBCD48

MDB5 0

C25

FBCD49

FBCD50

MDB5 1

C23

MDB5 2

A22

FBCD51

C13

GMAB3

MDB5 3

C22

FBCD52

FBC_CMD0

A16

GMAB0

MDB5 4

C21

FBCD53

FBC_CMD1

A13

GMAB2

MDB5 5

B22

FBCD54

FBC_CMD2

B17

GMAB1

MDB5 6

E22

FBCD55

FBC_CMD3

B20

GMBB3

GMBB3

<24>

MDB5 7

D22

FBCD56

FBC_CMD4

A19

GMBB4

MDB5 8

D21

FBCD57

FBC_CMD5

B19

GMBB5

GMBB4

<24>

MDB5 9

E21

FBCD58

FBC_CMD6

B14

GMBBA2

GMBB5

<24>

MDB6 0

E18

FBCD59

FBC_CMD7

E16

CSB0#

GMBBA2

<24>

MDB6 1

D19

FBCD60

FBC_CMD8

A14

WE B0#

CSB0#

<24>

MDB6 2

D18

FBCD61

FBC_CMD9

C15

GMBBA0

WEB 0#

<24>

MDB6 3

E19

FBCD62

FBC_CMD10

B16

CKEB0

GMBBA0

<24>

FBCD63

FBC_CMD11

F17

VMB_OD T0_R

CKEB0

<24>

FBC_CMD12

C19

GMBB2

GMBB2

<24>

DQMB #0

A4

FBC_CMD13

D15

GMAB12

DQMB #1

E11

FBCDQM0

FBC_CMD14

C17

RASB0 #

RASB0#

<24>

DQMB #2

F5

FBCDQM1

FBC_CMD15

A17

GMAB11

DQMB #3

C9

FBCDQM2

FBC_CMD16

C16

GMAB10

DQMB #4

C28

FBCDQM3

FBC_CMD17

D14

GMBBA1

GMBBA1

<24>

DQMB #5

F24

FBCDQM4

FBC_CMD18

F16

GMAB8

DQMB #6

C24

FBCDQM5

FBC_CMD19

C14

GMAB9

DQMB #7

E20

FBCDQM6

FBC_CMD20

C18

GMAB6

FBCDQM7

FBC_CMD21

E14

GMAB5

FBC_CMD22

B13

GMAB7

GR50

0Ohm

QSB0

C5

FBC_CMD23

E15

GMAB4

VMB_OD T0_R

2

1

ODTB0

<24>

QSB1

E10

FBCDQS_WP0

FBC_CMD24

F15

CASB0 #

CASB0#

<24>

QSB2

E5

FBCDQS_WP1

FBC_CMD25

A20

VMB_C MD26 1

B

QSB3

B8

FBCDQS_WP2

FBC_CMD26

GT45

QSB4

A29

FBCDQS_WP3

GR51

Do Not Stuff

QSB5

D25

FBCDQS_WP4

E13

CLKB0

CLKB0

<24>

GPU_FBB_DEBUG

2

1

QSB6

B25

FBCDQS_WP5

FBC_CLK0

F13

CLKB0#

QSB7

F20

FBCDQS_WP6

FBC_CLK0_N

F18

CLKB1

CLKB0#

<24>

/X

FBCDQS_WP7

FBC_CLK1

E17

CLKB1#

CLKB1

<24>

QSB# 0

C6

FBC_CLK1_N

CLKB1#

<24>

NB8P Sample Version

FBCDQS_RN0

(ref E463 demo

QSB# 1

E9

QSB# 2

FBCDQS_RN1

E6

FBCDQS_RN2

circuit)

QSB# 3

A8

QSB# 4

B29

FBCDQS_RN3

FBCDQS_RN4

QSB# 5

E25

QSB# 6

A25

FBCDQS_RN5

FBCDQS_RN6

QSB# 7

F21

FBCDQS_RN7

FBC_CMD27

C20

D1

NC10

F12

GPU_FBB_DEBUG

+3VS

FBC_DEBUG

GPU_I2CS_SDA

I2CS_SDA

B1

8

4.7KOhm

7

GRN1D

C1

GPU_I2CS_SCL

6

5

GRN1C

I2CS_SCL

4.7KOhm

GR70 1

2

Do Not /XStuff

SMB1_DAT <19,28,44 >

GR71 1

Do Not /XStuff

2

SMB1_ CLK <19,28,44 >

NC11

G8

NC12

G10

NC13

G9

+1.8VS

A28

NC9

FBCAL_PD_VDDQ

K26

GPU_FBCAL_PD_VDDQ

GR52 1

2

40.2Ohm

FBCAL_PU_GND

H26

GPU_FBCAL_PU_GND

GR53 1

2

40.2Ohm

FBCAL_TERM_GND

J26

GPU_FBCAL_THRM_GND

GR54 1

2

Do Not Stuff

A

/X

NB8P-SE

GND

D

U5G

+3VS

AD7

DACC_VDD

I2CB_SCL

H4

GPU_I2CB_SCL

4

4.7KOhm

3

GRN1B

J4

GPU_I2CB_SDA

2

1

GRN1A

AH4

DACC_VREF

I2CB_SDA

4.7KOhm

AF5

AG7

DACC_RSET

DACC_HSYNC

AG5

DACC_VSYNC

DACC_RED

AF6

DACC_GREEN

AG6

DACC_BLUE

AE5

DACC_IDUMP

AG4

NB8P-SE

GND

C

B

A

1.1

		Title :GPU_PCI-E(3)
ASUSTek COMPUTER INC		Engineer:	Alan Chen
Size	Project Name			Rev
Custom	Z96S			2.0
Date:	, 30, 2007	Sheet	21 of 67

5		4	3	2	1