Page 1
T668 MLB
w w w . t e k n i s i - i n d o n e s i a . c o m
DATE SYNC CONTENTS CSA PAGE DATE SYNC CONTENTS CSA PAGE
1
2
3
1
2
4
5
5
6
7
8
9
10 SOC: POWER (DDR,SRAM)
11
12
13
14
6
7
8
9
10
11
12
13
14
15
TABLE OF CONTENTS
REFERENCE DESIGN SYNC TABLES
PD PARTS
SOC: Support
SOC: CIO, USB, RESETS, CLOCKS, SWD
SOC: AP I/Os
SOC: LPDP & MIPI
SOC: PCIE
SOC: AOP
SOC: POWER (IO)
SOC: POWER (SOC, CPU, GPU)
SOC: POWER (SRAM)
SOC: POWER (Fixed, PLL's, Filtered)
T668_MLB
T668_KSAITO_MLB_0.11.1
T585_REF_SOC_H13G_0.56.0
AITKEN_T668_MLB
T585_REF_SOC_H13G_0.56.0
AITKEN_T668_MLB
ANDREW_T668_MLB
T585_REF_SOC_H13G_0.56.0
T585_REF_SOC_H13G_0.56.0
T585_REF_SOC_H13G_0.56.0
T585_REF_SOC_H13G_0.56.0
T585_REF_SOC_H13G_0.56.0
T585_REF_SOC_H13G_0.56.0
10/08/2019
10/08/2019
10/09/2019
61
62
63
64 4
65
66
67
68
69
70
71
72
73
74
158
200
201
220
221
224
230
231
236
237
238
239
242
243
USB-C: SUPPORT
WIFI/BT: MODULE07/17/2019
WIFI/BT: ANTENNA and GND
STORAGE: SSD0 S5E <0>
STORAGE: SSD0 S5E <1>
STORAGE: NON OCARINA SUPPORT
STORAGE: SSD SUPPORT
SECDIS: MIPI MUX
DISPLAY: CONNECTOR, PWR
DISPLAY POWER SEQUENCER
BEN: CONTROLLER
BEN: KEYBOARD
SECDIS: AMR
SECDIS: FPGA
T585_REF_USBC_ACE2_0.23.0
REF_WIRELESS_RASPUTIN
REF_WIRELESS_RASPUTIN
REF_STORAGE_S5E
REF_STORAGE_S5E
REF_STORAGE_NON_OCARINA_SUPPORT
WUDI_T668_MLB
T585_REF_SECDIS_MIPIMUX_0.7.0
AITKEN_T668_MLB
REF_PANELPWR_BNJ
REF_BLC_BEN
REF_BLC_BEN
T585_REF_SECDIS_AMR_0.9.0
REF_SECDIS_SAK
02/01/2020
02/01/2020
04/27/2020
04/27/2020
02/25/2020
01/28/2020
10/02/2019
04/22/2020
11/21/2019
11/21/2019
04/22/2020
15
16
17
18
19
20
21
22
23
24
25
26
27
28
16
17
19
21
SOC: GND
SOC: GND-2
SPI NOR
PROJECT SUPPORT (1/2)
22 PROJECT SUPPORT (2/2)
50
Secure Element
BATTERY CONNECTORS 51
52
53
57
58
59
77
78
PBUS SUPPLY & BATTERY CHARGER
BATTERY CHARGER SUPPORT
POWER: 3V8 AON (1/2)
POWER: 3V8 AON (2/2)
POWER: 3V8 AON SUPPORT
PMU: SLAVE INPUT PWR & BUCKS
PMU: SLAVE LDO
T585_REF_SOC_H13G_0.56.0
T585_REF_SOC_H13G_0.56.0
REF_SOC_H13G
AITKEN_T668_MLB
AITKEN_T668_MLB
REF_SE_CERES
AITKEN_T668_MLB
REF_CHARGER_SUONA
REF_CHARGER_SUONA
REF_VR_ICEMAN
REF_VR_ICEMAN
T585_REF_VR_ICEMAN_0.36.0
KEI_T668_MLB
KEI_T668_MLB
01/27/2020
09/18/2019
11/11/2019
02/26/2020
09/18/2019
02/25/2020
04/01/2020
04/09/2020
03/30/2020
04/07/2020
75
77
78
79
80
244
246
247
248
249
250 81
82
83
84
85
86
251
252
253
254
256
87 DFR SUPPORT 1 25704/07/2020
88 258
AUDIO SUPPORT
AUDIO JACK CODEC 245 76
AUDIO AMPLIFIERS (1/2)
AUDIO AMPLIFIERS (2/2)
AUDIO CONNECTORS: AMPS
AUDIO CONNECTORS: DMIC, JACK
KEYBOARD BLC CONNECTORS
KEYBOARD IOX, SUPPORT
KEYBOARD SIGNAL CONNECTOR, ESD
TRACKPAD SUPPORT
TRACKPAD CONNECTOR
TOUCHID SUPPORT
DFR SUPPORT 2
REF_SPKRAMP_TAS5770
REF_CODEC_CLIFDEN
REF_SPKRAMP_TAS5770
REF_SPKRAMP_TAS5770
KELVIN_T668_MLB
KELVIN_T668_MLB
T668_MLB
REF_KBD_SUPPORT
WUDI_T668_MLB
WUDI_T668_MLB
WUDI_T668_MLB
T585_REF_MESA_SUPPORT_0.11.0
T585_REF_DFR_V3_SUPPORT_0.25.0
T585_REF_DFR_V3_SUPPORT_0.25.0
04/16/2020
04/13/2020
04/16/2020
04/16/2020
09/18/2019
09/24/2019
05/16/2019
02/01/2020
01/28/2020
04/16/2020
04/16/2020
30
31
32
33
34
35
36
37
38
39
40
41
42
79 29
80
81
82
83
84
121
123
124
127
128
129
130
131
PMU: SLAVE GPIO & GND
PMU: SLAVE SUPPORT
PMU: MASTER INPUT PWR & BUCKS
PMU: MASTER BUCKS & GND
PMU: MASTER LDO & GPIO
PMU: MASTER SUPPORT
POWER: EXTERNAL LDO
POWER: 5V S2
POWER: 5V S2 SUPPORT
POWER: 3V3 S2
POWER: FETS
POWER: SUPPORT
I2C: SIO, DISP
I2C: ISP, AOP
KEI_T668_MLB
KEI_T668_MLB
KEI_T668_MLB
KEI_T668_MLB
KEI_T668_MLB
KEI_T668_MLB
KEI_T668_MLB
REF_VR_5V_TPS62135
T668_MLB
REF_VR_3V3_TPS62135
KEI_T668_MLB
KEI_T668_MLB
T668_MLB
T668_MLB
04/07/2020
01/27/2020
04/02/2020
04/26/2020
04/23/2020
04/16/2020
09/23/2019
04/16/2020
03/26/2020
01/09/2020
09/10/2019
09/10/2019
06/20/2019
06/20/2019
89
90
91
266
270
271
92 278
93
94
95
96
279
280
282
294
300 97
98
301
99 302
100
310 EMC
101
401
FCT
DEBUG: BUTTONS
DEBUG: MISC
DEBUG: LEDS (1/3)
DEBUG: LEDS (2/3)
DEBUG: LEDS (3/3)
DEBUG: P3V8AON ISENSE
DEBUG: VITAMIN-C
DESENSE (1/3)
DESENSE (2/3)
DESENSE (3/3)
POWER ALIASES 1 400
POWER ALIASES 2 102
KELVIN_T668_MLB
T668_MLB 06/20/2019
T668_MLB
T668_MLB
T668_MLB
T668_MLB
T668_MLB
MANAN_T668_MLB
KEI_T668_MLB
KEI_T668_MLB 09/30/2019
KEI_T668_MLB 09/30/2019
KEI_T668_MLB 10/02/2019
KEI_T668_MLB 11/06/2019
KEI_T668_MLB
01/29/2020
06/20/2019
07/24/2019
07/24/2019
07/24/2019
06/20/2019
02/03/2020
11/04/2019
11/06/2019
43
44
45
46
47
48
49
50
51
52
54
55
56
132
135
136
138
139
140
141
142
144
145
150 53
151
152
153
I2C: SMC
SENSORS: POWER HIGH SIDE (1/2)
SENSORS: POWER HIGH SIDE (2/2)
SENSORS: POWER LOW SIDE (1/2)
SENSORS: POWER LOW SIDE (2/2)
SENSORS: POWER SUPPORT
SENSORS: THERMAL (1/2)
SENSORS: THERMAL (2/2)
SENSORS: MOTION
FAN
USB-C: High Speed ATC0
USB-C: High Speed ATC1
USB-C: Support 1 ATC01
USB-C: Support 2 ATC01
KEI_T668_MLB
KEI_T668_MLB
KEI_T668_MLB
KEI_T668_MLB
KEI_T668_MLB
KEI_T668_MLB
KEI_T668_MLB
KEI_T668_MLB
WUDI_T668_MLB
AITKEN_T668_MLB
REF_USBC_ACE2
REF_USBC_ACE2
REF_USBC_ACE2
REF_USBC_ACE2
12/20/2019
04/04/2020
03/10/2020
03/10/2020
01/23/2020
02/04/2020
04/02/2020
01/23/2020
09/23/2019
09/18/2019
02/14/2020
02/14/2020
02/01/2020
02/01/2020
103
104
105
107
108
109
110
111
112
113
114
115
116
402
403
404
405 106
406
500
POWER ALIASES 3
POWER ALIASES 4
POWER ALIASES 5
SIGNAL ALIASES 1
SIGNAL ALIASES 2
17.2 RULES
501 17.2 PHYSICAL CSETS
502
503
600
601
17.2 SPACING CSETS, ISO
17.2 SPACING CSETS, CLASS-CLASS
BOM VARIANT TABLES
BOM OPTION TABLES
602
610
BOM ALTERNATES
700
T668_MLB
KEI_T668_MLB
T668_MLB
T668_MLB
T668_MLB
T668_MLB
T668_MLB
06/05/2019
11/06/2019
09/12/2019 KEI_T668_MLB
09/18/20 9 AITKEN_T668_MLB
05/29/2019
05/13/2019
05/13/2019 T668_MLB
05/13/2019
05/13/2019 T668_MLB
06/05/2018 T668_MLB
06/05/2018 T668_MLB
06/05/2018 T668_MLB
06/05/2018
06/05/2018
57
58
59
60
154
155
156
157
USB-C: Port Controller ATC0
USB-C: Port Controller ATC1
USB-C: Connector(s)
USB-C: HS Level Shifters
REF_USBC_ACE2
REF_USBC_ACE2
KEI_T668_MLB
REF_USBC_ACE2
02/01/2020
02/01/2020
02/01/2020
02/04/2020
117
999
CHECKPLUS SUPPORT
08/29/2019 T668_MLB
Page 2
D
w w w . t e k n i s i - i n d o n e s i a . c o m
REFERENCE DESIGNS J293 SYNCS FROM
SUB-DESIGN PAGES SUB-DESIGN NAME SOURCE PROJECT VERSION SYNC_DATE/TIME
T585 REF_VR_ICEMAN 57,58 1.14.0
T585 52,53REF_CHARGER_SUONA
224
T585 0.8.0
REF_VR_3V3_TPS62135
REF_SECDIS_MIPIMUX 231T585
REF_DFR_V3_SUPPORTT585 257,258
T585 50
T585 237REF_PANELPWR_BNJ 0.9.0
REF_SE_CERES
REF_SECD S_ AK 243 40.0
244,246,247REF_SPKRAMP_TAS5770
123T585
0.36.0
0.5.0 T585 REF_STORAGE_NON_OCARINA_SUPPORT
1.6.0245T585
0.8.0 T585 127
0.13.0REF_VR_5V_LT8642S
0.7.0
0.25.0
0.13.0
0.34.0 T585 220,221REF_STORAGE_S5E
HARD/
SOFT
2020/04/27
2020/04/27
2020/04/27
2020/04/27
2020/04/27
2020/04/27
2020/04/27
2020/04/27
2020/04/27
2020/04/27
2020/04/27
2 20/04/27
2020/04/27
REFERENCE DESIGNS NO LONGER SYNCS FROM
SUB-DESIGN P G S SUB-DES GN N ME SOUR E PROJECT VERSION YNC_DATE/TIME
5-17,19T585 REF_SOC_H13G
T585 REF_PMU_SERA_SIMETRA 77-79,81-83
T585 238,239REF_BLC_BEN
T585 294REF DEBUG_STUFF
T585 242REF_SECDIS_AMR
150-155,157REF_USBC_ACE2T 85
200-201T585 REF_WIRELESS_ ASPUTIN
REF_MESA_SUPPORT 256T585
REF_KBD_SUPPORT 251T585
HARD/
SOFT
<-- WE STOPPED SYNCING SOC AT 0.56.0 DUE TO REF DESIGN DESENSE CAP ADDITIONS CONFLICTING WITH DESENSE TEAM'S REQUESTS FOR J293
<-- WE STOPPED SYNCING PMU AT 0.57.0 DUE TO SLOW UPDATES AND REF DESIGN IS OFF GRID
<-- WE STOPPED SYNCING BLC AT 0.16.0 TO RELAX PLACE NEARS
<-- WE STOPPED SYNCING VITAMIN C AT 0.1.0 SINCE THE REF DESIGN IS INCOMPLETE ND MANY CHANGES ARE NEEDED TO SUPPORT VIT C MK II
<-- WE STOPPED SYNCING AMR REF SINCE THE REF HAS A DIFFERENT APN FOR AMR FOOTPRINT THAN PD USES IN J293'S MCO
<-- WE STOPPED SYNCING USB AT 0.31.0 AS THE 50V CC CAPS WHICH ARE 2.8X MORE EXPENSIVE THAN THE 25V ONES, ALSO LSF0 02 COMBO ADDED
<-- WE STOPPED SYNCING RASPUTIN TO ADD RF CONN BOM OPT ON, CHANGE 100M CLK TPS TO PPS, AND FIX OVERLAPPING IPU TEXT NOTES
<-- WE STOPPED SYNCING MESA SUPPORT AT 0.11.0 SINCE THE REF DESIGN REMOVED A PULL UP AND WE NEED 1V85 ON THE LDO
<-- WE STOPPED SYNCING KBD AT 0.25.0 TO FIX CREF GENERATION ERROR ON PIN Y8
REFERENCE DESIGNS WHERE NET NUDGE WAS NEEDED TO REMOVE CREFER ERRORS
S5E, USBC, SECDIS SAK
B
SYNC_MASTER T668_MLB SYNC_DA E=07/17/2019
PAGE TITLE
A
REFERENCE DESIGN SYNC TABLES
6 7 8
3 5 4
Page 3
3 2 4
w w w . t e k n i s i - i n d o n e s i a . c o m
TOP SIDE STANDOFFS
ALLOW_APPLE_PREFIX=Z
Z0400
2.8OD1.2ID-1.49H-SM
860-01216
CRITICAL
ALLOW_APPLE_PREFIX=Z
Z0401
2.8OD1.2ID-1.49H-SM
860-01216
CRITICAL
ALLOW_APPLE_PREFIX=Z
Z0402
2.8OD1.2ID-1.49H-SM
860-01216
CRITICAL
ALLOW_APPLE_PREFIX=Z
Z0403
2.8OD1.2ID-1.49H-SM
USB-C BOSS
ALLOW_APPLE_PREFIX=Z
CRITICAL
Z0420
3.4OD1.75ID-1.12H-SM
ALLOW_APPLE_PREFIX=Z
CRITICAL
Z0421
3.4OD1.75ID-1.12H-SM
DFR BOSS
ALLOW_APPLE_PREFIX=Z
CRITICAL
Z0430
3.4OD1.75ID-1.5H-SM
860-00392
860-00392
860-01484
TRACKPAD BOSS
ALLOW_APPLE_PREFIX=Z
CRITICAL
Z0440
3.5OD1.85ID-1.41H-SM
860-00381
ALLOW_APPLE_PREFIX=Z
CRITICAL
Z0441
3.5OD1.85ID-1.41H-SM
860-00381
CPU THERM STAGE HOLE 3.15 MM
OMIT
CRITICAL
ZT0400
3P9R3P15
998-0845
CORNER NEAREST KEYBOARD
DISPLAY BOSS
ALLOW_APPLE_PREFIX=Z
CRITICAL
Z0450
2.7X1.8R-1.4ID-0.84H-SM
ALLOW_APPLE_PREFIX=Z
CRITICAL
Z0451
2.7X1.8R-1.4ID-0.84H-SM
FAN MTG HOLE 2.0X2.6 MM
OMIT
ALLOW_APPLE_PREFIX=ZT
CRITICAL
ZT0430
TH-NSP
1
SL-2.6X2.0-4.7X4.1
SHIELD CAN ALIGNMENT HOLES
OMIT
ALLOW_APPLE_PREFIX=Z
Z04A0
TH-NSP
SL-1.2X0.4-1.5X0.7
OMIT
ALLOW_APPLE_PREFIX=Z
Z04A1
TH-NSP
SL-1.2X0.4-1.5X0.7
OMIT
ALLOW_APPLE_PREFIX=Z
Z04A2
TH-NSP
SL-1.2X0.4-1.5X0.7
OMIT
ALLOW_APPLE_PREFIX=Z
Z04A3
TH-NSP
SL-1.2X0.4-1.5X0.7
OMIT
ALLOW_APPLE_PREFIX=Z
998-04440
998-04440
998-04440
998-04440
D
CRITICAL
ALLOW_APPLE_PREFIX=Z
Z0404
2.8OD1.2ID-1.49H-SM
CRITICAL
ALLOW_APPLE_PREFIX=Z
Z0405
2.8OD1.2ID-1.49H-SM
CRITICAL
860-01216
860-01216
860-01216
BOTTOM SIDE STANDOFFS
ALLOW_APPLE_PREFIX=Z
Z0410
2.8OD1.2ID-3.15H-SM
860-01485
CRITICAL
ALLOW_APPLE_PREFIX=Z
Z0411
2.8OD1.2ID-3.15H-SM
860-01485
CRITICAL
CPU THERM STAGE HOLES 3.6 MM
OMIT
CRITICAL
ZT0401
4.0R3.6-NSP
998-03850
OMIT
CRITICAL
ZT0402
4.0R3.6-NSP
998-03850
CPU THERM STAGE HOLE OVAL
MLB MTG HOLES 2.1X3.51 MM
OMIT
ALLOW_APPLE_PREFIX=ZT
CRITICAL
ZT0420
TH-NSP
1
SL-2.1X3.51-4.6X6.01
OMIT
ALLOW_APPLE_PREFIX=ZT
CRITICAL
ZT0421
TH-NSP
1
SL-2.1X3.51-4.6X6.01
OMIT
ALLOW_APPLE_PREFIX=ZT
CRITICAL
ZT0422
TH-NSP
1
SL-2.1X3.51-4.6X6.01
Z04A4
TH-NSP
SL-1.2X0.4-1.5X0.7
OMIT
ALLOW_APPLE_PREFIX=Z
Z04A5
TH-NSP
SL-1.2X0.4-1.5X0.7
POGO PINS
ALLOW_APPLE_PREFIX=PP
PP0400
POGO-2.3OD-4.0H-SM
SM-1
998-04440
998-04440
C
DFR WASHER
ALLOW_APPLE_PREFIX=Z
CRITICAL
Z0431
4.75OD2.73ID-H0.2
RING-TH
860-01519
ALLOW_APPLE_PREFIX=Z
Z0412
2.8OD1.2ID-3.15H-SM
CRITICAL
ALLOW_APPLE_PREFIX=Z
Z0413
2.8OD1.2ID-3.15H-SM
CRITICAL
860-01485
860-01485
OMIT
CRITICAL
ZT0403
TH-NSP
SL-3.65X3.15-4.5X4.0
ALLOW_APPLE_PREFIX=ZT
998-21974
WIFI COAX STANDOFF
CRITICAL
Z0498
5.25X2.8R-1.4ID-1.5H-SM
860-01704
ALLOW_APPLE_PREFIX=Z
WIFI WASHER
ALLOW_APPLE_PREFIX=Z
CRITICAL
Z0432
4.75OD2.73ID-H0.2
RING-TH
AJ FLEX COWLING BOSS
ALLOW_APPLE_PREFIX=Z
CRITICAL
Z0470
3.5OD1.85ID-1.92H-SM
ALLOW_APPLE_PREFIX=PP
PP0401
POGO-2.3OD-4.0H-SM
SM-1
ALLOW_APPLE_PREFIX=PP
PP0402
POGO-2.3OD-4.0H-SM
SM-1
ALLOW_APPLE_PREFIX=PP
PP0403
POGO-2.3OD-4.0H-SM
SM-1
870-09667
870-09667
B
870-09667
FENCE SPMU
FENCE COMBO
CRITICAL PART NUMBER REFERENCE DES DESCRIPTION
FENCE,SPMU,X1727 FENCE_SPMU_C770 806-24457 FENCE_SPMU CRITICAL
CRITICAL PART NUMBER REFERENCE DES DESCRIPTION
870-09667
LANDING CLIP
FENCE_SPMU_SUSFENCE,SPMU,SUS,SBP,X1727806-24550 FENCE_SPMU CRITICAL
CRITICAL PART NUMBER BOM OPTION REFERENCE DES DESCRIPTION
CL P:YESCLIP CLIP,LAND NG,MLB,X1727806-25216 CRITICAL
PAGE TITLE
A
PD PARTS
LANDING CLIP SMALL
FENCE_COMBOFENCE_COMBOFENCE,COMBO,X1727806-24549 CRITICAL
CRITICAL PART NUMBER BOM OPTION REFERENCE DES DESCRIPTION
FENCE USBC
CRITICAL PART NUMBER REFERENCE DES DESCRIPTION
FENCE_USBC_C770 CRITICAL 806-24455 FENCE_USBCFENCE,BURNSIDE BRIDGE,X1727
CRITICALFENCE_USBC806-24548 FENCE,BURNSIDE BRIDGE,SUS,SBP,X1727 FENCE_USBC_SUS
CLIP_SMALL:YESCLIP_SMALL CLIP,LANDING,SMALL,MLB,X1727806-25217 CRITICAL
METAL SLED
CRITICAL PART NUMBER BOM OPTION REFERENCE DES DESCRIPTION
SLED,METAL,X1727 SLED1,SLED2 CRITICAL SLED:YES 806-24419
BOM_COST_GROUP=MECHANICALS
3 4
Page 4
BOOT CONFIG ID
w w w . t e k n i s i - i n d o n e s i a . c o m
6 88
6 18
6 18
SPI_DFR_MISO
OUT
SPI_DFR_MOSI_R
OUT
SPI_DFR_CLK_R
OUT
BOOT_CFG[2:0]
000
001
010
011
POR ---> 100
101
110
111
102 11 8 6 5 4
PP1V25_AWAKE_IO
MODE
SPI1 NOR (12 MHZ)
SPI1 NOR (12 MHZ) TESTMODE
SPI0 NAND
SPI0 NAND TESTMODE
SPI1 NOR (40 MHZ)
SPI1 NOR (40 MHZ) TESTMODE
SPI1 NOR (6 MHZ)
SPI1 NOR (6MHZ) TESTMODE
BOOT_CONFIG2 BOOT_CONFIG1 BOOT_CONFIG0
1
R0502
4.7K
5%
1/20W
MF
201
2
1
R0501
4.7K
5%
1/20W
MF
201
2
S/W READ FLOW
1. SET GPIO AS INPUT
2. DISABLE PU AND ENABLE PD
3. READ
1
R0500
4.7K
5%
1/20W
MF
20
2
R0533
10K
5%
1/20W
MF
201
R0534
10K
5%
1/20W
MF
201
R0535
10K
5%
1/20W
MF
201
R0536
10K
5%
1/20W
MF
201
2 1
SOC_JTAG_SEL
2 1
SOC_TESTMODE
SOC_HOLD_RESET
2 1
2 1
SOC_KIS_DFU_SELECT
OUT
OUT
OUT
OUT
9 18
5
5
5
BOARD ID
2 11 8 6 5 4
6
6
6
6
6
BOARD_ID[7:0] IS 8 TOTAL BITS
BOARD_ID[7:5] ARE SET INSIDE THE SOC
BOARD_ID[4:0] ARE SET WITH THESE RESISTORS
BOARD_ID[0] IS 0 FOR FORM FACTOR AND 1 FOR DEV PLATFORM
BOARD_ID[7:0] FOR J293 IS 0B00100100
<RDAR://53744986>
BOARD_ID4
OUT
BOARD_ID3
OUT
BOARD_ID2
OUT
BOARD_ID1
OUT
BOARD_ID0
OUT
S/W READ FLOW
PP1V25_AWAKE_IO
BOARDID4
1
2
R0514
1K
5%
1/20W
MF
201
1
R0513
1K
5%
1/20W
MF
201
2
BOARDID2 BOARDID3
1
R0512
1K
5%
1/20W
MF
201
2
BOARDID1 BOARDID0
1
R0511
1K
5%
1/20W
MF
201
2
1
R0510
1K
5%
1/20W
MF
201
2
PP1V25_AWAKE_IO
I2C_SEEPROM_SCL
6
I2C_SEEPROM_SDA
6
SEP EEPROM (128-Kbit)
PP1V8_AWAKE
1
R0540
2.2K
5%
1/20W
MF
201
2
(Write: 0xA2, Read 0xA3)
A1 PER <RDAR://590 9073>
1
R0541
2.2K
5%
1/20W
MF
201
2
7
SCL
6
SDA
VCC
U0500
STOCT
DFN
335S00488
VSS EPAD
VIO
NC
1
C0500
1.0UF
20%
4V
2
X6S
0201
5
2
NC
3
NC
4
NC
1. SET GPIO AS INPUT
2. DISABLE PU AND ENABLE PD
3. READ
BOARD REVISION
6
OUT
OUT
6
OUT
6
OUT
BOARD_REV0
BOARD_REV1
BOARD_REV2
BOARD_REV3
NOTE: STUFFING RESISTOR MEANS 0
BOARD_REV3
1
R0523
1K
5%
1/20W
MF
201
2
BOARD_REV2
1
R0522
1K
5%
1/20W
MF
201
2
BOARD_REV1
1
R0521
1K
5%
1/20W
MF
201
2
BOARD_REV0
1
R0520
1K
5%
1/20W
MF
201
2
board rev should start at 0b0000 and increment each rev.
S/W READ FLOW
1. SET GPIO AS INPUT
2. ENABLE PU AND DISABLE PD
3. READ
J293 BOARD_REV [3:0] = 0000 : PRE P1
0001 : P1 A0
0010 : P1 A1
0011 : P1 A1 AUDIO
0100 : P2
0101 : EVT
PAGE TITLE
SOC: Support
BOM_COST_GROUP=SOC
3 7 8
Page 5
SOC: CIO, USB, DRAM, RESETS, CLOCKS, SWD, FPWM
w w w . t e k n i s i - i n d o n e s i a . c o m
OMIT_TABLE
U0600
TMLR68A0-B09
BGA
SYM 1 OF 23
9 33 74 89 90 100
IN
5 33 56 89 90
4
IN
33 55 89
IN
4
IN
PMU_RESET_L
SOC_FORCE_DFU
SOC_REQUEST_DFU1
5 19
SOC_REQUEST_DFU2
5
SOC_TESTMODE
PMU_ACTIVE_READY
SOC_HOLD_RESET
R2
AA49
AK55
AJ54
AD
AL54
AC1
LP4_IN_RESET_N
FORCE_DFU
REQUEST_DFU1
REQUEST_DFU2
TESTMODE
CFSB
HOLD_RESET
IPD
IPD
RESET
DFU_STATUS
V51
SOC_DFU_STATUS
OUT IN
19 56 89 94
AMUX_OUT can go to TP or to AMUX_IN on PMU
4
18
BI
18
BI
60
IN
60
OUT
SOC_KIS_DFU_SELECT
IN
EUSB_ATC0_P
EUSB_ATC0_N
CIO_ATC0_LSRX_1V2
CIO_ATC0_LSTX_1V2
SOC_ATC0_USB_RESREF
5
AB49
BB54
BB55
BE18
BE13
BB53
KIS_DFU_SELECT
ATC0_USB_EDP
ATC0_USB_EDM
USB_C0_LSRX
USB_C0_LSTX
ATC0_USB_RESREF
CLOCKS
XI0
XO0
TST_CLKOUT
BE36
BF36
P54
SOC_XTAL24M_IN
SOC_XTAL24M_OUT
TP_TST_CLKOUT
18
SOC_ATCPHY0_RCAL_POS
SOC_ATCPHY0_RCAL_ EG
SOC_ATCPHY1_RCAL_POS
SOC_ATCPHY1_RCAL_NEG
1
R0600
200
1%
1/20W
MF
201
2
1
C0600
10PF
5%
25V
2
C0G
0201
1
R0601
200
1%
1/20W
MF
201
2
1
C0601
10PF
5%
25V
2
C0G
0201
99
1%
MF
201
1
2
24.000MHZ-20PPM-9.5PF-60OHM
OC_24M_O_R
CRITICAL
1
C0650
15PF
5%
50V
2
C0G
0201
1
R0631
10K
5%
1/20W
MF
201
2
CRITICAL
Y0600
1.60X1.20MM
3 1
4 2
SOC_FORCE_DFU
5 33 56 89 90 5 5 19
CRITICAL
1
C0651
15PF
5%
50V
2
C0G
0201
1
R0632
47K
5%
1/20W
MF
201
2
NC_ATC0_HPD
107
18
BI
18
BI
60
IN
60
OUT
53
BI
53
BI
53
OUT
53
OUT
53
BI
53
BI
53
OUT
53
OUT
53
BI
53
BI
54
BI
54
BI
54
OUT
54
OUT
54
BI
54
BI
54
OUT
54
OUT
EUSB_ATC1_P
EUSB_ATC1_N
CIO_ATC1_LSRX_1V2
CIO_ATC1_LSTX_1V2
SOC_ATC1_USB_RESREF
5
NC_ATC1_HPD
107
USB_VBUS_DETECT
5
USBC_ATC0_D2R_P<1>
USBC_ATC0_D2R_N<1>
USBC_ATC0_R2D_C_P<1>
USBC_ATC0_R2D_C_N<1>
USBC_ATC0_D2R_P<2>
USBC_ATC0_D2R_N<2>
USBC_ATC0_R2D_C_P<2>
USBC_ATC0_R2D_C_N<2>
USBC_ATC0_AUX_P
USBC_ATC0_AUX_N
SOC_ATCPHY0_RCAL_POS
5
SOC_ATCPHY0_RCAL_NEG
5
USBC_ATC1_D2R_P<1>
USBC_ATC1_D2R_N<1>
USBC_ATC1_R2D_C_P<1>
USBC_ATC1_R2D_C_N<1>
USBC_ATC1_D2R_P<2>
USBC_ATC1_D2R_N<2>
USBC_ATC1_R2D_C_P<2>
USBC_ATC1_R2D_C_N<2>
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
V48
BC54
BC55
BD3
BE10
BC53
R48
AG1
BE50
BF50
BC49
BD49
BE48
BF48
BC47
BD47
AY51
AY52
BE52
BF52
BF44
BE44
BD43
BC43
BF46
BE46
BD45
BC45
USB_C0_HPD/TMU_CLK_OUT0
ATC1_USB_EDP
ATC1_USB_EDM
USB_C1_LSRX
USB_C1_LSTX
ATC1_USB_RESREF
USB_C1_HPD/TMU_CLK_OUT1
EUSB_VBUS_DETECT
ATCPHY0_RX0_P
ATCPHY0_RX0_N
ATCPHY0_TX0_P
ATCPHY0_TX0_N
ATCPHY0_RX1_P
ATCPHY0_RX1_N
ATCPHY0_TX1_P
ATCPHY0_TX1_N
ATCPHY0_AUX_P
ATCPHY0_AUX_N
ATCPHY0_RCAL_P
ATCPHY0_RCAL_N
ATCPHY1_RX0_P
ATCPHY1_RX0_N
ATCPHY1_TX0_P
ATCPHY1_TX0_N
ATCPHY1_RX1_P
ATCPHY1_RX1_N
ATCPHY1_TX1_P
ATCPHY1_TX1_N
ATC
SWD
FPW
ANALOGMUX_OUT
SWD_TCK_OUT1
SWD_TMS2
SWD_TMS3
SWD_TMS4
FPWM0/MASTER_SYNC_GEN_0
FPWM1
FPWM2
AL48
AJ1
U54
V54
AH3
V50
Y49
U50
TP_SOC_AMUX_OUT
SWD_NAND0_SWCLK
SWD_NAND0_SWDIO
NC_SWD_TMS3
TP_SWD_TMS4
IPD
WLAN_TIME_SYNC
KBD_BKLT_PWM
TP_FPWM2
102 11 8 6 5 4
PP1V25_AWAKE_IO
SOC_REQUEST_DFU1
OUT
OUT
BI
106
IN
OUT
1
2
18 106
67 107
67 10
62
72
R0630
10K
5%
1/20W
MF
201
R0651
1/20
SOC_REQUEST_DFU2
102 11 8 6 5 4
PP1V25_AWAKE_IO
USB_VBUS_DETECT
5
1
R0639
0
5%
1/20W
MF
0201
2
54
BI
54
BI
USBC_ATC1_AUX_P
USBC_ATC1_AUX_N
SOC_ATCPHY1_RCAL_POS
5
SOC_ATCPHY1_RCAL_NEG
5
BA52
BA51
BF4
BE4
ATCPHY1_AUX_P
ATCPHY1_AUX_N
ATCPHY1_RCAL_P
ATCPHY1_RCAL_N
SOC_ATC0_USB_RESREF SOC_ATC1_USB_RESREF
5 5
R0641
200
1%
1/20W
MF
201
2
1
R0640
200
1%
1/20W
MF
201
2
SYNC_MASTER=AITKEN_T6 8_MLB SYNC_DATE=10/08/2019
PAGE TITLE
A
SOC: CIO, USB, RESETS, CLOCKS, SWD
AB E_ LT_HE D
PART NUMBER
Y0600 197S0590 EPSON,24MHZ.XTAL 197S0591
Y0600 197S0588 TXC,24MHZ,XTAL 197S0591
COMMENTS: REF DES BOM OPTION PART NUMBER ALTERNATE FOR
AB E_ LT_IT M
AB E_ LT_IT M
BOM_COST_GROUP=SOC
3 5 4 6
Page 6
**OK2INTEGRATE**
w w w . t e k n i s i - i n d o n e s i a . c o m
all signals are 1.2 unless otherwise specified.
all signals on this page reference PP1V2_AWAKE_GRP if they are 1.2V
if they are 1.8V they reference PP1V8_AWAKE_GRP
U0600
TMLR68A0-B09
BGA
SYM 3 OF 23
SOC: I/Os
18
UT
18
IN
18
OUT
18
OUT
18
OUT
1
IN
1
OUT
18
OUT
18
OUT
76
IN
18
OUT
18
OUT
TDM_SPKRAMP_L_BCLK_R
TDM_SPKRAMP_L_D2R
TDM_SPKRAMP_L_R2D_R
TDM_SPKRAMP_L_FSYNC_R
NC_SOC_I2S0_MCK
106
TDM_SPKRAMP_R_BCLK_R
TDM_SPKRAMP_R_D2R
TDM_SPKRAMP_R_R2D_R
TDM_SPKRAMP_R_FSYNC_R
NC_SOC_I2S1_MCK
6
TDM_CODEC_BCLK_R
TDM_CODEC_D2R
TDM_CODEC_R2D_R
TDM_CODEC_FSYNC_R
TP_SOC_I2S2_MCK
NC_I2S3_BCLK
106
NC_I2S3_D2R
6
NC_I2S3_R2D
6
NC_I2S3_LRCLK
106
NC_I2S3_MCLK
106
AK4
AJ3
AJ5
AJ4
AK3
AG3
AF3
AG4
AF2
AG2
AK5
AL6
AJ7
AM4
AK6
AH6
AH4
AG5
AJ6
AF5
I2S0_BCLK
I2S0_DIN
I2S0_DOUT
I2S0_LRCK
I2S0_MCK
I2S1_BCLK
I2S1_DIN
I2S1_DOUT
I2S1_LRCK
I2S1_MCK
I2S2_BCLK
I2S2_DIN
I2S2_DOUT
I2S2_LRCK
I2S2_MCK
I2S3_BCLK
I2S3_DIN
I2S3_DOUT
I2S3_LRCK
I2S3_MCK
IPD
IPD
IPD
I2S
SPI
IPD
IPD
IPD
IPD
IPD
SPI0_MISO
SPI0_MOSI
SPI0_SCLK
SPI1_MISO
SPI1_MOSI
SPI1_SCLK
SPI1_SSIN
SPI2_MISO
SPI2_MOSI
SPI2_SCLK
SPI2_SSIN
SPI3_MISO
SPI3_MOSI
SPI3_SCLK
SPI3_SSIN
SPI4_MISO
SPI4_MOSI
SPI4_SCLK
SPI4_SSIN
AL4
AK2
AK1
AD4
AE4
AF4
AE3
AF53
AF54
AF55
AF52
Y1
W1
AB1
AA1
AC4
AB4
AA4
AB3
SPI_DFR_MISO
SPI_DFR_MOSI_R
SPI_DFR_CLK_R
SPI_SOCROM_MISO
SPI_SOCROM_MOSI_R
SPI_SOCROM_CLK_R
SPI_SOCROM_CS_L
SPI_TOUCHID_MISO
SPI_TOUCHID_MOSI_R
SPI_TOUCHID_CLK_R
NC_SOC_SPI2_SSIN
SPI_IPD_MISO
SPI_IPD_MOSI_R
SPI_IPD_CLK_R
SPI_IPD_CS_L
SPI_TCON_MISO
SPI_TCON_MOSI_R
SPI_TCON_CLK_R
SPI_TCON_CS_L
106
IN
OUT
OUT
IN
OUT
OUT
OUT
IN
OUT
OUT
IN
OUT
OUT
OUT
IN
OUT
OUT
OUT
4
4
4
17
17
17
17
80
18
18
84
18
18
84
69
69
69
69
1.8V IO
1.8V IO
41
OUT
1
BI
1
OUT
41
BI
41
OUT
41
BI
41
OUT
41
BI
4
OUT
1
BI
I2C_UPC_SCL
I2C_UPC_SDA
I2C_SPKRAMP_L_SCL
I2C_SPKRAMP_L_SDA
I2C_CODEC_SCL
I2C_CODEC_SDA
I2C_SPKRAMP_R_SCL
I2C_SPKRAMP_R_SDA
I2C_DFR_SCL
I2C_DFR_SDA
NC_SPMI2_CLK
106
TP_SPMI2_DATA
W52
V52
AA48
Y48
AB50
Y50
AF6
AE6
AF50
AG49
AK7
AL7
I2C0_SCL
I2C0_SDA
I2C1_SCL
I2C1_SDA
I2C2_SCL
I2C2_SDA
I2C3_SCL
I2C3_SDA
I2C4_SCL
I2C4_SDA
AP_SPMI2_SCLK
AP_SPMI2_SDATA
SPMI
SI2C0_SCL
SEP
THROTTLE
IPU FOR ALL
THROTTLE_TRIGGER
THROTTLE_TRIGGER0/MTR_ADC_DOUT
THROTTLE_TRIGGER1/MTR_ADC_CLKOUT
THROTTLE_TRIGGER2/PLL_DIGOBS_0
THROTTLE_TRIGGER3/PLL_DIGOBS_1
THROTTLE_TRIGGER4
SI2C0_SDA
SSPI0_MISO
SSPI0_MOSI
SSPI0_SCLK
SGPIO0
SGPIO1
SOCHOT1
AC3
AC2
Y5
Y4
AC5
AD5
AD6
AK52
AK53
AL53
AJ55
AJ53
AJ49
DBL_CLICK_DET
DISABLE_STROBE
I2C_SEEPROM_SCL
I2C_SEEPROM_SDA
FTCAM_DISABLE_L
NC_SSPI0_MOSI
DMIC_DISABLE_L
SOC_SOCHOT_L
BUCK1_THERMAL_THROTTLE_L
BUCK0_THERMAL_THROTTLE_L
SOC_THROTTLE_TRIGGER2
PMU_VDDHI_UVWARN_L
PMU_VDDMAIN_UVWARN_L
106
33
IN
74
OUT
4
OUT
BI
74
OUT
74
OUT
6 33 89 91 96 100
OUT
33 34
IN
33 34
IN
19
IN
106
IN
33 34
IN
11 8 5 4
PP1V25_AWAKE_IO
SOC_SOCHOT_L
6 33 89 91 96 100
1
R0790
47K
5%
1/20W
MF
201
2
UPC_FORCE_PWR will likely be
removed in the future
TOUCHID_PWR_EN gets
pulled up to S2 on
TOUCHID page
This is OK because
the GPIO is failsafe
PD needed on DFR PAGE
107
107
1 6
106
U0600
TMLR68A0-B09
BGA
SYM 2 OF 23
IN
79
IN
89
79 89
IN
OUT
77 78 80
IN
76
IN
55
OUT
UPC_I2C_INT_L
NC_SOC_GPIO01
106
SPKR_ID0
SPKR_ID1
SPKRAMP_RESET_L
SPKRAMP_INT_L
CODEC_INT_L
SWD_UPC_SWCLK
NC_SOC_GPIO08
106
TP_SOC_GPIO09
TP_SOC_GPIO10
4
IN
4
IN
4
IN
4
IN
55
BI
BI
IN
84
OUT
86
IN
86 94
OUT
57 58 61
OUT
87 88
OUT
94
88 106
OUT
IN
BOARD_REV0
BOARD_REV1
BOARD_REV2
BOARD_REV3
NC_SOC_GPIO15
106
NC_SOC_GPIO16
106
SWD_UPC_SWDIO0
TP_SWD_UPC_SWDIO1
DFR_TOUCH_INT_L
IPD_SPI_EN
TOUCHID_INT
TOUCHID_PWR_EN
UPC_FORCE_PWR
DFR_PWR_EN
SPI_DFR CS_L
NC_ENET_SYNC_1588
AJ51
AA50
V53
U53
T53
W53
W50
U52
AC48
R53
R52
N55
AH54
Y52
AA51
R54
AC50
U51
AK50
T52
V49
AJ52
AJ50
AC49
R51
AL49
AF49
GPIO[0]
GPIO[1]
GPIO[2]
GPIO[3]
GPIO[4]
GPIO[5]
GPIO[6]
GPIO[7]
GPIO[8]
GPIO[9]
GPIO[10]
GPIO[11]
GPIO[12]
GPIO[13]
GPIO[14]
GPIO[15]
GPIO[16]
GPIO[17]
GPIO[18]
GPIO[19]
GPIO[20]
GPIO[21]
GPIO[22]
GPIO[23]
GPIO[24]
GPIO[25]
GPIO[26]
IPU
IPU
IPU
IPU
IPU
IPD
IPD
GPIO
UART
IPD
IPD
IPD
IPU
IPU
UART0_RXD
UART0_TXD
UART1_CTSN
UART1_RTSN
UART1_RXD
UART1_TXD
UART2_CTSN
UART2_RTSN
UART2_RXD
UART2_TXD
UART3_CTSN
UART3_RTSN
UART3_RXD
UART3_TXD
UART4_CTSN
UART4_RTSN
UART4_RXD
UART4_TXD
UART6_RXD
UART6_TXD
UART7_RXD
UART7_TXD
AB53
AC53
AC54
AA53
AA54
AC55
W55
Y54
Y53
Y55
AC51
AC52
AF48
AB52
AJ48
AK48
AL52
AL50
AF51
AG50
AM2
AJ2
UART_DEBUGPRT_D2R
UART_DEBUGPRT_R2D
DFR_1V8_TOUCH_RESET_L
DFR_1V8_DISP_RESET_L
DFR_1V8_DISP_INT
BT_TIME_SYNC_1V8
UART_WLAN_D2R_CTS_L
UART_WLAN_R2D_RTS_L
UART_WLAN_D2R
UART_WLAN_R2D
NC_UART3_D2R_CTS_L
NC_UART3_R2D_RTS_L
NC_UART3_D2R
NC_UART3_R2D
NC_UART4_D2R_CTS_L
NC_UART4_R2D_RTS_L
NC_UART4_D2R
NC_UART4_R2D
UART_TCON_HDMI_D2R
UART_TCON_HDMI_R2D
NC_UART7_RXD
NC_UART7_TXD
106
106
106
106
106
106
106
106
106
106
IN
OUT
OUT
OUT
IN
IN
IN
OUT
IN
OUT
IN
OUT
18 56 89
18 56 89
87 88 89
87 88 89
87 8 89
62 63
62
62
62
62
69 89
69 89
1.8V IO
1.8V IO
s UART2 if your wireless module is 1.2V IO
R2D is for desktop only
NAND0_RESET_L
6 64 65 67
4
IN
4
IN
4
IN
4
IN
4
IN
BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3
BOARD_ID4
W49
BOARD_ID0/SOC_DEBUG1
R55
BOARD_ID1/SOC_DEBUG2
T55
BOARD_ID2/SOC_DEBUG3
V55
BOARD_ID3/SPI0_SSIN
U55
BOARD_ID4
OARD ID
NAND
NAND_SYS_CLK0
NAND_SYS_CLK1
SSD_BFH
SSD_RESETN
AG52
AH53
AH51
AG53
NAND0_CLK24M_0_R
NAND0_CLK24M_1_R
NAND_BFH
NAND0_RESET_L
OUT
OUT
OUT
OUT
67
67
64 65 67
6 64 65 67
NOSTUFF
1
R0791
47K
5%
1/20W
MF
201
2
PAGE TITLE
SOC: AP I/Os
BOM_COST_GROUP=SOC
Page 7
**OK2INTEGRATE**
w w w . t e k n i s i - i n d o n e s i a . c o m
SOC: LPDP & MIPI
NC_LPDPRX_AUX0
106
NC_LPDPRX_AUX1
106
NC_LPDPRX_AUX2
106
NC_LPDPRX_AUX3
1 6
NC_LPDPRX_AUX4
106
NC_LPDPRX_AUX5
1 6
NC_LPDPRX_AUX6
106
NC_LPDPRX_AUX7
106
NC_LPDPRX_AUX8
106
NC_LPDPRX_AUX9
106
NC_LPDPRX_AUX10
106
NC_LPDPRX_AUX11
106
NC_LPDPRX_RX_P_0
107
NC_LPDPRX_RX_N_0
107
NC_LPDPRX_RX_P_1
107
NC_LPDPRX_RX_N_1
107
NC_LPDPRX_RX_P_2
107
NC_LPDPRX_RX_N_2
10
NC_LPDPRX_RX_P_3
107
NC_LPDPRX_RX_N_3
107
NC_LPDPRX_RX_P_4
107
NC_LPDPRX_RX_N_4
107
NC_LPDPRX_RX_P_5
107
NC_LPDPRX_RX_N_5
107
NC_LPDPRX_RX_P_6
107
NC_LPDPRX_RX_N_6
107
NC_LPDPRX_RX_P_7
107
NC_LPDPRX_RX_N_7
107
NC_LPDPRX_RX_P_8
107
NC_LPDPRX_RX_N_8
107
AP7
LPDPRX_AUX_D0_P
AR7
LPDPRX_AUX_ _P
AT7
LPDPRX_AUX_D2_P
AV7
LPDPRX_AUX_D3_P
AW7
LPDPRX_AUX_D4_P
AY7
LPDPRX_AUX_D5_P
AP8
LPDPRX_AUX_D6_P
AR8
LPDPRX_AUX_D7_P
AT8
LPDPRX_AUX_D8_P
AV8
LPDPRX_AUX_D9_P
AW8
LPDPRX_AUX_D10_P
AY8
LPDPRX_AUX_ 1_P
AP1
LPDPRX_RX_D0_P
AP2
LPDPRX_RX_D0_N
AR1
LPDPRX_RX_D1_P
AR2
LPDPRX_RX_D1_N
AT1
LPDPRX_RX_D2_P
AT2
LPDPRX_RX_D N
AV1
LPDPRX_RX_D3_P
AV2
LPDPRX_RX_D3_N
AW1
LPDPRX_RX_D4_P
AW2
LPDPRX_RX_D4_N
AY1
LPDPRX_RX_D5_P
AY2
LPDPRX_RX_D5_N
AP4
LPDPRX_RX_D6_P
AP5
LPDPRX_RX_D6_N
AR4
LPDPRX_RX_D7_P
AR5
LPDPRX_RX_D7_N
AT4
LPDPRX_RX_D8_P
AT5
LPDPRX_RX_D8_N
U0600
TMLR68A0-B09
BGA
SYM 4 OF 23
IPD
DISP_SPI_SCLK/DISP_I2C_SCL
DISP_SPI_SSIN/DISP_I2C_SDA
LPDP_TX0P
LPDP_TX0N
LPDP_TX1P
LPDP_TX1N
LPDP_TX2P
LPDP_TX2N
LPDP_TX3P
LPDP_TX3N
LPDP_TX4P
LPDP_TX4N
LPDP_TX5P
LPDP_TX5N
LPDP_AUX_P
LPDP_AUX_N
LPDP_RCAL_P
LPDP_RCAL_N
DISP_HPD
DISP_POL
DISP_SPI_MISO/DWI_CLK
DISP_SPI_MOSI/DWI_DO
DISP_SPMI_SCLK
DISP_SPMI_SDATA
DISP_FSYNC
DISP_LSYNC
GND_VOID=TRUE
AR55
AR54
AT55
AT54
AU54
AU55
AV55
AV54
AW55
AW54
AY55
AY54
AU52
AU51
AV52
AV51
AG55
AH55
AC6
AC7
AD7
AB6
W4
W3
T49
R50
LPDP_INT_DATA_C_P<0>
LPDP_INT_DATA_C_N<0>
GND_VOID=TRUE
LPDP_INT_DATA_C_P<1>
LPDP_INT_DATA_C_N<1>
GND_VOID=TRUE
LPDP_INT_DATA_C_P<2>
LPDP_INT_DATA_C_N<2>
GND_VOID=TRUE
LPDP_INT_DATA_C_P<3>
LPDP_INT_DATA_C_N<3>
GND_VOID=TRUE
NC_LPDP_TX4POS
NC_LPDP_TX4NEG
NC_LPDP_TX5POS
NC_LPDP_TX5NEG
LPDP_INT_AUX_C_P
LPDP_INT_AUX_C_N
SOC_LPDP_INT_RCAL_POS
SOC_LPDP_INT_RCAL_NEG
LPDP_INT_HPD
NC_DISPLAY_POL
NC_SPI_DISP_BKLT_MISO
NC_SPI_DISP_BKLT_MOSI_R
I2C_DISP_BKLT_SCL
I2C_DISP_BKLT_SDA
NC_DISP_SPMI_CLK
NC_DISP_SPMI_DATA
NC_DISP_FSYNC
NC_DISP_BKLT_LSYNC
OUT
OUT
OUT
OUT
OUT
OUT
OUT
06
06
106
106
7
106
106
106
106
OUT
UT
BI
BI
IN
69
69
69
69
69
69
69
69
69
69
69 89
106
42
42
106
IN
OUT
OUT
BI
NC_ISP_I2C0_SCL
106
NC_ISP_I2C0_SDA
106
NC_ISP_I2C1_SCL
106
NC_ISP_I2C1_SDA
106
I2C_CAM_SCL
OUT
I2C_CAM_SDA
BI
NC_ISP_I2C3_SCL
106
NC_ISP_I2C3_SDA
106
NC_FTCAM_RESET_L
OUT
NC_ISP_GPIO1
106
TP_ISP_GPIO2
TP_ISP_GPIO3
NC_ISP_SPMI0_CLK106
NC_ISP_SPMI0_DATA
106
NC_ISP_SPMI1_CLK
10
NC_ISP_SPMI1_DATA
106
TP_SENSOR0_CLK
NC_SENSOR1_CLK
106
NC_SENSOR2_CLK
106
NC_SENSOR3_CLK
106
106
106
41 1
41 106
Y2
ISP_I2C0_SCL/ISP_GPIO_8
Y3
ISP_I2C0_SDA/ISP_GPIO_9
AA5
ISP_I2C1_SCL/ISP_GPIO_10
AA6
ISP_I2C1_SDA/ISP_GPIO_11
AA3
ISP_I2C2_SCL
AA2
ISP_I2C2_SDA
AA7
ISP_I2C3_SCL
AB7
ISP_I2C3_SDA
Y6
ISP_GPIO_0
W6
ISP_GPIO_1
Y7
ISP_GPIO_2
W7
ISP_GPIO_3
AG7
ISP_SPMI0_SCLK/ISP_GPIO_5
AF7
ISP_SPMI0_SDATA/ISP_GPIO_4
AG6
ISP_SPMI1_SCLK/ISP_GPIO_7
AH7
ISP_SPMI1_SDATA/ISP_GPIO_6
AD1
SENSOR0_CLK
AE1
SENSOR1_CLK
AD3
SENSOR2_CLK
AF1
SENSOR3_CLK
U0600
TMLR68A0-B09
BGA
SYM 5 OF 23
ISP SPMI
MIPI0C_DPCLK
MIPI0C_ NCLK
MIPI0C_DPDATA0
MIPI0C_DNDATA0
MIPI0C_DPDATA1
MIPI0C_DNDATA1
MIPI1C_DPCLK
MIPI1C_DNCLK
MIPI1C_DPDATA0
MIPI1C_DNDATA0
MIPI1C_DPDATA1
MIPI1C_DNDATA1
MIPID_DPCLK
MIPID_DNCLK
MIPID_DPDATA0
MIPID_DNDATA0
MIPI_D
MIPI0C_REXT
MIPI1C_REXT
MIPID_REXT
L15
NC_MIPI0C_CLK_POS
L14
NC_MIPI0C_CLK_NEG
K15
NC_MIPI0C_DATA_0_POS
K14
NC_MIPI0C_DATA_0_NEG
M14
NC_MIPI0C_DATA_1_POS
M15
NC_MIPI0C_DATA_1_NEG
GND_VOID=TRUE
L11
MIPI_FTCAM_CLK_P
L12
MIPI_FTCAM_CLK_N
GND_VOID=TRUE
M12
MIPI_FTCAM_DATA_P<0>
M11
MIPI_FTCAM_DATA_N<0>
K11
NC_MIPI_FTCAM_DATA_POS1
K12
NC_MIPI_FTCAM_DATA_NEG1
GND_VOID=TRUE
K9
MIPI_DFR_CLK_P
K8
MIPI_DFR_CLK_N
GND_VOID=TRUE
GND_VOID=TRUE
L9
MIPI_DFR_DATA_P<0>
L8
MIPI_DFR_DATA_N<0>
GND_VOID=TRUE
K17
L17
SOC_MIPI1C_REXT
M9
SOC_MIPID_REXT
GND_VOID=TRUE
GND_VOID=TRUE
106
106
106
106
106
106
7
7
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
68
68
68
68
106
106
87
87
87
87
NC_LPDPRX_RX_P_9
10
NC_LPDPRX_RX_N_9
107
NC_LPDPRX_RX_P_10
107
NC_LPDPRX_RX_N_10
107
NC_LPDPRX_RX_P_11
107
NC_LPDPRX_RX_N_11
107
LPDPRX0_RCAL_POS
19
LPDPRX0_RCAL_NEG
19
LPDPRX1_RCAL_POS
19
LPDPRX1_RCAL_NEG
19
AV4
LPDPRX_RX_D P
AV5
LPDPRX_RX_D9_N
AW4
LPDPRX_RX_D10_P
AW5
LPDPRX_RX_D10_N
AY4
LPDPRX_RX_D11_P
AY5
LPDPRX_RX_D11_N
AU1
LPDPRX0_RCAL_P
AU2
LPDPRX0_RCAL N
AU4
LPDPRX1_RCAL_P
AU5
LPDPRX1_RCAL_N
DISP_TOUCH_BSYNC0
DISP_TOUCH_BSYNC1
DISP_TOUCH_EB
DFR_BSYNC/DISP_INT
DFR_DISP_TE
T50
R49
U49
AM5
AL51
NC_DISP_TOUCH_BSYNC0
NC_DISP_TOUCH_BSYNC1
NC_DISP_TOUCH_EB
NC_BKLT_FAULT_INT_L
DFR_DISP_TE
106
06
06
106
IN
88
IN
SOC_MIPI1C_REXT
7
SOC_MIPID_REXT
7
PLACE_NEAR=U0600.K17:6MM
PACK_OPTION=DFR
1
R0800
200
1%
1/20W
MF
201
2
PLACE_NEAR=U0600.L17:6MM
PACK_OPTION=FTCAM
1
R0820
200
1%
1/20W
MF
201
2
SOC_LPDP_INT_RCAL_POS
7
SOC_LPDP_INT_RCAL_NEG
7
1
R0895
200
1%
1/20W
MF
201
2
1
C0895
10PF
5%
25V
2
C0G
0201
SYNC_MASTER=AITKEN_T668_MLB SYNC_DATE=10/08/2019
PAGE TITLE
SOC: LPDP & MIPI
BOM_COST_GROUP=SOC
Page 8
PER PCISIG SPEC, AC COUPLING CAPS SHOULD BE BETWEEN
w w w . t e k n i s i - i n d o n e s i a . c o m
75 NF AND 265 NF FOR GEN1/2 AND BETWEEN
176 NF AND 265 NF FOR GEN 3/4
R0970 IS NEEDED DUE TO RDAR://53793006
SOC: PCIE
U0600
TMLR68A0-B09
BGA
SYM 6 OF 23
GND_VOID=TRUE
64
IN
64
IN
64
OUT
64
OUT
PCIE_NAND0_D2R_P<0>
PCIE_NAND0_D2R_N<0>
PCIE_NAND0_R2D_C_P<0>
PCIE_NAND0_R2D_C_N<0>
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
BE26
BF26
BC27
BD27
ST_PCIE_RX0_P
ST_PCIE_RX0_N
ST_PCIE_TX0_P
ST_PCIE_TX0_N
GP_PCIE_RX0_P
GP_PCIE_RX0_N
GP_PC E_TX0_P
GP_PCIE_ X0_N
GND_VOID=TRUE
BE30
BF30
GND_VOID=TRUE
GND_VOID=TRUE
BC31
BD31
GND_VOID=TRUE
PCIE_WLBT_D2R_P
PCIE_WLBT_D2R_N
PCIE_WLBT_R2D_C_P
PCIE_WLBT_R2D_C_N
IN
IN
OUT
OUT
62
62
62
62
102 11 6 5 4
PP1V25_AWAKE_IO
NAND0_CLKREQ1_L
8 67
WLBT_CLKREQ_L
8 62 63
NAND0_CLKREQ0_L
8 67
USBHC_CLKREQ_L
8
1
R0930
47K
1/20W
MF
201 201
2
1
R0940
47K
5% 5%
1/20W
MF
201
2
1
R0950
47K
5%
1/20W
MF
2
1
R0970
47K
5%
1/20W
MF
201
2
64 67
OUT
64 67
OUT
8 67
BI
67
8 64
OUT
65
65
IN
65 106
IN
65
OUT
65
OUT
65 67
OUT
65 67
OUT
8 67
BI
PCIE_CLK100M_NAND0_0_P
PCIE_CLK100M_NAND0_0_N
NAND0_CLKREQ0_L
NAND0_PCIE_RESET_L
PCIE_NAND0_D2R_P<1>
PCIE_NAND0_D2R_N<1>
PCIE_NAND0_R2D_C_P<1>
PCIE_NAND0_R2D_C_N<1>
PCIE_CLK100M_NAND0_1_P
PCIE_CLK100M_NAND0_1_N
NAND0_CLKREQ1_L
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
BB37
BC37
AH50
AH52
BE28
BF28
BC29
BD29
BB38
BC38
AH49
ST_PCIE_REF_CLK0_P
ST_PCIE_REF_CLK0_N
ST_PCIE_CLKREQ0_N
ST_PCIE_PERST0_N
ST_PCIE_RX1_P
ST_PCIE_RX1_N
ST_PCIE_TX1_P
ST_PCIE_TX1_N
ST_PCIE_REF_CLK1_P
ST_PCIE_REF_CLK1_N
ST_PCIE_CLKREQ1_N
GP_PCIE_REF_CLK0 P
GP_PCIE_REF_CLK0_N
GP_PCIE_CLKREQ0_N
GP_PCIE_PERST0_N
GP_PCIE_RX1 P
GP_PCIE_RX1_N
GP_PCIE_TX1_P
GP_PCIE_TX1_N
GP_PCIE_REF_CLK1_P
GP_PCIE_REF_CLK1_N
GP_PCIE_CLKREQ1_N
BE40
BF40
AB55
AA52
BE32
BF32
BC33
BD33
BE38
BF38
AA55
PCIE_CLK100M_WLBT_P
PCIE_CLK100M_WLBT_N
WLBT_CLKREQ_L
WLBT_RESET_L
NC_PCIE_USBHC_D2R_POS
NC_PCIE_USBHC_D2R_NEG
NC_PCIE_USBHC_R2D_C_POS
NC_PCIE_USBHC_R2D_C_NEG
NC_PCIE_CLK100M_USBHC_POS
NC_PCIE_CLK100M_USBHC_NEG
USBHC_CLKREQ_L
OUT
OUT
BI
OUT
IN
IN
OUT
OUT
OUT
OUT
62
62
8 62 63
8 62 63
1 6
106
106
106
106
8
TO BE CHECKED WITH SEG- DO NOT MATCH WITH SILVAL
IS THE PULL-UP VOLTAGE CORRECT?
NC_NAND0_PCIE_RESET1_L
106
AH48
ST_PCIE_PERST1_N
GP_PCIE_PERST1_N
GP_PCIE_RX2_P
GP_PCIE_RX2_N
GP_PCIE_TX2_P
GP_PCIE_TX2_N
GP_PCIE_REF_CLK2_P
GP_PCIE_REF_CLK2_N
GP_PCIE_CLKREQ2_N
GP_PCIE_PERST2_N
P55
BE34
BF34
BC35
BD35
BE39
BF39
AH1
AE7
NC_USBHC_RESET_L
NC_PCIE_ENET_D2R_POS
NC_PCIE_ENET_D2R_NEG
NC_PCIE_ENET_R2D_C_POS
NC_PCIE_ENET_R2D_C_NEG
NC_PCIE_CLK100M_ENET_POS
NC_PCIE_CLK100M_ENET_NEG
NC_ENET_CLKREQ_L
NC_ENET_RESET_L
OUT
IN
IN
OUT
OUT
OUT
OUT
BI
OUT
106
106
106
106
106
106
106
106
106
SOC_ST_PCIE_RCAL_POS
8
SOC_ST_PCIE_RCAL_NEG
8
SOC_GP_PCIE_RCAL_POS
8
SOC_GP_PCIE_RCAL_NEG
8
1
R0990
200
1%
1/20W
MF
201
2
1
C0990
10PF
5%
25V
2
C0G
0201
1
R0991
200
1%
1/20W
MF
201
2
1
C0991
10PF
5%
25V
2
C0G
0201
NAND0_PCIE_RESET_L
8 64 65 67
WLBT_RESET_L
8 62 63
SOC_ST_PCIE_RCAL_POS
SOC_ST_PCIE_RCAL_NEG
8
NC_MTR_VREF_ANAP
106
NC_MTR_VREF_ANAN
106
NC_MTR VREF_POS
106
NC_MTR_VREF_NEG
106
1
R0941
47K
5%
1/20W
MF
201
2
1
R0951
47K
5%
1/20W
MF
201
2
BC24
BB24
AM3
AL3
AL1
AM1
ST_PCIE_RCAL_P
ST_PCIE_RCAL_N
PAD_MTR_ANALOG_TEST_P
PAD_MTR_ANALOG_TEST_N
PAD_MTR_VREF_P
PAD_MTR_VREF_N
GP_PCIE_RCAL_P
GP_PCIE_RCAL_N
BC25
BB25
SOC_GP_PCIE_RCAL_POS
SOC_GP_PCIE_RCAL_NEG
8 8
8
SYNC_MASTER=ANDREW_T668_MLB SYNC_DATE=10/09/2019
PAGE TITLE
SOC: PCIE
BOM_COST_GROUP=SOC
Page 9
**OK2INTEGRATE**
w w w . t e k n i s i - i n d o n e s i a . c o m
AOP, NUB, AND SMC GPIO'S ARE REFERENCED TO PP1V25_S2_AOP
SOC: AOP
U0600
TMLR68A0-B09
BGA
SYM 7 OF 23
output if gyro, input for radar
I2C0 is ALS for portables
106
106
106
106
106
106
106
106
106
OUT
OUT
IN
OUT
51 106
OUT
51 106
IN
51 106
IN
74
IN
62 63
OUT
62 63
OUT
IN
OUT
BI
OUT
BI
74
OUT
74
OUT
NC_R1_DUMP_TRIG
NC_AOP_FUNC1
106
NC_R1_RTC_SYNC
NC_R1_INT
NC_SPI_R1_CS_L
NC_AOP_FUNC5
106
SPI_GYRO_CS_L
GYRO_INT
GYRO_MOTION_INT
LID_OPEN
NC_AOP_FUNC10
106
WLAN_CONTEXT_A
WLAN_CONTEXT_B
NC_ALS_INT_L
NC_AOP_FUNC14
106
I2C_AOP_ALS_SCL
I2C_AOP_ALS_SDA
NC_I2C_AOP_ENET_SCL
NC_I2C_AOP_ENET_SDA
NC_PDM_CLK1
106
NC_PDM_CLK2
106
PDM_DMIC_CLK3
PDM_DMIC_CLK4
NC_PDM_CLK5
106
NC_PDM_CLK6
106
BB18
BC16
BC12
BC13
BA16
BA13
BA15
BD13
BD16
BA14
BB12
BD20
BA11
BD18
BA10
BC20
BB19
BB16
BE15
BB9
BC9
BC6
BD9
BC8
BD8
AOP_FUNC[0]
AOP_FUNC[1]
AOP_FUNC[2]
AOP_FUNC[3]
AOP_FUNC[4]
AOP_FUNC[5]
AOP_FUNC[6]
AOP_FUNC[7]
AOP_FUNC[8]
AOP_FUNC[9]
AOP_FUNC[10]
AOP_FUNC[11]
AOP_FUNC[12]
AOP_FUNC[13]
AOP_FUNC[14]
AOP_I2CM0_SCL
AOP_I2CM0_SDA
AOP_I2CM1_SCL
AOP_I2CM1_SDA
AOP_PDM_IN_CLK1/AOP_I2S1_BCLK
AOP_PDM_IN_CLK2/AOP_I2S0_MCK
AOP_PDM_IN_CLK3/AOP_I2S0_LRCK
AOP_PDM_IN_CLK4/AOP_I2S0_DOUT
AOP_PDM_IN_CLK5/AOP_I2S0_DIN
AOP_PDM_IN_CLK6/AOP_I2S0_BCLK
IPD
IPD
IPU
AOP GPIO
AOP I2C
AOP PDM
NUB_CLK_OUT0
NUB_DOCK_ATTENTION/CTM_TRIGGER
NUB_DOCK_CONNECT
NUB_GPIO_0/AOP_FUNC15/NUB_CLK_OUT1
NUB_GPIO_1/AOP_PDM_IN_CLK0
NUB_GPIO_2/AOP_PDM_IN_DATA0
NUB_GPIO_3/AOP LEAP_MADI_IN
IPU
NUB_GPIO_6/AOP_PDM_OUT_DATA0/AOP_FUNC16
NUB GPIO
NUB SPMI
NUB SWD
NUB_GPIO_4/AOP_LEAP_MADI_OUT
NUB_GPIO_5/AOP_PDM_OUT_CLK0
NUB_GPIO_7/A P_ U C17
NUB_GPIO_8/AOP_FUNC18
NUB_GPIO_9/AOP_FUNC19
NUB_GPIO_10/AOP_FUNC20
NUB_GPIO_11/KIS_GPIO0/AOP_FUNC21
NUB_GPIO_12/KIS_GPIO1/AOP_FUNC22
NUB_SPMI0_SCLK
NUB_SPMI0_SDATA
NUB_SPMI1_SCLK
NUB_SPMI1_SDATA
NUB_SWD_TCK_OUT0
NUB_SWD_TMS0
NUB_SWD_TMS1
BA17
BC15
BC17
BD14
BD15
BD21
BD17
BB13
BD19
BD22
BB10
BD12
BD11
BC10
BB7
BD10
BB15
BC14
BA12
BC11
BC18
BC19
BC21
DFR_TOUCH_CLK32K_RESET_L
TP_SOC_DOCK_ATTENTION
SOC_DOCK_CONNECT
NC_BKLT_PWR_ON_SMC_LED_SEL
CODEC_RESET_L
SOC_SW_DBG
IPD_SPI_INT_L
SMC_FIXTURE_MODE_L
CHGR_INT_L
NC_ENET_I2C_LOM_INT_L
NC_ACDC_ID
NC_ACDC_BURST_EN_L
NC_SPI_DP2HDMI_HOLD_L
NC_HDMI_CEC_AOP_TX
NC_HDMI_CEC_AOP_RX
NC_HDMI_HPD_AOP
SPMI_NUB_MPMU_CLK_R
SPMI_NUB_MPMU_DATA_R
SPMI_NUB_SPMU_CLK_R
SPMI_NUB_SPMU_DATA_R
SWD_NUB_SWCLK
SWD_NUB_PMU_SWDIO
NC_SWD_NUB_R1_SWDIO
OUT
18 106
IN
OUT
OUT
OUT
N
IN
IN
IN
IN
OUT
OUT
OUT
IN
IN
OUT
BI
OUT
BI
OUT
BI
BI
88
9 96
106
76 80
94
106
18 89
106
106
106
106
106
106
106
106
18
18
1
18
29 33
29 33
106
DOC_ATTENTION should be a TP
for non dev programs,
SOC_SW_DBG SHOULD GO TO
A LED IF POSSIBLE.
NEEDS A TEST POINT AT MINIMUM
FIXTURE_MODE_L should be aliased to a TP
for non dev programs,
The TP is required
102 11 9
5 33 74 89 90 100
IN
PP1V25_S2
PMU_RESET_L
R1083
10K
5%
/2 W
MF
201
NC_PDM_DATA1
106
NC_PDM_DATA2
106
74
IN
74
IN
51
IN
18
OUT
18
OUT
18
OUT
18
BI
1
2
18 33
IN
PDM_DMIC_DATA3
PDM_DMIC_DATA4
SPI_AOP_GYRO_R1_MISO
SPI_AOP_GYRO_R1_MOSI_R
SPI_AOP_GYRO_R1_CLK_R
NC_AOP_SPMI0_SCLK
106
NC_AOP_SPMI0_SDATA
106
SPMI_SE_CLK_R
SPMI_SE_DATA_R
NC_AOP_UART2_D2R
106
NC_AOP_UART2_R2D
106
PMU_CLK32K_SOC
CKP S_W IVE=CLK_DATA_CON
CKPLUS_WAIVE=CLK_DATA_CON
BE21
BE16
BE19
BD5
BF15
BF14
BF17
BF18
BF19
BF20
BF21
BB3
BB4
BE6
BF10
BB5
AOP_PDM_IN_DATA1/AOP_I2S1_MCK
AOP_PDM_IN_DATA2/AOP_I2S1_LRCK
IPD
AOP_PDM_IN_DATA3/AOP_I2S1_DOUT/AOP_PDM_IN_CLK7
IPD
AOP_PDM_IN_DATA4/AOP_I2S1_DIN/AOP_PDM_IN_CLK8
AOP_SPI0_MISO
AOP_SPI0_MOSI
AOP_SPI0_SCLK
AOP_SPMI0_SCLK/AOP_UART0_TXD
AOP_SPMI0_SDATA/AOP_UART0_RXD
AOP_SPMI1_SCLK/AOP_UART1_TXD
AOP_SPMI1_SDATA/AOP_UART1_RXD
AOP_UART2_RXD
AOP_UART2_TXD
RT_CLK32768
CFSB_AON
COLD_RESETN
AOP SPI
AOP SPMI
AOP UART
AOP RESET
JTAG
SMC I2C
SMC UART
JTAG_SEL
IPU
IPU
IPU
IPD
SMC_I2CM0_SCL
SMC_I2CM0_SDA
SMC_I2CM1_SCL/SMC_UART1_TXD
SMC_I2CM1_SDA/SMC_UART1_RXD
SMC_I2CM2_SCL
SMC_I2CM2_SDA
SMC_I2CM3_SCL
SMC_I2CM3_SDA
SMC_I2CM4_SCL
SMC_I2CM4_SDA
IPU
SMC_UART0_RXD
SMC_UART0_TXD
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRSTN
BE4
BF5
BF16
BC1
BB1
BF7
BC3
BC2
BD4
BB2
BD6
BC5
BC7
BD7
BE7
BF9
BF4
BF8
SOC_JTAG_SEL
SWD_SOC_SWCLK
TP_JTAG_SOC_TDI
TP_JTAG_SOC_TDO
SWD_SOC_SWDIO
TP_JTAG_SOC_TRST_L
I2C_SMC_PWR_SCL
I2C_SMC_PWR_SDA
I2C_SMC_UPC_SCL
I2C_SMC_UPC_SDA
I2C_SMC_SNS1_SCL
I2C_SMC_SNS1_SDA
I2C_SMC_IPD_SCL
I2C_SMC_IPD_SDA
I2C_SMC_SNS0_SCL
I2C_SMC_SNS0_SDA
UART_SMC_DEBUGPRT_D2R
UART_SMC_DEBUGPRT_R2D
18
18
18
IN
IN
BI
O T
BI
OUT
BI
OUT
BI
OUT
OUT
BI
IN
OUT
I
4 18
18 56 89
18 56 89
106
106
43 89
3
43
43
106
106
43
43
56 89
56 89
102 11 9
PP1V25_S2
TP_AON_SLEEP1_RESET_L
18
33 100
OUT
XW1022
SHORT-14L-0.1MM SM
18 60
BI
18 60
BI
SOC_WDOG
2 1
SOC_DBG_PROBE_VALID
EUSB_DBG_P
EUSB_DBG_N
SOC_USBDBG_RESREF
1
2
R1042
200
1%
1/20W
MF
1
BB21
BF12
BF6
BF24
BE24
BE23
AON_SLEEP1_RESETN
WDOG
DBG_PROBE_VALID
DBG_USB_EDP
DBG_USB_EDM
DBG_USB_RESREF
AOP DEBUG
SMC GPIO
IPU
SMC_GPIO0
SMC_GPIO1
SMC_FPWM0
SMC_FPWM1
BF11
BF13
BE12
BE9
UPC_SMC_I2C_INT_L
NC_SMC_GPIO1
SMC_FAN_PWM
SMC_FAN_TACH
106
IN
OUT
IN
107
52 106
52
SOC_DOCK_CONNECT
1
R1066
47K
5%
1/20W
MF
201
2
PAGE TITLE
SOC: AOP
9 96
BOM_COST_GROUP=SOC
Page 10
**OK2INTEGRATE**
w w w . t e k n i s i - i n d o n e s i a . c o m
SOC: POWER (DDR,SRAM)
101 10
PP1V8_S2SW_VDD1
104
PP1V2_AWAKE_PLL
102
101 1
PP1V06_S2SW_DRAM
PP0V6_S1_VDDQL
DDR0_ZQ
10
DDR1_ZQ
10
DDR4_ZQ
10
DDR5_ZQ
10
CRITICAL
1
C1100
1.0UF
20%
4V
2
X6S
0201
PLACE_NEAR=U0600 A5:5MM
PLACE_NEAR=U0600 A7:5MM
PLACE_NEAR=U0600 A33:5MM
PLACE_NEAR=U0600 A35:5MM
CRITICAL
1
C1101
2
1
C1113
0.22UF
20%
6.3V
2
X6S-CERM
0201
1
R1161
240
%
1/20W
MF
201
2
1.0UF
20%
4V
X6S
0201
CRITICAL
1
2
1
C1112
0.1UF
10%
6.3V
2
X6S
0201
1
C1111
2.2UF
20%
4V
2
X6S-CERM
0201
1
R1162
240
1%
1/20W
MF
201
2
C1102
1.0UF
20%
4V
X6S
0201
80UM_STEN
C1105
11UF
1
2
1
R1163
240
1/20W
MF
201
2
1
2
20%
2.5V
X6T
0402
3
4
1
C1110
0.1UF
10%
6.3V
2
X6S
0201
1
C1115
1.0UF
20%
4V
2
X6S
0201
DDR0_RREF
10
DDR1_RREF
10
DDR2_RREF
10
DDR3_RREF
10
DDR4_RREF
10
DDR5_RREF
10
DDR6_RREF
10
DDR7_RREF
10
DDR0_ZQ
10
DDR1_ZQ
10
DDR4_ZQ
10
DDR5_ZQ
10
DDR0_ZQ1
10
DDR1_ZQ1
10
DDR4_ZQ1
10
DDR5_ZQ1
10
%
C1103
12PF
5%
25V
NP0-C0G
0201
80UM_STEN
C1106
11UF
20%
2.5V
X6T
0402
1
4
2
1
R1164
240
1%
1/20W
MF
201
2
1
2
80UM_STEN
C1107
1
3
1
C1114
0.01UF
10%
25V
2
X7R
0201
C1104
3.0PF
+/-0.1PF
25V
NP0-C0G
0201
11UF
20%
2.5V
X6T
0402
3
4
2
1
R1165
240
%
1/20W
MF
201
2
D21
D22
D48
D49
D7
D8
E21
E35
E48
E8
D34
D35
AJ19
AG19
AE13
T25
AA29
Y31
T33
AC43
AJ14
AH14
AC14
R25
T29
T30
T36
AA42
J1
H1
G1
A26
A31
A32
G55
H55
A5
A7
A33
A35
A6
A8
A34
A36
1
R1166
240
1%
1/20W
MF
201
2
U0600
TMLR68A0-B09
BGA
SYM 9 OF 23
VDD1_S2
VDD1_S2
VDD1_S2
VDD1_S2
VDD1_S2
VDD1_S2
VDD1_S2
VDD1_S2
VDD1_S2
VDD1_S2
VDD1_S2
VDD1_S2
VDDIO12_PLL_DDR0
VDDIO12_PLL_DDR1
VDDIO12_PLL_DDR2
VDDIO12_PLL_DDR3
VDDIO12_PLL_DDR4
VDDIO12_PLL_DDR5
VDDIO12_PLL_DDR6
VDDIO12_PLL_DDR7
VDDIO11_RET_DDR0_S2
VDDIO11_RET_DDR1_S2
VDDIO11_RET_DDR2_S2
VDDIO11_RET_DDR3_S2
VDDIO11_RET_DDR4_S2
VDDIO11_RET_DDR5_S2
VDDIO11_RET_DDR6_S2
VDDIO11_RET_DDR7_S2
DDR0_RREF
DDR1_RREF
DDR2_RREF
DDR3_RREF
DDR4_RREF
DDR5_RREF
DDR6_RREF
DDR7_RREF
DDR0_ZQ[0]
DDR1_ZQ[0]
DDR4_ZQ[0]
DDR5_ZQ[0]
DDR0_ZQ[1]
DDR1_ZQ[1]
DDR4_ZQ[1]
DDR5_ZQ[1] VDD2_S2
1
R1167
240
%
1/20W
MF
201
2
1
R1168
240
1%
1/20W
MF
201
2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
VDD2_S2
B30
B31
B52
F23
F25
F50
F52
G24
G26
G51
G53
H23
H25
H50
H52
J24
J26
J51
J53
P5
P24
P32
P51
B4
B3
B25
B26
B53
F4
F6
F31
F33
G3
G5
G30
G32
H4
H6
H31
H33
J3
J5
J30
J32
P6
P23
P33
P50
PP1V06_S2SW_DRAM
3
4
3
4
80UM_STEN
C1121
4.3UF
20%
2.5V
X6T
0402
1
4
2
80UM_STEN
C1126
4.3UF
20%
2.5V
X6T
0402
1
4
2
80UM_STEN
C1120
4.3UF
20%
2.5V
X6T
0402
1
2
80UM_STEN
C1125
4.3UF
20%
2.5V
X6T
0402
1
2
80UM_STEN
C1122
4.3UF
1
3
80UM_STEN
C1127
4.3UF
1
3
101 10
20%
2.5V
X6T
0402
2
20%
2.5V
X6T
0402
2
3
4
3
4
80UM_STEN
C1123
4.3UF
20%
2.5V
X6T
0402
1
4
2
80UM_STEN
C1128
4.3UF
20%
2.5V
X6T
0402
1
4
2
80UM_STEN
C1124
4.3UF
1
3
80UM_STEN
C1129
4.3UF
1
3
20%
2.5V
X6T
0402
2
20%
2.5V
X6T
0402
2
PP0V6_S1_VDDQL
3
4
3
4
3
4
80UM_STEN
C1132
4.3UF
20%
2.5V
X6T
0402
1
4
2
80UM_STEN
C1136
4 3UF
20%
5
X6T
0402
1
4
2
1
C1150
12PF
5%
25V
2
NP0-C0G
3
3
0201
1
C1151
3.0PF
+/-0.1PF
25V
2
NP0-C0G
0201
80UM_STEN
C1131
4.3UF
U0600
TMLR68A0-B09
BGA
SYM 8 OF 23
AA14
AA16
AA40
AB15
AB41
AC16
AC40
AD15
AE16
AF15
AG14
AH15
AK15
AL14
AL16
AM15
AM17
3
4
3
4
B21
B23
B33
B35
B50
B6
B8
C22
C24
C3
C32
C34
C49
C5
C51
C53
C7
D23
D25
D31
D33
D4
D50
D52
D6
E24
E26
E3
E30
E32
E51
E53
K24
K26
K3
K30
K32
K5
K51
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
VDDQL_S1
K53
L23
L25
L31
L33
L4
L50
L52
L6
M24
M26
M3
M30
M32
M5
M51
M53
N25
N31
N4
N52
T16
T18
T20
T22
T26
T28
T32
T38
T40
U14
U15
U17
U19
U21
U23
U25
U27
U29
U31
U33
U35
U37
U39
V16
V22
V24
V26
V32
V34
V40
W14
W40
Y15
80UM_STE
C1133
4.3UF
20%
2.5V
X6T
0402
1
4
2
80UM_STEN
C1140
4.3UF
20%
2.5V
X6T
0402
1
4
2
80UM_STEN
C1134
1
3
80UM_STEN
C1141
1
3
4.3UF
20%
5V
X6T
0402
4
2
4 3UF
20%
2.5V
X6T
0402
4
2
3
3
20%
2.5V
X6T
0402
1
2
80UM_STEN
C1135
4.3UF
20%
2.5V
X6T
0402
1
2
80UM_STEN
C1142
4.3UF
20%
2.5V
X6T
0402
1
2
101 10
101 10
DDR0_ZQ1
10
DDR1_ZQ1
10
DDR4_ZQ1
10
DDR5_ZQ1
10
PP0V6_S1_VDDQL
DDR0_RREF
10
DDR1_RREF
10
DDR2_RREF
10
DDR3_RREF
10
DDR4_RREF
10
DDR5_RREF
10
DDR6_RREF
10
DDR7_RREF
10
PLACE_NEAR=U0600 A6:5MM
PLACE_NEAR=U0600 A8:5MM
PLACE_NEAR=U0600 A34:5MM
PLACE_NEAR=U0600 A36:5MM
1
R1169
240
1%
1/20W
MF
201
2
PLACE_NEAR=U0600 J1: MM
PLACE_NEAR=U0600 H1: MM
PLACE_NEAR=U0600.G1:5MM
PLACE_NEAR=U0600 A26:5MM
PLACE_NEAR=U0600 A31:5MM
PLACE_NEAR=U0600 A32:5MM
PLACE_NEAR=U0600 G55:5MM
PLACE_NEAR=U0600.H55:5MM
1
R1170
240
1%
1/20W
MF
201
2
1
R1171
240
1%
1/20W
MF
201
2
1
R1172
240
1%
1/20W
MF
201
2
1
R1173
240
1%
1/20W
MF
201
2
1
R1174
240
1%
1/20W
MF
201
2
1
R1175
240
1%
1/20W
MF
201
2
1
R1176
240
1%
1/20W
MF
201
2
PAGE TITLE
SOC: POWER (DDR,SRAM)
BOM_COST_GROUP=SOC
2
1
Page 11
**OK2INTEGRATE**
w w w . t e k n i s i - i n d o n e s i a . c o m
102 9
102
PP1V25_S2
PP1V25_S2
Internally generated rail
PP0V6_S2_GRP1
VOLTAGE=0.6V
PP0V6_S2_GRP2
20%
2.5V
X6S
0201
1
2
1
C1210
2.2UF
20%
4V
2
X6S-CERM
0201
1
C1213
2.2UF
20%
4V
2
X6S-CERM
0201
C1200
4UF
C1201
4UF
20%
2.5V
X6S
0201
1
C1211
0.1UF
10%
6.3V
2
X6S
0201
SOC: POWER (IO)
VOLTAGE=0.6V
1
2
U0600
TMLR68A0-B09
BGA
SYM 14 OF 23
C1234
2.2UF
20%
X6S-CERM
4V
0201
AR40
AP40
BB22
AY23
1
2
AY25
AY27
BA24
BA26
VDD06_GRP1_S2
VDD06_GRP2_S2 VDD2_S2_SENSE2
VDDDIO_HIB_S4
VDDIO12_ OP_S2
VDDIO12_AOP_S2
VDDIO12_AOP_S2
VDDIO12_AOP_ 2
VDDIO12_AOP_S2
VDD2_S2_SENSE1
VDD_PCPU_SENSE
VDD_ECPU_ ENSE
VDD_GPU_SENSE
VDD_SOC_S1_SENSE
VDD_DISP_S1_SENSE
VDD_DCS_SENSE
VDDQL_SENSE
B10
B37
AD36
AN23
AC23
AH22
Y17
AN17
AN15
VSNS_VDD2_1
VSNS_VDD2_2
VSNS_VDD_PCPU
VSNS_VDD_ECPU
VSNS_VDD_GPU
VSNS_VDD_SOC
VSNS_VDD_DISP
VSNS_VDD_DCS
VSNS_VDDQL
48
48
45 48
45 48
45 48
45 48
48
48
48
102 8 6 5 4
PP1V25_AWAKE_IO
CRITICAL
20%
6.3V
0402
1
2
C1233
10UF
CER-X6S
138S00073
XW1232
SM
2 1
XW1231
SM
VOLTAGE=1.25V
97
PP1V25_AWAKE_GRP5
VOLTAGE=1.25V
2 1
PP1V25_AWAKE_GRP4
97
C1232
2.2UF
20%
X6S-CERM
0201
102 97
PP1V8_AWAKE
AP39
XW1230
SM
20%
4V
0201
1
2
C1231
2.2UF
X6S-CERM
1
2
VOLTAGE=1.25V
2 1
PP1V25_AWAKE_GRP3
97
20%
4V
0201
1
2
C1230
2.2UF
X6S-CERM
AF41
AG42
AH40
AL40
AN40
AT40
AV40
AP16
AR17
AT16
AU17
AV16
AW17
AP41
AR41
VDDIO12_GRP1_S2
VDDIO12_GRP3
VDDIO12_GRP3
VDDIO12_GRP3
VDDIO12_GRP3
VDDIO12_GRP3
VDDIO12_GRP4
VDDIO12_GRP4
VDDIO12_GRP5
VDDIO12_GRP5
VDDIO12_GRP5
VDDIO12_GRP5
VDDIO12_GRP5
VDDIO12_GRP5
VDDIO18_GRP1
VDDIO18_GRP1
VSS_PCPU_SENSE
VSS_DDR_SENSE
VSS_SENSE1
VSS_S NSE2
AD37
AN16
B9
B36
VSNS_VSS_PCPU
VSNS_VSS_DDR
VSNS_VSS_1
VSNS_VSS_2
45 48
48
48
48
C1240
2.2UF
2 %
X6S-CERM
0201
1
V
2
SOC: POWER (IO)
BOM_COST_GROUP=SOC
1 2
Page 12
**OK2INTEGRATE**
w w w . t e k n i s i - i n d o n e s i a . c o m
4
SOC: POWER (CPU, GPU)
80UM_STEN
C1310
11UF
20%
2.5V
X6T
0402
1
3
4
2
80UM_STEN
C1318
11UF
20%
2.5V
X6T
0402
1
2
101 12
80UM_STEN
C1311
11UF
1
3
20%
2 5V
X T
0402
2
4
80UM_STEN
C1312
11UF
20%
2.5V
X6T
0402
1
3
2
80UM_STEN
C1319
11UF
20%
2.5V
X6T
0402
1
3
4
2
PPVDD_PCPU_AWAKE
25V
0201
3
1
2
80UM_STEN
C1314
11UF
2.5V
0402
1
2
C1300
3.0PF
+/-0.1PF
NP0-C0G
80UM_STEN
C1313
11UF
20%
2.5V
X6T
0402
1
3
4
4
2
C1301
NP0-C0G
20%
X6T
3
4
12PF
5%
25V
0201
80UM_STEN
C1315
11UF
20%
2.5V
X6T
0402
1
2
0.575V @ 4400MA
U0600
TMLR68A0-B09
BGA
SYM 11 OF 23
AE33
AE35
AE36
AE37
AF33
AF36
AF39
AG34
AG38
AH34
AH39
AJ33
AJ34
AK29
AK33
1
2
80UM_STEN
C1316
11UF
20%
2.5V
X6T
0402
1
3
4
4
2
80UM_STEN
C1317
1
3
11UF
20%
2.5V
X6T
0402
4
2
3
AK35
AK36
AK38
AK40
AK41
AK42
AK43
AK44
AK45
AK46
AL30
AL32
AL37
AL41
AL42
AL43
AL44
AL45
AL46
AM29
AM34
AM38
AM41
AM42
AM43
AM44
AM45
AM46
AM47
AM48
AM49
AM50
AM51
AM52
AM53
AM54
AM55
AN33
AN34
AN38
AN42
AN43
AN44
AN45
AN46
AN47
AN48
AN49
AN50
AN51
AN52
AN53
AN54
AN55
AP29
AP33
AP38
AP43
AP44
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_ CPU
VDD_PC U
VDD_PCPU
VDD_PCPU
VDD_PCPU
VDD_ECPU
VDD_ECPU
VDD_ECPU
VDD_ECPU
VDD_ CPU
VDD_EC U
VDD_ECPU
VDD_ECPU
VDD_ECPU
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SO _S1
VDD_SOC_ 1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SO _S1
VDD_SOC_ 1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SO _S1
VDD_SOC_ 1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SO _S1
VDD_SOC_ 1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
VDD_SOC_S1
AP45
AP46
AP47
AP48
AP49
AP50
AP51
AP52
AR30
AR32
AR33
AR35
AR36
AR37
AR39
AK25
AL26
AL28
AL29
AN24
AN29
AP25
AR26
AR28
AB23
AC33
AC38
AE23
AE32
AE38
AF28
AG23
AG39
AJ20
AJ22
AJ24
AJ26
AJ28
AJ30
AJ32
AL20
AL22
AL24
AM39
AN18
AN20
AN22
AR18
AR22
AR24
AT33
AT35
AT37
AU18
AU20
AU22
AU24
AU26
AU28
AU30
AU38
Y21
Y26
Y36
PPVDD_PCPU_AWAKE
PPVDD_ECPU_AWAKE
80UM_STEN
C1320
1
80UM_STEN
C1330
11UF
20%
2.5V
X6T
0402
80UM_STEN
C1334
11UF
20%
2.5V
X6T
0402
1
3
11UF
20%
2.5V
X6T
0402
4
2
3 1
4
80UM_STEN
C1335
1
80UM_STEN
C1321
3
1
80UM_STEN
C1331
11UF
20%
2.5V
X6T
0402
1
2
11UF
20%
2.5V
X6T
0402
11UF
20%
2.5V
X6T
0402
4
2
3
4
80UM_STEN
C1336
1
3
80UM_STEN
C1322
3
1
80UM_STEN
C1332
11UF
20%
2.5V
X6T
0402
1
2
11UF
20%
2.5V
X6T
0402
3
11UF
20%
2.5V
X6T
0402
4
2
3
80UM_STEN
C1337
1
101 12
80UM_STEN
C1323
3
1
80UM_STEN
C1333
11UF
20%
2.5V
X6T
0402
1
2
11UF
20%
2.5V
X6T
0402
3
11UF
PPVDD_GPU_AWAKE
101 12
80UM_STEN
C1324
20%
2.5V
X6T
0402
2
4
3
4
PPVDD_SOC_S1
3
11UF
2.5V
0402
1
2
20%
X6T
20%
2.5V
X6T
0402
3
101
4
1
C1341
3.0PF
+/-0.1PF
25V
2
N 0-C0G
02 1
3
80UM_STEN
C1351
11UF
2 %
2.5V
X6T
0402
1
3
4
2
101
80UM_STEN
C1352
11UF
20%
2.5V
X6T
0402
1
3
4
2
AA24
AA26
AA28
AA31
AA33
AA35
AA37
AB25
AB27
AB28
AB30
AB32
AB34
AB36
AC24
AC26
AC31
AC35
AC37
AD25
AD27
AD32
AD34
AD41
AD42
AD43
AD44
AD45
AD46
AD47
AD48
AD49
AD50
AD51
AD52
AD53
AD54
AD55
AE24
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
1
C1340
12PF
5%
25V
2
NP0-C0G
0201
80UM_STEN
C1325
11UF
3
4
1
2
80UM_STEN
C1350
11UF
20%
2.5V
X6T
0402
1
4
2
U0600
TMLR68A0-B09
BGA
SYM 12 OF 23
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_GPU
VDD_DISP_S1
VDD_DISP_S1
VDD_DISP_S1
VDD_DISP_S1
VDD_DISP_S1
VDD_DISP_S1
VDD_DISP_S1
VDD_DISP_S1
VDD_DISP_S1
AE26
AE27
AE29
AE30
AE31
AE42
AE43
AE44
AE45
AE46
AE47
AE48
AE49
AE50
AE 1
AE52
AE53
AE54
AE55
AF24
AF32
AG25
AG27
AG31
AG33
AA19
AA21
AA23
AB22
AC19
AD22
AE19
AE21
AG21
PPVDD_GPU_AWAKE
80UM_STEN
C1353
11UF
20%
2.5V
X6T
0402
1
4
2
80UM_STEN
C1354
3
1
PPVDD_DISP_S1
1
C1370
12PF
5%
25V
2
NP0-C0G
0201
11UF
20%
2 5V
X6T
0402
3
4
2
80UM_STEN
C1361
11UF
20%
2.5V
X6T
0402
1
4
2
80UM_STEN
C1365
11UF
2.5V
0402
1
2
80UM_STEN
C1355
11UF
20%
2.5V
X6T
0402
1
2
80UM_STEN
C1362
11UF
1
3
20%
X6T
3
4
4
20%
2.5V
X6T
0402
2
80UM_STEN
C1356
3
1
3
4
11UF
20%
2 5V
X6T
0402
3
4
2
80UM_STEN
C1363
11UF
20%
2.5V
X6T
0402
1
4
2
80UM_STEN
C1366
11UF
20%
2.5V
X6T
0402
3 1
4
80UM_STEN
C1357
11UF
20%
2.5V
X6T
0402
1
4
2
80UM_STEN
C1364
11UF
20%
2.5V
X6T
0402
1
3
2
101 12
3
101
3
4
4
4
4
4
2
2
2
2
PAGE TITLE
SOC: POWER (SOC, CPU, GPU)
BOM_COST_GROUP=SOC
Page 13
**OK2INTEGRATE**
w w w . t e k n i s i - i n d o n e s i a . c o m
SOC: POWER (SRAM, SOC)
U0600
TMLR68A0-B09
BGA
SYM 10 OF 23
101
PVDD_CPU_SRAM_AWAKE
80UM_STEN
C1400
11UF
20%
2.5V
X6T
0402
1
PPVDD_DCS_S1
101
3
4
2
80UM_STEN
C1401
11UF
20%
2.5V
X6T
0402
1
4
2
80UM_STEN
C1402
11UF
2.5V
0402
1
3
2
80UM_STEN
C1410
11UF
20%
2.5V
X6T
0402
1
2
20%
X6T
4
80UM_STEN
3
4
80UM_STEN
C1411
3
C1403
11UF
20%
2.5V
X6T
0402
1
4
2
11UF
20%
2.5V
X6T
0402
1
4
2
80UM_STEN
3
80UM_STEN
3
C1404
11UF
20%
2.5V
X6T
0402
1
3
4
2
C1412
11UF
20%
2.5V
X6T
0402
1
3
4
2
80UM_STEN
C1405
11UF
20%
2.5V
X6T
0402
1
4
2
80UM_STEN
C1413
11UF
20%
2.5V
X6T
0402
1
4
2
AE34
AE39
AG36
AH35
AH37
AJ36
AJ38
AK27
AK31
AK37
AL33
AL35
AL38
1
C1406
12PF
5%
25V
NP0-C0G
0201
3
3
1
C1407
3.0PF
+/-0.1PF
25V
2
NP0-C0G
0201
AM25
AM26
AM31
AM36
AN26
AN27
AN30
AN32
AN35
AN37
AP27
AP36
AR31
AR34
AR38
AA39
AB17
AB38
AC18
AC39
AD17
AE18
AF17
AG18
AJ18
AK17
AL18
VDD CPU_SRAM
VDD CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD CPU_SRAM
VDD CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD CPU_SRAM
VDD CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD_CPU_SRAM
VDD DCS_S1
VDD DCS_S1
VDD_DCS_S1
VDD_DCS_S1
VDD_DCS_S1
VDD_DCS_S1
VDD_DCS_S1
VDD_DCS_S1
VDD_DCS_S1
VDD_DCS_S1
VDD DCS_S1
VDD DCS_S1
W17
VDD_DCS_S1
W22
VDD_DCS_S1
W24
VDD_DCS_S1
W26
VDD_DCS_S1
W31
VDD_DCS_S1
W33
VDD_DCS_S1
W35
VDD_DCS_S1
W39
VDD_DCS_S1
Y18
VDD DCS_S1
Y20
VDD DCS_S1
Y23
VDD_DCS_S1
Y25
VDD_DCS_S1
Y27
VDD_DCS_S1
Y29
VDD_DCS_S1
Y32
VDD_DCS_S1
Y34
VDD_DCS_S1
Y38
VDD_DCS_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_ 1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_ 1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_ 1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_ 1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
VDD_SRAM_S1
AA18
AA32
AB20
AB24
AB31
AB35
AC21
AC28
AC30
AD20
AD21
AD24
AD28
AD30
AD35
AF20
AF22
AF26
AF30
AG28
AH19
AH21
AH23
AH25
AH27
AH29
AH31
AK19
AK21
AK23
AM19
AM21
AM23
AP21
AP23
AT19
AT21
AT23
AT25
AT27
AT29
AT31
AT39
AU36
AV37
PP0V764_S1_SRAM
C1420
11UF
20%
2.5V
X6T
0402
1
3
4
2
80UM_STEN 80UM_STEN
C1421
11UF
20%
2.5V
X6T
0402
1
2
3
4
80UM_STEN
C1422
11UF
20%
2.5V
X6T
0402
1
4
2
80UM_STEN
3
C1423
11UF
20%
2.5V
X6T
0402
1
3
4
2
80UM_STEN
C1424
11UF
20%
2.5V
X6T
0402
1
4
2
101 482
80UM_STEN
C1425
11UF
20%
2.5V
X6T
0402
3
1
3
4
2
PAGE TITLE
SOC: POWER (SRAM)
BOM_COST_GROUP=SOC
Page 14
**OK2INTEGRATE**
w w w . t e k n i s i - i n d o n e s i a . c o m
PP0V805_S1_VDD_FIXED
103
PP0V805_S1_VDD_FIXED
103
103 14
103 14
PP0V805_S1_VDD_FIXED
PP0V805_S1_VDD_FIXED
80UM_STEN
C1513
4.3UF
103 14
103 97
102 48
PP0V805_S1_VDD_FIXED
PP0V805_S1_VDD_FIXED
103
PP0V805_S1_VDD_FIXED
PP0V72_S2_VDD_LOW
PP0V72_S2_VDD_LOW
102
PP0V72_S2_VDD_LOW
102
20%
2.5V
X6T
0402
4
2
C1520
C1507
2.2UF
X6S-CERM
3
3.0PF
+/-0.1PF
25V
NP0-C0G
0201
2 %
0201
1
2
V
1
2
C1508
0.1UF
10%
6.3V
X6S
0201
1
2
FL1510
120OHM-25%-0.25A-0.5OHM
2 1
0201
1
C1510
2.2UF
20%
4V
2
X6S-CERM
0201
C1521
2.2UF
20%
X6S-CERM
4V
0201
1
2
C1511
2.2UF
20%
X6S-CERM
4V
0201
PP0V805_S1_VDD_FIXED
103
PP0V805_S1_VDD_FIXED
103
C1505
0.1UF
PP0V805_S1_VDD_FIXED
R1500
0
5%
1/20W
MF
0201
C1514
0.1UF
103 14
2 1
10%
6.3V
X6S
0201
PP0V805_S1_VDD_FIXED
VOLTAGE=0.805V
103
VOLTAGE=0.805V
PP0V805_S1_SOC_VDDFIXEDPCIE_R
10%
6.3V
X6S
0201
6.3V
0201
10%
X6S
1
2
1
C1503
0.1UF
2
1
2
C1515
0.1UF
C1502
0.1UF
PP0V805_S1_SOC_VDDFIXEDPLL_F
1
C1512
0.1UF
2
R1590
10
5%
1/20W
MF
201
117S0004
2 1
1
10
6.3V
X6S
0201
VOLTAGE=0 805V
C1516
0.1UF
10%
6.3V
X6S
0201
1
2
PP0V805_S1_SOC_VDDFIXEDXTAL_R
1
C1590
4UF
20%
2.5V
2
X6S
0201
138S00329
80UM_STEN
C1530
4.3UF
1
R1535
10
2 1
5%
1/20W
MF
201
R1536
49.9
1%
1/20W
MF
201
PP0V72_S2_VDD_LOW
102
VOLTAGE=0.72V
PP0V72_S2_VDD_LOWFLPLL_R
20%
6.3V
0201
1
C1536
4UF
20%
2.5V
2
X6S
0201
1
2
C1535
0.22UF
X6S-CERM
VOLTAGE=0.72V
2 1
PP0V72_S2_VDD_LOWULPPLL_R
1
10%
6.3V
2
X6S
0201
C1500
2.2UF
20%
10
X6S
4V
0201
1
2
X6S-CERM
6.3V
0201
C1517
0.22UF
20%
2.5V
X6T
0402
2
20%
6.3V
X6S-CERM
0201
3
4
C1506
2.2UF
X6S-CERM
0201
1
C1501
0.1UF
2
C1504
2.2UF
20%
X6S-CERM
0201
1
2
80UM_STEN
C1531
4.3UF
20%
2.5V
X6T
0402
1
4
2
20%
4V
4V
6.3V
0201
3
10%
X6S
1
2
U0600
TMLR68A0-B09
BGA
10%
6.3V
X6S
0201
10%
6.3V
X6S
0201
1
4V
2
0.1UF
10%
6.3V
X6S
0201
1
C1584
4.7UF
20%
6.3V
2
CER
0402
1
2
1
2
R1574
0
5%
1/20W
MF
0 01
1
2
R1584
49.9
2 1
C1571
0.1UF
10%
6.3V
X6S
0201
2 1
1%
/ 0W
MF
201
1
C1572
2.2UF
2
X6S-CERM
PP1V25_S2
80UM_STEN
C1555
4.3UF
1
1
20%
4V
2
0201
20%
2.5V
X6T
0402
2
4
SYM 13 OF 23
C1540
0.1UF
AM28
AW19
AW20
AW21
BA37
1
2
1
2
BA38
BA39
AY18
AV33
AV29
AV30
AV31
AV32
AL34
AT32
AF29
AR20
AH13
AG13
AC13
AC42
AD40
AG40
AJ39
AP17
AU32
AV39
AY16
AV23
AV25
AV27
AW26
AY26
BA23
AW24
AW22
AW28
BA22
VDD_FIXED_ECPU_S1
VDD_FIXED_LPDP_RX_S1
VDD_FIXED_LPDP_RX_S1
VDD_FIXED_LPDP_RX_S1
VDD_FIXED_LPDP_TX_S1
VDD_FIXED_LPDP_TX_S1
VDD_FIXED_LPDP_TX_S1
R11
VDD_FIXED_MIPIC_S1
R12
VDD_FIXED_MIPIC_S1
R13
VDD_FIXED_MIPIC_S1
R10
VDD_FIXED_MIPID_PLL_S1
P9
VDD_FIXED_MIPID_S1
R9
VDD_FIXED_MIPID_S1
VDD_FIXED_MTR_S1
VDD_FIXED_PCIE_REFBUF_S1
VDD_FIXED_PCIE_S1
VDD_FIXED_PCIE_S1
VDD_FIXED_PCIE_S1
VDD_FIXED_PCIE_S1
VDD_FIXED_PCPU_S1
VDD_FIXED_PLL_ANE_S1
VDD_FIXED_PLL_GPU_S1
VDD_FIXED_PLL_SOC_S1
VDD_FIXED_PLL_DDR0_S1
VDD_FIXED_PLL_DDR1_S1
VDD_FIXED_PLL_DDR2_S1
T24
VDD_FIXED_PLL_DDR3_S1
R28
VDD_FIXED_PLL_DDR4_S1
R29
VDD_FIXED_PLL_DDR5_S1
T34
VDD_FIXED_PLL_DDR6_S1
VDD_FIXED_PLL_DDR7_S1
A32
VDD_FIXED_XTAL_S1
VDD_FIXED_S1
VDD_FIXED_S1
VDD_FIXED_S1
VDD_FIXED_S1
VDD_FIXED_S1
VDD_FIXED_S1
VDD_FIXED_S1
V17
VDD_FIXED_S1
VDD_LOW_S2
VDD_LOW_S2
VDD_LOW_S2
VDD_LOW_S2
VDD_LOW_S2
VDD_LOW_S2
VDD_LOW_FLPPLL_S2
VDD_LOW_ULPPLL_S2
VDD_LOW_USB_DEBUG_S2
VDD_HIB_S4
VDD_CIO
VDD_CIO
VDD_CIO
VDD12_CIO_S2
VDD12_CIO_S2
VDD12_CIO_S2
VDD12_CIO_S2
VDD12_CIO_S2
VDD12_CIO_S2
VDD12_CIO_S2
VDD_CIO_USB
VDD12_CIO_USB_S2
VDD12_AMUX_S2
VDD12_LPDP_RX
VDD12_LPDP_RX
VDD12_LPDP_RX
VDD12_LPDP_RX
VDD12_LPDP_RX
VDD12_LPDP_RX
VDD12_LPDP_RX
VDD12_LPDP_RX
VDD12_LPDP_TX
VDD12_LPDP_TX
VDD12_LPDP_TX
VDD12_MIPIC
VDD12_MIPIC
VDD12_MIPIC
VDD12_MIPID
VDD12_MIPID
VDD12_MTR
VDD12_PCIE
VDD12_PCIE
VDD12_PCIE
VDD12_PCIE
VDD12_PCIE
VDD12_PCIE
VDD12_PCIE
VDD12_PCIE_REFBUF
VDD12_PLL_ANE
VDD12_PLL_CPU
VDD12_PLL_GPU
VDD12_PLL_SOC
VDD12_TSADC_CPU
VDD12_TSADC_SOC0
VDD12_TSADC_SOC1
VDD12_TSADC_SOC2
VDD12_TSADC_SOC3
VDD12_TSADC_SOC4
VDD12_ULPPLL_S2
VDD12_USB_DEBUG_S2
VDD12_XTAL
AV34
AV36
AW35
AU42
AU43
AV42
AV43
AY34
AY36
BA35
AU34
AU35
AT42
AV11
AV20
AW11
AW13
AY13
AY19
AY20
AY21
AW37
AW38
AW39
P11
P12
P13
P8
R8
AW18
AY29
AY30
AY31
AY32
AY43
B 42
BA43
AW33
AP31
AK34
AG29
AP19
AK32
U20
Y33
AH32
AY15
AE40
AW23
AY28
BA33
PP1V2_S2_CIO
C1544
0.1UF
PP0V855_S2SW_CIO
PP1V2_S2_CIO
PP1V25_S2
PP1V25_AWAKE_IO
PP1V2_AWAKE_PLL
10%
6.3V
X6S
0201
1
2
C1550
2.2UF
20%
X6S-CERM
4V
0201
1
C1551
0.1UF
PP1V25_AWAKE_IO
C1560
2.2UF
2 %
X6S-CERM
0201
1
C1561
0.1UF
V
10%
6.3V
X6S
0201
1
2
PP1V25_AWAKE_IO
PP1V2_AWAKE_PLL
10%
6 3V
X6S
020
1
2
C1554
0.1UF
10%
6.3V
X6S
0201
C1553
0.1UF
VOLTAGE=1.2V
PP1V2_AWAKE_PLL_PCIE_R
C1573
0.1UF
PP1V2_AWAKE_PLL
PP1V25_AWAKE_IO
VOLTAGE=1.25V
PP1V25_S2_ULPPLL_R
PP1V25_S2
1
C1582
0.1UF
10%
6.3V
2
X6S
0201
1
10%
6.3V
2
X6S
0201
1
10%
6.3V
2
X6S
020
C15622
1
2
10%
6.3V
X6S X6S-CERM
0201
C1541
C1545
2.2UF
20%
X6S-CERM
1
2
4V
201
C1574
2.2UF
0.1UF
0.1UF
1
2
20%
0201
C1570
102
102
80UM_STEN
3
80UM_STEN
C1542
4.3UF
20%
2.5V
X6T
0402
1
4
2
C1546
4.3UF
20%
2.5V
X6T
0402
1
3
4
2
3
102
103
102
102
102
102
102
80UM_STEN
C1556
1
102
102
80UM_STEN
80UM_STEN
C1547
1
4.3UF
20%
2.5V
X T
0402
4
2
C1543
4.3UF
20%
2.5V
X6T
0402
1
4
2
4.3UF
20%
2.5V
X6T
0402
3
4
2
3
3
LPDP_RX POWER MAY BE GROUNDED
BUT J293 IS NOT DOING THIS PER
<RDAR://61722166>
PP0V855_S2SW_CIO
102
103
102
FL1580
VDD12_EFUSE1
VDD12_EFUSE2
VDD12_EFUSE3
VDD12_FMON
AU40
AT20
AB43
AU19
VOLTAGE=1.25V
PP1V25_AWAKE_XTAL_F
VOLTAGE=1.25V
PP1V25_AWAKE_FMON_R
1
C1583
2.2UF
20%
4V
2
X6S-CERM
0201
240-OHM-0.2A-0.9-OHM
2 1
0201
1
C1580
0 1UF
10%
6.3V
2
X6S
0201
R1583
49.9
1/20W
1%
MF
201
2 1
1
C1581
2.2UF
20%
4V
2
X6S-CERM
0201
PP1V25_AWAKE_IO
PP1V25_AWAKE_IO
1 2
102
PAGE TITLE
SOC: POWER (Fixed, PLL's, Filtered)
PP0V72_S2_VDD_LOW
102
C1537
0.1UF
10%
6.3V
X6S
0201
1
2
BOM_COST_GROUP=SOC
2
1
Page 15
**OK2INTEGRATE**
w w w . t e k n i s i - i n d o n e s i a . c o m
SOC: GND (1)
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A2
A20
A21
A22
A23
A24
A25
A27
A28
A29
A3
A30
A37
A38
A39
A4
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A9
AA10
AA11
AA12
AA13
AA15
AA17
AA20
AA22
AA25
AA27
AA30
AA34
AA36
AA38
AA41
AA43
AA44
AA45
AA46
AA47
AA8
AA9
AB10
AB11
AB12
AB13
AB14
AB16
AB18
AB19
AB2
AB21
AB26
AB29
AB33
AB37
AB39
AB40
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
U0600
SYM 15 OF 23
VSS VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
V S
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
V S
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
V S
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
V S
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
V S
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
V S
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
V S
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AB42
AB44
AB45
AB46
AB47
AB48
AB5
AB51
AB54
AB8
AB9
AC10
AC11
AC12
AC15
AC17
AC20
AC22
AC25
AC27
AC29
AC32
AC34
AC36
AC41
AC44
AC45
AC46
AC47
AC8
AC9
AD10
AD11
AD12
AD13
AD14
AD16
AD18
AD19
AD23
AD26
AD29
AD31
AD33
AD38
AD39
AD8
AD9
AE10
AE11
AE12
AE14
AE15
AE17
AE2
AE20
AE22
AE25
AE28
AE41
AE5
AE8
AE9
AF10
AF11
AF12
AF13
AF14
AF16
AF18
AF19
AF21
AF23
AF25
AF27
AF31
AF34
AF35
AF37
AF38
AF40
AF42
AF43
AF44
AF45
AF46
AF47
AF8
AF9
AG10
AG11
AG12
AG15
AG20
AG22
AG24
AG26
AG30
AG32
AG35
AG37
AG41
AG43
AG44
AG45
AG46
AG47
AG48
AG51
AG54
AG8
AG9
AH10
AH11
AH12
AH18
AH2
AH20
AH24
AH26
AH28
AH30
AH33
AH36
AH38
AH41
AH42
AH43
AH44
AH45
AH46
AH47
AH5
AH8
AH9
AJ10
AJ11
AJ12
AJ13
AJ15
AJ21
AJ23
AJ25
AJ27
AJ29
AJ31
AJ35
AJ37
AJ40
AJ41
AJ42
AJ43
AJ44
AJ45
AJ46
AJ47
AJ8
AJ9
AK10
AK11
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
U0600
SYM 16 OF 23
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AK12
AK13
AK14
AK16
AK18
AK20
AK22
AK24
AK26
AK28
AK30
AK39
AK47
AK49
AK51
AK54
AK8
AK9
AL10
AL11
AL12
AL13
AL15
AL17
AL19
AL2
AL21
AL23
AL25
AL27
AL31
AL36
AL39
AL47
AL5
AL55
AL8
AL9
AM10
AM11
AM12
AM13
AM14
AM16
AM18
AM20
AM22
AM24
AM27
AM30
AM32
AM33
AM35
AM37
AM40
AM6
AM7
AM8
AM9
AN1
AN10
AN11
AN12
AN13
AN14
AN19
AN2
AN21
AN25
AN28
AN3
AN31
AN36
AN39
AN4
AN41
AN5
AN6
AN7
AN8
AN9
AP10
AP11
AP12
AP13
AP14
AP15
AP18
AP20
AP22
AP24
AP26
AP28
AP3
AP30
AP32
AP34
AP35
AP37
AP42
AP53
AP54
AP55
AP6
AP9
AR10
AR11
AR12
AR13
AR14
AR15
AR16
AR19
AR21
AR23
AR25
AR27
AR29
AR3
AR42
AR43
AR44
AR45
AR46
AR47
AR48
AR49
AR50
AR51
AR52
AR53
AR6
AR9
AT10
AT11
AT12
AT13
AT14
AT15
AT17
AT18
AT22
AT24
AT26
AT28
AT3
AT30
AT34
AT36
AT38
AT41
AT43
AT44
AT45
AT46
AT47
AT48
AT49
AT50
AT51
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
U0600
SYM 17 OF 23
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AT52
AT53
AT6
AT9
AU10
AU11
AU12
AU13
AU14
AU15
AU16
AU21
AU23
AU25
AU27
AU29
AU3
AU31
AU33
AU37
AU39
AU41
AU44
AU45
AU46
AU47
AU48
AU49
AU50
AU53
AU6
AU7
AU8
AU9
AV10
AV12
AV13
AV14
AV15
AV17
AV18
AV19
AV21
AV22
AV24
AV26
AV28
AV3
AV35
AV38
AV41
AV44
AV45
AV46
AV47
AV48
AV49
AV50
AV53
AV6
AV9
AW10
AW12
AW14
AW15
AW16
AW25
AW27
AW29
AW3
AW30
AW31
AW32
AW34
AW36
AW40
AW41
AW42
AW43
AW44
AW45
AW46
AW47
AW48
AW49
AW50
AW51
AW52
AW53
AW6
AW9
AY10
AY11
AY12
AY14
AY17
AY22
AY24
AY3
AY33
AY35
AY37
AY38
AY39
AY40
AY41
AY42
AY44
AY45
AY46
AY47
AY48
AY49
AY50
AY53
AY6
AY9
B1
B11
B12
B13
B14
B15
B16
B17
B18
B19
B2
B20
B22
B24
B27
B28
B29
B32
B34
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B49
B5
B51
B54
B55
B7
BA1
BA18
BA19
BA2
BA20
BA21
BA25
BA27
V S
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
V S
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
V S
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
U0600
SYM 18 OF 23
VSS
VS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BA28
BA29
BA3
BA30
BA31
BA34
BA36
BA4
BA40
BA41
BA44
BA45
BA46
BA47
BA48
BA49
BA5
BA50
BA53
BA54
BA55
BA6
BA7
BA8
BA9
BB11
BB14
BB17
BB20
BB23
BB26
BB27
BB28
BB29
BB30
BB31
BB32
BB33
BB34
BB35
BB36
BB39
BB40
BB41
BB42
BB43
BB44
BB45
BB46
BB47
BB48
BB49
BB50
BB51
BB52
BB6
BB8
BC22
BC23
BC26
BC28
BC30
BC32
BC34
BC36
BC39
BC4
BC40
BC41
BC42
BC 4
BC46
BC48
BC50
BC51
BC52
BD1
BD2
BD23
BD24
BD25
BD26
BD28
BD30
BD32
BD34
BD36
BD37
BD38
BD39
BD40
BD41
BD42
BD44
BD46
BD48
BD50
BD51
BD52
BD53
BD54
BD55
BE1
BE11
BE14
BE17
BE2
BE20
BE22
BE25
BE27
BE29
BE3
BE31
BE33
BE35
BE37
BE41
BE43
BE45
BE47
BE49
BE5
BE51
BE53
BE54
BE55
BE8
BF2
BF22
BF23
BF25
BF27
BF29
BF3
BF31
BF33
BF35
BF37
BF41
BF43
BF45
BF47
BF49
BF51
BF53
BF54
C1
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C2
C20
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
U0600
TMLR68A0-B09 TMLR68A0-B09 TMLR68A0-B09 TMLR68A0-B09 TMLR68A0-B09
BGA BGA BGA BGA
SYM 19 OF 23
VS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C21
C23
C25
C26
C27
C28
C29
C30
C31
C33
C35
C36
C37
C38
C39
C4
C40
C41
C42
C43
C44
C45
C46
C47
C48
C50
C52
C54
C55
C6
C8
C9
D1
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D2
D20
D24
D26
D27
D28
D29
D3
D30
D32
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D5
D51
D53
D54
D55
D9
E1
E10
E11
E12
E13
E14
E15
E16
E17
PAGE TITLE
SOC: GND
BOM_COST_GROUP=SOC
Page 16
**OK2INTEGRATE**
w w w . t e k n i s i - i n d o n e s i a . c o m
SOC: GND (2)
E18
E19
E2
E20
E22
E23
E25
E27
E28
E29
E31
E33
E34
E36
E37
E38
E39
E4
E40
E41
E42
E43
E44
E45
E46
E47
E49
E5
E50
E52
E54
E55
E6
E7
E9
F1
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F2
F20
F21
F22
F24
F26
F27
F28
F29
F3
F30
F32
F34
F35
F36
F37
F38
F39
F40
F41
F42
F43
F44
F45
F46
F47
F48
F49
F5
F51
F53
F54
F55
F7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
U0600
BGA BGA BGA BGA
SYM 20 O 23
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
F8
F9
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G2
G20
G21
G22
G23
G25
G27
G28
G29
G31
G33
G34
G35
G36
G37
G38
G39
G4
G40
G41
G42
G43
G44
G45
G46
G47
G48
G49
G50
G52
G54
G6
G7
G8
G9
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H2
H20
H21
H22
H24
H26
H27
H28
H29
H3
H30
H32
H34
H35
H36
H37
H38
H39
H40
H41
H42
H43
H44
H45
H46
H47
H48
H49
H5
H51
H53
H54
H7
H8
H9
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J2
J20
J21
J22
J23
J25
J27
J28
J29
J31
J33
J34
J35
J36
J37
J38
J39
J4
J40
J41
J42
J43
J44
J45
J46
J47
J48
J49
J50
J52
J54
J55
J6
J7
J8
J9
K1
K10
K13
K16
K18
K19
K2
K20
K21
K22
K23
K25
K27
K28
K29
K31
K33
K34
K35
K36
K37
K38
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
U0600
SYM 21 OF 23
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SS
VSS
VSS
VSS
K3
K4
K40
K41
K42
K43
K44
K45
K46
K47
K48
K49
K50
K52
K54
K55
K6
K7
L1
L10
L13
L16
L18
L19
L2
L20
L21
L22
L24
L26
L27
L28
L29
L3
L30
L32
L34
L35
L36
L37
L38
L39
L40
L41
L42
L43
L44
L45
L46
L47
L48
L49
L5
L51
L53
L54
L55
L7
M1
M10
M13
M16
M17
M18
M19
M2
M20
M21
M22
M23
M25
M27
M28
M29
M31
M33
M34
M35
M36
M37
M38
M39
M4
M40
M41
M42
M43
M44
M45
M46
M47
M48
M49
M50
M52
M54
M55
M6
M7
M8
N1
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N2
N20
N21
N22
N23
N24
N26
N27
N28
N29
N3
N30
N32
N33
N34
N35
N36
N37
N38
N39
N40
N41
N42
N43
N44
N45
N46
N47
N48
N49
N5
N50
N51
N53
N54
N6
N7
N8
N9
P1
P10
P14
P15
P16
P17
P18
P19
P2
P20
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
U0600
SYM 22 OF 23
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
P21
P22
P25
P26
P27
P28
P29
P3
P30
P31
P34
P35
P36
P37
P38
P39
P4
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P52
P53
P7
R1
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R26
R27
R3
R30
R31
R32
R33
R34
R35
R36
R37
R38
R39
R4
R40
R41
R42
R43
R44
R45
R46
R47
R5
R6
R7
T1
T10
T11
T12
T13
T14
T15
T17
T19
T2
T21
T23
T27
T3
T31
T35
T37
T39
T4
T41
T42
T43
T44
T45
T46
T47
T48
T5
T51
T54
T6
T7
T8
T9
U1
U10
U11
U12
U13
U16
U18
U2
U22
U24
U26
U28
U3
U30
U32
U34
U36
U38
U4
U40
U41
U42
U43
U44
U45
U46
U47
U48
U5
U6
U7
U8
U9
V1
V10
V11
V12
V13
V14
V15
V2
V21
V23
V25
V27
V3
V31
V33
V35
V39
V4
V41
V42
V43
V44
V45
V46
V47
V5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
U0600
TMLR68A0-B09 TMLR68A0-B09 TMLR68A0-B09 TMLR68A0-B09
SYM 23 OF 23
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
V6
V7
V8
V9
W10
W11
W12
W13
W15
W16
W2
W21
W23
W25
W27
W32
W34
W41
W42
W43
W44
W45
W46
W47
W48
W5
W51
W54
W8
W9
Y10
Y11
Y12
Y13
Y14
Y16
Y19
Y22
Y24
Y28
Y30
Y35
Y37
Y39
Y40
Y41
Y42
Y43
Y44
Y45
Y46
Y47
Y51
Y8
Y9
B48
PAGE TITLE
SOC: GND-2
BOM_COST_GROUP=SOC
Page 17
**OK2INTEGRATE**
w w w . t e k n i s i - i n d o n e s i a . c o m
SPI NOR (1.8V 64 M-BIT)
PP1V8_AWAKE
102
102 17
R1974
6
SPI_SOCROM_MOSI_R
IN
1/20W
R1975
6
SPI_SOCROM_CLK_R
IN
1
R1972
47K
5%
1/20W
MF MF
201
2
1
R1973
47K
5%
1/20W
201
2
1/20W
102 17
PP1V25_AWAKE_IO
33
2 1
5%
MF
201
33
5%
MF
201
2 1
SPI_SOCROM_MOSI
SPI_SOCROM_CLK
PP1V8_AWAKE
1
C1974
0.1UF
10%
6.3V
2
X6S
0201
U1974
74AVC2T45
1A
2A
5
DIR
VSSOP
GND
PP1V8_AWAKE
VCCB VCCA
7 2
1B
2B
SPI_SOCROM_1V8_MOSI_R
6 3
SPI_SOCROM_1V8_CLK_R
PP1V25_AWAKE_IO
102 17
1
C1975 2
0 1UF
10
6 3V
2
X6S
0201
102 17
R1976
33
5%
1/20W
MF
201
R1977
33
5%
1/20W
MF
201
2 1
SPI_SOCROM_1V8_MOSI
2 1
SPI_SOCROM_1V8_CLK
17
17
17
17
1
C1970
0.1UF
10%
6.3V
X6S
0201
R1971
10K
1/20W
201
SPI_SOCROM_1V8_CLK
SPI_SOCROM_1V8_CS_L
5%
MF
1
2
R1970
100K
5%
1/20W
MF
201
2
SPI_SOCROM_WP_L
VCC
U1970
W25Q64JWUUIQ
64MB-1.8V
6
CLK
1
CS*
3
WP*/IO2
7
HOLD*/RESET*/(IO3)
USON
335S00494
PACK_OPTION=SMALL_NOR
5
DI(IO0)
DO(IO1)
EPAD GND
SPI_SOCROM_1V8_MOSI
2
SPI_SOCROM_1V8_MISO_R
17
17
SPI_SOCROM_1V8_MISO_R
17
1
R1980
100K
5%
1/20W
MF
201
2
R1983
33
5%
1/20W
MF
201
1
C1983
0.1UF
10%
6.3V
2
X6S
0201
VCCA VCCB
5
DIR
2 1
SPI_SOCROM_1V8_MISO SPI_SOCROM_MISO SPI_SOCROM_MISO_R
A
GND
U1983
SN74AXC1T45
SOT- X3
4 3
B
1
C1984
0.1UF
10%
6.3V
2
X6S
0201
R1984
33
5%
1/20W
MF
201
2 1
OUT
6
102 17
6
IN
SPI_SOCROM_CS_L SPI_SOCROM_1V8_CS_L
PP1V25_AWAKE_IO
1
C1992
0.1UF
10%
6.3V
2
X6S
0201
1
R1992
47K
5%
1/20W
MF
201
2
VCCA VCCB
5
DIR
A
PP1V8_AWAKE
U1992
SN74AXC1T45
SOT-5X3
4 3
B
1
C1993
0.1UF
10%
6.3V
2
X6S
0201
102 17
SYNC_MASTER=REF_SOC_H13G SYNC_DATE=01/27/2020
17
PAGE TITLE
SPI NOR
GND
BOM_COST_GROUP=SOC
2
1
Page 18
TGA SPMI SE SOURCE TERMINATIONS
w w w . t e k n i s i - i n d o n e s i a . c o m
R2103
20
5%
MF
201
2 1
SPMI_SE_CLK
PLACE_NEAR=U0600.BF20:10MM
OUT
20
IN
SPMI_SE_CLK_R
1/20W
R2102
20
5%
MF
2 1
201
BI
PLACE_NEAR=U0600.BF21:10MM
9 20
BI
SPMI_SE_DATA_R SPMI_SE_DATA
1/20W
TGA SPMI MPMU SOURCE TERMINATIONS
TGA SPI SENSOR SOURCE TERMINATIONS
SENSOR_IMU
R2104
20
2 1
9
IN
SPI_AOP_GYRO_R1_MOSI_R
5%
1/20W
MF
201
SPI_AOP_SENSOR_MOSI
PLACE_NEAR=U0600.BF14:10MM
SENSOR_IMU
R2105
20
2 1
9
IN
SPI_AOP_GYRO_R1_CLK_R
%
1/20W
MF
201
SPI_AOP_SENSOR_CLK
PLACE_NEAR=U0600.BF17:10MM
TGA SPI IPD SOURCE TERMINATIONS
OUT
OUT
TGA 1V2 TDM SOURCE TERMINATIONS
R2110
20
5%
MF
201
20
5%
MF
201
2 1
2 1
TDM_SPKRAMP_L_BCLK
MAKE_BASE=TRUE
TDM_SPKRAMP_L_BCLK
TDM_SPKRAMP_L_R2D
MAKE_BASE=TRUE
TDM_SPKRAMP_L_R2D
75
75
51 9
51
6
IN
6
IN
TDM_SPKRAMP_L_BCLK_R
1/20W
PLACE_NEAR=U0600.AK4:10MM
R2111
TDM_SPKRAMP_L_R2D_R
1/20W
PLACE_NEAR=U0600.AJ5:10MM
R2107
20
5%
MF
201
2 1
PLACE_NEAR=U0600.BB15:10MM
OUT
9 33
IN
SPMI_NUB_MPMU_CLK_R SPMI_NUB_MPMU_CLK
1/20W
R2106
20
5%
MF
2 1
201
BI
PLACE_NEAR=U0600.BC14:10MM
9 33
BI
SPMI_NUB_MPMU_DATA_R SPMI_NUB_MPMU_DATA
1/20W
TGA SPMI SPMU SOURCE TERMINATIONS
R2109
20
5%
MF
201
2 1
PLACE_NEAR=U0600.BA12:10MM
OUT
9 29
IN
SPMI_NUB_SPMU_CLK_R SPMI_NUB_SPMU_CLK
1/20W
R2108
20
5%
MF
2 1
201
9
BI
SPMI_NUB_SPMU_DATA_R
1/20W
SPMI_NUB_SPMU_DATA
PLACE_NEAR=U0600.BC11:10MM
BI
29
TGA MISC DEBUG TEST-POINTS
R2100
20
5%
201
2 1
PLACE_NEAR=U0600 W1:10MM
F
OUT
6 84
IN
SPI_IPD_MOSI_R SPI_IPD_MOSI
1/20W
R2101
20
5%
MF
201
2 1
SPI_IPD_CLK
PLACE_NEAR=U0600.AB1:10MM
OUT
84
6
IN
SPI_IPD_CLK_R
1/20W
TGA SPI DFR SOURCE TERMINATIONS
R2113
20
5%
MF
201
20
5%
MF
201
2 1
2 1
SPI_DFR_MOSI
PLACE_NEAR=U0600.AK2:10MM
SPI_DFR_CLK
PLACE_NEAR=U0600.AK1:10MM
OUT
OUT
88
88
4 6
IN
SPI_DFR_MOSI_R
1/20W
R2114
4
IN
SPI_DFR_CLK_R
1 20
R2112
20
5%
MF
201
2 1
6
IN
6
OUT
TDM_SPKRAMP_L_FSYNC_R
1/20W
PLACE_NEAR=U0600.AJ4:10MM
TDM_SPKRAMP_L_D2R
MA E_BASE=TRUE
TDM_SPKRAMP_L_FSYNC
MAKE_BASE=TRUE
TDM_SPKRAMP_L_FSYNC
TDM_SPKRAMP L_D2R
75
75
R2120
20
5%
MF
201
2 1
TDM_SPKRAMP_R_BCLK
MAKE_BASE=TRUE
TDM_SPKRAMP_R_BCLK
75
6
IN
TDM_SPKRAMP_R_BCLK_R
1/20W
PLACE_NEAR=U0600.AG3:10MM
R2121
20
5%
MF
201
2 1
TDM_SPKRAMP_R_R2D
MAKE_BASE=TRUE
TDM_SPKRAMP_R_R2D
75
6
IN
TDM_SPKRAMP_R_R2D_R
1/20W
PLACE_NEAR=U0600.AG4:10MM
TP2126
9 33
BI
9 106
BI
9
BI
9 89
BI
PMU_CLK32K_SOC
TP_SOC_DOCK_ATTENTION
TP_AON_SLEEP1_RESET_L
SMC_FIXTURE_MODE_L
1
TP-P5
TP2127
1
TP-P5
TP2128
1
TP-P5
TP2129
1
TP-P5
A
A
A
A
TGA JTAG TEST-POINTS
TP2110
4 9
BI
9 56 89
BI
9
BI
9
BI
9 56 89
BI
9
BI
SOC_JTAG_SEL
SWD_SOC_SWCLK
TP_JTAG_SOC_TDI
TP_JTAG_SOC_TDO
SWD_SOC_SWDIO
TP_JTAG_SOC_TRST_L
1
TP-P5
TP2111
1
TP-P5
TP2112
1
TP-P5
TP2113
1
TP-P5
TP2114
1
TP-P5
TP2115
1
TP-P5
A
A
A
A
A
A
TGA DEBUG TEST-POINTS
TP2120
5
BI
TP_TST_CLKOUT
1
TP-P5
A
PLACE_SIDE=BOTTOM
PLACE_SIDE=TOP
PLACE_SIDE=BOTTOM
PLACE_SIDE=BOTTOM
PLACE_SIDE=TOP
TGA SPI TOUCHID SOURCE TERMINATIONS
R2115
20
5%
MF
01
2 1
SPI_TOUCHID_MOSI
PLACE_NEAR=U0600.AF54:10MM
6
IN
SPI_TOUCHID_MOSI_R
1/20
R2116
20
5%
MF
201
2 1
SPI_TOUCHID_CLK
PLACE_NEAR=U0600.AF55:10MM
6
IN
SPI_TOUCHID_CLK_R
1/20W
EUSB SERIES RESISTORS AND TEST POINTS
R2150
0
5
BI
PP2190
PLACE_NEAR=U0600.BB54:10MM
5
BI
EUSB_ATC0_P
P4MM
PP
SM
EUSB_ATC0_N
1
PP2191
P4MM
PLACE_NEAR=U0600.BB55:10MM
5
BI
PP
SM
EUSB_ATC1_P
PP2192
P4MM
PLACE_NEAR=U0600.BC54:10MM
5
BI
PP
SM
EUSB_ATC1_N
PP2193
P4MM
PLACE_NEAR=U0600.BC55:10MM
PP
SM
1/20W
0201
R2151
1/20W
0201
R2152
1/20W
0201
R2153
1/20W
0201
2 1
5%
MF
0
2 1
5%
MF
0
2 1
5%
PP2196
MF
0
2 1
5%
PP2197
MF
(TP ON FCT PAGE)
(TP ON FCT PAGE)
P4MM
PLACE_NEAR=UF750.A1:10MM
P4MM
PLACE_NEAR=UF750.B1:10MM
PP
S
PP
SM
EUSB_ATC0_R_P
MAKE_BASE=TRUE
EUSB_ATC0_R_P
EUSB_ATC0_R_N
MAKE_BASE=TRUE
EUSB_ATC0_R_N
EUSB_ATC1_R_P
MAKE_BASE=TRUE
EUSB_ATC1_R_P
EUSB_ATC1_R_N
MAKE_BASE=TRUE
EUSB_ATC1_R_N
OUT
OUT
BI
BI
80 9
80 89
89
60
89
60
60
60
R2122
20
5%
MF
201
2 1
TDM_SPKRAMP_R_FSYNC
MAKE_BASE=TRUE
TDM_SPKRAMP_R_FSYNC
TDM_SPKRAMP_R_D2R
75
75
6
IN
6
OUT
TDM_SPKRAMP_R_FSYNC_R
1/20W
LA E_NEAR=U0600.AF2:10MM
TDM_SPKRAMP_R_D2R
MAKE_BASE=TRUE
R2130
20
5%
MF
201
2 1
TDM_CODEC_BCLK
OUT
76
6
IN
TDM_CODEC_BCLK_R
1/20W
PLACE_NEAR=U0600.AK5:10MM
R2131
20
5%
MF
201
2 1
TDM_CODEC_R2D
OUT
76
6
IN
TDM_CODEC_R2D_R
1/20W
PLACE_NEAR=U0600.AJ7:10MM
R2132
20
5%
MF
201
2 1
TDM_CODEC_FSYNC
OUT
76
6
IN
TDM_CODEC_FSYNC_R
1/20W
PLACE_NEAR=U0600.AM4:10MM
TP2121
1
TP-P5
TP2122
5 106
BI
6 56 89
BI
6 56 89
BI
TP_SOC_AMUX_OUT
UART_DEBUGPRT_D2R
UART_DEBUGPRT_R2D
1
TP-P5
TP2123
1
TP-P5
TP2124
1
TP-P5
TP2125
1
TP-P5
PLACE_SIDE=BOTTOM
A
A
PLACE_SIDE=BOTTOM
A
PLACE_SIDE=TOP
A
PLACE_SIDE=BOTTOM
A
PLACE_SIDE=BOTTOM
9 60
BI
PP21A0
PLACE_NEAR=U0600.BF24:10MM
9 60
BI
PLACE_NEAR=U0600.BE24:10MM
EUSB_DBG_P
P4MM
PP
SM
EUSB_DBG_N
P4MM
SM
PP21A
P4MM
PLACE_NEAR UF 00.A1:10MM
PP
SM
PP21A3 PP21A2
P4MM
PLACE_NEAR=UF700.B1:10MM
PP PP
SM
SYNC_MASTER=AITKEN_T668_MLB SYNC_DATE=09/18/2019
PAGE TITLE
PROJECT SUPPORT (1/2)
BOM_COST_GROUP=SOC
2
1
Page 19
5 56 89 94
w w w . t e k n i s i - i n d o n e s i a . c o m
IN
SOC_DFU_STATUS
NOSTUFF
1
R2200
47K
5%
1/20W
MF
201
2
NOSTUFF
R2205
0
33
MPMU_BUTTONO1
1
5%
1/20W
MF
0201
OPTION FOR SW TO READ POWER BUTTON, NOT USED
SOC_REQUEST_DFU1
5
OUT N
7
IN
7
IN
7
IN
7
IN
LPDPRX0_RCAL_POS
LPDPRX0_RCAL_NEG
LPDPRX1_RCAL_POS
LPDPRX1_RCAL_NEG
NOSTUFF
1
R2201
47K
5%
1/20W
MF
201
2
NOSTUFF
1
R2202
47K
5%
1/20W
MF
01
2
NOSTUFF
1
R2203
47K
5%
1/20W
MF
201
2
NOSTUFF
1
R2204
47K
5%
1/20W
MF
201
2
SOC_THROTTLE2
R2299
0
IN OUT
1/ 0W
0201
2 1
5%
MF
<RDAR://59954844>
SOC_THROTTLE_TRIGGER2 RSVD_GPU_TRIGGER1_L
6 33 34
SYNC_MASTER=AITKEN_T668_MLB SYNC_DATE=11/11/2019
PAGE TITLE
PROJECT SUPPORT (2/2)
BOM_COST_GROUP=SOC
Page 20
Timing Requirements:
w w w . t e k n i s i - i n d o n e s i a . c o m
- VBAT supply ramp time: 20ms
Ceres - Secure Element
*** OK2INTEGRATE ***
Per TGA Power Block Diagram v0.3
U5000.B5:3mm
C5008
0.22UF
6.3V
X5R
0201
PP1V8_S2
101
U5000.E8:3mm
1
2
C5009
0.22UF
20% 20%
X5R
0201
1
2
U5000.F9:3mm
C5014
1.0UF
0201-1
U5000.E9:3mm
C5010
0.22UF
20%
6.3V 6.3V
X5R
0201
20%
6.3V
X5R
PP1V25_S2
U5000.F8:3mm
20%
6.3V
X5R
0201
0
1
2
2 1
VUP_SE VDDBOOST_SE
5% 0201
1
C5002
0.22UF
2
R5030
MF 1/20W
U5000.E7:3mm
C5003
0.22UF
20%
6.3V
X5R
0201
1
2
IccMax SE only: 10mA IccMax SE only: 125mA
102
Based on SPMI only use case
VDDPLL_SE
VDDNV_SE
VDDC_SE
20%
10V
X5R
0201
1
2
C5051
2.2UF
1
2
PP3V8_AON 101 20
IccMax: 100mA
As per NXP preliminary stimate, final pending
NC
D4
NFC_CLK_32K
H6
NC
SE_CTLR_FW_DWLD
20
TP_SE_GPIO0
NC
NC
NC
R5042
MF 1/20W 201
R5041
1/20W MF 201
18
18
BI
SPMI_SE_CLK
IN
SPMI_SE_DATA
1
R5050
1M
5% 5%
1/20W
MF
201
2
5%
5%
47K
47K
1
R5051
1M
1/20W
MF
201
2
2 1
UART_SE_R2D_RTS_L
NC_UART_SE_D2R_CTS_L
NO_TEST
2 1
UART_SE_R2D
NC_UART_SE_D2R
2
SE_DEV_WAKE
NO TEST
NC
NC
NC
NC
NC
NC
NFC_CLK_REQ
A6
NFC_CLK_XTAL1
G4
NFC_DWL_REQ
F6
NFC_GPIO0
J7
NFC_GPIO1
J5
NFC_GPIO2_AO
NFC_GPIO3_AO
E6
NFC_HSU_CTS
F5
NFC_HSU_RTS
G5
NFC_HSU_RX
E5
NFC_HSU_TX
E4
NFC_I2C_SCL
F4
NFC_I2C_SDA
J6
NFC_IRQ
NFC_SIM_SWIO1
J8
NFC_SIM_SWIO2
H7
NFC_SPMI_SCLK
G7
NFC_SPMI_SDATA
H5
NFC_WKUP_REQ
B6
NFC_XTAL2
G6
TM
A3
RXP
A4
RXN
SN210VUK/B101V7
50K internal pull-down
U5000
WLCSP
OMIT_TABLE
NC
NC NC NC
SE_GPIO0
SE_GPIO1
SE_I2C_SCL
SE_I2C_SDA
SE_ISO_CLK
SE_ISO_IO
SE_ISO_RST
SE_SPI_CLK
SE_SPI_CS
SE_SPI_MISO
SE_SPI_MOSI
TXVCASCP
TXVCASCN
RXVCM
TXVCM
TX1
TX2
VCASCHI
VCASCLO
BOOST_LX
BOOST_LX
VHV
VTUNE
VEN
VREF
H3
NC
F3
NC
G1
H1
F2
NC
F1
NC
G3
NC
G2
NC
J2
NC
H2
NC
E2
NC
D2
NC
D1
NC
B3
NC
C2
NC
A1
NC
C1
NC
D7
NC
C7
NC
B8
B9
B7
VHV_SE
D3
NC
D5
SE_PWR_EN
C5
VREF_SE
Pulls to be added in system, can be NC'd if unused
NC_I2C_SE_SCL
NC_I2C_SE_SDA
PP3V8_AON
IN
33
IN
BI
107
107
101 20
1
C5004
0.1UF
10%
6.3V
2
CERM-X5R
0201
1
C5017
0.22UF
20%
6.3V
2
X5R
0201
SYNC_DATE=02/26/2020 SYNC_MASTER=REF_SE_CERES
PAGE TITLE
Secure Element
R5000
R5006
47K
47K
2 1
5% MF
2 1
201 1/20W
MF 1/20W 5% 201
SE_CTLR_FW_DWLD
SE_DEV_WAKE
20
20
<rdar://problem/52067756> [SN200V] Wired Mode SE Only Reference Design Material
<rdar://problem/45108950> Mac - Venus Reference guide and De-coupling requirements
BOM_COST_GROUP=SECURE ELEMENT
Page 21
BATTERY (BMU) LOGIC CONNECTOR
w w w . t e k n i s i - i n d o n e s i a . c o m
BATTERY (BMU) FLEX SOLDER PADS
BMU POWER FLEX IS SOLDERED TO MLB.
518S00014
CRITICAL
J5151
FF18-10A-R11AD-B-3H
F-RT-SM-A
TP5100
A
PLACE_SIDE=TOP
TP5101
A
PLACE_SIDE=TOP
11
1
2
3
4
5
6
7
8
9
10
12
1
TP P5
1
TP-P5
NC
NC
NC
NC
I2C_SMC_PWR_3V3_SCL
I2C_SMC_PWR_3V3_SDA
89
SYS_DETECT_L
NOSTUFF
1
R5155
10K
5%
1/16W
MF-LF
402
2
998-03828
CRITICAL
J5150
TP5103
A
PLACE_SIDE=BOTTOM
CRITICAL
U5150
RCLAMP3552T
SLP1006N3T
PLACE_SIDE=BOTTOM
376S00282
3
D
Q5155
NTNS4CS69N
XDFN
SYM_VER_2
1
2
G S
89
SYS_DETECT
PLACE_SIDE=TOP
1
TP-P5
TP5104
A
1
TP-P5
PLACE_SIDE=BOTTOM
43
IN
43
BI
PP3V8_AON
1
R5156
10K
5%
1/16W
MF-LF
402
2
TP5102
1
TP-P5
PLACE_SIDE=TOP
A
101
SYS_DET_BTN SYS_DET_BTN
S5191 S5190
STO-060A16AE
SM
705S00069
STO-060A16AE
SM
705S00069
PWR-MLB-X520
HB-SM
11 10
12
1
2
3
5 4
9
8
TP5105
7
PLACE_SIDE=BOTTOM
6
C5150
0.1UF
10%
25V
X5R
402
1
2
C5160
603-1
1
1UF 3PF
10%
25V
2
X5R
A
C5161
+/-0.1PF
TP- 5
25V
C0G
201
1
PPVBAT_AON
1
2
C5162
3PF
+/-0.1PF
25V
C0G
0201
1
2
101
CRITICAL PART NUMBER QTY BOM OPTION REFERENCE DES DESCRIPTION
J5150 632-00731 1 PCBA,FLEX,BMU PWR,X502
CRITICAL
SYNC_MASTER=AITKEN_T668_MLB SYNC_DATE=09/18/2019
PAGE TITLE
BATTERY CONNECTORS
BOM_COST_GROUP=BATTERY
Page 22
*** OK2INTEGRATE ***
w w w . t e k n i s i - i n d o n e s i a . c o m
PPDCIN_AON_CHGR_R
89 98
MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1800
VOLTAGE=20V
CRITICAL
1
C5201
6.8UF
20%
35V-0.09OHM
2
POLY-TANT
CASE-B1-2-SM
CAPMAT=POLY-TANT
CRITICAL
1
C5202
6.8UF
20%
35V-0.09OHM
2
POLY-TANT
CASE-B1-2-SM
CAPMAT=POLY-TANT
CRITICAL
1
C5203
6.8UF
20%
35V-0.09OHM
2
POLY-TANT
CASE-B1-2-SM
CAPMAT=POLY-TANT
CRITICAL
1
C520A
2.2UF
20%
35V
2
X5R-CERM
0402
CRITICAL
1
C520B
2.2UF
20%
35V
2
X5R-CERM
0402
CRITICAL
1
C520C
2.2UF
20%
35V
2
X5R-CERM
0402
CRITICAL
1
C520D
2.2UF
20%
35V
2
X5R-CERM
0402
CKPLUS_WAIVE=CAPDERATE
CRITICAL
1
C5250
68UF
20%
16V
2
POLY-TANT
CASE-D2E-SM
CAPMAT=POLY-TANT
PACK_OPTION=CHGR_60W
CKPLUS_WAIVE CAPDERATE
CRITICAL
1
C5251
68UF
20%
16V
2
POLY-TANT
CASE-D2E-SM
CAPMAT=POLY-TANT
PACK_O TION=CHGR_60W
CKPLUS_WAIVE=CAPDERATE
CRITICAL
1
C5252
68UF
20%
16V
2
POLY-TANT
CASE-D2E-SM
CAPMAT=POLY-TANT
PACK_IGNORE=TRUE
PACK_OPTION CHGR_75W
CKPLUS_WAIVE=CAPDERATE
CRITICAL
1
C5253
68UF
20%
16V
2
POLY-TANT
CASE-D2E-SM
CAPMAT=POLY-TANT
PACK_IGNORE=TRUE
PACK_OPTION=CHGR_75W
FROM USB-C SOURCE
101 22
PACK_OPTION=CHGR_TP_TOP
PACK_OPTION=CHGR_TP_TOP
PACK_OPTION=CH R_TP_TOP
PACK_OPTION=CHGR_TP_TOP
PACK_OPTION=CHGR_TP_TOP
PACK_OPTION=CHGR_T _ O
PACK_OPTION=CHGR_TP
PACK_OPTION=CHGR_TP
101 22
PPDCIN_USBC_AON
PP5201
P2MM
SM
1
CHGR_GATE_Q1
22
PP
PLACE_SIDE=TOP
PP5202
P2MM
SM
1
CHGR_GATE_Q2
22
PP
PLACE_SIDE=TOP
PP5203
P2MM
SM
1
CHGR_GATE_Q3
22
PP
PLACE_SIDE=TOP
PP5204
P2MM
SM
1
CHGR_GATE_Q4
22
PP
PLACE_SIDE=TOP
PP5205
P2MM
SM
1
CHGR_PHASE1
22
PP
PLACE_SIDE=TOP
PP5206
P2MM
SM
1
CHGR_PHASE2
22
PP
PLACE_SIDE=TOP
PP5207
P2MM
SM
1
PP
PP5208
P2MM
SM
PP
CHGR_EN_MVR
1
CHGR_INT_1V8_L
PPDCIN_USBC_AON
101
NOSTUFF
C5216
0.01UF
PP1V8_S2
CRITICAL
1
C520
6.8UF
20%
35V-0.09OHM
2
POLY-TANT
CASE-B1-2-SM
CAPMAT=POLY-TANT
PP5211
P2MM
SM
1
PP
PLACE_SIDE=BOTTOM
PACK_OP ION=CHGR_TP_BOT
PP5212
P2MM
M
1
PP
PLACE_SIDE=BOTTOM
PACK_OPTION=CHGR_TP_BOT
PP5213
P2MM
SM
1
PP
PLACE_SIDE=BOTTOM
PACK_ PTION=CHGR_TP_BOT
PP5214
P2MM
M
1
P
PLACE_SIDE=BOTTOM
PACK_OPTION=CHGR_TP_BOT
PP5215
P2MM
SM
1
PP
PLACE_SIDE=BOTTOM
PACK_OPTION=CHGR_TP_BOT
PP5216
P2MM
SM
1
PP
PLACE SIDE=BOTTOM
PACK_OPT ON C GR_TP_BOT
22 23
22 89 97
22 23
1
R5215
750K
1%
/20W
MF
1
1
2
PPVBAT_AON_CHGR_REG
CHGR_AUX_DET
10%
25V
X5R-CERM
020
C5280
1.0UF
1
2
20%
6.3V
X5R
0201-1
1
R5216
255K
1%
1/20W
MF
201
2
1
2
CRITICAL
C5205
6.8UF
20%
35V-0.09OHM
POLY-TANT
CASE-B1-2-SM
CAPMAT=POLY-TANT
PACK_OPTION=CHGR_60W
48 48
PLACE_NEAR=U5200.D5:2M
CRITICAL
1
C5206
6.8UF
20%
35V-0.09OHM
2
POLY-TANT
CASE-B1-2-SM
CAPMAT=POLY-TANT
PACK_OPTION=CHGR_60W
CHGR_CSI_FILT_P
CRITICAL
20%
35V
0402
1
2
C5278
2.2UF
X5R-C RM
CRITICAL
1
C5205
6.8UF
20%
35V-0.09OHM
2
POLY-TANT
CASE-B1-2-SM
CAPMAT=POLY-TANT
PACK_IGNORE=TRUE
PACK_OPTION=CHGR_75W
CRITICAL
1
C5206
6.8UF
20%
35V-0.09OHM
2
POLY-TANT
CASE-B1-2-SM
CAPMAT=POLY-TANT
PACK_IGNORE=TRUE
PACK_OPTION=CHGR_75W
CRITICAL
R5220
0.01
0 5%
0. W
MF
0306
NO_XNET_CONNECTION=1
(AMON)
2-CELL: 0.02 OHM
3-CELL: 0.01 OHM
107S00053
2 1
4 3
CHGR_CSI_P CHGR_CSI_N
PLACE_NEAR=U5200.C5:2MM
R5221
1.00
1%
1/20W
MF-LF
0201
1
2
1
R5222
1.00
1%
1/20W
MF-LF
0201
2
CHGR_CSI_FILT_N
CRITICAL
C5221
0.047UF
10%
50V
CER-X7R
0402
1
2
1
C5222
0.047UF
10%
50V
2
CER-X7R
0402
CRIT CAL
C5220
0.47UF
2 1
20%
4V
CERM-X5R-1
201
NO_XNET_CONNECTION=1
43
BI
43
IN
34
IN
NOSTUFF
CRITICAL
C5270
0.12UF
10%
10V
X5R
0402
1
2
CRITICAL
C5271
0.12UF
CRITICAL
1
C5207
6.8UF
20%
35V-0.09OHM
2
POLY-TANT
CASE-B1-2-SM
CAPMAT=POLY-TANT
PACK_IGNORE=TRUE
PACK_OPTION=CHGR_75W
I2C_SMC_PWR_1V8_SDA
I2C_SMC_PWR_1V8_SCL
CHGR_RST_IN
CHGR_COMP
H:3-C LL
L:2 CELL
1
10%
10V
2
X5R
0402
CHGR_GATE_Q1
22
SWITCH_NODE=TRUE
VOLTAGE=5V
PPCHGR_VDDA
23
CRITICAL
1
C5275
2.2UF
20%
25V
2
X5R-CERM
0402-1
B5
P_IN
C5
CSIN
D5
CSIP
A5
PBUS_PWR
D3
AUX_DET
F5
VDDIO1P8
G5
SDA
H5
SCL
G2
SMC_RST_IN
G3
HPWR_EN*
E5
COMP
G4
CELL
B2
NC0
C2
NC1
E4
CRITICAL
L5230
2.7UH-20%-12.5A-0.0196OHM
CHGR_PHASE1
22 22
DIDT=TRUE
SWITCH_NODE=TRUE SWITCH_NODE=TRUE
CRITICAL
ALLOW_APPLE_PREFIX=Q
IHLP4040BD-PIMA102D-COMBO
152S00198
2 1
ALLOW_APPLE_PREF X=Q
CHGR_PHASE2
CRITICAL
DIDT=TRUE
Q5230
DIDT=TRUE
CHGR_GATE_Q2
22
DIDT=TRUE
GATE_NODE=TRUE
CHGR_LX1
DIDT=TRUE
SWITCH_NODE=TRUE
CRITICAL
1
C5230
0.1UF
10%
25V
2
X7R-CERM-1
0402
2
XW5230
1
CHGR_GATE_Q3
GATE_NODE=TRUE
2
XW5240
SM SM
1
SWITCH_NODE=TRUE
DIDT=TRUE
CHGR_LX2
DIDT=TRUE
CRITICAL
C5240
0.1UF
X7R-CERM-1
22
10%
25V
0402
CHGR_BOOT1_RC CHGR_BOOT2_RC
DIDT=TRUE
SWITCH_NODE=TRUE
1
R5230
0
5%
1/16W
MF-LF
402
2
CHGR_BOOT1
DIDT=TRUE
SWITCH_NODE=TRUE
SWITCH_NODE=TRUE
SWITCH_NODE=TRUE
DIDT=TRUE
R5240
0
5%
1/16W
MF-LF
402
CHGR_BOOT2
DIDT=TRUE
1
2
1
2
CHGR_GATE_Q4
DIDT=TRUE
SWITCH_NODE=TRUE
R5275
4.7
5%
1/20W
MF
201
2 1
VOLTAGE=5V
PPCHGR_VDDP
CRITICAL
C5277
10UF
0603-1
20%
10V
X5R
PLACE_NEAR=Q5240.3:2MM
1
2
XW5260
SM
2 1
PLACE_NEAR=U5200. 4:2MM
48 48
CHGR_CSO_P CHGR_CSO_N
R5261
CHGR_CSO_FILT_P
CRITICAL
C5261
U5200
ISL9240 I
WCSP
CRITICAL
SCH SYMBOL
353S01525
(5V)
(OD)
GATE_Q1
BOOT1
LX1
GATE_Q2
GATE_Q3
LX2
BOOT2
GATE_Q4
PBUS
CSOP
CSON
BGATE
VBAT
EN_VR1
SMC_RST*
IRQ*
CBC_ON
EN_MVR
AUX_OK
AMON
BMON NC2
H1
F1
G1
E1
D1
B1
C1
A1
A3
A4
B4
B3
C3
F2
H4
H3
H2
F4
F3
D4
C4
CHGR_PBUS_SNS
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
CHGR_BGATE
CHGR_VBAT
NC_CHGR_EN_VR1
TP_CHGR_SMC_RST_L
CHGR_INT_1V8_L
TP_CHGR_CBC_ON
CHGR_EN_MVR
CHGR_AUX_OK
CHGR_AMON
CHGR_BMON
0.047UF
1 %
50
CER-X7R
0402
107
OUT
OUT
OUT
O T
OUT
Q5240
22
NO_XNET_CONNECTION=1
CRITICAL
R5260
0.005
1%
1W
MF
0612-8
1 2
3 4
1
1.00 1.00
1%
1/20W
MF-LF
2
0201
(BMON)
2-CELL: 0.010 OHM
3-CELL: 0.005 OHM
107S00087
PLACE_NEAR=U5200.B4:2MM
1
R5262
1%
1/20W
MF-LF
0201
2
CHGR_CSO_FILT_N
1
2
CRITICAL
C5260
0.47UF
2 1
20% 4V
CERM-X5R-1
201
NO_XNET_CONNECTION=1
22 23
22 23
23
44 48
4 48
CRITICAL
1
C5262
0.047UF
10%
50
2
CER-X7R
0402
PPVBAT_AON_CHGR_REG
22 89 97
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=13.05V
PPVBAT_AON_CHGR_R
MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1500
VOLTAGE=13.05V
CRITICAL
Q5265
SI7655DN-COMBO
PWRPK-1212-8
SYM-VER-2
3
S
2
1
G
4
C5264
1000PF
2 1
10%
25V
X7R
0201
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
NTNS4CS69N
1
R5263
1K
5%
1/20W
MF
201
2
CRITICAL
1
C5254
33UF
20%
16V
2
TANT
CASED12-SM
CAPMAT=POLY-TANT
PACK_IGNORE=TRUE
PACK_OPTION=CHGR_40W
CRITICAL
1
C5255
33UF
20%
16V
2
TANT
CASED12-SM
CAPMAT=POLY-TANT
PACK_IGNORE=TRUE
PACK_OPTION=CHGR_40W
CRITICAL
12A-32V-0.0045OHM
1
2
5
D
1
C5263
4700PF
10%
25V
2
CER X5R
0201
CRITICAL
Q5270
XDFN
SYM_VER_1
CRITICAL
C5265
2.2UF
20%
25V
X5R
0402-1
3
D
S
2
G
CRITICAL
1
C5266
2.2UF
20%
25
2
X5R
0402
1
C5269
0.1UF
10%
25V
2
X5R
0201
<rdar://37259372&39763505>
1
SAVE_BAT_S SAVE_BAT_G
CRITICAL
R5270
24K
5%
/2 W
MF
201
1
2
PAGE TITLE
D5270
DFN0201
ALLOW APPLE_PREFIX=D
GDZ5V6LP3-55
PBUS SUPPLY & BATTERY CHARGER
CRITICAL
1
C5256
2.2UF
20%
25V
2
X5R
0402-1
F5200
1206
CRITICAL
1
C5267
0.1UF
10%
25V
2
X5R
0201
CRITICAL
1
C5257
2.2UF
20%
25V
2
X5R
0402-1
TO SYSTEM
2 1
1
2
PPBUS_AON
CRITICAL
C5268
0.01UF
10%
25V
X5R-CERM
0201
TO/FROM BATTERY
PPVBAT_AON
MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1500
VOLTAGE=13.05V
PPDCIN_USBC_AON
1
R5271
200K
1%
1/20W
MF
201
2
1
C5258
1000PF
10%
25V
2
X7R
0201
101
101
101 22
SYNC_DATE=02/25/2020 SYNC_MASTER=REF_CHARGER_SUONA
BOM_COST_GROUP=BATTERY
Page 23
*** OK2INTEGRATE ***
w w w . t e k n i s i - i n d o n e s i a . c o m
CHGR I2C Level Translation
SMBUS_CHGR_1V8_[SCL/SDA]: Level translation circuit to be placed in project specific I2C page.
CHGR_INT_L Level Translation
Stuff R5320 in case, glitch during power sequencing is a concern.
101 22
PP1V8_S2
PP1V25_S2
NOSTUFF
1
R5320
47K
5%
1/20W
MF
201
2
U5320
SN74AUP1G17
GND
SON
Y
4
CHGR_INT_L
CHGR_INT_1V8_L
VCC
2
A
NC
NC
CHGR_AUX_OK Pull Up
Pull up to MPMU LDO9, or rely on MPMU internal pull up.
OK, to compl te y remove pull up , but co sult PMU architecture and check OTP before that.
PP1V8_AON
104
NOSTUFF
1
R5330
47K
5%
1/20W
MF
201
2
102
PLACE_NEAR=U5320.6:5MM
1
C5320
0.1UF
10%
6.3V
2
CERM-X5R
0201
>> SOC NUB_GPIO_5
106 22
OUT IN
22 33
IN
CHGR_AUX_OK
CHGR_AUX_OK
MAKE_BASE=TRUE
Delay for 3.8V VR Enable
RDAR://59315467
R5340 and C5340 might need tweaking afer charz.
R5342
2 2K
1/20W
5%
MF
201
2 1
CHGR_EN_MVR_A
NSR01L30MXT5G-COMBO
R5340
22
IN
CHGR_EN_MVR
200K
1/20W
1
MF
201
2 1
CHGR_EN_MVR_DLY
1
C5340
1UF
20%
10V
2
X5R
0201
D5340
X3DFN2
K A
PPCHGR_VDDA
22
PLACE_NEAR=U5340.5:2MM
1
C5341
0.1UF
10%
6.3V
2
CERM-X5R
0201
>> MPMU GPIO2
OUT
NOSTUFF
R5341
1/20W
0201
2
0
5%
MF
NC
2 1
5
U5340
74LVC1G17
X2SON5
1 3
4
PLACE_NEAR=U5200:5MM
P3V8AON_PWR_EN
OUT
24
SYNC_DATE=04/01/2020 SYNC_MASTER=REF_CHARGER_SUONA
PAGE TITLE
BATTERY CHARGER SUPPORT
BOM_COST_GROUP=BATTERY
Page 24
*** OK2RELEASE ***
w w w . t e k n i s i - i n d o n e s i a . c o m
3V8 AON CONTROLLER
105 25
26
101
25
5.5 < VIN < 13.5 V
4.75 < VDRV < 5.5 V
VDRV IS EXTERNAL OPTION TO
POWER IC INSTEAD OF VIN
TO SAVE POWER
4.75 < LDO5 < 5.25 V
MAX I_OUT TYP 160 MA
LDO5 NOT TO BE USED BY
SYSTEM IN 30A DESIGNS
PPBUS_VMAIN_VIN_ISNS
1
C5704
2.2UF
20%
25V
2
X6S-CERM
0402
138S00042
BYPASS=U5700.8::15MM
PP5V_S2_P3V8AON_VDRV
1
C5700
10UF
20%
16V
2
X6S
0603-1
138S00248
BYPASS=U5700.6::15MM
0603 SIZE REQUESTED BY DCDC
PP5V_AON
1
C5702
10UF
20%
16V
2
X6S
0603-1
138S00248
BYPASS=U5700.7::15MM
0603 SIZE REQUESTED BY DCDC
P3V8AON_PVCC
8
6
7
5
VIN
VDRV
LDO5
PVCC
U5700
RAA225501A-BOM1
QFN
OMIT_TABLE
"BOM1" SCH SYMBOL
FOR 30A OTP
APN OF SYMBOL
353S02326
BOOT1
UGATE1
PHASE1
LGATE1
BOOT2
UGATE2
PHASE2
LGATE2
BOOT3
UGATE3
PHASE3
LGATE3
4
3
2
1
29
30
31
32
28
27
26
25
F_SW IS REGISTER CONTROLLED
ICCMAX 30A DESIGN: 1 MHZ
P3V8AON_BST1
P3V8AON_DRVH1
P3V8AON_SW1
P3V8AON_DRVL1
P3V8AON_BST2
P3V8AON_DRVH2
P3V8AON_SW2
P3V8AON_DRVL2
P3V8AON_BST3
P3V8AON_DRVH3
P3V8AON_SW3
P3V8AON_DRVL3
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
25
25
25
25
2
25
25 99
25
25
25
25 99
25
23
33
101
IN
IN
ONLY FOR USE BY GATE
DRIVE CIRCUITRY
P3V8AON_PWR_EN
P3V8AON_LPM
PP5V_AON
PU TO INT LDO5 OR OTHER RAIL
P3V8AON_FAULT_L
R5710
0
2 1
5%
1/20W
MF
0201
R5711
0
2 1
5%
1/20W
MF
P3V8AON_LPM
0201
1
R5712
47K
5%
1/20W
MF
201
2
1
C5701
10UF
20%
16V
2
X6S
0603-1
138S00248
BYPASS=U5700.5::15MM
0603 SIZE REQUESTED BY DCDC
P3V8AON_PWR_EN_R
VIH_MAX 1.07 V
VIL_MIN 0.63 V
P3V8AON_LPM_R
VIH_MAX 1.1 V
VIL_MIN 0.5 V
24 117
24 117
I2C_P3V8AON_SCL
I2C_P3V8AON_SDA
VIH_MAX 1.1 V
VIL_MIN 0.5 V
GND'ED FOR POR (DATASHEET TABLE 1.5)
FAULT PULL DOWN CURRENT 1-2 MA TYPICAL
12
13
10
9
14
ENABLE
LPM
SCL
SDA
FAULT*
(9M PD)
(9M PD)
(OD)
VSEN
VRTN
CSP1
CSN1
CSP2
CSN2
15
16
19
20
21
22
P3V8AON_VSENSE
P3V8AON_VRTN
P3V8AON_ISEN1_P
P3V8AON_ISEN1_N
P3V8AON_ISEN2_P
P3V8AON_ISEN2_N
IN
IN
IN
IN
IN
IN
25
25
2
25
25
25
P3V8AON_IMON
IMON NOT TO BE USED SYSTEM SIDE
<RDAR://58648650>
IMON IS 2.52 V @ 30 A
VENDOR REQUIRES R > 1M, C < 50 PF
1
C5751
10PF
5%
25V
2
C0G
0201
131S00003
NOSTUFF
1
R5751
2.21K
1%
1/20W
MF
201
2
118S0199
R5750
1M
5%
1/20W
MF
201
117S0009
2 1
P3V8AON_IMON_P3V8AON
P3V8AON_GPIO
OPEN FOR PRODUCTION APPLICATION
PER DATASHEET REV 1.0
P3V8AON_SS
LONG STARTUP TIME SO INRUSH
NOSTUFF
1
R5700
100K
5%
1/20W
MF
201
2
BELOW 0.5A USB LIMIT
1
C5703
0.22UF
10%
25V
2
X5R
0201-1
18
IMON
11
GPIO
17
SOFTSTART
(0-4.5V)
CSP3
CSN3
EPAD
23
24
P3V8AON_ISEN3_P
P3V8AON_ISEN3_N
IN
IN
25
25
132S00202
REFERENCE DESIGNATOR(S) QTY DESCRIPTION PART#
IC,RAA225501,3-PH VOLT REG,TQFN32353S02326 1 U5700 CRITICAL P3V8AON_IC:A0
BOM OPTION CRITICAL
P3V8AON_IC:A1_R0B0IC AA 5501B,ICE,BOM1,A1,OTP-R0B0,QFN32353S02472 CRITICAL U5700 1
TA LE_5_ EAD
TA LE_5_ TEM
TA LE_5_ TEM
3V8_AON_I2C-DEV
NOSTUFF
1
R5760
1K
5%
1/20W
MF
201
2
3V8_AON_I2C-DEV
1
R5762
0
5%
1/20W
MF
0201
2
TPT_P3V8AON_PU_RAIL
3V8_AON_I2C-DEV
NOSTUFF
1
R5761
1K
5%
1/20W
MF
201
2
3V8_AON_I2C-DEV
1
R5763
0
5%
1/20W
MF
0201
2
TP5700
1
TP
TP-P5
3V8_AON_I2C-DEV
CKPLUS_WAIVE=I2C_PULLUP
I2C_P3V8AON_SCL
CKPLUS_WAIVE=I2C_PULLUP
I2C_P3V8AON_SDA
3V8_AON_I2C-POR 3V8_AON_I2C-POR
GND
MAKE_BASE=TRUE
GND
MAKE_BASE=TRUE
24 117
24 117
SYNC_MASTE =REF_VR_ICEMAN SYNC_DATE=04/09/2020
PAGE TITLE
POWER: 3V8 AON (1/2)
BOM_COST_GROUP=PLATFORM POWER
8
2
Page 25
*** OK2RELEASE ***
w w w . t e k n i s i - i n d o n e s i a . c o m
105 25 24
24
24
24
24
PPBUS_VMAIN_VIN_ISNS
CRITICAL
R5804
IN
OUT
P3V8AON_DRVH1
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
GATE_NODE=TRUE
DIDT=TRUE
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
DIDT=TRUE
SWITCH_NODE=TRUE
R5803
0
5%
1/20W
F
0201
117S0201
NOSTUFF
2.2
1/20W
117S0056
<RDAR://59524111>
2 1
P3V8AON_BST1_RC P3V8AON_BST1
MIN_LINE_WIDTH=0 2000
MIN_NECK_WIDTH=0.1000
DIDT=TRUE
SWITCH_NODE=T UE
5%
MF
201
2 1
C5811
0.1UF
2 1
10%
25V
X7R-CERM-1
0402
132S0438
P3V8AON_DRVH1_R
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
GATE_NODE=TRUE
DIDT=TRUE
P3V8AON_SW1
MIN_ INE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
SWITCH NODE=TRUE
DIDT TRUE
24
OUT
CRITICAL
Q5800
CSD58889Q3D
3
TG
4
TGR
Q3D
376S00012
VIN
VSW
1
6
7
8
99
D5800
SOD523
K A
5
BG
R5805
1
5%
1 16
MF-LF
402
116S0006
2 1
P3V8AON_DRVL1_R
MIN_LINE_WIDTH=0.2000
MIN_NECK WIDTH=0.1000
GATE_N DE=TRUE
DIDT=TRUE
24 25
IN
P3V8AON_PVCC
P3V8AON_DRVL1
MIN_LINE_WIDTH=0.2000
MIN NECK_WIDTH=0.1000
AT _ ODE=TRUE
DID =TRUE
SBR1A30T5
371S00245
3V8_EXT_DIODE
1
C5800
33UF
20%
16V
2
TANT
CASE-T
128S00009
CKPLUS_WAIVE=CAPDERATE
PACK_IGNORE=TRUE
3V8_AON_PBUS-B12
P3V8AON_VSW1 PP3V8AON_PH1
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
SWITCH_NODE=TRUE
DIDT=TRUE
116S0007
1
R5809
1.5
5%
1/16W
MF-LF
402
2
P3V8AON_SNUB1
SWITCH_NODE=TRUE
DIDT=TRUE
C ITICAL
1
C5801
33UF
20%
16V
2
TANT
CASE-T
128S00009
CKPLUS_WAIVE=CAPDERATE
PACK_IGNORE=TRUE
3V8_AON_PBUS-B12
CRITIC L
1
C5800
33UF
20%
16V
2
TANT
CASED12-SM
128S0436
CKPLUS_WAIVE=CAPDERATE
PACK_ GNORE=TRUE
3V8_AON PBUS-D12
1
2
1
2
NOSTUFF
C5814
220PF
5%
50V
C0G
0201-1
CRITICAL
C5801
33UF
20%
16V
TANT
CASED12-SM
128S0436
CKPLUS_WAIVE=CAPDERATE
PACK_IGNORE=TRUE
3V8_AON_PBUS-D12
1UH-20%-11A-0.0127OHM
NO_XNET_CONNECTION=1
1
C5810
5600PF
10%
10V
2
CERM-X7R
0201
132S0370
CRITICAL
1
C5800
68UF
20%
16V
2
POLY-TANT
CASE-D2E-SM
128S0264
CKPLUS_WAIVE=CAPDERATE
3V8_AON_PBUS-D2
CRIT C L
L5800
PIHA052D-SM
152S00265
R5801
2 1
118S0744
R5802
131S0514
1
OUT
P3V8AON_ISEN1_P
C5809
150PF
5%
50V
2
C0G-CERM
0402
<RDAR://59524111>
NOSTUFF
1
C5815
220PF
5%
50V
2
C0
0201-1
118S0744
CRITICAL
1
C5801
68UF
20%
16V
2
POLY-TANT
CASE-D2E-SM
128S0264
CKPLUS_WAIVE=CAPDERATE
3V8_AON_PBUS-D2
2 1
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=5V
1.00
1%
1/20W
MF-LF
0201
1.00
1%
1/20W
MF-LF
0201
P3V8AON_ISNS1_P
2 1
P3V8AON_ISNS1_N
1
C5804
2.2UF
20%
25V
2
X6S-CERM
0402
138S00042
MIRROR_WITH=C5804
1
C5805
2.2UF
20%
25V
2
X6S-CERM
0402
138S00042
NO_XNET_CONNECT ON=1
107S00373
R5800
0 004
1%
1/3W
LF
0306
95
ICCMAX = 30 A
2 1
4 3
1
C5890
150UF
20%
6.3V
2
TANT-POLY
CASE-B1S-1
128 00067
CKPLUS_WAI =CAPDERATE
MIRROR_WITH=C5887
1
C5886
2.2UF
20%
25V
2
95
X6S-CERM
0402
138S00042
CRITICAL CRITICAL
1
C5891
150UF
20%
6.3V
2
TANT-POLY
CASE-B1S-1
128S00067
CKPLUS_WAIVE=CAPDERATE
1
C5887
2.2UF
20%
25V
2
X6S-CERM
0402
138S0 042
CRITICAL
1
C5892
150UF
20%
6.3V
2
TANT-POLY
CASE-B1S-1
128S00067
CKPLUS_WAIVE=CAPDERATE
MIRROR_WITH=C5889
1
C5888
2.2UF
20%
25V
2
X6S-CERM
0402
138S00042
CRITICAL
1
C5893
150UF
20%
6.3V
2
TANT-POLY
CASE-B1S-1
128S00067
CKPL _WAIVE=CAPDERATE
1
C5889
2.2UF
20%
25V
2
X6S-CERM
0402
138S00042
CRITICAL
1
C5894
150UF
20%
6 3V
2
TANT-POLY
CASE-B1S-1
128S00067
CKPLUS_WAIVE=CAPDERAT
PP3V8_AON
CRITICAL
1
C5895
150UF
20%
6.3V
2
TANT-POLY
CASE-B1S-1
128S00067
CKPLUS_WAIVE=CAPDERATE
101
24
105 25 24
24
24
24
24
24
OUT
P3V8AON_ISEN1_N
PPBUS_VMAIN_VIN_ISNS
CRITICAL
1
C5820
ALLOW_APPLE_PREFIX=Q
IN
P3V8AON_DRVH2
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
GATE_NODE=TRUE
DIDT=TRUE
R5824
1 5
1
5%
1/8W
TK
0402
P3V8AON_DRVH2_R
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
GATE_NODE=TRUE
DIDT=TRUE
CRITICAL
Q5820
AONE36196
DFN
376S00281
107S00371
8
D1
OUT
P3V8AON_BST2
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
DIDT=TRUE
SWITCH_NODE=TRUE
R5823
0
0%
1/16W
MTL-FILM
0402
116 0 0
C5831
0.22UF
10%
25V
X7R
0402
2 1
P3V8AON_SW2
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
SWITCH_NODE=TRUE
DIDT= RUE
OUT
24 25 99
1
G1
2
3
D2/S1
4
2 1
P3V8AON_BST2_RC
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH 0.1000
DIDT=TRUE
SWITCH_NODE=TRUE
132S0401
D1
9
NOSTUFF
D5820
SOD523
1%
1/4W
MF
0402
K A
G2
7
R5826
2 1
P3V8AON_DRVL2_R
MIN_NECK_WIDTH=0. 00
MIN_LINE_WIDTH=0.1000
GATE_NODE=TRUE
DIDT=TRUE
0.100
1%
1/4W
MF
0402
104S0050
2 1
P3V8AON_DRVL2_RR
MIN_ IN _WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
GATE_NODE=TRUE
DIDT=TRUE
VER-1
24 25
P3V8AON_PVCC
SBR1A30T5
371S00245
8_EXT_DIODE
R5825
0.100
104S0050
IN
OUT
OUT
P3V8AON_DRVL2
M N_ ECK_WIDTH=0.2000
MIN LINE_WIDTH=0.1000
GATE_NODE=TRUE
DIDT=TRUE
P3V8AON_ISEN2_P
P3V8AON_ISEN2_N
33UF
20%
16V
2
TANT
CASE-T
128S00009
CKPLUS_WAIVE=CAPDERATE
PACK_IGNORE=TRUE
3V8_AON_PBUS-B12
24 25 99
IN
SAME SW NET
ON BOTH SIDES
P3V8AON_SW2
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
SWITCH_NODE=TRUE
DIDT=TRUE
1
R5829
2.2
5%
1/16W
MF-LF
402
2
P3V8AON_SNUB2
1
C5829
100PF
5%
50V
2
C0G
0402
CRITICAL
1
C5821
33UF
20%
16V
2
TANT
CAS -T
128S00009
CKPLUS_WAIVE=CAPDERATE
PACK_IGNORE=TRUE
3V8_AON_PBUS-B12
NOSTUFF
DIDT=TRUE
SWITCH_NODE=TRUE
NOSTUFF
CRITICAL
1
C5820
33UF
20%
16V
2
TANT
CASED12-SM
128S0436
CKPLUS_WAIVE=CAPDERATE
PACK_IGNORE=TRUE
3V8_AON_PBUS-D12
CRITICAL
1
C5820
68UF
20%
16V
2
POLY-TANT
CASE-D2E-SM
128S0264
CKPLUS_WAIVE=CAPDERATE
3V8_AON_PBUS-D2
0.56UH-20%-22.0A-0.0067OHM
NOSTUFF
1
C5834
220PF
5%
50V
2
C0G
0201-1
NOSTUFF
1
C5835
220PF
5%
50V
2
C0G
0201-1
1
C5824
2.2UF
20%
25V
2
X6S CERM
0402
138S00042
CRITICAL
L5820
PILA062D-SM- OMBO
152S01248
NO_XNET_CONNECTION=1
1
C5830
5600PF
10%
10V
2
CERM-X7R
0201
132 3 0
MIRROR_WITH=C5824
1
C5825
2.2UF
20%
25V
2
X6S-CERM
0402
138S00042
2 1
PP3V8AON_PH2
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=5V
R5821
1.00
2 1
1%
1/20W
MF-LF
0201
118S0744
R5822
1.00
1%
1/20W
MF-LF
0201
118S0744
P3V8AON_ISNS2_P
2 1
P3V8AON_ISNS2_N
107S00090
R5820
0.001
1%
1/3W
MF
030
NO_XNET_CONNECT ON=1
2 1
4 3
95
95
105 25 24
24
24
24
24
24
PPBUS_VMAIN_VIN_ISNS
CRITICAL
ALLOW_APPLE_PREFIX=Q
IN
P3V8AON_DRVH3
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
GATE_NODE=TRUE
DIDT=TRUE
R5844
1.5
5%
1/8W
TK
0402
2 1
P3V8AON_DRVH3_R
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
GATE_NODE=TRUE
DIDT=TRUE
CRITICAL
Q5840
AONE36196
DFN
376S00281
107S00371
8
D1
OUT
P3V8AON_BST3
MIN LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
DIDT=TRUE
SWITCH_NODE=TRUE
R5843
0
1
0%
1/16W
MTL-FILM
0402
116S00006
P3V8AON_BS 3_RC
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
DIDT=TRUE
SWITCH_NODE=TRUE
C5851
0.22UF
2 1
10%
25V
X7R
0402
132S0401
P3V8AON_SW3
MIN_L NE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
SWITCH_NODE=TRUE
DIDT=TRUE
24 25 99
OUT
1
G1
2
3
D2/S1
4
D1
9
NOSTUFF
D5840
SOD5 3
1%
1/4W
MF
0402
K A
G2
7
R5846
2 1
P3V8AON_DRVL3_R
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.1000
GATE_NODE=TRUE
DIDT=TRUE
0.100
1%
1/4W
MF
0402
104S0050
2 1
P3V8AON_DRVL3_RR
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
GATE_NODE=TRUE
DIDT=TRUE
VER-1
24 25
P3V8AON_PVCC
SBR1A30T5
371S00245
3V8_EXT_DIODE
R5845
0.100
104S0050
IN
OUT
OUT
P3V8AON_DRVL3
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.1000
GATE_NODE=TRUE
DIDT=TRUE
P3V8AON_ISEN3_P
P3V8AON_ISEN3_N
1
C5840
33UF
20%
16V
2
TANT
CASE-T
128S00009
CKPLUS_WAIVE=CAPDERA
PACK_IGNORE=TRUE
3V8_AON_PBUS-B12
24 25 99
IN
SAME SW NET
ON BOTH SIDES
P3V8AON_SW3
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
SWITCH_NODE=TRUE
DIDT=TRUE
1
R5849
2.
5%
1/16W
MF-LF
402
2
P3V8AON_SNUB3
1
C5849
100PF
5%
50V
2
C0G
0402
CRITICAL
1
C5841
33UF
20%
16V
2
TANT
CASE-T
128S00009
CKPLUS_WAIVE=CAPDERATE
PACK_IGNORE=TRUE
3V8_AON_PBUS-B12
NOSTUFF
DIDT=TRUE
SWITCH_NODE=TRUE
NOSTUFF
CRITICAL
1
C5840
33UF
20%
16V
2
TANT
CASED12-SM
128S0436
CKPLUS_W VE=CAPDERATE
PACK_IGNORE=TRUE
3V8_AON_PBUS-D12
CRITICAL
1
C5840
68UF
20%
16V
2
POLY-TANT
CASE-D2E-SM
128S0264
CKPLUS_WAIVE=CAPDERATE
3V8_AON_PBUS-D2
0.56UH-20%-22.0A-0.0067OHM
NOSTUFF
1
C5854
220PF
5%
50V
2
C0G
0201-1
NOSTUFF
1
C5855
220PF
5%
50V
2
C0G
0201-1
1
C5844
2.2UF
20%
25V
2
X6S-CERM
0402
138S00042
CRITICAL
L5840
PILA062D-SM-COMBO
152S01248
NO_XNET_CONNECTION=1
1
C5850
5600PF
10%
10V
2
CERM-X7R
0201
132S0370
MIRROR_WITH=C5844
1
C5845
2.2UF
20%
25V
2
X6S-CERM
0402
138S00042
2 1
PP3V8AON_PH3
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=5V
R5841
1.00
2 1
1%
1/20W
MF-LF
0201
118S0744
R5842
1.00
1%
1/20W
MF-LF
0201
118S0744
P3V8AON_ISNS3_P
2 1
P3V8AON_ISNS3_N
107S00090
R5840
0 001
1%
1/3W
MF
0306
NO_XNET_CONNECT ON=1
2 1
4 3
95
95
NO_XNET_CONNECTION=1
XW5870
2 1
SM
NO_XNET_CONNECTION=1
XW5871
2 1
S
P3V8AON_VSNS_XW_P
P3V8AON_VSNS_XW_N
NO_XNET_CONNEC ON
R5870
0
2 1
5%
1/20W
MF
0201
117S0201
NO_XNET_CONNECTION=1
R5871
0
2 1
5%
1/20W
MF
0201
117S0201
PAGE TITLE
P3V8AON_VSENSE
OUT
24
NOSTUFF
1
C5870
1UF
20%
10V
2
X6S-CERM
0201
138S00044
NO_XNET_CONNECTION=1
P3V8AON_VRTN
OU
24
POWER: 3V8 AON (2/2)
SYNC_DATE=03/30/2020SYNC_MASTER=REF_VR_ICEMAN
BOM_COST_GROUP=PLATFORM POWER
2
1
Page 26
104
w w w . t e k n i s i - i n d o n e s i a . c o m
ZERO OHM RESISTOR TO ALLOW ACCESS TO VDRV
PP5V_S2
R5900
0
2 1
5%
1/16W
MF-LF
402
116S0004
PP5V_S2_P3V8AON_VDRV
MAKE_BASE=TRUE
VOLTAGE=5V
MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000
PP5V_S2_P3V8AON_VDRV
24
BOM_COST_GROUP=PLATFORM POWER
PAGE TITLE
POWER: 3V8 AON SUPPORT
2
1
Page 27
SLAVE PMU INPUT POWER & BUCKS
w w w . t e k n i s i - i n d o n e s i a . c o m
105 28 27
PP3V8_AON_SPMU_ISNS_VIN
CRITICAL
1
C7700
10UF
20%
6.3V
2
CER-X6S
0402
1
C7708
1UF
20%
10V
2
X6S-CERM
0201
1
C770G
1UF
20%
10V
2
X6S-CERM
0201
1
C771M
12PF
5%
25V
2
NP0-C0G
0201
PLACE_NEAR=U7700.C13:10MM
FED BY SPMU BUCK13 (1.2V)POWER ALIAS=>
FED BY MPMU BUCK3 (1.8V)POWER ALIAS=>
PLACE_NEAR=U7700 C13:10MM
CRITICAL
1
C7701
10UF
20%
6.3V
2
CER-X6S
0402
1
C7709
1UF
20%
10V
2
X6S-CERM
0201
1
C770H
1UF
20%
10V
2
X6S-CERM
0201
1
C771N
3.0PF
+/-0.1PF
25V
2
NP0-C0G
02
PLACE_NEAR=U7700.G13:10MM
1
C7702
10UF
20%
6.3V
2
CER-X6S
0402
1
C770A
1UF
20%
10V
2
X6S-CERM
0201
1
C770I
1UF
20%
10V
2
X6S-CERM
0201
1
C772M
12PF
5%
25V
2
NP0-C0G
0201
1
C7703
10UF
20%
6.3V
2
CER-X6S
0402
1
C770B
1UF
20%
10V
2
X6S-CERM
0201
1
C770J
1UF
20%
10V
2
X6S- ERM
0201
1
C772N
3.0PF
+/-0.1PF
25V
2
NP0-C0G
0201
PLACE_NEAR=U7700.G13:10MM
28
102
101
PLACE_NEAR=U7700.M2:10MM
PLACE_NEAR=U7700.L13:10MM
PP5V_BSTLQ_SPMU
VOLTAGE=5V
1
C7716
10%
10V
2
X6S-CERM
0201
1
2
1
2
1
2
1
2
1
2
CRITICAL CRITICAL CRITICAL CRITICAL
1
C7704
10UF
20%
6.3V
CER-X6S
0402
C770C
1UF
20%
10V
X6S-CERM
0201
C770K
1UF
20%
10V
X6S-CERM
0201
C773M
12PF
5%
25V
NP0-C0G
0201
PLACE_NEAR=U7700.M2:10MM
C775M
12PF
5%
25V
NP0-C0G
0201
PLACE_NEAR=U7700.L13:10MM
PP1V5_VLDOINT_SPMU
28
105 28 27
PLACE_NEAR=U7700.D4:5MM
PP3V8_AON_SPMU_ISNS_VIN
1
C7717
0.1UF
10%
10V
2
X6S-CERM
0201
C7705
10UF
20%
6.3V
2
0402
1
C770D
1UF
20%
10V
2
X6S-CERM
0201
1
C770L
1UF
20%
10V
2
X6S-CERM
0201
1
C773N
3.0PF
+/-0.1PF
25V
2
NP0-C0G
0201
1
C775N
3.0PF
+/-0.1PF
25V
2
NP0-C0G
0201
PLACE_NEAR=U7700.L7:5MM
PP1V25_S2
PP1V8_S2
CRITICAL CRITICAL
1
C771A
0.1UF 0.1UF
10%
10V
2
X6S-CERM
0201
1
C7706
1UF
20%
10V
2
X6S-CERM CER-X6S
0201
1
C770E
1UF
20%
10V
2
X6S-CERM
0201
1
C770M
12PF
5%
25V
2
NP0-C0G
0201
PLACE_NEAR=U7700 L1 0MM
1
C774M
12PF
5%
25V
2
NP0-C0G
02
PLACE_NEAR=U7700.N6:10MM
1
C776M
12PF
5%
25V
2
NP0-C0G
0201
PLACE_NEAR=U7700.D9:10MM
1
C7714
0.1UF
10%
10V
2
X6S-CERM
0201
PLACE_NEAR=U7700.C9:5MM
1
C7707
1UF
20%
10V
2
X6S-CERM
0201
1
C770F
1UF
20%
10V
2
X6S-CERM
0201
1
C770N
3.0PF
+/-0.1PF
25V
2
NP0-C0G
0201
PLACE_N AR=U7700.L1:10MM
1
C774N
3.0PF
+/-0.1PF
25V
2
NP0-C0G
0201
PLACE_NEAR=U7700.N6:10MM
1
C776N
3.0PF
+/-0.1PF
25V
2
NP0-C0G
0201
PLACE_NEAR=U7700.D9:10MM
CRITICAL CRITICAL CRITICAL
1
C7715
0.1UF
1 %
10V
2
X6S-CERM
0201
30 29 27
VSS_ANA_SPMU
C13
VDD_BUCK5_4_10
C14
VDD_BUCK5_4_10
G13
VDD_BUCK5_4_10
G14
VDD_BUCK5_4_10
M2
VDD_BUCK6
N2
VDD_BUCK6
P2
VDD_BUCK6
N6
VDD_BUCK12
P6
VDD_BUCK12
L13
VDD_BUCK13
L14
VDD_BUCK13
L1
VDD_MAIN_BUCK6
L9
VDD_MAIN_SOUTH
E8
VDD_MAIN
D2
VDD_MAIN_LDO
E2
VDD_MAIN_LDO
D8
VDD_MAIN_SNS
E10
VDD_SNS_SPARE
C12
VDD_ANA
D3
VDD_ANA
E7
VDD_ANA
G12
VDD_ANA
K3
VDD_ANA
L8
VDD_ANA
L12
VDD_ANA
M6
VDD_ANA
D5
VDD_DIG
D10
VDD_DIG
J3
VDD_DIG
J10
VDD_DIG
D9
VDD_BOOST
B2
VDD_BOOST_LDO
C2
VDD_BOOST_LDO
E9
VDD_BOOST_SNS
D4
VDD_HI_INT1
L4
VDD_HI_INT2
L7
VDD_HI_INT3
M10
VDD_HI_INT4
J11
VDD_HI_INT5
A11
VDD_HI_INT6
C9
VDD_HI_INT7
G10
VDDIO_1V2
H10
VDDIO_BUCK3
K6
VPP
998-22526
OMIT_TABLE
U7700
TMLT47A1-JPE
WLCSP
SYM 1 OF 4
BUCK4_LX0
BUCK4_LX1
BUCK4_LX1
BUCK4_FB
BUCK4_VSS_FB
BUCK5_LX_0
BUCK5_LX_1
BUCK5_FB
BUCK5_VSS_FB
BUCK6_LX_0
BUCK6_LX_1
BUCK6_LX_2
BUCK6_FB
BUCK6_VSS_FB
BUCK6_VOUT_0
BUCK6_VOUT_1
BUCK6_VOUT_2
BUCK10_LX_0
BUCK10_LX_1
BUCK10_FB
BUCK10_VSS_FB
BUCK12_LX_0
BUCK12_LX_1
BUCK12_FB
BUCK12_VSS_FB
BUCK13_LX_0
BUCK13_LX_1
BUCK13_FB
BUCK13_VSS_FB
F14
D13
D14
F11
F12
H13
H14
H11
H12
M3
N3
P3
L3
K2
M1
N1
P1
B13
B14
B11
B12
N5
P5
L5
M5
K13
K14
K11
K12
L7740
OUT
30
1.0UH-20%-4A-0.038OHM
BUCK4_LX0
DIDT=TRUE
SWITCH_NODE=TRUE
30
OUT
0.22UH-20%-6.7A-0.023OHM
PIKA20161B-COMBO
L7741
BUCK4_LX1
DIDT=TRUE
SWITCH_NODE=TRUE
PINA20121T-SM
R770A
0
2 1
BUCK4_FB
5
PLACE_NEAR=U7700.F11:15MM
VSS_ANA_SPMU
30
OUT
0.47UH-20%-4A-0.027OHM
BUCK4_FB_R
0201 MF 1/20W
30 29 27
L7750
BUCK5_LX0
DIDT=TRUE
SWITCH_NODE=TRUE
2012
R770B
0
BUCK5_FB BUCK5_FB_R
PLAC _NEAR=U7700.H12:15MM
VSS_ANA_SPMU
30
OUT
2 1
0201
MF 1/20W 5%
30 29 27
L7760
0.47UH-20%-6.9A-0.022OHM
BUCK6_LX0
DIDT= RUE
SWITCH_NODE=TRUE
IUA25201B-SM
R770C
0
BUCK6_FB BUCK6_FB_R
1/20W 0201 MF
5%
PLACE_NEAR=U7700.L3:15MM
VSS_ANA_SPMU
2 1
30 29 27
PP2V5_AWAKE_NAND
L77A0
OUT
30
0.47UH-20%-4A-0.027OHM
BUCK10_LX0
DIDT=TRUE
SWITCH_NODE=TRUE
2012
R770D
0
BUCK10_FB
PLACE_NEAR=U7700.B11:15MM
VSS_ANA_SPMU
30
OUT
2 1
BUCK10_FB_R
0201
MF 5% 1/20W
30 29 27
L77C0
0.47UH-20%-4A-0.027OHM
BUCK12_LX0
DIDT=TRUE
SWITCH_NODE=TRUE
2012
R770E
BUCK12_FB
PLACE_NEAR=U7700.L5:15MM
VSS_ANA_SPMU
2 1
BUCK12_FB_R
0201 5% 1/20W0MF
29 27
L77D0
0.47UH-20%-4A-0.027OHM
30
BUCK13_LX0
DIDT=TRUE
SWITCH_NODE=TRUE
2012
R770F
0
BUCK13_FB
PLACE_NEAR=U7700.K11:15MM
VSS_ANA_SPMU
5%
1/20W
2 1
BUCK13_FB_R
MF 0201
30 29 27
CRITICAL
2 1
CRITICAL
2 1
XW7700
SHORT-14L-0.1MM-SM
2 1
NO_XNET_CONNECTION=1
CRITICAL
2 1
XW7701
SHORT-14L-0.1MM-SM
2 1
NO_XNET_CONNECTION=1
CRITICAL
2 1
XW7760
SHORT-14L-0.1MM-SM
2 1
NO_XNET_CONNECTION=1
101 27
CRITICAL
2 1
XW77A0
SHORT-14L-0.1MM-SM
2 1
NO_XNET_CONNECTION=1
CRITICAL
2 1
XW77C0
SHORT-14L-0.1MM-SM
2 1
NO_XNET_CONNECTION=1
CRITICAL
2 1
XW77D0
SHORT-14L-0.1MM-SM
2 1
NO_XNET_CONNECTION=1
CRITICAL
1
C7740
15UF
20%
2V
2
X6S
0402
CRITICAL CRITICAL CRITICAL
1
C7710
20% 20% 20%
2V
2
X6S X6S
CRITICAL
1
C7750
15UF
2V
2
X6S
0402 04 0402 0402 0402 0402 04
1
C778M
12PF
5%
25V
2
NP0-C0G
0201
PLACE_NEAR=L7750.2:5MM
PLACE_NEAR=L7750.2:5MM
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
1
C7760
10UF
20%
6.3V
2
CER-X6S
0402
CRITICAL
1
C7766
10UF
20%
6.3V
2
CER-X6S
0402
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
1
C77A0
15UF
20%
2V
2
0402 0402 0402 0402
1
C77C0
15UF 15UF
2V
2
X6S
1
C7792
12PF
5%
25V
2
NP0-C0G
0201
PLACE_NEAR=L77C0.2:5MM
PLACE_NEAR=L77C0.2:5MM
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
1
C77D3
15UF
20%
2V
2
X6S
0402 0402 0402 0402 0402 0402
PP1V06_S2SW_DRAM
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
1
C7741
15UF
20%
2V
2
X6S
0402 0402 0402 0402 0402 0402
1
C7742
15UF
20%
2V
2
0402
1
C7743
15UF
20%
2V
2
1
C7744
15U
20%
2
1
C7745
15UF
20%
2V 2V
2
CRITICAL CRITICAL
1
C7746
15UF
20%
2V
2
1
C7747
15UF
20%
2V
2
X6S X6S X6S X6S X6S X6S
CRITICAL
1
C7711
15UF 15UF
2V
2
1
C7712
15UF
2V
2
X6S
1
C7713
15UF
20%
2V
2
X6S
0402 0402 0402 0402
1
C777M
12PF
5%
5V
2
NP0-C0G
0201
PLACE_NEAR=L7740.2:5MM
P CE N AR=L7741.2:5MM
1
C777N
3.0PF
+/-0.1PF
25V
2
NP0-C0G
0201
PP0V764_S1_SRAM
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
1
C7751
20% 20%
2V
2
X6S
0402
1
C778N
3.0PF
+/-0.1PF
25V
2
NP0-C0G
0201
1
C7752
15UF 15UF
20%
2
X6S
1
C7753
15UF
20%
2V 2V
2
1
C779M
12PF
5%
25V
2
NP0-C0G
0201
PLACE_NEAR=L7760.2:5MM
PLACE_NEAR=L7760.2:5MM
1
C7754
15UF
2
X6S X6S
1
C779N
3.0PF
+/-0.1PF
25V
2
NP0-C0G
0201
1
C7755
20% 20%
2V 2V
2
X6S
1
C7756
15UF 15UF
2V
2
X6S
1
C7757
15UF
20% 20%
2V
2
X6S
PP2V5_AWAKE_NAND
1
C7761
10UF
20%
6 3V
2
C R-X6S
0402
1
2
CRITICAL
1
C7767
10UF 10UF
20%
6.3V
2
CER-X6S
0402
1
2
C7762
10UF
20%
6.3V
CER-X6
0402
C7768
20%
6 3V
CER-X6S
04
1
C7763
10UF
20%
6.3V
2
CER-X6S
0402
1
C7769
10UF
20%
6.3V
2
0402
1
C7764
10UF
20%
6 3V
2
C R- 6S
0402
1
C776A
10UF
20%
6.3V
2
CER-X6S CER-X6S
0402
1
C7765
10UF
20%
6.3V
2
CER-X6S
0402
1
C776B
10UF
20%
6.3V
2
CER-X6S
0402
1
C776C
10UF
20%
6 3V
2
C R-X6S
1
C776E
10UF
20%
6.3V
2
CER-X6S
0402 04
1
C776D
10UF
20%
6.3V
2
CER-X6S
0402 0402
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
1
C776F
10UF
20%
6 3V
2
CER-X6S
PP0V6_S1_VDDQL
1
C77A1
15UF
2V
2
X6S X6S
NOSTUFF
1
C77A2
15UF
20% 20%
2
X6S
1
C77A3
15UF
20%
2V 2V
2
X6S
NOSTUFF
1
C7722
15UF
20%
2
0402 0402
1
C7723
15UF
20%
2V 2V
2
X6S X6S
1
C7790
12PF
5%
25V
2
NP0-C0G
0201
PLACE_NEAR=L77A0.2:5MM
PLACE_NEAR=L77A0.2:5MM
PP0V88_S1 1 1
1
C7791
3.0PF
+/-0.1PF
25V
2
NP0-C0G
0201
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
1
C77C1
20%
2V 2V
2
X6S
1
C7793
3.0PF
+/-0.1PF
25V
2
N 0-C0G
0201
1
C77C2
15UF
20%
2
X6S
0402 0402 0402 0402
1
2
C77C3
15UF
20% 20%
2V
X6S
1
C7718
15UF
20%
2V 2V
2
X6S
1
C7719
15UF
20%
2
X6S
1
C7720
15UF 15UF
20%
2V
2
X6S
1
C7721
20%
2V
2
X6S
0402 0402 0402 0402
PP1V25_S2
1
C77D4
15UF
2
X6S
1
C77D5
15UF
20% 20%
2V 2V
2
1
C77D6
15UF
20%
2V
2
X6S X6S
1
C77D7
15UF
20%
V
2
X6S
1
C77D8
15UF
20%
2V
2
X6S
1
C7794
12PF
5%
25V
2
NP0-C0G
0201
PLACE_NEAR=L77D0.2:5MM
PLACE_NEAR=L77D0.2:5MM
1
C7795
3.0PF
+/-0 1PF
25V
2
NP0-C0G
0201
101
101
101 27
101
102
PLACE_NEAR=U7700.G10:5MM
PLACE_NEAR=U7700.H10:5MM
C TE CM TE E T M
PAGE TITLE
PMU: SLAVE INPUT PWR & BUCKS
BOM COST GROUP=PLATFORM POWER
Page 28
SLAVE PMU LDO, SWITCHES & BOOST
w w w . t e k n i s i - i n d o n e s i a . c o m
FROM BUCK13 =>
FROM BUCK13 OR =>
POST EVT: BUCK14
FROM BUCK4 =>
FROM BUCK12 =>
102
34 28
101
101 28
105 28 27
LDO/SW INPUTS LDO/SW OUTPUTS
PP1V25_S2
PPVDD_PMU_LDO_PREREG
PP1V06_S2SW_DRAM
PP0V88_S1
PP3V8_AON_SPMU_ISNS_VIN
M7
C4
N7
P7
A1
A2
VDD_LDO4
VDD_LDO8
VDD_LDO11
VDD_LDO12
VDD_LDO15
VDD_LDO15
998-22526
OMIT_TABLE
U7700
TMLT47A1-JPE
WLCSP
SYM 2 OF 4
VLDO4
VLDO6
VLDO8
VLDO9
VLDO11
VLDO12
VLDO15
VLDO17
M8
D1
C3
E3
N8
P8
A3
B1
PP0V72_S2_VDD_LOW
NC_SPMU_VLDO6
PP1V2_AWAKE_PLL
PP1V8_AON_SPMU
PP0V855_S2SW_CIO
PP0V805_S1_VDD_FIXED
NC_SPMU_VLDO15
NC_SPMU_VLDO17
102 28
102
102 28
102 28
102 28
103 28
103
103
FROM BUCK3 POWER ALIAS =>
FROM BUCK13 POWER ALIAS =>
FROM BUCK12 POWER ALIAS =>
102 29
101 28
101
1
C7810
10UF
20%
6.3V
2
CER-X6S
0402
CRITICAL
1
C7811
10UF
20%
6.3V
2
CER-X6S
0402
FROM BUCK13 OR =>
POST EVT: BUCK14
34 28
CRITICAL CRITICAL
1
C7812
10UF
20%
6.3V
2
CER-X6S
0402
THIS IS AN OUTPUT(1.5V) =>
105 28 27
27
PPVDD_PMU_LDO_PREREG
PP1V8_S2
PP1V25_S2
PP0V88_S1
PP3V8_AON_SPMU_ISNS_VIN
PP1V5_VLDOINT_SPMU
VOLTAGE=1.5V
B4
M11
M13
N13
P13
N11
P11
N9
P9
J2
E1
VDD_LDO20
VDD_SW4
VDD_SW5
VDD_SW5
VDD_SW5
VDD_SW6
VDD_SW6
VDD_SW7
VDD_SW7
VDD_MAIN_BSTLQ
VLDOINT
SWITCHED RAILS
VLDO18
VLDO20
BUCK_SW4
BUCK_SW5
BUCK_SW5
BUCK_SW5
BUCK_SW6
BUCK_SW6
BUCK_SW7
BUCK_SW7
BSTLQ_LX
BSTLQ_FB
BSTLQ_VOUT
VCP_OUT_SPARE
VMBX_SPARE
C1
B3
M12
M14
N14
P14
N12
P12
N10
P10
G1
J1
H1
M9
F10
NC_SPMU_VLDO18
PP1V2_S2_CIO
PP1V8_AWAKE_SPMU_GPIO
VOLTAGE=1.8V
PP1V25_AWAKESW_VCCQ
PP0V88_AWAKESW_NAND
SPMU_BSTLQ_LX
30
SWITCH_NODE=TRUE
DIDT=TRUE
PP5V_BSTLQ_SPMU
27
NO_TEST=1
VOLTAGE=5V
NC_SPMU_VCP_OUT_SPARE
NC_SPMU_VMBX_SPARE
NO_TEST=1
103
103 28
102 28
102 28
CRITICAL
L7800
0.47UH-20%-1.7A-0.175OHM
2 1
0402-COMBO
XW78D0
SHORT-12L-0.25MM-SM
1
C7800
20UF
20%
10V
2
X5R
0402
2 1
CRITICAL
1
C7801
20UF
20%
10V
2
X R
PLACE_NEAR=U7700.H1:5MM
1
C7822
1UF
20%
10
2
X6S-CERM
0201
PLACE_NEAR=U7700.M12:5MM
1
C7898
12PF
5%
25V
2
NP0-C0G
0201
PLACE_NEAR=U7700.M12:5MM
PP3V8_AON_SPMU_ISNS_VIN
PP5V_BSTLQ_VOUT_SPMU
1
C7892
5%
25V
2
NP0-C0
0201 0402
PLACE_NEAR=U7700.H1:5MM
1
C7893
3.0PF 12PF
+/-0.1PF
25V
2
NP0-C0G
0201
<= BUCK_SW4 USED FOR SPMU GPIO
1
C7899
3.0PF
+/-0.1PF
25V
2
NP0-C0G
0201
CRITICAL CRITICAL
1
C7831
0.1UF
1 %
10V
2
X S ERM
02 1
VOLTAGE=5V
PLACE_NEAR=U7700 H :5MM
GND
105 28 27
30 29
Decoupling: VDD_LDO8
PPVDD_PMU_LDO_PREREG
CRITICAL
1
C7813
10UF
20%
6.3V 6.3V
2
CER-X6S
0402 0402
Decoupling: LDO4
PP0V72_S2_VDD_LOW
CRITICAL
1
C7820
10UF 10UF
20% 20%
6.3V 6.3V
2
CER-X6S CER-X6S
0402 0402
CRITICAL
1
C780D
2
Decoupling: LDO11
34 28
PP0V855_S2SW_CIO
CRITICAL
1
C7809
10UF
20%
2
CER-X6S
Decoupling: LDO12
102 28
PP0V805_S1_VDD_FIXED
CRITICAL
1
C7821
10UF
20%
2
CER-X6S
Decoupling: SW5
PP1V25_AWAKESW_VCCQ
1
C7802
10UF
20%
6.3V
2
CER-X6S
0402
1
C780C
10UF
20%
6.3V
2
CER-X6S
0402
NOSTUFF
102 28
Decoupling: SW6/7
103 28
CRITICAL CRITICAL CRITICAL CRITICAL
1
C780B
10UF
20%
6.3V 6.3V
2
CER-X6S
0402 0402
PP0V88_AWAKESW_NAND
1
C7830
10UF
20%
6.3V
2
CER-X6S
1
C7803
10UF
20%
6.3V
2
CER-X6S
0402
1
C7829
10UF
20%
6.3V
2
CER-X6S
0402 0402
1
C7896
12PF
5%
25V
2
NP0-C0G
0201
PLACE_NEAR=U7700.M14:5MM
PLACE_NEAR=U7700.M14:5MM
1
C7828
10UF
20%
6.3V
2
CER-X6S
0402
PLACE_NEAR=U 700.N12:5MM
1
2
1
2
PLACE_NEAR=U7700.N12:5MM
C7897
3.0PF
+/-0.1PF
25V
NP0-C0G
0201
C7894
12PF
5%
25V
NP0-C0G
0201
102 28
1
2
C7895
3.0PF
+/-0.1PF
25V
NP0-C0G
0201
CRITICAL
1
C7825
0.1UF
10%
10V
Decoupling: LDO.INT
PP1V5_VLDOINT_SPMU
1
C7807
220PF
10%
16V
2
CER-X7R
0201
1
C7808
220PF 10UF
10%
16V
2
CER-X7R
0201
CRITICAL
1
C7823
10UF
20%
6.3V
2
CER-X6S
0402
CRITICAL CRITICAL CRITICAL CRITICAL
1
C7834
20%
6.3V
2
CER-X6S
0402
27 28
2
X6S-CERM
0201
PLACE_NEAR=U7700.J1:5MM
Decoupling and Desense: BSTLQ
102 28
PP3V8_AON_SPMU_ISNS_VIN
CRITICAL CRITICAL
1
C7815
1UF
20%
10V
2
X6S-CERM
0201
PLACE_NEAR= 7700.J2:5MM
PLACE_NEAR=U7700.J2:5MM PLACE_NEAR=L7800.2:5MM
1
C7816
1UF
20%
10V
2
X6S-CERM
1
C7890
12PF
5%
25V
2
NP0-C0G
0201
PLACE_NEAR=L7800.2:5MM
1
C7891
3.0PF
+/-0.1PF
25V
2
NP0-C0G
0201 0201
105 28 27
Decoupling: LDO8
PP1V2_AWAKE_PLL
CRITICAL
1
C7805
10UF 10UF
20%
2
1
C7806
20%
6.3V 6.3V
2
CER-X6S CER-X6S
0402 0402
Decoupling: VDD_LDO20
102 28
PPVDD_PMU_LDO_PREREG
CRITICAL CRITICAL
1
C7814
10UF
20%
6.3V
2
CER-X6S
0402
NOSTUFF
Decoupling: LDO9 Decoupling: LDO20
PP1V8_AON_SPMU
CRITICAL
1
C7824
1UF
20%
2
1
2
CRITICAL
C7835
1UF
20%
10V 10V
X6S-CERM X6S-CERM
102 28
PP1V2_S2_CIO
1
C7804
2
0402
NOSTUFF
CRITICAL CRITICAL
1
C780A
10UF 10UF
20% 20%
6.3V 6.3V
2
CER-X6S CER-X6S
0402 0201 0201
34 28
CM TE E T M
PAGE TITLE
PMU: SLAVE LDO
103 28
BOM COST GROUP=PLATFORM POWER
Page 29
SLAVE PMU GND,ADC,& GPIO
w w w . t e k n i s i - i n d o n e s i a . c o m
998-22526
OMIT_TABLE
PLACEMENT NOTE:
CONNECT VSS_REF THROUGH ALL GND PLANES PLACE XW AT VSS_REF PIN, ROUTE VSS_RTN
BACK FROM THE VREF / IREF PASSIVES
XW79D0
SHORT-14L-0.1MM-SM
49 30 29
VSS_ANA_SPMU
2 1
SPMU_VREF_IREF_RTN
C7985
0.1UF
10%
6.3V
CERM-X5R
0201
30 29
VSS_ANA_SPMU
U7700
TMLT47A1-JPE
WLCSP
SYM 3 OF 4
SPMU_IREF
1
R7903
200K
0.1%
1/20W
TF
0201
2
NOSTUFF
1
C7906
0.1UF
10%
6.3V
2
CERM-X5R
0201
1
C7905
1.5UF
20%
6.3V
2
CER-X5R
0201
49 30 29
SPMU_VREF
SPMU_VREF_ADC
VSS_ANA_SPMU
SPMU_TCAL
49
1
2
VSS_ANA_SPMU
30
103S00511
CRITICAL
R7940
3.92K
0201-2
1/20W
DFT_CTRL0=0 ==> DFT_CTRL1=SWDCLK
0.1%
MF
2
1
1
C7940
100PF
5%
25V
2
C0G
0201
IN
49
IN
49
IN
49
IN
49
IN
30
IN
30
IN
30
IN
3
IN
30
IN
30
OUT
30
IN
30
IN
30
IN
30
IN
30
OUT
30
IN
30 29 27
9 33
IN
SPMU_THMSNS
AMB_THMSNS
NAND0_THMSNS
NAND1_THMSNS
FINSTACK_THMSNS
SPMU_ADC_IN
SOC_VDDPCPU_VSENSE
SOC_VSSPCPU_VSENSE
SOC_VDDPGPU_VSENSE
SOC_VDDSOC_VSENSE
SPMU_AMUX_AY
SOC_VDDECPU_VSENSE
SPMU_AMUX_B<1>
WLANBT_3V3_ISENSE
SPMU_HS_ISENSE
SPMU_AMUX_BY
SPMU_RESET_IN
VSS_ANA_SPMU
SWD_NUB_SWCLK
SPMU_EXT32K_EN
D7
D6
C7
C6
A7
A6
A5
B8
B7
B6
E6
B10
A10
A9
A8
C8
D11
E11
B9
C10
B5
J4
H8
J8
F9
IREF
VREF
VREF_ADC
VSS_REF
TCAL
TDEV1
TDEV2
TDEV3
TDEV4
TDEV5
ADC_IN
AMUX_A<0>
AMUX_A<1>
AMUX_A<2>
AMUX_A<3>
AMUX_AY
AMUX_B<0>
AMUX_B<1>
AMUX_B<2>
AMUX_B<3>
AMUX_BY
DFT_CTRL_0
DFT_CTRL_1
EXT32K_EN
TDEV
AMUX
GPIO
SPMI_SCLK
SPMI_SDATA
SPMI
SGPIO_READY_REQ
SGPIO_SCLK
SGPIO_SDATA
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
UVWARN* RESET_IN
SCRASH*
NC_SPMU_GPIO1
K8
NC_SPMU_GPIO2
K7
SWD_NUB_PMU_SWDIO
J7
NC_SPMU_GPIO4
G7
NC_SPMU_GPIO5
F7
NC_SPMU_GPIO6
F6
NC_SPMU_GPIO7
H6
NC_SPMU_GPIO8
G6
NC_SPMU_GPIO9
J6
NC_SPMU_GPIO10
F5
NC_SPMU_GPIO11
H5
NC_SPMU_GPIO12
J5
NC_SPMU_GPIO13
G5
NC_SPMU_GPIO14
F4
NC_SPMU_GPIO15
F3
NC_SPMU_GPIO16
J9
SPMI_NUB_SPMU_CLK
H9
SPMI_NUB_SPMU_DATA
H3
SGPIO_SCLK
G3
SGPIO_SDATA
G8
VDD_MAIN_PRE_UVLO_L
G4
PMU_SCRASH_R_L
H4
PMU_SGPIO_READY_REQ
30
OUT
30
OUT
9 33
BI
30
OUT
30
OUT
30
OUT
30
OUT
30
OUT
30
OUT
30
OUT
30
OUT
30
OUT
30
OUT
30
OUT
30
OUT
30
OUT
18
IN
18
BI
33
IN
33
BI
29
R7904
5%1K1/20W
33
IN
PP1V8_AON_MPMU
102
35 34 33
<== FROM LDO9 POWER ALIAS
NOSTUFF
1
R7900
10K
5%
1/20W
MF
201
2
2 1
201 MF
<== IPU on Sera enabled.
PMU_SCRASH_L
33 91 33 91
BI
BI
R7920
10K
1/20W
201 201
1%
MF
1
R7902
2
30
10K
1%
1/20W
MF
SPMU_EXT32K_IN
IN
FORCE_SYNC
1
2
GND30 28
GND30
GND30
GND30
GND30
VSS_ANA_SPMU30
K9
EXT32K_IN
G9
FORCE_SYNC
F1
VSS_BSTLQ
E13
VSS_BUCK4
E14
VSS_BUCK4
A13
VSS_BUCK10
A14
VSS_BUCK10
N4
VSS_BUCK12_6
P4
VSS_BUCK12_6
J13
VSS_BUCK13_5
J14
VSS_BUCK13_5
F8
VSS_DFT_2
998-22526
OMIT_TABLE
U7700
TMLT47A1-JPE
WLCSP
SYM 4 OF 4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A4
A12
C5
C11
D12
E4
E5
E12
F2
F13
G2
G11
H2
J12
K1
K4
K5
K10
L2
L6
L10
L11
M4
VSS_ANA_SPMU 30 29
VSS_ANA_SPMU 29 27
VSS_ANA_SPMU 30 29
VSS_ANA_SPMU 29 27
VSS_ANA_SPMU
VSS_ANA_SPMU 30 29
VSS_ANA_SPMU
VSS_ANA_SPMU 30 29
VSS_ANA_SPMU 29 27
VSS_ANA_SPMU 30 29
VSS_ANA_SPMU 30 29 27
VSS_ANA_SPMU 30 29
VSS_ANA_SPMU 30 29 27
VSS_ANA_SPMU 30 29 27
VSS_ANA_SPMU 30 29 27
VSS_ANA_SPMU 30 29 27
VSS_ANA_SPMU 30 29 27
VSS_ANA_SPMU 30 29 27
Pulls
PP1V25_S2
R7 01
5% MF 1/20W
29 27
29 27
10K
2 1
VDD_MAIN_PRE_UVLO_L
201
102 28
<== FROM BUCK13 POWER ALIAS
29
NC TE CM TE E T M
PAGE TITLE
PMU: SLAVE GPIO & GND
BOM COST GROUP=PLATFORM POWER
Page 30
SLAVE PMU AMUX ALIAS
w w w . t e k n i s i - i n d o n e s i a . c o m
SLAVE PMU GPIOS SLAVE PMU PROBE POINTS
45
IN
45
IN
45 29
IN
45
IN
45
IN
46 29
IN
45 29
IN
SOC_VDDPCPU_VSENSE
MAKE_BASE=TRUE
NO_TEST=1
SOC_VSSPCPU_VSENSE
MAKE_BASE=TRUE
NO_TEST=1
SOC_VDDPGPU_VSENSE
MAKE_BASE=TRUE
NO_TEST=1
SOC VDDSOC_VSENSE
MAKE_BASE=TRUE
NO_TEST=1
SOC_VDDECPU_VSENSE
MAKE_BASE=TRUE
R8004
5% 1/20W
NO_TEST=1
2 1
1M
MF 201
WLANBT_3V3_ISENSE
MAKE_BASE=TRUE
NO_TEST=1
SPMU_HS_ISENSE
MAKE_BASE=TRUE
NO_TEST=1
SOC_VDDPCPU_VSENSE
SOC_VSSPCPU_VSENSE
SOC_VDDPGPU_VSENSE
SOC_VDDSOC_VSENSE
SOC_VDDECPU_VSENSE
SPMU_AMUX_B<1>
NO_TEST=1
WLANBT_3V3_ISENSE
SPMU_HS_ISENSE
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
29
29
29
29
VSS alias connection
GND
29
GND
29
GND
29
GND
29 28
GND
PP8001
NC_SPMU_GPIO1
29
NC_SPMU_GPIO2
9
29
NC_SPMU_GPIO4
29
NC_SPMU_GPIO5
29
NC_SPMU_GPIO6
29
NC_SPMU_GPIO7
29
NC_SPMU_GPIO8
29
NC_SPMU_GPIO9
29
NC_SPMU_GPIO10
29
NC_SPMU_GPIO11
29
NC_SPMU_GPIO12
29
NC_SPMU_GPIO13
29
NC_SPMU_GPIO14
29
NC_SPMU_GPIO15
29
NC_SPMU_GPIO16
29
NC_SPMU_GPIO1
MAKE_BASE=TRUE
NC_SPMU_GPIO2
MAKE_BASE=TRUE
NC_SPMU_GPIO4
MAKE_BASE=TRUE
NC_SPMU_GPIO5
MAKE_BASE=TRUE
NC_SPMU_GPIO6
MAKE_BASE=TRUE
NC_SPMU_GPIO7
MAKE_BASE=TRUE
NC_SPMU_GPIO8
MAKE_BASE=TRUE
NC_SPMU_GPIO9
MAKE_BASE=TRUE
NC_SPMU_GPIO10
MAKE_BASE=TRUE
NC_SPMU_GPIO11
MAKE_BASE=TRUE
NC_SPMU_GPIO12
MAKE_BASE=TRUE
NC_SPMU_GPIO13
MAKE_BASE=TRUE
NC_SPMU_GPIO14
MAKE_BASE=TRUE
NC_SPMU_GPIO15
MAKE_BASE=TRUE
NC_SPMU_GPIO16
MAKE_BASE=TRUE
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
P4MM
SM
1
PP8002
P4MM
SM
1
PP
PP8003
P4MM
SM
1
PP
2
IN
29
IN
SPMU_EXT32K_IN
NO_TEST=1
SPMU_ADC_IN
NO_TEST=1
SPMU_RESET_IN
SPMU_AMUX_AY
NO_TEST=1
SPMU_AMUX_BY
NO_TEST=1
R8001
5% 1/20W MF 201
R8002
R8003
2 1
2 1
2 1
100K
1M
MF 5% 1/20W 201
100K
MF 1/20W 5%
PP8004
PP8005
201
P4MM
1
P4MM
1
SM
PP
SM
PP
OUTPP
OUT
OUT
29
29
29
27
IN
27
IN
27
IN
27
IN
IN
27
IN
27
IN
28
IN PP
BUCK4_LX0
NO_TEST=1
BUCK4_LX1
NO_TEST=1
BUCK5_LX0
NO_TEST=1
BUCK6_LX0
NO_TEST=1
BUCK10_LX0
NO_TEST=1
BUCK12_LX0
NO_TEST=1
BUCK13_LX0
NO_TEST=1
SPMU_BSTLQ_LX
NO_TEST=1
PP8040
P4MM
SM
1
PP
PP8041
P4MM
SM
1
PP
PP8050
P4MM
SM
1
PP
PP8060
P4MM
SM
1
PP
PP80A0
P4MM
SM
1
PP
PP80C0
P4MM
SM
1
PP
PP80D0
P4MM
SM
1
PP
PP80E0
P4MM
SM
1
2 27
29
29 27
49 29
VSS_ANA_SPMU
29
VSS_ANA_SPMU
29
VSS_ANA_SPMU
VSS_ANA_SPMU
VSS_ANA_SPMU
VSS_ANA_SPMU
29
VSS_ANA_SPMU
VSS_ANA_SPMU
29
VSS_SPMU_AMUX
45 46
XW8000
SHORT-12L-0.25MM-SM
2 1
VSS_ANA_SPMU
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000
VOLTAGE=0
# & WIDTH XW IS LAYOUT DEPENDENT
2
XW8001
1
SHORT-12L-0.25MM-SM
2
XW8002
1
SH RT-12L-0.25MM-SM
CM TE E T M
PAGE TITLE
PMU: SLAVE SUPPORT
BOM_COST_GROUP=PLATFORM POWER
Page 31
MASTER PMU BUCKS
w w w . t e k n i s i - i n d o n e s i a . c o m
33 31
105 34
101
PP3V8_AON_MPMU_ISNS_VIN
1
C81C0
1UF
20%
10V
2
X6S-CERM
0201
1
C81C8
1UF 1UF
20%
10V
2
X6S-CERM
0201
1
C81F6
1UF
20%
10V
2
X S-CERM
0201
1
C81D4
10UF
20%
6.3V
2
CER-X6S
0402
1
2
1
2
1
2
1
2
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
1
C81DC
10UF
20%
6.3V
2
CER-X6S
0402
1
C81FA
12PF
5
25V
2
NP0-C0G
0201
PLACE_NEAR=U8100.B1:10MM PLACE_NEAR=U8100.F1:10MM
1
2
PLACE_NEAR=U8100.L1:10MM
FED BY SPMU BUCK13 (1.2V) =>
FED BY MPMU BUCK3 (1.8V) =>
PLACE_NEAR=U8100.B1:10MM
C81FJ
12PF
5%
25V
PLACE_NEAR=U8100.L1:10MM
FROM BUCK13 OR =>
1
2
1
2
1
2
OPTIONAL BUCK14
OMIT_TABLE
R8100
PPBUS_AON
1
103S00480
103S00481
103S00482
103S00385
103S0413
1
1
1
1
1
RES,TK,887KOHM,0.1%,1/20W,0201 CRITICAL
RES,MF,453KOHM,0.1%,1/20W,0201
RES,MF,910KOHM,0.1% 1/20W,0201
RES,MF,348KOHM,0.1%,1/ 0W,0201
RES,TK,887KOHM,0.1%,1/20W,0201
RES,MF,180KOHM,0.1%,1/20 0 1
887K
C81C1
1UF
20%
10V
X6S-CERM
02 1
C81C9
20%
10V
X6S-CERM
0201
C81F7
1UF
20%
10V
X6S-CERM
0201
1
C81C2
1UF
20% 20%
10V
2
X6S-CERM
0201
1
C81CA
1UF
20%
10V
2
X6S-CERM
0201 0201
1
C81F8
1UF
20%
10V
2
X6S-CERM
0201
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
1
32 33 34
31 44
101
C81D6
10UF
20%
6.3V
2
CER-X6S
1
C81F2
10UF
20%
6.3V
2
CER-X6S
0402
1
C81FC
5%
25V
2
NP0-C0G
0201 0201
1
C81FL
12PF
5%
25V
2
NP0-C0G
1
2
C81D5
10UF
2 %
6. V
CER X6S
0402 0402
C81DD
10UF
20%
6.3V
CER-X6S
0402
C81FB
3.0PF
+/-0.1 F
25V
NP0-C0G
C81FK
3 0PF
+/-0 1PF
25V
NP0-C0G NP0-C0G
0201 0201
PLAC _NEAR=U8100.R1:10MM
34
102
105 34 33 31
2 1
MPMU_SNS_DIV
0.1%
1/20W
TK
0201
1
C81C3
1UF 1UF
10V
2
X6S-CERM
0201
1
C81CB
1UF
20%
10V
2
X6S-CERM
1
C81C4
20%
10V
2
X6S-CERM
0201
1
C81CC
1UF
20%
10V
2
X6S-CERM
0201
CRITICAL
1
C81F9
1UF
20%
10V
2
X S-CE M CER-X6S
0201
1
C81D7
10UF
20%
6.3V
CER-X6S
0402
1
C81F3
10UF
20%
6.3V
2
CER-X6S
0402
1
C81FD
3.0PF 12PF
+ -0 1 F
25V
2
NP0 C0G
0201
PLACE_NEAR=U8100.F1:10MM
1
2
PLACE_NEAR=U8100.R1:10MM
PLACE_NEAR=U8100.K1:10MM
C81FM
+/-0.1PF
25V
NP0-C0G
0201 0201
PLACE_NEAR=U8100.W1:10MM
1
C81D0
10UF
20%
6.3V
2
0402
1
C81D8
10UF
20%
6.3V
2
CER-X6S
0402 0402
1
C81F4
10UF
20%
6.3V
2
CER-X6S
1
C81FE
12PF
5%
25V
2
NP0-C0G
0201 0201
1
C81FN
12PF
5%
25V
2
NP0-C0G
0201
PPVDD_P U_LDO_PREREG
PP1V5_VLDOINT_MPMU
PMU_VDD_HI
PP1V25_ 2
PP1V8_S2
CRITICAL
C8131
0.1UF
10%
10V
X6S-CERM
0201 0201
CRITICAL
1
C8 32
0.1UF
10%
10V
2
X6S-CERM
PP3V8_AON_MPMU_ISNS_VIN
1
1
R8101
453K
1%
1/20W
MF
201
2
3
OMIT_TABLE
REFERENCE DESIGNATOR(S) QTY DESCRIPTION PART#
R8100
R8101
R8100
R8101
R8100
R8101
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL PBUS_ 5 8VDCIN
1
C81CD
1UF
20%
10V
2
X6S-CERM
0201
1
C81D1
10UF
6.3V
2
C R-X6S
0402
1
C81D9
10UF 10UF
20%
6.3V
2
CER-X6S
1
C81F5
10UF
20%
6.3V
2
CER-X6S
0402
PLACE_NEAR=U8100.B15:10MM
1
C81FF
3.0PF
+ -0.1PF
25V
2
NP0-C0G
0201
PLACE_NEAR=U8100.K1:10MM
1
2
PLACE_NEAR=U8100.W1:10MM
PLACE_NEAR=U8100.A15:10MM
C81FP
3.0PF 3.0PF
+/-0.1PF
25V
NP0-C0G
0201
PLACE_NEAR=U8100.Y7:10MM
CRITICAL
1
C8 30
10UF
20%
6.3V
2
CER-X6S
0402
COINCELL BATTERY =>
105
34 32 31
U8110
NCS333ASQ3
SC70-5-COMBO
4
BOM OPTION CRITICAL
PBUS_3S103S00385
PBUS_3S
PBUS_12VDCIN
PBUS_12VDCIN
PBUS_15P8VDCIN
1
C81C6
1UF
20%
10V
2
X6S-CERM
02 1
1
C81E0
1UF
20%
10V
2
X6S-CERM
0201
1
C81C7
1UF
20%
10V
2
X6S-CERM
0201
1
C81E1
1UF
20%
10V
2
X6S-CERM
0201
CRITICAL CR TICAL CRITICAL
1
C81D2
10UF
20% 20%
6.3V
2
CER-X6
0402
1
C81DA
2 %
6. V
2
CER X6S
0402
1
C81F0
5%
25V
2
NP0-C0G
0201 0402
PLACE_NEAR=U8100.B15:10MM
1
C81FG
12PF
5%
25V
2
NP0-C0G
PLACE_NEAR=U8100.A15:10MM
1
C81FQ
12PF
5%
25V
2
NP0-C0G
0201
PLACE_NEAR=U8100.Y7:10MM
1
C81D3
10UF
20%
6.3V
2
CER-X6S
0402
1
C81DB
10UF
20%
6.3V
2
CER-X6S
0402
1
C81F1
3.0PF 12PF
+/-0.1PF
25V
2
NP0-C0G
0201
1
C81FH
3.0PF
+/-0.1PF
25V
2
NP0-C0G
0201
1
C81FR
3.0PF
+/-0.1PF
25V
2
NP0-C0G
0201
PP3V8_AON_MPMU_ISNS_VIN
VSS_ANA_MPMU
PLACE_NEAR=U8110.5:5MM
1
C8128
0 1UF
10%
6.3V
2
CERM-X5R
0201
PMU_VDD_HI
T BLE_5_HE D
T BLE_5_IT M
<== FOR 3S BATTERY
T BLE_5_IT M
T BLE_5_IT M
<== FOR 12V DCIN
T BLE_5_IT M
T BLE_5_IT M
<== FOR 15.8V DCIN
T BLE_5_IT M
OUT
31 44
L1
VDD_BUCK0_2_7_11
L2
VDD_BUCK0_2_7_11
L3
VDD_BUCK0_2_7_11
L4
VDD_BUCK0_2_7_11
R1
VDD_BUCK0_2_7_11
R2
VDD_BUCK0_2_7_11
R3
VDD_BUCK0_2_7_11
R4
VDD_BUCK0_2_7_11
W1
VDD_BUCK0_2_7_11
W2
VDD_BUCK0_2_7_11
W3
VDD_BUCK0_2_7_11
W4
VDD_BUCK0_2_7_11
W7
VDD_BUCK0_2_7_11
W11
VDD_BUCK0_2_7_11
W15
VDD_BUCK0_2_7_11
W19
VDD_BUCK0_2_7_11
Y7
VDD_BUCK0_2_7_11
Y11
VDD_BUCK0_2_7_11
Y15
VDD_BUCK0_2_7_11
Y19
VDD_BUCK0_2_7_11
A7
VDD_BUCK1_8_9
A11
VDD_BUCK1_8_9
B1
VDD_BUCK1_8_9
B2
VDD_BUCK1_8_9
B3
VDD_BUCK1_8_9
B4
VDD_BUCK1_8_9
B7
VDD_BUCK1_8_9
B11
VDD_BUCK1_8_9
F1
VDD_BUCK1_8_9
F2
VDD_BUCK1_8_9
F3
VDD_BUCK1_8_9
F4
VDD_BUCK1_8_9
K1
VDD_BUCK1_8_9
K2
VDD_BUCK1_8_9
K3
VDD_BUCK1_8_9
K4
VDD_BUCK1_8_9
A15
VDD_BUCK3_14
B15
VDD_BUCK3_14
K19
VDD_LDO2
L20
VDD_LDO3_14
K21
VDD_LDO5
J19
VDD_LDO19
C18
VDD_MAIN_WBOOST
F20
VDD_MAIN_WBOOST
F15
VDD_MAIN_WIDAC
K11
VDD_MAIN
V17
VDD_MAIN1
E19
VDD_MAIN_DRV
K10
VDD_MAIN_SNS
F19
VDD_MAIN_SNS_WLED
H8
VDD_BOOST_SNS
R16
VDDIO_1V2
N16
VDDIO_BUCK3
N20
VDD_RTC_ALT
K6
VPP
OMIT_TABLE
U8100
TMLT46B0-JPE
WLCSP
SYM 1 OF 6
BUCK0_LX0
BUCK0_LX0
BUCK0_LX1
BUCK0_LX1
BUCK0_LX1
BUCK0_LX1
BUCK0_LX2
BUCK0_LX2
BUCK0_LX2
BUCK0_LX2
BUCK0_LX3
BUCK0_LX3
BUCK0_LX3
BUCK0_LX3
BUCK0_LX4
BUCK0_LX4
BUCK0_LX4
BUCK0_LX4
BUCK0_FB
BUCK0_VSS_FB
BUCK1_LX0
BUCK1_LX0
BUCK1_LX1
BUCK1_LX1
BUCK1_LX1
BUCK1_LX1
BUCK1_LX2
BUCK1_LX2
BUCK1_LX2
BUC 1_LX2
BUCK1_LX3
BUCK1_LX3
BUCK1_LX3
BUCK1_LX3
BUCK1_LX4
BUC 1_LX4
BUCK1_LX4
BUCK1_LX4
BUCK1_FB
BUCK1_VSS_FB
BUCK2_LX0
BUCK2_LX1
BUCK2_LX1
BUCK2_LX2
BUCK2_LX2
BUCK2_FB
BUCK2_VSS FB
W6
Y6
V1
V2
V3
V4
P1
P2
P3
P4
T1
T2
T3
T4
M1
M2
M3
M4
U6
T6
A6
B6
C1
C2
C3
C4
G1
G2
G3
G4
E1
E2
E3
E4
J1
J2
J3
J4
D6
E6
Y20
18
Y18
W16
Y16
V20
U20
34
OUT
BUCK0_LX0
DIDT=TRUE
SWITCH_NODE=TRUE
34
OUT
BUCK0_LX1
DIDT=TRUE
SWITCH_NODE=TRUE
34
OUT
BUCK0_LX2
DIDT=TRUE
SWITCH_NODE=TRUE
34
OUT
BUCK0_LX3
DIDT=TRUE
SWITCH_NODE=TRUE
34
OUT
BUCK0_LX4
DIDT=TRUE
SWITCH_NODE=TRUE
BUCK0_FB
PLACE_NEAR=U8100.U6:15MM
VSS_ANA_MPMU
34
OUT
BUCK1_LX0
DIDT=TRUE
SWITCH_NODE=TRUE
34
OUT
BUCK1_LX1
DIDT=TRUE
SWITCH_NODE=TRUE
34
OUT
BUCK1_LX2
DIDT=TRUE
SWITCH_NODE=TRUE
34
OUT
BUCK1_LX3
DIDT=TRUE
SWITCH_NODE=TRUE
34
OUT
BUCK1_LX4
DIDT=TRUE
SWITCH_NODE=TRUE
BUCK1_FB
PLACE_NEAR=U8100.D6:15MM
VSS_ANA_MPMU
BUCK2_LX0
34
DIDT=TRUE
SWITCH_NODE=TRUE
BUCK2_LX1
34
DIDT=TRUE
SWITCH_NODE=TRUE
BUCK2_LX2
34
DIDT=TRUE
SWITCH_NODE=TRUE
BUCK2_FB
PLACE_N AR=U8100.V20:15MM
VSS_ANA_MPMU
R810A
1/20W 5%
R810B
R810C
5% 1/20W
L8100
1.0UH-20%-4A-0.038OHM
CRITICAL
2 1
PIKA20161B-COMBO
L8101
0.1UH-20%-10.3A-0.01OHM
PCCE20161B-SM
1
2
152S01268
CRITICAL
3
4
L8102
0.1UH-20%-10.3A-0.01OHM
PCCE20161B-SM
1
2
152S01268
CRITICAL
3
4
XW8100
0
2 1
BUCK0_FB_R
0201
MF
34 32 31
SHORT-14L-0.1MM-SM
NO_XNET_CONNECTION=1
L8110
1.0UH-20%-4A-0.038OHM
CRITICAL
2 1
PIKA20161B-COMBO
L8111
0.1UH-20%-10.3A-0.01OHM
PCCE20161B-SM
1
2
152S01268
CRITICAL
3
4
L8112
0.1UH-20%-10.3A-0.01OHM
PCCE20161B-SM
1
2
152S01268
CRITICAL
3
4
XW8110
SHORT-14L-0.1MM-SM
2 1
BUCK1_FB_R
0201 MF 5%01/20W
34 32
NO_XNET_CONNECTION=1
L8120
1.0UH-20%-4A-0.038OHM
CRITICAL
2 1
PIKA20161B-COMBO
L8121
0.1UH-20%-10.3A-0.01OHM
PCCE20161B-SM
1
2
152S01268
0
2 1
MF
BUCK2_FB_R
0201
34 33 32
NO_XNET_CONNECTION=1
CRITICAL
3
4
XW8120
SHORT-14L-0.1MM-SM
2 1
PPVDD_PCPU_AWAKE
CRITICAL
1
C8100
15UF
20%
2
X6S
0402
CRITICAL
1
C810B
15UF
20%
2V
2
X6S
0402
CRITICAL
1
C810F
2.2UF
20%
4V
2
X6S-CERM
0201
PLACE_SIDE=TOP
PLACE_NEAR=U8100 5MM
2 1
CRITICAL CRITICAL
1
C8101
20
2V 2V
2
X6S
0402 0402
CRITICAL
1
C810C
15UF
20%
2V
2
X6S
0402
1
C8102
20%
2V
2
X6S
0402
CRITICAL
1
C810D
15UF
20%
2V
2
X6S
1
C8103
20%
2V
2
X6S
0402
CRITICAL
1
C810E
15UF
20%
2V
2
X6S
0402 0402
PLACE_NEAR=L81 0.2:5MM
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
1
C8104
2V
2
X6S
0402
1
C81H0
12PF
5%
25V
2
NP0-C0G
0201
PLAC _NEAR=L8100.2:5MM
CRITICAL
1
C810G
2.2UF
20%
4V
2
X6S-CERM
0201
PLACE_SIDE=TOP
PLACE_NEAR=U8100:5MM
1
C8105
15UF 15UF 15UF 15UF 15UF
20% 20%
2V
2
X6S
1
C81H1
3.0PF
+/-0.1PF
25V
2
NP0-C0G
0201
1
C8109
15UF
20
2V
2
X6S
0402
1
C81H2
12PF
5%
25V
2
NP0-C0G
0201
PLA E_NEAR=L8101.4:5MM
PLACE_NEAR=L8101.3:5MM
1
2
1
2
C810A
15UF
20%
2V
X6S
0402
C81H3
3.0PF
+/-0.1PF
25V
NP0-C0G
0201
PPVDD_GPU_AWAKE
CRITICAL
1
C8110
15UF
20%
2V
2
X6S
0402
MIRROR_WITH=C8111
CRITICAL
1
C8119
15UF
20%
2V
2
X6S
0402
1
C81H6
12PF
5%
25V
2
NP0-C0G
0201
PLACE_NEAR=L8111.3:5MM
2 1
PLACE_NEAR=L8111.4:5MM
NOSTUFF
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
1
C8111
15UF
20%
2V
2
X6S
0402
1
C8112
15UF
20%
2V
2
X6S
0402
1
C8113
15UF
20%
2V
2
X6S
0402
1
C8114
15UF
20%
2V
2
X6S
0402
1
C8115
15UF
2V
2
X6S
0402
1
C8116
15UF
20% 20%
2V
2
0402
1
C8117
15UF
20%
2V
2
X6S X6S
0402
MIRROR WITH=C8117 MIRROR WITH=C8115 MIRROR_WITH=C8113
CRITICAL
1
C811A
15UF
20%
2V
2
X6S
0402
1
C81H7
3 0PF
+/-0 1PF
25V
2
NP0-C0G
0201
CRITICAL
1
C811B
15UF
20%
2V
2
X6S
0402
CRITICAL
1
C811C
15UF
20%
2V
2
X6S
0402
MIRROR_ ITH=C811C
CRITICAL
1
C811F
2.2UF
20%
4V
2
X6S-CERM
0201
PLACE_SIDE=TOP
PLACE_NEAR=U8100:5MM
CRITICAL
1
C811G
2.2UF
20%
4V
2
X6S-CERM
0201
PLACE_SIDE=TOP
PLACE_NEAR=U8100:5MM
1
2
MIRROR_WITH=C811E MIRROR_WITH=C811A
CRITICAL
C811D
15UF
20%
2V
X6S
0402
CRITICAL
1
C811E
15UF
20%
2V
2
X6S
0402
1
C81H4
12PF
5%
25V
2
NP0-C0G
0201 0201
PLACE_NEAR=L8110.2:5MM
PLACE_NEAR=L811 .2:5MM
1
2
C81H5
3.0PF
+/-0.1PF
25V
NP0-C0G
PPVDD_SOC_S1
101
101 34
101
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
1
C8120
15UF
20%
2V
2
X6S
0402
1
C81H8
12PF
5%
25V
2
NP0-C0G
0201
PLACE_NEAR=L8120.2:5MM
PLACE_NEAR=L8120.2:5MM
1
2
1
2
C8121
15UF
20%
2V
X6S
0402
C81H9
3.0PF
+/-0.1PF
25V
NP0-C0G
0201
1
C8122
15UF
20%
2V
2
X6S
0402
CRITICAL
1
C812A
2.2UF
20%
4V
2
X6S-CERM
0201
PLACE_SIDE=TOP
PLACE_NEAR=U8100:5MM
1
C8123
15UF
20%
2V
2
X6S
0402
CRITICAL
1
C812B
2.2UF
20%
4V
2
X6S-CERM
0201
PLACE_SIDE=TOP
PLACE_NEAR=U8100:5MM
1
C8124
15UF
20%
2V
2
X6S
0402
PAGE TITLE
1
C8125
15UF
20%
2V
2
X6S
0402
1
C8126
15UF
2V
2
X6S
0402
1
C8127
15UF
20% 20%
2V
2
X6S
0402
NC TE CM TE E T M
PMU: MASTER INPUT PWR & BUCKS
BOM_COST_GROUP=PLATFORM POWER
Page 32
MASTER PMU BUCKS & GND
w w w . t e k n i s i - i n d o n e s i a . c o m
OMIT_TABLE
U8100
TMLT46B0-JPE
WLCSP
SYM 6 OF 6
GND
34
GND
34
GND
34
GND
34
GND
34
GND
34
GND
34
GND
34
GND
33
34
34
VSS_ANA_MPMU
32
33
49
VSS_ANA_MPMU
34
N1
VSS_BUCK0
N2
VSS_BUCK0
N3
VSS_BUCK0
N4
VSS_BUCK0
U1
VSS_BUCK0
U2
VSS_BUCK0
U3
VS _BUCK0
U4
VSS_BUCK0
W5
VSS_BUCK0
Y1
VSS_BUCK0
Y2
VSS_BUCK0
Y3
VSS_BUCK0
Y4
VSS_BUCK0
Y5
VSS_BUCK0
A1
VSS_BUCK1
A2
VSS_BUCK1
A3
VSS_BUCK1
A4
VSS_BUCK1
A5
VSS_BUCK1
B5
VSS_BUCK1
D1
VSS_BUCK1
D2
VSS_BUCK1
D3
VSS_BUCK1
D4
VSS_BUCK1
H1
VSS_BUCK1
H2
VSS_BUCK1
H3
VSS_BUCK1
H4
VSS_BUCK1
W17
VSS_BUCK2
W21
VSS_BUCK2
W22
VSS_BUCK2
Y17
VSS_BUCK2
Y21
VSS_BUCK2
Y22
VSS_BUCK2
A17
VSS_BUCK3
B17
VSS_BUCK3
W13
VSS_BUCK7
Y13
VSS_BUCK7
A9
VSS_BUCK8
B9
VSS_BUCK8
A13
VSS_BUCK9_14
B13
VSS_BUCK9_14
W9
VSS_BUCK11
Y9
VSS_BUCK11
V22
VSS_BSTLQ
A21
VSS_WLED_LP
A22
VSS_WLED_LP
B21
VSS_WLED_LP
B22
VSS_WLED_LP
A20
VSS_WLED_HP1
B20
VSS_WLED_HP1
C20
VSS_WLED_HP1
D21
VSS_WLED_HP2
D22
VSS_WLED_HP2
J11
VS _REF
K7
VSS_DFT_2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A18
B8
B18
C5
C6
C9
C10
C13
C17
D5
D7
D10
D11
D15
D18
D19
D20
E5
E7
E15
E17
E20
F6
F16
F17
F21
F22
G5
G6
G15
G18
H5
H6
H15
H18
J5
J6
J13
J17
J18
K15
K18
L6
L7
L8
L9
L10
L11
L12
L15
M5
N5
N18
N22
P5
P7
R18
T5
T18
U5
U19
V5
V6
V9
V10
V13
V14
V16
V18
V21
W8
W12
W20
VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_M MU
VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU
MPMU_VREF
PP1V8_S2
CRITICAL
1
C8230
10UF
OMIT_TABLE
U8100
TMLT46B0-JPE
WLCSP
SYM 2 OF 6
MPMU_ADC_IN
3
PP1V5_VLDOINT_MPMU
31 33 34
34 32
34 33 32
34 32
34 32 31
34 33 32
34 32
34 32 31
34 33 32
34 32
34 32 31
34 33 32
34 32
34 32 31
34 32
34 32 31
34 33 32
34 32 31
34 33 32
34 32 31
34 32
PLACE_NEAR=U8100.C15:5MM
1
C8206
0.1UF
10%
10V
2
X6S-CERM
0201
32
34
IN
34
IN
32
MPMU_VREF
MPMU_VBAT
MPMU_IBAT
MPMU_IREF
K9
C7
C11
C15
F5
F18
J15
K5
K8
L5
P18
R5
V7
V11
V15
V19
D9
E16
J7
M18
P9
R17
K12
J10
J9
J8
ADC_IN
VDD_ANA
VDD_ANA
VDD_ANA
VDD_ANA
VDD_ANA
VDD_ANA
VDD_ANA
VDD_ANA
VDD_ANA
VDD_ANA
VDD_ANA
VDD_ANA
VDD_ANA
VDD_ANA
VDD_ANA
VDD_DIG
VDD_DIG
VDD_DIG
VDD_DIG
VDD_DIG
VDD_DIG
VREF
VBAT
IBAT
IREF
BUCK3_LX
BUCK3_LX
BUCK3_FB
BUCK3_VSS_FB
BUCK7_LX0
BUCK7_LX1
BUCK7_LX1
BUCK7_FB
BUCK7_VSS_FB
BUCK8_LX0
BUCK8_LX1
BUCK8_LX1
BUCK8_FB
BUCK8_VSS_FB
BUCK9_LX
BUCK9_LX
BUCK9_FB
BUCK9_VSS_FB
A16
B16
D16
C16
Y12
W14
Y14
U12
V12
A8
A10
B10
D8
C8
A12
B12
D12
C12
BUCK3_LX0
BUCK3_FB
VSS_ANA_MPMU
BUCK7_LX0
DIDT=TRUE
SWITCH_NODE=TRUE
BUCK7_LX
DIDT=TRUE
SWITCH_NODE=TRUE
BUCK7_FB
VSS_ANA_MPMU
BUCK8_LX0
DIDT=TRUE
SWITCH_NODE=TRUE
BUCK8_LX1
DIDT=TRUE
SWITCH_NODE=TRUE
BUCK8_FB
VSS_ANA_MPMU
BUCK9_LX0
DIDT=TRUE
SWITCH_NODE=TRUE
BUCK9_FB
VSS_ANA_MPMU
34 33 32
34 32 31
BUCK11_LX0
BUCK11_LX1
BUCK11_LX1
Y8
W10
Y10
BUCK11_LX0
DIDT=TRUE
SWITCH_NODE=TRUE
BUCK11_LX1
DIDT=TRUE
SWITCH_N DE=TRUE
34
OUT
DIDT=TRUE
SWITCH_NODE=TRUE
R820A
1/20W 5%
0.22UH-20% 6.7A-0.023OHM
OUT
OUT
PLACE_NEAR=U8100.D16:15MM
34
34
R820B
0
5% 0201
PLACE_NEAR=U8100.U12:15MM
34
OUT
OUT
34
0.22UH-20%-6.7A-0.023OHM
R820C
0
PLACE_NEAR=U8100.D8:15MM
34
OUT
1/20W MF 5% 0201
R820D
0
1/20W
5% 0201
PLACE_NEAR=U8100.D12:15MM
34
OUT
OUT
34
0.22UH-20%-6.7A-0.023OHM
0.47UH-20%-4A-0.027OHM
0
2 1
MF
1.0UH-20%-4A-0.038OHM
2 1
MF 1/20W
1.0UH-20%-4A-0.038OHM
2 1
BUCK8_FB_R
0.47UH-20%-4A-0.027OHM
2 1
BUCK9_FB_R
MF
1.0UH-20%-4A 0 038OHM
R820E
34 32
34 33 32
BUCK11_FB
BUCK11_VSS_FB
U8
V8
BUCK11_FB
PLACE_NE R=U8100.U8:15MM
VSS_ANA_MPMU
34 32 31
33 32 31
34
34 32 31
34 33 32 31
34 32 31
34 33 32 31
34 32 31
34 33 32 31
PP1V8_S2
34 32 31
34 32
101
FROM BUCVK3 =>
PP1V25_S2102 32
FROM BUCK13 =>
34 33 32 31
34 32
R21
R22
T20
R19
R20
VDD_SW1
VDD_SW1
VDD_SW2
VDD_SW3
VDD_SW3
SWITCHED RAILS
BUCK14_LX
BUCK14_LX
BUCK14_FB
BUCK14_VSS FB
BUCK_SW1
BUCK_SW1
BUCK_SW2
BUCK_SW3
BUCK_SW3
Decoupling: VDD_SW3
34 32
34 32
PP1V25_S2
102 32
A14
B14
D14
C14
P21
P22
T19
P19
P20
BUCK14_LX
BUCK14_FB_MPMU
VSS_ANA_MPMU
PP1V8_AWAKE
NC_MPMU_BUCK_SW2
PP1V25_AWAKE_IO
Decoupling:BUCK_SW1
PP1V8_AWAKE
CRITICAL
1
C8201
10UF
20%
32
6.3V
2
CER-X6S
0402
1
2
0
2 1
BUCK11_FB_R
1/20W 5% 0201
MF
34 32
CRITICAL
C8202
10UF
20%
6.3V
CER-X6S
0402
L8230
2 1
2012
BUCK3_FB_
0201
34 32
L8270
2 1
PIKA20161B-COMBO
L8271
2
PINA20121T-SM
BUCK7_FB_R
34 32
L8280
2 1
PIKA20161B CO BO
L8281
2 1
PINA20121T-SM
34 33 32
L8290
2 1
2012
34 33 32
L82B0
2 1
PIKA20161B-COMBO
L82B1
2 1
PINA20121T-SM
NO_TEST=1
CRITICAL
1
C8203
10UF
20%
6.3V
2
CER-X6S
0402
CRITICAL
XW8230
SHORT-14L-0.1MM-SM
2 1
NO_XNET_CONNECTION=1
CRITICAL
CRITICAL
XW8270
SHORT-14L-0.1MM-SM
2 1
NO_XNET_CONNECTION=1
PLACE_NEAR=L8270.1:5MM
CRITICAL
CRITICAL
XW8280
SHORT-14L-0.1MM-SM
2 1
NO_XNET_CONNECTION=1
CRITICAL
XW8290
SHORT-14L-0.1MM-SM
2 1
NO_XNET_CONNECTION=1
CRITICAL
CRITICAL
XW82B0
SHORT-14L-0.1MM-SM
2 1
NO_XNET_CONNECTION=1
PLACE_NEAR=L82B0.1:5MM
34
34
34 33 32
VIN FROM BUCK13 IS POR FOR LDO3, 8, 20. IF PDN (VMIN VIOLATION, WHEN LDO8 IN DROPOUT MODE)
32
IS AN ISSUE THEN BUCK14 WILL BE THE BACKUP OPTION. THIS WOULD THEN REQUIRE ADDING BEAD AND CAPS
102
102 32
102 32
20%
6.3V
2
CER-X6S
0402
CRITICAL
1
C8236
10UF
20%
6.3V
2
CER-X6S
0402
NOSTUFF
CRITICAL
1
C8270
15UF
20%
2V
2
X6S
0402
1
C82D2
12PF
5%
25V
2
NP0-C0G
0201
PLACE_NEAR=L82 .1:5MM
CRITICAL
1
C8280
15UF
20%
2V
2
X6S
0402
CRITICAL
1
C8286
2.2UF
20%
4V
2
X6S-CERM
0201
PLACE_SIDE=TOP
PLACE_NEAR=U8100:5MM
CRITICAL
1
C8290
15UF
20%
2V
2
X6S
0402
NOSTUFF
CRITICAL
1
C82B1
15UF
20%
2V
2
X6S
0402
1
C82D8
12PF
5%
25V
2
NP0-C0G
0201
PLACE_NEAR=L82B1.1:5MM
CRITICAL
1
C8231
10UF
20%
6.3V
2
CER-X6S
0402
CRITICAL
1
C8237
10UF
20%
6.3V
2
C R-X6
0402
NOSTUFF
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
1
C8271
15UF
20%
2V
2
X6S
0402
1
C82D3
3.0PF
+/-0.1PF
25V
2
NP0-C0G
0201
CRITICAL CRITICAL CRITICAL
1
C8281
15UF
20%
2V
2
X6S
0402
CRITICAL
1
C8287
2.2UF
20%
4V
2
X S-CE M
0201
CRITICAL
1
C8291
15UF
20%
2V
X6S
0402
NOSTUFF
CRITICAL
1
C82B2
15UF
20%
2V
2
X6S
0402
1
C82D9
3.0 F
+/-0 1PF
25V
2
NP0-C0G
0201
CRITICAL
1
C8232
10UF 10UF
20%
6.3V
2
CER-X6S
0402
CRITICAL
1
C8238
10UF
20%
6.3V
2
CER-X6S
0402
CRITICAL
1
C8233
20%
6.3V
2
CER-X6S
0402
CRITICAL
1
C8239
10UF
20%
6.3V
2
C R-X6S
0402
CRITICAL
1
C8234
10UF
20%
6.3V
2
CER-X6S
0402
CR TICAL
1
C823A
10UF
20%
6.3V
2
CER-X6
0402
CRITICAL
1
C8272
15UF
20%
2V
2
X6S
0402
CRITICAL
1
C8278
2.2UF
20%
4V
2
X6S-CERM
0201
PLACE_SIDE=TOP
PLACE_NEAR U8100:5MM
1
C8273
15UF
20%
2V
2
X6S
0402
1
C8274
15UF
20%
2V
2
X6S
0402
CRITICAL
1
C8279
2.2UF
20%
4V
2
X6S-CERM
0201
PLACE_SIDE=TOP
PLACE_NEAR=U8100:5MM
CRITICAL
1
C8282
15UF
20%
2V
2
X6S
0402
PLACE_SIDE=TOP
PLACE_NEAR=U8100:5MM
CRITICAL
1
C8292
15UF
20%
2V
2
X6S
0402
CRITICAL
1
C82B3
15UF
20%
2V
2
X6S
0402
CRITICAL
1
C82BA
2.2UF
20%
4V
2
X6S-CERM
0201
PLACE_SIDE=TOP
PLACE_NEAR=U8100:5MM PLACE_NEAR=U8100:5MM
1
C8283
15UF
20%
2V
2
X6S
0402
CRITICAL
1
C8293
15UF
20%
2V
2
X6S
0402
CRITICAL
1
C82B4
15UF
20%
2V
2
X6S
0402
CRITICAL
1
C82BB
2.2UF
2 %
4V
2
X6S-CERM
0201
1
C8284
15UF
20%
2V
2
X6S
0402
CRITICAL
1
C8294
15UF
2 %
2V
2
X6S
0402
CRITICAL
1
C82B6
15UF
20%
2V
2
X6S
04 2
PLACE_SIDE=TOP
CRITICAL
1
C8235
10UF
20%
6.3V
2
CER-X6S
0402
CRITICAL
1
C823B
10UF
20%
6.3V
2
CER-X6S
0402
1
C8275
15UF
20%
2V
2
X6S
0402
CRITICAL
1
C8285
15UF
20%
2V
2
X6S
0402
PLACE_NEAR=L8280.1:5MM
CRITICAL
1
C8295
15UF
20%
2V
2
X6S
0402
PLACE_NEAR L8290.1:5MM
CRITICAL
1
C82B7
15UF
20%
2V
2
X6S
0402
1
C82D0
12PF
5%
25V
2
NP0-C0G
0201
PLACE_NEAR=L8230.1:5MM
1
C82D1
3.0PF
+/-0.1PF
25V
2
NP0-C0G
0201
PLACE_NEAR=L8230.1:5MM
PPVDD_CPU_SRAM_AWAKE
1
C8276
15UF
20%
2V
2
X6S
0402
1
C8277
15UF
20%
2V
2
X6S
0402
PPVDD_DISP_S1
1
C82D4
12PF
5%
25V
2
NP0-C0G
0201
PLACE_NEAR=L8281.1:5MM
1
C82D5
3.0PF
+/-0.1PF
25V
2
NP0-C0G
0201
PPVDD_DCS_S1
1
C82D6
12PF
5%
25V
NP0-C0G
0201
P ACE_NEAR=L8290.1:5MM
1
C82D7
3.0PF
+/-0.1PF
25V
2
NP0-C0G
0201
PPVDD_ECPU_AWAKE
CRITICAL
1
C82B8
15UF
20%
2V
2
X6S
0402
CRITICAL
1
C82B9
15UF
20%
2V
2
X6S
0402
01
D
101
101
C
101
101
49 34 33 32
VSS_ANA_MPMU
PLACEMENT NOTE:
CONNECT VSS_REF THROUGH ALL GND PLANES PLACE XW AT VSS_REF PIN, ROUTE VSS_RTN
BACK FROM THE VREF / IREF PASSIVES
XW82B2
SHORT-14L-0.1MM-SM
2 1
MPMU_VREF_IREF_RTN
1
C8204
1.5UF
20%
6.3V
2
CER-X5R
0201
MPMU_IREF
1
R8201
200K
0.1%
1/20W
TF
0201
2
NOSTUFF
1
C8205
0.1UF
10%
6.3V
2
CERM-X5R
0201
32
PAGE TITLE
Decoupling: BUCK_SW3
PP1V25_AWAKE_IO
CRITICAL
1
C8240
15UF
20%
2V
2
X6S
0402
CRITICAL
1
C8241
15UF
20%
2V
2
X6S
0402
102 32
PMU: MASTER BUCKS & GND
A
NC TE CM TE E T M
BOM_COST_GROUP=PLATFORM POWER
2
1
Page 33
OMIT_TABLE
w w w . t e k n i s i - i n d o n e s i a . c o m
MASTER PMU LDO,ADC, & GPIO
34
PP3V8_AON_MPMU_ISNS_VIN
31
33
105
1
C83A0
12PF
5%
25V
2
NP0-C0G
PLACE_NEAR=L8300.1:5MM
CRITICAL
1
C8300
20UF
20%
10V
2
X5R
0402
1
C83A2
12PF
5%
25V
2
0201
105 34 33 31
PP3V8_AON_MPMU_ISNS_VIN
LDO1 NOT USED ==>
THIS IS AN OUTPUT ==>
THIS IS AN OUTPUT ==>
DECOUPLING: LDORTC KEEP AS NOSTUFF FOR P1
PP1V5_VLDOINT_MPMU
CRITICAL
1
C8326
1.0UF
20%
6.3V
2
X5R
0201-1
BOMOPTION=DESKTOP_COINCELL
CRITICAL
1
C8327
1.0UF
20%
6.3V
2
X5R
0201-1
BOMOPTION=DESKTOP_COINCELL
0.47UH-20%-1.7A-0.175OHM
1
C83A1
3.0PF
+/-0.1PF
25V
2
NP0-C0G
0201 0201
PLACE_NEAR=L8300.1:5MM
CRITICAL
1
C8301
20UF
20%
10V
2
X5R
0402
1
C83A3
3.0PF
+/-0.1PF
25V
2
NP0-C0G NP0-C0G
0201
CRITICAL
1
C8314
10UF
20%
6.3V
2
CER-X6S
0402
NC_MPMU_LDO1_EN
34
PP1V5_VLDOINT_MPMU
31 32 33 34
VOLTAGE=1.5V
34 33
PP1V5_VLDOINT_MPMU
34 33
CRITICAL
L8300
0402-COMBO
VOLTAGE=5V
34 33 31
CRITICAL
1
C8302
0.1UF
10%
10V
2
X6S-CERM
0201
GND
PP3V8_AON_MPMU_ISNS_VIN
105
XW83D0
SHORT-12L-0 25MM SM
CRITICAL
1
C8315
10UF
20%
6.3V
2
CER-X6S
0402
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
2 1
2 1
VOLTAGE=5V
PLACE_NEAR=U8100.T21:5MM
34 32
NC_MPMU_IDAC_OUT<0>
NC_MPMU_IDAC_OUT<1>
NC_MPMU_IDAC_OUT<2>
NC_MPMU_IDAC_OUT<3>
NC_MPMU_IDAC_OUT<4>
NC_MPMU_IDAC_OUT<5>
NC_MPMU_IDAC_OUT<6>
NC_MPMU_IDAC_OUT<7>
NC_MPMU_IDAC_OUT<8>
NC_MPMU_IDAC_OUT<9>
NC_MPMU_IDAC_OUT<10>
NC_MPMU_IDAC_OUT<11>
NC_MPMU_IDAC_OUT<12>
NC_MPMU_IDAC_OUT<13>
NC_MPMU_IDAC_OUT<14>
NC_MPMU_IDAC_OUT<15>
NC_MPMU_IDAC_OUT<16>
NC_MPMU_IDAC_OUT<17>
MPMU_BSTLQ_LX
34
SWITCH_NODE=TRUE
DIDT=TRUE
PP5V_BSTLQ_VOUT_MPMU
PP5V_BSTLQ_MPMU
CRITICAL
1
C8310
0.1UF
10%
10V
2
0201
CRITICAL
1
C8316
0.1UF
10%
10V
2
X6S-CERM
0201 0201
PLACE_NEAR=U8100.D17:5MM
CRITICAL
1
C8311
0.1UF
10%
10V
2
X6S-CERM X6S-CERM
0201
PLACE_NEAR=U8100.L18:5MM
CRITICAL
1
C8317
0.1UF
10%
10V
2
X6S-CERM
PLACE_NEAR=U8100.H12:5MM PLACE_NEAR=U8100.T22:5MM
OMIT_TABLE
U8100
TMLT46B0-JPE
WLCSP
SYM 3 OF 6
G19
VDD_BOOST_LDO
G21
VDD_BOOST_LDO
H19
VDD_BOOST_LDO
H21
VDD_BOOST_LDO
J21
VDD_BOOST_LDO
M20
VDD_MAIN_LDO
N17
LDO1_EN
M21
VLDOINT
N21
VLDORTC
G17
G16
G14
G13
H17
H16
H14
H13
J16
J14
K17
K16
K14
K13
L17
L16
L14
L13
U22
T22
H9
H10
T21
H11
D13
D17
H12
L18
VLDO1
VLDO2
VLDO3
VLDO5
VLDO7
VLDO9
VLDO10
VLDO13
VLDO14
VLDO16
VLDO19
VREF_ADC
OMIT_TABLE
TMLT46B0-JPE
IDAC_OUT<0>
IDAC_OUT<1>
IDAC_OUT<2>
IDAC_OUT<3>
IDAC_OUT<4>
IDAC_OUT<5>
IDAC_OUT<6>
IDAC_OUT<7>
IDAC_OUT<8>
IDAC_OUT<9>
IDAC_OUT<10>
IDAC_OUT<11>
IDAC_OUT<12>
IDAC_OUT<13>
IDAC_OUT<14>
IDA _O T 15>
IDAC_OUT<16>
IDAC_OUT<17>
BSTLQ_LX
BSTLQ_VOUT
VDD_BOOST
VDD_SNS_SPARE
VDD_HI_INT1
VDD_HI_INT2
VDD_HI_INT3
VDD_HI_INT4
VDD_HI_INT5
VDD_HI_INT6
J22
K20
L21
K22
H22
M19
G20
H20
L19
G22
J20
H7
NC_MPMU_VLDO1
NC_MPMU_VLDO2
PP1V2_S2
NC_MPMU_VLDO5
PP3V3_S2_UPC
PP1V8_AON_MPMU
NC_MPMU_VLDO10
NC_MPMU_VLDO13
NC_MPMU_VLDO14
NC_MPMU_VLDO16
NC_MPMU_VLDO19
MPMU_VREF_ADC
U8100
WLCSP
SYM 5 OF 6
WLED_LP_LX
WLED_LP_LX
WLED_HP1_LX
WLED_HP1_LX
WLED_HP1_LX
WLED_HP2_LX
WLED_HP2_LX
WLED_VOUT_FB
VCP_OUT_SPARE
VMBX_SPARE
NO_TEST=1
NO_TEST=1
C21
C22
A19
B19
C19
E21
E22
E18
U21
J12
NC_MPMU_WLED_LP_LX_0
NC_MPMU_WLED_LP_LX_1
NC_MPMU_WLED_HP1_LX_0
NC_MPMU_WLED_HP1_LX_1
NC_MPMU_WLED_HP1_LX_2
NC_MPMU_WLED_HP2_LX_0
NC_MPMU_WLED_HP2_LX_1
NC_MPMU_WLED_VOUT_FB
NC_MPMU_VCP_OUT_SPARE
NC_MPMU_VMBX_SPARE
102 35 34 33 29
FEED BY PP1V8_AON (LDO9) ==>
102
102 33
102
102 33
102 33
102
103
103
103
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
PP1V8_AON_MPMU
NXTAL_MEMS=0 ==> XTAL
R8326
5%
103S00511
CRITICAL
R8320
VSS_ANA_MPMU
34
R8321
1K
2 1
1%
1/20W
MF
201
100K
1/20W
MF
2 1
201
49
IN
49
IN
49
IN
9
IN
49
IN
49
IN
49
IN
49
IN
2
3.92K
0.1%
0201-2
1/20W
MF
1
33 34 80 89 90
IN
33 34 82 89 90
IN
34
IN
34
IN
9 100
IN
3
IN
6 89 91 96 100
IN
MPMU_VBUS_DET
34 32
89 90
IPD >>
34 32 31
33
33
3
IN
3
IN
34
IN
34
N
34
OUT
34
IN
34
IN
34
IN
34
IN
34
OUT
WLBT_PWR_EN
NOSTUFF
P3V8AONVR_THMSNS
SOC_THMSNS1
SOC_THMSNS3
NC_MPMU_TDEV4
NC_MPMU_TDEV5
WLANBT_THMSNS
MPMU_THMSNS
CHGR_THMSNS
MPMU_TCAL
1
C8320
100PF
5%
25V
2
C0G
0201
PMU_ONOFF_L
PMU_RSLOC_RST_L
NC_MPMU_BUTTON3
NC_MPMU_BUTTON4
SOC_WDOG
UPC_PMU_RESET_1V8
SOC_SOCHOT_L
VSS_ANA_MPMU
PMU_SHDN
R8322
10K
1/20W
VSS_ANA_MPMU
MPMU_XIN
MPMU_XOUT
DCIN_VSENSE
DCIN_ISENSE
PBUS_VSENSE
BMON_ISENSE
MPMU_AMUX_AY
P3V8AON_HS_ISENSE
P3V3S2_HS_ISENSE
P5VS2_HS_ISENSE
MPMU_HS_ISENSE
MPMU_AMUX_BY
1%
MF
201
2 1
NOSTUFF
33 62 63 94
U8100
TMLT46B0-JPE
WLCSP
SYM 4 OF 6
E8
TDEV1
F9
TDEV2
F8
TDEV3
F7
TDEV4
G9
TDEV5
G10
TDEV6
G8
TDEV7
G7
TDEV8
F10
TCAL
TDEV GPIO
P10
BUTTON1
M6
BUTTON2
N8
BUTTON3
P11
BUTTON4
N11 N13
RESET_IN1
M10
RESET_IN2
M9
RESET_IN3
R7
VBUS_DET
E9
BRICK_ID1
E10
BRICK_ID2
M8
SHDN
N19
NXTAL_MEMS
L22
XIN
M22
XOUT
E13
AMUX_A<0>
F11
AMUX_A<1>
E12
AMUX_A<2>
E11
AMUX_A<3>
G12
AMUX_AY
E14
AMUX_B<0>
F14
AMUX_B<1>
F12
AMUX_B<2>
F13
AMUX_B<3>
G11
A UX_BY
AMUX
BUTTONS
RESET
SPMI
CLOCKS
DBLCLICK_DET
FAULT_OUT*
SGPIO_READY_REQ
SGPIO_SCLK
SGPIO_SDATA
SPMI_SDATA
ACTIVE_READY
REQUEST_DFU
CPU_TRIGGER0*
CPU_TRIGGER1*
GPU_TRIGGER0*
GPU_TRIGGER1*
VDD_BOOST_UVLO*
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
BUTTONO1
BUTTONO2
BUTTONO3
RESET*
FORCE_DFU
SCRASH*
SPMI_SCLK
SLEEP_32K
OUT_32K
CRASH*
DFT_CTRL0
DFT_CTRL1
SYS_ALI E
UVWARN*
P16
T9
T7
R11
T8
U7
T11
U10
R12
U9
T12
U11
T13
U13
M13
M14
N14
R13
U14
U15
T14
U16
U17
R14
N10
P8
P17
N7
N9
M7
N6
T10
M12
N12
M15
N15
P15
R15
T15
U18
T16
P12
M16
M17
M11
P13
R6
P6
R9
R8
R10
P14
T17
IPD_LID_OPEN_1V8
CHGR_AUX_OK
SWD_NUB_PMU_SWDIO
CODEC_WAKE_L
WLBT_WAKE
MPMU_GPIO6
NC_HDMI_CEC_IRQ
NC_USB3_WAKE
NC_HDMI_RESET_L
MPMU_GPIO10
P3V3S2_PWR_EN
PVDD1_PWR_EN
WLBT_PWR_EN
MPMU_GPIO14
SE_PWR_EN
SENSOR_PWR_EN
NAND0_LPB_L
BL_PWR_EN
P3V8AON_LPM
MPMU_GPIO20
TPT_MPMU_NAND0_RESET_L
NC_MPMU_GPIO22
NC_USB3_PWR_EN
NC_UWB_PWR_EN
P2V5_NAND0_DISCHARGE_EN
NC_MPMU_GPIO26
NC_MPMU_GPIO27
MPMU_BUTTONO1
NC_MPMU_BUTTONO2
NO_TEST=1
NC_MPMU_BUTTONO3
DBL_CLICK_DET
PMU_RESET_L
SOC_FORCE_DFU
MPMU_FAULT_OUT_L
PMU_SCRASH_L
PMU_SGPIO_READY_REQ
SGPIO_SCLK_R
SGPIO_SDATA_R
SPMI_NUB_MPMU_CLK
SPMI_NUB_MPMU_DATA
R8331
PMU_CLK32K_SOC_R
1/20W
PLACE_NEAR=U8100.U18:5MM
5%
R8330
PMU_CLK32K_WLBT_R
PMU_CRASH_L
VSS_ANA_MPMU
SWD_NUB_SWCLK
PMU_SYS_ALIVE
PMU_ACTIVE_READY
MPMU_REQUEST_DFU
BUCK0_THERMAL_THROTTLE_L
PMU_VDDHI_UVWARN_L
BUCK1_THERMAL_THROTTLE_L
RSVD_GPU_TRIGGER1_L
PMU_VDDMAIN_UVWARN_L
TPT_MPMU_BOOST_UVLO_L
PLACE_NEAR=U8100.T16:5MM
5%
1/20W
MF
MF
73 85 87 89
IN
23
IN
9 29
BI
76
IN
62 63
IN
34
IN
34
OUT
34
IN
34
OUT
34
OUT
33 38
OUT
33 39
OUT
33 62 63 94
OUT
34
OUT
20 33
OUT
33 39 44
OUT
64 65 67
OUT
71 94
OUT
24 33
OUT
34
OUT
34
OUT
34
OUT
34
OUT
34
OUT
66
OUT
34
OUT
34
OUT
19
OUT
34
OUT
34
OUT
6
OUT
5 9 74 89 90 100
OUT
5 56 89 90
T
33 91
29 91
BI
29
OUT
33
33
18
IN
18
BI
33
2 1
2 1
PMU_CLK32K_SOC
201
33
PMU_CLK32K_WLBT
201
OUT
OUT
33 91
9 29
IN
33 67 89 100 107
5 55 89 94
33
OUT
OUT
OUT
OUT
OUT
OUT
34 32
<= FOR J274 ONLY
<= FOR J274 ONLY
<= FOR J274 ONLY
HDMI_PWR_EN==> FOR J274 ONLY
HDMI_CECFET_EN==> FOR J274 ONLY
NAND RESET NOT POR
FOR DESKTOP ONLY (5V USB3 SWITCH ENABLE
FOR J456 ONLY (ENABLE UWB LDO)
<= NOT USED
<= NOT USED
<= NOT USED
<< VDDIO_1V2 OD
<< PMOS_OD
9 18
OUT
62 63
OUT
6 34
34 106
6 34
19 34
6 34
34
DECOUPLING: LDOINT
PP1V5_VLDOINT_MPMU
CRITICAL
1
C8322
10UF
20%
6.3V
2
CER-X6S
0402
CRITICAL
1
C830D
10UF
20%
6.3V
2
CER-X6S
0402
DECOUPLING: LDO3
PP1V2_S2
CRITICAL
1
C8307
10UF
20%
6.3V
2
CER-X6S
0402
CRITICAL
1
C830A
10UF
20%
6.3V
2
CER-X6S
0402
DECOUPLING: LDO9
PP1V8_AON_ PMU
CRITICAL
1
C8304
1UF
20%
10V
2
X6S-CERM
CRITICAL
1
C830C
1UF
20%
10V
2
X6S-CERM
0201 0201
1
C830G
220PF
10%
16V
CER-X7R
0201
1
C830H
220PF
10%
16V
2
CER-X7R
0201
DECOUPLING: LDO7
102 33
CRITICAL
1
C8309
10UF 10UF
20%
6.3V
2
CER-X6S
0402
102 33
1
C8303
2
NOSTUFF
31 32 33 34
PP3V3_S2_UPC
20%
6.3V
CER-X6S
0402
CRITICAL CRITICAL
1
C830E
10UF
20%
6.3V
2
CER-X6S
04 2
INTEGRATOR ALIAS TO:
1V8 OCARINA=Y
1V2 OCARINA=N
102 33
49 34 32
VSS_ANA_MPMU
PP1V25_S2
R8343
5%
NOSTUFF SINCE PMU_SYS_ALIVE IS PUSH PULL PER OTP
PP1V8_AON_MPMU
R8324
5% 201 MF
R8325
5% 1/20W
R8338
5%
R8339
5% MF 201
1/20W
1/20W
1/20W
1
2
10K
10K
100K
100K
10K
C8321
0.1UF
10%
6.3V
CERM-X5R
0201
2 1
PMU_SYS_ALIVE
201 1/20W
MF
2 1
PMU_ONOFF_L
2 1
PMU_RSLOC_RST_L
201 MF
2 1
MPMU_FAULT_OUT_L
MF
201
2 1
PMU_CRASH_L
NOSTUFF
29
NOSTUFF
102
33 67 89 100 107
<== LDO9 POWER ALIAS
102 35 34 33
33 34 80 89 90
33 34 82 89 90
33 91
33 91
R8327
5%
1/20W
R8328
1/20W
5%
R8329
5%
1/ 0W
R8335
5%
1/20W
R8336
1/20W
5%
R8334
R8337
R8344
5% 1/20W MF
100K
100K
100K
100K
100K
10K
100K
100K
MF
MF
MF
MF
MF
MF
2 1
SE_PWR_EN
201
NOSTUFF
2 1
P5VS2_PWR_EN_RC
201
2 1
P3V3S2_PWR_EN
201
NOSTUFF
2 1
SENSOR_PWR_EN
201
NOSTUFF
2 1
IPD_PWR_EN
201
2 1
MPMU_REQUEST_DFU
201 5% 1/20W
2 1
P3V8AON_LPM
201 MF 5% 1/20W
NOSTUFF
2 1
PVDD1_PWR_EN
201
NOSTUFF
20 33
34 37 84
33 38
33 39 44
34 84 92
33
24 33
33 39
VSS_ANA_MPMU
34
SGPIO_SCLK_R
33
PL CE_NEAR=U8100.N15:5MM
SGPIO_SDATA_R
33
PLACE_NEAR=U8100.P15:5MM
1
2
R8341
20
5%
1/20W
MF
201
R8342
20
5%
1/20W
MF
201
MPMU_XTAL1_R
CRITICAL
Y8301
32.768KHZ 20PPM-12.5PF
1.60X1.00-SM
2 1
C8312
18PF
5%
25V
C0G-CERM
0201
2 1
SGPIO_SCLK
2 1
SGPIO_SDATA
OU
OUT
R8313
0
2 1
0201 MF 1/20W 5% MPMU_XIN
CRITICAL CRITICAL
1
C8313
18PF
5%
25V
2
C0G-CERM
0201
29
PAGE TITLE
NOSTUFF
1
R8318
1M
5%
1/20W
MF
201
2
MPMU_XOUT
33
33
NC TE CM TE E T M
PMU: MASTER LDO & GPIO
29
BOM_COST_GROUP=PLATFORM POWER
2
1
Page 34
PP1V2 LDO VDD IN option (LDO3, 8, 20)
w w w . t e k n i s i - i n d o n e s i a . c o m
Stuff R8422 for BUCK14 pre-regulator (Proto2 and later)
MASTER PMU AMUX ALIAS
44
IN
DCIN_VSENSE
MAKE_BASE=TRUE
DCIN_VSENSE
OUT
ADDITIONAL VDD_MAIN DECOUPLING CAPS
33
105 34 33 31
14X 1.0UF X6S
PP3V8_AON_MPMU_ISNS_VIN
102
102
PP1V25_S2
PP1V4_LDO_PREREG
BUCK 14
32
IN
32
OUT
P1V2_PREREG:BUCK13
P1V2_PREREG:BUCK14
BUCK14_LX
BUCK14_FB_MPMU
R8411
0
2 1
5% 1/16W MF 0402
116S00014
R8422
0
2 1
5% 1/16W MF 0402
116S00014
34
BUCK14_LX
BUCK14_FB_MPMU
MAKE_BASE=TRUE
DIDT=TRUE
SWITCH_NODE=TRUE
MAKE_BASE=TRUE
PPVDD_PMU_LDO_PREREG
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000
VOLTAGE=1.4
PPVDD_PMU_LDO_PREREG
PPVDD_PMU_LDO_PREREG
PPVDD_PMU_LDO_PREREG
L84E0
0.47UH-20%-4A-0.027OHM
2012
PLACE_NEAR=U8100.D14:15MM
R84E0
0
2 1
5% 1/20W
0201 MF
2 1
BUCK14_FB_R
NO_XNET_CONNECTION=1
XW84E0
2 1
SM
31
28
28
1
C84E0
15UF
20%
2V
2
X6S
0402
44
IN
44
IN
44
IN
44
IN
44
IN
44
IN
45
IN
MIRROR_WITH=C84E0
1
C84E1
15UF
20%
2V
2
X6S
0402
DCIN_ISENSE
MAKE_BASE=TRUE
PBUS_VSENSE
MAKE_BASE=TRUE
BMON_ISENSE
MAKE_BASE=TRUE
P3V8AON_HS_ISENSE
MAKE_BASE=TRUE
NO_TEST=1
P3V3S2_HS_ISENSE
MAKE_BASE=TRUE
NO_TEST=1
P5VS2_HS_ISENSE
MAKE_BASE=TRUE
NO_TEST=1
MPMU_HS_ISENSE
MAKE_BASE=TRUE
1
C84E2
15UF
20%
2V
2
X6S
0402
NO_TEST=1
MIRROR_WITH=C84E2
1
C84E3
15UF
20%
2V
2
X6S
0402
DCIN_ISENSE
PBUS_VSENSE
BMON_ISENSE
P3V8AON_HS_ISENSE
P3V3S2_HS_ISENSE
P5VS2_HS_ISENSE
MPMU_HS_ISENSE
PP1V4_LDO_PREREG
MIRROR_WITH=C84E4
1
C84E4
15UF
20%
2V
2
X6S
0402
1
C84E5
15UF
20%
2V
2
X6S
0402
1
C84EA
12PF
5%
25V
2
NP0-C0G
0201
OUT
OUT
OUT
OUT
OUT
OUT
OUT
1
33
3
33
105 34 33 31
33
33
33
33
PP3V8_AON_MPMU_ISNS_VIN
C84C0
1UF
20%
10V
2
X6S-CERM
0201
1
C84C8
1UF
20%
10V
2
X6S-CERM
0201
1
C84C1
1UF
20%
10V
2
X6S-CERM
0201
1
C84C9
1UF
20%
10V
2
X6S-CERM
0201
1
C84C2
1UF
20%
10V
2
X6S-CERM
0201
1
C84CA
1UF
20%
10V
2
X6S-CERM
0201
1
C84C3
1UF
20%
10V
2
X6S-CERM
0201
1
C84CB
1UF
20%
10V
2
X6S-CERM
0201
1
C84C4
1UF
20%
10V
X6S-CERM
0201
1
C84CC
1UF
20%
10V
2
X6S-CERM
0201
1
C84C5
1UF
20%
10V
2
X6S-CERM
0201
1
C84CD
1UF
20%
10V
2
X6S-CERM
0201
1
C84C6
1UF
20%
10V
2
X6S-CERM
0201
1
C84CE
1UF
20%
10V
2
X6S-CERM
0201
1
C84C7
1UF
2 %
10V
2
X6S CERM
0201
GPU RAIL N&V DOE CAPS
102
1
C84EB
3.0PF
+/-0.1PF
25V
2
NP0-C0G
0201
101 31
PPVDD_GPU_AWAKE
1
C8410
15UF
20%
2V
2
X6S
0402
PLACE_SIDE=TOP
1
C8411
15UF
20%
2V
2
X6S
0402
PLACE_SIDE=TOP
1
C8412
15UF
20%
2V
2
X6S
0402
PLACE_SIDE=TOP
1
C8413
15UF
20%
2V
2
X6S
0402
PLACE_SIDE=TOP
1
C8414
15UF
20%
2V
2
X6S
0402
PLACE_SIDE=TOP
1
C8415
15UF
20%
2V
2
X6S
0402
PLACE_SIDE=TOP
GPIO7
GPIO8
GPIO9
GPIO21
GPIO23
GPIO24
MASTER PMU SIGNALS
NC_MPMU_LDO1_EN
33
NC_MPMU_BUTTON3
33
NC_MPMU_BUTTON4
33
NC_MPMU_BUTTONO2
33
NC_MPMU_BUTTONO3
33
NC_HDMI_CEC_IRQ
33
NC_USB3_WAKE
33
NC_HDMI_RESET_L
33
TPT_MPMU_NAND0_RESET_L
33
NC_MPMU_GPIO22
33
NC_USB3_PWR_EN
33
NC_UWB_PWR_EN
33
NC_MPMU_GPIO26
33
NC_MPMU_GPIO27
33
EXTERNAL PULL UPS FOR THROTTLE SIGNALS: SOC HAS IPU
PP1V25_AWAKE_IO
1
10K
10K
10K
10K
10K
R8450
5% 1/20W 201
R8451
R8452
R8453
R8454
NOSTUFF
2 1
MF
NOSTUFF
2 1
201 MF 1/20W 5%
NOSTUFF
2 1
201 1/20W 5%
MF
2 1
201 5% 1/20W
MF
NOSTUFF
201
MF 1/20W 5%
102
BUCK0_THERMAL_THROTTLE_L
PMU_VDDHI_UVWARN_L
BUCK1_THERMAL_THROTTLE_L
RSVD_GPU_TRIGGER1_L
PMU_VDDMAIN_UVWARN_L
NC_MPMU_LDO1_EN
MAKE_BASE=TRUE
NO_TEST=1
NC_MPMU_BUTTON3
MAKE_BASE=TRUE
NO_TEST=1
NC_MPMU_BUTTON4
MAKE_BASE=TRUE
NO_TEST=1
NC_MPMU_BUTTONO2
MAKE_BASE=TRUE
NO_TEST=1
NC_MPMU_BUTTONO3
MAKE_BASE=TRUE
NO_TEST=1
NC_HDMI_CEC_IRQ
MAKE_BASE=TRUE
NO_TEST=1
NC_USB3_WAKE
MAKE_BASE=TRUE
NO_TEST=1
NC_HDMI_RESET_L
MAKE_BASE=TRUE
NO_TEST=1
TPT_MPMU_NAND0_RESET_L
MAKE_BASE=TRUE
NO_TEST=1
NC_MPMU_GPIO22
MAKE_BASE=TRUE
NO_TEST=1
NC_USB3_PWR_EN
MAKE_BASE=TRUE
NO_TEST=1
NC_UWB_PWR_EN
MAKE_BASE=TRUE
NO_TEST=1
NC_MPMU_GPIO26
MAKE_BA E= R E
NO_TEST=1
NC_MPMU_GPIO27
MAKE_BASE=TRUE
NO_TEST=1
IN
IN
IN
IN
IN
6 33
33 106
6 33
19 33
6 33
BOMOPTION=NV_DOE
BOMOPTION=NV_DOE
BOMOPTION=NV_DOE
BOMOPTION=NV_DOE
BOMOPTION=NV_DOE
BOMOPTION=NV_DOE
EVT GPIO changes <rdar://59851797>
0
0
0
5% MF 1/20W
0
5 MF 1/20W
0
5% MF
0
5% MF 1/20W
0
5% MF 1/20W
0
5% MF 1/20W
2 1
2 1
2 1
2 1
2 1
2 1
2 1
2 1
0201
0201
0201
0201
0201
0201
0201
0201
IPD_PWR_EN
PP1V8_AON_MPMU
1
R8420
100K
5%
1/20W
MF
201
2
TPAD_KBD_WAKE_L
P5VS2_PWR_EN_RC
LCD_PWR_EN
OUT
OUT
OUT
33 84 92
102 35 34 33 29
85 89
33 37 4
70 94
MASTER PMU PROBE POINTS
1
PP8403
PP8404
PP8405
P4MM
SM
P4MM
P4MM
102 35 34 33 29
33
IN
PP
PP
PP1V8_AON_MPMU
MPMU_ADC_IN
NO_TEST=1
R8402
5% 1/20W MF1M201
1
MPMU_AMUX_AY
NO_TEST=1
1
MPMU_AMUX_BY
NO_TEST=1
MPMU_VBAT
NO_TEST=1
R8403
5% 1/20W MF1M201
MPMU_IBAT
NO_TEST=1
R8404
5% 1/20W MF1M201
R8410
2 1
TPT_MPMU_BOOST_UVLO_L
NO_TEST=1
100K
201
MF 1/20W 5%
32
OUTPP
2
33
OUT
33
OUT
32
OUT
2 1
32
OUT
2 1
1
PP
PP8402
P4MM
31
IN
31
IN
31
IN
31
IN
31
IN
31
IN
31
IN
31
IN
31
IN
31
IN
31
IN
31
IN
31
IN
32
IN
32
IN
32
IN
32
IN
BUCK0_LX0
NO_TEST=1
BUCK0_LX1
NO_TEST=1
BUCK0_LX2
NO_TEST=1
BUCK0_LX3
NO_TEST=1
BUCK0_LX4
NO_TEST=1
BUCK1_LX0
NO_TEST=1
BUCK1_LX1
NO_TEST=1
BUCK1_LX2
NO_TEST=1
BUCK1_LX3
NO_TEST=1
BUCK1_LX4
NO_TEST=1
BUCK2_LX0
NO_TEST=1
BUCK2_LX1
NO_TEST=1
BUCK2_LX2
NO_TEST=1
BUCK3_LX0
NO_TEST=1
BUCK7_LX0
NO_TEST=1
BUCK7_LX1
NO_TEST=1
BUCK8_LX0
NO_TEST=1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PP8406
PP
PP8407
PP
P4MM SM
PP8408
PP
P4MM SM
PP8409
PP
PP840A
PP
P4MM SM
PP8410
PP
PP8411
PP
P4MM SM
PP8412
PP
P4MM SM
PP8413
PP
P4MM SM
PP8414
PP
P4MM SM
PP8420
PP
PP8421
PP
PP8422
PP
PP8430
PP
PP8470
PP
PP8471
PP
PP8480
PP
P4MM SM
SMP4MM
SMP4MM
SMP4MM
SMP4MM
SMP4MM
SMP4MM
SMP4MM
SMP4MM
SMP4MM
33 34
IN
MPMU_GPIO6
IPD_PMU_GPIO:EVT
33 34
IN
MPMU_GPIO14
IPD_PMU_GPIO:PROTO
MPMU_GPIO14
1
PP8401
P4MM
PP
SM
33 34
MPMU_GPIO6
3 34
IPD_PMU_GPIO:EVT
R8431
1/20W MF 5%
R8432
1/20W MF 5
R8433
R8434
IPD_PMU_GPIO:PROTO
33 34
IN OUT
33 34
IN
MPMU_GPIO20
MPMU_GPIO10
R8435
IPD_PMU_GPIO:EVT
R8436
1/20W
IPD_PMU_GPIO:PROTO
MPMU_GPIO10
33 34
R8437
IPD_PMU_GPIO:EVT
MPMU_GPIO20
33 34
R8438
IPD_PMU_GPIO:PROTO
CHARGER RESET CIRCUIT
RIGHT SHIFT & LEFT OPTION CONTROL (RSLOC)
FOLLOWED BY ON-OFF BUTTON PRESS.
NEW APN 343S00387 can take 1.8V as BTN1/2 inputs.
PP3V3_AON
104
PLACE_NEAR=U8440.1:5MM
10%
25V
X5R
0201
1
VDD
2
U8440
SLG4AP43601
STQFN
3
4
BTN1
BTN2
RE ET
C8440
0.1UF
33 80 89 90
IN
33 82 89 90
IN
PMU_ONOFF_L CHGR_RST_IN_R
PMU_RSLOC_RST_L
CRITICAL
343S00387
NC
GND
Isolation for CHGR_RST_IN not to assert when ACE drives UPC_PMU_RESET
SAK output should hold it below charger VIL
10
2
NC
5
NC
6
NC
8
NC
9
NC
11
NC
12
NC
57 58 90 100
IN
R8440
3.3K
1/20W
5%
MF
201
2 1
R8441
3.3K
1/20W
UPC_PMU_RESET_3V3
5%
MF
201
2 1
CHGR_RST_IN
OUT
32
IN
VLDORTC SHORTED TO VDD_ANA FOR PORTABLES RDAR://57024711
PP1V5_VLDOINT_MPMU
33
PP1V5_VLDOINT_MPMU
MAKE_BASE=TRUE
31 32 33
32
IN
32
IN
32
IN
VSS alias connection
# & WIDTH OF XW IS LAYOUT DEPENDENT
32 3
32 31
33 32
33 32
33 32 31
22
PP1V8_AON
311S00246
1
C8445
0.1UF
10%
6.3V
2
CERM-X5R
0201
104
49 33 32
U8445
VCC
2
GND
SN74AUP1G17
SON
4
NC
NC
NC
NC
UPC_PMU_RESET_1V8
OUT
33
VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU
3
VSS_ANA_MPMU
32
VSS_ANA_MPMU
VSS_ANA_MPMU
32
VSS_ANA_MPMU
VSS_ANA_MPMU
VSS_ANA_MPMU
32
VSS_ANA_MPMU
32
VSS_ANA_MPMU
3
VSS_ANA_MPMU
VSS_ANA_MPMU
3
VSS_ANA_MPMU
33
VSS_MPMU_AMUX
44 45
XW8400
SHORT-8L-0.25MM-SM
2 1
VSS_ANA_MPMU
MAKE_BASE=TRUE
MIN_ E K_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000
VOLTAGE=0
GND
32
GND
32
GND
32
GND
32
GND
32
GND
32
GND
32
GND
32
33 32
GND
2
XW8401
1
SHORT-12L-0.25MM-SM
2
XW8402
1
SHORT-12L-0.25MM-SM
2
XW8403
1
SHORT-12L-0.25MM-SM
PAGE TITLE
2
XW8404
1
SHORT-12L-0.25MM-SM
33
IN PP
PMU: MASTER SUPPORT
BUCK8_LX1
NO_TEST=1
BUCK9_LX0
NO_TEST=1
BUCK11_LX0
NO_TEST=1
BUCK11_LX1
NO_TEST=1
BUCK14_LX
34
NO_TEST=1
MPMU_BSTLQ_LX
NO_TEST=1
1
1
1
1
1
1
PP8481
PP
PP8490
PP
PP84B0
PP
PP84B1
PP
P4MM SM
PP84E0
PP
PP84F0
SMP4MM
SMP4MM
SMP4MM
SMP4MM
SMP4MM
NC TE CM TE E T M
BOM_COST_GROUP=PLATFORM POWER
Page 35
PP3V8_AON
w w w . t e k n i s i - i n d o n e s i a . c o m
101
3.3V AON LDO
102 35 34 33 29
102 35 34 33 29
PP1V8_AON_MPMU
PP3V8_AON
101
PP1V8_AON_MPMU
RC100
0
5%
1/20W
MF
0201
RC120
0
5%
1/20W
MF
0201
CC100
1.0UF
20%
6.3V
X5R
0201-1
2 1
P3V3_AON_EN
CC120
1.0UF
20%
6.3V
X5R
0201-1
2 1
P1V8_AON_EN
1
2
B1
353S3698
UC100
LP5907UVX-3.3V
VIN
VEN
USMD
GND
VOUT
250MA MAX
IQ_ON < 12 UA
A2 A1
1
CC101
1.0UF
20%
6.3V
2
X5R
0201-1
PP3V3_AON
104
1.8V AON LDO
1
2
B1
353S4262
UC120
LP5907UVX-1.8
VIN
VEN
DSBGA
GND
VOUT
250MA MAX
IQ_ON < 12 UA
A2 A1
1
CC121
1.0UF
20%
6.3V
2
X5R
0201-1
PP1V8_AON
104
SYNC_DATE=09/23/2019 SYNC_MASTER=KEI_T668_MLB
PAGE TITLE
POWER: EXTERNAL LDO
BOM_COST_GROUP=PLATFORM POWER
Page 36
* OK2INTEGRATE *
www.teknisi-indonesia.com
w w w . t e k n i s i - i n d o n e s i a . c o m
PPBUS_AON_5VS2_VIN_ISNS
105
5V_S2 Voltage Regulator
SET ONE OPTION FOR PBUS CAPS
PACK_OPTION=5V_S2_PBUS-B12
PACK_OPTION=5V_S2_PBUS-D2
PACK_OPTION=5V_S2_PBUS-D12
CAPDERATE
POLY-TANT
CRITICAL
1
CC320
33UF
20%
16V
2
TANT
CASE-T
128S00009
PAC _IGNORE=TRUE
PAC _IGNORE=TRUE
PAC _IGNORE=TRUE
PACK_OPTION=5V_S2_PBUS-B12
PACK_OPTION=5V_S2_PBUS-B12
PACK_OPTION=5V_S2_PBUS-B12
CAPDERATE
POLY T N
CRITICAL
1
CC340
68UF
20%
16V
2
POLY-TANT
CASE-D2E-SM
128S0264
PAC _OPTION=5V_S2_PBUS-D2
PAC _OPTION=5V_S2_PBUS-D2
CAPDERATE
POLY-T NT
CRITICAL
1
CC350
33UF
20%
16V
2
TANT
CASED12-SM
128S0436
CAPDERATE CAPDERATE
POLY-TANT
CRITICAL
1
CC321
33UF
20%
16V
2
TANT
CASE-T
128S00009
CAPDERATE
POLY-TANT
CRITICAL
1
CC341
68UF
20%
16V
2
POLY-TANT
CASE-D2E-SM
128S0264
CAPDERATE
POLY-TANT
CRITICAL
1
CC351
33UF
20%
16V
2
TANT
CASED12-SM
128S0436
POLY-TANT
CRITICAL
1
CC322
33UF
20%
16V
2
TANT
CASE-T
128S00009
P5VS2_PGOOD
36
RC328
100K
5%
1/20W
MF
201
117S 008
2 1
PP5V_S2
START UP TIME < 15 MS
104
P5VS2_VC_R
PACK_IGNORE=TRUE
PACK_IGNORE=TRUE
PACK_OPTION=5V_S2_PBUS-D12
PACK_OPTION=5V_S2_PBUS-D12
1
CC323
2.2UF
20%
25V
2
X6S-CERM
0402
138S00042
37
IN
1
RC321
2
1
2
P5VS2_PWR_EN
20.5K
1%
1/20W
MF
201
118S0 8
CC328
1000PF
10%
16V
X R-1
02 1
132S0651
1
2
1
2
CC324
2.2UF
20%
25V
X6S-CERM
0402
138S00042
CC329
100PF
5%
25V
C0G
0201
131S0805
1
CC325
2.2UF
20%
25V
2
X6S-CERM
0402
138S00042
RC333
117S0201
1
CC327
0.01UF
10%
16V
2
X7R-CERM
0402
132S0374
0
5%
1/20W
MF
0201
36
1
CC326
2.2UF
20%
25V
2
X6S-CERM
0402
138S00042
4
VIN
5
VIN
6
VIN
13
VIN
14
2 1
P5VS2_EN
P5VS2_VC
OUT
36
P5VS2_PGOOD
P5VS2_FB
P5VS2_SS
P5VS2_RT
1
RC320
25.5K
1%
1/20W
MF
201
2
118S0235
XWC320
SM
15
17
22
23
24
21
18
20
2 1
VIN
VIN
EN/UV
VC
PG
FB
SS
RT
SYNC/MODE
UC300
LT8642EV-2#PBF
LQFN
353S02219
CRITICAL
GND
NC
BIAS
INTVCC
BST
SW
SW
SW
SW
SW
CLKOUT
1
2
7
8
9
10
11
12
19
P5VS2_BIAS
P5VS2_INTVCC
P5VS2_BST P5VS2_BST_R
SWITCH_NODE=TRUE
DIDT=TRUE
P5VS2_SW
SWITCH_NODE=TRUE
DIDT=TRUE
MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000
NC
1
CC330
2.2UF
20%
25V
2
X6S-CERM
0402
138S00042
RC332
1.5
5%
1/20W
MF
201
117S0029
2 1
SWITCH_NODE=TRUE
DIDT=TRUE
P5VS2_FB_RC
1
CC331
2.2UF
20%
25V
2
X6S-CERM
0402
138S00042
RC326
47K
1/20W
118S0395
201
1
1%
MF
2
CC332
47NF
2 1
%
10V
X6S-CERM
0201
132S00028
CRITICAL
LC320
1UH-20%-11A-0.0127OHM
PIHA052D-SM
152S00265
XWC321
P5VS2_FB_XW
2 1
SM
2
1
1
RC322
10
5%
1/20W
MF
201
2
117S0004
1
RC323
9.31K
1%
1/20W
MF
201
2
118S0569
1
RC327
0
5%
1/20W
MF
0201
2
117S0201
CAPDERATE
POLY-TANT
CRITICAL
1
CC334
150UF
20%
6.3V
2
TANT
CASE-B-S
128S00038
CAPDERATE
POLY-TANT
CRITICAL
1
CC335
150UF
20%
6.3V
2
TANT
CASE-B-SM
128S00038
CRITICAL
1
CC337
2.2UF
20%
25V
2
X6S-CERM
04 2
138S00042
Vout=5.15V
EDC=6.6A
F=1.5MHz
PP5V_S2 104
CRITICAL
1
CC338
2.2UF
20%
25V
2
X6S-CERM
0402
138S00042
P5VS2_AGND
P5VS2_FB_C P5VS2_FB_RC2
P5VS2_FB
36
CC333
470PF
10%
X5R-X7R-CERM
132S0361
16
0201
1
2
CRITICAL
1
RC324
200K
0.1%
1/20W
TF
0201
2
118S0738
CRITICAL
1
RC325
27.4K
0.1%
1/20W
MF
0201
2
103S00009
SYNC_MASTER=REF_VR_5V_TPS62135 SYNC_DATE=04/16/2020
PAGE TITLE
POWER: 5V S2
BOM_COST_GROUP=PLATFORM POWER
2
1
Page 37
5VS2_EN TURN OFF DELAY 13-16MS
w w w . t e k n i s i - i n d o n e s i a . c o m
DC401
X3DFN2
33 34 84 36
P5VS2_PWR_EN_RC
NSR01L30MXT5G-COMBO
K A
371S00062
RC401
1K
5%
1/20W
MF
201
2 1
P5VS2_PWR_EN P5VS2_PWR_EN_RC_D
OUT IN
RC402
255K
2 1
1%
1/20W
MF
201
10%
6.3V
X6S
0201
1
2
CC401
0.1UF
BOM_COST_GROUP=PLATFORM POWER
PAGE TITLE
SYNC_DATE=03/26/2020 SYNC_MASTER=T668_MLB
POWER: 5V S2 SUPPORT
A
Page 38
* OK2INTEGRATE *
w w w . t e k n i s i - i n d o n e s i a . c o m
PPBUS_AON_3V3S2_VIN_ISNS
105
CAPDERATE
POLY-TANT
CRITICAL
1
CC710
33UF
20%
16V
2
TANT
CASE-T
128S00009
PACK_IGNORE=TRUE
PACK_IGNORE=TRUE
PACK_O TION=3V3_S2_PBUS-B12
PACK_O TION=3V3_S2_PBUS-B12
CAPDERATE
POLY-TANT
CRITICAL
1
CC711
33UF
20%
16V
2
TANT
CASE-T
128S00009
3V3_S2 VR
SET ONE OPTION FOR PBUS CAPS
PACK_OPTION=3V3_S2_PBUS-B12
PACK_OPTION=3V3_S2_PBUS-D2
PACK_OPTION=3V3_S2_PBUS-D12
PACK_OPTION=3V3_S2_PBUS-25V_D2
START UP TIME <5 MS
CAPDERATE
POLY-TANT
CRITICAL
1
CC721
68UF
20%
16V
2
POLY-TANT
CASE-D2E-SM
128S0264
PACK_O TION=3V3_S2_PBUS-D2
CAPDERATE
POLY-TANT
CRITICAL
1
CC722
33UF
20%
16V
2
TANT
CASED12-SM
128 0436
PACK_IG ORE=TRUE
PACK_OPTION=3V3_S2_PBUS-D12
CRITICAL
1
CC723
22UF
20%
25V
2
POLY-TANT
CASE-D2-SM
128S0217
PACK_IGNORE=TRUE
PACK_OPTION=3V3_S2_PBUS-25V_D2
P3V3S2_PGOOD
38
RC715
100K
5%
1/20W
MF
201
117S0008
2 1
PP3V3_S2
104
CRITICAL
1
CC712
2.2UF
20%
25V
2
X6S-CERM
0402
138S00042
CRITICAL
1
CC713
2.2UF
20%
25V
2
X6S-CERM
0402
138S00042
VOUT=3.3V
EDC=2.5A
CRITICAL
UC710
SN621371
1 2
RC714
0
5%
MF
2 1
P3V3S2_SS
1
CC714
0.01UF
10%
10V
2
X7R-CERM
0201
132S0411
33
IN
P3V3S2_PWR_EN P3V3S2_EN
1/20W
0201
117S0201
VIN
8
EN
9
SS/TR
11
VSEL
10 4
MODE
XWC710
SM
VQFN
353S02228
CRITICAL
GND
2 1
SW
VOS
FB
PG
FB2
MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000
DIDT=TRUE
SWITCH_NODE=TRUE
P3V3S2_SW
6
P3V3S2_VOS
5
P3V3S2_FB
7
P3V3S2_PGOOD
O T
38
1.5UH-20%-3.9A-0.048OHM
LC710
1210
152S00476
2 1
P3V3S2_FB_XW
2
XWC711
SM
1
1
RC709
15
5%
1/20W
MF
201
2
117S0030
P3V3S2_FB_LPF
CC719
0.1UF
2 1
POLY-TANT
CRITICAL
1
CC715
150UF
20%
6.3V
2
TANT
CASE-B-SM
128S00038
CRITICAL
1
CC717
10UF
20%
6 3V
2
CE -X6S
02
138S00073
TDC=2.0A
F=1.5MHz
PP3V3_S2
CRITICAL
1
CC718
10UF
20%
6.3V
2
CER-X6S
0402
138S00073
104
1
CC720
150PF
5%
50V
2
CER-C0G
0201
131S00142
P3V3S2_FB_R
1
RC710
0
5%
1/20W
MF
0201
2
117S0201
1
RC711
2.26K
1%
1/20W
MF
201
2
118S0204
CRITICAL
1
RC712
127K
0.1%
1/20W
MF
0201
2
103S0442
CRITICAL
1
RC713
34.8K
0.1%
1/20W
MF
0201-1
2
103S00058
10%
16V
CER
0201
132S00048
SYNC_MASTER=REF_VR_3V3_TPS62135 SYNC_DATE=01/09/2020
PAGE TITLE
POWER: 3V3 S2
P3V3S2_AGND
BOM_COST_GROUP=PLATFORM POWER
Page 39
CC811
w w w . t e k n i s i - i n d o n e s i a . c o m
4700PF
10%
10V
X7R
20
3.3V SENSOR SWITCH (WIP)
VDD: 2.5 to 5.5V
PP3V3_S2
104
PLACE_NEAR=UC810.1:5MM
10%
35V
0201
1
2
VDD
UC810
SLG5AP1445V
CAP
ON S
VIH_MIN
0.85 V 0.85 V
TDFN8
CRITICAL
353S00764
GND
3 7
D
5 2
PP3V3_S2SW_SNS
104
1
CC820
4700PF
10%
10V
2
X7R
201
CC810
0.1UF
CER-X5R
UC810_SS
1
2
IN
SENSOR_PWR_EN
1V8_S2 SWITCH (FROM J213 1V8 G3S)
PP3V8_AON
101
1
CC821
0.1UF
10%
35V
2
CER-X5R
0201
VDD
UC820
SLG5AP1445V
UC820_SS
33 33 44
IN
PVDD1_PWR_EN
NOSTUFF
1
RC820
47K
5%
1/20W
MF
201
2
CAP
ON S
VIH_MIN
TDFN8
CRITICAL
353S00764
GND
VDD: 2.5 to 5.5V
3 7
D
5 2
PP1V8_S2
PP1V8_S2SW_VDD1
101
104
SYNC_DATE=09/10/2019 SYNC_MASTER=KEI_T668_MLB
PAGE TITLE
POWER: FETS
BOM_COST_GROUP=PLATFORM POWER
Page 40
w w w . t e k n i s i - i n d o n e s i a . c o m
SYNC_MASTER=KEI_T668_MLB SYNC_DATE=09/10/2019
PAGE TITLE
POWER: SUPPORT
BOM_COST_GROUP=PLATFORM POWER
Page 41
SIO I2C0
w w w . t e k n i s i - i n d o n e s i a . c o m
102
PP1V25_S2
DIAGS BUS: 0
DEVICE 7-BIT
------ ----ACE 0 0X38
ACE 1 0X3F
SIO I2C1
DIAGS BUS: 1
DEVICE 7-BIT
------ ----SPKRAMP L (A) 0X31
SPKRAMP L (B) 0X32
102
1
RD000
1.5K
5%
1/20W
MF
201
2
6
6
BI
I2C_UPC_SCL
IN
MAKE_BASE=TRUE
I2C_UPC_SDA
MAKE_BASE=TRUE
PP1V25_AWAKE_IO
IN
BI
1
CD010
0.1UF
20%
16V
2
X6S-CERM
0201
I2C_SPKRAMP_L_SCL
I2C_SPKRAMP_L_SDA
1
RD010
1.5K
5%
1/20W
MF
201
2
1
RD001
1.5K
5%
1/20W
MF
201
2
1
RD011
1.5K
5%
1/20W
MF
201
2
I2C_UPC_SCL
I2C_UPC_SCL
I2C_UPC_SDA
I2C_UPC_SDA
UD010
LSF0101DRY
SON
6
EN
5 2
VREF_B
4 3
INB
VER-2
VREF_A
311S00244
GND
INA
1
RD012
2.2K
5%
1/20W
MF
201
2
OUT
OUT
1
RD013
2.2K
5%
1/20W
MF
201
2
BI
55 57
58
55 57
I
58
PP1V8_AWAKE
I2C_1V8_SPKRAMP_L_SCL
MAKE_BASE=TRUE
I2C_1V8_SPKRAMP_L_SDA
MAKE_BASE=TRUE
102
I2C_1V8_SPKRAMP_L_SCL
I2C_1V8_SPKRAMP_L_SCL
I2C_1V8_SPKRAMP_L_SDA
I2C_1V8_SPKRAMP_L_SDA
OUT
OUT
BI
BI
77 80
77
77 80
77
SIO I2C2
DIAGS BUS: 2
DEVICE 7-BIT
------ ----CS42L83A 0X48
SIO I2C3
DIAGS BUS: 3
DEVICE 7-BIT
------ ----SPKRAMP R (D) 0X34
SPKRAMP R (E) 0X35
102
102
PP1V25_AWAKE_IO
1
RD020
1.5K
5%
1/20W
201
2
6
6
BI
I2C_CODEC_SCL
IN
MAKE_BASE=TRUE
I2C_CODEC_SDA
MAKE_BASE=TRUE
PP1V25_AWAKE_IO
1
CD030
0.1UF
20%
16V
2
X6S-CERM
0201
6
6
BI
I2C_SPKRAMP_R_SCL
IN
I2C_SPKRAMP_R_SDA
1
RD030
1.5K
5%
1/20W 1/20W
MF
201
2
1
RD021
1.5K
5%
1/20W
MF
201
2
1
RD031
1.5K
5%
MF
201
2
I2C_CODEC_SCL
I2C_CODEC_SDA
UD030
LSF0101DRY
SON
6
EN
5 2
VREF_B
4 3
INB
VER-2
VREF_A
311S00244
GND
INA
1
RD032
2.2K
5%
1/20W
MF
201
2
O T
1
RD033
2.2K
5%
1/20W
MF
201
2
BI
76
76
PP1V8_AWAKE
I2C_1V8_SPKRAMP_R_SCL
MAKE_BASE=TRUE
I2C_1V8_SPKRAMP_R_SDA
MAKE_BASE=TRUE
102
I2C_1V8_SPKRAMP_R_SCL
I2C_1V8_SPKRAMP_R_SCL
I2C_1V8_SPKRAMP_R_SDA
I2C_1V8_SPKRAMP_R_SDA
OUT
OUT
BI
BI
78 80
78
78 80
78
SIO I2C4
DIAGS BUS: 4
DEVICE 7-BIT
------ ----DFR DISPLAY 0X-DFR TOUCH 0X--
DISP I2C
DIAGS BUS: 12
DEVICE 7-BIT
------ ----JERRY 0X--
87 88 89
6
6
BI
PP1V8_AWAKE_DFR
I2C_DFR_SCL
IN
I2C_DFR_SDA
1
RD040
2.2K
5%
1/20W
201 201
2
1
RD041
2.2K
5%
1/20W
MF
2
RD042
RD043
15
15
CKPLUS_WAIVE=I2C_PULLUP
2 1
2 1
1/20W 5% 201
M
MF
201 1/2 W 5%
89
I2C_DFR_RES_SCL
MAKE_B SE T UE
89
I2C_DFR_RES_SDA
MAKE_BASE=TRUE
CKPLUS_WAIVE=I2C_PULLUP
I2C_DFR_RES_SCL
I2C_DFR_RES_SCL
I2C_DFR_RES_SDA
I2C_DFR_RES_SDA
OUT
UT
BI
BI
87
87
87
87
RD055
0
5%
MF
0
5%
MF
2 1
VOLTAGE=1.2
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
2 1
PP1V2_DISPI2C_PU
1
CD050
0.1UF
20%
16V
2
X6S-CERM
0201
1
RD050
1.5K
5%
1/20W
MF
201
2
1
RD051
1.5K
1/20W
MF
201
2
VREF_A VREF_B
UD050
LSF0102
3
A1
4
A2 B2
X2SON-COMBO
311S00234
GND
EN
B1
1
RD054
200K
5%
1/20W
MF
201
8
2
1
RD052
1.8K
5%
/20W
MF
201
2
UD050_EN
6
5
1
CD051
0.1UF
20%
16V
2
X6S-CERM
0201
PP3V3_SW_LCD
1
RD053
1.8K
5%
1/20W
MF
201
2
I2C_MLB2JERRY_3V3_SCL
I2C_MLB2JERRY_3V3_SDA
69 89 104
OUT
BI
69 89
69 89 7 106
SYNC_MASTER=T668_MLB SYNC_DATE=06/20/2019
PAGE TITLE
I2C: SIO, DISP
102
102
PP1V25_AWAKE_IO
1/20W
0201
NOSTUFF
RD056
PP1V25_S2
1/20W
0201
7 1 6
BI
I2C_DISP_BKLT_SCL
IN
I2C_DISP_BKLT_SDA
BOM_COST_GROUP=SMC
2
Page 42
ISP I2C0
w w w . t e k n i s i - i n d o n e s i a . c o m
ISP I2C1
UNUSED
ISP I2C2
DIAGS BUS: TBD
DEVICE 7-BIT
------ ----CAMERA PMU 0X--
CAMERA SENSOR 0X--
102
UNUSED
PP1V25_S2
1
CD120
0.1UF
20%
16V
2
X6S-CERM
0201
7
7
BI
I2C_CAM_SCL
IN
I2C_CAM_SDA
1
RD120
1.5K
5%
MF
201
2
1
RD121
1.5K
5%
1/20W
MF
201
2
UD120
LSF0101DRY1/20W
SON
6
EN
5 2
VREF_B
4 3
INB
VER-2
VREF_A
311S00244
GND
INA
1
RD122
2.2K
5%
1/20W
MF
201
1
RD123
2.2K
5%
1/20W
MF
201
2
PP1V8_S2
I2C_CAM_1V8_SCL
MAKE_BASE=TRUE
I2C_CAM_1V8_SDA
MAKE_BASE=TRUE
101
I2C_CAM_1V8_SCL
I2C_CAM_1V8_SDA
OUT
BI
68
68
ISP I2C3
AOP I2C0
DIAGS BUS: 5
DEVICE 7-BIT
------ ----ALS CT720SW 0X29
1 2
UNUSED
PP1V25_S2
1
CD140
0.1UF
20%
16V
2
X6S-CERM
0201
1
RD140
1.5K
5%
1/20W
MF
201
2
1
RD141
1.5K
5%
1/20W
MF
201
2
UD140
LSF0101DRY
6
EN
VER-2
SON
1
RD142
2.2K
5%
1/20W
MF
201
2
1
RD143
2.2K
5%
1/20W
MF
201
2
PP1V8_S2
101
AOP I2C1
106
106
IN
BI
5 2
VREF_B
I2C_AOP_ALS_SDA
4 3
311S00244
INB
UNUSED
GND
VREF_A
INA
I2C_ALS_1V8_SCL I2C_AOP_ALS_SCL
MAKE_BASE=TRUE
I2C_ALS_1V8_SDA
MAKE_BASE=TRUE
OUT
BI
69 89
69 89
SYNC_DATE=06/20/2019 SYNC_MASTER=T668_MLB
PAGE TITLE
I2C: ISP, AOP
BOM_COST_GROUP=SMC
Page 43
SMC I2C0
w w w . t e k n i s i - i n d o n e s i a . c o m
102 43
PP1V25_S2
PP1V8_S2
101
DIAGS BUS: 7
DEVICE 7-BIT
------ ----CHGR ISL9240HI 0X9
BMU BQ40Z651 0XB
1
CD200
0.1UF
20%
16V
2
X6S-CERM
0201
91 106
91 106
I2C_SMC_PWR_SCL
IN
I2C_SMC_PWR_SDA
1
RD200
2.2K 2.2K
5%
1/20W
MF
2
1 43
PP1V25_S2
1
RD201
5%
1/20W
MF
201 201
2
UD200
LSF0101DRY
SON
6
EN
5 2
VREF_B
4 3
INB
VER-2
VREF_A
311S00244
GND
INA
UD201_EN
1
RD202
2.2K
5%
1/20W
MF
201
2
1
RD203
2.2K
5%
1/20W
MF
201
2
I2C_SMC_PWR_1V8_SCL
MAKE_BASE=TRUE
I2C_SMC_PWR_1V8_SDA
MAKE_BASE=TRUE
PP3V3_S2
PP3V3_AON
I2C_SMC_PWR_1V8_SCL
I2C_SMC_PWR_1V8_SDA
104
104
OUT
BI BI
22
22
NOSTUFF
1
RD209
200K
5%
1/20W
MF
201
2
1
RD207
5% 5%
1/20W
MF MF
2
1
RD208
4.7K 4.7K
1/20W
201 201
2
I2C_SMC_PWR_3V3_SCL
89
MAKE_BASE=TRUE
I2C_SMC_PWR_3V3_SDA
89
MAKE_BASE=TRUE
I2C_SMC_PWR_3V3_SCL
I2C_SMC_PWR_3V3_SDA
OUT
BI
21
21
VREF_A VREF_B
UD201
LSF0102
3
A1
4
A2 B2
X2SON-COMBO
311S00234
GND
EN
B1
1
RD206
200K
5%
1/20W
MF
201
8
6
5
2
1
CD201
0.1UF
20%
16V
2
X6S-CERM
0201
SMC I2C1
DIAGS BUS: 8
DEVICE 7-BIT
------ ----ACE 0 0X38
ACE 1 0X3F
SMC I2C2
DIAGS BUS: 9
DEVICE 7-BIT
------ ----TMP464 0X48
102
9
9
102
PP1V25_S2
1
RD210
1.5K
5%
MF
201
2
9 89
9 89
BI
I2C_SMC_UPC_SCL
IN
MAKE_BASE=TRUE
I2C_SMC_UPC_SDA
MAKE_BASE=TRUE
PP1V25_S2
IN
BI
1
2
I2C_SMC_SNS1_SCL
I2C_SMC_SNS1_SDA
CD220
0.1UF
20%
16V
X6S-CERM
0201
1
RD220
1.5K
5%
1/20W
MF
201
2
1
RD211
1.5K
5%
1/20W 1/20W
MF
201
2
1
RD221
1.5K
5%
1/20W
MF
201
2
I2C_SMC_UPC_SCL
I2C_SMC_UPC_SCL
I2C_SMC_UPC_SDA
I2C_SMC_UPC_SDA
VREF_A VREF_B
UD220
LSF0102
3
A1
4
A2 B2
X2SON-COMBO
311S00234
GND
EN
B1
55 57
BI
58
BI
55 57
OUT
58
OUT
PP3V3_S2SW_SNS
1
RD224
200K
5%
1/20W
MF
8
2
1
RD222
2.2K
5%
1/20W
MF
201 201
2
1
RD223
2.2K
5%
1/20W
MF
201
2
104 50
UD220_EN
6
5
1
CD221
0.1UF
20%
16V
2
X6S-CERM
0201
I2C_THMSNS_3V3_SCL
MAKE_BASE=TRUE
I2C_THMSNS_3V3_SDA
MAKE_BASE=TRUE
I2C_THMSNS_3V3_SCL
I2C_THMSNS_3V3_SDA
OUT
BI
50
50
SMC I2C3
DIAGS BUS: 10
DEVICE 7-BIT
------ ----PALM TMP461 0X4C
SMC I2C4
DIAGS BUS: 11
DEVICE 7-BIT
------ ----TLA2528 EADC1 0X17
TLA2528 EADC2 0X10
106
106
102
102
9
PP1V8_S2
101
PP1V25_S
1
CD230
0.1UF
20%
16V
2
X6S-CERM
0201
BI
IN
I2C_SMC_IPD_SCL
I2C_SMC_IPD_SDA
PP1V25_S2
SNSRES_DEV
1
CD240
0.1UF
20%
16V
2
X6S-CERM
0201
IN
9
BI
I2C_SMC_SNS0_SCL
I2C_SMC_SNS0_SDA
1
RD230
1.5K
5%
1/20W
MF
201
2
1
RD240
1 5K
5%
MF
201
2
1
RD231
1.5K
5%
1/20W
MF
201
2
1
RD241
1.5K
5%
1/20W 1/20W
MF
201
2
UD230
LSF0101DRY
SON
6
EN
5 2
VREF_B
4 3
INB
A1
4
A2 B2
VER-2
VREF_A
311S00244
GND
VREF_A VREF_B
INA
UD240
LSF0102
X2SON-COMBO
311S00234
SNSRES_DEV
GND
EN
B1
1
RD233
4.7K
5%
1/20W
MF
201
2
8
6
5
1
2
UD240_EN
SNSRES_DEV
1
CD241
0.1UF
20%
16V
2
X6S-CERM
0201
RD234
4.7K
5%
1/20W
MF
201
SNSRES_DEV
1
RD244
200K
5%
1/20W
MF
201
2
89
I2C_SMC_IPD_1V8_SCL
MAKE_BASE=TRUE
I2C_SMC_IPD_1V8_SDA
89
MAKE_BASE=TRUE
SNSRES_DEV
1
RD242
2.2K
5%
1/20W
MF
201
2
PP3V3_S2SW_SNS
SNSRES_DEV
1
RD243
2.2K
5%
1/20W
MF
201
2
I2C_EADC_3V3_SCL
MAKE_BASE=TRUE
I2C_EADC_3V3_SDA
MAKE_BASE=TRUE
I2C_SMC_IPD_1V8_SCL
I2C_SMC_IPD_1V8_SDA
104 50 43
I2C_EADC_3V3_SCL
I2C_EADC_3V3_SCL
I2C_EADC_3V3_SDA
I2C_EADC_3V3_SDA
OUT
BI
OUT
OUT
BI
BI
85
85
SYNC_MASTER=KEI_T668_MLB SYNC_DATE=12/20/2019
48
48
48
48
PAGE TITLE
I2C: SMC
BOM_COST_GROUP=SMC
Page 44
101
w w w . t e k n i s i - i n d o n e s i a . c o m
105
P3V8 AON HIGH SIDE CURRENT SENSE (IMVR)
GAIN: 50X, TDP: 3.55 A
RSENSE: 0.01 OR SHORT
VSENSE: 35.6 MV, RANGE: 6.6 A
SHORT APN: 998-01924?
PPBUS_AON
NO_XNET_CONNECTION=1
SNSRES_DEV
RD540
0 01
0612-COMBO
107S00076
PPBUS_VMAIN_VIN_ISNS
PLACE_NEAR=UD540.3:5MM
1
0 5%
1W
MF
432
PLACE_NEAR=UD540.4:5MM
104 47 46 45 44
104 47 46 45 44
48
OUT
ISNS_3V8AONHS_P
ISNS_3V8AONHS_N
48
OUT
PP3V3_S2SW_SNS
PP3V3_S2SW_SNS
3
4
7
VS
UD540
INA190A2RSW
UQFN
IN+
CRITICAL
IN-
SNSRES_DEV
50X
ENABLE
GND
OUT
REF
NC
NC
NC
SNSRES_DEV
1
CD540
0.1UF
10%
6.3V
2
CERM-X5R
0201
10
INA_3V8AONHS_IOUT
8
1
NC
2
NC
5
NC
PLACE_NEAR=U8100.E14:15MM
SNSRES_DEV
RD548
36.5K
1/20W
1
MF
201
NOSTUFF
RD549
2 1
100K
1%
1/20W
MF
201
1
2
P3V8AON_HS_ISENSE
SNSRES_DEV
1
CD549
0.22UF
10%
6.3V
2
X5R-CERM
0201
VSS_MPMU_AMUX
OUT
34 44 45
DCIN VOLTAGE SENSE (VD0R)
PMU AMUX inputs are not fail safe but RD501 limits the current rdar://60591705
101 48
34
PPDCIN_USBC_AON
RD502
54.9K
1%
1/20W
MF
201
PLACE_NEAR=U8100.E13:15MM
1
RD501
255K
1%
1/20W
MF
201
2
DCIN_VSENSE
1
2
1
CD501
0.022UF
10%
6.3V
2
X5R-CERM
0201
VSS_MPMU_AMUX
OUT
34 44 45
34
DCIN CURRENT SENSE [AMON] (ID0R)
PLACE_NEAR=U8100.F11:15MM
101
105
5V S2 VR HIGH SIDE CURRENT SENSE (IO5R)
GAIN: 100X, EDP: 2.52 A
RSENSE: 0.01 OR SHORT
VSENSE: 25.2 MV, RANGE: 5.0 A
SHORT APN: 998-07031
PPBUS_AON
NO_XNET_CONNECTION=1
SNSRES_DEV
RD550
0.01
107S00020
PPBUS_AON_5VS2_VIN_ISNS
PLACE_NEAR=UD550.3:5MM
1
1%
1/3W
MF
0306
104 47 46 45 44
432
PLACE_NEAR=UD550.4:5MM
104 47 46 45 44
48
OUT
ISNS_5VS2HS_P
ISNS_5VS2HS_N
48
OUT
PP3V3_S2SW_SNS
PP3V3_S2SW_SNS
3
4
7
VS
UD550
INA19 A3RSW
UQFN
IN+
CRITICAL
IN-
SNSRES_DEV
100X
E ABLE
GND
OUT
REF
NC
NC
NC
BYPASS=UD550.6::5MM
SNSRES_DEV
1
CD550
0.1UF
10%
6.3V
2
CERM-X5R
0201
10
INA_5VS2HS_IOUT
8
1
NC
2
NC
5
NC
PLACE_NEAR=U8100.F12:15MM
SNSRES_DEV
RD558
36.5K
1/20W
1%
MF
201
2 1
NOSTUFF
RD559
100K
1/20W
1%
MF
201
1
2
P5VS2_HS_ISENSE
SNSRES_DEV
1
CD559
0.22UF
10%
6.3V
2
X5R-CERM
0201
VSS_MPMU_AMUX
OUT
34
4 44 45
RD518
22 48
IN OUT
CHGR_AMON
45.3K
1/20W
1%
MF
201
2 1
NOSTUFF
RD519
45.3K
1%
1/20W
MF
201
DCIN_ISENSE
1
2
1
CD519
0.022UF
10%
6.3V
2
X5R-CERM
0201
VSS_MPMU_AMUX
34 44 45
34
BATTERY CHARGER CURRENT SENSE [BMON] (IPBR)
PLACE_NEAR=U8100.E11:15MM
RD528
22 48 34
IN OUT
CHGR_BMON
45.3K
1/20W
1%
MF
201
2 1
NOSTUFF
RD529
45.3K
1%
1/20W
MF
201
BMON_ISENSE
1
2
1
CD529
0.022UF
10%
6. V
X R CERM
0201
101
105
3V3 S2 VR HIGH SIDE CURRENT SENSE (IO3R)
GAIN: 100X, EDP: 0.69 A
RSENSE: 0.05 OR SHORT
VSENSE: 34.5 MV, RANGE: 1.0 A
SHORT APN: 998-07031
PPBUS_AON
NO_XNET_CONNECTION=1
SNSRES_DEV
RD560
0.05
107S00017
PPBUS_AON_3V3S2_VIN_ISNS
PLACE_NEAR=UD560.3:5MM
1
1%
1/3W
MF
0306
4 7 6 45 44
432
PLACE_NEAR=UD560 4:5MM
104 47 46 45 4
48
OUT
ISNS_3V3S2HS_P
ISNS_3V3S2HS_N
48
OUT
PP3V3_S2SW_SNS
PP3V3_S2SW_SNS
3
4
7
VS
UD560
INA190A3RSW
UQFN
IN+
CRITICAL
IN-
SNSRES_DEV
100X
ENABLE
GND
OUT
REF
NC
NC
NC
BYPASS=UD560.6::5MM
SNSRES_DEV
1
CD560
0.1UF
10%
6.3V
2
CERM-X5R
0201
10
INA_3V3S2HS_IOUT
8
1
NC
2
NC
5
NC
PLACE_NEAR=U8100.F14:15MM
SNSRES_DEV
RD568
36.5K
1/20W
1%
MF
201
2 1
NOSTUFF
RD569
100K
1%
1/20W
MF
201
1
2
P3V3S2_HS_ISENSE
SNSRES_DEV
1
CD569
0.22UF
10%
6. V
2
X R CERM
0201
VSS_MPMU_AMUX
OUT
34 44 45
VSS_MPMU_AMUX
34 44 45
PBUS VOLTAGE SENSE (VP0R)
RD531/RD532 updated per rdar://60591705
QD530
NTUD3169CZ
SOT-963
N-CHANNEL
34
D
33 39
IN
PPBUS_AON
101
SENSOR_PWR_EN
PBUS_VSNS_IN
75K
1%
MF
201
1
2
RD531
1/20W
PBUS_VSNS_EN_L_DIV
NO_TEST=1
1%
MF
201
1
2
RD532
124K
1/20W
XWD530
SM
1
2
1
5
4
G
S
D
G
S
P-CHANNEL
NOSTUFF
RD530
0
5%
1/20W
MF
0201
2
PBUS_VSNS_EN_L
NO_TEST=1
6
3
PBUS_VSNS_OUT
48
RD539
59K
1%
1/20W
MF
201
PLACE_NEAR=U8100.E12:15MM
1
RD538
200K
1%
1/20W
MF
201
2
PBUS_VSENSE
1
1
CD539
0.022UF
10%
6.3V
2
2
X5R-CERM
0201
VSS_MPMU_AMUX
OUT
34 44 45
34
NOSTUFF
RD535
3
N
PMU_VDD_HI
45.3K
1/20W
1%
MF
201
2 1
C TE CM TE E T M
PAGE TITLE
SENSORS: POWER HIGH SIDE (1/2)
BOM_COST_GROUP=SENSORS
Page 45
101
w w w . t e k n i s i - i n d o n e s i a . c o m
105
101
105
MASTER PMU HIGH SIDE CURRENT SENSE (IPMR)
GAIN: 100X, EDP: 24.5 A
RSENSE: 0.0025 OR SHORT
104 47 46 45 44
PP3V3_S2SW_SNS
VSENSE: 61.25 MV, RANGE: 13.2 A
SHORT APN: 998-01924?
PP3V8_AON
NO_XNET_CONNECTION=1
107S00094
PP3V8_AON_MPMU_ISNS_VIN
RD610
0.0025
1%
1.5W
MF
0612
47 46 45 44
PLACE_NEAR=UD610.3:5MM
48
OUT
1
ISNS_MPMUHS_P
ISNS_MPMUHS_N
432
OUT
48
PP3V3_S2SW_SNS
PLACE_NEAR=UD610.4:5MM
INA190A3RSW
3
IN+
4
IN-
7
ENABLE
VS
UD610
UQFN
CRITICAL
100X
GND
OUT
REF
NC
NC
NC
10
8
1
2
5
SLAVE PMU HIGH SIDE CURRENT SENSE (IPSR)
GAIN: 100X, EDP: 9.92 A
RSENSE: 0.005 OR SHORT
VSENSE: 49.6 MV, RANGE: 6.6 A
SHORT APN: 998-07031
PP3V8_AON
NO_XNET_CONNECTION=1
RD620
0.005
107S00005
PP3V8_AON_SPMU_ISNS_VIN
PLACE_NEAR=UD620.3:5MM
1
1%
1/3W
MF
0306
104 47 46 45 44
432
PLACE_NEAR=UD620.4:5MM
104 47 46 45 44
48
OUT
ISNS_SPMUHS_P
ISNS_SPMUHS_N
48
OUT
PP3V3_S2SW_SNS
PP3V3_S2SW_SNS
3
4
7
VS
UD620
INA19 A3RSW
UQFN
IN+
CRITICAL
IN-
100X
E ABLE
GND
OUT
REF
NC
NC
NC
10
8
1
2
5
BYPASS=UD610.6::5MM
1
CD610
0.1UF
10%
6.3V
2
CERM-X5R
0201
INA_MPMUHS_IOUT
NC
NC
NC
BYPASS=UD620.6::5MM
1
CD620
0.1UF
10%
6.3V
2
CERM-X5R
0201
INA_SPMUHS_IOUT
NO_TEST=1
NC
NC
NC
PLACE_NEAR=U8100.F13:15MM
RD618
36.5K
1/20W
PLACE_NEAR=U7700.C10:5MM
1%
MF
201
2 1
NOSTUFF
RD619
100K
1%
1/20W
MF
201
1
2
RD628
36.5K
1/20W
1%
MF
201
2 1
NOSTUFF
RD629
100K
1%
1/20W
MF
201
1
2
MPMU_HS_ISENSE
1
CD619
0.22UF
10%
6.3V
2
X5R-CERM
0201
VSS_MPMU_AMUX
SPMU_HS_ISENSE
1
CD629
10%
6.3V
2
X5R-CERM
0201
VSS_SPMU_AMUX
OUT
OUT
34
34 44
30
0 45 46
SOC VDD PCPU VSENSE (VCDP)
RD638
11 48 11 48
VSNS_VDD_PCPU VSNS_VSS_PCPU
36.5K 36.5K
1/20W
1%
MF
201
2 1
NOSTUFF
RD639
100K
1%
1/20W
MF
201
SOC_VDDPCPU_VSENSE
1
2
1
CD639
0.22UF
10%
6.3V
2
X5R-CERM
0201
VSS_SPMU_AMUX
30
30 45 46
SOC VDD GPU VSENSE (VGDR)
PLACE_NEAR=U7700.A9:5MM
RD658
1%
MF
201
2 1
NOSTUFF
IN OUT IN OUT
1/20W
RD659
100K
1/20W
SOC_VDDPGPU_VSENSE
1%
MF
201
1
2
1
CD659
0.22UF
10%
6.3V
2
X5R-CERM
0201
VSS_SPMU_AMUX
30
30 45 46
SOC VSS PCPU VSENSE (VCSP)
PLACE_NEAR=U7700.A10:5MM PLACE_NEAR=U7700.B10:5MM
RD648
1%
MF
201
2 1
NOSTUFF
IN OUT IN OUT
1/20W
RD649
100K
1/20W
SOC_VSSPCPU_VSENSE
1
1%
MF
201
2
SOC VDD SOC VSENSE (VSDR)
PLACE_NEAR=U7700.A8:5MM
RD668
11 48 11 48
VSNS_VDD_SOC VSNS_VDD_GPU
36.5K 36.5K
1/20W
1%
MF
201
2 1
NOSTUFF
RD669
100K
1%
1/20W
MF
201
SOC_VDDSOC_VSENSE
1
2
1
CD649
0.22UF
10%
6.3V
2
X5R-CERM
0201
VSS_SPMU_AMUX
1
CD669
0.22UF
10%
6.3V
2
X5R-CERM
0201
VSS_SPMU_AMUX
SOC VDD ECPU VSENSE (VCDE)
PLACE_NEAR=U7700.D11:5MM
RD678
11 48
IN OUT
VSNS_VDD_ECPU
36.5K
1/20W
1%
MF
201
2 1
NOSTUFF
RD679
100K
1%
1/20W
MF
201
SOC_VDDECPU_VSENSE
1
2
1
CD679
0.22UF 0.22UF
10%
6.3V
2
X5R-CERM
0201
VSS_SPMU_AMUX
30
30 45 46
30
30 45 46
30
30 45 46
ATC 3V3 LDO HIGH SIDE CURRENT SENSE (IULR)
GAIN: 100X, EDP: 0.68 A
RSENSE: 0.025 OR SHORT
VSENSE: 17 MV, RANGE: 1.32 A
SHORT APN: 998-07031
101
105
PP3V8_AON
NO_XNET_CONNECTION=1
PP3V8_AON_ATC_ISNS
SNSRES_DEV
RD690
0.025
1%
1/3W
MF
107S00058
0306
4 7 6 45 44
104 47 46 45 44
PLACE_NEAR=UD690.2:5MM
48
OUT
1
ISNS_ATCHS_P
ISNS_ATCHS_N
432
PLACE_NEAR=UD690 4:5MM
OUT
48
PP3V3_S2SW_SNS
PP3V3_S2SW_SNS
3
4
7
VS
UD690
INA190A3RSW
UQFN
IN+
CRITICAL
IN-
SNSRES_DEV
100X
ENABLE
GND
OUT
REF
NC
NC
NC
BYPASS=UD690.6::5MM
SNSRES_DEV
1
CD690
2
10
INA_ATCHS_IOUT
8
1
NC
2
NC
5
NC
0.1UF
10%
6.3V
CERM-X5R
0201
PLACE_NEAR=UE000.15:5MM
SNSRES_DEV
RD698
45.3K
1/20W
1%
MF
201
2 1
NOSTUFF
RD699
100K
1%
1/20W
MF
201
ATC3V3_HS_ISENSE
1
2
SNSRES_DEV
1
CD699
2.2UF
20%
6. V
X R CERM
0201
GND_EADC1_COM
48
45 46 48
MESA 1.8/3.3/16V HIGH SIDE CURRENT SENSE (IIDR)
GAIN: 100X, EDP: 0.176 A
RSENSE: 0.1 OR SHORT
VSENSE: 17.6 MV, RANGE: 0.33 A
SHORT APN: 998-07031
101
105
PP3V8_AON
NO_XNET_CONNECTION=1
PP3V8_MESA_ISNS
SNSRES_DEV
RD6B0
0.1
1%
0.5W
MF
107S00116
0306
4 47 46 45 44
104 47 46 45 44
PLACE_NEAR=UD6B0.2:5MM
48
OUT
1
ISNS_MESAHS_P
ISNS_MESAHS_N
432
PLACE_NEAR=UD6B0.4:5MM
OUT
48
PP3V3_S2SW_SNS
PP3V3_S2SW_SNS
INA190A3RSW
3
IN+
4
IN-
SNSRES_DEV
7
ENABLE
VS
UD6B0
UQFN
CRITICAL
100X
GND
OUT
REF
NC
NC
NC
10
INA_MESAHS_IOUT
8
1
NC
2
NC
5
NC
BYPASS=UD6B0.6::5MM
SNSRES_DEV
1
CD6B0
0.1UF
10%
6.3V
2
CERM-X5R
0201
PLACE_NEAR=UE000.3:5MM
SNSRES_DEV
RD6B8
45.3K
1/20W
1%
MF
201
2 1
NOSTUFF
RD6B9
100K
1/20W
201
MESA_HS_ISENSE
1
1%
MF
2
SNSRES_DEV
1
CD6B9
2.2UF
20%
6.3V
X5R-CERM
0201
GND_EADC1_COM
OUT OUT
45 46 48
48
DFR 1.8/3.3V HIGH SIDE CURRENT SENSE (IFDC)
GAIN: 100X, EDP: 0.75 A
RSENSE: 0.025 OR SHORT
VSENSE: 18.75 MV, RANGE: 1.32 A
SHORT APN: 998-07031
101
PP3V8_AON
NO_XNET_CONNECTION=1
SNSRES_DEV
107S00058
105
PP3V8_AON_DFR_ISNS
RD6A0
0.025
1%
1/3W
MF
0306
104 47 46 45 44
104 47 46 45 44
PLACE_NEAR=UD6A0.2:5MM
OUT
1
ISNS_DFRHS_P
ISNS_DFRHS_N
432
PLACE_NEAR=UD6A0.4:5MM
OUT
PP3V3_S2SW_SNS
PP3V3_S2SW_SNS
48
48
INA190A3RSW
3
IN+
CRITICAL
4
IN-
7
ENABLE
VS
UD6A0
UQFN
100X
GND
OUT
REF
NC
NC
NC
BYPASS=UD6A0.6::5MM
SNSRES_DEV
1
CD6A0
2
10
INA_DFRHS_IOUT
8
1
NC
2
NC
5
NC
0.1UF
10%
6.3V
CERM-X5R
0201
PLACE_NEAR=UE000.2:5MM
RD6A8
45.3K
1/20W
1%
MF
201
2 1
NOSTUFF
RD6A9
100K
1/20W
1%
MF
201
1
2
DFR_HS_ISENSE
SNSRES_DEV
1
CD6A9
2 2UF
20%
6.3V
2
X5R-CERM
0201
GND_EADC1_COM
LCD BACKLIGHT HIGH SIDE CURRENT SENSE (IBLR)
GAIN: 100X, EDP: 0.9 A
RSENSE: 0.025 (RP800) OR SHORT
104 47 6 45 44
PP3V3_S2SW_SNS
VSENSE: 22.6 MV, RANGE: 1.32 A
VS
UD6C0
INA190A3RSW
48
OUT OUT
48 71
IN
ISNS_LCDBKLT_P
3
IN+
UQFN
CRITICAL
48 71
IN
ISNS_LCDBKLT_N
4
IN-
SNSRES_DEV SNSRES_DEV
100X
7
ENABLE
104 47 46 45 44
45 46 48 46 47 48
PP3V3_S2SW_SNS
GND
OUT
REF
NC
NC
NC
10
INA_LCDBKLT_IOUT
NO_TEST=1
8
1
NC
2
NC
5
NC
BYPASS=UD6C0.6::5MM
SNSRES_DEV
1
CD6C0
0.1UF
10%
6.3V
2
CERM-X5R
0201
PLACE_NEAR=UE020.15:5MM
SNSRES_DEV SNSRES_DEV
RD6C8
45.3K
1/20W
1%
MF
201
2 1
NOSTUFF
RD6C9
100K
1%
1/20W
MF
201
LCDBKLT_HS_ISENSE
1
2
SNSRES_DEV
1
CD6C9
2.2UF
20%
6.3V
2
X5R-CERM
0201
GND_EADC2_COM
48
BOM_COST_GROUP=SENSORS
PAGE TITLE
SENSORS: POWER HIGH SIDE (2/2)
2
1
C TE CM TE E T M
Page 46
104
w w w . t e k n i s i - i n d o n e s i a . c o m
105
WLAN BT 3V3 S2 CURRENT SENSE (IW3C)
GAIN: 100X, EDP: 1.5 A
RSENSE: 0.01 OR SHORT
VSENSE: 15 MV, RANGE: TBA A
APN: 107S00020
SHORT APN: 998-07031
PP3V3_S2
NO_XNET_CONNECTION=1
SNSRES_DEV
RD810
107S00020
PP3V3_S2_WLBT_ISNS
PLACE_NEAR=UD810.2:5MM
1
0 01
1%
1/3W
MF
0306
PLACE_NEAR=UD810.4:5MM
104 47 46 45 44
104 47 46 45 44
OUT
ISNS_WLBT3V3_P
ISNS_WLBT3V3_N
432
OUT
PP3V3_S2SW_SNS
PP3V3_S2SW_SNS
48
48
INA190A3RSW
3
IN+
CRITICAL
4
IN-
SNSRES_DEV
7
ENABLE
UD810
100X
VS
UQFN
GND
OUT
REF
NC
NC
NC
BYPASS=UD810.6::5MM
SNSRES_DEV
1
CD810
0.1UF
10%
6.3V
2
CERM-X5R
0201
10
INA_WLBT3V3_IOUT
8
1
NC
2
NC
5
NC
PLACE_NEAR=U7700.B9:5MM
SNSRES_DEV
RD818
36.5K
1/2 W
1
MF
201
2 1
NOSTUFF
WLANBT_3V3_ISENSE
RD819
100K
1%
1/20W
MF
201
WLAN BT 1V8 S2 CURRENT SENSE (IW2C)
GAIN: 200X, EDP: 0.008 A
RSENSE: 0.005 OR SHORT
104 47 46 45 44
PP3V3_S2SW_SNS
VSENSE: 8 MV, RANGE: 0.0165 A
SHORT APN: 998-07031
101
PP1V8_S2
NO_XNET_CONNECTION=1
SNSRES_DEV
OUT
RD850
1.0
1/3W
1
2
SNSRES_DEV
1
CD819
0.22UF
10%
6.3V
2
X5R-CERM
0201
105
PP1V8_S2_WLBT_ISNS
107S00147
0306
104 47 46 45 44
PLACE_NEAR=UD850.2:5MM
48
OUT
1
1%
MF
ISNS_WLBT1V8_P
ISNS_WLBT1V8_N
432
PLACE_NEAR=UD850.4:5MM
OUT
48
PP3V3_S2SW_SNS
UD850
INA190A4IRSW
3
IN
CRITICAL
4
IN-
SNSRES_DEV
200X
7
ENABLE
VS
UQFN
GND
OUT
REF
NC
NC
NC
10
INA_WLBT1V8_IOUT
8
1
NC
2
NC
5
NC
VSS_SPMU_AMUX
BYPASS=UD850.6::5MM
SNSRES_DEV
1
CD850
0.1UF
10%
6.3V
2
CERM-X5R
0201
PLACE_NEAR=UE000.1:5MM
SNSRES_DEV
RD858
45.3K
1/20W
1
MF
201
2 1
NOSTUFF
RD859
100K
1/20W
201
WLANBT_1V8_ISENSE
1
1%
MF
2
SNSRES_DEV
1
CD859
2.2UF
20%
6.3V
2
X5R-CERM
0201
GND_EADC1_COM
OUT
48 30
45 46 48 30 45
101
105
LEFT AMP CURRENT SENSE (IALR)
GAIN: 200X, EDP: 4.0 A
RSENSE: 0.005 OR SHORT
VSENSE: 20 MV, RANGE: 6.6 A
SHORT APN: 998-07031
PPBUS_AON
NO_XNET_CONNECTION=1
SNSRES_DEV
RD820
107S00005
PPBUS_SPKRAMP_LEFT_ISNS
PLACE_NEAR=UD820.2:5MM
1
0.005
1%
1/3W
MF
0306
PLACE_NEAR=UD820.4:5MM
104 47 46 45 44
104 47 46 45 44
OUT
ISNS_SPKRAMPL_P
ISNS_SPKRAMPL_N
432
OUT
PP3V3_S2SW_SNS
PP3V3_S2SW_SNS
48
48
INA19 A3RSW
3
IN+
CRITICAL
4
IN-
SNSRES_DEV
7
ENABLE
VS
UD820
UQFN
100X
GND
OUT
REF
NC
NC
NC
1
2
10
SPKRAMPL_IOUT
8
1
NC
2
NC
5
NC
BYPASS=UD820.6::5MM
SNSRES_DEV
CD820
0.1UF
10%
6.3V
CERM-X5R
0201
PLACE_NEAR=UE000.6:5MM
SNSRES_DEV
RD828
45 3K
1%
1/20W
MF
201
2 1
NOSTUFF
RD829
SPKRAMPL_ISENSE
SNSRES_DEV
1
CD829
2.2UF
20%
6.3V
2
X5R-CERM
0201
100K
1%
1/20W
MF
201
1
2
GND_EADC1_COM
OUT
4 4 48
USB2 LEVEL SHIFTER 3.3V (UF750) CURRENT SENSE (IU3C)
GAIN: 100X, EDP: 0.029 A
RSENSE: 1.0 OR SHORT
104 47 46 45 44
PP3V3_S2SW_SNS
VSENSE: 29 MV, RANGE: 0.033 A
SHORT APN: 998-07031
PLACE_NEAR=UD860.2:8MM
104
48
105
PP3V3_S2SW_USB1
NO_XNET_CONNECTION=1
SNSRES_DEV
107S00147
PP3V3_S2SW_USBLS1_ISNS
RD860
1.0
1%
1/3W
MF
0306
104 47 46 45 44
48
OUT
1
ISNS_USBLS3V3_P
ISNS_USBLS3V3_N
432
PLACE_NEAR=UD860.4:8MM
OUT
48
PP3V3_S2SW_SNS
IN 190A3RSW
3
IN+
4
IN-
SNSRES_DEV
ENABLE
VS
UD860
UQFN
CRITICAL
100X
GND
OUT
REF
NC
NC
NC
10
INA_USBLS3V3_IOUT
8
1
NC
2
NC
5
NC
BYPASS=UD860.6::5MM
SNSRES_DEV
1
CD860
0.1UF
10%
6.3V
2
CERM-X5R
0201
PLACE_NEAR=UE000.16:5MM
SNSRES_DEV
RD868
4 3K
1/20W
1%
MF
201
2 1
NOSTUFF
RD869
100K
1%
1/20W
MF
201
USBLS_3V3_ISENSE
1
2
SNSRES_DEV
1
CD869
2.2UF
20%
6.3V
2
X5R-CERM
0201
GND_EADC1_COM
OUT
48
5 46 48
101
105
RIGHT AMP CURRENT SENSE (IARR)
GAIN: 200X, EDP: 4.0 A
RSENSE: 0.005 OR SHORT
VSENSE 20 MV, RANGE: 6.6 A
SHORT APN: 998-07031
PPBUS_AON
NO_XNET_CONNECTION=1
SNSRES_DEV
RD830
107S00005
PPBUS_SPKRAMP_RIGHT_ISNS
PLACE_NEAR=UD830.2:5MM
1
0.005
1%
1/3W
MF
0306
PLACE_NEAR=UD830 4:5MM
104 7 6 45 44
104 47 46 45 44
48
OUT
ISNS_SPKRAMPR_P
ISNS_SPKRAMPR_N
432
OUT
48
PP3V3_S2SW_SNS
PP3V3_S2SW_SNS
INA190A3RSW
3
IN+
CRITICAL
4
IN-
SNSRES_DEV
7
ENABLE
VS
UD830
UQFN
100X
GND
OUT
REF
NC
NC
NC
1
2
10
SPKRAMPR_IOUT
NO_TEST=1
8
1
NC
2
NC
5
NC
BYPASS=UD830.6::5MM
SNSRES_DEV
CD830
0.1UF
10%
6.3V
CERM-X5R
0201
PLACE_NEAR=UE020.6:5MM
SNSRES_DEV
RD838
45.3K
1%
1/20W
MF
201
2 1
NOSTUFF
RD839
SPKRAMPR_ISENSE
SNSRES_DEV
1
CD839
2.2UF
20%
6. V
X R CERM
0201
100K
1%
1/20W
MF
201
1
2
GND_EADC2_COM
OUT
45 47 48
USB2 LEVEL SHIFTER 1.8V (UF750) CURRENT SENSE (N/A)
GAIN: 100X, EDP: 0.158 A
RSENSE: 0.1 OR SHORT
104 47 46 45 44
PP3V3_S2SW_SNS
VSENSE: 15.8 MV, RANGE: 0.33 A
SHORT APN: 998-07031
PLACE_NEAR=UD870.2:8MM
101
48
105
PP1V8_S2
NO_XNET_CONNECTION=1
SNSRES_DEV
PP1V8_S2_USBLS1_ISNS
RD870
0.1
1%
0.5W
MF
107S00116
0306
4 47 46 45 44
48
OUT
1
ISNS_USBLS1V8_P
ISNS_USBLS1V8_N
432
PLACE_NEAR=UD870.4:8MM
OUT
48
PP3V3_S2SW_SNS
INA190A3RSW
3
IN+
4
IN-
SNSRES_DEV
7
ENABLE
VS
UD870
UQFN
CRITICAL
100X
GND
OUT
REF
NC
NC
NC
10
INA_USBLS1V8_IOUT
8
1
NC
2
NC
5
NC
BYPASS=UD870.6::5MM
SNSRES_DEV
1
CD870
0.1UF
10%
6.3V
2
CERM-X5R
0201
PLACE_NEAR=RE052.1:5MM
SNSRES_DEV
RD878
45.3K
1/20W
1%
MF
201
2 1
NOSTUFF
RD879
100K
1/20W
201
USBLS_1V8_ISENSE
1
1%
MF
2
SNSRES_DEV
1
CD879
2.2UF
20%
6.3V
X5R-CERM
0201
GND_EADC1_COM
OUT
45 46 48
48
104
105
KEYBOARD BACKLIGHT 5V CURRENT SENSE (IKBC)
GAIN: 200X, EDP: 0.23 A
RSENSE: 0.05 OR SHORT
VSENSE: 11.5 MV, RANGE: 0.33 A
SHORT AP : 9 8-07031
PP5V_S2
NO_XNET_CONNECTION=1
SNSRES_DEV
RD880
0.05
1/3W
0306
107S00017
PP5V_S2_KB LED_ISNS
104 47 46 45 44
104 47 46 45 4
PLACE_NEAR=UD880.2:5MM
48
OUT
1
1%
MF
ISNS_KBDLED_P
ISNS_KBDLED_N
432
PLACE_NEAR=UD880.4:5MM
OUT
48
PP3V3_S2SW_SNS
PP3V3_S2SW_SNS
3
IN+
4
IN-
7
VS
UD880
INA190A4IRSW
UQFN
CRITICAL
SNSRES_DEV
200X
ENABLE
GND
OUT
REF
NC
NC
NC
10
8
1
2
5
BYPASS=UD880.6::5MM
SNSRES_DEV
1
CD880
0.1UF
10%
6.3V
2
CERM-X5R
0201
INA_KBDLED_IOUT
NO_TEST=1
NC
NC
NC
PLACE_NEAR=UE000.5:5MM
SNSRES_DEV
RD888
45.3K
1/20W
1%
MF
201
2 1
NOSTUFF
RD889
100K
1/20W
KBDLED_5V_ISENSE
SNSRES_DEV
1
CD889
2 2UF
20%
6.3V
2
X5R-CERM
0201
1%
MF
201
1
2
GND_EADC1_COM
KEYBOARD 1.85V CURRENT SENSE (IK2C)
GAIN: 200X, EDP: 0.08 A
RSENSE: 0.1 OR SHORT
104 47 6 45 44
PP3V3_S2SW_SNS
VSENSE: 8 MV, RANGE: 0.165 A
SHORT APN: 998-07031
PP1V85_S2_IPD
NO_XNET_CONNECTION=1
SNSRES_DEV
RD890
OUT
104
48
0.1
0.5W
0306
107S00116
105
45 46 48 45 46 48
PP1V85_S2_KBD_ISNS
104 47 46 45 44
PLACE_NEAR=UD890.2:5MM
48
OUT
1
1%
MF
ISNS_KBD1V85_P
ISNS_KBD1V85_N
432
PLACE_NEAR=UD890.4:5MM
OUT
48
PP3V3_S2SW_SNS
INA190A4IRSW
3
IN+
4
IN-
SNSRES_DEV
7
ENABLE
VS
UD890
UQFN
CRITICAL
200X
GND
OUT
REF
NC
NC
NC
10
INA_KBD1V85_IOUT
8
1
NC
2
NC
5
NC
BYPASS=UD890.6::5MM
SNSRES_DEV
1
CD890
0.1UF
10%
6.3V
2
CERM-X5R
0201
PLACE_NEAR=UE000.4:5MM
SNSRES_DEV
RD898
45.3K
1/20W
1%
MF
201
2 1
NOSTUFF
RD899
100K
1/20W
201
KBD_1V85_ISENSE
1
1%
MF
2
SNSRES_DEV
1
CD899
2.2UF
20%
6.3V
2
X5R-CERM
0201
GND_EADC1_COM
OUT
48
BOM_COST_GROUP=SENSORS
CM TE E T M
PAGE TITLE
SENSORS: POWER LOW SIDE (1/2)
2
1
Page 47
TODO: UPDATE PLACE NEAR
w w w . t e k n i s i - i n d o n e s i a . c o m
4
LCD PANEL 5V CURRENT SENSE (IL5C)
GAIN: 200X, EDP: 0.1 A
RSENSE: 0.1 (RP621) OR SHORT
VSENSE: 10 MV, RANGE: 0.165 A
SHORT APN: 998-07031
48 69
IN
48 69
IN
104 47 46 45 44
104 47 46 45 44
ISNS_PP5V_SW_LCD_P
ISNS_PP5V_SW_LCD_N
PP3V3_S2SW_SNS
PP3V3_S2SW_SNS
INA190A4IRSW
3
IN+
4
IN-
7
ENABLE
VS
UD910
UQFN
CRITICAL
SNSRES_DEV
200X
GND
OUT
REF
NC
NC
NC
BYPASS=UD910.6::5MM
SNSRES_DEV
1
CD910
2
10
INA_LCD5V_IOUT
8
1
NC
2
NC
5
NC
0.1UF
10%
6.3V
CERM-X5R
0201
PLACE_NEAR=UE020.16:5MM
SNSRES_DEV
RD918
45.3K
1/20W
1%
MF
201
2 1
NOSTUFF
RD919
100K
1%
1/20W
MF
201
LCD_5V_ISENSE
SNSRES_DEV
1
2
1
CD919
2.2UF
20%
6.3V
2
X5R-CERM
0201
GND_EADC2_COM
OUT
TPAD 5V CURRENT SENSE (IT5C)
GAIN: 200X, EDP: 0.05 A
RSENSE: 0.1 OR SHORT
104 47 46 45 44
PP3V3_S2SW_SNS
VSENSE: 5 MV, RANGE: 0.165 A
SHORT APN: 998-07031
PLACE_NEAR=UD940.2:5MM
104
48
105
PP5V_S2
NO_XNET_CONNECTION=1
PP5V_S2_TPAD_ISNS
SNSRES_DEV
RD940
0.1
1%
0.5W
MF
107S00116
0306
104 47 46 45 44
48
OUT
1
ISNS_TPAD5V_P
ISNS_TPAD5V_N
432
PLACE_NEAR=UD940.4:5MM
OUT
48
PP3V3_S2SW_SNS
INA190A4IRSW
3
IN
4
IN-
SNSRES_DEV
7
ENABLE
VS
UD940
UQFN
CRITICAL
200X
GND
OUT
REF
NC
NC
NC
10
INA_TPAD5V_IOUT TPAD_5V_ISENSE
NO_TEST=1
8
1
NC
2
NC
5
NC
BYPASS=UD940.6::5MM
SNSRES_DEV
1
CD940
0.1UF
10%
6.3V
2
CERM-X5R
0201
PLACE_NEAR=UE020.2:5MM
SNSRES_DEV
RD948
45.3K
1/20W
1
MF
201
2 1
NOSTUFF
RD949
100K
1/20W
201
1%
MF
48
OUT
SNSRES_DEV
1
2
1
CD949
2.2UF
20%
6.3V
2
X5R-CERM
0201
GND_EADC2_COM
45 46 47 48 45 46 47 48
LCD PANEL 3.3/3.8V CURRENT SENSE (IL3C)
GAIN: 200X, EDP: 1.0 A
RSENSE: 0.01 (RP620) OR SHORT
VSENSE: 10 MV, RANGE: 1.65 A
SHORT APN: 998-07031
48 69
IN
48 69
IN
104 47 46 45 44
104 47 46 45 44
ISNS_PPPANEL_SW_LCD_P
ISNS_PPPANEL_SW_LCD_N
PP3V3_S2SW_SNS
PP3V3_S2SW_SNS
UD920
IN 1 0 4IRSW
3
IN+
CRITICAL
4
IN-
SNSRES_DEV
200X
7
E ABLE
VS
UQFN
GND
OUT
REF
NC
NC
NC
BYPASS=UD920.6::5MM
SNSRES_DEV
1
CD920
0.1UF
10%
6.3V
2
CERM-X5R
0201
PLACE_NEAR=UE020.1:5MM
RD928
10
INA_PPPANEL_IOUT LCD_3V3_ISENSE
8
1
NC
2
NC
5
NC
45.3K
1%
1/20W
MF
201
2 1
NOSTUFF
RD929
100K
1/20W
1%
MF
201
1
2
1
2
SNSRES_DEV
CD929
2.2UF
20%
6.3V
X5R-CERM
0201
GND_EADC2_COM
48
OUT
4 4 47 48
104
105
TPAD 3.3V S2 CURRENT SENSE (IT3C)
GAIN: 200X, EDP: 0.1 A
RSENSE: 0.1 OR SHORT
VSENSE: 10 MV, RANGE: 0.165 A
SHORT APN: 998-07031
PP3V3_S2_TPAD
NO_XNET_CONNECTION=1
SNSRES_DEV
RD950
107S00116
PP3V3_S2_TPAD_ISNS
104 47 46 45 44
0.1
1%
0.5W
MF
0306
104 47 46 45 44
PLACE_NEAR=UD950.2:5MM
OUT
1
ISNS_TPAD3V3_P
ISNS_TPAD3V3_N
432
PLACE_NEAR=UD950.4:5MM
OUT
PP3V3_S2SW_SNS
PP3V3_S2SW_SNS
4
48
INA190A4IRSW
3
IN+
CRITICAL
4
IN-
SNSRES_DEV
7
ENABLE
VS
UD950
UQFN
200X
GND
OUT
REF
NC
NC
NC
10
8
1
2
5
NO_TEST=1
NC
NC
NC
BYPASS=UD950.6::5MM
SNSRES_DEV
1
CD950
0.1UF
10%
6.3V
2
CERM-X5R
0201
PLACE_NEAR=UE020.3:5MM
SNSRES_DEV SNSRES_DEV
RD958
4 3K
1/20W
1%
MF
201
2 1
NOSTUFF
RD959
100K
1/20W
201
1%
MF
TPAD_3V3_ISENSE INA_TPAD3V3_IOUT
OUT
48
SNSRES_DEV
1
2
1
CD959
2.2UF
20%
6.3V
2
X5R-CERM
0201
GND_EADC2_COM
5 46 47 48
104
105
ALSCAM 5V CURRENT SENSE (ICMC)
GAIN: 200X, EDP: 0.1 A
RSENSE: 0.1 OR SHORT
VSENSE: 10MV, RANGE: 0.165 A
SHORT APN: 998-07031
PP5V_S2
NO_XNET_CONNECTION=1
SNSRES_DEV
RD930
107S00116
PP5V_S2_ALSCAM_ISNS
104 47 6 45 44
0.1
1%
0.5W
MF
0306
104 47 46 45 44
PLACE_NEAR=UD930.3:8MM
OUT
1
ISNS_ALSCAM_P
ISNS_ALSCAM_N
432
PLACE_NEAR=UD930.4:8MM
OUT
PP3V3_S2SW_SNS
PP3V3_S2SW_SNS
48
48
UD930
INA190A4IRSW
3
IN+
CRITICAL
4
IN-
SNSRES_DEV
200X
7
ENABLE
VS
UQFN
GND
OUT
REF
NC
NC
NC
BYPASS=UD930.6 :5MM
SNSRES_DEV
1
CD930
0.1UF
10%
6.3V
2
CERM-X5R
0201
10
INA_ALSCAM_IOUT
8
1
NC
2
NC
5
NC
PLACE_NEAR=UE020.5:5MM
SNSRES_DEV
RD938
45.3K
1/20W
1%
MF
201
2 1
NOSTUFF
RD939
100K
1/20W
201
ALSCAM_5V_ISENSE
1
1%
MF
2
SNSRES_DEV
1
CD939
2.2UF
20%
6. V
X R CERM
0201
GND_EADC2_COM
48
OUT
45 46 47 48
104
105
TPAD 1.85V S2 CURRENT SENSE (IT2C)
GAIN: 100X, EDP: 0.372 A
RSENSE: 0.05 OR SHORT
VSENSE: 18.6 MV, RANGE: 0.66 A
SHORT APN: 998-07031
PP1V85_S2_IPD
NO_XNET_CONNECTION=1
SNSRES_DEV
RD960
0.05
107S00017
PP1V85_S2_TPAD_ISNS
47 46 45 44
1%
1/3W
MF
0306
104 47 46 45 44
PLACE_NEAR=UD960.2:5MM
OUT
1
ISNS_TPAD1V85_P
ISNS_TPAD1V85_N
432
PLACE_NEAR=UD960.4:5MM
OUT
PP3V3_S2SW_SNS
PP3V3_S2SW_SNS
48
48
INA190A3RSW
3
IN+
CRITICAL
4
IN-
SNSRES_DEV
7
ENABLE
UD960
100X
VS
UQFN
GND
OUT
REF
NC
NC
NC
BYPASS=UD960.6::5MM
SNSRES_DEV
1
CD960
0.1UF
10%
6.3V
2
CERM-X5R
0201
PLACE_NEAR=UE020.4:5MM
SNSRES_DEV
RD968
10
INA_TPAD1V85_IOUT TPAD_1V85_ISENSE
NO_TEST=1
8
1
2
5
45.3K
1%
1/20W
MF
2 1
NOSTUFF
RD969
100K
1/20W
1%
MF
201
SNSRES_DEV
1
2
1
CD969
2.2UF
20%
6.3V
2
X5R-CERM
0201
GND_EADC2_COM
48
OUT
45 46 47 48
BOM_COST_GROUP=SENSORS
CM TE E T M
PAGE TITLE
SENSORS: POWER LOW SIDE (2/2)
2
1
Page 48
104 48
w w w . t e k n i s i - i n d o n e s i a . c o m
48 43
48 43
104 48
PP3V3_S2SW_SNS
1
CE010
1.0UF
20%
6.3V
2
X5R
0201-1
SNSRES_DEV
I2C_EADC_3V3_SDA
PLACE_NEAR=UE010:10MM
I2C_EADC_3V3_SCL
PLACE_NEAR=UE010:10MM
PP3V3_S2SW_SNS
PLACE_NEAR=UE010:10MM
PLACE_N A =UE010:10MM
UE010
REF3325AIRSE
UQFN
SNSRES_DEV
5
IN OUT
PPE001
P4MM
SM
1
PP
PPE002
P4MM
SM
1
PP
PPE003
P4MM
SM
1
PP
PPE004
P4MM
SM
1
PP
8
1
NC0
NC1
NC2
NC3
NC4
NC
2
NC
3
NC
6
NC
7
NC
48
48
8
48
48
48
48
48
ATC3V3_HS_ISENSE
USBLS_3V3_ISENSE
WLANBT_1V8_ISENSE
MESA_HS_ISENSE
EADC1_AIN5
KBDLED_5V_ISENSE
SPKRAMPL_ISENSE
GND_EADC1_COM
PP2V5_S2SW_EADC1_AVREF
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=2.5V
1
CE001
1.0UF
20%
6.3V
2
X5R
0201-1
SNSRES_DEV
15 11
16
1
2
3
4
5
XWE000
SM
2 1
PLACE_NEAR=UE000.9:5MM
AVDD DVDD DECAP
UE000
TLA2528
AIN0/GPIO0
AIN1/GPIO1
AIN2/GPIO2
AIN3/GPIO3
AIN4/GPIO4
AIN5/GPIO5
AIN6/GPIO6
AIN7/GPIO7
EPAD GND
VOLTAGE=1.8
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
PP3V3_S2SW_SNS
WQFN
ADDR
SDA
SCL
NC
14
13
12 6
PLACE_NEAR=UE000.8:5MM PLACE_NEAR=UE020.8:5MM
1
CE002
1.0UF
20%
6.3V
2
X5R
0201-1
SNSRES_DEV
LACE_NEAR=UE000.10:5MM
1
CE003
1 0UF
20%
6.3V
2
X5R
0201-1
SNSRES_DEV
EADC1_ADDR
I2C_EADC_3V3_SDA
I2C_EADC_3V3_SCL DFR_HS_ISENSE
NC
PULL UP TO DECAP WITH 0 OHM: I2C ADDR = 0B0010_1110 PULL UP TO DECAP WITH 0 OHM: I2C ADDR = 0B0010_1110
PULL DOWN TO GND WITH 0 OHM: I2C ADDR = 0B0010_0000 PULL DOWN TO GND WITH 0 OHM: I2C ADDR = 0B0010_0000
EADC2 (ADDR WR:0X20 RD: 0X21 [7BIT 0X10]) EADC1 (ADDR WR:0X2E RD: 0X2F [7BIT: 0X17])
PPDECAP_EADC2 PPDECAP_EADC1
VOLTAGE=1.8
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
UE030
REF3325AIRSE
UQFN
SNSRES_DEV
NC0
NC1
NC2
NC3
NC4
8
1
NC
2
NC
3
NC
6
NC
7
NC
PP2V5_S2SW_EADC2_AVREF
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=2.5V
1
CE021
1.0UF
20%
6.3V
2
X5R
0201-1
SNSRES_DEV
PP3V3_S2SW_SNS
AVDD DVDD DECAP
UE020
TLA2528
WQFN
48
48
48
48
48
48
48
LCDBKLT_HS_ISENSE
LCD_5V_ISENSE
LCD_3V3_ISENSE
TPAD_3V3_ISENSE
8
TPAD_1V85_ISENSE
ALSCAM_5V_ISENSE
SPKRAMPR_ISENSE
PLACE_NEAR UE020.9:5MM
XWE020
SM
15 11
AIN0/GPIO0
16
AIN1/GPIO1
1
AIN2/GPIO2
2
AIN3/GPIO3
3
AIN4/GPIO4
4
AIN5/GPIO5
5
AIN6/GPIO6
AIN7/GPIO7
2 1
SNSRES_DEV SNSRES_DEV
EPAD GND
ADDR
SDA
SCL
NC
14
13
12 6
EADC2_ADDR
I2C_EADC_3V3_SDA
I2C_EADC_3V3_SCL TPAD_5V_ISENSE
NC
104 48
104 48
1
RE005
0
5%
1/20W
MF
0201
2
BI
IN
43 48
43 48
NOSTUFF
1
RE006
0
5%
1/20W
MF
201
2
PP3V3_S2SW_SNS
1
CE020
1.0UF
2 %
6.3V
2
X5R
0201-1
SNSRES_DEV
5
IN OUT
45 46 47 45 46
GND_EADC2_COM
1
CE022
1.0UF
20%
6.3V
2
X5R
0201-1
SNSRES_DEV
104
PLACE_NEAR=UE020.10:5MM
1
CE023
1.0UF
20%
6.3V
2
X5R
0201-1
SNSRES_DEV
BI
IN
43
43
NOSTUFF
1
RE025
0
5%
1/20W
MF
201
2
1
RE026
0
5%
1/20W
MF
0201
2
EADC1 AIN ALIAS
45
IN
46
IN
46
IN
45
IN
45
IN
46
IN
46
IN
46
IN
46
IN
ATC3V3_HS_ISENSE
MAKE_BASE=TRUE
NO_TEST=1
USBLS_3V3_ISENSE
MAKE_BASE=TRUE
WLANBT_1V8_ISENSE
MAKE_BASE=TRUE
NO_TEST=1
DFR_HS_ISENSE
MAKE_BASE=TRUE
NO_TEST=1
MESA_HS_ISENSE
MAKE_BASE=TRUE
NO_TEST=1
KBDLED_5V_ISENSE
MAKE_BASE=TRUE
NO_TEST=1
SPKRAMPL_ISENSE
MAKE_BASE=TRUE
NO_TEST=1
NO_TEST=1
PLACE_NEAR=UE000.4:5MM
USBLS_1V8_ISENSE
NO_TEST=1
1/20W
1/20W
EADC2 AIN ALIAS
45
IN
47
IN
47
IN
47
IN
47
IN
47
IN
47
IN
46
IN
LCDBKLT_HS_ISENSE
MAKE_BASE=TRUE
NO_TEST=1
LCD_5V_ISENSE
AKE_BASE=TRUE
NO_TEST=1
LCD_3V3_ISENSE
MAKE_BASE=TRUE
NO_TEST=1
TPAD_5V_ISENSE
MAKE_BASE=TRUE
NO_TEST=1
TPAD_3V3_ISENSE
MAKE_BASE=TRUE
NO_TEST=1
TPAD_1V85_ISENSE
MAKE_BASE=TRUE
NO_TEST=1
ALSCAM_5V_ISENSE
AKE_BASE=TRUE
NO_TEST=1
SPKRAMPR_ISENSE
MAKE_BASE=TRUE
NO_TEST=1
RE051
0
5% MF
RE052
0
NOSTUFF
ATC3V3_HS_ISENSE
USBLS_3V3_ISENSE
WLANBT_1V8_ISENSE
DFR_HS_ISENSE
MESA_HS_ISENSE
KBDLED_5V_ISENSE
SPKRAMPL_ISENSE
2 1
0201
2 1
0201 MF 5%
EADC1_AIN5 KBD_1V85_ISENSE
NO_TEST=1
LCDBKLT_HS_ISENSE
LCD_5V_ISENSE
LCD_3V3_ISENSE
TPAD_5V_ISENSE
TPAD_3V3_ISENSE
TPAD_1V85_ISENSE
ALSCAM_5V_ISENSE
SPKRAMPR_ISENSE
POWER VALIDATION TEST POINTS (WIP)
48
48
48
44
IN
44
IN
ISNS_3V8AONHS_P
TP-P5
ISNS_3V8AONHS_N
TP-P5
1
TP
TPE002
1
TP
PLACE_SIDE=TOP
PLACE_NEAR=RD540.3:5MM
PLACE_SIDE=TOP
PLACE_NEAR=RD540.4:5MM
45 71 47
45 71
ISNS_LCDBKLT_P
IN
ISNS_LCDBKLT_N
IN
TPE003
TPE001
44
48
IN
ISNS_5VS2HS_P
TP-P5
1
TP
PLACE_SIDE=TOP
PLACE_NEAR=RD550.3:5MM
46
ISNS_WLBT3V3_P
IN
TPE004
48
48
48
44
IN
44
IN
ISNS_5VS2HS_N
TP-P5
ISNS_3V3S2HS_P
TP-P5
1
TP
TPE005
1
TP
PLACE_SIDE=TOP
PLACE_NEAR=RD550.4:5MM
PLACE_SIDE=TOP
PLACE_NEAR=RD560.3:5MM
46
46
ISNS_WLBT3V3_N
IN
ISNS_SPKRAMPL_P
IN
TPE006
44
IN
ISNS_3V3S2HS_N
TP-P5
1
TP
PLACE_SIDE=TOP
PLACE_NEAR=RD560.4:5MM
46
ISNS_SPKRAMPL_N
IN
TPE007
44 101
48
IN
PPDCIN_USBC_AON
TP-P5
1
TP
PLACE_SIDE=TOP
PLACE_NEAR=RD501.1:5MM
46
ISNS_SPKRAMPR_P
IN
TPE008
TP-P5
1
TP
PLACE_SIDE=TOP
PLACE_NEAR=RD502.2:5MM PLACE_NEAR=UE000.4:5MM
46
ISNS_SPKRAMPR_N
IN
TPE009
2 44
IN
CHGR_AMON
TP-P5
1
TP
PLACE_SIDE=TOP
46
ISNS_KBDLED_P
IN
TPE010
TP-P5
1
TP
PLACE_SIDE=TOP
PLACE_NEAR=TPE009.1:5MM
46
ISNS_KBDLED_N
IN
TPE011
22 44
IN
CHGR_BMON
TP-P5
1
TP
PLACE_SIDE=TOP
46
ISNS_WLBT1V8_P
IN
TPE012
48
48
IN
48
48
PBUS_VSNS_OUT
TP-P5
TP-P5
TP-P5
1
TP
TPE013
1
TP
TPE014
1
TP
PLACE_SIDE=TOP
PLACE_NEAR=TPE011.1:5MM
PLACE_SIDE=TOP
PLACE_NEAR=RD538.1:10MM
PLACE_SIDE=TOP
PLACE_NEAR=TPE013.1:5MM
46
46
46
ISNS_WLBT1V8_N
IN
ISNS_USBLS3V3_P
IN
ISNS_USBLS3V3_N
IN
TPE015
45
48
IN
ISNS_MPMUHS_P
TP-P5
1
TP
PLACE_SIDE=TOP
PLACE_NEAR=RD610.3:10MM
46
ISNS_USBLS1V8_P
IN
TPE016
48
48
48
45
IN
45
IN
ISNS_MPMUHS_N
TP-P5
ISNS_SPMUHS_P
TP-P5
1
TP
TPE017
1
TP
PLACE_SIDE=TOP
PLACE_NEAR=RD610.4:10MM
PLACE_SIDE=TOP
PLACE_NEAR=RD620.3:5MM
46
46
ISNS_USBLS1V8_N
IN
ISNS_KBD1V85_P
IN
TPE018
45
ISNS_SPMUHS_N
N
P P5
1
TP
PLACE_SIDE=TOP
PLACE_NEAR=RD620.4:5MM
46
ISNS_KBD1V85_N
IN
TPE019
45
IN
ISNS_ATCHS_P
TP-P5
1
TP
PLACE_SIDE=TOP
PLACE_NEAR=RD690.3:5MM
47 69
ISNS_PP5V_SW_LCD_P
IN
TPE025
1
TP-P5 TP-P5
TP
PLACE_SIDE=TOP
PLACE_NEAR=RP800.4:5MM
IN
ISNS_TPAD5V_P
TPE026
TP-P5
1
TP
PLACE_SIDE=TOP
PLACE_NEAR=RP800.3:5MM
47
IN
ISNS_TPAD5V_N
TPE027
TP-P5
1
TP
PLACE_SIDE=TOP
PLACE_NEAR=RD810.3:5MM
47
IN
ISNS_TPAD3V3_P
TPE028
TP-P5
1
TP
PLACE_SIDE=TOP
PLACE_NEAR=RD810.4:5MM
47
IN
ISNS_TPAD3V3_N
TPE029
TP-P5
1
TP
PLACE_SIDE=TOP
PLACE_NEAR=RD820.3:5MM
47
IN
ISNS_TPAD1V85_P
TPE030
TP-P5
1
TP
PLACE_SIDE=TOP
PLACE_NEAR=RD820.4:5MM
47
IN
ISNS_TPAD1V85_N
TPE031
TP-P5
1
TP
PLACE_SIDE=TOP
PLACE_NEAR=RD830.3:5MM
22
IN
CHGR_CSI_P
TPE032
TP-P5
1
TP
PLACE_SIDE=TOP
PLACE_NEAR=RD830.4:5MM
22
IN
CHGR_CSI_N
TPE033
TP-P5
1
TP
PLACE_SIDE=TOP
PLACE_NEAR=RD880.3:5MM
22
IN
CHGR_CSO_P
TPE034
TP-P5
1
P
PLACE_SIDE=TOP
PLACE_NEAR=RD880.4:5MM
22
IN
CHGR_CSO_N
TPE035
TP-P5
1
TP
PLACE_SIDE=TOP
PLACE_NEAR=RD850.3:5MM
TPE036
TP-P5
1
TP
PLACE_SIDE=TOP
PLACE_NEAR=RD850.4:5MM
PROBE POINTS
TPE037
TP-P5
1
TP
PLACE_SIDE=TOP
PLACE_NEAR=RD860.3:10MM
13 1 1
PPVDD_CPU_SRAM_AWAKE
IN
TPE038
TP-P5
TPE039
TP-P5
TPE040
TP-P5
1
P
1
TP
1
TP
PLACE_SIDE=TOP
PLACE_NEAR=RD860.4:10MM
PLACE_SIDE=TOP
PLACE_NEAR=RD870.4:10MM
PLACE_SIDE=TOP
PLACE_NEAR=RD870.3:10MM
13 101
14 102
PP0V764_S1_SRAM
IN
PP0V72_S2_VDD_LOW
IN
TPE041
TP-P5
1
TP
PLACE_SIDE=TOP
PLACE_NEAR=RD890.3:10MM
TPE042
TP-P5
1
TP
PLACE_SIDE=TOP
PLACE_NEAR=RD890.4:10MM
TPE043
TP-P5
1
TP
PLACE_SIDE=TOP
PLACE_NEAR=RP621.3:5MM
TPE049
TPE050
TP-P5
TPE051
TP-P5
TPE052
TP-P5
TPE053
TP-P5
TPE054
TP-P5
TPE055
TP-P5
TPE056
TP-P5
TPE057
TP-P5
TPE058
TP-P5
1
TP
1
TP
1
TP
1
TP
1
TP
1
TP
1
TP
1
TP
1
TP
1
P
PLACE_SIDE=TOP
PLACE_NEAR=RD940.3:5MM
PLACE_SIDE=TOP
PLACE_NEAR=RD940.4:5MM
PLACE_SIDE=TOP
PLACE_NEAR=RD950.3:10MM
PLACE_SIDE=TOP
PLACE_NEAR=RD950.4:10MM
PLACE_SIDE=TOP
PLACE_NEAR=RD960.3:5MM
PLACE_SIDE=TOP
PLACE_NEAR=RD960.4:5MM
PLACE_SIDE=TOP
PLACE_NEAR=R5220.3:15MM
PLACE_SIDE=TOP
PLACE_NEAR=R5220.4:15MM
PLACE_SIDE=TOP
PLACE_SIDE=TOP
PLACE_NEAR=TPE057.1:5MM
PPE0B1
P4MM
SM
1
PPE0B2
P4MM
1
PPE0B3
P4MM
1
PLACE_SIDE=TOP
PP
SM
PLACE_SIDE=TOP
PP
SM
PLACE_SIDE=TOP
PP
SOC SENSE LINES
11 45
IN
1 45
IN
11 45
IN
11 45
IN
1 45
IN
11
N
11
IN
11
IN
11
IN
11
IN
11
IN
1
IN
11
IN
VSNS_VDD_PCPU
VSNS_VSS_PCPU
VSNS_VDD_GPU
NO_TEST=1
VSNS_VDD_SOC
NO_TEST=1
VSNS_VDD_ECPU
VSNS_VDD_DISP
NO_TEST=1
VSNS_VDD2_1
NO_TEST=1
VSNS_VSS_1
NO_TEST=1
VSNS_VDD2_2
VSNS_VSS_2
VSNS_VDD_DCS
NO_TEST=1
VSNS_VSS_DDR
NO_TEST=1
VSNS_VDDQL
NO_TEST=1
PPE0AE
P4MM
SM
1
PPE0AF
P4MM
1
PLACE_NEAR=PPE0A3:2MM
PLACE_SIDE=TOP
PP
SM
PLACE_SIDE=TOP
PP
PPE0A1
P4MM
SM
1
PPE0A2
P4MM
1
PPE0A3
P4MM
1
PPE0A4
P4MM
1
PPE0A5
P4MM
1
PPE0A6
P4MM
1
PPE0A7
P4MM
1
PPE0A8
P4MM
1
PPE0A9
P4MM
1
PPE0AA
P4MM
1
PPE0AB
P4MM
1
PPE0AC
P4MM
1
PPE0AD
P4MM
1
PLACE_SIDE=TOP
PP
SM
PLACE_SIDE=TOP
PP
SM
PLACE_SIDE=TOP
PP
SM
PLACE_SIDE=TOP
PP
SM
PLACE_SIDE=TOP
PP
SM
PLACE_SIDE=TOP
PP
SM
PLACE_SIDE=TOP
PP
SM
PLACE_SIDE=TOP
PP
SM
PLACE_SIDE=TOP
PP
SM
PLACE_SIDE=TOP
PP
SM
PLACE_SIDE=TOP
PP
SM
PLACE_SIDE=TOP
PP
SM
PLACE_SIDE=TOP
PP
TPE020
45
IN
ISNS_ATCHS_N
TP-P5
1
TP
PLACE_SIDE=TOP
PLACE_NEAR=RD690.4:5MM
47 69
ISNS_PP5V_SW_LCD_N
IN
TPE021
45
IN
ISNS_DFRHS_P
TP-P5
1
TP
PLACE_SIDE=TOP
PLACE_NEAR=RD6A0.3:10MM
47 69
ISNS_PPPANEL_SW_LCD_P
IN
TPE022
45
IN
ISNS_DFRHS_N
TP-P5
1
TP
PLACE_SIDE=TOP
PLACE_NEAR=RD6A0.4:10MM
47 69
ISNS_PPPANEL_SW_LCD_N
IN
TPE023
45
IN
ISNS_MESAHS_P
TP-P5
1
TP
PLACE_SIDE=TOP
PLACE_NEAR=RD6B0.3:5MM
47
ISNS_ALSCAM_P
IN
TPE024
5
IN
ISNS_MESAHS_N
TP-P5
1
TP
PLACE_SIDE=TOP
PLACE_NEAR=RD6B0.4:5MM
47
ISNS_ALSCAM_N
IN
TPE044
TP-P5
TPE045
TP-P5
TPE046
TP-P5
TPE047
TP-P5
TPE048
TP-P5
1
TP
1
TP
1
TP
1
TP
1
TP
PLACE_SIDE=TOP
PLACE_NEAR=RP621.4:5MM
PLACE_SIDE=TOP
PLACE_NEAR=RP620.3:5MM
PLACE_SIDE=TOP
PLACE_NEAR=RP620.4:5MM
PLACE_SIDE=TOP
PLACE_NEAR=RD930.3:5MM
PLACE_SIDE=TOP
PLACE_NEAR=RD930.4:5MM
CM TE E T M
PAGE TITLE
SENSORS: POWER SUPPORT
BOM_COST_GROUP=SENSORS
2
1 7 8
Page 49
MASTER PMU TDEV1 [TMVR]
w w w . t e k n i s i - i n d o n e s i a . c o m
MASTER PMU TDEV6 [TW0P] SLAVE PMU TDEV1 [TPSP]
LOCATION: SLAVE PMU, BUCK10 INDUCTOR PROXIMITY LOCATION: WLANBT, BACKSIDE LOCATION: 3.8V AON VR BETWEEN PHASE 2 AND PHASE3 MOSFETS
THMSNS_MPMU1_P
NO_TEST=1
1
CRITICAL
RE111
10KOHM-1%-0.31MA
0201
2
NO_TEST=1
PLACE_NEAR=U8100.E8:15MM
1
CE111
100PF
5%
25V
2
C0G
0201
MASTER PMU TDEV2 [TSDD]
LOCATION: SOC DRAM AREA, BACKSIDE (TOP)
THMSNS_MPMU2_P
NO_TEST=1 NO_TEST=1
1
CRITICAL
RE121
10KOHM-1%-0.31MA
0201
2
THMSNS_MPMU2_N
NO_TEST=1
PLACE_NEAR=U8100.F9:15MM
1
CE121
100PF
5%
25V
2
C0G
0201
XWE111
SM
2 1
NO_XNET_CONNECTION=1
XWE112
SM
2 1
NO_XNET_CONNECTION=1
XWE121
SM
2 1
NO_XNET_CONNECTION=1
XWE122
SM
2 1
NO_XNET_CONNECTION=1
P3V8AONVR_THMSNS
THMSNS_MPMU_VSS THMSNS_MPMU1_N
SOC_THMSNS1
THMSNS_MPMU_VSS
XWE161
SM
SM
SM
2 1
M
2 1
WLANBT_THMSNS
THMSNS_MPMU_VSS
49
SLAVE PMU TDEV2 [TaMP]
LOCATION: MLB AIR INTAKE PROXIMITY
2 1
2 1
MPMU_THMSNS
THMSNS_MPMU_VSS
49
49
49
49
THMSNS_MPMU6_P
1
CRITICAL
RE161
10KOHM-1%-0.31MA
0201
2
THMSNS_MPMU6_N
NO_XNET_CONNECTION=1
PLACE_NEAR=U8100.G10:15MM
1
CE161
100PF
5%
25V
2
C0G
0201
NO_XNET_CONNECTION=1
XWE162
MASTER PMU TDEV7 [TPMP]
LOCATION: MASTER PMU, BETWEEN BUCK0 AND BUCK1 INDUCTORS
XWE171
49
49
THMSNS_MPMU7_P
1
CRITICAL
RE171
10KOHM-1%-0.31MA
0201
2
THMSNS_MPMU7_N
NO_TEST=1
PLACE_NEAR=U8100.G8:15MM
1
CE171
100PF
5%
25V
2
C0G
0201
NO_XNET_CONNECTION=1
XWE172
NO_XNET_CONNECTION=1
THMSNS_SPMU1_P
NO_TEST=1
1
CRITICAL
RE1B1
10KOHM-1%-0.31MA
0201
2
THMSNS_SPMU1_N
NO_TEST=1
THMSNS_SPMU2_P
1
CRITICAL
RE1C1
10KOHM-1%-0.31MA
0201
2
THMSNS_SPMU2_N
PLACE_NEAR=U7700.A6:5MM
1
CE1B1
100PF
5%
25V
2
C0G
0201
PLACE_NEAR=U7700.A5:5MM
1
CE1C1
100PF
5%
25V
2
C0G
0201
XWE1B1
SM
2 1
NO_XNET_C NNEC ION=1
XWE1B2
SM
2 1
NO_XNET_CONNECTION=1
XWE1C1
SM
2 1
NO_XNET_CONNECTION=1
XWE1C2
SM
2 1
NO_XNET_CONNECTION=1
SPMU_THMSNS
THMSNS_SPMU_VSS
AMB_THMSNS
THMSNS_SPMU_VSS
49
49 49
49
49
MASTER PMU TDEV3 [TSCD]
LOCATION: SOC CORE AREA BACKSIDE (TOP)
THMSNS_MPMU3_P SOC_THMSNS3
NO_TEST=1
1
CRITICAL
RE131
10KOHM-1%-0.31MA
0201
2
NO_TEST=1
PLACE_NEAR=U8100.F8:15MM
1
CE131
100PF
5%
25V
2
C0G
0201
MASTER PMU TDEV4 & TDEV5
LOCATION: DOES NOT EXIST
XWE131
SM
2 1
NO_XNET_CONNECTION=1
XWE132
SM
2 1
NO_XNET_CONNECTION=1
THMSNS_MPMU_VSS THMSNS_MPMU3_N
MASTER PMU TDEV8 [TCHP]
LOCATION: CHARGER, BETWEEN INDUCTOR AND MOSFETS
XWE181
SM
SM
2 1
2 1
CHGR_THMSNS
THMSNS_MPMU_VSS
49
49
49
49
THMSNS_MPMU8_P
1
CRITICAL
RE181
10KOHM-1%-0.31MA
0201
2
THMSNS_MPMU8_N
PLACE_NEAR=U8100.G7:15MM
1
CE181
100PF
5%
25V
2
C0G
0201
NO_XNET_CONNECTION=1
XWE182
NO_XNET_CONNECTION=1
SLAVE PMU TDEV3 [TH0T]
LOCATION: LOWER LEFT CORNER OF NAND DEVICES
THMSNS_SPMU3_P
NO_TEST=1
1
CRITICAL
RE1D1
10KOHM-1%-0.31MA
0201
2
THMSNS_SPMU3_N
NO_TEST=1
PLACE_NEAR=U7700.B8:5MM
1
CE1D1
100PF
5%
25V
2
C0G
0201
XWE1D1
SM
2 1
NO_XNET_CONNECTION=1
XWE1D2
SM
2 1
NO_XNET_CONNECTION=1
NAND0_THMSNS
THMSNS_SPMU_VSS
49
49
SLAVE PMU TDEV4 [TH0B]
LOCATION: UPPER RIGHT CORNER OF NAND DEVICES
PMU TDEV MAPPING
49
49
49
P3V8AONVR_THMSNS
MAKE_BASE=TRUE
NO_TEST=1
SOC_THMSNS1
MAKE_BASE=TRUE
NO_TEST=1
SOC_THMSNS3
MAKE_BASE=TRUE
NO_TEST=1
NC_MPMU_TDEV4
MAKE_BASE=TRUE
NO_TEST=1
NC_MPMU_TDEV5
MAKE_BASE=TRUE
49
49
49
WLANBT_THMSNS
MAKE_BASE=TRUE
MPMU_THMSNS
MAKE_BASE=TRUE
CHGR_THMSNS
MAKE_BASE=TRUE
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
P3V8AONVR_THMSNS
SOC_THMSNS1
SOC_THMSNS3
NC_MPMU_TDEV4
NC_MPMU_TDEV5
WLANBT_THMSNS
MPMU_THMSNS
CHGR_THMSNS
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
33
33
33
33
33
33
33
33
TAP NEGATIVE CLOSE TO VSS_REF
ADDED OPTION PER RDAR://60203428
NOSTUFF
RE100
49 49
THMSNS_MPMU_VSS
1 20
0
PLACE_NEAR=U8100.J11:5MM
2 1
MF 5%
0201
XWE1E1
SM
SM
SM
SM
2 1
2 1
2 1
2 1
NAND1_THMSNS
THMSNS_SPMU_VSS
FINSTACK_THMSNS
THMSNS_SPMU_VSS
49
49
49
49
THMSNS_SPMU4_P
NO_TEST=1
1
CRITICAL
RE1E1
49
49
49
49
49
SPMU_THMSNS
MAKE_BASE=TRUE
AMB_THMSNS
MAKE_BASE=TRUE
NAND0_THMSNS
MAKE_BASE=TRUE
NAND1_THMSNS
MAKE_BASE=TRUE
FINSTACK_THMSNS
MAKE_BASE=TRUE
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
NO_TEST=1
SPMU_THMSNS
AMB_THMSNS
NAND0_THMSNS
NAND1_THMSNS
FINSTACK_THMSNS
OUT
OUT
OUT
OUT
OUT
29
29
29
29
SLAVE PMU TDEV5 [Th1H]
29
LOCATION: FINSTACK PROXIMITY
10KOHM-1%-0.31MA
0201
2
THMSNS_SPMU4_N
NO_TEST=1
PLACE_NEAR=U7700.B7:5MM
1
CE1E1
100PF
5%
25V
2
C0G
0201
NO_XNET_CONNECTION=1
XWE1E2
NO_XNET_CONNECTION=1
XWE1F1
THMSNS_SPMU5_P
NOSTUFF
PLACE_NEAR=U7700.C6:5MM
NO_TEST=1
1
CRITICAL
RE1F1
10KOHM-1%-0.31MA
0201
2
THMSNS_SPMU5_N
NO_TEST=1
PLACE NEAR=U7700.B6:5MM
1
CE1F1
100PF
5%
25V
2
C0G
0201
NO_XNET_CONNECTION=1
XWE1F2
NO_XNET_CONNECTION=1
RE1A0
0
THMSNS_SPMU_VSS
1/20W
2 1
0201 MF 5%
PAGE TITLE
C TE CM TE E T M
SENSORS: THERMAL (1/2)
RE101
1/20W
RE1A1
0
2 1
VSS_ANA_MPMU
0201 MF 5%
34 33 32
0
5% 1/20W
2 1
MF 0201
VSS_ANA_SPMU
30 29
BOM_COST_GROUP=SENSORS
2
1
Page 50
RETIMER ATC0 [TT0D] I/O PROXIMITY [TIOP]
w w w . t e k n i s i - i n d o n e s i a . c o m
LOCATION: ON CHIP
53
IN
53
IN
ATCRTMR0_THERM_D_P THMSNS_D1
1
2
ATCRTMR0_THERM_D_N
RETIMER ATC1 [TT1D]
LOCATION: ON CHIP
54
IN
1
2
54
IN
ATCRTMR1_THERM_D_N
PLACE_NEAR=UE200.6:5MM
NO_XNET_CONNECTION=1
CE211
2200PF
10%
10V
X7R-CERM
0201
NO_XNET_CONNECTION=1
PLACE_NEAR=UE200.5:5MM
NO_XNET_CONNECTION=1
CE221
2200PF
10%
10V
X7R-CERM
0201
NO_XNET_CONNECTION=1
XWE211
SM
2 1
XWE212
SM
2 1
XWE221
SM
2 1
XWE222
SM
2 1
THMSNS_COM
THMSNS_D2 ATCRTMR1_THERM_D_P
THMSNS_COM
I2C ADDR WR:0X90 RD: 0X91
LOCATION: TBD
50
50
104 43
UNUSED CHANNELS CONNECT TO D-
50
50
PP3V3_S2SW_SNS
PLACE_NEAR=UE200.14:5MM
RE201
0
2 1
5%
1/20W
MF
0201
THMSNS_D1
50
THMSNS_D2
50
THMSNS_COM
50
THMSNS_COM
50
THMSNS_COM
50
THMSNS_ADDR_SEL
1
RE202
100K
5%
1/20W
MF
201
2
1
2
PP3V3_S2SW_THMSNS_R
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=3.3V
CE201
0.1UF
10%
6.3V
CERM-X5R
0201
6
5
4
3
7
9
D1+
D2+
D3+
D4+
D-
ADD
V+
UE200
TMP464
VQFN
CRITICAL
EPAD
GND
SCL
SDA
THERM2*
THERM*
NC1
NC0
NC3
NC2
13
12
11
10
2
1
16
15
I2C_THMSNS_3V3_SCL
I2C_THMSNS_3V3_SDA
NC
NC
NC
NC
NC
NC
43
43
BOM_COST_GROUP=SENSORS
PAGE TITLE
2
C TE CM TE E T M
SENSORS: THERMAL (2/2)
1
Page 51
KOBOL: ACCEL & GYRO
w w w . t e k n i s i - i n d o n e s i a . c o m
PP1V8_S2
SENSOR_IMU SENSOR_IMU
RE403
100K
5%
1/20W
MF
201
2
SPI_GYRO_CS_1V8_L
51
GYRO_INT_1V8
51
GYRO_MOTION_INT_1V8
51
RE404
100K
5%
1/20W
MF
201
VOLTAGE=1.8V
MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000
PP1V8_S2_IMU_FILT
51
SENSOR_IMU
1
SENSOR_IMU
1
2
1
RE400
100K
5%
1/20W
MF
201
2
VDD
VDDIO
CE400
0.1UF
10%
10V
2
X5R-CERM
0201
1
CE401
10%
10V
2
X5R-CERM
0201
SENSOR_IMU SENSOR_IMU
1
CE402
2.2UF 0.1UF
20%
10V
2
X5R
0201
120OHM-25%-0.25A-0.5OHM
SENSOR_IMU
FLE400
0201
2 1
PP1V8_S2
101 51
SENSOR_IMU
UE400
BMI282AA
LGA
5
CS*
15
SM
INT
7
MOTION_INT
SCLK
MOSI
MISO
GND
2
SPI_AOP_SENSOR_CLK_1V8
3
SPI_AOP_SENSOR_MOSI_1V8
4 6
SPI_AOP_SENSOR_MISO_1V8_R
51
51
SENSOR_IMU
RE401
20
2 1
5%
1/20W
MF
201
SPI_AOP_SENSOR_MISO_1V8
51
SENSOR_IMU
47K
5%
MF
201
1
2
RE405
1/20W
102 51
51
PP1V25_S2
SPI_AOP_SENSOR_MISO_1V8
102 51
51
PP1V25_S2
GYRO_INT_1V8
SENSOR_IMU
1
CE411
0.1UF
10%
10V
2
X5R-CERM
0201
SENSOR_IMU
1
CE412
0.1UF
10%
10V
2
X5R-CERM
0201
VCC
GND
NC
VCC
GND
SENSOR_IMU
UE411
SN74AUP1G17
SON
4 2
NC
SPI_AOP_GYRO_R1_MISO
SENSOR_IMU
UE412
SN74AUP1G17
SON
4 2
NC
NC
GYRO_INT
OUT
OUT
9
9 106
PP1V25_S2
102 51
SENSOR_IMU
RE420
9 106
IN
SPI LEVEL TRANSLATION
47K
5%
1/20W
MF
201
SENSOR_IMU
1
CE421
0.1UF
10%
10V
1
2
SPI_GYRO_CS_L
X5R-CERM
0201
VCCA VCCB
5
DIR
A
GND
SENSOR_IMU
UE4202
SN74AXC1T45
SOT-5X3
4 3
B
SPI_GYRO_CS_1V8_L
SENSOR_IMU
RE435
20
2 1
SPI_AOP_SENSOR_CLK_1V8 SPI_AOP_SENSOR_CLK_1V8_R
5%
1/20W
MF
PLACE_NEAR=UE430:10MM
201
SENSOR_IMU
1
CE422
0.1UF
10%
10V
2
X5R-CERM
0201
PP1V8_S2_IMU_FILT
51 51
51
51
102 51
51
PP1V25_S2
SENSOR_IMU
1
CE413
0.1UF
10%
10V
2
X5R-CERM
0201
VCC
GND
SENSOR_IMU
UE413
SN74AUP1G17
SON
4 2
NC
NC
SENSOR_IMU
RE436
20
2 1
SPI_AOP_SENSOR_MOSI_1V8_R
51
5%
1/20W
MF
201
102 51
PLACE_NEAR=UE430:10MM
PP1V25_S2
SENSOR_IMU
1
CE431
0.1UF
10%
10V
2
X R-CE M
0201
GYRO_MOTION_INT GYRO_MOTION_INT_1V8
OUT
9 106
SPI_AOP_SENSOR_MOSI_1V8
PP1V8_S2_IMU_FILT
SENSOR_IMU
1
CE432
0.1UF
10%
10V
2
X5R-CERM
0201
VCCB VCCA
51
51
UE430
18
IN
18
IN
SPI_AOP_SENSOR_CLK
SPI_AOP_SENSOR_MOSI
SENSOR_IMU
RE430
47K
5%
1/20W
MF
201
1
2
SENSOR_IMU
RE431
47K
5%
1/20W
MF
201
5
1
2
74AVC2T45
1A
2A
DIR
VSSOP
SENSOR_IMU
GND
1B
2B
7 2
SPI_AOP_SENSOR_CLK_1V8_R
6 3
SPI_AOP_SENSOR_MOSI_1V8_R
51
51
C TESYNC_MASTER=WUDI_T668_MLB
PAGE TITLE
SENSORS: MOTION
BOM_COST_GROUP=SENSORS
Page 52
PP3V3_S2
w w w . t e k n i s i - i n d o n e s i a . c o m
104
PP1V8_S2
101
NOSTUFF
RE590
0
0%
1/16W
MTL-FILM
0402
116S00006
RE591
0
0%
1/16W
MTL-FILM
0402
116S00006
FAN CONTROL
XWE598
SM
104 52
2 1
2 1
PPVCC_FAN_PWM_LS
MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000
VOLTAGE=3.3V
PP5V_S2
2 1
1
CE503
0.1UF
10%
10V
2
X6S-CERM
0201
1V2
1V2
1
CE502
0.1UF
PP1V25_S2
102
1
CE501
0.1UF
0%
6.3V
2
CERM-X5R
0201
9 106
IN
9
OUT
SMC_FAN_PWM
SMC_FAN_TACH
RE500
RE505
20K
5%
1/20W
MF
201
2 1
20K
5%
1/20W
MF
201
47K
5%
MF
201
1
2
RE503
1
2
1/20W
VCCA VCCB
5
DIR
A
GND
UE501
SN74AXC1T45
SOT-5X3
4 3
B
10%
6.3V
2
CERM-X5R
0201
SMC_FAN_LS_PWM
NOSTUFF
RE501
100K
5%
1/20W
MF
201
RE502
100K
5%
1/20W
MF
201
1
1
2
2
1
2
QE500
NTNS4CS69N
XDFN
376S00282
3
89
89
2
DZE500
NOSTUFF
1M
5%
MF
201
1
2
RE580
1/20W
FAN_RT_PWM
NOTE: 1.5 MOHM PU INSIDE IC
FAN_RT_TACH
J223 FAN CONNECTOR
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=5
89
PP5V_S2_TO_FAN
TP_FAN_RT_OTP1
89
TP_FAN_RT_OTP2
89
518S0818
JE501
FF14A-6C-R11DL-B-3H
F-RT-SM
7
1
2
3
4
5
6
5.5V-0.28PF
0201-THICKSTNCL
8
1
XWE599
SM
2 1
89
GND_FAN
104 52
5V POWER FOR A DEBUG FAN
518S0769
CRITICAL
PLACE_SIDE=BOTTOM
DBG_FAN
JE500
PP5V_S2
1
CE504
0.1UF
10%
10V
2
X6S-CERM
0201
FF14A-5C-R11DL-B-3H
NC
NC
NC
NC
NC
F-RT-SM
6
1
3
4
5
7
SYNC_DATE=09/18/2019SYNC_MASTER=AITKEN_T668_MLB
PAGE TITLE
FAN
BOM_COST_GROUP=FAN
Page 53
** OK2INTEGRATE **
w w w . t e k n i s i - i n d o n e s i a . c o m
5
IN
5
IN
5
IN
5
IN
5
BI
5
BI
5
BI
5
BI
USBC_ATC0_R2D_C_P<1>
USBC_ATC0_R2D_C_N<1>
USBC_ATC0_R2D_C_P<2>
USBC_ATC0_R2D_C_N<2>
USBC_ATC0_D2R_P<1>
USBC_ATC0_D2R_N<1>
USBC_ATC0_D2R_P<2>
USBC_ATC0_D2R_N<2>
USBC HIGH-SPEED AC COUPLING
GND_VOID=TRUE
2 1
USBC_ATC0_R2D_P<1>
20%
X5R
2 1
USBC_ATC0_R2D_N<1>
X5R
2 1
USBC_ATC0_R2D_P<2>
20%
X5R
2 1
USBC_ATC0_R2D_N<2>
20%
X5R
2 1
USBC_ATC0_D2R_C_P<1>
20% 6.3V
X5R
2 1
USBC_ATC0_D2R_C_N<1>
20%
X5R
2 1
USBC_ATC0_D2R_C_P<2>
% 6.3V
X5GND_VOID=TRUE
2 1
USBC_ATC0_D2R_C_N<2>
20% 0201
X5R
0201 6.3V
6.3V 20%
0201
0201
6.3V
0201 6.3V
0201
6.3V 0201
0201
6 3V
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=T U
GND_VOID=TRUE
CF020
0.22UF
CF021
0.22UF
CF024
0.22UF
CF025
0.22UF
CF022
0.22UFGND_VOID=TRUE
CF023
0.22UF
CF026
0.22UF
CF027
0.22UF
107
107
107
107
107
107
107
107
Caps and connector must be aliased to BBR signals.
Lanes 1 and 2 can be swapped, both pairs, both sides; all or nothing.
Inputs can be polarity inverted independently per pair.
All swaps and inversions must be communicated to TBT Firmware team.
GND_VOID=TRUE GND_VOID=TRUE
USBC_ATC0_R2D_P<1>
107
USBC_ATC0_R2D_N<1>
107
USBC_ATC0_R2D_P<2>
107
USBC_ATC0_R2D_N<2>
107
USBC_ATC0_D2R_C_P<1>
107
USBC_ATC0_D2R_C_N<1>
107
USBC_ATC0_D2R_C_P<2>
107
USBC_ATC0_D2R_C_N<2>
107
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
J1
J2
C1
C2
G1
G2
E1
E2
ASSRXP1
ASSRXN1
ASSRXP2
ASSRXN2
ASSTXP1
ASSTXN1
ASSTXP2
ASSTXN2
338S00561
UF000
9999HH
BGA
SYM 1 OF 2
CRITICAL
OMIT_TABLE
BSSRXP1
BSSRXN1
BSSRXP2
BSSRXN2
BSSTXP1
BSSTXN1
BSSTXP2
BSSTXN2
GND_VOID=TRUE
J12
J11
GND_VOID=TRUE
GND_VOID=TRUE
C12
C11
GND_VOID=TRUE
GND_VOID=TRUE
G12
G11
GND_VOID=TRUE
GND_VOID=TRUE
E12
E11
USBC0_D2R_P<1>
USBC0_D2R_N<1>
USBC0_D2R_P<2>
USBC0_D2R_N<2>
USBC0_R2D_CR_P<1>
USBC0_R2D_CR_N<1>
USBC0_R2D_CR_P<2>
USBC0_R2D_CR_N<2>
BI
BI
BI
BI
OUT
OUT
OUT
OUT
107
07
107
107
107
107
107
107
5
BI
5
BI
USBC_ATC0_AUX_P
USBC_ATC0_AUX_N
CF028
CF029
0.1UF
RF028
33K
5%
1/20W
MF
201
1
2
1
RF029
33K
5%
1/20W
MF
201
2
PP3V3_S2SW_USB0
PP3V3_S2SW_USB0
2 1
10%
CERM-X5R0.1UF
2 1
10%
CERM-X5R
104 55 53
104 55 53
6.3V 0201
0201 6.3V
USBC_ATC0_AUX_C_P
USBC_ATC0_AUX_C_N
60
60
CIO_ATC0_LSTX_3V3
IN
CIO_ATC0_LSRX_3V3
OUT
NOSTUFF
RF008
100K
1/20W 1/20W
201
5%
MF
1
RF009
100K
2
5%
MF
201
1
2
55
55 57 60
55 57 60
55
50
INT_I2C_ATCRTMR0_L
OUT
I2C_UPC0_ATCRTMR0_SCL
BI
I2C_UPC0_ATCRTMR0_SDA
BI
ATCRTMR0_GPIO_5
53
ATCRTMR0_GPIO_6
53
ATCRTMR0_FLASH_SHARE_EN
53
ATCRTMR01_FLASH_MSTR
IN
ATCRTMR0_GPIO_12
53
ATCRTMR0_THERM_D_P
OUT
ATCRTMR0_XTAL25M_IN
53
ATCRTMR0_XTAL25M_OUT
53
L8
M8
L7
A10
C9
E7
B9
A8
A4
A5
A6
M11
L9
M9
L12
A11
PA_AUX_P
PA_AUX_N
PA_LSTX_SBU1
PA_LSRX_SBU2
I2C_INT
I2C_SCL
I2C_SDA
POC_GPIO_5
POC_GPIO_6
POC_GPIO_10
POC_GPIO_11
POC_GPIO_12
THERMDA
XTAL_25_IN
XTAL_25_OUT
MONDC_SVR
MONDC
INTERNAL CAPS,
PU, PD
IPU ~ 65K
IPU ~ 65K
IPU ~ 65K
To SPI Flash
TEST_PWR_GOOD
BSBU1
BSBU2
PERST*
RESET*
TDI
TMS
TCK
TDO
EE_DI
EE_DO
EE_CS*
EE_CLK
TEST_EN
RBIAS
RSENSE
ATEST_P
ATEST_N
M10
L10
B8 M7
L11
A3
C3
B5
C5
C4
B4
B6
C7
B11
B3
L4
L5
A1
A2
USBC0_AUXLSX_P
USBC0_AUXLSX_N
ATCRTMR01_ACTIVE_READY_3V3
ATCRTMR0_RESET_L
JTAG_ATCRTMR01_TDI
JTAG_ATCRTMR0_TMS
JTAG_ATCRTMR01_TCK
JTAG_ATCRTMR01_TDO
SPI_ATCRTMR0_R_MOSI
SPI_ATCRTMR0_R_MISO
SPI_ATCRTMR0_R_CS_L
SPI_ATCRTMR0_R_CLK
ATCRTMR0_TEST_PWR_GOOD
ATCRTMR0_RBIAS
ATCRTMR0_RSENSE
NC
NC
PLACE_NEAR=UF000.L5:2MM
PLACE_NEAR=UF000.L4:2MM
OUT
OUT
OUT
4.75K
0.5%
0201
57
BI
57
BI
53 54 55
IN
55 57 60
IN
55
IN
55
IN
55
IN
55
55
UT
55
IN
55
55
2 1
1/20W
RF007
TF
RF006
100
5%
1/20W
MF
201
1
2
107
100K
NOSTUFF
53 54 55
ATCRTMR01_ACTIVE_READY_3V3
IN
NOSTUFF
NOSTUFF
NOSTUFF
100K
100K
100K
100K
RF050
2 1
RF041
2 1
RF051
2 1
RF043
2 1
5% 1/20W 201 MF
RF045
2 1
5% 1/20W MF
MF
201 1/20W MF 5%
201 1/20W 5%
0
201 1/20W 5% MF
2 1
RF040
ATCRTMR0_GPIO_5
ATCRTMR0_GPIO_6
0201 MF 5% 1/20W
ATCRTMR0_FLASH_SHARE_EN
ATCRTMR0_GPIO_12
53
53
53
53
ATCRTMR0_XTAL25M_OUT_R
5%
25V
C0G
0201
0201
C0G
25V
5%
1
2
2
CF002
20PF
20PF
CF003
1
ATCRTMR0_XTAL25M_IN_R
RF002
0
2 1
0201
MF 1/20W
5%
ATCRTMR0_XTAL25M_OUT
CRITICAL
YF000
25MHZ-25PPM-20PF-50OHM
2.00X1.60-SM
RF003
0
2 1
0201
MF 1/20W
5%
ATCRTMR0_XTAL25M_IN
53
NC
NC
NC
NC
53
M12
A12
J6
L3
J5
TEST_EDM
NC_A12
NC_J6
NC_L3
NC_J5
FORCE_PWR
FLASH_BUSY*
FUSE_VQPS_64
SMBUS_SCL
SMBUS_SDA
338S00561
UF000
9999HH
BGA
SYM 2 OF 2
CRITICAL
OMIT_TABLE
VCC3P3_SX
VCC3P3A
VCC3P3_SVR
VCC0P9_SVR
SVR_IND
SVR_VSS
VSS_ANA
PP3V8_AON_ATC_ISNS
105
USBC0_3V3LDO_EN_MUX
IN
RF012
100K
1/20W
5%
MF
201
PP0V9_ATCRTMR0_SVR
53
3.3V LDO
1
CF010
1.0UF
2
0201-1
20%
6.3V
X5R
1
2
CRITICAL
1
CF065
20UF
20%
2.5V
2
X6S-CERM
0402
PACK_OPTION=PKGS:SMALL_PITCH
ALLOW_APPLE_PREFIX=U
CRITICAL
1
CF064
20UF
20%
2.5V
2
X6S-CERM
0402
UF015
TLV75533
4
IN
3
EN
X2SON
GND
OUT
THRM
PAD
CRITICAL
1
CF063
20UF
20%
2.5V
2
X6S-CERM
0402
1
PP3V3_S2SW_USB0
1
CF015
1.0UF
20%
6.3V
2
X5R
0201-1
CRITICAL
1
CF062
20UF 4UF
20%
2.5V
2
X6S-C RM
0402
MIN_LINE_WIDTH=0.1400
MIN_NECK_WIDTH=0.0750
PACK_OPTION=PKGS:LARGER_PITCH
1
2
UF015
TLV75533
6
IN OUT
4
EN
GND EPAD
CF061
20%
6.3V
CER-X5R
0201
WSON
1
CF060
4UF
20%
6 3V
2
CE -X5R
020
CF054
NC
10UF
1
2
5
1
CF050
4UF
20%
6.3V
2
CER-X5R
0201
20%
6.3V
CERM
0402
1
2
CF055
2.2UF
20%
6.3V
X5R-CERM
0201
PP3V3_ATCRTMR0_LC
VOLTAGE=3.3V
1
CF056
2 2UF
20%
6.3V
2
X5R-CERM
0201
104
NC
NC
1
CF051
4UF 4UF
20%
6.3V
2
CER-X5R
201
1
2
VOLTAGE=3 3V
1
2
1
CF057
2.2UF
20%
6.3V
2
X5R-CERM
0201
CF052
20%
6.3V
CER-X5R
0201
1
CF053
4UF
20%
6.3V
2
CER-X5R
0201
PP0V9_ATCRTMR0_LVR
VOLTAGE=0.9V
PP3V3_ATCRTMR0_ANA
55
PP0V9_ATCRTMR0_LC
VOLTAGE=0.9V
1
CF058
2.2UF
20%
6.3V
2
X5R-CERM
0201
F6
G6
E9
G9
L6
M6
E5
L2
J3
F3
F5
G5
B1
B12
D1
D11
D12
D2
F1
F11
F12
F2
VCC0P9_SVR_ANA
VCC0P9_SVR_PB_ANA
VCC0P9_LVR
VCC0P9_LVR_SENSE
VCC3P3_LC
VCC3P3_ANA
VCC0P9_LC
VSS
VSS_ANA
B10
A9
B2
A7
B7
E6
J7
M4
M5
E3
G3
L1
M1
M2
M3
F7
F9
G7
H1
H11
H12
H2
J9
K1
K11
K12
K2
ATCRTMR0_FORCE_PWR
FLASH_BUSY_USBC01_L
TP_SMBUS_ATCRTMR0_SCL
TP_SMBUS_ATCRTMR0_SDA
VOLTAGE=3.3V
PP3V3_ATCRTMR0_VCCA
1
CF043 2
12PF
5%
25V
2
NP0-C0G
0201
1
CF030
2
VOLTAGE=3.3V
PP3V3_ATCRTMR0_SVR
1
CF032
10UF
20%
6.3V
2
CERM
0402
BYPASS=UF000.M4:M3:3MM
1
CF033
2
1
CF038
2
0.68UH-20%-4.3A-0.043OHM
PP0V9_ATCRTMR0_SVR_IND
_
VOLTAGE=0.9V
DIDT=TRUE
XWF030
SM
2 1
ATCRTMR0_THERM_D_N
PLACE_NEAR=UF000.K11:2MM
NO_XNET_CONNECTION=1
CONNECT TO GND PIN
CLOSEST TO THERMDA PIN
2.2UF
20%
6.3V
X5R-CERM
0201
10UF
20%
6.3V
CERM
0402
12PF
5%
25V
NP0-C0G
0201
55 57
IN
BI
1
2
CRITICAL
LF000
0805
55
RF000
0
2 1
0
5%
4 2
2 1
402
MF-LF
1
CF031
10UF
20%
6.3V
2
CERM
0402
1
CF034
10UF
20%
6.3V
2
CERM
0402
1/16W5%MF-LF
RF001
1/16W
1
CF035
10UF
20%
6.3V
2
CERM
0402
P0V9_ATCRTMR0_SVR_PGND
VOLTAGE=0V
CF039
4UF
20%
6.3V
CER-X5R
0201
OU
1
CF041
4UF
20%
6.3V
2
CER-X5R
0201
2 1
50
PLACE_NEAR=CF032.2:2MM
NO_XNET_CONNECTION=1
SYNC_MASTER=REF_USBC_ACE2 SYNC_DATE=02/14/2020PACK_IGNORE=TRUE
PAGE TITLE
USB-C: High Speed ATC0
1
CF036
2.2UF
20%
6.3V
2
X5R-CERM
0201
XWF001
SM
2 1
NO_XNET_CONNECTION=1
XWF000
SM
2 1
1
CF040
47UF
20%
6.3V
2
CER-X5R
0603
FROM USB-C PORT
CONTROLLER (UPC)
PP3V3_S2SW_USB0
NOSTUFF
1
CF037
2.2UF
20%
6.3V
2
X5R-CERM
0201
1
CF042
47UF
20
6.3V
CER-X5R
0603
PP3V3_S2SW_USB0
PP0V9_ATCRTMR0_SVR
VOLTAGE=0.9V
104 55 53
104 55 53
53
BOM_COST_GROUP=TBT
Page 54
** OK2INTEGRATE **
w w w . t e k n i s i - i n d o n e s i a . c o m
5
IN
5
IN
5
IN
5
IN
5
BI
5
BI
5
BI
5
BI
USBC_ATC1_R2D_C_P<1>
USBC_ATC1_R2D_C_N<1>
USBC_ATC1_R2D_C_P<2>
USBC_ATC1_R2D_C_N<2>
USBC_ATC1_D2R_N<1>
USBC_ATC1_D2R_P<2>
USBC_ATC1_D2R_N<2>
USBC HIGH-SPEED AC COUPLING
GND_VOID=TRUE
2 1
USBC_ATC1_R2D_P<1>
20%
X5R
2 1
USBC_ATC1_R2D_N<1>
X5R
2 1
USBC_ATC1_R2D_P<2>
20%
X5R
2 1
USBC_ATC1_R2D_N<2>
20%
X5R
2 1
USBC_ATC1_D2R_C_P<1> USBC_ATC1_D2R_P<1>
20% 6.3V
X5R
2 1
USBC_ATC1_D2R_C_N<1>
20%
X5R
2 1
USBC_ATC1_D2R_C_P<2>
% 6.3V
X5
2 1
USBC_ATC1_D2R_C_N<2>
20% 0201
X5R
0201 6.3V
6.3V 20%
0201
0201
6.3V
0201 6.3V
0201
6.3V 0201
0201
6 3V
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
CF120
0.22UF
CF121
0.22UF
CF124
0.22UF
CF125
0.22UF
CF122
0.22UF
CF123
0.22UF
CF126
0.22UF
CF127
0.22UF
107
107
107
107
107
107
107
107
Caps and connector must be aliased to BBR signals.
Lanes 1 and 2 can be swapped, both pairs, both sides; all or nothing.
Inputs can be polarity inverted independently per pair.
All swaps and inversions must be communicated to TBT Firmware team.
GND_VOID=TRUE GND_VOID=TRUE
USBC_ATC1_R2D_P<1>
107
USBC_ATC1_R2D_N<1>
107
USBC_ATC1_R2D_P<2>
107
USBC_ATC1_R2D_N<2>
107
USBC_ATC1_D2R_C_P<1>
107
USBC_ATC1_D2R_C_N<1>
107
USBC_ATC1_D2R_C_P<2>
107
USBC_ATC1_D2R_C_N<2>
107
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRU
GND_VOID=TRUE
J1
J2
C1
C2
G1
G2
E1
E2
ASSRXP1
ASSRXN1
ASSRXP2
ASSRXN2
ASSTXP1
ASSTXN1
ASSTXP2
ASSTXN2
338S00561
UF100
9999HH
BGA
SYM 1 OF 2
CRITICAL
OMIT_TABLE
BSSRXP1
BSSRXN1
BSSRXP2
BSSRXN2
BSSTXP1
BSSTXN1
BSSTXP2
BSSTXN2
GND_VOID=TRUE
J12
J11
GND_VOID=TRUE
GND_VOID=TRUE
C12
C11
GND_VOID=TRUE
GND_VOID=TRUE
G12
G11
GND_VOID=TRUE
GND_VOID=TRUE
E12
E11
USBC1_D2R_P<1>
USBC1_D2R_N<1>
USBC1_D2R_P<2>
USBC1_D2R_N<2>
USBC1_R2D_CR_P<1>
USBC1_R2D_CR_N<1>
USBC1_R2D_CR_P<2>
USBC1_R2D_CR_N<2>
BI
BI
BI
BI
OUT
OUT
OUT
OUT
107
07
107
107
107
107
107
107
104 54
2 1
10%
CERM-X5R0.1UF
2 1
10%
CERM-X5R
104 55 54
6.3V 0201
0201 6.3V
5
BI
5
BI IN
USBC_ATC1_AUX_P
USBC_ATC1_AUX_N
CF128
CF129
0.1UF
RF128
33K
5%
1/20W
MF
201
1
2
1
RF129
33K
5%
1/20W
MF
201
2
PP3V3_S2SW_USB1
PP3V3_S2SW_USB1
USBC_ATC1_AUX_C_P
USBC_ATC1_AUX_C_N
60
60
CIO_ATC1_LSTX_3V3
CIO_ATC1_LSRX_3V3
OUT
NOSTUFF
RF108
100K
1/20W
201
5%
MF
1
RF109
100K
2
5%
1/20W
MF
201
1
2
55
55 58 60
55 58 6
55
50
INT_I2C_ATCRTMR1_L
OUT
I2C_UPC1_ATCRTMR1_SCL
BI
I2C_UPC1_ATCRTMR1_SDA
BI
ATCRTMR1_GPIO_5
54
ATCRTMR1_GPIO
54
ATCRTMR1_FLASH_SHARE_EN
54
ATCRTMR01_FLASH_SLV_L
IN
ATCRTMR1_GPIO_12
54
ATCRTMR1_THERM_D_P
OUT
ATCRTMR1_XTAL25M_IN
54
ATCRTMR1_XTAL25M_OUT
54
L
M8
L7
A10
C9
E7
B9
A8
A4
A5
A6
M11
L9
M9
L12
A11
PA_AUX_P
PA_AUX_N
PA_LSTX_SBU1
PA_LSRX_SBU2
I2C_INT
I2C_SCL
I2C_SDA
POC_GPIO_5
POC_GPIO_6
POC_GPIO_10
POC_GPIO_11
POC_GPIO_12
THERMDA
XTAL_25_IN
XTAL_25_OUT
MONDC_SVR
MONDC
INTERNAL CAPS,
PU, PD
IPU ~ 65K
IPU ~ 65K
IPU ~ 65K
To SPI Flash
TEST_PWR_GOOD
BSBU1
BSBU2
PERST*
RESET*
TDI
TMS
TCK
TDO
EE_DI
EE_DO
EE_CS*
EE_CLK
TEST_EN
RBIAS
RSENSE
ATEST_P
ATEST_N
M10
L10
B8 M7
L11
A3
C3
B5
C5
C4
B4
B6
C7
B11
B3
L4
L5
A1
A2
USBC1_AUXLSX_P
USBC1_AUXLSX_N
ATCRTMR01_ACTIVE_READY_3V3
ATCRTMR1_RESET_L
JTAG_ATCRTMR01_TDI
JTAG_ATCRTMR1_TMS
JTAG_ATCRTMR01_TCK
JTAG_ATCRTMR01_TDO
SPI_ATCRTMR1_R_MOSI
SPI_ATCRTMR1_R_MISO
SPI_ATCRTMR1_R_CS_L
SPI_ATCRTMR1_R_CLK
ATCRTMR1_TEST_PWR_GOOD
ATCRTMR1_RBIAS
ATCRTMR1_RSENSE
NC
NC
PLACE_NEAR=UF100.L5:2MM
PLACE_NEAR=UF100.L4:2MM
OUT
OUT
OUT
4.75K
0.5%
0201
58
BI
58
BI
53 54 55
IN
58 60
IN
55
IN
55
IN
55
IN
55
55
UT
55
IN
55
55
1/20W
RF107
100
5%
1/20W
MF
201
1
2
RF106
1
TF
107
100K
NOSTUFF
53 54 55
ATCRTMR01_ACTIVE_READY_3V3
IN
NOSTUFF
NOSTUFF
NOSTUFF
100K
100K
100K
100K
RF150
2 1
RF141
2 1
RF151
2 1
RF143
2 1
5% 1/20W 201 MF
RF145
2 1
5% 1/20W 201 MF
MF
201 5% 1/20W MF
201 1/20W 5%
0
201 1/20W 5% MF
2 1
RF140
ATCRTMR1_GPIO_5
ATCRTMR1_GPIO_6
0201 MF 5% 1/20W
ATCRTMR1_FLASH_SHARE_EN
ATCRTMR1_GPIO_12
54
54
54
54
ATCRTMR1_XTAL25M_OUT_R
5%
25V
C0G
02 1
0201
C0G
25V
5%
1
2
2
CF102
20PF
20PF
CF103
1
ATCRTMR1_XTAL25M_IN_R
RF102
0
2 1
0201
MF 1/20W
5%
ATCRTMR1_XTAL25M_OUT
CRITICAL
YF100
25MHZ-25PPM-20PF-50OHM
2.00X1.60-SM
RF103
0
2 1
0201
MF 1/20W
5%
ATCRTMR1_XTAL25M_IN
54
NC
NC
NC
NC
54
M12
A12
J6
L3
J5
TEST_EDM
NC_A12
NC_J6
NC_L3
NC_J5
FORCE_PWR
FLASH_BUSY*
FUSE_VQPS_64
SMBUS_SCL
SMBUS_SDA
338S00561
UF100
9999HH
BGA
SYM 2 OF 2
CRITICAL
OMIT_TABLE
VCC3P3_SX
VCC3P3A
VCC3P3_SVR
VCC0P9_SVR
SVR_IND
SVR_VSS
VSS_ANA
PP3V8_AON_ATC_ISNS
105
USBC1_3V3LDO_EN
IN
RF112
100K
1/20W
5%
MF
201
PP0V9_ATCRTMR1_SVR
54
3.3V LDO
1
CF110
1.0UF
2
0201-1
20%
6.3V
X5R
1
2
CRITICAL
1
CF165
20UF
20%
2.5V
2
X6S-CERM
0402
PACK_OPTION=PKGS:SMALL_PITCH
ALLOW_APPLE_PREFIX=U
CRITICAL
1
CF164
20UF
20%
2.5V
2
X6S-CERM
0402
UF115
TLV75533
4
IN
3
EN
X2SON
GND
OUT
THRM
PAD
CRITICAL
1
CF163
20UF
20%
2.5V
2
X6S-CERM
0402
1
PP3V3_S2SW_USB1
1
CF115
1.0UF
20%
6.3V
2
X5R
0201-1
CRITICAL
1
CF162
20UF 4UF
20%
2.5V
2
X6S-C RM
0402
MIN_LINE_WIDTH=0.1400
MIN_NECK_WIDTH=0.0750
PACK_IGNORE=TRUE
PACK_OPTION=PKGS:LARGER_PITCH
1
2
UF115
TLV75533
6
IN OUT
4
EN
GND EPAD
CF161
20%
6.3V
CER-X5R
0201
WSON
1
CF160
4UF
20%
6 3V
2
CE -X5R
020
CF154
NC
10UF
1
2
5
1
CF150
4UF
20%
6.3V
2
CER-X5R
0201
20%
6.3V
CERM
0402
1
2
CF155
2.2UF
20%
6.3V
X5R-CERM
0201
PP3V3_ATCRTMR1_LC
VOLTAGE=3.3V
1
CF156
2 2UF
20%
6.3V
2
X5R-CERM
0201
104
NC
NC
1
CF151
4UF
20%
6.3V
2
CER-X5R
201
1
2
VOLTAGE=3 3V
1
2
1
CF157
2.2UF
20%
6.3V
2
X5R-CERM
0201
CF152
4UF
20%
6.3V
CER-X5R
0201
1
CF153
4UF
20%
6.3V
2
CER-X5R
0201
PP0V9_ATCRTMR1_LVR
VOLTAGE=0.9V
PP3V3_ATCRTMR1_ANA
PP0V9_ATCRTMR1_LC
VOLTAGE=0.9V
1
CF158
2.2UF
20%
6.3V
2
X5R-CERM
0201
F6
G6
E9
G9
L6
M6
E5
L2
J3
F3
F5
G5
B1
B12
D1
D11
D12
D2
F1
F11
F12
F2
VCC0P9_SVR_ANA
VCC0P9_SVR_PB_ANA
VCC0P9_LVR
VCC0P9_LVR_SENSE
VCC3P3_LC
VCC3P3_ANA
VCC0P9_LC
VS
VSS_ANA
B10
A9
B2
A7
B7
E6
J7
M4
M5
E3
G3
L1
M1
M2
M3
F7
F9
G7
H1
H11
H12
H2
J9
K1
K11
K12
K2
ATCRTMR1_FORCE_PWR
FLASH_BUSY_USBC01_L
TP_SMBUS_ATCRTMR1_SCL
TP_SMBUS_ATCRTMR1_SDA
VOLTAGE=3.3V
PP3V3_ATCRTMR1_VCCA
1
CF143
12PF
5%
25V
2
NP0-C0G
0201
1
CF130
2
VOLTAGE=3.3V
PP3V3_ATCRTMR1_SVR
1
CF132
10UF
20%
6.3V
2
CERM
0402
BYPASS=UF100.M4:M3:3MM
1
CF133
2
1
CF138
2
0.68UH-20%-4.3A-0.043OHM
PP0V9_ATCRTMR1_SVR_IND
_
VOLTAGE=0.9V
DIDT=TRUE
XWF130
SM
2 1
ATCRTMR1_THERM_D_N
PLACE_NEAR=UF100.K11:2MM
NO_XNET_CONNECTION=1
CONNECT TO GND PIN
CLOSEST TO THERMDA PIN
2.2UF
20%
6.3V
X5R-CERM
0201
10UF
20%
6.3V
CERM
0402
12PF
5%
25V
NP0-C0G
0201
55 58
IN
5 55
BI
1
2
CRITICAL
LF100
0805
RF100
0
2 1
0
5%
402
2 1
402
MF-LF
1
CF131
10UF
20%
6.3V
2
CERM
0402
1
CF134
10UF
20%
6.3V
2
CERM
04 2
1/16W5%MF-LF
RF101
1/16W
1
CF135
10UF
20%
6.3V
2
CERM
0402
P0V9_ATCRTMR1_SVR_PGND
VOLTAGE=0V
CF139
4UF
20%
6.3V
CER-X5R
0201
OU
1
CF141
4UF
20%
6.3V
2
CER-X5R
0201
2 1
50
PLACE_NEAR=CF132.2:2MM
NO_XNET_CONNECTION=1
SYNC_MASTER=REF_USBC_ACE2 SYNC_DATE=02/14/2020
PAGE TITLE
USB-C: High Speed ATC1
1
CF136
2.2UF
20%
6.3V
2
X5R-CERM
0201
XWF101
SM
2 1
NO_XNET_CONNECTION=1
XWF100
SM
2 1
CF140
47UF
20%
6.3V
2
CER-X5R
0603
FROM USB-C PORT
CONTROLLER (UPC)
PP3V3_S2SW_USB1
NOSTUFF
1
CF137
2.2UF
20%
6.3V
2
X5R-CERM CER-X5R
0201
1
CF142
47UF
20%
6.3V
2
0603
PP3V3_S2SW_USB1
PP0V9_ATCRTMR1_SVR
VOLTAGE=0.9V
104 54
104 55 54
54
BOM_COST_GROUP=TBT
2
1
Page 55
** OK2INTEGRATE **
w w w . t e k n i s i - i n d o n e s i a . c o m
NOSTUFF
1
RF260
3.3K
5%
1/20W
MF
201
2
55
ROM_UPC01_WP_L
ROM_UPC01_HOLD_L
RF261
3.3K
5%
1/20W
MF
201
RF264
3.3K
5%
1/20W
MF
201
PP3V3_UPC0_LDO
1
2
1
RF263
3.3K
5%
1/20W
MF
201
2
6
1
3
7
1
2
8MBIT-3.0V
CLK
CS*
WP*(IO2)
HOLD*(IO3)
VCC
UF260
W25Q80DVUXIE
USON
OMIT_TABLE
CRITICAL
GND EPAD
DI(IO0)
DO(IO1)
5
2
1
RF262
3.3K
5%
1/20W
MF
201
2
SPI_UPC01_MOSI
55
SPI_UPC01_MISO
55
SPI_UPC01_CLK
55
SPI_UPC01_CS_L
55
1
CF260
1UF
10%
6.3V
2
CERM
402
55
RF294
RF295
1
RF296
RF297
RF298
RF290
RF291
RF292
RF293
RF299
RF29A
RF29B
RF29C
NO_XNET_CONNECTION=1
100
1
15
15
15
15
15
15
15
15
15
15
15
2 1
5% 1/20W MF
5% 1/20W MF 201
2 1
5% 1/20W MF 201
2 1
5% 1/20W MF 201
2 1
5% 1/20W MF 201
2 1
5% 1/20W MF 201
2 1
5% 1/20W MF 201
2 1
5% 1/20W MF 201
2 1
5% 1/20W MF 201
2 1
5% 1/20W MF 201
2 1
5% 1/20W MF 201
2 1
5% 1/20W MF
2 1
5% 1/20W MF
SPI_UPC01_CLK_DBG
201
SPI_UPC01_R_CLK
SPI_UPC01_R_CS_L
SPI_UPC01_R_MOSI
SPI_UPC01_R_MISO
SPI_ATCRTMR0_R_CLK
SPI_ATCRTMR0_R_CS_L
SPI_ATCRTMR0_R_MOSI
SPI_ATCRTMR0_R_MISO
SPI_ATCRTMR1_R_CLK
SPI_ATCRTMR1_R_CS_L
SPI_ATCRTMR1_R_MOSI
SPI_ATCRTMR1_R_MISO
55
55
55
55
55
IN
IN
IN
OUT
IN
IN
IN
OUT
53
53
53
53
54
54
54
54
SPI Ace
BB
BB
ATC0: I2C_ADDR=GND, I2CM_*_CNFG=1M\u03a9 3V3_LDO_X pull-ups
ATC1: I2C_ADDR=Float, I2CM_*_CNFG=1M\u03a9 3V3_LDO_X pull-ups
ATC2: I2C_ADDR=GND, I2CM_*_CNFG=1M\u03a9 pull-downs
ATC3: I2C_ADDR=Float, I2CM_*_CNFG=1M\u03a9 pull-downs
57
58
57
58
53
IN
60
IN
INT_I2C_ATCRTMR0_L
INT_I2C_EUSBLS0_L
GND
OUT
NC_UPC1_I2C_ADDR
OUT
Configure to enable VDDIO and use it for SWD.
GND
OUT
GND
OUT
PP3V3_UPC0_LDO
10K
2 1
5% 1/20W MF 201
RF242
55
UPC_ATCRTMR_INT
RF210
5% 1/20W MF 0201
UPC_EUSBLS_INT
RF211
5% 1/20W MF 0201
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
0
2 1
0
2 1
NC_UPC1_I2C_ADDR
NO_TEST=1
FLASH_BUSY_USBC01_L
MAKE_BASE=TRUE
INT_I2C_UPC0_ATCRTMR0_L
OUT
OUT
53 54 55
55 57
104 53
55
55
55
55
55
6 55
OUT
6 55
BI
55
SPI_UPC01_R_CLK
SPI_UPC01_R_CS_L
SPI_UPC01_R_MOSI
SPI_UPC01_R_MISO
ROM_UPC01_WP_L
SWD_UPC_SWCLK
SWD_UPC_SWDIO0
PP3V3_UPC0_LDO
PP3V3_S2SW_USB0
53 54 55
FLASH_BUSY_USBC01_L
BI BI
PACK_OPTION=USBC_SPI_UPC0
PACK_OPTION=USBC_SPI_UPC0
PACK_OPTION=USBC_SPI_UPC0
PACK_OPTION=USBC_SPI_UPC0
PACK_OPTION=USBC_SPI_UPC0 PACK_OPTION=USBC_SPI_UPC0 PACK_OPTION=USBC_SPI_UPC0
PACK_OPTION=USBC_SPI_UPC0 PACK_OPTION=USBC_SPI_UPC0 PACK_OPTION=USBC_SPI_UPC0
PACK_OPTION=USBC_SPI_UPC0
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
(Internal pull-up)
NOSTUFF
PACK_OPTION=USBC_S _UPC0
100K
2 1
MAKE_BASE=TRUE
PACK_OPTION=USBC_SPI_UPC0
PACK_OPTION=USBC_SPI_UPC0
PACK_OPTION=USBC_SPI_UPC0 PACK_OPTION=USBC_SPI_UPC0 PACK_OPTION=USBC_SPI_UPC0
PACK_OPTION=USBC_SPI_UPC0
PACK_OPTION=USBC_SPI_UPC0
PACK_OPTION=USBC_SPI_UPC0
PACK_OPTION=USBC_SPI_UPC0
PACK_OPTION=USBC_SPI_UPC0
PACK_OPTION=USBC_SPI_UPC0
SPI_UPC01_R_CLK
SPI_UPC01_R_CS_L
SPI_UPC01_R_MOSI
SPI_UPC01_R_MISO
ROM_UPC01_WP_L
SWD_UPC_SWCLK
SWD_UPC_SWDIO0
PP3V3_UPC0_LDO
MAKE_BASE=TRUE
Master should be on SPI Ace2.
RF244
5% 1/20W MF 201
ATCRTMR01_FLASH_MSTR
ATCRTMR01_FLASH_MSTR
MAKE_BASE=TRUE
FLASH_BUSY_USBC01_L
PACK_OPTION=USBC_SPI_UPC0
PACK_OPTION=USBC_SPI_UPC0
GND
ACE 0 IS SPI ACE
57
IN
57
IN
57
IN
57
OUT
57
IN
57
IN
57
BI
56 57 89
OUT
53
OUT
57
ACE 1 IS UART ACE
58
IN
54
60
PP3V3_S2_UPC
57 55
102 58
IN
IN
INT_I2C_ATCRTMR1_L
INT_I2C_EUSBLS1_L
Is UPCx_5V_EN being used?
UPC0_5V_EN
57
UPC1_5V_EN
58
RF220
5% 1/20W MF 201
RF221
5% 1/20W MF 201
RF222
5% 1/20W MF 201
RF223
5% 1/20W MF 201
RF224
5% 1/20W MF 20
102 5 57 55
PP1V25_S2
UPC_ATCRTMR_INT
RF215
5% 1/20W MF 0201
UPC_EUSBLS_INT
RF216
5% 1/20W MF 0201
10K
10K
100K
100K
10K
2 1
JTAG_ATCRTMR01_TCK
2 1
JTAG_ATCRTMR0_TMS
2 1
JTAG_ATCRTMR1_TMS
2 1
JTAG_ATCRTMR01_TDI
2 1
JTAG_ATCRTMR01_TDO
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_B SE=TRUE
0
2 1
0
2 1
INT_I2C_UPC1_ATCRTMR1_L
RF234
5% 1/20W MF 201
RF235
5% 1/20W MF 201
PACK_OPTION=USBC01_VR5V_LOCAL_NO
100K
100K
2 1
2 1
JTAG_ATCRTMR01_TCK
JTAG_ATCRTMR0_TMS
JTAG_ATCRTMR01_TDI
JTAG_ATCRTMR01_TDO
JTAG_ATCRTMR01_TCK
JTAG_ATCRTMR1_TMS
JTAG_ATCRTMR01_TDI
JTAG_ATCRTMR01_TDO
PP3V3_S2_UPC
102 58 57 55
OUT
55 58
OUT
OUT
OUT
IN
OUT
OUT
OUT
IN
53
53
53
53
54
54
54
54
MAKE_BASE=TRUE
GND
GND
GND
55 58
OUT
55
BI
SWD_UPC01_UART_CLK
SWD_UPC01_UART_DATA
MAKE_BASE=TRUE
MAKE_BASE=TRUE
ATCRTMR01_FLASH_SLV_L
RF247
RF272
RF273
1/20W
SPI Ace
57
IN
OUT
UART_UPC01_TX
1
5% 1/20W MF 201
5% 1/20W MF 201
5% MF 201
2 1
2 1
2 2K
100K
100K
ATCRTMR01_FLASH_SLV_L
UART_UPC01_TX
MAKE_BASE=TRUE
UART_UPC01_RX
MAKE_BASE=TRUE
SWD_UPC01_UART_CLK
SWD_UPC01_UART_DATA
PD_UPC1_GPIO1
55
UART_UPC01_TX
55
UART_UPC01_RX UART_UPC01_RX
MAKE_BASE=TRUE
UART Ace
ACE ARKANOID CONN
JF200
57 43
57 43
107 57
ATCRTMR0_RESET_L
53 57 60
I2C_SMC_UPC_SCL
I2C_SMC_UPC_SDA
UPC_SMC_I2C_INT_L
SPI_UPC01_CLK_DBG
55
UART_UPC01_TX
55
USBC_DBG 505070-1222
SMC
SPI Ace
M-ST-SM
15
14 13
2 1
4 3
6 5
8 7
10 9
12 11
16
SOC
UPC_I2C_INT_L
I2C_UPC_SDA
I2C_UPC_SCL
UPC0_SER_DBG
UPC1_SER_DBG
UART_UPC01_RX
SPI Ace
IN
IN
OUT
IN
BI
OUT
BI
OUT
58
58
58
58
54
58
58
5 33 89 94 53 54 55
IN
PMU_ACTIVE_READY ATCRTMR01_ACTIVE_READY_3V3
CF230
0.1UF
CERM-X5R
10%
6.3V
0201
1
UF230
SN74AXC1T45
2
VCCA VCCB
5
DIR
A
GND
SOT-5X3
B
4 3
1
CF231
0.1UF
10%
6.3V
2
CERM-X5R
0201
OUT
HV POWER ALIASES
Fuses for laptop charging.
58
OUT
IN
5 57
PACK_OPTION=USBC_LAPTOP
PACK_OPTION=USBC_LAPTOP
CRITICAL
0603-1
FF200
USBC_DBG
RF280
VREFB_ARDV01
102 58 57 55
107 57
57 55 41
57 55 41
57
58
55
57 55 41
57 55 41
PP1V25_S2
USBC_DBG
CF281
0.1UF
CERM-X5R
I2C_UPC_SCL
I2C_UPC_SDA
10%
6.3V
0201
1
2
VREF_A VREF_B
UF280
LSF0102
3
A1
4
A2 B2
X2SON-COMBO
311S00234
USBC_DBG
PACK_OPTION=PKGS:SMALL_PITCH
GND
200K
EN
B1
2 1
MF
1/20W
5% 201
USBC_DBG
CF280
0.1UF
2 1
10%
6.3V
8
6
5
CERM-X5R
0201
I2C_UPC01_3V3_SCL
I2C_UPC01_3V3_SDA
PP3V3_S2_UPC
USBC_DBG
RF282
1
5.1K
1/20W
MF
20
2
USBC_DBG
1
RF283
5.1K
5% 5%
1/20W
MF
201
2
102 58 57 55
55
55
PPDCIN_USBC_AON
101
PLACE_NEAR=UF400:5MM
PLACE_NEAR=UF500:5MM
PPVBUS_USBC0
57
PPVBUS_USBC1
58
6A-32V
CRITICAL
0603-1
FF201
6A-32V
2 1
PPHV_INT0_AONSW
MAKE_BASE=TRUE
VOLTAGE=20V
2 1
PPHV_INT1_AONSW
MAKE_BASE=TRUE
VOLTAGE=20V
PACK_IGNORE=TRUE
PACK_IGNORE=TRUE
PACK_OPTION=USBC_DESKTOP
PACK_OPTION=USBC_DESKTOP
RF200
0
5%
1/20W
MF
0201
RF201
0
5%
1/20W
MF
0201
MAKE_BASE=TRUE
MAKE_BASE=TRUE
2 1
2 1
Desktops only need connection
for programming OTP.
PPHV_INT0_AONSW
PPHV_INT0_AONSW
PPHV_INT1_AONSW
PPHV_INT1_AONSW
PPVBUS_USBC0
PPVBUS_USBC1
57 59 89
58 59 89
57
57
58
58
104 53
104 54
USBC_DBG 505070-1222
ATCRTMR0_FORCE_PWR
53 57
PP3V3_S2SW_USB0
PP0V9_ATCRTMR0_LC
53
ATCRTMR01_ACTIVE_READY_3V3
53 54 55
PP3V3_S2SW_USB1
I2C_UPC1_ATCRTMR1_SDA
54 58 60
BRIDGE ARKANOID CONN
JF201
M-ST-SM
14 13
15
2 1
4 3
6 5
8 7
10 9
12 11
16
INT_I2C_UPC0_ATCRTMR0_L
I2C_UPC0_ATCRTMR0_SCL
I2C_UPC0_ATCRTMR0_SDA
ATCRTMR1_FORCE_PWR
INT_I2C_UPC1_ATCRTMR1_L
I2C_UPC1_ATCRTMR1_SCL
55 57
53 57 60
53 57 60
54 58
5 58
54 5 60
PACK_IGNORE=TRUE
PACK_OPTION=PKGS LARGER_PITCH
VREF_B VREF_A
USBC_DBG
UF280
LSF0102
3
A1
4
A2
VSSOP
GND
EN
B1
B
AARDVARKANOID CONN
JF202
USBC_DBG 505070-1222
M-ST-SM
14 13
SPI ACE
102 58 57 55
8
6
5
PP1V25_S2
SWD_UPC_SWDIO0
6 55
SWD_UPC_SWCLK
6 55
I2C_UPC01_3V3_SCL
55
15
2 1
4 3
6 5
8 7
10 9
12 11
16
SPI_UPC01_CS_L
SPI_UPC01_CLK
SPI_UPC01_MOSI
SWD_UPC01_UART_CLK SPI_UPC01_MISO
SWD_UPC01_UART_DATA I2C_UPC01_3V3_SDA
PP1V25_S2
UART ACE
55
55
55
55 55
55 55
102 58 57 55
SYNC_MASTER=REF_USBC_ACE2 SYNC_DATE=02/01/2020
PAGE TITLE
USB-C: Support 1 ATC01
BOM_COST_GROUP=USB-C
2
1 3 7
Page 56
** OK2INTEGRATE **
w w w . t e k n i s i - i n d o n e s i a . c o m
Ace 0 is Debug Port?
PACK_OPTION=USBC_DEBUG_UPC0
PACK_OPTION=USBC_DEBUG_UPC0
PACK_OPTION=USBC_DEBUG_UPC0 PACK_OPTION=USBC_DEBUG_UPC0 PACK_OPTION=USBC_DEBUG_UPC0 PACK_OPTION=USBC_DEBUG_UPC0 PACK_OPTION=USBC_DEBUG_UPC0 PACK_OPTION=USBC_DEBUG_UPC0 PACK_OPTION=USBC_DEBUG_UPC0 PACK_OPTION=USBC_DEBUG_UPC0 PACK_OPTION=USBC_DEBUG_UPC0 PACK_OPTION=USBC_DEBUG_UPC0 PACK_OPTION=USBC_DEBUG_UPC0
ATC0 / UPC0 / RTMR0
107
6 18 89
IN
6 18 89
OUT
9 18 89
BI
9 18 89
BI
9 89
IN
9 89
OUT
UART_DEBUGPRT_R2D
MAKE_BASE=TRUE
UART_DEBUGPRT_D2R
MAKE_BASE=TRUE
SWD_SOC_SWCLK
MAKE_BASE RUE
SWD_SOC_SWDIO
MAKE_BASE=TRUE
UART_SMC_DEBUGPRT_R2D
MAKE_BASE=TRUE
UART_SMC_DEBUGPRT_D2R
MAKE_BASE=TRUE
UART_DEBUGPRT_R2D
UART_DEBUGPRT_D2R
SWD_SOC_SWCLK
SWD_SOC_SWDIO
UART_SMC_DEBUGPRT_R2D
UART_SMC_DEBUGPRT_D2R
IN
IN
OUT
OUT
OUT
IN
57 96
57 96
57 96
57 96
57 96
57 96
Main Debug Port
89 96
BI
89 96
BI
USB_DBG_LS_P
MAKE_BASE=TRUE
USB_DBG_LS_N
MAKE_BASE=TRUE
PP1V8_S2
OUT
UPC0_GPIO7
USB_DBG_LS_P
USB_DBG_LS_N
PP1V8_S2
PP1V8_S2 PP1V8_S2
UPC0_GPIO7
BI
BI
BI
BI
IN
57
57
57 60 101
60 101
57 96 107
5 19 89 94
IN
5 33 89 90
OUT
SOC_DFU_STATUS
MAKE_BASE=TRUE
SOC_FORCE_DFU
MAKE_BASE=TRUE
SOC_DFU_STATUS
SOC_FORCE_DFU
OUT
IN
57
57
Ace 1 is non-debug Port?
ATC1 / UPC1 / RTMR1
PACK_OPTION=USBC_DEBUG_UPC0
PACK_OPTION=USBC_DEBUG_UPC0
PACK_OPTION=USBC_DEBUG_UPC0 PACK_OPTION=USBC_DEBUG_UPC0 PACK_OPTION=USBC_DEBUG_UPC0 PACK_OPTION=USBC_DEBUG_UPC0 PACK_OPTION=USBC_DEBUG_UPC0 PACK_OPTION=USBC_DEBUG_UPC0 PACK_OPTION=USBC_DEBUG_UPC0 PACK_OPTION=USBC_DEBUG_UPC0 PACK_OPTION=USBC_DEBUG_UPC0 PACK_OPTION=USBC_DEBUG_UPC0 PACK_OPTION=USBC_DEBUG_UPC0
PACK_OPTION=USBC_DEBUG_UPC0
PACK_OPTION=USBC_DEBUG_UPC0
PACK_OPTION=USBC_DEBUG_UPC0
PACK_OPTION=USBC_DEBUG_UPC0
PACK_OPTION=USBC_DEBUG_UPC0
PACK_OPTION=USBC_DEBUG_UPC0
PACK_OPTION=USBC_DEBUG_UPC0
PACK_OPTION=USBC_DEBUG_UPC0
PACK_OPTION=USBC_DEBUG_UPC0
PACK_OPTION=USBC_DEBUG_UPC0
PACK_OPTION=USBC_DEBUG_UPC0
RF320
RF321
RF322
RF323
RF324
RF325
PP1V8_S2 PP1V8_S2
PP1V8_S2_USBLS1_ISNS PP1V8_S2_USBLS1_ISNS
2 1
100K
201 MF 5% 1/20W
2 1
2 1
2 1
2 1
2 1
100K
100K
201 MF 5% 1/20W
100K
100K
201 MF 5% 1/20W
100K
5% 201 MF 1/20W
5% 201 MF 1/20W
5% 201 MF 1/20W
PD_UPC1_DBG0_R
MAKE_BASE=TRUE
PD_UPC1_DBG1_R
MAKE_BASE=TRUE
PD_UPC1_DBG2_R
MAKE_BASE=TRUE
PD_UPC1_DBG3_R
MAKE_BASE=TRUE
PD_UPC1_DBG4_R
MAKE_BASE=TRUE
PD_UPC1_DBG5_R
MAKE_BASE=TRUE
PD_UPC1_DBG0_R
PD_UPC1_DBG1_R
PD_UPC1_DBG2_R
PD_UPC1_DBG3_R
PD_UPC1_DBG4_R
PD_UPC1_DBG5_R
BI
BI
BI
BI
BI
BI
BI
BI
58 60 101
60 105
58
58
58
58
58
58
Non-debug Port
RF316
1/20W 201 MF 5%
RF317
2 1
100K
2 1
5% 1/20W MF 201
100K
PD_UPC0_DBG6_R
MAKE_BASE=TRUE
PD_UPC0_DBG7_R
MAKE_BASE=TRUE
RF328
RF329
5% 201 MF 1/20W
RF373
RF374
1/20W 201 MF 5%
RF375
PD_UPC0_DBG6_R
PD_UPC0_DBG7_R
2 1
2 1
2 1
2 1
2 1
100K
201 MF 5% 1/20W
100K
100K
201 MF 5% 1/20W
100K
100K
201 M 5% 1/20W
PD_UPC1_USBP2_RP
MAKE_BASE=TRUE
PD_UPC1_USBP2_RN
MAKE_BASE=TRUE
Ace2 GPIOs
PD_UPC1_GPIO7
PD_UPC1_GPIO9
PD_UPC1_GPIO10
CKPLUS_WAIVE=SINGLE_NODENET CKPLUS_WAIVE=SINGLE_NODENET CKPLUS_WAIVE=SINGLE_NODENET CKPLUS_WAIVE=SINGLE_NODENET CKPLUS_WAIVE=SINGLE_NODENET CKPLUS_WAIVE=SINGLE_NODENET CKPLUS_WAIVE=SINGLE_NODENET CKPLUS_WAIVE=SINGLE_NODENET CKPLUS_WAIVE=SINGLE_NODENET CKPLUS_WAIVE=SINGLE_NODENET CKPLUS_WAIVE=SINGLE_NODENET
on all nets above.
Unused ports
57
BI
57
BI
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PD_UPC1_USBP2_RP
PD_UPC1_USBP2_RN
PD_UPC1_GPIO7
PD_UPC1_GPIO9
PD_UPC1_GPIO10
RF326
RF327
OUT
OUT
OUT
2 1
2 1
MF 1/20W 201 5%
BI
BI
58
58
58
100K
100K
58
58
201 MF 1/20W 5%
PD_UPC1_DBG6_R
MAKE_BASE=TRUE
PD_UPC1_DBG7_R
MAKE_BASE=TRUE
PD_UPC1_DBG6_R
PD_UPC1_DBG7_R
BI
BI
58
58
RF31A
1/20W 5% MF 201
RF31B
5% 1/20W MF 201
2 1
2 1
100K
100K
PD UPC0_USBP3_RP
MAKE_BASE=TRUE
PD_UPC0_USBP3_RN
MAKE_BASE=TRUE
PD_UPC0_USBP3_RP
PD_UPC0_USBP3_RN
57
5
57
58
PP3V3_UPC0_LDO
OUT
BI
BI
OUT
USBC0_CC1
USBC0_CC2
PP3V3_UPC1_LDO
BI
BI
57
57
RF32A
1/20 MF 201 5%
RF32B
Connections for Laptops (USBC power in)
PACK_OPTION=USBC_LAPTOP PACK_OPTION=USBC_LAPTOP PACK_OPTION=USBC_LAPTOP PACK_OPTION=USBC_LAPTOP PACK_OPTION=USBC_LAPTOP PACK_OPTION=USBC_LAPTOP
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PP3V3_UPC0_LDO
USBC0_CC1
USBC0_CC2
PP3V3_UPC1_LDO
2 1
2 1
IN
BI
BI
IN
100K
100K
201 MF 5% 1/20W
55 57 89
57 59 89
57 59 89
58
PD_UPC1_USBP3_RP
MAKE_BASE RUE
PD_UPC1_USBP3_RN
MAKE_BASE=TRUE
PD_UPC1_USBP3_RP
PD_UPC1_USBP3_RN
B
BI
58
58
SYNC_DATE=02/01/2020 SYNC_MASTER=REF_USBC_ACE2
PAGE TITLE
A
USB-C: Support 2 ATC01
58
BI
58
BI
USBC1_CC1
USBC1_CC2
MAKE_BASE=TRUE
MAKE_BASE=TRUE
USBC1_CC1
USBC1_CC2
BI
BI
58 59 89
58 59 89
BOM_COST_GROUP=USB-C
2
1
Page 57
PPVBUS_USBC0
w w w . t e k n i s i - i n d o n e s i a . c o m
55 59 89
PP3V3_UPC0_LDO
1M
10K
1M
100K
100K
RF409
2 1
5% 201 MF
2 1
5%1M1/20W MF 201
2 1
5%
2 1
5% 1/20W 201 MF
2 1
5% 201 MF
2 1
/2 W
RF408
RF407
RF405
RF406
1/20W
RF402
MF 1/20W 5%
MF 1/20W
201
55 56 57 89
Internal Pull-ups
Enabled after reading straps
I2C_UPC0_ATCRTMR0_SCL
CKPLUS_WAIVE=I2C_PULLUP
I2C_UPC0_ATCRTMR0_SDA
CKPLUS_WAIVE=I2C_PULLUP
INT_I2C_UPC0_ATCRTMR0_L
201
UART_UPC01_RX
PD_UPC0_MRESET
PD_UPC0_GPIO5
Either a Testpoint or Arkanoid connector
must be present for GPIO0
(EVEN IN PRODUCTION)
53 55 5 60
53 55 57 60
55 57
57 55
57
57
REAR PORT:
FRONT PORT:
CRITICAL
15K
0.1%
0201
1
2
RF403
1/20W
TF-LF
CONNECT UPC SPI TO ROM
GROUND UPC SPI
GND I2C_ADDR
PRIMARY ONLY
PPHV_INT0_AONSW
MAX 100uF TOTAL ON RAIL
PP5V_S2
104 58
PP5V_S2
104 58
CAP FOR PP_5V0 ON VR PAGE
PD_UPC0_MRESET
57
53 55 60
OUT
55
OUT
55
OUT
55 57
IN
55
OUT
53 55
OUT
6 58 61
IN
56 96 107
OUT
34 58 90 100
OUT
56
IN
56
OUT
ATCRTMR0_RESET_L
UPC0_SER_DBG
FLASH_BUSY_USBC01_L
INT_I2C_UPC0_ATCRTMR0_L
UPC0_5V_EN
ATCRTMR0_FORCE_PWR
PD_UPC0_GPIO5
57
UPC_FORCE_PWR
UPC0_GPIO7
UPC_PMU_RESET_3V3
SOC_DFU_STATUS
SOC_FORCE_DFU
PP3V3_UPC0_LDO
56
GND
55
UPC0_R_OSC
53 55 57 60
BI
53 55 57 60
BI
41 55
BI
41 55
BI
55 107
OUT
43 55
BI
43 55
BI
55 107
OUT
55
OUT
55
OUT
55
IN
55
OUT
I2C_UPC0_ATCRTMR0_SDA
I2C_UPC0_ATCRTMR0_SCL
I2C_UPC_SDA
I2C_UPC_SCL
UPC_I2C_INT_L
I2C_SMC_UPC_SDA
I2C_SMC_UPC_SCL
UPC_SMC_I2C_INT_L
SPI_UPC01_R_CLK
SPI_UPC01_R_MOSI
SPI_UPC01_R_MISO
SPI_UPC01_R_CS_L
B13
A14
B17
A2
B1
D1
F1
C2
E2
B3
C4
D3
E4
F3
F7
A18
M19
M21
A16
B15
B5
A4
D7
B7
A6
C8
B9
B11
A10
A8
HRESET
MRESET
RESET*
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
BUSPOWER
I2C_ADDR
R_OSC
I2CM_SDA_CNFG
I2CM_SCL_CNFG
I2C_SDA1
I2C_SCL1
I2C_IRQ1*
I2C_SDA2
I2C_SCL2
I2C_IRQ2*
SPI_CLK
SPI_MOSI
SPI_MISO
SPI_SSZ
IPU-BOOT
UF400
CD3217B12BCE
FCBGA
DIGITAL CORE I/O & CONTROL POWER
TYPE-C
353S02158
CRITICAL
OMIT_TABLE
VIN_3V3
VDDIO
VDDIO_CFG
LDO_3V3
VIN_LV
VOUT_LV
VRET
SS
LDO_CORE
VBUS_OPT
PP_HV_OPT
C_CC1
C_CC2
RPD_G1
RPD_G2
C_USB_TP
C_USB_TN
C_USB_BP
C_USB_BN
C_SBU1
C_SBU2
C20
A12
D11
C22
D21
L20
L18
C16
L22
E22
D5
F5
M15
N16
M17
N18
L14
L16
K19
K21
J20
J22
J16
H15
10%
35V
X5R
0402
20%
6.3V
CERM
0402
20%
6.3V
X5R
1
2
1
2
1
2
CF401
1UF
CF400
10UF
CF402
1.0UF
0201-1
GND
UPC0_SS
PP1V5_UPC0_LDO_CORE
PPVBUS_USBC0
PPHV_INT0_AONSW
USBC0_CC1
USBC0_CC2
USBC0_CC1
USBC0_CC2
USBC0_USB_TOP_P
USBC0_USB_TOP_N
USBC0_USB_BOT_P
USBC0_USB_BOT_N
USBC0_SBU1
USBC0_SBU2
PP3V3_S2_UPC
MIN_LINE_WIDTH=0.2800
MIN_NECK_WIDTH=0.0750
VOLTAGE=3.3V
PP3V3_UPC0_LDO
1
CF408
10UF
20%
6 3V
2
CERM
0402
55
(cap needed when used as power source)
VOLTAGE=1.5V
MIN_LINE_WIDTH=0.2800
MIN_NECK_WIDTH=0.0750
55
55
56
BI
56
BI
59
BI
59
BI
59
BI
59
BI
59 89
BI
59 89
BI
PP1V25_S2
1
CF405
10UF
20%
6.3V
2
CERM
0402
102 58 55
102 58 55
1
2
55 56 57 89
PP1V8_S2
CF403
0.1UF
10%
6.3V
CERM-X5R
0201
USBC0_3V3LDO_EN
1
CF409
0.68UF
5%
6.3V
2
X6S
0402
MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0 1500
MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.1500
1
CF414
220PF
10%
25V
2
X7R-CERM
201 201
96
1
CF413
220PF
10%
25V
2
X7R-CERM
132S0212 132S0212
101 60 56
56 59 89
BI
56 59 89
BI
55
BI
55
BI
55 57
IN
55
OUT
61 89 91
BI
61 89 91
BI
56
BI
56
BI
56
BI
56
BI
53
BI
53
BI
55
OUT
56 96
BI
56 96
BI
56 96
BI
56 96
BI
56 96
OUT
56 96
BI
56
IN
56
OUT
SWD_UPC_SWDIO0
SWD_UPC_SWCLK
UART_UPC01_RX
UART_UPC01_TX
USB2_UPC0_P1_P
USB2_UPC0_P1_N
USB_DBG_LS_P
USB_DBG_LS_N
PD_UPC0_USBP3_RP
PD_UPC0_USBP3_RN
USBC0_AUXLSX_P
USBC0_AUXLSX_N
ROM_UPC01_WP_L
UART_DEBUGPRT_R2D
UART_DEBUGPRT_D2R
SWD_SOC_SWCLK
SWD_SOC_SWDIO
UART_SMC_DEBUGPRT_R2D
UART_SMC_DEBUGPRT_D2R
PD_UPC0_DBG6_R
PD_UPC0_DBG7_R
E20
E16
B19
A20
H19
H21
G20
G22
F19
F21
J12
H11
C12
G12
F11
E8
E12
G16
F15
D15
D19
SWD_DATA
SWD_CLK
UART_RX
UART_TX
USB_RP1_P
USB_RP1_N
USB_RP2_P
USB_RP2_N
USB_RP3_P
USB_RP3_N
AUX_P
AUX_N
HPD
DEBUG0
DEBUG1
DEBUG2
DEBUG3
DEBUG4
DEBUG5
DEBUG6
DEBUG7
IPU
IPU
GND_OPT
GND_OPT
GND_OPT
GND PORT_MUX
GND
GND_OPT
C18
E18
D17
G18
BOM_COST_GROUP=USB-C
PAGE TITLE
USB-C: Port Controller ATC0
SYNC_DATE=02/01/2020 SYNC_MASTER=REF_USBC_ACE2
A
Page 58
** OK2INTEGRATE **
w w w . t e k n i s i - i n d o n e s i a . c o m
PP3V3_UPC1_LDO
1M
1M
10K
1M
100K
100K
RF509
2 1
RF508
2 1
RF507
2 1
1/20W MF 5% 201
2 1
RF505
5% 1/20W 201 MF
2 1
RF506
5% 1/20W 201 MF
2 1
RF502
MF 201 1/20W 5%
56 58
MF 1/2 W 5% 201
201 MF 1/20W 5%
I2C_UPC1 ATCRTMR1_SCL
CKPLUS_ AI E I2C_PULLUP
I2C_UPC1_ATCRTMR1_SDA
CKPLUS_WAIVE=I2C_PULLUP
INT_I2C_UPC1_ATCRTMR1_L
UART_UPC01_TX
PD_UPC1_MRESET
PD_UPC1_GPIO5
Either a Testpoint or Arkanoid connector
must be present for GPIO0
(EVEN IN PRODUCTION)
54 55 58 6
54 55 58 60
55 58
58 55
58
58
REAR PORT:
FRONT PORT:
CRITICAL
15K
0.1%
0201
1
2
RF503
1/20W
TF-LF
CONNECT UPC SPI TO ROM
GROUND UPC SPI
PRIMARY ONLY
PPHV_INT1_AONSW
55
MAX 100uF TOTAL ON RAIL
PP5V_S2
104 57
PP5V_S2
104 57
CAP FOR PP_5V0 ON VR PAGE
PD_UPC1_MRESET
58
54 60
OUT
55
OUT
55
OUT
55 58
IN
55
OUT
54 55
OUT
6 57 61
IN
56
OUT
34 57 90 100
OUT
56
IN
56
OUT
ATCRTMR1_RESET_L
UPC1_SER_DBG
PD_UPC1_GPIO1
INT_I2C_UPC1_ATCRTMR1_L
UPC1_5V_EN
ATCRTMR1_FORCE_PWR
PD_UPC1_GPIO5
58
UPC_FORCE_PWR
PD_UPC1_GPIO7
UPC_PMU_RESET_3V3
PD_UPC1_GPIO9
PD_UPC1_GPIO10
PP3V3_UPC1_LDO
56
NC_UPC1_I2C_ADDR
55
UPC1_R_OSC
I2C_UPC1_ATCRTMR1_SDA
I2C_UPC1_ATCRTMR1_SCL
I2C_UPC_SDA
I2C_UPC_SCL
UPC_I2C_INT_L
I2C_SMC_UPC_SDA
I2C_SMC_UPC_SCL
UPC_SMC_I2C_INT_L
GND
GND
GND
GND
107
107
54 55 58 60
BI
54 55 58 60
BI
41
BI
41
BI
OUT
43
BI
43
BI
OUT
55
OUT
55
OUT
55
IN
55
OUT
B13
A14
B17
A2
B1
D1
F1
C2
E2
B3
C4
D3
E4
F3
F7
A18
M19
M21
A16
B15
B5
A4
D7
B7
A6
C8
B9
B11
A10
A8
HRESET
MRESET
RESET*
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
BUSPOWER
I2C_ADDR
R_OSC
I2CM_SDA_CNFG
I2CM_SCL_CNFG
I2C_SDA1
I2C_SCL1
I2C_IRQ1*
I2C_SDA2
I2C_SCL2
I2C_IRQ2*
SPI_CLK
SPI_MOSI
SPI_MISO
SPI_SSZ
IPU-BOOTGND I2C_ADDR
UF500
CD3217B12BCE
FCBGA
DIGITAL CORE I/O & CONTROL POWER
TYPE-C
353S02158
CRITICAL
OMIT_TABLE
VIN_3V3
VDDIO
VDDIO_CFG
LDO_3V3
VIN_LV
VOUT_LV
VRET
SS
LDO_CORE
VBUS_OPT
PP_HV_OPT
C_CC1
C_CC2
RPD_G1
RPD_G2
C_USB_TP
C_USB_TN
C_USB_BP
C_USB_BN
C_SBU1
C_SBU2
C20
A12
D11
C22
D21
L20
L18
C16
L22
E22
D5
F5
M15
N16
M17
N18
L14
L16
K19
K21
J20
J22
J16
H15
10%
35V
X5R
0402
20%
6.3V
CERM
0402
20%
6.3V
X5R
1
2
1
2
1
2
CF501
1UF
CF500
10UF
CF502
1.0UF
0201-1
GND
UPC1_SS
PP1V5_UPC1_LDO_CORE
PPVBUS_USBC1
PPHV_INT1_AONSW
USBC1_CC1
USBC1_CC2
USBC1_CC1
USBC1_CC2
USBC1_USB_TOP_P
USBC1_USB_TOP_N
USBC1_USB_BOT_P
USBC1_USB_BOT_N
USBC1_SBU1
USBC1_SBU2
PPVBUS_USBC1
PP3V3_S2_UPC
MIN_LINE_WIDTH=0.2800
MIN_NECK_WIDTH=0.0750
VOLTAGE=3.3V
PP3V3_UPC1_LDO
1
CF508
10UF
20%
6 3V
2
CERM
0402
55
(cap needed when used as power source)
VOLTAGE=1.5V
MIN_LINE_WIDTH=0.2800
MIN_NECK_WIDTH=0 0750
55
55
56
BI
56
BI
59
BI
59
BI
59
BI
59
BI
59 89
BI
59 89
BI
PP1V25_S2
1
CF505
10UF
20%
6.3V
2
CERM
0402
55 59 89
102 57 55
102 57 55
1
2
56 58
PP1V8_S2
CF503
0.1UF
10%
6.3V
CERM-X5R
0201
USBC1_3V3LDO_EN
1
CF509
0.68UF
5%
6.3V
2
X6S
0402
MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.1500
MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.1500
1
CF514
10% 10%
25V
2
X7R-CERM
201 201
107
1
CF513
220PF 220PF
25V
2
X7R-CERM
132S0212 132S0212
101 60 56
56 59 89
BI
56 59 89
BI
55
BI
55
BI
55 58
IN
55
OUT
61
BI
61
BI
56
BI
56
BI
56
BI
56
BI
54
BI
54
BI
55
OUT
56
BI
56
BI
56
BI
56
BI
56
OUT
56
BI
56
IN
56
OUT
SWD_UPC01_UART_DATA
SWD_UPC01_UART_CLK
UART_UPC01_TX
UART_UPC01_RX
USB2_UPC1_P1_P
USB2_UPC1_P1_N
PD_UPC1_USBP2_RP
PD_UPC1_USBP2_RN
PD_UPC1_USBP3_RP
PD_UPC1_USBP3_RN
USBC1_AUXLSX_P
USBC1_AUXLSX_N
PD_UPC1_HPD
PD_UPC1_DBG0_R
PD_UPC1_DBG1_R
PD_UPC1_DBG2_R
PD_UPC1_DBG3_R
PD_UPC1_DBG4_R
PD_UPC1_DBG5_R
PD_UPC1_DBG6_R
PD_UPC1_DBG7_R
E20
E16
B19
A20
H19
H21
G20
G22
F19
F21
J12
H11
C12
G12
F11
E8
E12
G16
F15
D15
D19
SWD_DATA
SWD_CLK
UART_RX
UART_TX
USB_RP1_P
USB_RP1_N
USB_RP2_P
USB_RP2_N
USB_RP3_P
USB_RP3_N
AUX_P
AUX_N
HPD
DEBUG0
DEBUG1
DEBUG2
DEBUG3
DEBUG4
DEBUG5
DEBUG6
DEBUG7
IPU
GND_OPT
GND_OPT
GND_OPT
GND PORT_MUX
GND
GND_OPT
C18
E18
D17
G18
BOM COST GROUP=USB-C
PAGE TITLE
2
SYNC_DATE=02/01/2020 SYNC_MASTER=REF_USBC_ACE2
USB-C: Port Controller ATC1
1
Page 59
---- Reference only ----
w w w . t e k n i s i - i n d o n e s i a . c o m
Left Rear Port
USBC0_CC1
56 57 89
107
107
107
107
107
107
107
107
IN
USBC0_R2D_CR_P<1>
IN
USBC0_D2R_N<1>
OUT
USBC0_D2R_P<1>
OUT
USBC0_SBU2
57 89
USBC0_USB_BOT_N
57
USBC0_USB_BOT_P
57
2
1
USBC1_USB_BOT_N
58
USBC1_USB_BOT_P
58
USBC1_SBU1
58 89
USBC1_R2D_CR_P<2>
IN
USBC1_R2D_CR_N<2>
IN
USBC1_D2R_P<2>
OUT
USBC1_D2R_N<2>
OUT
USBC1_CC2
56 58 89
2
1
2
1
2
1
RF661
RF660
RF663
RF662
2
1
RF680
RF681
RF682
RF683
2
1
2 1
USBC0_R2D_C_N<1> USBC0_R2D_CR_N<1>
5% 1/20W MF 201
1/20W
5%
5%
5% 1/20W MF 201
2
1
5% MF 201
5% 1/20W MF 201
5% 1/20W MF
5% MF 201
2
1
GND_VOID=TRUE
GND_VOID=TRUE
1 20W
GND_VOID=TRUE
GND_VOID=TRUE
1/20W
GND_VOID=TRUE
GND_VOID=TRUE
1/20W
GND_VOID=TRUE
2
2 1
USBC0_R2D_C_P<1>
2
MF 201
2 1
USBC0_D2R_R_N<1>
2
MF 201
2 1
USBC0_D2R_R_P<1>
2
2
1
2 1
USBC1_R2D_C_P<2>
2
2 1
USBC1_R2D_C_N<2>
2
2 1
USBC1_D2R_R_P<2>
2
201
2 1
USBC1_D2R_R_N<2>
2
2
1
FOR POR, VERIFY 20% TOLERANCE ON 0.22UF AC COUPLING CAP IS OK
PLACE VBUS CAP NEAR EACH VBUS PIN
BYPASS=JF600.57::10MM
CRITICAL CRITICAL
1
CF623
0 01UF
10%
25V
2
X5R-CERM
0201
BYPASS=JF600.57::10MM
CRITICAL
1
CF625
0.01UF
10%
25V
2
X5R-CERM
02 1
PLACE_NEAR=JF600 58:5MM
DF622
TVS2200
4
IN
5
IN
6
IN
ALLOW_APPLE_PREFIX=D
WSON
CRITICAL
K
DF620
X3-WLB1608-1
SDM2U40CSP
A
PPVBUS_USBC0
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=20V
55 57 89
516S00457
Mates with:
x on y
BYPASS=JF600.57::10MM
BYPASS=JF600.57::10MM
CRITICAL CRITICAL
1
CF620
0 01UF
10%
25V
2
X5R-CERM
0201
BYPASS=JF600.57::10MM
1
CF621
0.01UF
10%
25V
2
X5R-CERM
0201
BYPASS=JF600.57::10MM
CRITICAL CRITICAL
1
CF626
0.01UF
10%
25V
2
X5R-CERM
0 01
1
CF627
0.01UF
10%
25V
2
X5R-CERM
0201
BYPASS=JF600.5 ::10MM
1
CF622
0.01UF
10%
25V
2
X5R-CERM
0201
BYPASS=JF600.57::10MM
CRITICAL
1
CF628
0.01UF
10%
25V
2
X5R-CERM
0201
(NO LANE REVERSALS ALLOWED)
TP USBC0 PP20V
GND_VOID=TRUE GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
CER-X5R
CER-X5R
2
1
2
1
2
1
2
1
2
1
2
1
10% 25V 0201
10% 25V 0201
GND_VOID=TRUE
GND_VOID=TRUE
10% 25V X5R 201
10% 25V X5R
GND_VOID=TRUE
GND_VOID=TRUE
10% 25V CER-X5R 0201
10% 25V CER-X5R 0201
GND_VOID=TRUE
0.22UF
2 1CF661
25V 10% X5R 0201
0.22UF
2 1CF660
25V 10% X5R 0201
0.33UF
2 1CF663
0.33UF
2 1CF662
0.22UF
2 1CF680
0.22UF
2 1CF681
0.33UF
2 1CF682
0.33UF
2 1CF683
0201
USBC0_R2D_N<1>
USBC0_R2D_P<1>
JF600
20875-056E-01
F-ST-SM
PWR
58 57
USBC0_R2D_N<2>
USBC0_R2D_P<2>
USBC0_D2R_CR_N<1>
USBC0_D2R_CR_P<1>
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
1
2
1
2
1
2
1
2
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
USBC1_R2D_P<2>
SIGNAL
2 1
4 3
6 5
8 7
10 9
12 11
14 13
16 15
18 17
20 19
22 1
24 23
26 25
28 27
30 29
32 31
34 33
36 35
38 37
40 39
42 1
44 43
46 45
48 47
50 49
52 51
54 53
56 55
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
USBC0_D2R_CR_N<2>
USBC0_D2R_CR_P<2>
USBC1_R2D_P<1>
USBC1_R2D_N<1>
USBC1_R2D_N<2>
PWR
60 59
USBC1_D2R_CR_P<1>
USBC1_D2R_CR_P<2>
GND
USBC1_D2R_CR_N<2>
1
2
1
2
1
2
1
2
62 61
64 63
66 65
68 67
70 69
72 71
74 73
76 75
78 77
80 79
82 81
84 83
86 85
TP_USBC1_PP20V
USBC1_D2R_CR_N<1>
89
USBC0_CC2
0.22UF
GND_VOID=TRUE
10% 25V X5R 0201
0 22UF
10% 25V X5R 0201
GND_VOID=TRUE
2 1 CF691
2 1 CF690
USBC0_R2D_C_N<2>
USBC0_R2D_C_P<2>
5% 1/20W MF 201
5% 1/20W MF 201
GND_VOID=TRUE
2
2
GND_VOID=TRUE
RF691
2 1
RF690
2 1
USBC0_R2D_CR_N<2>
USBC0_R2D_CR_P<2>
USBC0_USB_TOP_P
USBC0_USB_TOP_N
0.33UF
CER-X5R
0.33UF
CER-X5R
GND_VOID=TRUE GND_VOID=TRUE
2 1 CF693
10% 25V 0201
2 1 CF692
10% 25V 0201
GND_VOID=TRUE
USBC0_D2R_R_N<2>
USBC0_D2R_R_P<2>
2
5% 1/20W MF 201
2
5% 1/20W MF 201
GND_VOID=TRUE
RF693
2 1
RF692
2 1
USBC0_D2R_N<2>
USBC0_D2R_P<2>
USBC0_SBU1
1
2
1
2
1
2
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
USBC1_SBU2
0.22UF
10%
0.22UF
10% 25V X5R 0201
GND_VOID=TRUE
2 1 CF670
2 1 CF671
GND_VOID=TRUE
25V X5R 0201
USBC1_R2D_C_P<1>
USBC1_R2D_C_N<1>
5% 1/20W MF 201
5% 1/20W MF 201
GND_VOID=TRUE
2
2
GND_VOID=TRUE
RF670
2 1
RF671
2 1
USBC1_R2D_CR_P<1>
USBC1_R2D_CR_N<1>
USBC1_USB_TOP_P
USBC1_USB_TOP_N
0 33UF
1 % 25V CER-X5R 0201
0.33UF
10% 25V CER-X5R 0201
GND_VOID=TRUE
2 1 CF672
2 1 CF673
GND_VOID=TRUE
USBC1_D2R_R_P<1>
USBC1_D2R_R_N<1>
5% 1 20 MF 201
5% 1/20W MF 201
GND_VOID=TRUE
2
2
GND_VOID=TRUE
RF672
2 1
RF673
2 1
USBC1_D2R_P<1>
USBC1_D2R_N<1>
USBC1_CC1
89
1
2
1
2
1
2
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
56 57 89
IN
IN
5
57
OUT
OUT
57 89
58 89
IN
IN
58
58
UT
OUT
56 58 89
107
107
107
107
107
107
107
107
PPVBUS_USBC1
55 58 89
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=20V
CRITICAL
DF600
X3-WLB1608-1
SDM2U40CSP
FOR POR, VERIFY 20% TOLERANCE ON 0.22UF AC COUPLING CAP IS OK
BYPASS=JF600 59: 0MM
CRITICAL
1
CF601
0.01UF
10%
25V
2
X5R-CERM
0201
BYPASS JF600.5 : 10MM
CRITICAL
1
CF607
0.01UF
10%
25V
2
X5R-CERM
0201
K
A
ALLOW_APPLE_PREFIX=D
PLACE_NEAR=JF600.59:5MM
DF602
TVS2200
WSON
4
IN
5
IN
6
IN
BYPASS=JF600.59::10MM
CRITICAL
1
CF600
0.01UF
10%
25V
2
X5R-CERM
0201
BYPASS=JF600.59::10MM
CRITICAL
1
CF606
0.01UF
10%
25V
2
X5R-CERM
0201
PLACE VBUS CAP NEAR EACH VBUS PIN
BYP SS=JF600.59::10MM
CRITICAL
1
CF602
0.01UF
10%
25V
2
X5R-CERM
0201
BYPASS=JF600.59::10MM
CRITICAL
1
CF608
0.01UF
10%
25V
2
X5R-CERM
0201
BYPASS=JF 0 59::10MM
CRITICAL
1
CF603
0.01UF
10%
25V
2
X5R-CERM
0201
BYPASS=JF600.59::10MM
CRITICAL
1
CF605
0.01UF
10%
25V
2
X5R-CERM
0201
SYNC_DATE=02/01/2020 SYNC_MASTER=KEI_T668_MLB
PAGE TITLE
USB-C: Connector(s)
Left Front Port
BOM_COST_GROUP=USB-C
Page 60
** OK2INTEGRATE **
w w w . t e k n i s i - i n d o n e s i a . c o m
3 2
PP3V3_S2SW_USBLS1_ISNS
105
PP1V8_S2_USBLS1_ISNS
105 60 56
104
PP3V3_S2SW_USB0
1
CF700
0.1UF
10%
10V
2
X5R-CERM
0201
1
CF701
0.1UF
10%
10V
2
X5R-CERM
0201
1
CF702
0.1UF
10%
10V
2
X5R-CERM
0201
VDD1V8 VDD3V3
OMIT_TABLE
INT_I2C_EUSBLS0_1V8_L
60
A4
INT
UF700
CD2E22
DSBGA
I2C_UPC0_ATCRTMR0_SCL_1V8
60
I2C_UPC0_ATCRTMR0_SDA_1V8
60
18
BI
18
BI
EUSB_ATC0_R_P
EUSB_ATC0_R_N
A3
A2
A1
B1
SCL
SDA
EDP0
EDN0
GPIO0
GPIO1
DPA
DNA
E2
E3
A5
B5
NC
NC
PP1V8_S2
1
CF703
0.1UF
10%
10V
2
X5R-CERM
0201
101 60 56
USB2_ATC0_LS_MUX_P
USB2_ATC0_LS_MUX_N
BI
BI
96 107
96 107
1
CF750
0.1UF
10%
10V 10V
2
X5R-CERM
0201
1
CF751
0.1UF
10%
2
X5R-CERM
0201
1
CF752
0.1UF
10%
10V
2
X5R-CERM
0201
VDD1V8 VDD3V3
1
CF753
0.1UF
10%
10V
2
X5R-CERM
0201
OMIT_TABLE
INT_I2C_EUSBLS1_1V8_L
6
A4
INT
UF750
CD2E22
DSBGA
I2C_UPC1_ATCRTMR1_SCL_1V8
60
I2C_UPC1_ATCRTMR1_SDA_1V8
60
18
BI
18
EUSB_ATC1_R_P
EUSB_ATC1_R_N
I
A3
A2
A1
B1
SCL
SDA
EDP0
EDN0
G IO0
GPIO1
DPA
DNA
CROSS
E2
E3
A5
B5
C2
NC
NC
USB2_ATC1_LS_P
USB2_ATC1_LS_N
BI
BI
1 7
107
9 18
BI
9 18
BI
107 96
101 60 56
53 55 57
53 55 57
CROSS
PACK_OPTION=USBC_DEBUG_UPC0 PACK_OPTION=USBC_DEBUG_UPC0 PACK_OPTION=USBC_DEBUG_UPC0 PACK_OPTION=USBC_DEBUG_UPC0
EUSB_DBG_P
MAKE_BASE=TRUE
EUSB_DBG_N
MAKE_BASE=TRUE
EUSB_DBG_P
EUSB_DBG_N
ATCRTMR0_RESET_MUX_1V8_L
PP1V8_S2
High:Select 1,8V I C, GPIOs.
E1
D1
E4
EDP1
EDN1
RESET*
VIOSEL
DPB
DNB
VPP/VSS
VSS
C2
E5
D5
C4 C3
USB_DBG_LS_MUX_P
USB_DBG_LS_MUX_N
USB_DBG_LS_MUX_P
USB_DBG_LS_MUX_N
PARROT 0 I2C/RESET LEVEL SHIFTERS
Pull ups on high-side
do most of the work.
PP1V8_S2
1
1
RF712
5.1K
1/20W
3
4
5%
MF
01
2
5.1K
5%
1/20W
MF
201
2
101 60 57 56
1
CF711
0.1UF
10%
6.3V
2
CERM-X5R
0201
I2C_UPC0_ATCRTMR0_SDA_1V8 I2C_UPC0_ATCRTMR0_SDA
I2C_UPC0_ATCRTMR0_SCL_1V8 I2C_UPC0_ATCRTMR0_SCL
104 60
BI
BI
PP3V3_S2SW_USB0
CF710
0.1UF
2 1
10%
6.3V
CERM-X5R
0201
RF703
200K
2 1
MF
1/20W 5% 201
VREFB_EUSBLS0
8
EN
6
B1
5
X2SON-COMBO
3 1S00234
RF713
VREF_A VREF_B
UF710
LSF0102
A1
GND
BI
BI
96 107
96 107
102 60
5
IN
TBT LS RX/TX LEVEL SHIFTERS
SOC
PP1V25_S2
10%
6.3V
0201
1
2
CF730
0.1UF
CERM-X5R
CIO_ATC0_LSTX_1V2
47K
5%
1/20W
MF
201
1
2
RF730
VCCA VCCB
5
DIR
A
UF730
SN74AXC1T45
SOT-5X3
B
GND
PP3V3_S2SW_USB0
4 3
CIO_ATC0_LSTX_3V3
105 60 56
BBR Retimer
1
CF731
0.1UF
10%
6.3V
2
CERM-X5R
0201
TP_EUSB_LS1POS
107
TP_EUSB_LS1NEG
107
ATCRTMR1_RESET_1V8_L
60
PP1V8_S2_USBLS1_ISNS
High:Select 1,8V I2C, GPIOs.
104 60
53
OUT
E1
D1
E4
EDP1
EDN1
RESET*
VIOSEL
DPB
DNB
VPP/VSS
VSS
E5
D5
C4 C3
NC_USB_LS1POS
NC_USB_LS1NEG
107
107
PARROT 1 I2C/RESET LEVEL SHIFTERS
RF753
200K
104 60
PP3V3_S2SW_USB1
CF760
0.1UF
2 1
10%
6.3V
CERM-X5R
0201
54 55 58
BI
5
BI
2 1
%MF01 1/20
VREFB_EUSBLS1
8
EN
6
B1
X2SON-COMBO
311S00234
RF763
VREF_A VREF_B
UF760
LSF0102
A1
A B2
GND A2 B2
Pull-ups on high-side
do most of the work.
PP1V8_S2
1
5.1K
5%
1/20W
MF
201
3
4
1
2
RF762
5.1K
5%
1/20W
MF
201
2
101 60 58 56
1
CF761
0.1UF
10%
6.3V
2
CERM-X5R
0201
I2C_UPC1_ATCRTMR1_SDA_1V8 I2C_UPC1_ATCRTMR1_SDA
I2C_UPC1_ATCRTMR1_SCL_1V8 I2C_UPC1_ATCRTMR1_SCL
60
60
102 60
SN74AUP1G17
5
OUT
CIO_ATC0_LSRX_1V2
NOSTUFF
RF735
PP1V8_S2
10%
6.3V
0201
1
1
RF720
2
VCC
UF720
74AUP1G07GF
SOT891
4
Y A
5
NC NC
NC NC
G D
2
1
1.5K
5%
1/20W
MF
201
2
INT_I2C_EUSBLS0_1V8_L
CF720
0.1UF
CERM-X5R
55
OUT
INT_I2C_EUSBLS0_L
101 60 57 56
102 60
CF740
60
5
IN
CIO_ATC1_LSTX_1V2
RF740
PP1V8_S2
10%
6.3V
0201
1
2
UF725
VCC
GND
SN74AUP1G17
SON
4 2
NC
NC
ATCRTMR0_RESET_1V8_L ATCRTMR0_RESET_L
CF725
0.1UF
CERM-X5R
53 55 57
IN
101 60 57 56
96
5
OUT
CIO_ATC1_LSRX_1V2
1
47K
5%
1/20W
MF
201
2
0.1UF
10%
6.3V
CERM-X5R
0201
1
47K
5%
1/20W
MF
201
2
PP1V25_S2
1
2
102 60
SN74AUP1G17
NOSTUFF
NC
NC
RF745
47K
5%
1/20W
MF
201
1
2
PP1V25_S2
UF735
SON
4 2
5
PP1V25_S2
UF745
SON
4 2
VCC
NC
NC
GND
UF740
SN74AXC1T45
SOT-5X3
VCCA VCCB
DIR
A
GND
VCC
NC
NC
GND
1
CF735
0.1UF
10%
6.3V
2
CERM X5R
02 1
CIO_ATC0_LSRX_3V3
PP3V3_S2SW_USB1
1
CF741
0.1UF
10%
6.3V
2
CERM-X5R
0201
4 3
B
CIO_ATC1_LSTX_3V3
1
CF745
0 1UF
10%
6.3V
2
CERM-X5R
0201
CIO_ATC1_LSRX_3V3
IN
IN
OU
53
PP1V8_S2
10%
6.3V
0201
1
2
1
1
RF770
2
VCC
UF770
74AUP1G07GF
SOT891
4
Y A
5
NC NC
NC NC
GND
2
1
1.5K
5%
1/20W
MF
201
2
INT_I2C_EUSBLS1_1V8_L INT_I2C_EUSBLS1_L
UF775
VCC
GND
SN74AUP1G17
SON
4 2
NC
NC
NC
NC
60
PAGE TITLE
CF770
0.1UF
104 60
CERM-X5R
55
OUT
101 60 58 56
54
PP1V8_S2
CF765
0.1UF
10%
6.3V
CERM-X5R
0201
54 58
ATCRTMR1_RESET_L ATCRTMR1_RESET_1V8_L
IN
101 60 58 56
60
SY C_DA E=0 /04 2020 YNC_MAS ER=R F_U BC_ CE2
USB-C: HS Level Shifters
54
BOM_COST_GROUP=USB-C
3
2
1
Page 61
LF800
w w w . t e k n i s i - i n d o n e s i a . c o m
90-OHM-0.1A
EXCX4CE
SYM_VER-1
96
BI
USB2_ATC0_LS_N
1
4
USB2_UPC0_P1_N
BI
57 89 91
96
BI
USB2_ATC0_LS_P
PLACE_NEAR=UF400:5MM
3 2
USB2_UPC0_P1_P
155S0667
LF810
90-OHM-0.1A
EXCX4CE
SYM_VER-1
107
107
BI
BI
USB2_ATC1_LS_P
USB2_ATC1_LS_N
1
PLACE_NEAR UF500:5MM
4
3 2
USB2_UPC1_P1_P
USB2_UPC1_P1_N
155S0667
NOTE: CHOKE PINOUT IS DIFFERENT BETWEEN LANE 0 AND LANE 1 FOR EASE OF ROUTING
BI
BI
BI
57 89 91
58
58
<RDAR://59047957>
UPC_FORCE_PWR
6 57 58
1
RF850
47K
5%
/20W
MF
201
2
PAGE TITLE
USB-C: SUPPORT
BOM_COST_GROUP=USB-C
Page 62
*** OK2INTEGRATE ***
w w w . t e k n i s i - i n d o n e s i a . c o m
RASPUTIN WIFI/BT MODULE
FOR HOSTINTERFACE TABLES REFER TO
RDAR://PROBLEM/53187294
105 62
PP1V8_S2_WLBT_ISNS
105
PP3V3_S2_WLBT_ISNS
1
2
1 CL012
2
CL002
10UF
20%
10V
X5R-CERM
0402-8
10UF
20%
10V
X5R-CERM
0402-8
1
CL021
10UF
20%
2
10V
X5R-CERM
0402-8
CRITICAL
1
CL003
3.0PF
+/-0.1PF
2
25V
NP0-C0G
CRITICAL
1CL013
3.0PF
+/-0.1PF
2
25V
NP0-C0G
0201
CRITICAL
1 CL022
3.0PF
+/-0.1PF
2
25V
NP0-C0G
0201
CRITICAL
1
CL004
12PF
5%
2
25V
NP0-C0G
0201 0201
CRITICAL
1 CL014
12PF
5%
2
25V
NP0-C0G
0201
CRITICAL
1
CL023
12PF
5%
2
25V
NP0-C0G
0201
CRITICAL
1
CL031
3.0PF
/-0.1PF
2
25V
NP0-C0G
0201
CRITICAL
1
CL041
3.0PF
+/-0.1PF
2
25V
NP0-C0G
0201
CRITICAL
1
CL051
3.0PF
+/-0.1PF
2
25V
NP0-C0G
0201
PP3V3_S2_WLBT_ISNS
CRITICAL
1
CL032
12PF
5%
2
25V
NP0-C0G
0201 0402-8
1
CL033
10UF
20%
2
10V
X5R-CERM
CRITICAL
1
CL042
12PF
5%
2
25V
NP0-C0G X5R-CERM
0201
1
CL043
10UF
20%
2
10V
0402-8
CRITICAL
1
CL052
12PF
5%
2
25V
NP0-C0G X5R-CERM
0201
1
CL053
10UF
20%
2
10V
0402-8
105 62
1
TPL001
TPL002
TPL003
TPL004
TPL005
TPL006
TPL007
TPL008
TPL009
TP
TP-P55
TP
TP-P55
TP
TP-P55
1
TP
TP-P55
1
TP
TP-P55
1
TP
TP-P55
1
TP
TP 55
1
TP
TP-P55
1
TP
TP-P55
PMU_CLK32K_WLBT
WLBT_PWR_EN
1
1
WLBT_WAKE
TP_WLAN_JTAG_TCK
TP_WLAN_JTAG_TMS
TP_WLAN_JTAG_TDI
TP_WLAN_JTAG_TDO
TP_WLAN_JTAG_TRSTN
WLAN_JTAG_SEL
3 62 63
33 62 63 94
33 62 63
62
62
62 63
62 63
62
62
PP1V25_S2 102 62
CRITICAL
1
CL061
OMIT_TABLE
UL000
VDDIO_ZONE2
85
LBEE5XV1YR-506
LGA
63
BI
63
BI
63
BI
RF_ANT_0
RF_ANT_1
RF_BT_DED
NC
NC
6 62 63
BT_TIME_SYNC_1V8
OUT
BT_R1_WAKE
62
BT_R1_TIME_SYNC
62 63
NC
NC
NC
NC
NC
NC
SPMI_WLBT_CLK_1V8
62
SPMI_WLBT_DAT_1V8
62
NC
33 62 63 94
IN
33 62 63
IN
WLBT_PWR_EN
PMU_CLK32K_WLBT
27
89
44
133
124
37
123
36
38
125
39
126
507
528
517
518
48
76
153
ANT_C0
ANT_C1
BT_DEDICATED
BT_GPIO_1
BT_GPIO_2
BT_GPIO_3
BT_GPIO_4
BT_GPIO_5
BT_I2S_DI
BT_I2S_DO
BT_I2S_CLK
BT_I2S_WS
RF_SW_CTRL_18
RF_SW_CTRL_19
LHL_GPIO0
LHL_GPIO1
LHL_GPIO2
WLBT_REG_ON
CLK_32K
GPIO HW SETTINGS:
VDDIO|RESET|POST-RESET
1.8V|HZ|NP
1.8V|HZ|PD
1.8V|HZ|PD
1.8V|HZ|PU
1.8V|HZ|PU
SYM 1 OF 4
1.8V|HZ|PD
1.8V|HZ|PU
1.8V|HZ|PU
1.8V|HZ|PU
1.8V|HZ|NP
1.8V|HZ|PU
1.8V|HZ|PD
1.2V|HZ|HZ
1.2V|PU|PU
1.2V|HZ|HZ
1.2V|PU|PU
1.8V|HZ|HZ
1.2V|HZ|HZ
1.2V|PU|PU
1.8V|HZ|HZ
1.8V|HZ|HZ
1.8V|HZ|HZ
1.8V|HZ|HZ
1.8V|HZ|HZ
1.2V|HZ|HZ
1.2V
1.2V
WLBT_HOST_WAKE
WL_GPIO_2
WL_GPIO_3
WL_GPIO_4
WL_GPIO_5
WL_GPIO_6
WL_GPIO_7
WL_GPIO_8
WL_GPIO_9
WL_GPIO_10
WL_GPIO_11
WL_GPIO_12
WL_GPIO_13
WL_GPIO_14
WL_GPIO_15
WL_GPIO_16
WL_GPIO_17
WL_GPIO_18
WL_GPIO_19
WL_GPIO_20
PCI_PME_L
PCIE_PERST_L
PCIE_CLKREQ_L
PCIE_RXD_P
PCIE_RXD_N
PCIE_TXD_P
PCIE_TXD_N
145
149
65
64
61
62
134
66
150
67
151
525
161
78
504
160
77
524
503
68
60
127
40
142
143
139
140
WLBT_WAKE
TP_WLAN_JTAG_TCK
TP_WLAN_JTAG_TMS
TP_WLAN_JTAG_TDI
TP_WLAN_JTAG_TDO
TP_WLAN_JTAG_TRSTN
UART_WLAN_R2D
UART_WLAN_D2R
UART_WLAN_R2D_RTS_L
UART_WLAN_D2R_CTS_L
WLAN_TIME_SYNC_1V8
WLAN_CONTEXT_A
WLAN_CONTEXT_B
WLBT_RESET_L
WLBT_CLKREQ_R_L
PCIE_WLBT_R2D_P
PCIE_WLBT_R2D_N
PCIE_WLBT_D2R_C_P
PCIE_WLBT_D2R_C_N
2
12PF
5%
25V
NP0-C0G
0201
62
62
62 63
62 63
62
NC
NC
NC
NC
NC
NC
NC
NC
62
62
62
62
62
CRITICAL
CL062
2
33 62 63
OUT
6 62
IN
6 62
OUT
6 62
IN
6 62
OUT
62 63
OUT
9 62 63
IN
9 62 63
IN
8 62 63
IN
3.0PF
+/-0.1PF
25V
NP0-C0G
0201
1
TPL012
TPL013 PACK_IGNORE=TRUE
TPL014 PACK_IGNORE= RUE
TPL017
TPL018
TPL019
TPL020
TPL021
TPL022
TPL023
TPL024 PACK_IGNORE=TRUE
TPL025 PACK_IGNORE=TRUE
TP
TP-P55
1
TP
TP-P55
1
TP
1
TP
TP-P55
1
TP
TP-P55
1
TP
TP P55
1
TP
TP-P55
1
TP
TP-P55
1
TP
TP-P55
1
TP
TP P55
1
TP
1
TP
TP-P55 PACK_OPTION=CARLSBERG
BT_TIME_SYNC_1V8
BT_R1_WAKE
PACK_OPTION=CARLSBERG
BT_R1_TIME_SYNC
PACK_OPTION=CARLSBERGTP-P55
UART_WLAN_R2D
UART_WLAN_D2R
UART_WLAN_R2D_RTS_L
UART_WLAN_D2R_CTS_L
WLAN_TIME_SYNC_1V8
WLAN_CONTEXT_A
WLAN_CONTEXT_B
SPMI WLBT CLK 1V8
PACK_OPTION=CARLSBERGTP-P55
SPMI WLBT DAT 1V8
6 62 63
62
63
6 62
62
6 62
6 62
62 63
62 63
9 62 63
62
62
RASPUTIN BOM TABLE:
REFERENCE DESIGNATOR(S) QTY DESCRIPTION PART#
MODULE, WLAN BT, RASPUTIN, ES6.11, M, LGA549339S00763
1 UL000 CRITICAL
136
PCIE_REFCLK_P
PCIE_REFCLK_N
62 63
RL005
RL003
T BLE_5_HE D
BOM OPTION CRITICAL
T BLE_5_IT M
10K
MF 1/20W 201
10K
2 1
5%
2 1
201 1/20W MF
5%
GND_VOID=TRUE
WLAN_JTAG_SEL
WLBT_PACKAGE_OPTION_2
NOSTUFF
PLACE_NEAR=UL000.142:4MM
62
WLBT_CLKREQ_R_L
62
PCIE_CLK100M_WLBT_P
137
PCIE_CLK100M_WLBT_N
102 62
PP1V25_S2
WLAN_TIME_SYNC_1V8
RL006
MF 1/20W 201
RL002
100K
GND_VOID=TRUE PLACE_NEAR=U0600.BE30:10MM
5%
1K
5%
2 1
201
2 1
MF 1/20W
WLBT_CLKREQ_L
IN
IN
V C
GND
8 62
8 62
UL001
SN74AUP1G17
SON
4 2
NC
NC
1
CL071
0.1UF
10%
6.3V
2
CERM-X5R
0201
WLAN_TIME_SYNC
8 62 63
BI
OUT
PPL030
P4MM
PPL031
P4MM
TPL032
TPL033
PAGE TITLE
SM
1
PP
SM
1
P
1
TP
TP-P55
1
TP
TP-P55
PCIE_CLK100M_WLBT_P
PCIE_CLK100M_WLBT_N
WLBT_RESET_L
WLBT_CLKREQ_L
62
8 62
8 62 63
8 62 63
WIFI/BT: MODULE
SYNC_DATE=02/01/2020 SYN C_MASTER=REF_WI ELESS_R IN
SIZE DRAWING NUMBER
8
IN
PCIE_WLBT_R2D_C_P
0 1UF
CL009
CL010
8
PCIE_WLBT_R2D_C_N
0 1UF
GND_VOID=TRUE
2 1
CERM-X5R
0201 6.3V 10%
2 1
CERM-X5R
0201 6.3V 10%
PLACE_NEAR=UL000.143:4MM
PCIE_WLBT_R2D_P
PCIE_WLBT_R2D_N
62
62
62
62
PCIE_WLBT_D2R_C_N
0 1UF
0 1UF
CL008
6.3V 0201
10%
CL007
10% 6.3V
GND_VOID=TRUE
2 1
2 1
0201
CERM-X5R
CERM-X5R
PLACE_NEAR=U0600.BF30:10MM
PCIE_WLBT_D2R_P PCIE_WLBT_D2R_C_P
PCIE_WLBT_D2R_N
OUT
O T IN
8
8
BOM_COST_GROUP=WIRELESS
3 4
Page 63
*** OK2INTEGRATE ***
w w w . t e k n i s i - i n d o n e s i a . c o m
RASPUTIN WIFI/BT MODULE GND
OMIT_TABLE
OMIT_TABLE
OMIT_TABLE
ANTENNA CONNECTORS
10
15
16
17
18
19
20
24
25
26
28
29
30
33
34
35
41
43
45
46
47
50
51
52
53
54
55
56
57
58
59
69
70
71
75
79
80
81
84
86
87
88
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
UL000
1
2
6
7
8
9
LBEE5XV1YR-506
LGA
SYM 2 OF 4
GND GND
119
120
121
122
128
129
130
131
132
135
138
141
144
146
147
148
154
158
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
UL000
LBEE5XV1YR-506
LGA
SYM 3 OF 4
GND
GND
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
UL000
LBEE5XV1YR-506
LGA
SYM 4 OF 4
GND
GND
463
464
465
46
467
468
469
470
471
472
473
474
475
47
477
478
479
480
481
482
483
484
485
48
487
488
489
490
491
492
493
494
495
49
497
498
499
500
501
502
505
506
508
50
510
511
512
513
514
515
516
519
520
52
522
523
526
527
529
530
531
532
533
53
535
536
537
538
539
540
541
542
543
54
545
546
547
548
549
2G_C1
5G_C0
BT_C0
2G_C0
5G_C1
BT_C1
JL102
IR050D15010C
F-ST-SM
BT_C0_DED
JL122
20431-001E-01
F-ST SM
SIGNAL
GND
WLBT DEBUG CONNECTOR
JL100
IR050D15010C
F-ST-SM
RF_CONN
JL110
20449-001E-03
F-ST SM
JL101
IR050D15010C
F-ST-S
RF_CONN
JL111
20449-001E-03
RF_BT_DED_ANT
1
63
PACK_IGNORE=TRUE
PACK_OPTION=ANT_T664
12
RF_BT_DED_ANT
PACK_OPTION=ANT_MAC_MINI
F-ST-SM
PACK_IGNORE=TRUE
PACK_OPTION=3X_ANTENNA
JL103
505070-1222
14 13
RF_ANT_0
1
PACK_IGNORE=TRUE
PACK_OPTION=SUNWAY
1
PACK_OPTION=IPEX
518S0867
1
RF_ANT_1
PACK_IGNORE=TRUE
PACK_OPTION=SUNWAY
1
PACK_OPTION=IPEX
518S0867
PACK_IGNORE=TRUE
PACK_OPTION=3X_ANTENNA
RL102
1
2
1 2
CL101
0.3PF
+/-0.1PF
25V
C0G-CERM
201
NOSTUFF
63
PACK_IGNORE=TRUE
M-ST-SM
0
5%
201 MF 1/20W
PACK_IGNORE=TRUE
BI
BI
1
CL102
0.3PF
+/-0.1PF
25V
2
C0G-CERM
201
NOSTUFF
62 63
62 63
JL120
20431-001E-01
F-ST-SM
GND
SIGNAL
1
JL121
20431-001E-01
PACK_IGNORE=TRUE
PACK_OPTION=3X_ANTENNA
F-ST-SM
GND
SIGNAL
12
UL101
2.4G
1 3
0603
OUT IN
GND
2 4
RF_ANT_0 RF_ANT_0
PACK_OPTION=ANT_MAC_MINI
RF_ANT_1 RF_ANT_1
PACK_OPTION=ANT_MAC_MINI
PACK_IGNORE=TRUE PACK_OPTION=3X_ANTENNA
PACK_OPTION=3X_ANTENNA
62 63 62 63
62 63 62 63
PACK_IGNORE=TRUE
PACK OPTION=3X_ANTENNA
RL104
1/20W MF 0201
1
2
PACK_IGNORE=TRUE
PACK_IGNORE=TRUE
0
1 2
5%
CL103
0.3PF
+/-0.1PF
25V
C0G-CERM
201
NOSTUFF
PACK_IGNORE=TRUE
PACK_OPTION=3X_ANTENNA
RF_BT_DED RF_BT_DED_FIN RF_BT_DED_FOUT
1
CL105
0.3PF
+/-0.1PF
25V
2
C0G-CERM
201
NOSTUFF
BI
62
WLAN_TIME_SYNC_1V8
62
WLAN_CONTEXT_A
9 62
WLAN_CONTEXT_B
9 62
WLBT_WAKE
33 62
WLBT_PWR_EN
33 62 94
WLBT_RESET_L
8 62
2 1
4 3
6 5
8 7
10 9
12 11
16
TP_WLAN_JTAG_TDI
TP_WLAN_JTAG_TDO
BT_R1_TIME_SYNC
WLBT_CLKREQ_L
BT_TIME_SYNC_1V8
PMU_CLK32K_WLBT
15
BOMOPTION=WLBT_DBG
PACK_OPTION=WLBT_DBG_CONN
62
62
62
8 62
6 62
33 62
BOM_COST_GROUP=WIRELESS
S NC_MASTER=REF_WIRELESS_ ASPUTIN SY C_DA E=0 /01 2020
PAGE TITLE
WIFI/BT: ANTENNA and GND
2
1
Page 64
*** OK2INTEGRATE ***
www.teknisi-indonesia.com
w w w . t e k n i s i - i n d o n e s i a . c o m
NAND0 S5E0
102 65
102 64
PP0V88_AWAKESW_NAND
1
CN010
20UF
20% 20%
10V
2
X5R
0402
RN010
PP1V25_AWAKESW_VCCQ
1/20W
PLACE NEAR=UN000.L2:10MM
0201
FLN000
10OHM-50%-1A-0.05OHM
PLACE_NEAR=UN000.J6:10MM
The inductance from CN047, CN046, CN045, CN044 to
their S5E pins shall be less than 1100pH
2
1%
MF
0201
1
CN011
20UF
10V
2
X5R
0402
2 1
2 1
1
CN012
2.2UF
20%
10V
2
X5R
0201
1
CN047
2.2UF
20%
10V
2
X5R
0201
1
CN045
4.7UF
20%
4V
2
CER-X5R
0201
1
CN013
2.2UF
20%
10V
2
X5R
0201
67
67
1
CN046
0.1UF
10%
6.3V
2
CERM-X5R
0201
1
CN044
0 1UF
10%
6 3V
2
CERM-X5R
0201
1
CN014
2.2UF
20%
10V
2
X5R
0201
1
CN015
0.1UF
10%
6.3V
2
CERM-X5R
0201
TP_NAND0_S5E0_ANI1_VREF
TP_NAND0_S5E0_ANI0_VREF
MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.1000
VOLTAGE=1.2V
PP1V2_NAND0_S5E0_AVDD1X_PLL
MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.1000
VOLTAGE=1.2V
PP1V2_NAND0_S5E0_PCI_AVDD_H
1
CN016
0.1UF
10%
6.3V
2
CERM-X5R
0201
1
CN017
0.1UF
10%
6.3V
2
CERM-X5R
0201
1
CN032
20UF
20%
10V
2
X5R
0402
CN030
4.3UF
20%
4V
CERM
0402
1
3
4
2
1
CN034
2.2UF
20%
10V 10V
2
X5R
0201
1
CN020
20UF
20%
10V
2
X5R
0402 0201
MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.1000
VOLTAGE=0.9V
1
CN022
2.2UF
20%
10V
2
X5R
0201
1
CN035
2.2UF
20%
2
X5R
0201
1
2
CN023
2.2UF
20%
10V
X5R
0201
1
CN036
2.2UF
20%
10V
2
X5R
0201
1
2
CN024
2.2UF
20%
10V
X5R
0201
1
CN037
2.2UF
20%
10V
2
X5R
0201 0201
1
2
10OHM-50%-1A-0.05OHM
PP0V9_S5E0_VDD_PLL107
TP_NAND0_S5E0_VPP
PLACE_NEAR=UN000.R4:10MM
CN025
2.2UF
20%
10V
X5R
FLN001
0201
1
CN038
2.2UF
20%
10V
2
X5R
2 1
1
CN039
2.2UF
20%
10V
2
X5R
0201
PLACE_NEAR=FLN001.2:5MM
1
CN083
4.7UF
20%
4V
2
CER-X5R
0201
PP1V25_AWAKESW_VCCQ
1
CN03A
2.2UF
20%
10V
2
X5R
0201
PP2V5_AWAKE_NAND
PP0V88_AWAKESW_NAND
102 64
101 66 65
102 64
67
1
1
CN085
10PF
5%
25V
2
C0G
0201
8
IN
8
IN
8
OUT
8
OUT
PCIE_NAND0_R2D_C_P<0>
PCIE_NAND0_R2D_C_N<0>
PCIE_NAND0_D2R_P<0>
PCIE_NAND0_D2R_N<0>
RN004
2 0
0.1%
1/20W
TK
0201-1
2
GND_VOID=TRUE
0.22UF
GND_VOID=TRUE
0.22UF
GND_VOID=TRUE
0.22UF
GND_VOID=TRUE
0.22UF
2 1CN003
10% 6.3V
2 1CN004
6.3V
10%
2 1CN001
6.3V 10%
2 1CN002
10%
6.3V
PLACE_NEAR=UN000.C10:15MM
1
RN006
3 0
1%
1/20W
MF
201
2
IN
8 67
8 67
IN
67
OUT
X5R-CERM
X5R-CERM
X5R-CERM
X5R-C RM
6 65 67
IN
NAND0_CLK24M_0
PCIE_CLK100M_NAND0_0_P
N
PCIE_CLK100M_NAND0_0_N
NAND0_CLKREQ0_R_L
NAND0_S5E0_PCIE_RESREF
67
PCIE_NAND0_R2D_P<0>
0201
PCIE_NAND0_R2D_N<0>
0201
PCIE_NAND0_D2R_C_P<0>
0201
PCIE_NAND0_D2R_C N<0>
0201
NAND0_RESET_L
NAND0_JTAG_TRST_L
64 65 67
NAND0_S5E0_ZQ_0
67
NAND0_S5E0_ZQ_1
67
PLACE_NEAR=UN000.K3:15MM
1
RN005
300
1%
1/20W
MF
201
2
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_ OID=TRUE
M3
K11
J12
P5
H7
M11
N12
R12
T11
L4
G10
C10
K3
CLK_IN
PCIE_REFCLK_P
PCIE_REFCLK_N
PCIE_ LKREQ*
PCIE_RESREF
PCIE_RX0_P
PCIE_RX0_N
PCIE_TX0_P
PCIE_TX0_N
RESET*
TRST*
ZQ_0
ZQ_1
OMIT_TABLE
UN000
S5E-MCP-STUDY
LGA
EXT_D0/BOOT0
EXT_D1/BOOT1
EXT_D2/BOOT2/SPINAND_SCLK
EXT_D3/SWD_UID0/SPINAND_MISO
EXT_D4/SPI_CS
EXT_D5/SWD_UID1/SPINAND_MOSI
EXT_D6/BOOT3
EXT_D7/SPF
EXT_DQS/BCM*
EXT_NCE/PERST*
EXT_NRE/JTAG_TMS
EXT_NWE/JTAG_TCK
EXT_RNB/JTAG_TDO
EXT_CLE/JTAG_TDI
EXT_ALE/JTAG_SEL
DROOP*
WP*
B3
NAND0_LPB_L
C4
NAND_BFH
B5
NAND0_BOOT2
C6
NAND0_S5E0_SWD_UID0
B7
C8
NAND0_S5E0_SWD_UID1
B9
B11
NAND0_PFN_L
D11
NAND0_BCM_L
E8
NAND0_PCIE_RESET_L
D7
SWD_NAND0_SWDIO
E6
SWD_NAND0_SWCLK
E4
NAND0_S5E0_JTAG_TDO
D5
TP_NAND0_S5E0_JTAG_TDI
D9
NAND0_JTAG_SEL
T3
TP_NAND0_S5E0_DROOP_L
G2
NAND0_WP_L
IN
N
64 65 67
64 67
64 67
IN
64 65
IN
I
IN
OUT
IN
64 65 67
4 65 67
33 65 67
6 65 67
65 67
8 65 67
107
107
65 67
67
NAND0_BOOT2
64 65 67
NAND0_JTAG_SEL
64 65 67
NAND0_JTAG_TRST_L
64 65 67
1
RN000
47K
1%
1/20W
MF
201
2
1
RN002
47K
1%
1/20W
MF
201
2
1
RN021
0
5%
1/20W
MF
0201
2
Spec recommends to tie Boot2 directly to Gnd
PP V 5_AWAKESW_VCCQ
1
RN001
0
5%
1/20W
MF
0201 0201
2
64 65
64 65 7
NAND0_BCM_L
NAND0_WP_L
1
RN007
0
5%
1/20W
MF
2
Spec recommends to tie BCM, WP directly to 1.2V rail
SYNC_MASTER=REF_STORAGE_S5E SYNC_DATE=04/27/2020
102 65 64
64 6
64 67
NAND0_S5E0_SWD_UID0
NAND0_S5E0_SWD_UID1
1
RN009
47K
1%
/20W
MF
201
2
1
RN008
47K
1%
1/20W
MF
201
2
PAGE TITLE
STORAGE: SSD0 S5E <0>
BOM_COST_GROUP=SSD
2
1 3 5
Page 65
*** OK2INTEGRATE ***
w w w . t e k n i s i - i n d o n e s i a . c o m
NAND0 S5E1
102 65 64
102 65
PP0V88_AWAKESW_NAND
SSD_2L
1
CN110
20UF
20%
10V
2
X5R
0402
SSD_2L
RN110
PP1V25_AWAKESW_VCCQ
1/20W
PLACE NEAR=UN100.L2:10MM
0201
SSD_2L
FLN100
10OHM-50%-1A-0.05OHM
PLACE_NEAR=UN100.J6:10MM
The inductance from CN147, CN146, CN145, CN144 to
their S5E pins shall be less than 1100pH
2
1%
MF
0201
SSD_2L
1
CN111
20UF
20%
10V
2
X5R
0402
2 1
2 1
SSD_2L SSD_2L SSD_2L
1
CN112
2.2UF
20%
10V
2
X5R
0201
1
CN113
2.2UF
20%
10V
2
X5R
0201
67
67
MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.1000
VOLTAGE=1.2V
1
CN114
2.2UF
20%
10V
2
X5R
0201
TP_NAND0_S5E1_ANI1_VREF
TP_NAND0_S5E1_ANI0_VREF
PP1V2_NAND0_S5E1_AVDD1X_PLL
SSD_2L SSD_2L
1
CN147
2.2UF
20%
10V
2
X5R
0201
1
CN146
0.1UF
10%
6.3V
2
CERM-X5R
0201
MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.1000
VOLTAGE=1.2V
PP1V2_NAND0_S5E1_PCI_AVDD_H
SSD_2L
1
CN145
4.7UF
20%
4V
2
CER-X5R
0201
SSD_2L
1
CN144
0 1UF
10%
6 3V
2
CERM-X5R
0201
1
CN115
0.1UF
10%
6.3V
2
CERM-X5R
0201
1
CN116
0.1UF
10%
6.3V
2
CERM-X5R
0201
SSD_2L SSD_2L SSD_ L
1
CN117
0.1UF
10%
6.3V
2
CERM-X5R
0201
SSD_2L
1
CN132
20UF
20%
10V
2
X5R
0402
SSD_2L
CN130
4.3UF
20%
4V
CERM
0402
1
3
4
2
SSD_2L
1
CN134
2.2UF
20%
10V
2
X5R
0201
SSD_2L SSD_2L
1
CN120
20UF
20%
10V
2
X5R
0402
MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.1000
VOLTAGE=0.9V
1
CN122
2.2UF
20%
10V
2
X5R
0201
PP0V9_S5E1_VDD_PLL107
TP_NAND0_S5E1_VPP
SSD_2L SSD_2L SSD_2L SSD_2L SSD_2L
1
CN135
2.2UF
20%
10V
2
X5R
0201
1
2
SSD_2L
CN123
2.2UF
20%
10V
X5R X5R
0201
1
CN136
2.2UF
20%
10V
2
X5R
0201
1
2
1
CN137
2.2UF
20%
10V
2
X5R
0201 0201
SSD_2L
CN124
2.2UF
20%
10V 10V
0201
SSD_2L
1
CN125
2.2UF
20%
2
X5R
0201
1
CN138
2.2UF
20%
10V
2
X5R
1
CN139
2.2UF
20%
10V
2
X5R
0201
SSD_2L
FLN101
10OHM-50%-1A-0.05OHM
2 1
0201
PLACE_NEAR=UN100.R4:10MM
1
CN183
4.7UF
20%
4V
2
CER-X5R
0201
SSD_2L
PP1V25_AWAKESW_VCCQ
SSD_2L
1
CN13A
2.2UF
20%
10V
2
X5R
0201
PP2V5_AWAKE_NAND
PP0V88_AWAKESW_NAND
PLACE_NEAR=FLN101.2:5MM
102 64
101 66 64
102 65
SSD_2L
1
CN185
10PF
5%
25V
2
C0G
0201
8
IN
8
IN
8
OUT
8
OUT
PCIE_NAND0_R2D_C_P<1>
PCIE_NAND0_R2D_C_N<1>
PCIE_NAND0_D2R_P<1>
PCIE_NAND0_D2R_N<1>
SSD_2L
1
RN104
2 0
0.1%
1/20W
TK
0201-1
2
SSD_2L
GND_VOID=TRUE
0.22UF
SSD_2L
GND_VOID=TRUE
0.22UF
SSD_2L
GND_VOID=TRUE
0.22UF
SSD_2L
GND_VOID=TRUE
0.22UF
67
8 67
8 67
IN
67
OUT
2 1CN103
6.3V
2 1CN104
10% 6.3V
2 1CN101
6.3V X5R-CERM
2 1CN102
10% 6.3V 0201
PLACE_NEAR=UN100.C10:15MM
1
RN106
3 0 300
1%
1/20W
MF
201
2
X5R-CERM
X5R-C RM
6 64 67
IN
64 67
IN
NAND0_CLK24M_1
PCIE_CLK100M_NAND0_1_P
N
PCIE_CLK100M_NAND0_1_N
NAND0_CLKREQ1_R_L
NAND0_S5E1_PCIE_RESREF
67
PCIE_NAND0_R2D_P<1>
0201 X5R-CERM 10%
PCIE_NAND0_R2D_N<1>
0201
PCIE_NAND0_D2R_C_P<1>
0201 10%
PCIE_NAND0_D2R_C N<1>
NAND0_RESET_L
NAND0_JTAG_TRST_L
NAND0_S5E1_ZQ_0
67
NAND0_S5E1_ZQ_1
67
PLACE_NEAR=UN100.K3:15MM
1
RN105
1%
1/20W
MF
201
2
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_ OID=TRUE
M3
K11
J12
P5
H7
M11
N12
R12
T11
L4
G10
C10
K3
CLK_IN
PCIE_REFCLK_P
PCIE_REFCLK_N
PCIE_ LKREQ*
PCIE_RESREF
PCIE_RX0_P
PCIE_RX0_N
PCIE_TX0_P
PCIE_TX0_N
RESET*
TRST*
ZQ_0
ZQ_1
OMIT_TABLE
UN100
S5E-MCP-STUDY
LGA
EXT_D0/BOOT0
EXT_D1/BOOT1
EXT_D2/BOOT2/SPINAND_SCLK
EXT_D3/SWD_UID0/SPINAND_MISO
EXT_D4/SPI_CS
EXT_D5/SWD_UID1/SPINAND_MOSI
EXT_D6/BOOT3
EXT_D7/SPF
EXT_DQS/BCM*
EXT_NCE/PERST*
EXT_NRE/JT G_TMS
EXT_NWE/JTAG_TCK
EXT_RNB/JTAG_TDO
EXT_CLE/JTAG_TDI
EXT_ALE/JTAG_SEL
DROOP*
WP*
B3
NAND0_LPB_L
C4
NAND_BFH
B5
NAND0_BOOT2
C6
NAND0_S5E1_SWD_UID0
B7
C8
NAND0_S5E1_SWD_UID1
B9
B11
NAND0_PFN_L
D11
NAND0_BCM_L
E8
NAND0_PCIE_RESET_L
D7
SWD_NAND0_SWDIO
E6
SWD_NAND0_SWCLK
E4
NAND0_S5E1_JTAG_TDO
D5
NAND0_S5E0_JTAG_TDO
D9
NAND0_JTAG_SEL
T3
TP_NAND0_S5E1_DROOP_L
G2
NAND0_WP_L
IN IN
64 67
65 67
65 67
IN
IN
IN
I
IN
OUT
IN
IN
IN
N
33 64 67
6 64 67
64 67
64
8 64 67
107
107
67
64 67
64 67
64 67
SSD_2L SSD_2L
PP1V25_AWAKESW_VCCQ
1
RN108
47K
1%
1/20W
MF
201
65 67
65 67
NAND0_S5E1_SWD_UID0
NAND0_S5E1_SWD_UID1
SSD_2L
1
RN109
47K
1%
/20W
MF
201
2
2
SSD_2L
102 65 64
SYNC_MASTER=REF_STORAGE_S5E SYNC_DATE=04/27/2020
PAGE TITLE
STORAGE: SSD0 S5E <1>
BOM_COST_GROUP=SSD
2
1 3
Page 66
***OK2INTEGRATE***
w w w . t e k n i s i - i n d o n e s i a . c o m
THIS EXTERNAL NAND VCC DISCHARGE CIRCUITRY IS FOR SYSTEM THAT DOES NOT USE OCARINA
101 65 64
PP2V5_AWAKE_NAND
PP2V5_NAND0_DISCHARGE
VOLTAGE=2.5
MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000
1
RN420
24.9
1%
1/10W
MF-LF
603
2
1
RN421
24.9
1%
1/10W
MF-LF
603
2
1
RN422
24.9
1%
1/10W
MF-LF
603
2
1
RN423
24 9
1%
1/10W
MF-LF
603
2
4
D
RN430
10K
33
IN
1
RN431
10K
5%
1/20W
MF
201
2
1
5%
1/20W
MF
201
P2V5_NAND0_DISCHARGE_EN_R P2V5_NAND0_DISCHARGE_EN
1
CN420
33000PF
10%
6.3V
2
X5R
201
G
1
S
3 2
376S00019
QN420
DMN2044UCB4
BGA
ALLOW_APPLE_PREFIX=Q
SYNC_MASTER=REF STORAGE_N N OCARINA_SUPPORT SYNC_DATE=02/25/2020
PAGE TITLE
STORAGE: NON OCARINA SUPPORT
2
1
A
Page 67
NAND0_CLK24M_0
w w w . t e k n i s i - i n d o n e s i a . c o m
64 67
PPP001
P4MM
SM
1
PP
NAND0_CLK24M_1
65 67
PCIE_CLK100M_NAND0_0_N
8 64
PCIE_CLK100M_NAND0_0_P
8 64
PCIE_CLK100M_NAND0_1_N
65
PCIE_CLK100M_NAND0_1_P
8 65
PPP002
P4MM
SM
1
PP
PPP003
P MM
SM
1
PP
PPP004
P4MM
SM
1
PP
PPP005
P4MM
SM
PP
PPP006
P4MM
SM
1
PP
SSD 24M CLOCK TERMINATIONS
RP000
15
1%
MF
201
15
1%
1/20W
MF
201
2 1
NAND0_CLK24M_0
OUT
64
NOSTUFF
1
RP005
47K
1%
1/20W
MF
201
2
2 1
NAND0_CLK24M_1
OUT
65 67
NOSTUFF
1
RP006
47K
1%
1/20W
MF
201
2
NAND0_CLK24M_0_R
1/20W
RP001
6
IN
NAND0_CLK24M_1_R
107
107
PP0V9_S5E0_VDD_PLL
IN
PP0V9_S5E1_VDD_PLL
IN
33 64 65
6 64 65
64 65
64
65
64
65
64 65 67
8 64 65
NAND0_LPB_L
IN
NAND_BFH
IN
NAND0_BOOT2
IN
NAND0_S5E0_SWD_UID0
IN
NAND0_S5E1_SWD_UID0
IN
NAND0_S5E0_SWD_UID1
IN
NAND0_S5E1_SWD_UID1
IN
NAND0_PFN_L
IN
NAND0_PCIE_RESET_L
IN
TOP TP-P5
TOP TP-P5
1
TOP
1
1
1
TOP
1
1
1
TOP
1
TPP001
TP
TPP002
TP
TPP003
TP
TPP004
TP
TPP005
TP
TPP006
TP
TPP007
TP
TPP008
TP
TPP009
TP
TPP010
TP
TPP011
TP
TP-P5
TP-P5TOP
TP-P5TOP
TP-P5
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5
TP-P5TOP
5 10
5 107
64 65
64
65
64 65
64 65
8 67
8 67
SWD_NAND0_SWDIO
IN
SWD_NAND0_SWCLK
IN
NAND0_S5E0_JTAG_TDO
IN
TP_NAND0_S5E0_JTAG_TDI
IN
NAND0_S5E1_JTAG_TDO
IN
NAND0_JTAG_SEL
IN
NAND0_WP_L
IN
NAND0_CLKREQ0_L
IN
NAND0_CLKREQ1_L
IN
1
TOP TP-P5
1
1
TOP TP-P5
1
1
1
1
TOP TP-P5
TPP012
TP
TPP013
TP
TPP014
TP
TPP015
TP
TPP016
TP
TPP017
TP
TPP018
TP
TPP019
TP
TPP020
TP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
8 67
TP-P5TOP
TP-P5TOP
IN OUT
NAND0_CLKREQ0_L
RP003
0
5%
1/20W
MF
0201
2 1
NAND0_CLKREQ0_R_L
64
SSD_2L
RP004
64
5
6 64 65
NAND0_S5E0_PCIE_RESREF
IN
NAND0_S5E1_PCIE_RESREF
IN
NAND0_RESET_L
IN
1
TOP TP-P5
1
TPP021
TP
TPP022
TP
TPP023
TP
TP-P5TO
TP-P5TOP
0
8 67
IN OUT
NAND0_CLKREQ1_L
1 20
0201
2 1
5%
MF
NAND0_CLKREQ1_R_L
65
65
64
64
65
64 65
64
64
65
65
NAND0_S5E1_ZQ_0
IN
NAND0_S5E0_ZQ_0
IN
NAND0_S5E0_ZQ_1
IN
NAND0_S5E1_ZQ_1
IN
NAND0_JTAG_TRST_L
IN
TP_NAND0_S5E0_ANI1_VREF
IN
TP_NAND0_S5E0_ANI0_VREF
IN
TP_NAND0_S5E1_ANI1_VREF
IN
TP_NAND0_S5E1_ANI0_VREF
IN
1
1
TOP TP-P5
1
TOP TP-P5
TO TP-P5
1
TOP TP-P5
1
1
1
TOP TP-P5
TOP TP-P5
TPP024
TP
TPP025
TP
TPP026
TP
TPP027
TP
TPP028
TP
TPP029
TP
TPP030
TP
TPP031
TP
TPP032
TP
TP-P5TOP
TP-P5TOP
TP-P5TOP
RP002
0
33 89 100 107
IN
PMU_SYS_ALIVE
1/20W
0201
2 1
5%
MF
NAND0_PFN_L
O T
64 65 67
PAGE TITLE
SYNC_DATE=01/28/2020 SYNC_MASTER=WUDI_T668_MLB
A
STORAGE: SSD SUPPORT
BOM_COST_GROUP=SSD
2
1
Page 68
*** OK2INTEGRATE ***
w w w . t e k n i s i - i n d o n e s i a . c o m
PP3V3_S2
104
HOST SIDE
CKPLUS_WAIVE=CLK_DATA_CON
7
OUT
7
OUT
7
OUT
7
OUT
42
BI
PPP100
42
BI
PPP101
74
IN
MIPI_FTCAM_DATA_N<0>
CKPLUS_WAI E CLK_DATA_CON
MIPI_FTCAM_DATA_P<0>
CKPLUS_WAIVE=CLK_DATA_CON
MIPI_FTCAM_CLK_N
CKPLUS_WAIVE=CLK_DATA_CON
MIPI_FTCAM_CLK_P
I2C_CAM_1V8_SDA
1
PP
SM-SP
I2C_CAM_1V8_SCL
1
PP
SM-SP
FTCAM_DISABLE_1V8_IC_L
CAMERA SECURE DISABLE
BYPASS=UP102::5MM
1
CP102
0.1UF
10%
6.3V
2
CERM-X5R
0201
CKPLUS_WAIVE=NDIFPR_BADTERM
CKPLUS_WAIVE=PDIFPR_BADTERM
CKPLUS_WAIVE=NDIFPR_BADTERM
CKP US W IVE=PDIFPR_BADTERM
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
11
NX3DV642GU
CLK+
1
CLK-
2
1D+
3
1D-
4
2D+
5
2D-
6
8
E*
S
VCC
CRITICAL
UP102
QFN-COMBO
CLK1+
CLK2+
CLK1-
CLK2-
1D1+
1D2+
1D1-
1D22D1+
2D2+
2D1-
2D2-
CONTROL
LOGIC
NC
NC
17
22
GND_VOID=TRUE
CKPLUS_WAIVE=NDIFPR_BADTERM
1
23
GND_VOID=TRUE
CKPLUS_WAIVE=PDIFPR_BADTERM
15
20
GND_VOID=TRUE
CKPLUS_WAIVE=NDIFPR_BADTERM
14
2
GN _VOID=TRUE
CKPLUS_WAIVE=PDIFPR_BADTERM
13
19
12
18
7
24
CKPLUS_WAIVE=CLK_DATA_CON
MIPI_FTCAM_DATA_ISOL_N
CKPLUS_WAIVE=CLK_DATA_CON
MIPI_FTCAM_DATA_ISOL_P
CKPLUS_WAIVE=CLK_DATA_CON
MIPI_FTCAM_CLK_ISOL_N
CKPLUS_WAIVE=CLK_DATA_CON
MIPI_FTCAM_C K SOL_P
I2C_FTCAM_DSBL_SDA
I2C_FTCAM_ISOL_SDA
I2C_FTCAM_DSBL_SCL
I2C_FTCAM_ISOL_SCL
NC
NC
69 89
IN
69 89
IN
69 89
IN
69 89
IN
PP1V8_S2
1
RP105
100K
5%
1/20W
MF
201
2
I2C PULL VALUES TO BE DETERMINED FROM CHARACTERIZATION
1
RP107
100K
5%
1/20W
MF
201
2
1
RP106
100K
5%
1/20W
MF
201
2
1
RP108
100K
5%
1/20W
MF
201
2
BI
BI
101
69 89
69 89
VALUE STATE
L CAMERA DISABLE
H CAMERA ENABLE
GND
BOM_COST_GROUP=CAMERA
PAGE TITLE
2
SECDIS: MIPI MUX
1
Page 69
107S00020
w w w . t e k n i s i - i n d o n e s i a . c o m
NO_XNET_CONNECTION=1
RP620
0.01
1%
1/3W
MF
0306
41 89 104
ISNS_PPPANEL_SW_LCD_P
47 48
ISNS_PPPANEL_SW_LCD_N
47 48
CP620
7
BI
7
BI
LPDP_INT_AUX_C_N
LPDP_INT_AUX_C_P
CP621
0.1UF
2 1
2 1
2 1
4 3
X5R-CERM
X5R-CERM
PP3V3_SW_LCD_CONN PP3V3_SW_LCD
VOLTAGE=3.3V
PPVOUT_LCDBKLT
104
1
0201 16V 10%
0201 16V 10%0.1UF
1
RP612
1M
5%
1/20W
MF
201
2
1
RP613
1M
5%
1/20W
MF
201
2
CP600
1000PF
10%
100V
2
X7R-CERM
0603
JP600
20759-042E-02
F-ST-SM
JP600_PIN_18
69
JP600_PIN_2
69
JP600_PIN_8
69
JP600_PIN_10
69
JP600_PIN_12
69
JP600_PIN_14
69
DISPLAY:P0
DISPLAY:P1
DISPLAY:P0
DISPLAY:P1
DISPLAY:P0
DISPLAY:P1
DISPLAY:P0
DISPLAY:P1
RP640
RP641
RP642
RP643
RP644
RP645
RP646
RP647
0
0
0
0
0
0
0
0
1/20W 5%
MF
2 1
1/20W 5%
MF
2 1
1/20W 5%
MF
2 1
5% 1/20W
MF 0201
2 1
5% 1/20W
MF 0201
2 1
5% 1/20W
MF 0201
2 1
5% 1/20W
MF 0201
2 1
1/20W 5%
MF
2 1
0201
0201
0201
0201
UART_TCON_HDMI_D2R
SPI_TCON_CS_L
SPI_TCON_MISO
SPI_TCON_MOSI
89
RP601
OUT
IN
OUT
6 89
6 89
6 89
33
5% MF
2 1
201 1/20W
SPI_TCON_MOSI_R
IN
6
PWR
GND_VOID=TRUE
7
7
7
7
7
7
7
7
LPDP_INT_DATA_C_N<0>
IN
LPDP_INT_DATA_C_P<0>
IN
LPDP_INT_DATA_C_N<1>
IN
LPDP_INT_DATA_C_P<1>
I
LPDP_INT_DATA_C_N<2>
IN
LPDP_INT_DATA_C_P<2>
IN
LPDP_INT_DATA_C_N<3>
IN
LPDP_INT_DATA_C_P<3>
IN
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
CP612
CP613
CP614
CP615
CP616
CP617
CP618
CP619
2 1
10%
2 1
2 1
2 1
2 1
2 1
2 1
2 1
X5R-CERM 16V0.1UF
X5R-CERM 16V 10%0.1UF
X5R-CERM 16V 10%0.1UF
X5R-CERM
16V
0201 X5R-CERM 16V 10%0.1UF
0201
0201 X5R-CERM 16V 10%0.1UF
0201 X5R-CERM 16V 10%0.1UF
0201
0201
0201 16V 10%0.1UF
0201 X5R-CERM 10%0.1UF
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
AUX_N
89
AUX_P
89
89
DP0_N
9
DP0_P
89
DP1_N
89
DP1_P
89
DP2_N
89
DP2_P
89
DP3_N
89
DP3_P
SIGNAL
MIPI_DATA_CONN_N
MIPI_DATA_CONN_P
3.25-OHM-0.1A-2.4GHZ
68
OUT
68 89
OUT
MIPI_FTCAM_DATA_ISOL_N
MIPI_FTCAM_DATA_ISOL_P
3.25-OHM-0.1A-2.4GHZ
68 9
OUT
8 89
OUT
MIPI_FTCAM CLK_ISOL_N
MIPI_FTCAM_CLK_ISOL_P
LP602
TAM0605-4SM
SYM_VER-1
1
LP603
TAM0605-4SM
SYM_VER-1
1
4
3 2
4
3 2
MIPI_CLOCK_CONN_N
MIPI_CLOCK_CONN_P
PWR
GND
107S00116
NO_XNET_CON ECTION=1
RP621
0.1
1%
0.5W
MF
89 104
PP5V_SW_LCD
0306
2 1
4 3
PP5V_SW_LCD_CONN
VOLTAGE=5V
44 43
2 1
JP600_PIN_2
4 3
EDP_PANEL_1V8_EN
6 5
LPDP_INT_HPD
8 7
JP600_PIN_8
10 9
JP600_PIN_10
12 11
JP600_PIN_12
14 13
JP600_PIN_14
16 15
JP600_PIN_16
18 17
JP600_PIN_18
20 19
JP600_PIN_20
22 21
JP600_PIN_22
24 23
I2C_BKLT_SDA
26 25
I2C_BKLT_SCL
28 27
JP600_PIN_28
30 29
JP600_PIN_30
32 31
JP600_PIN_32
34 33
JP600_PIN_34
36 35
JP600_PIN_36
38 37
JP600_PIN_38
40 39
JP600_PIN_40
42 41
JP600_PIN_42
VOLTAGE=5V
46 45
48 47
50 49
52 51
54 53
56 55
58 57
60 59
62 61
64 63
66 65
68 67
PP5V_CAM
89
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
DISPLAY:P0
69
70 89
IN
7 89
OUT
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
1
RP611
47K
5%
1/20W
MF
201
2
LP610
BI
IN
71 89
71 89
FERR 120-OHM-1.5A
2 1
0402A
1
CP610
0.1UF
10%
16V
2
X5R-CERM
0201
JP600_PIN_16
69
JP600_PIN_34
69
JP600_PIN_30
69
JP600_PIN_36
69
JP600_PIN_32
69
JP600_PIN_38
69
JP600_PIN_34
69
JP600_PIN_40
69
JP600_PIN_36
69
DISPLAY:P1
DISPLAY:P0
DISPLAY:P1
DISPLAY:P0
DISPLAY:P1
DISPLAY:P0
DISPLAY:P1
DISPLAY:P0
DISPLAY:P1
DISPLAY:P0
JP600_PIN_20
69
JP600_PIN_22
69
JP600_PIN_28
69
JP600_PIN_30
69
DISPLAY:P1
DISPLAY:P1
DISPLAY:P0
DISPLAY:P0
RP648
RP649
1
RP614
100K
1%
1/20W
MF
201
2
RP650
RP651
RP652
RP653
RP654
RP655
RP656
RP657
RP664
RP660
RP661
RP662
RP663
DISPLAY:P0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5% 1/20W
MF 0201
2 1
5% 1/20W
MF 0201
2 1
5%
1/20W
MF
2 1
1/20W 5%
MF
2 1
1/20W 5%
MF
2 1
5% 1/20W
MF 0201
2 1
5% 1/20W
MF 0201
2 1
5% 1/20W
MF 0201
2 1
5% 1/20W
MF 0201
2 1
1/20W 5%
MF
2 1
5% 1/20W
MF 0201
2 1
5% 1/20W
MF 0201
2 1
5% 1/20W
MF 0201
2 1
5% 1/20W
MF 0201
2 1
1/20W 5%
MF
2 1
0201
0201
0201
0201
SPI_TCON_CLK
89
RP602
I2C_ALS_1V8_SDA
I2C_ALS_1V8_SCL
I2C_FTCAM_ISOL_SCL
I2C_FTCAM_ISOL_SDA
UART_TCON_HDMI_R2D
I2C_MLB2JERRY_3V3_SDA
I2C_MLB2JERRY_3V3_SCL
TP_TCON_SWCLK
TP_TCON_SWDIO
1/20W
5%
2 1
201
41 89
MF
SPI_TCON_CLK_R
IN
6
33
42 89
BI
42 89
IN
68 89
IN
68 89
BI
6 89
IN
BI
41 89
IN
89
89
ISNS_PP5V_SW_LCD_P
47 48
ISNS_PP5V_SW_LCD_N
47 48
105
PP5V_S2_ALSCAM_ISNS
JP600_PIN_2
69
JP600_PIN_22
69
JP600_PIN_32
69
JP600_PIN_42
6
JP600_PIN_8
69
JP600_PIN_18
69
JP600_PIN_28
69
JP600_PIN_38
69
DISPLAY:P0
DISPLAY:P0
DISPLAY:P0
DISPLAY:P0
DISPLAY:P1
DISPLAY:P1
DISPLAY:P1
DISPLAY:P1
RP670
RP671
RP672
RP673
RP674
RP675
RP676
RP677
0
0
0
0
0
0
0
0
5% 1/20W
MF
2 1
5% 1/20W
MF 0201
2 1
5% 1/20W
MF
2 1
1/20W 5%
MF
2 1
5% 1/20W
MF 0201
2 1
5% 1/20W
MF 0201
2 1
5% 1/20W
MF 0201
2 1
1/20W 5%
MF
2 1
0201
0201
SYNC_DATE=10/02/2019 SYNC_MASTER=AITKEN_T6 8_MLB
PAGE TITLE
DISPLAY: CONNECTOR, PWR
BOM_COST_GROUP=DISPLAY
Page 70
*** OK2INTEGRATE ***
w w w . t e k n i s i - i n d o n e s i a . c o m
PP5V_S2
104
LCD_PWR_SLEW
CRITICAL
UP700
SLG5AP1443V
CAP
VDD
TDFN
1
CP717
0.1UF
10%
10V
2
X5R-CERM
0201
3 7
D
CP709
2200PF
10%
10V
X7R-CERM
0201
ON S
1
GND
2
5 2
1
CP711
0.1UF
10%
10V
2
X5R-CERM
0201
1
CP712
10UF
20%
10V
2
X5R-CERM
0402-7
PP5V_SW_LCD
104
CONSULT YOUR DISPLAY DRI FOR DETAILS
GENERAL GUIDELINE IS
3V3 FOR 2020 SYSTEMS
3V8 FOR 2021 SYSTEMS
PP3V3_S2
104
PP1V8_S2
101
BYPASS=UP710.1::3.5MM
1
CP770
0.1UF
10%
10V
2
X5R-CERM
0201
CRITICAL
VDD
UP701
SLG5AP1564V
STDFN
2 3
ON
GND
PG
1
CP710
1.0UF
20% 6.3V
2
X5R
0201-1
B
D
5
S
7
NC
1
CP718
0.1UF
10%
10V
2
X5R-CERM
0201
1
CP719
10UF
20%
10V
2
X5R-CERM
0402-7
PP3V3_SW_LCD
104
UP710
SLG4AP43605V
STQFN
34 94
IN OUT
107
IN
LCD_PWR_EN EDP_PANEL_1V8_EN
PMU_SYS_ALIVE
NC
NC
NC
NC
NC
PANEL_EN_IN
3
SYS_ALIVE
5
NC
6
NC
7
NC
8
NC
12
NC
PANEL_EN_OUT
PANEL_PWR_EN
BLC_VDDIO_EN
BLC_5V_EN
PANEL_DISCHARGE
11 2
4
13
14
10
EDP_PANEL_PWR_EN
NC
EDP_BLC_5V_EN
EDP_PANEL_DISCHARGE
69 89
1
RP701
100K
5%
1/20W
MF
201
2
1
RP700
300
5%
1/16W
MF-LF
402
2
PPPANEL_PANEL_DISCHARGE
3
D
376S1140
MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000
VOLTAGE=4V
QP700
G
1
S
2
DMN2300UFB4
X2-DFN1006-3-COMBO
SYM_VER_1
C TE CM TE E P NE W N
PAGE TITLE
DISPLAY POWER SEQUENCER
BOM_COST_GROUP=DISPLAY
2
1
Page 71
*** OK2INTEGRATE ***
w w w . t e k n i s i - i n d o n e s i a . c o m
BEN IC: DISPLAY/KBD BACKLIGHT BOOST CONVERTER
PPBUS_AON
101
PP5V_S2
104
45 48
OUT
45 48
OUT
33 94
IN
ISNS_LCDBKLT_N
ISNS_LCDBKLT_P
BL_PWR_EN
UP800.17 VIH_MIN 1.2V
VIL_MAX 0.4V
740S0159
CRITICAL
FP800
3AMP-32V
0603-COMBO
VOLTAGE=13
MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000
2 1
PPVIN_LCDBKLT_F
RP842
0
2 1
5%
1/20W
MF
0201
107S00034
RP800
0.025
1%
1W
MF
0612-
2 1
4 3
1
RP801
80.6K
1%
1/16W
MF-LF
402
2
1
RP802
63.4K
1%
1/16W
MF-LF
402
2
OMIT_TABLE
RP844
OMIT_TABLE
PLACE_NEAR=UP800.5:5MM
CP840
1UF
402-1
VOLTAGE=13
MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000
PPVIN_LCDBKLT_R
1
CP800
1000PF
10%
16V
2
X7R-1
0201
LCDBKLT_EN_L
1
0
5%
1/16W
MF-LF
402
2
VOLTAGE=5
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
PP5V_BKLT_D
1
10%
10V
2
X5R
ALLOW_APPLE_PREFIX=Q
376S0604
CRITICAL
QP800
FDC638APZ_SBMS001
SSOT6-HF
4
3
CKPLUS_WAIVE=LIFECYCLE_STATUS
OMIT_TABLE
1
RP845
0
5%
1/16W
MF-LF
402
2
OMIT_TABLE
PLACE_NEAR=UP800.18:5MM
10%
10V
X5R
1
2
CP841
1UF
402-1
UP TO 22V ALLOWED ON UP800.11
WITH VDDD,VDDA AT 0V
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.2500
BKLT_SD
BKLT_SENSE_OUT
BKLT_EN_R
BKLT_SCL
BKLT_SDA
6
5
2
1
1
2
VOLTAGE=5
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
PP5V_BKLT_A
UP800
CRITICAL
LP8548B1SQ_-04
11
9
10
19
17
12
15
16
OMIT_TABLE
SD
VSENSE_N
VSENSE_P
SENSE_OUT
EN
PWM_KEYB
(5K IPU VDDD)
SCL
(5K IPU VDDD)
SDA
NOSTUFF
CP801
0.001UF
10%
50V
CERM
402
SYMBOL: 353S4160
LLP
ISET_KEYB
KEYB1
KEYB2
SW
SW
FB
GD
SW2
FB2
VOLTAGE=13
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
PPVIN_LCDBKLT_Q
PLACE_NEAR=LP 00.1:5MM
1
CP810
4.7UF
10%
25V
2
X6S-CERM
0603
376S0678
CRITICAL
QP801
SI7812DN
PWRPK-1212-8
VOLTAGE=55
DIDT=TRUE
SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=2.0000
2
1
21
4
20
13
14
6
8
LCDBKLT_SW
LCDBKLT_FB
LCDBKLT_FET_DRV
BKLT_ISET_KEYB
BKLT_KEYB1
BKLT_KEYB2
KBDBKLT_SW2
VOUT_KEYBDLED_FB2
PLACE_NEAR=LP800.1:5MM
1
CP811
4.7UF
10%
25V
2
X6S-CERM
0603
5
3 2 1
PLACE_NEAR=UP800.1:4MM
152S00253
PLACE_NEAR=QP801.5:3MM
CRITICAL
LP800
15UH-20%-1.9A-0.24OHM
2 1
PIME062D-SM
PLACE_NEAR=LP800.1:5MM
1
CP812
0.1UF
10%
25V
2
X5R
402
VOLTAGE=5
MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000
GATE_NODE=TRUE
DIDT=TRUE
4
LCDBKLT_FET_DRV_R
VOLTAGE=5
GATE_NODE=TRUE
MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000
72
BI
72
IN
72
IN
72
BI
72
IN
DIDT=TRUE
IF KEYBOARD BACKLIGHT NOT USED,
ALIAS TO NC
VOLTAGE=55
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
SWITCH_NODE=TRUE
DIDT=TRUE
PPVOUT_LCDBKLT_SW
OMIT_TABLE
PLACE_NEAR=LP800:5MM
1
RP833
10
1%
1/16W
MF-LF
402
2
5%
100V
C0G
0201
1
2
CP876
12PF
LCDBKLT_FB_XWR
OMIT_TABLE
NO_XNET_CONNECTION=1
1
RP831
1%
1/16W
MF-LF
402
2
1
RP832
150K
1%
1/16W
MF-LF
402
2
CRITICAL
DFLS2100
PLACE_NEAR=LP800.2:4.7MM
371S00180
DP800
POWERDI123-COMBO
K A
NO_XNET_CONNECTION=1
PLACE_NEAR=DP800:4MM
XWP801
NOSTUFF
1
CP830
100PF
5%
100V
2
C0G-CERM
0603
SM
PPVOUT_LCDBKLT
PLACE_NEAR=DP800.K:5MM
1
CP860
2.2UF
10%
100V
2
X5R
2
1
1206
PLACE_NEAR=DP800.K:5MM
1
CP864
2 2UF
10%
100V
2
X5R
1206
PLACE_NEAR=DP800.K:10MM
1
CP868
2.2UF
10% 10%
100V
2
X5R
1206
PLACE_NEAR=DP800.K:6MM PLACE_NEAR=DP800.K:8MM
1
CP872
2.2UF
10%
100V
2
X5R
1206
PLACE_NEAR=DP800.K:6MM PLACE_NEAR=DP800.K:5MM PLACE_NEAR=DP800.K:5MM
1
CP861
2.2UF
10%
100V
2
X5R
1206
PLACE_NEAR=DP800.K:5MM
1
CP865
2.2UF
10%
100V
2
X5R
1206
PLACE_NEAR=DP800.K:8MM
1
CP869
2.2UF
100V
2
X5R
1206
1
CP873
2.2UF
10%
100V
2
X5R
1206
1
CP862
2.2UF
10%
100V
2
X5R
1206
PLACE_NEAR=DP800.K:5MM
1
CP866
2.2UF
10%
100V
2
X5R
1206
PLACE_NEAR=DP800.K:6.5MM
1
CP870
2.2UF
10%
100V
2
X5R
1206
1
CP863
2.2UF
10%
100V
2
X5R
1206
PLACE_NEAR=DP800.K:5.5MM
1
CP867
2.2UF
10%
100V
2
X5R
1206
PLACE_NEAR=DP800.K:10MM
1
CP871
2.2UF
10%
100V
2
X5R
1206
104
TO JERRY ONLY
69 89
IN
9 89
BI
I2C_BKLT_SCL
I2C_BKLT_SDA
UP800.15 VIH_MIN 1.7V
VIL_MAX 0.4V
UP800.16 VIH_MIN 1.7V
VIL_MAX 0.4V
R_ON(TYP) 11.65 OHMS
R_ON(MAX) 12.85 OHMS
1
RP852
1.8K
5%
1/20W
MF
201
2
1
RP853
1.8K
5%
1/20W
MF
201
2
PLACE_NEAR=UP800.15:10MM
RP850
0
2 1
1/20W
5% MF 0201
RP851
0
2 1
5%
1/20W
MF
PLACE_NEAR=UP800.16:10MM
0201
NOSTUFF
RP840
1/20W
5%
25V
0201
1
2
CP842
33PF
NPO-C0G
CKPLUS_WAIVE=LIFECYCLE_STATUS
1M
5%
MF
201
1
2
OMIT_TABLE
RP847
10K
5%
1/20W
MF
201
1
2
XWP800
SM
THRM
PAD
2 1
BKLT_PWM_KEYB_3V3
GND_BKLT_SGND
MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.1000
VOLTAGE=0
UP800.12 VIH_MIN 1.7V
VIL_MAX 0.4V
IN
IF KEYBOARD BACKLIGHT USED,
CONNECT TO CSA 239
72
72 89
BEN IC VERSION TO MATCH VERSION OF JERRY IC IS ON THE PANEL
REFERENCE DESIGNATOR(S) QTY DESCRIPTION PART# BOM OPTION CRITICAL
353S4160
353S02256
BACKLIGHT SWITCH NODE DESENSE OPTION
131S00141
10K IF KEYBOARD PWM INPUT IS NOT PRESENT (J132, J213)
100K IF KEYBOARD PWM INPUT IS PRESENT (J152)
117S0007 BLC_KBD_BOOST_USED:NO RP847 1
118S0014 1 BLC_KBD_BOOST_USED:YESRES,MF,100KOHM,1,1/20W,0201 RP847
IC,LP8548B1-04,DC/DC CVTR,BOOST,QFN-24
1
CAP,C0G,12PF,5%,100V,0201
RES,MF,1/20W,10K OHM,5,0201,SMD
UP800 1
REFERENCE DESIGNATOR(S) QTY DESCRIPTION PART#
CP876 BLC_SW_NODE_DESENSE
REFERENCE DESIGNATOR(S) QTY DESCRIPTION PART#
BACKLIGHT BOOST VOLTAGE LEVEL BASED ON NUMBER OF LEDS PER STRING
TA LE_5_ TEM
BLC_BEN_IC:V4 UP800 1
TA LE_5_ TEM TA LE_5_ TEM
BLC_BEN_IC:V7 BLC_LEDS_PER_STRING:16
TA LE_5_ EAD
BOM OPTION CRITICAL
TA LE_5_ TEM
TA LE_5_ EAD
BOM OPTION CRITICAL
TA LE_5_ TEM
TA LE_5_ TEM
BOM OPTION FOR BLC 5V RC FILTER, BASED ON PER PROJECT 5V RIPPLE CHARACTERIZATION.
AS COMPARED TO BLC TEAM'S 50 MV RIPPLE SPEC FOR VDDD & VDDA, SEE <RDAR://50682542>
138S0614 2 CP840,CP841 BLC_5V_CAP:1_UFCAP,CER,X5R,1UF,10%,10V,0402
RES,MTL FILM,1/16W,18.2K,1,0402,SM,LF114S0339 RP831 1
RES,MTL FILM,1/16W,28.7K,1,0402,SM,LF114S0359 BLC_LEDS_PER_STRING:18 RP831 1
2 116S0004 RES,MTL FILM,0 OHM,1A MAX,0402,SMD RP844,RP845 BLC_5V_SERIES:0_OHM
CAP,CER,X5R,4.7UF,20%,25V,0402 BLC_5V_CAP:4P7_UF 138S00070 2 CP840,CP841
REFERENCE DESIGNATOR(S) QTY DESCRIPTION PART#
REFERENCE DESIGNATOR(S) QTY DESCRIPTION PART#
BOM OPTION CRITICAL
BOM OPTION CRITICAL
BLC_5V_SERIES:10_OHM 114S0023 RP844,RP845 2 RES,MTL FILM,1/16W,10 OHM,1,0402,SMD,LF
TA LE_5_ EAD
TA LE_5_ TEM
TA LE_5_ EAD
TA LE_5_ TEM
T
A LE_5_ TEM
TA LE_5_ TEM
BOM_COST_GROUP=DISPLAY
PAGE TITLE
2
SYNC_DATE=11/21/2019 SYNC_MASTER=REF_BLC_BENIC,LP8548B1A-07,DC/DC BOOST CVTR,QFN24
BEN: CONTROLLER
1 6 8
Page 72
*** OK2INTEGRATE ***
w w w . t e k n i s i - i n d o n e s i a . c o m
105
PP5V_S2_KBDLED_ISNS
1
CP940
2.2UF
10%
25V
2
X5R-CERM
603
1
CP941
2.2UF
10%
25V
X5R-CERM
603
1
CP942
0.1UF
10%
16V
2
X5R CE M
0201
BEN IC: KEYBOARD LED DRIVER
THIS PAGE IS ONLY TO BE INCLUDED IF THE KEYBOARD BACKLIGHT
IS CONTROLLED BY THE BEN ON PAGE 238
DP900
LP900
10UH-20%-1.4A-0.17OHM
2 1
PST041H-SM
OMIT_TABLE
PLACE_NEAR=LP900:5MM
1
CP976
12PF
5%
100V
2
C0G
0201
PLACE_NEAR=LP900.2:10MM
PMEG6010ER/S500
SOD123W
K A
PPVOUT_KBDLED
PLACE_NEAR=DP900:5MM PLACE_NEAR=DP900:5MM PLACE_NEAR=DP900:5MM PLACE_NEAR=DP900:5MM
1
CP950
2.2UF
10%
50V
2
X5R
0603
1
CP951
2.2UF
10%
50V
2
X5R
0603
1
CP952
2.2UF
10%
50V
2
X5R
0603
1
CP953
2.2UF
10%
50V
2
X5R
0603
104
KEYBOARD BACKLIGHT
POWER & CONTROL
SIGNALS FROM
SYSTEM
71
BI
71
BI
KBDBKLT_SW2
MIN_LINE_WIDTH=0.5000
MIN_NECK_WIDTH=0.2500
DIDT=TRUE
SWITCH_NODE=TRUE
VOLTAG =42V
VOUT_KEYBDLED_FB2
MIN_LINE_WIDTH=0.5000
MIN_NECK_WIDTH=0.2000
VOLTAGE=40V
XWP900
SM
2 1
PLACE_NEAR=CP950.1:10MM
PLACE_NEAR=DP900:5MM PLACE_NEAR=DP900:5MM PLACE_NEAR=DP900:5MM PL CE_NEAR=DP900:5MM
1
CP954
2.2UF
10%
50V
2
X5R
0603
PLACE_NEAR=DP900:5MM
1
CP958
0.001UF
10%
50V
2
X7R-CERM
0402
1
CP955
2.2UF
10%
50V
2
X5R
0603
1
CP956
2.2UF
10% 10%
50V
2
X5R
0603
1
CP957
2.2UF
50V
2
X5R
0603
KEYBOARD BACKLIGHT
CONNECTOR SIGNALS
KEYBOARD BKLT PWM LEVEL-SHIFTER
UP900.4: VOH_MIN = 2.3V
VOL_MAX = 0.1V @ PWM_KEYB I_MAX OF 1UA
104
102
5
IN OUT
PP3V3_S2
PP1V25_S2
KBD_BKLT_PWM
UP900.3:
VIH MIN = VCCA X 0.65 = 0.78V
RP901
0
5%
1/20W
MF
0201
PLACE_NEAR=UP900.6:5MMPLACE_NEAR=UP900.1:5MM
10%
16V
0201
1
2
CP900
0.1UF
X5R-CERM X5R-CERM
2 1
SOC_KBD_BKLT_PWM_RES
1
RP900
47K
5%
1/20W
MF
201
2
CP901
0.1UF
10%
16V
0201
311S00243
1
UP900
SN74AXC1T45
2
VCCA VCCB
5
DIR
A
GND
SOT-5X3
4 3
B
BKLT_PWM_KEYB_3V3
1 RP903
31.6K
1%
1/20W
MF
201
2
BKLT_ISET_KEYB
MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.0800
GND_BKLT_SGND
RP910
10
1%
2 1
MF-LF 402
KBDLED_CATHODE1
81 89
IN OUT
71
BKLT_KEYB1
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
1/16W
RP911
10
1%
2 1
402 MF-LF
KBDLED_CATHODE2
IN
81 89
71
OUT
BI
BKLT_KEYB2
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
71
71
71 89
1/16W
KEYBOARD SWITCH NODE DESENSE OPTION
CAP,C0G,12PF,5%,100V,0201131S00141
OFF=PAGE SIGNALS ON THIS VERTICAL LINE CONNECT TO BEN UP800
ON PAGE 238
SYNC_DATE=11/21/2019 SYNC_MASTER=REF_BLC_BEN
PAGE TITLE
BEN: KEYBOARD
TA LE_5_ EAD
REFERENCE DESIGNATOR(S) QTY DESCRIPTION PART#
CP976 BLC_KBD_SW_NODE_DESENSE 1
BOM OPTION CRITICAL
TA LE_5_ TEM
BOM_COST_GROUP=DISPLAY
7 8
Page 73
*** OK2INTEGRATE ***
w w w . t e k n i s i - i n d o n e s i a . c o m
PACK_OPTION=AMR_INTERPOSER_LEFT
998-19652
JR200
INTERPOSER-AMR-MLB
PACK_OPTION=AMR_INTERPOSER_RIGHT
SMT-PAD
8
7
6
5 4
1
2
3
OMIT_TABLE
ALLOW_APPLE_PREFIX=
PACK_IGNORE=TRUE
998-19652
PP1V8_AON
JR201
INTERPOSER-AM -MLB
SMT-PAD
8
7
6
5
1
2
3
4
PP1V8_AON
Lid Detect Sensors
104 89 73
Clamshell Open = High
Clamshell Closed = Low
104 89 73
0 89 73
RR200
PACK_IGNORE=TRUE
PACK_OPTION=NO_AMR_INTERPOSER_LEFT
PACK_OPTION=NO_AMR_INTERPOSER_RIGHT
PP1V8_AON
1
1M
5%
1/20W
MF
201
2
1
RR201
1M
5%
1/20W
MF
201
2
BYPASS=UR200::5MM
CR200
0.1UF
CERM-X5R
10%
6.3V
0201
AMR_LEFT_OR_ND_1V8
1
UR2002
6
2
1
NC
5 3
74LVC1G32
SOT891
RR203
1K
5%
1/20W
MF
2 1
2 1
IPD_LID_OPEN_1V8 IPD_LID_OPEN_R_1V8
OUT
OUT
74 89
33 85 87 89
NC
RR202
100K
5%
1/20W
MF
201
OMIT_TABLE
ALLOW_APPLE_PREFIX=J
MGL_1V8
1
2
OUT
AMR_RIGHT_OR_ND_1V8
74
OUT
74 80 89
PAGE TITLE
SECDIS: AMR
BOM_COST_GROUP=SOC
Page 74
*** OK2INTEGRATE ***
w w w . t e k n i s i - i n d o n e s i a . c o m
CURRENT PER RAIL
RAIL TYPICAL PEAK
1.2 S2 0.8MA 33MA
1.8 S2 0.8MA 14MA
UNLESS 1V8 IS NOTED, SIGNALS ARE 1.2V
101 74
102 74
PP1V8_S2
PP1V2_S2
101 74
PP1V8_S2
ROOM=SECURE_DISABLE
BYPASS=UR301.1::5MM
1
CR306
0.1UF
10%
6.3V
2
CERM-X5R
0201
NC
NC
NC
NC
NC
UR301
SLG4AP44010
2
3
4
NC
6
8
STQFN
CLK_2MHZ
7
CLK_2MHZ_SECDIS_1V8_R
ROOM=SECURE_DISABLE
RR314
10
2 1
MF 1/20W
201
5%
107
107
107
PLACE_NEAR=UR301.7:15MM
SUPER IMPORTANT PACK OPTIONS:
ROOM=SECURE_DISABLE
NOTES ARE ON CSA 2 OF THE REFERENCE DESIGN
READ, LEARN, IMPLEMENT
6
IN
IN
FTCAM_DISABLE_L
NC_IRCAM ENABLE_IN_IC
MAKE_BASE=TRUE
PACK_OPTION=PROD_SECDIS
FTCAM_DISABLE_L
NC
6
IN
OUT
5 9 33 89 90 100
IN
9
OUT
9
OUT
IN
DMIC_DISABLE_L
NC_DMIC_DATA2_SEC_OUT_IC
PMU_RESET_L
PD _DMIC_DATA4
PDM_DMIC_DATA3
NC_SEP_IRCAM_DISABLE_IC_L
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PACK_OPTION=PROD_SECDIS
PACK_OPTION=PROD_SECDIS
PACK_OPTION=PROD_SECDIS
RR313
1K
9
OUT
6
IN
LID_OPEN
MAKE_BASE=TRUE
DISABLE_STROBE
MAKE_BASE=TRUE
LID_OPEN
PACK_OPTION=PROD_SECDIS
1/20W
PACK_OPTION=PROD_SECDIS
2 1
5%
201 MF
DMIC_DISABLE_L
NC_FTCAM_ENABLE_IN
107
PDM_DMIC_DATA4
PDM_DMIC_DATA3
SMC_LID_OPEN_R
74
SECDIS_SN_TIE_OFF
DISABLE_STROBE
PDM_DMIC_CLK4
CKPLUS WAIVE=CLK DATA CON
CKPLUS WAIVE=CLK DATA CON
NC
NC
CKPLUS WAIVE=SYNONYM CHECK
DMIC_CLK0_1V8_OUT_R
CKPLUS_WAIVE=TERMSHORTED
PACK_IGNORE=TRUE
PACK_OPTION=DEV_SECDIS
PDM_DMIC_CLK3
CKPLUS WAIVE=SYNONYM CHECK
E7
PB3A
F7
PB3B
G7
PB5A/CSSPIN
F6
PB8A/MCLK/CCLK
F5
PB8B/SO/SPISO
E4
PB11A/PCLKT2_0
E3
PB11B/PCLKC2_0
G4
PB16A/PCLKT2_1
G3
PB16B/PCLKC2_1
F4
PB12A
F3
PB12B
G2
PB25A/SN
G1
PB25B/SI_SISPI
A7
PL2A/L_GPLLT_IN
B6
PL2B/L_GPLLC_IN
C7
PL3A/PCLKT5_0
C6
PL3B/PCLKC5_0
E6
PL5A
E5
PL5B
LCMXO2-2000ZE-1UWAP9
(IPD)*
(IPD)
(IPD)
ROOM=SECURE_DISABLE
1
RR300
0
9
IN
PDM_DMIC_CLK4
MAKE_BASE=TRUE
PACK_OPTION=PROD_SECDIS
PDM_DMIC_CLK4
1 2
5%
1/20W MF
0201
RR310
47K
1%
1/20W
MF
201
2
1
RR311
47K
1%
1/20W
MF
201
2
1
RR312
47K
1%
1/20W
MF PACK_OPTION=PROD_SECDIS_3DMIC
201
2
UR300
WLCSP
OMIT_TABLE
(IPD)*
(IPD)
(IPD)
(IPD)*
(IPD)*
GND
PT17A/PCLKT0_1
PT17B/PCLKC0_1
PT18C/SCL/PCLKT0_0
PT18D/SDA/PCLKC0_0
PT20D/PROGRAMN
PINS MARKED (IPD)* ONLY HAVE
INTERNAL PULLDOWNS IN THE
SECDIS_EVT VERSION OF THE PART
PT10A
PT10B
PT12C/TDO
PT12D/TDI
PT16C/TCK
PT16D/TMS
PT20A
PT20B
PT20C/JTAGENB
PT23A
PT23B
PT24A
(IPD)
PT24C/INITN
PT24D/DONE
PT24B
D5
D4
A6
C5
B4
B5
C4
D3
B3
C3
A3
B2
F2
F1
E2
C2
C1
D2
B1
A1
NC
CLK_2MHZ_SECDIS_1V8
NC_DMIC_CLK2_1V8_OUT_R_IC
DMIC_CLK_ENABLE
NC
NC
MGL_1V8
SECDIS_TDO_IC
SECDIS_TDI
SECDIS_TCK
SECDIS_TMS
74
74
74
74
JTAG SIGNALS ARE 1.8V
INPUTS ARE HARD-TIED TO RAILS IN POR DESIGNS
THE OUTPUT (TDO) IS NC'D IN POR DESIGNS
AMR_RIGHT_OR_ND_1V8
NC_DMIC_CLK2_IN_IC
74
NC_IRCAM_ENABLE_SEC_1V8_OUT
NC_FTCAM_ENABLE_SEC_1V8_OUT
DMIC_DATA0_1V8_IN
DMIC_DATA1_1V8_IN
FTCAM_DISABLE_1V8_IC_L DMIC_CLK1_1V8_OUT_R
NC_DMIC_DATA2_1V8_IN
AMR_LEFT_OR_ND_1V8
IN
IN
OUT
OUT
IN
IN
OUT
IN
IN
N
73
73 80 89
107
107
107
80
80
68
107
73 89
ROOM=SECURE_DISABLE
RR309
10
PLACE_NEAR=UR300.C3:15MM
2 1
201 5%
MF 1/20W
PACK_IGNORE=TRUE
PACK_OPTION=PROD_SECDIS_3DMIC
OMIT_TABLE
DMIC_CLK2_1V8_OUT_IC
PACK_IGNORE=TRUE
OUT
PACK_OPTION=PROD_SECDIS
PACK_OPTION=PROTO_PULLDOWN_SECDIS
PACK_OPTION=PROTO_PULLDOWN_SECDIS
ROOM=SECURE_DISABLE
RR301
80 89
OUT
DMIC_CLK1_1V8_OUT
OMIT_TABLE
10
5%
ROOM=SECURE_DISABLE
RR302
80 89
OUT
DMIC_CLK0_1V8_OUT
OMIT_TABLE
CKPLUS_WAIVE=TERMSHORTED
10
5%
PACK_IGNORE=TRUE
PACK_OPTION=DEV_SECDIS
ROOM=SECURE_DISABLE
PLACE_NEAR=UR300.C6:15MM
2 1
201
MF 1/20W
PLACE_NEAR=UR300.E6:15MM
2 1
201
MF 1/20W
PART# DESCRIPTION QTY
336S00038 1 IC,PLD,MACHX02,2112 LUT,1.2V,ANN,WLCSP49 SECDIS_PROTO UR300
PART# DESCRIPTION QTY
RR303
0
5%
2 1
0201
9
IN
PDM_DMIC_CLK3
MAKE_BASE=TRUE
PACK_OPTION=PROD_SECDIS
PDM_DMIC_CLK3
1/20W MF
PACK_OPTION=PROTO_PULLDOWN_SECDIS
BOM OPTION REFERENCE DESIGNATOR(S)
1 UR300 336S00039 IC,PLD,MACHX02,2112 LUT,1.2V,AP5,WLCSP49 SECDIS_EVT
SECDIS_EXT_CLK 336S00041 IC,PLD,MACHX02,2112 LUT,1.2V,XXX,WLCSP491 UR300
BOM OPTION REFERENCE DESIGNATOR(S)
RR301,RR302,RR309 DMIC_CLK_10OHMRES,MF,1/20W,10 OHM,5,0201,SMD117S0004 3
RR301,RR302,RR309 DMIC_CLK_33OHMRES,MF,1/20W,33 OHM,5,0201,SMD117S0080 3
AB E_5_H AD
AB E_5_I EM
AB E_5_I EM
AB E_5_I EM
AB E_5_H AD
AB E_5_I EM
AB E_5_I EM
102 74
PP1V2_S2
ROOM=SECURE_DISABLE
BYPASS=UR300.D7::5MM
ROOM=SECURE_DISABLE
BYPASS=UR300.G6::5MM
1
CR300
0.1UF
10%
6.3V
2
CERM-X5R
0201
1
2
CR301
0.1UF
10%
6 3V
CERM-X5R
0201
ROOM=SECURE_DISABLE
BYPASS=UR300.D1::5MM
1
CR302
0.1UF
10%
6.3V
2
CERM-X5R
0201
B
PACK_OPTION=PROD_SECDIS
JTAG FOR DEV & PROTO0 BOARDS ONLY
101 74
SECDIS_TDO_IC SECDIS_TMS
74 74
SECDIS_TDI
74
SECDIS_TCK SECDIS_TDI
74 74
SECDIS_TMS SECDIS_TDO_IC
74 74
PP1V8_S2
APN: 516S00115
ROOM=SECURE_DISABLE
JR300
505070-1222
M-ST-SM
14 13
2 1
3
6 5
8 7
10 9
12 11
15
16
I HAVE ROTATIONAL SYMMETRY
PACK_OPTION=JTAG_SECDIS:YES
SECDIS_TCK
102 74
PP1V2_S2
SERIAL PROGRAMMING DISABLE
74
ROOM=SECURE_DISABLE
PACK_OPTION=JTAG_SECDIS:NO PACK_OPTION=JTAG_SECDIS:NO
101 74
74
PP1V8_S2
CKPLUS_WAIVE=TERMSHORTED
PACK_OPTION=JTAG_SECDIS:YES
SECDIS_TMS
74
SECDIS_TDI
74
SECDIS_TCK
74
JTAG PORT TIE-OFFS
PACK_OPTION=JTAG_SECDIS:YES
CKPLUS_WAIVE=TERMSHORTED
1
RR304
4.7K
5%
1/20W
MF
201
2
1
RR306
4.7K
5%
1/20W
MF
201
2
PACK_OPTION=JTAG_SECDIS:YES
PACK_OPTION=JTAG_SECDIS:NO
GND
MAKE_BASE=TRUE
ROOM=SECURE_DISABLE
1
RR305
4.7K
5%
1/20W
MF
201
2
CKPLUS_WAIVE=TERMSHORTED
101 74
74
ROOM=SECURE_DISABLE
SECDIS_SN_TIE_OFF
PP1V8_S2
MUST BE SAME RAIL AS DMICS
DMIC_CLK_ENABLE
ROOM=SECURE_DISABLE
1
RR307
7K
5%
1/20W
MF
201
2
1
RR308
47K
1%
1/20W
MF
201
2
BOM_COST_GROUP=SOC
101 74
ROOM=SECURE_DISABLE
BYPASS=UR300.B7::5MM
ROOM=SECURE_DISABLE
BYPASS=UR300.A5::5MM
ROOM=SECURE_DISABLE
BYPASS=UR300.A2::5MM
PP1V8_S2
1
CR303
0.1UF
10%
6.3V
2
CERM-X5R
0201
SYNC_MASTER=REF_SECDIS_SAK SYNC_DATE=04/22/2020
PAGE TITLE
1
CR304
0.1UF
10%
6.3V
2
CERM-X5R
0201
1
CR305
0.1UF
10%
6.3V
2
CERM-X5R
0201
SECDIS: FPGA
Page 75
*** OK2INTEGRATE ***
w w w . t e k n i s i - i n d o n e s i a . c o m
102 77 76 75
PP1V25_AWAKE_IO
PACK_IGNORE=TRUE
SPKRAMP_LVL_4B_BGA
PLACE_NEAR=UR400.B4:5MM
1
CR400
0.1UF
10%
25V
2
X5R
0201
VCCA VCCB
UR400
SN74AVC4T234
18 75
18 75
18 75
75 107
TDM_SPKRAMP_L_BCLK
IN
TDM_SPKRAMP_L_FSYNC
IN
TDM_SPKRAMP_L_R2D
IN
SPKRAMP_RESET_L
N
C7
C5
C3
C1
B1
B2
B3
B4
BGA
GND
PACK_IGNORE=TRUE
SPKRAMP_LVL_4B_BGA
PP1V8_AWAKE
PACK_IGNORE=TRUE
SPKRAMP_LVL_4B_BGA
PLACE_NEAR=UR400.B6:5MM
1
CR401
0 1UF
10%
25V
2
X5R
0201
75
A7
A5
A3
A1
75
75
A1
A2
A3
A4
102 78 77 75
TDM_1V8_SPKRAMP_L_BCLK_R
PLACE_NEAR=UR400.A7:10MM
TDM_1V8_SPKRAMP_L_FSYNC_R
PLACE_NEAR=UR400.A5:10MM
TDM_1V8_SPKRAMP_L_R2D_R
PLACE_NEAR=UR400.A3:10MM
SPKRAMP_1V8_RESET_L
RR400
RR401
RR402
PACK_IGNORE=TRUE
SPKRAMP_LVL_4B_BGA
33
33
33
2 1
TDM_1V8_SPKRAMP_L_BCLK
PACK_IGNORE=TRUE
SPKRAMP_LVL_4B_BGA
2 1
TDM_1V8_SPKRAMP_L_FSYNC
PACK_IGNORE=TRUE
SPKRAMP_LVL_4B_BGA
2 1
TDM_1V8_SPKRAMP_L_R2D
5% 1/20W
102 77 76 75
75 107
MF 1/20W 5%
OUT
PP1V25_AWAKE_IO
PACK_IGNORE=TRUE
SPKRAMP_LVL_4B_BGA
PLACE_NEAR=UR430.B4:5MM
1
CR430
0.1UF
10%
25V
2
X5R
0201
VCCA VCCB
UR430
SN74AVC4T234
75 107
MF 201 1/20W 5%
OUT
OUT
75 107
75 77 78 80
18 75
IN
18 75
IN
18 75
IN
TDM_SPKRAMP_R_BCLK
TDM_SPKRAMP_R_FSYNC
TDM_SPKRAMP_R_R2D
C7
C5
C3
C1
B1
B2
B3
B4
BGA
GND
PACK_IGNORE=TRUE
SPKRAMP_LVL_4B_BGA
PP1V8_AWAKE
PACK_IGNORE=TRUE
SPKRAMP_LVL_4B_BGA
PLACE_NEAR=UR430.B6:5MM
1
CR431
0.1UF
10%
25V
2
X5R
0201
75
A1
A2
A3
A4
A7
A5
A3
A1
75
75
NC
102 78 77 75
TDM_1V8_SPKRAMP_R_BCLK_R
PLACE_NEAR=UR430.A7:10MM
TDM_1V8_SPKRAMP_R_FSYNC_R
PLACE_NEAR=UR430.A5:10MM
TDM_1V8_SPKRAMP_R_R2D_R
PLACE_NEAR=UR430.A3:10MM
RR430
RR431
RR432
PACK_IGNORE=TRUE
SPKRAMP_LVL_4B_BGA
33
2 1
TDM_1V8_SPKRAMP_R_BCLK
PACK_IGNORE=TRUE
SPKRAMP_LVL_4B_BGA
33
2 1
TDM_1V8_SPKRAMP_R_FSYNC
PACK_IGNORE=TRUE
SPKRAMP_LVL_4B_BGA
33
2 1
1/20W 5%
TDM_1V8 SPKRAMP_R_R2D
MF 1/20W 5%
MF
MF 1/20W 5%
OUT
OUT
OUT UT
75 107
75 107
75 107
102 7 76 75
75 18
75 18
75 18
107 75
PP1V25_AWAKE_IO
SPKRAMP_LVL_4B_QFN
PLACE_NEAR=UR400 14:5MM
1
CR400
0.1UF
10%
25V
2
X5R
0201
TDM_SPKRAMP_L BCLK
TDM_SPKRAMP_L_FSYNC
TDM_SPKRAMP_L_R2D
SPKRAMP_RESET_L
UR400
SN74AVC4T774-COMBO
QFN
GND
15
16
1
A1
DIR1
2
A2
DIR2
3
A3
5
DIR3
4
A4
6
DIR4
7
OE*
PP1V8_AWAKE
VCCB VCCA
12
B1
B2
B3
B4
75
11
75
10
9
SPKRAMP_1V8_RESET_L
102 78 77 75
SPKRAMP_LVL_4B_QFN
PLACE_NEAR=UR400.13:5MM
1
CR401
0.1UF
10%
25V
2
X5R
0201
TDM_1V8_SPKRAMP_L_BCLK_R
PLACE_NEAR=UR400.12:10MM
TDM_1V8_SPKRAMP_L_FSYNC_R
PLACE_NEAR=UR400.11:10MM
TDM_1V8_SPKRAMP_L_R2D_R
PLACE_NEAR=UR400.10:10MM
75 77 78 80
RR400
RR401
RR402
SPKRAMP_LVL_4B_QFN
33
33
33
2 1
TDM_1V8_SPKRAMP_L_BCLK
SPKRAMP_LVL_4B_QFN
2 1
TDM_1V8_SPKRAMP_L_FSYNC
1/20W 5%
SPKRAMP_LVL_4B_QFN
2 1
TDM_1V8_SPKRAMP_L_R2D
5% 1/20W MF 201
01 MF 1/20W 5%
MF 201
75 107
75 107
75 107 75
102 77 76 75
75 18
75 18
75 18
PP1V25_AWAKE_IO
SPKRAMP_LVL_4B_QFN
PLACE_NEAR=UR430.14:5MM
1
CR430
0.1UF
10%
25V
2
X5R
0201
TDM_SPKRAMP_R_BCLK
TDM_SPKRAMP_R_FSYNC
TDM_SPKRAMP_R_R2D
UR430
SN74AVC4T774-COMBO
QFN
GND
15
16
1
A1
DIR1
2
A2
DIR2
3
A3
5
DIR3
4
A4
6
DIR4
7
OE*
PP1V8_AWAKE
VCCB VCCA
12
B1
11
B2
B3
B4
75
10
75 75 107
9
1 78 77 75
SPKRAMP_LVL_4B_QFN
PLACE_NEAR=UR430.13:5MM
1
CR431
0.1UF
10%
25V
2
X5R
0201
TDM_1V8_SPKRAMP_R_BCLK_R
PLACE_NEAR=UR400.12:10MM
TDM_1V8_SPKRAMP_R_FSYNC_R
PLACE_NEAR=UR400.11:10MM
TDM_1V8_SPKRAMP_R_R2D_R
PLACE_NEAR=UR400.10:10MM
NC
RR430
RR431
RR432
SPKRAMP_LVL_4B_QFN
33
2 1
TDM_1V8_SPKRAMP_R_BCLK
1/20W 5%
SPKRAMP_LVL_4B_QFN
33
2 1
TDM_1V8_SPKRAMP_R_FSYNC
1/20W MF
5%
SPKRAMP_LVL_4B_QFN
33
2 1
TDM_1V8_SPKRAMP_R_R2D
5% 1/20W MF
MF
75 107 75
75 107
OUT
TDM_SPKRAMP_L_D2R
102 77 76 75
RR410
33
1 2
5%
1/20W
MF
201
SPKRAMP_LVL_4B_QFN
PP1V25_AWAKE_IO
PACK_IGNORE=TRUE
SPKRAMP_LVL_1B_DTQ
PLACE_NEAR=UR410.1:5MM
1
CR410
0.1UF
10%
25V
2
X5R
0201
TDM_SPKRAMP_L_D2R_R
PACK_IGNORE=TRUE
SPKRAMP_LVL_1B_DTQ
PLACE_NEAR=UR410.3:10MM
PP1V8_AWAKE
PACK_IGNORE=TRUE
SPKRAMP_LVL_1B_DTQ
UR410
SN74AXC1T45
X2SON
VCCA VCCB
5
DIR
3 4
75
A
GND
B
PACK_IGNORE=TRUE
SPKRAMP_LVL_1B_DTQ
PLACE_NEAR=UR410.6:5MM
1
CR411
0.1UF
10%
25V
2
X5R
0201
TDM_1V8_SPKRAMP_L_D2R
102 78 77 75
75 107 18 75 75 107 18 75
IN
OUT
TDM_SPKRAMP_R_D2R
102 77 76 75
RR440
33
5%
1/20W
MF
201
PP1V25_AWAKE_IO
PACK_IGNORE=TRUE
SPKRAMP_LVL_1B_DTQ
PLACE_NEAR=UR440.1:5MM
1
CR440
0.1UF
10%
25V
2
X5R
0201
2 1
TDM_SPKRAMP_R_D2R_R
PACK_IGNORE=TRUE
SPKRAMP_LVL_1B_DTQ
PLACE_NEAR=UR440.3:10MM
SPKRAMP_LVL_4B_QFN
PP1V8_AWAKE
PACK_IGNORE=TRUE
SPKRAMP_LVL_1B_DTQ
PLACE_NEAR=UR440.6:5MM
1
PACK_IGNORE=TRUE
SPKRAMP_LVL_1B_DTQ
UR440
SN74AXC1T45
X2SON
VCCA VCCB
5
DIR
4 3
A
75
GND
B
TDM_1V8_SPKRAMP_R_D2R
CR441
0.1UF
10%
25V
2
X5R
0201
102 78 77 75
IN
AUDIO
1.2V <-> 1.8V
75 18
75 18
TDM_SPKRAMP_L_D2R
TDM_SPKRAMP_L_D2R
102 77 76 75
RR410
33
5%
1/20W
MF
201
102 77 76 75
RR410
33
5%
1/20W
MF
201
PP1V25_AWAKE_IO
PACK_IGNORE=TRUE
SPKRAMP_LVL_1B_DEA
PLACE_NEAR=UR410.1:5MM
1
CR410
0.1UF
10%
25V
2
X5R
0201
2 1
TDM_SPKRAMP_L_D2R_R
PACK_IGNORE=TRUE
SPKRAMP_LVL_1B_DEA
PLACE_NEAR=UR410.3:10MM
PP1V25_AWAKE_IO
SPKRAMP_LVL_1B_SON
PLACE_NEAR=UR410.6:5MM
1
CR410
0.1UF
10%
25
X R
0201
2 1
SPKRAMP_LVL_1B_SON
PLACE_NEAR=UR410.4:10MM
5
75
SPKRAMP_LVL_1B_SON
UR410
SN74AUP1G17
4 2
75 75
VCCA VCCB
DIR
A
GND
SON
NC
NC
PP1V8_AWAKE
PACK_IGNORE=TRUE
SPKRAMP_LVL_1B_DEA
UR410
SN74AXC1T45
X2SON-1
4 3
B
VCC
TDM_1V8_SPKRAMP_L_D2R TDM_SPKRAMP_L_D2R_R TDM_SPKRAMP_R_D2R_R TDM_1V8_SPKRAMP_R_D2R
GND
PACK_IGNORE=TRUE
SPKRAMP_LVL_1B_DEA
PLACE_NEAR=UR410.6:5MM
1
CR411
0.1UF
10%
25V
2
X5R
0201
102 78 77 75
102 77 76 75
PP1V25_AWAKE_IO
PACK_IGNORE=TRUE
SPKRAMP_LVL_1B_DEA
PLACE_NEAR=UR440.1:5MM
1
CR440
0.1UF
10%
25V
2
X5R
0201
RR440
33
5%
/ 0W
MF
201
2 1
PACK_IGNORE=TRUE
SPKRAMP_LVL_1B_DEA
PLACE_NEAR=UR44 3 1 MM
PP1V25_AWAKE_IO
SPKRAMP_LVL_1B_SON
PLACE_NEAR=UR440.6:5MM
1
CR440
0.1UF
10%
2 V
2
X5R
0201
SPKRAMP_LVL_1B_SON
TDM_1V8_SPKRAMP_L_D2R TDM_SPKRAMP_R_D2R_R
75 107
75 18
TDM_SPKRAMP_R_D2R
102 77 76 75
RR440
33
5%
MF
201
2 1
SPKRAMP_LVL_1B_SON
PLACE_NEAR=UR440.4:10MM
75 107
75 18
TDM_SPKRAMP_R_D2R
1/20W
5
DIR
A
75
UR440
SN74AUP1G17
SON
4 2
VCCA VCCB
GND
VCC
NC
NC
GND
PP1V8_AWAKE
PACK_IGNORE=TRUE
SPKRAMP_LVL_1B_DEA
UR440
SN74AXC1T45
X2SON-1
4 3
B
TDM_1V8_SPKRAMP_R_D2R
PACK_IGNORE=TRUE
SPKRAMP_LVL_1B_DEA
PLACE_NEAR=UR440.6:5MM
1
CR441
0.1UF
10%
25V
2
X5R
0201
102 78 7 75
75 107
75 107
LEVEL SHIFTERS
MAX PROP DELAY:
TP (4-BIT) + TP (1-BIT) < 35 NS
SYNC_DATE=04/16/2020 SYNC_MASTER=REF_SPKRAMP_TAS5770
PAGE TITLE
AUDIO SUPPORT
2
1
Page 76
*** OK2INTEGRATE ***
w w w . t e k n i s i - i n d o n e s i a . c o m
AUDIO JACK CODEC I2C ADDRESS
GND
GND
1.8V
AD0 AD1
GND
GND
ADDRESS
0X48 <-0X49 1.8V
0X4A
CHANGES FROM PREVIOUS DESIGNS:
- REMOVED LDO TO GENERATE LOCAL 1.8V
<RDAR://50645294>
- CHANGED VL SUPPLY FROM 1.8V TO 1.2V
<RDAR://TBD>
- SUPPLIED VD_FILT EXTERNALLY
<RDAR://TBD>
- CHANGED VP SUPPLY FROM 3.3V TO 3.8V
<RDAR://TBD>
1.8V
0X4B 1.8V
AUDIO JACK PINOUT
RING SENSE
TIP SENSE
LEFT
LEFT SENSE
RIGHT
RIGHT SENSE
GLOBAL GND
CHINA MIC
CHINA GND
GLOBAL MIC
TO / FROM
AUDIO JACK
CONNECTOR
NOTES:
- SEE TEST POINT SIGNALS & LOCATIONS ON REF DESIGN PAGE 1
- THE FOLLOWING SIGNALS SHOULD HAVE A LOW DCR PATH:
- VP SUPPLY
- VCP SUPPLY
- AUDIO_JACK_LEFT/RIGHT_OUT
- AUDIO_JACK_GB/CH_GND
LR501
2 1
0201
* SEE NOTE
PP1V8_AWAKE
EDC CURRENT = 380MA
TDC CURRENT = 150MA
102
PP1V25_AWAKE_IO
102
EDC CURRENT = 2 MA
TDC CURRENT = 10M
LR500
FERR-22-OHM-1A-0.055OHM
2 1
0201
PP1V2_CODEC_VL_VD
MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.1000
VOLTAGE=1.225V
BYPASS=UR500.A7:B6:5MM
20%
6.3V
X5R
1
2
CR500
1.0UF
0201-1
PP1V8_CODEC_VA
MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.1000
VOLTAGE=1.8V
NO_XNET_CONNECTION=1
BYPASS=UR500.B1:C2:4MM
GND_AUDIO_CODEC
76 89
CR501
2.2UF
20%
10V
X5R-CERM
402
FERR-22-OHM-1A-0.055OHM
1
2
LR502
FERR-22-OHM-1A-0.055OHM
BYPASS=UR500.A3:B3:5MM
10%
6.3V
0201
1
2
VP
VD_FILT
VL VA VCP
CRITICAL
UR500
CS42L83A
WLCSP-SKT
+VCP_FILT
-VCP_FILT
DIGLDO_PDN*
SWIRE_SEL
ASP_LRCK/FSYNC
SWIRE_SD/ASP_SDIN
ASP_SDOUT
SWIRE_CLK/ASP_SCLK
CR502
0.1UF
CERM-X5R
FERR-22-OHM-1A-0.055OHM
PP3V8_AON
101
EDC CURRENT = 850MA
TDC CURRENT = 110MA
80
OUT
80
OUT
80
IN
80
IN
80
IN
80
IN
80
IN
80
IN
80
IN
80
IN
AUDIO_JACK_LEFT_OUT
AUDIO_JACK_RIGHT_OUT
* SEE NOTE
76 89
NO_XNET_CONNECTION=1
GND_AUDIO_CODEC
AUDIO_JACK_LEFT_SNS
AUDIO_JACK_RIGHT_SNS
AUDIO_JACK_CH_GND
AUDIO_JACK_GB_GND
* SEE NOTE
AUDIO_JACK_CH_MIC
AUDIO_JACK_GB_MIC
* SEE NOTE
AUDIO_JACK_RING_SNS
AUDIO_JACK_TIP_SNS
LR503
0201
RR500
1K
5%
1/20W
MF
201
* SEE NOTE
2 1
NO_XNET_CONNECTION=1
1
2
1
RR501
1K
5%
1/20W
MF
201
2
PP3V8_CODEC_VP
MIN_LINE_WIDTH=0.3000
MIN_NECK_WIDTH=0.1500
VOLTAGE=3.8V
BYPASS=UR500.D7:C7:5MM
CODEC_HSBIAS_FILT
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
1
CR508
4.7UF
20%
16V
2
X5R
0402-1
BYPASS=UR500.F3:E3:4MM
CR504
10UF
20%
10V
X5R-CERM
0402-7
1
2
D5
HPSENSA
E5
HPOUTA
F5
HPSENSB
G5
HPOUTB
F1
HS4
E2
HS_CLAMP2
E1
HSIN+
G2
HS3
F2
HS_CLAMP1
D1
HSIN-
F4
HS4_REF
G4
HS3_REF
G3
RING_SENSE
E4
TIP_SENSE
F3
HSBIAS_FILT
E3
HSBIAS_FILT_REF
CODEC_HSBIAS_FILT_REF
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
SM
GNDHS GNDA GNDD
2 1
76 89
PLACE_NEAR=UR500 G1:1MM
GND_AUDIO_CODEC
VOLTAGE=0V
GNDL
XWR501
PP1V8_CODEC_VCP
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1500
VOLTAGE=1.8V
E6
G6
AD0
AD1
SDA
SCL
F6
C4
D4
B7
C6
C5
A6
D3
B5
A5
A4
B4
C3
B2
A1
A2
E7
F7
G7
C1
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
BYPASS=UR500.C1:C2 4 MM
GNDCP
VL_SEL
INT*
WAKE*
RESET*
SPDIF_TX
FLYP
FLYC
FLYN
FILT_P
BYPASS=UR500.D6:F6:6MM
CODEC_VCP_FILTP
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1500
NO_XNET_CONNECTION=1
BYPASS=UR500.E6:F6:4MM
NO_XNET_CONNECTION=1
BYPASS=UR500.F6:G6:4MM
CODEC_VCP_FILTN
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1500
NC
TDM_CODEC_D2R_R
PLACE_NEAR=UR500.A4:5MM
CODEC_FLYP
CODEC_FLYC
CODEC_FLYN
CODEC_FILT
NO_XNET_CONNECTION=1
CR510
10UF
0603-1
NO_XNET_CONNECTION=1
CR503
2.2UF
20%
10V
X5R-CERM
402
20%
16V
X5R
20%
16V
X5R
1
2
1
2
CR505
4.7UF
CR506
4.7UF
1
20%
10V
2
X5R
0402-1
0402-1
1
2
CODEC_VCP_FILT_GND
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1500
33
2 1
1/20W 5%
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0 1000
MF 201
NO_XNET_CONNECTION=1
BYPASS=UR500.E7:F7:4MM
NO_XNET_CONNECTION=1
BYPASS=UR500.F7:G7:4MM
2 1
0201
RR505
NOSTUFF
1
RR502
47K
5%
1/20W
MF
201
2
CR509
2.2UF
20%
10V
X5R-CERM
402
CR511
2.2 F
20
10V
X5R-CERM
402
XWR500
SM
2 1
PP1V25_AWAKE_IO
PP1V25_S2
102 77 75
102
NOSTUFF
1
RR503
47K
5%
1/20W
MF
201
2
CODEC_INT_L
CODEC_WAKE_L
CODEC_RESET_L
1
RR504
47K
5%
1/20W
MF
201
2
TDM_CODEC_FSYNC
TDM_CODEC_R2D
TDM_CODEC_D2R
TDM_CODEC_BCLK
I2C_CODEC_SDA
I2C_CODEC_SCL
1
2
1
2
OUT
OUT
IN
IN
IN
OUT
IN
BI
IN
6
33
9 80
18
18
6
18
41
41
-> TO SOC
-> TO PMU
<- FROM SOC
- GB_MIC SIGNAL CONNECTS TO CH_GND AT A/J CONNECTOR.
CH_MIC SIGNAL CONNECTS TO GB_GND AT A/J CONNECTOR.
- VP SUPPLY RAIL ACCEPTS 3.0V TO 5.25V AND NEEDS TO
COME UP FIRST AND TURN OFF LAST (NEED TO STAY UP
WHEN THE OTHER RAILS GO DOWN)
VP CURRENT CONSUMPTION WITH PART IN LOWEST POWER STATE:
3.1UA (1V8 OFF, RST# LOW)
3.6UA (1V8 ON, RST# LOW)
36UA (1V8 ON, RST# HIGH)
SYNC_MASTER=REF_CODEC_CLIFDEN
PAGE TITLE
AUDIO JACK CODEC
BOM_COST_GROUP=AUDIO
7 8
2
Page 77
*** OK2INTEGRATE ***
w w w . t e k n i s i - i n d o n e s i a . c o m
102 78
PP1V8_AWAKE
75 77 78 80
I
41 80
BI
41 80
IN
6 77 78 80
OUT
80 107
IN
80 107
OUT
80 107
IN
80 107
IN
SPKRAMP_12V8_RESET_L
SPKRAMP_A
I2C_1V8_SPKRAMP_L_SDA
SPKRAMP_A
I2C_1V8_SPKRAMP_L_SCL
SPKRAMP_A
SPKRAMP_INT_L
SPKRAMP_A
SPKRAMP_A_ADDR
77
TDM_1V8_SPKRAMP_L_R2D
SPKRAMP_A
TDM_1V8_SPKRAMP_L_D2R
SPKRAMP_A
TDM_1V8_SPKRAMP_L_FSYNC
SPKRAMP_A
TDM_1V8_SPKRAMP_L_BCLK
SPKRAMP_A
SPKRAMP_A
PLACE_NEAR=UR600.C1:6MM PLACE_NEAR=UR600.C1:4MM
1
CR600
1UF
20%
16V
2
CER-X5R
0201
SPKRAMP_A
1
CR601
0.1UF
10%
25V
2
X5R
0201
RR600
33
PLACE_NEAR=UR600.E1:10MMSPKRAMP_A
2 1
TDM_SPKRAMP_A_D2R_R
5%
SPKRAMP_A
PLACE_NEAR=UR600.D2:6MM
1
CR602
1UF
20%
16V
2
CER-X5R
0201
1/20W
SPKRAMP_A
PLACE_NEAR=UR600.D2:4MM
1
CR603
0.1UF
10%
25V
2
X5R
0201
C3
SDZ*
F3
SDA
F4
SCL
D4
IRQZ
MODE
F2
SDIN
E1
SDOUT
E2
FSYNC
F1
SBCLK
E4
PDMD0
E3
PDMCK0
E5
PDMD1
F5
PDMCK1
AVDD IOVDD
UR600
TAS5770AC0
DSBGA
SPKRAMP_A
GND
PGND
VBAT
VSNS_P
VSNS_N
BST_P
OUT_P
OUT_P
BST_N
OUT_N
OUT_N
AREG
DREG
B2
A3
B3
A1
A2
A5 D3
B5
B1
D5
D1
SPKRAMP_A
PLACE_NEAR=UR600.C5:5MM
1
CR604
10%
25V
2
X5R
0201
SPKRAMP_A_BOOTP
MIN_LINE_WIDTH=0.1000
SPKRAMP_A_OUTP_R
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0 1000
SPKRAMP_A_BOOTN
MIN_LINE_WIDTH=0.1000
SPKRAMP_A_OUTN_R
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0 1000
SPKRAMP_A_AREG
SPKRAMP_A_DREG
SPKRAMP_A
PLACE_NEAR=UR600.D1:3 MM
1
CR613
0.1UF
10%
25V
2
X5R
0201
SPKRAMP_A
PLACE_NEAR=UR600.C5:10MM
1
CR605
10UF
20%
25V
2
X5R-CERM
0603
BYPASS=UR600.B2:B3:10MM
NO_XNET_CONNECTION=1
CR609
CR610
BYPASS=UR600.A2 A5:10MM
NO_XNET_CONNECTION=1
SPKRAMP_A
PLACE_NEAR=UR600.D1:5 MM
1
CR614
1UF
20%
16V
2
CER-X5R
0201
0.1UF
25V
0.1UF
25V
2 1
0201
2 1
0201
SPKRAMP_A
PLACE_NEAR=UR600.C5:10MM
1
CR606
10UF
20%
25V
2
X5R-CERM
0603
10
SPKRAMP_A
X5R
* SEE NOTE
10%
SPKRAMP_A
X5R
SEE NOTE
SPKRAMP_A
PLACE_NEAR=UR600.D5:3 MM
1
CR615
0.1UF
10%
25V
2
X5R
0201
RR601
0%
MF 1/4W
SPKRAMP_A
RR602
0%
MF
SPKRAMP_A
SPKRAMP_A
PLACE_NEAR=UR600.C5:10MM
1
CR607
10UF 0.1UF
20%
25V
2
X5R-CERM
0603
PPBUS_SPKRAMP_LEFT_ISNS
MAX CURRENT EDC = 4A (PER AMP)
SPKRAMP_A
PLACE_NEAR=UR600.C5:10MM
1
CR608
10UF
20%
35V
2
X5R-CERM
0603
105
102 78 77 75
AMP A
0
2 1
0603
0
2 1
0603
1/4W
* SEE NOTE
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
* SEE NOTE
MIN_LINE_WIDTH 0.2000
MIN_NECK_WIDTH=0.1000
SPKRAMP_A
CR611
220PF
X7R-CERM
10%
25V
201
1
2
NOSTUFF
SPKRAMP_A
PLACE_NEAR=UR600.D5:5 MM
1
CR616
1UF
20%
16V
2
CER-X5R
0201
SPKRAMP_A_OUTP
SPKRAMP_A
SPKRAMP_A_VSENSEP
* SEE NOTE
SPKRAMP_A
SPKRAMP_A_OUTN
SPKRAMP_A
SPKRAMP_A_VSENSEN
* SEE NOTE
SPKRAMP_A
1
CR612
220PF
10%
25V
2
X7R-CERM
201
SPKRAMP_A
NOSTUFF
OUT
IN
OUT
IN
79 89
79
79 89
79
PP1V8_AWAKE
SPKRAMP_A_ADDR
77
0X62
SPKRAMP_B_ADDR
77
0X64
SPKRAMP_C_ADDR
77
0X66
SPKRAMP_A
SPKRAMP_B
SPKRAMP_C
RR605
0
2 1
5%
1/20W
MF
0201
RR635
470
1/20W
PACK_IGNORE=TRUE
5%
MF
201
2 1
RR664
470
2 1
5%
1/20W
MF
201
102 78 77 75
PP1V8_AWAKE
SPKRAMP_1V8_RESET_L
SPKRAMP_B
I2C_1V8_SPKRAMP_L_SDA
SPKRAMP_B
I2C_1V8_SPKRAMP_L_SCL
SPKRAMP_B
SPKRAMP_INT_L
SPKRAMP_B
SPKRAMP_B_ADDR
7
TDM_1V8_SPKRAMP_L_R2D
SPKRAMP_B
TDM_1V8_SPKRAMP_L_D2R
SPKRAMP_B
TDM_1V8_SPKRAMP_L_FSYNC
SPKRAMP_B
TDM_1V8_SPKRAMP_L_BCLK
SPKRAMP_B
107
107
107
107
75 77 78 80
IN
41
BI
41
IN
6 77 78 80
OUT
I
OUT
IN
IN
SPKRAMP_B
PLACE_NEAR=UR630.C1:6MM
1
CR630
1UF
20%
16V
2
CER-X5R
0201
SPKRAMP_B
PLACE_NEAR=UR630.C1:4MM
1
CR631
0.1UF
10%
25V
2
X5R
0201
33
RR630
2 1
SPKRAMP_B
PLACE_NEAR=UR630.D2:6MM
1
CR632
1UF
20%
16V
2
CER-X5R
0201
PLACE_NEAR=UR630.E1:10MMSPKRAMP_B
TDM_SPKRAMP_B_D2R_R
201 MF 1/20W 5%
SPKRAMP_B
PLACE_NEAR=UR630.D2:4MM
1
CR633
0 1UF
10%
25V
2
X5R
0201
C3
SDZ*
F3
SDA
F4
SCL
D4
IRQZ
MODE
F2
SDIN
E1
SDOUT
E2
FSYNC
F1
SBCLK
E4
PDMD0
E3
PDMCK0
E5
PDMD1
F5
PDMCK1
AVDD IOVDD
UR630
TAS5770AC0
DSBGA
SPKRAMP_B
GND
PGND
VBAT
VSNS_P
VSNS_N
BST_P
OUT_P
OUT_P
BST_N
OUT_N
OUT_N
AREG
DREG
B2
A3
B3
A
A2
A5 D3
B5
B1
D5
D1
SPKRAMP_B
PLACE_NEAR=UR630.C5:5MM
1
CR634
0.1UF
10%
25V
2
X5R
0201
SPKRAMP_B_BOOTP
MIN_LINE_WIDTH=0.1000
SPKRAMP_B_OUTP_R
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0 1000
SPKRAMP_B_BOOTN
MIN_LINE_WIDTH=0.1000
SPKRAMP_B_OUTN_R
M N_LINE_WIDTH=0.2000
MI _NECK_WIDTH=0 1000
SPKRAMP_B_AREG
SPKRAMP_B_DREG
SPKRAMP_B
PLACE_NEAR=UR630.D1:3 MM
1
CR643
0.1UF
10%
25
2
X5R
0201
SPKRAMP_B
PLACE_NEAR=UR630.C5:10MM
1
CR635
10UF
20%
25V
2
X5R-CERM
0603
BYPASS=UR630.B2:B3:10MM
NO_XNET_CONNECTION=1
CR639
CR640
BYPASS=UR630.A2:A5:10MM
NO_XNET_CONNECTION=1
SPKRAMP_B
PLACE_NEAR=UR630.D1:5 MM
1
CR644
1UF
20%
16
2
CER-X5R
0201
0.1UF
25V
0.1UF
25V
0201
2 1
0201
2 1
SPKRAMP_B
PLACE_NEAR=UR630.C5:10MM
1
CR636
10UF
20%
25V
2
X5R-CERM
0603
10%
SPKRAMP_B
X5R
* SEE NOTE
10%
SPKRAMP_B
X5R
* E NOTE
SPKRAMP_B
PLACE_NEAR=UR630.D5:3 MM
1
CR645
0.1UF
10%
25
2
X5R
0201
RR631
0%
SPKRAMP_B
RR632
0%
MF
SPKRAMP_B
PACK_IGNORE=TRUE
SPKRAMP_EXT_PU
102 76 75
PACK_IGNORE=TRUE
SPKRAMP_EXT_PU
6 77 78 80
75 77 78 80
SPKRAMP_B
PLACE_NEAR=UR630.C5:10MM
1
CR637
10UF
20%
25V
2
X5R-CERM
0603
PPBUS_SPKRAMP_LEFT_ISNS
MAX CURRENT EDC = 4A (PER AMP)
SPKRAMP_B
PLACE_NEAR=UR630.C5:10MM
1
CR638
10UF
20%
35V
2
X5R-CERM
0603
105
AMP B
0
2 1
0603
1/4W MF
0
2 1
0603
1/4W
* SEE NOTE
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
* SEE NOTE
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
SPKRAMP_B
CR641
220PF
X7R-CERM
10%
25V
201
1
2
NOSTUFF
SPKRAMP_B
PLACE_NEAR=UR630.D5:5 MM
1
CR646
1UF
20%
16
2
CER-X5R
0201
SPKRAMP_B_OUTP
SPKRAMP_B
SPKRAMP_B_VSENSEP
* S E NOTE
SPKRAMP_B
SPKRAMP_B_OUTN
SPKRAMP_B
SPKRAMP_B_VSENSEN
* SEE NOTE
SPKRAMP_B
1
CR642
220PF
10%
25V
2
X7R-CERM
201
SPKRAMP_B
NOSTUFF
OUT
IN
OUT
IN
79 89
79
9 89
9
PP1V25_AWAKE_IO
SPKRAMP_INT_L
OUT
SPKRAMP_1V8_RESET_L
IN
1
RR691
47K
5%
1/20W
MF
201
2
1
RR692
47K
5%
1/20W
MF
201
2
102 78 77 75
PP1V8_AWAKE
75 77 78 80
IN
BI
IN
6 77 78 80
OUT
77
IN
OUT
IN
IN
SPKRAMP_1V8_RESET_L
PACK_IGNORE=TRUE
SPKRAMP_C
=I2C_1V8_SPKRAMP_C_SDA
PACK_IGNORE=TRUE
SPKRAMP_C
=I2C_1V8_SPKRAMP_C_SCL
PACK_IGNORE=TRUE
SPKRAMP_C
SPKRAMP_INT_L
P CK_IGNORE=TRUE
S KRAMP_C
SPKRAMP_C_ADDR
=TDM_1V8_SPKRAMP_C_R2D
PACK_IGNORE=TRUE
SPKRAMP_C
=TDM_1V8_SPKRAMP_C_D2R
PACK_IGNORE=TRUE
SPKRAMP_C
=TDM_1V8_SPKRAMP_C_FSYNC
PACK_IGNORE=TRUE
SPKRAMP_C
=TDM_1V8_SPKRAMP_C_BCLK
PACK_IGNORE=TRUE
SPKRAMP_C
PACK_IGNORE=TRUE
SPKRAMP_C
PLACE_NEAR=UR660.C1:6MM
1
CR660
1UF
20%
16V
2
CER-X5R
0201
PACK IGNORE=TRUE
SPKR MP_C
PLACE_NEAR=UR660.C1:4MM
1
CR661
0.1UF
10%
25V
2
X5R
0201
PACK_IGNORE=TRUE
33
RR660
2 1
PACK IGNORE=TRUE
SPKR MP_C
PLACE_NEAR=UR660.D2:6MM
1
CR662
1UF
20%
16V
2
CER-X5R
0201
PLACE_NEAR=UR660.E1:10MMSPKRAMP_C
TDM_SPKRAMP_C_D2R_R
5% 1/20W 201
MF
PACK IGNORE=TRUE
SPKR MP_C
PLACE_NEAR=UR660.D2:4MM
1
CR663
0.1UF
10%
25V
2
X5R
0201
C3
SDZ*
F3
SDA
F4
SCL
D4
IRQZ
MODE
F2
SDIN
E1
SDOUT
E2
FSYNC
F1
SBCLK
E4
PDMD0
E3
PDMCK0
E5
PDMD1
F5
PDMCK1
AVDD IOVDD
UR660
TAS5770AC0
DSBGA
PACK_IGNORE=TRUE
SPKRAMP_C
GND
PGND
VBAT
VSNS_P
VSNS_N
BST_P
OUT_P
OUT_P
BST_N
OUT_N
OUT_N
AREG
DREG
B2
A3
B3
A1
A2
A5 D3
B5
B1
D5
D1
PACK_IGNORE=TRUE
SPKRAMP_C
PLACE_NEAR=UR660.C5 5MM
1
CR664
0.1UF
10%
25
X R
0201
SPKRAMP_C_BOOTP
MIN_LINE_WIDTH=0.1000
SPKRAMP_C_OUTP_R
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0 1000
PKRAMP_C_BOOTN
MIN_LINE_WIDTH=0.1000
SPKRAMP_C_OUTN_R
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0 1000
SPKRAMP_C_AREG
SPKRAMP_C_DREG
PACK_IGNORE=TRUE
SPKRAMP_C
PLACE_NEAR=UR660.D1:3 MM
1
CR673
0.1UF
10%
25V
2
X5R
0201
PACK_IGNORE=TRUE
SPKRAMP_C
PLACE_NEAR=UR660.C5:10MM
1
CR665
10UF
20%
25
X R CERM
0603
BYPASS=UR660.B2:B3:10MM
NO_XNET_CONNECTION=1
CR669
CR670
BYPASS=UR660.A2:A5:10MM
NO_XNET_CONNECTION=1
PACK_IGNORE=TRUE
SPKRAMP_C
LA E_NEAR=UR660.D1:5 MM
1
CR674
1UF
20%
16V
2
CER-X5R
0201
0.1UF
25V
0.1UF
25V
2 1
0201
2 1
0201
PACK_IGNORE=TRUE
SPKRAMP_C
PLACE_NEAR=UR660.C5:10MM
1
CR666
10UF
20%
25
X R CERM
0603
PACK_IGNORE=TRUE
10%
SPKRAMP_C
X5R
* SEE NOTE
10%
X5R
ACK_IGNORE=TRUE
SPKRAMP_C
* SEE NOTE
PACK_IGNORE=TRUE
SPKRAMP_C
LA E_NEAR=UR660.D5:3 MM
1
CR675
0.1UF
10%
25V
2
X5R
0201
RR661
0%
MF 1/4W
PACK_IG ORE=TRUE
SPKRAMP_C
RR662
0%
MF
PACK_IGNORE=TRUE
SPKRAMP_C
PACK_IGNORE=TRUE
SPKRAMP_C
PLACE_NEAR=UR660.C5:10MM
1
CR667
10UF
20%
25
X R CERM
0603
0
2 1
0603
0
2 1
0603
1/4W
PACK_IGNORE=TRUE
SPKRAMP_C
LA E_NEAR=UR660.D5:5 MM
1
CR676
1UF
20%
16V
2
CER-X5R
0201
* SEE NOTE
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
* SEE NOTE
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
PACK_IGNORE=TRUE
MAX CURRENT EDC = 4A (PER AMP)
SPKRAMP_C
PLACE_NEAR=UR660.C5:10MM
1
CR668
10UF
20%
35
X R CERM
0603
SPKRAMP_C_OUTP
SPKRAMP_C_VSENSEP
SPKRAMP_C_OUTN
SPKRAMP_C_VSENSEN
PACK_IGNORE=TRUE
SPKRAMP_C
CR671
220PF
10%
25V
X7R-CERM
201
1
2
1
2
NOSTUFF
AMP C
* SEE NOTE
PACK_IGNORE=TRUE
* SEE NOTE
SPKRAMP_C
CR672
220PF
10
25V
X7R-CERM
201
NOSTUFF
PACK_IGNO TRUE
SPKRAMP_C
PACK_IGNORE T E
SPKRAMP_C
PACK_IGNOR TRUE
SPKRAMP_C
PACK_IGNORE TRUE
SPKRAMP_C
OUT
IN
OUT
IN
NOTES:
- CHECK THAT SPKRAMP_INT_L
HAS IPU ON SOC SIDE.
- VSENSEP/N SIGNALS CONNECT
TO OUTP/N SIGNALS AT THE
SPEAKER CONNECTOR PINS.
- THE FOLLOWING SIGNALS SHOULD
HAVE A VERY LOW DCR PATH:
- SPKRAMP_XX_OUTP/N_R
- SPKRAMP_XX_OUTP/N
- PVDD SUPPLY
- FOR THERMALS PGND PINS MUST
CONNECT TO GND LAYERS USING
COPIOUS AMOUNT OF VIAS.
SYNC_DATE=04/16/2020SYNC_MASTER=REF_SPKRAMP_TAS5770
PAGE TITLE
AUDIO AMPLIFIERS (1/2)
=PPBUS_AON_C_SPKRAMP
BOM_COST_GROUP=AUDIO
Page 78
*** OK2INTEGRATE ***
w w w . t e k n i s i - i n d o n e s i a . c o m
7
102 78 77 75
PP1V8_AWAKE
75 77 78 80
I
41 80
BI
41 80
IN
6 77 78 80
OUT
80 107
IN
80 107
OUT
80 107
IN
80 107
IN
SPKRAMP_1V8_RESET_L
SPKRAMP_D
I2C_1V8_SPKRAMP_R_SDA
SPKRAMP_D
I2C_1V8_SPKRAMP_R_SCL
SPKRAMP_D
SPKRAMP_INT_L
SPKRAMP_D
SPKRAMP_D_ADDR
78
TDM_1V8_SPKRAMP_R_R2D
SPKRAMP_D
TDM_1V8_SPKRAMP_R_D2R
SPKRAMP_D
TDM_1V8_SPKRAMP_R_FSYNC
SPKRAMP_D
TDM_1V8_SPKRAMP_R_BCLK
SPKRAMP_D
SPKRAMP_D
PLACE_NEAR=UR700.C1:6MM
1
CR700
1UF
20%
16V
2
CER-X5R
0201
SPKRAMP_D
PLACE_NEAR=UR700.C1:4MM
1
CR701
0.1UF
10%
25V
2
X5R
0201
SPKRAMP_D
RR700
33
2 1
SPKRAMP_D
PLACE_NEAR=UR700.D2:6MM
1
CR702
1UF
20%
16V
2
CER-X5R
0201
PLACE_NEAR=UR700.E1:10MM
TDM_SPKRAMP_D_D2R_R
5% 1/20W
SPKRAMP_D
PLACE_NEAR=UR700.D2:4MM
1
CR703
0.1UF
10%
25V
2
X5R
0201
C3
SDZ*
F3
SDA
F4
SCL
D4
IRQZ
MODE
F2
SDIN
E1
SDOUT
E2
FSYNC
F1
SBCLK
E4
PDMD0
E3
PDMCK0
E5
PDMD1
F5
PDMCK1
AVDD IOVDD
UR700
TAS5770AC0
DSBGA
SPKRAMP_D
GND
PGND
VBAT
VSNS_P
VSNS_N
BST_P
OUT_P
OUT_P
BST_N
OUT_N
OUT_N
AREG
DREG
B2
A3
B3
A1
A2
A D3
B5
B1
D5
D1
SPKRAMP_D
PLACE_NEAR=UR700.C5:5MM
1
CR704
0.1UF
10%
25V
2
X5R
0201
SPKRAMP_D_BOOTP
MIN_LINE_WIDTH=0.1000
SPKRAMP_D_OUTP_R
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0 1000
SPKRAMP_D_BOOTN
MIN_LINE_WIDTH=0 1000
SPKRAMP_D_OUTN_R
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0 1000
SPKRAMP_D_AREG
SPKRAMP_D_DREG
SPKRAMP_D
PLACE_NEAR=UR700.D1:3 MM
1
CR713
0.1UF
10%
25V
2
X5R
0201
SPKRAMP_D
PLACE_NEAR=UR700.C5:10MM
1
CR705
10UF
20%
25V
2
X5R-CERM
0603
BYPASS=UR700.B2:B3:10MM
NO_XNET_CONNECTION=1
CR709
CR710
BYPASS=UR700.A2 A5:10MM
NO_XNET_CONNECTION=1
SPKRAMP_D
PLACE_NEAR=UR700.D1:5 MM
1
CR714
1UF
20%
16V
2
CER-X5R
0201
0.1UF
2 1
0201
25V
0.1UF
2 1
0201
25V X5R
SPKRAMP_D
PLACE_NEAR=UR700.C5:10MM
1
CR706
10UF
20%
25V
2
X5R-CERM
0603
10%
SPKRAMP_D
X5R
* SEE NOTE
10%
SPKRAMP_D
SEE NOTE
SPKRAMP_D
PLACE_NEAR=UR700.D5:3 MM
1
CR715
0.1UF
10%
25V
2
X5R
0201
RR701
0%
MF 1/4W
SPKRAMP_D
RR702
0%
MF
SPKRAMP_D
SPKRAMP_D
PLACE_NEAR=UR700.C5:10MM
1
CR707
10UF
20%
25V
2
X5R-CERM
0603
PBUS_SPKRAMP_RIGHT_ISNS
MAX CURRENT EDC = 4A (PER AMP)
SPKRAMP_D
PLACE_NEAR=UR700.C5:10MM
1
CR708
10UF
20%
35V
2
X5R-CERM
0603
105
102 78 77 75
AMP D
0
2 1
0603
0
2 1
0603
1/4W
* SEE NOTE
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
* SEE NOTE
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
SPKRAMP_D
CR711
220PF
X7R-CERM
10%
25V
201
1
2
NOSTUFF
SPKRAMP_D
PLACE_NEAR=UR700.D5:5 MM
1
CR716
1UF
20%
16V
2
CER-X5R
0201
SPKRAMP_D_OUTP
SPKRAMP_D
SPKRAMP_D_VSENSEP
* SEE NOTE
SPKRAMP_D
SPKRAMP_D_OUTN
SPKRAMP_D
SPKRAMP_D_VSENSEN
* SEE NOTE
SPKRAMP_D
1
CR712
220PF
10%
25V
2
X7R-CERM
201
SPKRAMP_D
NOSTUFF
OUT
IN
OUT
IN
79 89
79
79 89
79
PP1V8_AWAKE
SPKRAMP_D_ADDR
78
0X68
SPKRAMP_E_ADDR
78
0X6A
SPKRAMP_F_ADDR
78
0X6C
SPKRAMP_D
RR705
2.2K
1/20W
201
SPKRAMP_E
PACK_IGNORE=TRUE
SPKRAMP_F
RR734
2.2K
2 1
1/20W
RR765
10K
1/20W
201
5%
MF
5
MF
201
1%
MF
2 1
2 1
102 78 77 75
PP1V8_AWAKE
SPKRAMP_1V8_RESET_L
SPKRAMP_E
I2C_1V8_SPKRAMP_R_SDA
SPKRAMP_E
I2C_1V8_SPKRAMP_R_SCL
SPKRAMP_E
SPKRAMP_INT_L
SPKRAMP_E
SPKRAMP_E_ADDR
7
TDM_1V8_SPKRAMP_R_R2D
SPKRAMP_E
TDM_1V8_SPKRAMP_R_D2R
SPKRAMP_E
TDM_1V8_SPKRAMP_R_FSYNC
SPKRAMP_E
TDM_1V8_SPKRAMP_R_BCLK
SPKRAMP_E
107
107
107
107
75 77 78 80
IN
41
BI
41
IN
6 77 78 80
OUT
I
OUT
IN
IN
SPKRAMP_E
PLACE_NEAR=UR730.C1:6MM
1
CR730
1UF
20%
16V
2
CER-X5R
0201
SPKRAMP_E
PLACE_NEAR=UR730.C1:4MM
1
CR731
0.1UF
10%
25V
2
X5R
0201
SPKRAMP_E
RR730
33
2 1
SPKRAMP_E
PLACE_NEAR=UR730.D2:6MM
1
CR732
1UF
20%
16V
2
CER-X5R
0201
PLACE_NEAR=UR730.E1:10MM
TDM_SPKRAMP_E_D2R_R
201 MF 1/20W 5%
SPKRAMP_E
PLACE_NEAR=UR730.D2:4MM
1
CR733
0 1UF
10%
25V
2
X5R
0201
C3
SDZ*
F3
SDA
F4
SCL
D4
IRQZ
MODE
F2
SDIN
E1
SDOUT
E2
FSYNC
F1
SBCLK
E4
PDMD0
E3
PDMCK0
E5
PDMD1
F5
PDMCK1
AVDD IOVDD
UR730
TAS5770AC0
DSBGA
SPKRAMP_E
GND
PGN
VBAT
VSNS_P
VSNS_N
BST_P
OUT_P
OUT_P
BST_N
OUT_N
OUT_N
AREG
DREG
B2
A3
B3
A
A2
A5 D3
B5
B1
D5
D1
SPKRAMP_E
PLACE_NEAR=UR730.C5:5MM
1
CR734
0.1UF
10%
25V
2
X5R
0201
SPKRAMP_E_BOOTP
MIN_LINE_WIDTH=0.1000
SPKRAMP_E_OUTP_R
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0 1000
SPKRAMP_E_BOOTN
MIN_LINE_WIDTH=0.1000
SPKRAMP_E_OUTN_R
M N_LINE_WIDTH=0.2000
MI _NECK_WIDTH=0 1000
SPKRAMP_E_AREG
SPKRAMP_E_DREG
SPKRAMP_E
PLACE_NEAR=UR730.D1:3 MM
1
CR743
0.1UF
10%
25
2
X5R
0201
SPKRAMP_E
PLACE_NEAR=UR730.C5:10MM
1
CR735
10UF
20%
25V
2
X5R-CERM
0603
BYPASS=UR730.B2:B3:10MM
NO_XNET_CONNECTION=1
CR739
CR740
BYPASS=UR730.A2:A5:10MM
NO_XNET_CONNECTION=1
SPKRAMP_E
PLACE_NEAR=UR730.D1:5 MM
1
CR744
1UF
20%
16V
2
CER-X5R
0201
0.1UF
25V
0.1UF
25V
2 1
0201
0201
2 1
SPKRAMP_E
PLACE_NEAR=UR730.C5:10MM
1
CR736
10UF
20%
25V
2
X5R-CERM
0603
10%
SPKRAMP_E
X5R
* SEE NOTE
10%
SPKRAMP_E
X5R
* SEE NOTE
SPKRAMP_E
PLACE_NEAR=UR730.D5:3 MM
1
CR745
0.1UF
10%
25
2
X5R
0201
RR731
0%
SPKRAMP_E
RR732
0%
MF
SPKRAMP_E
SPKRAMP_E
PLACE_NEAR=UR730.C5:10MM
1
CR737
10UF
20%
25V
2
X5R-CERM
0603
PPBUS_SPKRAMP_RIGHT_ISNS
MAX CURRENT EDC = 4A (PER AMP)
SPKRAMP_E
PLACE_NEAR=UR730.C5:10MM
1
CR738
10UF
20%
35V
2
X5R-CERM
0603
105
AMP E
0
2 1
0603
1/4W MF
0
2 1
0603
1/4W
* SEE NOTE
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
* SEE NOTE
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
SPKRAMP_E
CR741
220PF
X7R-CERM
10%
25V
201
1
2
NOSTUFF
SPKRAMP_E
PLACE_NEAR=UR730.D5:5 MM
1
CR746
1UF
20%
16
2
CER-X5R
0201
SPKRAMP_E_OUTP
SPKRAMP_E
SPKRAMP_E_VSENSEP
* SEE NOTE
SPKRAMP_E
SPKRAMP_E_OUTN
SPKRAMP_E
SPKRAMP_E_VSENSEN
* SEE NOTE
SPKRAMP_E
1
CR742
220PF
10%
25V
2
X7R-CERM
201
SPKRAMP_E
NOSTUFF
OUT
IN
OUT
IN
79 89
79
9 89
9
102 78 77 75
PP1V8_AWAKE
75 77 78 80
IN
BI
IN
6 77 78 80
OUT
78
IN
OUT
IN
IN
SPKRAMP_1V8_RESET_L
PACK_IGNORE=TRUE
SPKRAMP_F
=I2C_1V8_SPKRAMP_F_SDA
PACK_IGNORE=TRUE
SPKRAMP_F
=I2C_1V8_SPKRAMP_F_SCL
PACK_IGNORE=TRUE
SPKRAMP_F
SPKRAMP_INT_L
P CK_IGNORE=TRUE
S KRAMP_F
SPKRAMP_F_ADDR
=TDM_1V8_SPKRAMP_F_R2D
PACK_IGNORE=TRUE
SPKRAMP_F
=TDM_1V8_SPKRAMP_F_D2R
PACK_IGNORE=TRUE
SPKRAMP_F
=TDM_1V8_SPKRAMP_F_FSYNC
PACK_IGNORE=TRUE
SPKRAMP_F
=TDM_1V8_SPKRAMP_F_BCLK
PACK_IGNORE=TRUE
SPKRAMP_F
PACK_IGNORE=TRUE
SPKRA P_F
PLACE_NEAR=UR760.C1:6MM
1
CR760
1UF
20%
16V
2
CER-X5R
0201
PACK_IGNORE=TRUE
SPKRAMP_F
PLACE_NEAR=UR760.C1:4MM
1
CR761
0.1UF
10%
25V
2
X5R
0201
PACK_IGNORE=TRUE
SPKRAMP_F
RR760
33
2 1
PACK_IGNORE=TRUE
SPKRAMP_F
PLACE_NEAR=UR760.D2:6MM
1
CR762
1UF
20%
16V
2
CER-X5R
0201
PLACE_NEAR=UR760.E1:10MM
TDM_SPKRAMP_F_D2R_R
MF 5% 1/20W 201
PACK_IGNORE=TRUE
SPKRAMP_F
PLACE_NEAR=UR760.D2:4MM
1
CR763
0.1UF
10%
25V
2
X5R
0201
C3
SDZ*
F3
SDA
F4
SCL
D4
IRQZ
MODE
F2
SDIN
E1
SDOUT
E2
FSYNC
F1
SBCLK
E4
PDMD0
E3
PDMCK0
E5
PDMD1
F5
PDMCK1
AVDD IOVDD
UR760
TAS5770AC0
DSBGA
PACK_IGNORE=TRUE
SPKRAMP_F
GND
PGND
VBAT
VSNS_P
VSNS_N
BST_P
OUT_P
OUT_P
BST_N
OUT_N
OUT_N
AREG
DREG
B2
A3
B3
A1
A2
A5 D3
B5
B1
D5
D
PACK_IGNORE=TRUE
SPKRAMP_F
PLACE_NEAR=UR760.C5:5MM
1
CR764
0.1UF
10%
25V
X R
0201
SPKRAMP_F_BOOTP
MIN_LINE_WIDTH=0.1000
SPKRAMP_F_OUTP_R
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0 1000
SPKRAMP_F_BOOTN
MIN_LINE_WIDTH=0.1000
SPKRAMP_F_OUTN_R
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0 1000
SPKRAMP_F_AREG
SPKRAMP_F_DREG
PACK_IGNORE=TRUE
SPKRAMP_F
LA E_NEAR=UR760.D1:3 MM
1
CR773
0.1UF
10%
25V
2
X5R
0201
PACK_IGNORE=TRUE
SPKRAMP_F
PLACE_NEAR=UR760.C5:10MM
1
CR765
10UF
20%
25V
2
X5R-CERM
0603
BYPASS=UR760.B2:B3:10MM
NO_XNET_CONNECTION=1
CR769 SPKRAMP_F
CR770 SPKRAMP_F
BYPASS=UR760.A2:A5:10MM
NO_XNET_CONNECTION=1
PACK_IGNORE=TRUE
SPKRAMP_F
LA E_NEAR=UR760.D1:5 MM
1
CR774
1UF
20%
16V
2
CER-X5R
0201
0.1UF
25V
0.1UF
25V
PLACE_NEAR=UR760.C5:10MM
1
2
10%
2 1
0201
X5R
* SEE NOTE
10%
2 1
0201
X5R
* SEE NOTE
PACK_IGNORE=TRUE
SPKRAMP_F
1
2
PACK_IGNORE=TRUE
SPKRAMP_F
CR766
10UF
20%
25V
X5R-CERM
0603
PACK_IGNORE=TRUE
RR761
0%
MF 1/4W
ACK_IGNORE=TRUE
0
PACK_IG ORE=TRUE
SPKRAMP_F
RR762
0%
MF
LA E_NEAR=UR760.D5:3 MM
0
PACK_IGNORE=TRUE
SPKRAMP_F
CR775
0.1UF
10%
25V
X5R
0201
PACK_IGNORE=TRUE
SPKRAMP_F
PLACE_NEAR=UR760.C5:10MM
1
CR767
10UF
20%
25V
X R-CERM
0603
2 1
0603
2 1
0603
1/4W
PACK_IGNORE=TRUE
SPKRAMP_F
LA E_NEAR=UR760.D5:5 MM
1
CR776
1UF
20%
16V
2
CER-X5R
0201
* SEE NOTE
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
* SEE NOTE
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
=PPBUS_AON_F_SPKRAMP
PACK_IGNORE=TRUE
MAX CURRENT EDC = 4A (PER AMP)
SPKRAMP_F
PLACE_NEAR=UR760.C5:10MM
1
CR768
10UF
20%
35V
X5R-CERM
0603
SPKRAMP_F_OUTP
SPKRAMP_F_VSENSEP
SPKRAMP_F_OUTN
SPKRAMP_F_VSENSEN
PACK_IGNORE=TRUE
SPKRAMP_F
CR771
220PF
10%
25V
X7R-CERM
201
1
2
1
2
NOSTUFF
AMP F
* SEE NOTE
* SEE NOTE
PACK_IGNORE=TRUE
SPKRAMP_F
CR772
220PF
10%
25V
X7R-CERM
201
NOSTUFF
PACK_IGNO TRUE
SPKRAMP_F
PACK_IGNORE T E
SPKRAMP_F
PACK_IGNOR TRUE
SPKRAMP_F
PACK_IGNORE TRUE
SPKRAMP_F
OUT
IN
OUT
IN
NOTES:
- VSENSEP/N SIGNALS CONNECT
TO OUTP/N SIGNALS AT THE
SPEAKER CONNECTOR PINS.
- THE FOLLOWING SIGNALS SHOULD
HAVE A VERY LOW DCR PATH:
- SPKRAMP_XX_OUTP/N_R
- SPKRAMP_XX_OUTP/N
- PVDD SUPPLY
- FOR THERMALS PGND PINS MUST
CONNECT TO GND LAYERS USING
COPIOUS AMOUNT OF VIAS.
SYNC_DATE=04/16/2020SYNC_MASTER=REF_SPKRAMP_TAS5770
PAGE TITLE
AUDIO AMPLIFIERS (2/2)
BOM_COST_GROUP=AUDIO
2
1
Page 79
LEFT AUDIO AMP CONNECTOR
w w w . t e k n i s i - i n d o n e s i a . c o m
NO_XNET_CONNECTION=1
XWR800
77
OUT
77
OUT
SPKRAMP_A_VSENSEP
SPKRAMP_A_VSENSEN
NO_XNET_CONNECTION=1
2 1
SM
XWR801
2 1
SM
APN:518S00019
CRITICAL
JR800
FF14A-14C-R11DL-B-3H
F-RT-SM1
16
LEFT AUDIO AMP PBUS BULK CAPS
CKPLUS_WAIVE=CAPDERATE CKPLUS_WAIVE=CAPDERATE
128S0264
1
CR800
68UF
20%
16V
2
POLY-TANT
CASE-D2E-SM
128S0264
1
CR801
68UF
20%
16V
2
POLY-TANT
CASE-D2E-SM
PPBUS_SPKRAMP_LEFT_ISNS
CKPLUS_WAIVE=CAPDERATE
128S0264
1
CR802
68UF
20%
16V
2
POLY-TANT
CASE-D2E-SM
105
102 79
PP1V25_AWAKE_IO
OUT
SPKR_ID0
6 89
NOSTUFF
RR800
47K
5%
1/20W
MF
201
77 89
IN
77 89
IN
77 89
1
2
IN
77 89
IN
SPKRAMP_A_OUTP
SPKRAMP_A_OUTN
SPKRAMP_B_OUTP
SPKRAMP_B_OUTN
NO_XNET_CONNECTION=1
14
13
12
11
10
9
8
7
6
5
4
3
2
1
15
XWR802
77
OUT
SPKRAMP_B_VSENSEP
2 1
SM
XWR803
77
OUT
SPKRAMP_B_VSENSEN
NO_XNET_CONNECTION=1
2 1
SM
1 2 9
PP1V25_AWAKE_IO
OUT
SPKR_ID1
6 89
NOSTUFF
RR850
47K
5%
1/20W
MF
201
RIGHT AUDIO AMP CONNECTOR
NO_XNET_CONNECTION=1
XWR850
78
OUT
78
OUT
78 89
IN
78 89
IN
78 89
1
2
IN
78 89
IN
SPKRAMP_D_VSENSEP
SPKRAMP_D_VSENSEN
NO_XNET_CONNECTION=1
SPKRAMP_D_OUTP
SPKRAMP_D_OUTN
SPKRAMP_E_OUTP
SPKRAMP_E_OUTN
2 1
SM
XWR851
2 1
SM
APN:518S00019
CRITICAL
JR850
FF14A-14C-R11DL-B-3H
F-RT-SM1
16
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RIGHT AUDIO AMP PBUS BULK CAPS
CKPLUS_WAIVE=CAPDERATE CKPLUS_WAIVE=CAPDERATE
128S0264
1
CR850
68UF
20%
16V
2
POLY-TANT
CASE-D2E-SM
CKPLUS_WAIVE=CAPDERATE
128S0264
1
CR851
68UF
20%
16V
2
POLY-TANT
CASE-D2E-SM
128S0264
1
CR852
68UF
20%
16V
2
POLY-TANT
CASE-D2E-SM
PPBUS_SPKRAMP_RIGHT_ISNS
105
NO_XNET_CONNECTION=1
15
XWR852
78
OUT
SPKRAMP_E_VSENSEP
2 1
SM
XWR853
78
OUT
SPKRAMP_E_VSENSEN
NO_XNET_CONNECTION=1
2 1
SM
PAGE TITLE
SY C_DA E=0 /18 2019SYNC_MASTER=KELVIN T668_MLB
A
AUDIO CONNECTORS: AMPS
BOM_COST_GROUP=AUDIO
2
1 6
Page 80
AUDIO JACK FLEX CONNECTOR
w w w . t e k n i s i - i n d o n e s i a . c o m
DIGITAL MIC FLEX CONNECTOR
APN: 516S1064
DMIC_CLK0_1V8_OUT
MATES WITH APN: 516S0573 ON FLEX
JR900
51338-0374
F-ST-SM
32
80 89
80 89
80 89
80 89
80 89
80 89
80 89
33 34 89 90
OUT
18 89
OUT
18 89
OUT
86 89
80 86 89
AUD_CONN_LEFT_OUT
AUD_CONN_SLEEVE
AUD_CONN_RIGHT_OUT
AUD_CONN_RING2
AUD_CONN_RING_SENSE
AUD_CONN_RIGHT_SNS
AUD_CONN_SLEEVE_XW
PMU_ONOFF_L
SPI_TOUCHID_MOSI
SPI_TOUCHID_CLK
PP16V0_TOUCHID_FILT_CONN
PP3V0_TOUCHID_FILT_CONN
MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0 2000
MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0 2000
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
31
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0 1000
AUD_CONN_LEFT_OUT
AUD_CONN_SLEEVE
AUD_CONN_RIGHT_OUT
AUD_CONN_RING2
AUD_CONN_TIP_SENSE
AUD_CONN_LEFT_SNS
AUD_CONN_RING2_XW
PP1V8_TOUCHID_FILT_CONN
TOUCHID_INT_1V8_CONN
SPI_TOUCHID_MISO
TOUCHID_BOOST_EN
PP1V8_AON
AMR_RIGHT_OR_ND_1V8
80 89
80 89
80 89
80 89
80 89
80 89
80 89
OUT
IN
OUT
104
OUT
86 89
86 89
6 86 89
86 89
73 74 89
FF14A-6C-R11DL-B-3H
APN: 518S0818
JR940
F-RT-SM
7
1
2
3
4
5
6
8
AUD_DMIC0_DATA_CONN
89
AUD_DMIC1_DATA_CONN
89
PLACE_NEAR=JR940.2:8MM
PLACE_NEAR=JR940.5:8MM
RR941
0
5%
1/20W
MF
0201
RR943
0
5%
1/20W
MF
0201
2
DMIC_DATA0_1V8_IN
VOLTAGE=1.8V
PP1V8_DMIC
89
DMIC_CLK1_1V8_OUT
2 1
DMIC_DATA1_1V8_IN
IN
OUT
I
OUT
74 89
4
4 9
74
LR940
FERR-470-OHM
0201
1
CR940
1UF
20%
16V
2
CER-X5R
0201
2 1
PP1V8_S2
101
80 86 89
PP3V0_TOUCHID_FILT_CONN
1
CR990
100PF
5%
50V
2
C0G
0201
1
CR991
100PF
5%
50V
2
C0G
0201
MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0 2000
1
CR992
100PF
5%
2
C0G
0201
1
CR993
100PF
5%
50V 50V
2
C0G
0201
34
33
1
CR994
100PF
5%
2
C0G
0201
1
CR995
100PF
5%
50V 50V
2
C0G
0201
1
CR996
100PF
5%
50V
2
C0G
1
CR997
100PF
5%
50V
2
C0G
0201 0201
ESD:PROJECT DEPENDENT
CODEC_RESET_L
NOSTUFF
1
CR900
1000PF
10%
25V
2
X7R
CRITICAL
0201
FLR901
120-OHM-25%-1.3A
76
IN
AUDIO_JACK_LEFT_OUT
0402
2 1
CRITICAL
AUD_CONN_LEFT_OUT
80 89
FLR902
120-OHM-25%-1.3A
76
IN
AUDIO_JACK_RIGHT_OUT
CRITICAL
0 2
2 1
AUD_CONN_RIGHT_OUT
80 89
FLR903
120-OHM-25%-1.3A
76
OUT
76
OUT
AUDIO_JACK_GB_GND AUD_CONN_RING2
0402
AUDIO_JACK_CH_GND
CRITICAL
FLR905
120-OHM-25%-1.3A
76
OUT
76
OUT
AUDIO_JACK_LEFT_SNS
0402
AUDIO_JACK_RIGHT_SNS
LR907
FERR-470-OHM
76
OUT
AUDIO_JACK_TIP_SNS
0201
2 1
CRITICAL
FLR904
120-OHM-25%-1.3A
2 1
0402
2 1
CRITICAL
FLR906
120-OHM-25%-1.3A
2 1
0402
2 1
LR908
AUD_CONN_SLEEVE
AUD_CONN_LEFT_SNS
AUD_CONN_RIGHT_SNS
AUD_CONN_TIP_SENSE
80 89
80 89
80 89
80 89
80 89
TPR901
A
TPR902
A
1
TP P5
1
TP-P5
TPR903
A
TP-P5
TPR904
A
TPR905
A
TPR906
A
TPR907
A
1
TP-P5
1
TP P5
1
TP-P5
1
TP-P5
SPKRAMP_INT_L
TDM_1V8_SPKRAMP_L_BCLK
PLACE_NEAR=UR600.F1:20MM
TDM_1V8_SPKRAMP_L_FSYNC
PLACE_NEAR=UR600.E2:20MM
TDM_1V8_SPKRAMP_L_R2D
PLACE_NEAR=UR600.F2:20MM
TDM_1V8_SPKRAMP_L_D2R
PLACE NEAR SOC PLACE NEAR SOC
I2C_1V8_SPKRAMP_L_SCL
I2C_1V8_SPKRAMP_L_SDA
FERR-470-OHM
76
OUT
AUDIO_JACK_RING_SNS
CRITICAL
0201
2 1
AUD_CONN_RING_SENSE
80 89
FLR909
120-OHM-25%-1.3A
76
OUT
AUDIO_JACK_GB_MIC
0402
2 1
CRITICAL
AUD_CONN_SLEEVE_XW
80 89
FLR910
120-OHM 25%-1.3A
76
OUT
AUDIO_JACK_CH_MIC
0402
2 1
AUD_CONN_RING2_XW
80 89
IN
9 76
TPR900
6 77 78 75 7 78
A
TPR920
107 7
A
TPR921
107 77
A
TPR922
107 77
A
TPR923
107 77
A
TPR924
77 4
A
TPR925
77 41
A
TP-P5
TP-P5
TP-P5
TP-P5
TP-P5
TP-P5
TP-P5
1
1
PLACE_NEAR=UR700.F1:20MM
1
PLACE_NEAR=UR700.E2:20MM
1
PLACE_NEAR=UR700.F2:20MM
1
1
1
SPKRAMP_1V8_RESET_L
TDM_1V8_SPKRAMP_R_BCLK
TDM_1V8_SPKRAMP_R_FSYNC
TDM_1V8_SPKRAMP_R_R2D
TDM_1V8_SPKRAMP_R_D2R
I2C_1V8_SPKRAMP_R_SCL
I2C_1V8_SPKRAMP_R_SDA
107 78
107 78
107 78
107 78
78 41
78 41
PAGE TITLE
AUDIO CONNECTORS: DMIC, JACK
A
NC TE C M TE EV N T M
BOM_COST_GROUP=AUDIO
2
1
Page 81
518S0818
w w w . t e k n i s i - i n d o n e s i a . c o m
FF14A-6C-R11DL-B-3H
NC
NC
89
KBDLED_CATHODE1_R
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
JT000
F-RT-SM
7
2
4
5
6
8
518S00116
JT002
FF14A-10C-R11DL-B-3H
F-RT-SM1
11
PPVOUT_KBDLED
104
1
CT059
2.2UF
10%
2
50V
X5R
0603
1 CT055
001UF
1 %
2
50V
X7R-CERM
0402
RT046
0
5%
1/16W
MF-LF
402
2 1
PPVOUT_S0_KBDLED_CONN
89
MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.2000
VOLTAGE=40V
1
2
72 89
72 89
KBDLED_CATHODE1
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
KBDLED_CATHODE2
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
NC
NC
89
KBDLED_CATHODE2_R
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
3
4
5
6
7
8
9
10
12
5 8S0818
FF14A-6C-R11DL-B-3H
NC
NC
JT001
F-RT-SM
7
1
2
3
4
5
8
SYNC_DATE=05/16/2019 SYNC_MASTER=T668_MLB
PAGE TITLE
KEYBOARD BLC CONNECTORS
BOM_COST_GROUP=DISPLAY
Page 82
*** OK2PLACE ***
w w w . t e k n i s i - i n d o n e s i a . c o m
6
TO/FROM TRACKPAD
RT110
33
82 85 89 117
IN
I2C_KBD_SCL
PLACE_NEAR=JT400.8:10MM
DZT110
5.5V-0.28PF
0201-THICKSTNCL
82 85 89 117
BI
I2C_KBD_SDA
PLACE_NEAR=JT400.9:10MM
DZT111
5.5V-0.28PF
0201-THICKSTNCL
2 1
2
1
RT111
2 1
2
1%
1/20W
MF
201
33
1%
1/20W
MF
201
CKPLUS_WAIVE=I2C_PULLUP
IOXP_I2C_SCL
CKPLUS_WAIVE=I2C_PULLUP
IOXP_I2C_SDA
105 82
TIE TO SAME VOLTAGE AS TPAD
CONTROLLER, EITHER 1V8 OR 3V3
PP1V85_S2_KBD_ISNS
IOX1 DOESN'T SEND THE INTERRUPT
INSTEAD, IOX2 SENDS INT WHEN
A KEY IS PRESSED
IOXP1_INT_L
82
2
IOXP1_RESET_L
1
CT111
0.1UF
10%
6 3V
2
CERM-X5R
0201
132S0444
1
CT110
1.0UF
6.3V
2
X5R
0201-1
138S0692
KEYBAORD IOX1
1 22
2
3
4
5
6
7
8
10
11
12
13
14
15
16
17
18
19
20
24
INT*
ADDR
SCL
SDA
RESET*
PCAL6416A
WRITE: 0X40
READ: 0X41
UT101
HWQFN
311S0665
P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
P0_6
P0_7
P1_0
P1_1
P1_2
P1_3
P1_4
P1_5
P1_6
P1_7
ALL PLATFORMS CONNECT TO 1V8
PP1V85_S2_KBD_ISNS
1
CT112
0.1UF
10% 20%
6.3V
2
CERM-X5R
0201
132S0444
1
CT113
0.1UF
10%
6.3V
2
CERM-X5R
0201
132S0444
KBD_DRIVE_Y0
KBD_DRIVE_Y1
KBD_DRIVE_Y2
KBD_DRIVE_Y3
KBD_DRIVE_Y4
KBD_DRIVE_Y5
KBD_DRIVE_Y6
KBD_DRIVE_Y7
KBD_DRIVE_Y8
RT144
HW_ID1
NC
2 1
1/20W
1%
BOMOPTION=KBD_NEW
NC
NC
KBD_ID_DETECT1
CAPSLOCK_LED_EN
MF
1K
201
1
CT114
10UF
20%
10V
2
X5R-CERM
0402-7
IN
IN
IN
IN
IN
IN
IN
IN
IN
83 89
83 89
83 89
83 89
83 89
83 89
83 89
83 89
83 89
82
82
105 83 82
ADD NEW IO FOR KBD_DRIVE_Y8
FOR J293/313/314/316 AND AFTER
CONNECT THE DRIVE_Y8 TO ESD
ADD HW ID PIN STRAPPING
STUFF FOR NEW KBD MATRIX
NOSTUFF FOR OLD KBD MATRIX
104 82
105 3
3.3V RSLOC ISOLATION KEYS/ASIC RESET
PP3V3_AON
PP1V85_S2_KBD_ISNS
OUT123_EN
83 89
IN
IN
83 89
IN
KBD_RIGHT_SHIFT_KEY
KBD_LEFT_OPTION_KEY
KBD_CONTROL_KEY
PLACE_NEAR=UT103.10:5MM
1
CT150
1.0UF
20%
6.3V
2
X5R
0201-1
138S0692
1
RT190
0
5%
1/20W
MF
2
IN_X:
VIH_MIN 2.0V
VIL_MAX 0.8V
100K IPD
4
OE
1
IN 1
2
IN 2
3
IN 3
PLACE_NEAR=UT103.10:2MM
1
CT151
0.1UF
10%
6.3V
2
CERM-X5R
0201
132S0444
SLG4AP4815V
343S00073
(2.97 < VDD < 3.63)
VDD
UT103
TQFN 0201
GND EPAD
OUT_X:
VOH_MIN 2.4V
VOL_MAX 0.4V
12.5K IPU OE
OUT 1
OUT 2
OUT 3
OUT_ALL#
(OD)
(OD)
(OD)
(OD)
9
KBD_RIGHT_SHIFT_L
8
KBD_LEFT_OPTION_L
7
KBD_CONTROL_L
6
RSLOC_RST_L
RT152
33
1%
1/20W
MF
201
82
82
82
2 1
PMU_RSLOC_RST_L
OUT
33 34 89 90
85 89
OUT
KBD_INT_L
PLACE_NEAR=JT400.9:10MM
DZT112
5.5V-0.28PF
0201-THICKSTNCL
PP1V85_S2_KBD_ISNS
1
RT112
2 1
2
1
33
1%
1/20W
MF
201
IOXP2_INT_L
105 83 82
105 82
TIE TO SAME VOLTAGE AS TPAD
CONTROLLER, EITHER 1V8 OR 3V3
PP1V85_S2_KBD_ISNS
1
RT121
100K
5%
1/20W
MF
201
2
IOXP2_ADDR
2
82
O P2_RESET_L
1
CT123
0.1UF
10%
6.3V
2
CERM-X5R
0201
132S0444
1
CT120
1.0UF
20%
6.3V
2
X5R
0201-1
138S0692
18
19
20
24
INT*
ADDR
SCL
SDA
RE ET*
PCAL6416A
WRITE: 0X42
READ: 0X43
UT102
HWQFN
311S0665
P0_0
P0_1
P0_2
P0_3
P0_4
P0 5
P0_6
P0_7
P1_0
P1_1
P1_2
P1_3
P1_4
P1_5
P1_6
P1_7
1
CT121
0.1UF
10% 10%
6.3V
2
CERM-X5R
0201
132S0444
1 22
KBD_SENSE_X0
2
KBD_SENSE_X1
3
KBD_SENSE_X2
4
KBD_SENSE_X3
5
KBD_SENSE_X4
6
KBD_SENSE_X5
7
KBD_SENSE_X6
8
KBD_SENSE_X7
10
KBD_SENSE_X8
11
KBD_SENSE_X9
12
KBD_SENSE_X10
13
KBD_SENSE_X11
14
KBD_SENSE_X12
15
KBD_CONTROL_L
16
KBD_LEFT_OPTION_L
17
KBD_RIGHT_SHIFT_L
1
2
ALL PLATFORMS CONNECT TO 1V8KEYBAORD IOX2
PP1V85_S2_KBD_ISNS
CT122
0.1UF
10V
X5R-CERM
0201
82 83 89
IN
82 83 89
IN
82 83
IN
82 83 89
IN
82 83 89
IN
82 83 89
IN
82 83 89
IN
82 83 89
IN
82 83 89
IN
82 83 89
IN
82 83 89
IN
82 83 89
IN
82 83 89
IN
82
82
82
105 83 82
RT130
RT131
RT132
RT133
RT134
RT135
RT136
RT137
RT138
RT139
RT140
RT141
RT142
RT143
RT120
RT122
RT123
RT124
RT125
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
1K
2 1
2 1
2 1
2 1
2 1
2 1
2 1
2 1
2 1
2 1
2 1
2 1
2 1
2 1
1/20W
5% 201 MF
1/20W 5% 201
1/20W MF 5% 201
1/20W
1/20W
1/20W MF 201 5%
1/20W 201 MF 5%
1/20W MF 201 5%
1/20W
1/20W
PP1V85_S2_KBD_ISNS
10K
10K
1.3K
1 3K
100K
2 1
2 1
2 1
2 1
1/20W
2 1
1/20W MF 201 1%
MF
MF 201 5%
MF 5% 201
201 1/20W F 5%
201 1/20W MF 5%
MF 201 1/20W 5%
MF
201 5%
MF 201 1/20W 5%
201 MF 1%
201 5% 1/20W MF
201 1/20W 5%
MF
201 MF 1%
201 MF 1/20W 5%
KBD_SENSE_X0
KBD_SENSE_X1
KBD_SENSE_X2
KBD_SENSE_X3
KBD_SENSE_X4
KBD_SENSE_X5
KBD_SENSE_X6
KBD_SENSE_X7
KBD_SENSE_X8
KBD_SENSE_X9
KBD_SENSE_X10
KBD_SENSE_X11
KBD_SENSE_X12
IOXP2_ADDR
105 82
IOXP2_RESET_L
IOXP1_RESET_L
I2C_KBD_SCL
I2C_KBD_SDA
IOXP1_INT_L
82 83 89
82 83 89
82 83 89
82 83 89
82 83 89
82 83 89
82 83 89
82 83 89
82 83 89
82 83 89
82 83 89
82 83 89
82 83 89
82
2
82
82 85 89 117
82 85 89 117
82
104 82
3V3 KBD CONN SERIES R
PP3V3_AON
KBD DRI REQUEST, TO MEASURE CAPSLOCK LED CURRENT
RT103
0
5%
1/20W
MF
0201
TO KBD CONN AND ESD
2 1
PP3V3_AON_KBD_CONN
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000
VOLTAGE=3.3V
NOTE: THIS CAN BE THE SAME RAIL AS
THE CAPSLOCK LED, OR IT CAN BE A RAIL
THAT COMES UP AFTER
PP3V3_S2
104
1
CT105
1.0UF
20%
6.3V
2
X5R
0201-1
138S0692
RT161
1K
5%
MF
201
2 1
RT162
200K
5%
1/20W
MF
201
1
2
CAPSLOCK_LED_EN
82
1/20W
83
CAPSLOCK LED DRIVER
CURRENT CONTROLLED LED DRIVING FROM J214/J223/J230
DIFFERENT FROM RESISTANCE CONTROL LED DRIVING FROM J152
VIN
UT105
VIH_MIN 1.2V
VIL_MAX 0.4V
LED_CTRL
LED_ISET
<R_SET>
RT160
19.1K
1%
1/20W
MF
201
FAN5622
1
CTRL
5
ISET
1
2
SSOT23
LED1
LED2
GND
PAGE TITLE
R_SET 19.1K
15 MA SINK
6
KBD_LED1 KBD_CAP_CATHODE
4
RT118
1.00
1%
1/20W
MF-LF
0201
2 1
SYNC_DATE=02/01/2020 SYNC_MASTER=REF_KBD_SUPPORT
IN
83 89
A
ID_DETECT SERIES R
KEYBOARD IOX, SUPPORT
RT117
1K
2 1
82
5%
1/20W
MF
201
KBD_ID1 KBD_ID_DETECT1
KBD_ID PIN ON KBD CONNECTOR
ANSI: NO CONNECT
ISO: TIED HIGH TO PP1V8
JIS: TIED LOW TO GND
IN
83 89
BOM_COST_GROUP=KEYBOARD
2
1 5 4
Page 83
KEYBOARD ESD
w w w . t e k n i s i - i n d o n e s i a . c o m
DZT202
PESD3V3L5UF
SOT886
82 83 89 82 83 89
BI
82 83 89
BI
KBD_CAP_CATHODE KBD_DRIVE_Y0
KBD_DRIVE_Y5
1
6
5
KBD_DRIVE_Y6
4 3
KBD_DRIVE_Y7
BI
BI
I
82 83 89
82 83 89
DZT203
PESD3V3L5UF
SOT886
82 83 89
BI
1
6
KBD_SENSE_X7
BI
82 83 89
DZT201
PESD3V3L5UF
SOT886
NC
82 83 89
PP3V3_AON_KBD_CONN
1
6
KBD_CONTROL_KEY
KBD_LEFT_OPTION_KEY
4 3
KBD_RIGHT_SHIFT_KEY
BI
BI
BI
83 89
82 83 9
82 83 89
BI
82 83 89
BI
KBD_SENSE_X9
1
DZT206
PESD3V3L5UF
SOT886
82 83 89
BI
KBD_DRIVE_Y4
1
6
KBD_DRIVE_Y3
BI
82 83 89
82 83 89
BI
KBD_SENSE_X3 KBD_SENSE_X8
1
DZT204
PESD3V3L5UF
SOT886
DZT205
PESD3V3L5UF
SOT886
6
5
4 3
6
KBD_SENSE_X11 KBD_SENSE_X10
KBD_SENSE_X4
KBD_SENSE_X12
KBD_SENSE_X5
BI
BI
BI
BI
82 83 89 82 83 89
82 83 89
82 83 89
82 83 89
5
KBD_SENSE_X6
4 3
82 83 89
BI
KBD_DRIVE_Y8
KBD_ID1
BI
BI
82 83 89
82 83 89
82 83 105
BI
PP1V85_S2_KBD_ISNS
5
KBD_DRIVE_Y1
4 3
KBD_DRIVE_Y2
BI
BI
82 83 89
82 83 89
82 83 89
BI
KBD_SENSE_X0
5
KBD_SENSE_X2
4 3
KBD_SENSE_X1
BI
BI
82 83 89
82 83 89
MEMBRANE ZIF CONNECTOR
105 83 2
82 83 89
82 83 89
82 83 89
82 83 89
82 83 89
82 83 89
82 83 8
82 89
82 83 89
82 83 89
82 83 89
82 83 89
82 83 89
82 83 89
82 83 89
82 83 8
82 89
82 83 89
82 83 89
82 83 89
82 83 89
82 83 89
82 83 89
82 83 89
82 83 8
82 89
518S0752
CRITICAL
FF14A-30C-R11DL-B-3H
JT200
F-RT-SM
31
PP1V85_S2_KBD_ISNS
BI
BI
BI
BI
BI
BI
BI
BI
2 83 89
BI
BI
B
BI
BI
BI
BI
BI
BI
BI
2 83 89
BI
BI
B
BI
BI
BI
BI
BI
BI
BI
KBD_ID1
KBD_DRIVE_Y8
KBD_DRIVE_Y2
KBD_DRIVE_Y1
KBD_DRIVE_Y3
KBD_DRIVE_Y4
KBD_SENSE_X0
KBD_SENSE_X1
KBD_SENSE_X2
KBD_SENSE_X5
KBD_SENSE_X3
KBD_SENSE_X9
KBD_SENSE_X12
KBD_SENSE_X4
KBD_SENSE_X11
KBD_SENSE_X10
KBD_SENSE_X6
KBD_SENSE_X7
KBD_SENSE_X8
KBD_DRIVE_Y5
KBD_DRIVE_Y7
KBD_DRIVE_Y6
KBD_DRIVE_Y0
KBD_CAP_CATHODE
PP3V3_AON_KBD_CONN
KBD_RIGHT_SHIFT_KEY
KBD_LEFT_OPTION_KEY
KBD_CONTROL_KEY
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
32
BOM_COST_GROUP=KEYBOARD
SYNC_DATE=01/28/2020 SYNC_MASTER=WUDI_T668_MLB
PAGE TITLE
KEYBOARD SIGNAL CONNECTOR, ESD
2
1
Page 84
TRACKPAD SPI BUS LEVEL SHIFTER (+1.2V TO +1.8V)
w w w . t e k n i s i - i n d o n e s i a . c o m
102 84
18
18
PP1V25_AWAKE_IO
BYPASS=UT360::5MM
47K
5%
MF
201
1
2
SPI_IPD_CS_L
SPI_IPD_CLK
SPI_IPD_MOSI
RT303
1/20W
6
IN
IN
IN
CT360
0.1UF
CERM-X5R
RT304
20
6
OUT
SPI_IPD_MISO
RT377
1/20W
1
47K 47K
5%
MF
201
2
1/20W 5% MF 201
PLACE NEAR=UT360.5:2MM
2 1
RT379
SPI_IPD_MISO_R
47K
5%
1/20W
MF
201
1
2
RT378
1/20W
201
10%
6.3V
0201
5%
MF
1
2
VCCB VCCA
UT360
SN74AVC4T774-COMBO
1
A1
15
DIR1
2
A2
16
DIR2
3
A3
5
DIR3
4
A4
6
DIR4
7
OE*
1
2
QFN
311S00129
GND
B1
B2
B3
B4
12
11
10
9
BYPASS=UT360::5MM
1
CT361
0.1UF
10%
6.3V
2
CERM-X5R
0201
SPI_TPAD_CS_CONN_L
SPI_TPAD_CLK_CONN_R
SPI_TPAD_MOSI_CONN_R
SPI_TPAD_MISO_CONN
NOSTUFF
RT361
100K
5%
1/20W
MF
201
RT374
100K
1/20W
1
2
5%
MF
201
NOSTUFF
RT362
1
2
1
100K
5%
1/20W
MF
201
2
RT371
100K
5%
1/20W
MF
201
NOSTUFF
RT363
100K
1/20W
1
RT372
2
1
5%
MF
201
2
100K
5%
1/20W
MF
201
RT373
100K
1/20W
RT375
1/20W205% MF 201
PLACE_NEAR=UT360.11:2MM
RT376
PLACE_NEAR=UT360.10:2MM
1
2
1
5%
MF
201
2
20
5% 1/20W 201
2 1
2 1
MF
PP1V85_S2_IPD
SPI_TPAD_CLK_CONN
SPI_TPAD_MOSI_CONN
OUT
OUT
OUT
IN
104 84
85 89
85 89
85 89
85 89
SN74AVC4T774 Truth Table
CTRL INPUTS
/OE
L
L
H
DIR
L
H
X
OUTPUT CIRCUITS
A PORT
Enabled
Hi-Z
Hi-Z
B PORT
Hi-Z
Enabled
Hi-Z
OPERATION
B data to A data
A data to B data
Isolation
101
84
PP3V8_AON
IPD_PWR_EN_GATE
IPD LDO
1.85 V FOR TRACKPAD AND KEYBOARD IOX
LOAD CAP:3.2UF NOM
EDP:0.42 A
PP1V85_S2_IPD
1CT303
2.2UF
20%
2
6.3V
X5R-CERM
0201
1
CT301
1UF
10%
10V
2
X5R-CERM
0402
BYPASS=UT301.4::3MM
IPD_P1V8_PWR_EN_RC
RT301
255K
2 1
1%
1/20W
MF
201
UT301
SCY99258
4
3
XDFN-COMBO-THICKSTNCL
IN
EN
353S01993
GND E AD
OUT
1
1 CT302
1UF
10%
2
10V
X5R-CERM
0402
BYPASS=UT301.1::3MM
TRACKPAD SPI ENABLE LEVEL SHIFTER
102 84
104 84
6
IN OUT
PP1V25_AWAKE_IO
IPD_SPI_EN
RT352
47K
5%
1/20W
MF
201
BYPASS=UT355::5MM
10%
6.3V
0201
1
SON
GND
VCC_B
4 2
B
2
NC
VCC_A
UT355
N74AUP1T34-COMBO
A
5
NC
311S0 177
CT355
0.1UF
CERM-X5R
1
2
BYPASS=UT355::5MM
1
CT356
0.1UF
10%
6.3V
2
CERM-X5R
0201
1
2
PP1V8_AWAKE
NOSTUFF
1
RT354
100K
5%
1/20W
MF
201
2
SPI_TPAD_EN_CONN
RT353
100K
5%
1/20W
MF
201
102
85 9
101
84
NOSTUFF
47K
5%
MF
201
1
2
RT399
1/20W
PP3V8_AON
IPD_PWR_EN_GATE
RT398
1K
2 1
IPD_PWR_EN_RES
5%
1/20W
MF
201
CT390
1.0UF
0201-1
NSR01L30MXT5G-COMBO
1
20%
6.3V
2
X5R
DT302
X3DFN2
K A
37 S00062
RT396
DT301
X3DFN2
K A
NSR01L30MXT5G-COMBO
371S00062
1
CT304
0.01UF
10%
25V
2
X5R-CERM
0201
3.3V S2 LDO FOR TPAD
UT390
IPD_PWR_EN_D
470K
1/20W
5%
MF
201
2 1
IPD_P3V3_PWR_EN_RC
RT397
1K
2 1
5%
1/20W
MF
201
1
CT392
0.01UF
10%
25V
2
X5R-CERM
0201
TLV70733PDQN
4
IN
ALLOW_APPLE_PREFIX=U
3
EN
DQN
353S3332
GND
THRM
PAD
OUT
150mA max
+/-1.5% DC max error
1
1
CT391
1.0UF
20%
6.3V
2
X5R
0201-1
PP3V3_S2_TPAD
IPD SPI INTERRUPT LEVEL SHIFTER
106
102
PP1V25_S2
IPD_SPI_INT_L
1
RT380
10K
5%
1/20W
MF
2
NC
VCC
UT380
74AUP1G07GF
SOT891
4
Y A
5
NC NC
GND
1
CT380
0.1UF
10%
6.3V
2
CERM-X5R
0201
2
1
NC
PP1V8_S2
1
RT381
100K
5%
1/20W
MF
201 20
2
SPI_TPAD_INT_CONN_L
OPEN DRAIN AT TPAD MCU
101
85 89
IN OUT
AND GATE FOR IPD_PWR_EN
PP1V8_AON
89 104
104
UT311
6
33 34 37
IN
33 34 92
IN
P5VS2_PWR_EN_RC
IPD_PWR_EN
2
B
1
A
NC
NC
74LVC1G08FW5
DFN1010
4
Y
3
IPD_PWR_EN_GATE
RADAR:61370457 J293 ANG GATE FOR IPD_PWR_EN AND 5VS2_EN
NOSTUFF
RT311
0
2 1
5%
1/20W
MF
0201
PLACE_NEAR=UT311.6:5MM
1
CT311
0.1UF
10%
6.3V
2
CERM-X5R
0201
84
SYNC_DATE=04/16/2020 SYNC_MASTER=WUDI_T668_MLB
PAGE TITLE
TRACKPAD SUPPORT
BOM_COST_GROUP=TRACKPAD
2
1
Page 85
MATES WITH 518S00080 ON TRACKPAD FLEX
w w w . t e k n i s i - i n d o n e s i a . c o m
516S00187
JT400
DF40C-50DS-0.4V-51
F-ST-SM
43
IN
43 34 89
BI
82 89
OUT
82 89 117
BI
82 89 117
101
I2C_SMC_IPD_1V8_SCL
I2C_SMC_IPD_1V8_SDA
KBD_INT_L
I2C_KBD_SDA
I2C_KBD_SCL
PPBUS_AON
2 1
4 3
6 5
8 7
10 9
12 11
14 13
16 15
18 17
20 19
22 21
24 23
26 25
28 27
30 29
32 31
34 33
36 35
38 37
40 39
42 41
44 43
46 45
48 47
50 49
IPD_LID_OPEN_1V8
TPAD_KBD_WAKE_L
SPI_TPAD_INT_CONN_L
SPI_TPAD_MOSI_CONN
SPI_TPAD_CS_CONN_L
SPI_TPAD_MISO_CONN
SPI_TPAD_EN_CONN
SPI_TPAD_CLK_CONN
PP5V_S2_TPAD_CONN
89
VOLTAGE=5
PP1V85_S2_TPAD_ISNS
PP3V3_S2_TPAD_ISNS
IN
OUT
OUT
IN OUT
IN
OUT
I
IN
33 73 87 89
84 89
84 89
84 89
84 89
84 89
84 89
105
105
CT400
0.1UF
10%
25V
X5R
402
LT400
FERR-120-OHM-1.5A
0402A
1
2
2 1
PP5V_S2_TPAD_ISNS
105
ACT_GND
89
XWT401
SM
2 1
SYNC_DATE=04/16/2020 SYNC_MASTER=WUDI_T668_MLB
PAGE TITLE
TRACKPAD CONNECTOR
BOM_COST_GROUP=TRACKPAD
Page 86
*** OK2INTEGRATE ***
w w w . t e k n i s i - i n d o n e s i a . c o m
105 86
PP3V8_MESA_ISNS
PLACE_NEAR=UT600:5MM
LT601
1.0UH-0.4A-0.636OHM
2 1
0402
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=16V
PP16V0_TOUCHID_SW
DIDT=TRUE
TOUCHID POWER SEQUENCING REQUIREMENTS
POWER ON: 1V8 -> 3V3 -> 16V0
16V BOOST
LOAD CAP:6.6UF NOM
EDP:13.75MA
UT600
1
CT625
2.2UF
20%
25V
2
X5R
0402-3
B1
A2
SW
VIN
LM3638A0
BGA
VOUT
C3
1
CT624
2.2UF
20%
25V
2
X5R
0402-3
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=16V
1
CT626
56PF
5%
25V
2
NP0-C0G
0201
EMC FILTER
FLT600
80-OHM-25%-500MA
BYPASS=UT600.C3::4MM
BYPASS=UT600.C3::4MM
BYPASS=UT600.C3::5MM
0201
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=16V
2 1
PP16V0_TOUCHID_FILT_CONN PP16V0_TOUCHID
1
CT627
100PF
5%
25V
2
C0G
0201
OUTPUT VOLTAGE
80 8
16.0V +/- 2%
105 86
BYPASS=UT600.A2::3MM
CT610
CERM-X5R
PP3V8_MESA_ISNS
1
CT611
1.0UF
20%
6.3V
2
X5R
0201-1
BYPASS=UT610.4::3MM
10UF
20%
6.3V
0402-9
1
2
PP1V8_TOUCHID
86
B2
EN_M
80 89
IN
TOUCHID_BOOST_EN
1
RT620
100K
5%
1/20W
MF
201
2
3.0V LDO
UT610
NCP160AMX300
4
IN
3
EN
353S00599
XDFN-COMBO-THICKSTNCL
EPAD GND
A3
C2
EN_S
LDOIN
OUT
PMID
AGND PGND
C1
353S00671
VOLTAGE=17V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=3V
LOAD CAP:14.3UF NOM
EDP:100MA
1
PP3V0_TOUCHID
BYPASS=UT610.1::3MM
CT616
1.0UF
20%
6.3V
2
X5R
0201-1
PP17V0_LDOIN
1
CT623
2.2UF
20%
25V
2
X5R
0402-3
1
CT620
2.2UF
20%
6.3V
2
X5R-CERM
0201
1
CT621
2.2UF
20%
6.3V
2
X5R-CERM
0201
EMC FILTER
FLT610
80-OHM-25%-500MA
0201
1
CT622
2.2UF
20%
6.3V
2
X5R-CERM
0201
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=3V
2 1
1
CT628
0.1UF
10%
6.3V
2
CERM-X5R
0201
PP3V0_TOUCHID_FILT_CONN
1
CT629
100PF
5%
25V
2
C0G
0201
IOUT (MAX AVG)
OCP (MIN)
ACTIVE DISCHARGE
MAX OUTPUT CAP
OUTPUT VOLTAGE
DROPOUT VOLTAGE
6MA
13 MA
15 MA SINK
0.5UF @ 16V
80 89
3.0V +/- 2%
250MA IOUT (MAX AVG)
155MV
105 86
PP3V8_MESA_ISNS
1
CT612
1.0UF
20%
6.3V
2
X5R
0201-1
BYPASS=UT620.4::3MM
PP1V25_S2
102
47K
1%
MF
201
1
2
RT610
1/20W
6 94
UT620 CHANGED FROM 353S00754 TO 353S02212 FOR 1.2V EN SIGNAL SUPPORT.
TOUCHID_PWR_EN
IN
1.85 V LDO
UT620
SCY99217AMX185TBG
IN OUT
3
EN
X2DFN
353S02314
EPAD
GND
OCP (MIN)
ACTIVE DISCHARGE
250 MA
280 OHM TYP
LOAD CAP:3.4UF NOM
EDP:0.5MA
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
1 4
BYPASS=UT620.1::3MM
1
CT614
1.0UF
20%
6.3V
2
X5R
0201-1
BYPASS=UT620.1::3MM
20%
6.3V
0201
1
2
CT618
2.2UF
X5R-CERM
VOLTAGE=1.8V
EMC FILTER
FLT620
80-OHM-25%-500MA
2 1
PP1V8_TOUCHID_FILT_CONN
0201
PP1V8_TOUCHID
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
VOLTAGE=1.8V
1
CT617
100PF
5%
25V
2
C0G
0201
86
80 89
OUTPUT VOLTAGE
IOUT (MAX AVG)
DROPOUT VOLTAGE
OCP (MIN)
ACTIVE DISCHARGE
MIN OUTPUT CAP
1.825 V +/- 2%
250 MA
75MV TYP @ 100MA
250 MA
280 OHM TYP
1.0 UF
RT650
TOUCHID_INT_1V8_CONN
IN OUT
665
1/20W
1%
MF
201
2 1
1
RT651
1.33K
1%
1/20W
MF
201
2
TOUCHID_INT
6 80 89
6 80 89
BI
SPI_TOUCHID_MISO
1RT641
100K
5%
1/20W
MF
201
2
A
PAGE TITLE
TOUCHID SUPPORT
BOM_COST_GROUP=TOUCH ID
2
1 8
Page 87
33 73
w w w . t e k n i s i - i n d o n e s i a . c o m
IN
85 89
PP5V_S2
104
**OK2INTEGRATE** DFR V3 SUPPORT
IPD_LID_OPEN_1V8
1.2UH-20%-0.12A-1.17OHM
PP1V8_AWAKE_DFR
41 87 88 89
RT702
100K
2 1
5%
1/20W
MF
201
LT700
0402
IPD_LID_OPEN_1V8_R
RT706
100K
5%
1/20W
MF
201
2 1
4.7UF
20%
25V
X5R
0402
2
S
QT700
1
G
D
3
DFR_LID_OPEN_L
89
89
1
88 89
IN
88 89
IN
2
41
IN
41
BI
6 88 89
IN
41 87 88 89
1CT700
2
TP_DFR_TOUCH_RSVD
SPI_1V8_DFR_CS_L
SPI_1V8_DFR_MOSI
I2C_DFR_RES_SCL
I2C_DFR_RES_SDA
DFR_1V8_TOUCH_RESET_L
PP1V8_AWAKE_DFR
PP5V_S2_DFR_FILT
89
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000
VOLTAGE=5V
DMP31D0UFB4
DFN1006H4-3
4.7UF
DFR TOUCH CONN
JT700
AA07-S022VA1
20%
25V
X5R
0402
F-ST-SM
2 1
4 3
6 5
8 7
10 9
12 11
14 13
16 15
18 17
20 19
22 21
1CT701
2
24
2
25
26
TP_DFR_TOUCH_PANEL_DETECT
DFR_DISP_VSYNC
SPI_1V8_DFR_MISO
SPI_1V8_DFR_CLK
DFR_1V8_TOUCH_INT_L
DFR_1V8_TOUCH_CLK32K_RESET_L
TP_DFR_TOUCH_ROM_WC
PP1V8_AWAKE_DFR
NOSTUFF
BYPASS=JT700.21::5MM
1
CT706
0.1UF
10%
6.3V
2
X5R
0201
9
87 8
88 89
OUT
88 89
IN
88 89
OUT
88 89
IN
89
1 87 88 89
DFR_DISP_VSYNC
87 89
89
UT
6 88 89
OUT
6 88 89
IN
DFR_1V8_DISP_TE
DFR_1V8_DISP_INT
DFR_1V8_DISP_RESET_L
PP3V3_AWAKE_DFR
87 89
0.1UF
6.3V
0201
DFR DISP CONN
JT710
10%
X5R
DF40SG(1.5)-26DS-0.4V
1CT710
2
F-ST-SM
28 27
2 1
4 3
6 5
8 7
10 9
12 11
14 13
16 15
18 17
20 19
22 21
24 23
26 25
30 29
GND
GND
GND
GND
GND_VOID=TRUE
MIPI_DFR_CLK_CONN_FILT_P
89
MIPI_DFR_CLK_CONN_FILT_N
89
GND_VOID=TRUE
GND_VOID=TRUE
MIPI_DFR_DATA_CONN_FILT_P
89
MIPI_DFR_DATA_CONN_FILT_N
89
GND_VOID=TRUE
PP1V8_AWAKE_DFR
I2C_DFR_RES_SCL
I2C_DFR_RES_SDA
BYPASS=JT710.17::3MM
1CT711
1 0UF
20
2
6.3V
X5R
0201-1
LT710
3.25-OHM-0.1A-2.4GHZ
TAM0605-4SM
4
3 2
SYM_VER-2
1
LT711
3.25-OHM-0.1A-2.4GHZ
TAM0605-4SM
4
3 2
SYM_VER-2
41 87 88 89
IN
BI
1
41
41
MIPI_DFR_CLK_P
MIPI_DFR_CLK_N
MIPI_DFR_DATA_P<0>
MIPI_DFR_DATA_N<0>
IN
IN
IN
IN
7
7
7
7
PP3V8_AON_DFR_ISNS
105
6 88 94
IN
DFR_PWR_EN
BYPASS=UT700.4::3MM
CT702
1UF
10%
10V
X5R-CERM
0402
RT711
0
5%
1/20W
MF
0201
EDP: 230MA NOTE: THIS IS INRUSH CURRENT SPEC ONLY.THE LDO WILL CURRENT LIMIT THIS VALUE. EDP: 3.1A
1
2
DFR_PWR_EN_R
IN OUT
3
EN
NOSTUFF
47K
5%
MF
201
1
1UF
CER-X5R
2
RT701
2 1
1/20W
20%
16V
0201
1CT704
2
OUTPUT VOLTAGE
IOUT (MAX AVG)
DROPOUT VOLTAGE
UT700
SCY99217AMX180 SCY99217AMX330
X2DFN-COMBO
EPAD
GND
1.8V +/- 2%
250MA
80MV TYP @ 250MA
1 4
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
BYPASS=UT700 3MM
1CT703
1UF
10%
10V
X5R-CERM
0402
PP3V8_AON_DFR_ISNS
105
BYPASS=UT710.4::3MM
CT712
1UF
10%
10V
X5R-CERM
0402
1
2
PP1V8_AWAKE_DFR
41 87 88 89
DFR 3.3V LDO DFR 1.8V LDO
X2DFN-COMBO
IN OUT
3
EN
OUTPUT VOLTAGE
IOUT (MAX AVG)
DROPOUT VOLTAGE
UT710
EPAD
GND
1 4
3.3V +/- 2%
250MA
80MV TYP @ 250MA
TDP: 109MA TDP: 2MA
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
PP3V3_AWAKE_DFRPP1V8_AWAKE_DFR
BYPASS=UT710.1::3MM
10%
10V
0402
1
2
CT713
1UF
X5R-CERM
87 89 41 87 88 89
PAGE TITLE
DFR SUPPORT 1
OCP (MIN)
ACTIVE DISCHARGE
MAX OUTPUT CAP
250 MA
280 OHM TYP
OCP (MIN)
ACTIVE DISCHARGE
MAX OUTPUT CAP
250 MA
280 OHM TYP
BOM_COST_GROUP=TOUCH BAR
Page 88
**OK2INTEGRATE**
www.teknisi-indonesia.com
w w w . t e k n i s i - i n d o n e s i a . c o m
102 88
6 88 106
IN
9 88
IN
SPI_DFR_CS_L
DFR_TOUCH_CLK32K_RESET_L
PP1V25_AWAKE_IO
BYPASS=UT820::5MM
1
CT820
0.1UF
10%
10V
2
X5R-CERM
0201
DFR V3 SUPPORT
PP1V25_AWAKE_IO
PP1V8_AWAKE_DFR
BYPASS=UT820::5MM
1
CT821
0.1UF
10%
10V
2
X5R CERM
VCCB VCCA
02 1
41 87 88 89
UT820
74AVC2T45
1A
2A
5
DIR
VSSOP
GND
1B
2B
7 2
6 3
SPI_1V8_DFR_CS_L
DFR_1V8_TOUCH_CLK32K_RESET_R_L
RT857
33
2 1
DFR_1V8_TOUCH_CLK32K_RESET_L
1/20W 201 MF
5%
OUT
OUT
87 89
87 89
102 88
87 89
PP1V8_AWAKE_DFR
41 87 88 89
IN
SPI_1V8_DFR_MISO
1
RT860
100K
5%
1/ 0
MF
201
2
BYPASS=UT860 5MM
1
CT860
0.1UF
10%
10V
2
X5R-CERM
0201
B1
A
126
C1
SPI0 MISO IS A BOOTSTRAP PIN, TRI-STATE BUFFER PROVIDES ISOLATION
UT860
A2
74AUP1G126
BGA-YZP
C2
Y OUT
OE
A1
DFR_PWR_EN
IN
6 87 94
RT856
33
2 1
1/20W 5% 201MF
SPI_DFR_MISOSPI_DFR_MISO_R
4 6
PP1V25_AWAKE_IO
102 88
102 88
PP1V25_AWAKE_IO
BYPASS=UT830::5MM
1
CT831
0.1UF
10%
10V
2
X5R-CERM
0201
PP1V8_AWAKE_DFR
BYPASS=UT830::5MM
1
CT830
0.1UF
10%
10V
2
X5R-CERM
VCCB VCCA
0201
41 87 88 9
87 89 7
DFR_1V8_DISP_TE DFR_DISP_TE
IN OUT
UT830
18
IN
88
18
IN
88
SPI_DFR_MOSI
SPI_DFR_CLK
5
74AVC2T45
1A
2A
DIR
VSSOP
GND
1B
2B
7 2
6 3
SPI_1V8_DFR_MOSI_R
SPI_1V8_DFR_CLK_R
RT854
RT855
33
33
2 1
1/20W 5% MF
2 1
201
MF 201 5% 1/20W
SPI_1V8_DFR_MOSI
SPI_1V8_DFR_CLK
OUT
OUT
87 89
87 89
PP1V25_AWAKE_IO
102 88
RT880
BYPASS=UT880::5MM
1
CT880
0.1UF
10%
10V
2
X5R-CERM
0201
1
100K
5%
1/20W
MF
201
2
VCC
GND
UT880
SN74AUP1G17
SON
4 2
NC
NC
PP1V25_AWAKE_IO
1 2 88
RT800
47K
5%
1/20W
MF
201
SPI_DFR_CS_L
6 88 106
DFR_TOUCH_CLK32K_RESET_L
9 88
DFR_1V8_TOUCH_RESET_L
6 87 89
DFR_1V8_DISP_INT
6 87 89
DFR_1V8_DISP_RESET_L
6 87 89
SPI_DFR_MOSI
18 88
SPI_DFR_CLK
18 88
PP1V8_AWAKE_DFR
41 87 88 89
RT890
1
100K
5%
1/20W
MF
201
2
1
2
RT801
1/20W
47K
5%
MF
201
1
87 89 6
IN OUT
2
DFR_1V8_TOUCH_INT_L DFR_TOUCH_INT_L
BYPASS=UT890::5MM
1
CT890
0.1UF
10%
10V
2
X5R-CERM
0201
UT890
VCC
2
GND
SN74AUP1G17
SON
4
NC
NC
RT802
47K 47K
5%
MF
201
1
RT803
1/20W 1/20W
2
5%
MF
201
1
RT804
2
100K
5%
1/20W
MF
201
1
RT805
2
100K
5%
MF
201
1
RT806
2
100K
5%
1/20W 1/20W
MF
201
1
2
BOM_COST_GROUP=TOUCH BAR
PAGE TITLE
2
DFR SUPPORT 2
1
Page 89
DFU/DEBUG
w w w . t e k n i s i - i n d o n e s i a . c o m
POWER RAILS
DMIC AJ/MESA
106
101
101
18
IN
18
IN
5 33 56 90
IN
5 19 56 94
IN
6 18 56
IN
6 18 56
IN
9 18 56
9 18 56
IN
9 56
IN
9 56
IN
IN
9 18
IN
9 43
IN
9 43
IN
33 67 100 107
IN
5 33 55 94
IN
33 34 80 90
33 34 82 90
IN
6 33 91 96 100
IN
5 9 33 74 90 100
IN
33 90
IN
56 96
IN
56 96
IN
57 61 91
IN
57 61 91
IN
EUSB_ATC0_R_P
EUSB_ATC0_R_N
SOC_FORCE_DFU
SOC_DFU_STATUS
UART_DEBUGPRT_R2D
UART_DEBUGPRT_D2R
SWD_SOC_SWCLK
N
SWD_SOC_SWDIO
UART_SMC_DEBUGPRT_R2D
UART_SMC_DEBUGPRT_D2R
TP_SOC_AMUX_OUT
SMC_FIXTURE_MODE_L
I2C_SMC_UPC_SDA
I2C_SMC_UPC_SCL
PMU_SYS_ALIVE
PMU_ACTIVE_READY
PMU_ONOFF_L
N
PMU_RSLOC_RST_L
SOC_SOCHOT_L
PMU_RESET_L
PMU_SHDN
USB_DBG_LS_N
USB_DBG_LS_P
USB2_UPC0_P1_N
USB2_UPC0_P1_P
BATTERY
IN
43
IN
43
IN
21
IN
21
IN
PPVBAT_AON
I2C_SMC_PWR_3V3_SCL
I2C_SMC_PWR_3V3_SDA
SYS_DETECT_L
SYS_DETECT
GND
CHARGER
IN
22 98
IN
PPDCIN_USBC_AON
PPDCIN_AON_CHGR_R
GND
FAN
52
IN
52
IN
52
IN
52
IN
52
IN
52
IN
PP5V_S2_TO_FAN
FAN_RT_PWM
FAN_RT_TACH
TP_FAN_RT_OTP1
TP_FAN_RT_OTP2
GND_FAN
USBC
55 57 59
IN
57 59
IN
57 59
IN
56 57 59
56 57 59
IN
55 58 59
IN
56 58 59
IN
56 58 59
IN
58 59
58 59
IN
59
IN
59
IN
PPVBUS_USBC0
USBC0_SBU1
USBC0_SBU2
USBC0_CC1
N
USBC0_CC2
GND
PPVBUS_USBC1
USBC1_CC1
USBC1_CC2
USBC1_SBU1
N
USBC1_SBU2
GND
TP_USBC0_PP20V
TP_USBC1_PP20V
1
TOP TP-P5
1
1
1
1
TOP
1
TOP TP-P5
1
TOP TP-P5
1
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
1
1
TOP
1
TOP
1
1
TOP TP-P5
1
1
1
TOP TP-P5
1
1
1
TOP TP-P5
1
TOP TP-P5
1
1
1
1
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
1
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
1
TOP TP-P5
1
1
1
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
1
1
1
1
1
1
TOP TP-P5
1
TOP TP-P5
1
TOP
1
TOP
1
TOP
1
1
TPU600
TP
TPU601
TP
TPU602
TP
TPU603
TP
TPU604
TP
TPU605
TP
TPU606
P
TPU607
TP
TPU608
TP
TPU609
TP
TPU610
TP
TPU611
TP
TPU612
TP
TPU613
TP
TPU614
TP
TPU615
TP
TPU616
P
TPU617
TP
TPU618
TP
TPU619
TP
TPU620
TP
TPU634
TP
TPU635
TP
TPU636
TP
TPU637
TP
TPU621
TP
TPU622
TP
TPU623
TP
TPU624
TP
TPU625
TP
TPU626
TP
TPU627
T
TPU628
TP
TPU629
TP
TPU630
TP
TPU631
TP
TPU632
TP
TPU633
TP
TPU640
TP
TPU641
TP
TPU642
TP
TPU643
TP
TPU644
TP
TPU645
TP
TPU646
TP
TPU647
TP
TPU650
TP
TPU651
TP
TPU652
TP
TPU653
TP
TPU654
TP
TPU655
TP
TPU656
TP
TPU657
T
TPU660
TP
TPU661
TP
TPU662
TP
TPU663
TP
TPU664
TP
TPU665
TP
TPU666
P
TPU667
TP
TPU668
TP
TPU669
TP
TPU670
TP
TPU671
TP
TPU672
TP
TPU673
TP
TPU674
TP
TPU675
P
TPU676
TP
TPU677
TP
TPU678
TP
TPU679
TP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5
TP-P5
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5
TP-P5
TP-P5
TP-P5TOP
TP-P5TOP
101
101
101
101
101
101
102
102
101
101
101
101
102
102
102
102
101
103
101
101
103
101
102
102
102
102
101
104
104
104
104
104
102
104
104
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
84 104
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
41 69 104
IN
IN
55 56 57
IN
IN
22 97
IN
69
69
69
69
69
69
69
69
69
69
68 69
68 69
68 69
68 69
69 104
6 69
69 70
7 69
6 69
6 69
69
69
42 69
42 69
68 69
68 69
69 71
69 71
6 69
41 69
41 69
69
69
69
PPBUS_AON
PP3V8_AON
PPVDD_PCPU_AWAKE
PPVDD_GPU_AWAKE
PPVDD_CPU_SRAM_AWAKE
PPVDD_ECPU_AWAKE
PP1V8_AWAKE
PP1V25_AWAKE_IO
PPVDD_SOC_S1
PPVDD_DISP_S1
PPVDD_DCS_S1
PP1V8_S2
PP1V2_S2
PP3V3_S2_UPC
PP1V25_S2
PP1V8_AON
PP1V2_AWAKE_PLL
PP0V88_S1
PP0V805_S1_VDD_FIXED
PP0V6_S1_VDDQL
PP0V764_S1_SRAM
PP1V2_S2_CIO
PP1V06_S2 W_DRAM
PP0V855_S2SW_CIO
PP0V72_S2_VDD_LOW
PP0V88_AWAKESW_NAND
PP1V25_AWAKESW_VCCQ
PP2V5_AWAKE_NAND
PP3V3_S2SW_USB1
PP3V3_S2SW_USB0
PP3V3_AON
PP3V3_S2
PP5V_S2
PP1V4_LDO_PREREG
PP3V3_SW_LCD
PP3V3_S2SW_SNS
PP3V3_UPC0_LDO
PPVOUT_LCDBKLT
PPVBAT_AON_CHGR_REG
DISPLAY
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
AUX_N
AUX_P
DP0_P
DP0_N
DP1_P
DP1_N
DP2_P
DP2_N
DP3_P
DP3_N
MIPI_FTCAM_DATA_ISOL_N
MIPI_FTCAM_DATA_ISOL_P
MIPI_FTCAM_CLK_ISOL_N
MIPI_FTCAM_CLK_ISOL_P
PP5V_SW_LCD
UART_TCON_HDMI_D2R
EDP_PANEL_1V8_EN
LPDP_INT_HPD
SPI_TCON_CS_L
SPI_TCON_MISO
SPI_TCON_MOSI
SPI_TCON_CLK
I2C_ALS_1V8_SDA
I2C_ALS_1V8_SCL
I2C_FTCAM_ISOL_SCL
I2C_FTCAM_ISOL_SDA
I2C_BKLT_SDA
I2C_BKLT_SCL
UART_TCON_HDMI_R2D
I2C_MLB2JERRY_3V3_SDA
I2C_MLB2JERRY_3V3_SCL
TP_TCON_SWCLK
TP_TCON_SWDIO
PP5V_CAM
GND
1
1
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
1
1
TOP TP-P5
1
TOP TP-P5
1
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP
1
1
1
1
TOP TP-P5
1
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
1
1
1
TOP
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
1
1
TOP TP-P5
1
1
TOP
1
TOP
1
TOP
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP
1
TOP TP-P5
1
TOP
1
TOP
1
TOP TP-P5
1
TOP
1
TOP
TOP
TOP TP-P5
TOP
TOP
TOP
TOP
TOP
TOP
TOP
TOP
TOP
TOP TP-P5
TOP TP-P5
TOP
TOP TP-P5
TOP TP-P5
TOP TP-P5
TOP TP-P5
TOP TP-P5
TOP TP-P5
TPU6A0
TP
TPU6A1
TP
TPU6A2
TP
TPU6A3
TP
TPU6A4
TP
TPU6A5
TP
TPU6A6
TP
TPU6A7
TP
TPU6A8
TP
TPU6A9
TP
TPU6B0
TP
TPU6B1
TP
TPU6B2
TP
TPU6B3
TP
TPU6B4
TP
TPU6B5
TP
TPU6B6
TP
TPU6B7
TP
TPU6B8
TP
TPU6F0
TP
TPU6B9
TP
TPU6C0
TP
TPU6C1
TP
TPU6C2
TP
TPU6C3
TP
TPU6C4
TP
TPU6C5
TP
TPU6C6
TP
TPU6C7
TP
TPU6C8
TP
TPU6C9
TP
TPU6D0
TP
TPU6D1
TP
TPU6D2
TP
TPU6D3
TP
TPU6D4
TP
TPU6D5
TP
TPU6D6
TP
TPU6D7
TP
TPU6D8
TP
TPU6D9
TP
TPU6E0
TP
TPU6E1
TP
TPU6E2
TP
TPU6E3
TP
TPU6E4
TP
TPU6E5
TP
TPU6E6
TP
TPU6E7
TP
TPU6E8
TP
TPU6E9
TP
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TPU6G0
TP
TPU6G1
TP
TPU6G2
TP
TPU6G3
TP
TPU6G4
TP
TPU6G5
TP
TPU6G6
TP
TPU6G7
TP
TPU6G8
TP
TPU6G9
TP
TPU6H0
TP
TPU6H1
TP
TPU6H2
TP
TPU6H3
TP
TPU6H4
TP
TPU6H5
TP
TPU6H6
TP
TPU6H7
TP
TPU6H8
TP
TPU6H9
TP
TPU6I0
TP
TPU6I1
TP
TPU6I2
TP
TPU6I3
TP
TPU6I4
TP
TPU6I5
TP
TPU6I6
TP
TPU6I7
TP
TPU6I8
TP
TPU6I9
TP
TPU6J0
TP
TPU6J1
TP
TPU6J2
TP
TPU6J3
TP
TPU6J4
TP
TP-P5OP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5
TP-P5
TP-P5
TP-P5
TP-P5
TP-P5
TP-P5
TP-P5
TP-P5
TP-P5 GND_VOID=TRUE
TP-P5
TP-P5
TP-P5
TP-P5
TP-P5
TP-P5TOP
TP-P5
TP-P5
TP-P5
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
80
IN
80
IN
80
IN
80
IN
80
IN
80
IN
80
IN
80
IN
80
IN
IN
86
86
IN
6 80 86
IN
18 80
IN
80 86
IN
18 80
IN
80 86
IN
73 104
IN
80 86
IN
73 74 0
IN
IN
76
IN
77 79
77 79
77 79
77 79
6 7
78 79
78 79
78 79
78 79
6 79
105
82 83
82 83
82 83
82 83
82 83
82 83
82 83
82 83
2 83
82 83
82 83
82 83
82 83
82 83
82 83
82 83
82 83
82 83
82 83
82 83
82 83
82 83
82 83
82 83
82 83
82 83
82 83
81
72 81
72 81
81
AMR
AUD_CONN_LEFT_OUT
AUD_CONN_SLEEVE
AUD_CONN_RIGHT_OUT
AUD_CONN_RING2
AUD_CONN_TIP_SENSE
AUD_CONN_LEFT_SNS
AUD_CONN_RING2_XW
AUD_CONN_RING_SENSE
AUD_CONN_RIGHT_SNS
AUD_CONN_SLEEVE_XW
PP1V8_TOUCHID_FILT_CONN
SPI_TOUCHID_MISO
SPI_TOUCHID_MOSI
TOUCHID_INT_1V8_CONN
SPI_TOUCHID_CLK
TOUCHID_BOOST_EN
PP1V8_AON
PP16V0_TOUCHID_FILT_CONN
AMR_RIGHT_OR_ND_1V8
PP3V0_TOUCHID_FILT_CONN
GND
GND_AUDIO_CODEC
SPEAKER
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
SPKRAMP_A_OUTP
SPKRAMP_A_OUTN
SPKRAMP_B_OUTP
SPKRAMP_B_OUTN
SPKR_ID0
GND
SPKRAMP_D_OUTP
SPKRAMP_D_OUTN
SPKRAMP_E_OUTP
SPKRAMP_E_OUTN
SPKR_ID1
GND
KEYBOARD
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
PP1V85_S2_KBD_ISNS
KBD_ID1
KBD_DRIVE_Y2
KBD_DRIVE_Y1
KBD_DRIVE_Y3
KBD_DRIVE_Y4
KBD_SENSE_X0
KBD_SENSE_X1
KBD_SENSE_X2
KBD_SENSE_X5
KBD_SENSE_X3
KBD_SENSE_X9
KBD_SENSE_X12
KBD_SENSE_X4
KBD_SENSE_X11
KBD_SENSE_X10
KBD_SENSE_X6
KBD_SENSE_X7
KBD_SENSE_X8
KBD_DRIVE_Y5
KBD_DRIVE_Y7
KBD_DRIVE_Y6
KBD_DRIVE_Y0
KBD_CAP_CATHODE
PP3V3_AON_KBD_CONN
KBD_RIGHT_SHIFT_KEY
KBD_LEFT_OPTION_KEY
KBD_CONTROL_KEY
PPVOUT_S0_KBDLED_CONN
KBDLED_CATHODE1_R
KBDLED_CATHODE1
KBDLED_CATHODE2
KBDLED_CATHODE2_R
GND
1
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
1
1
TOP TP-P5
1
TOP TP-P5
TOP TP-P5
TOP TP-P5
TOP TP-P5
TOP TP-P5
TOP TP-P5
TOP TP-P5
TOP TP-P5
TOP TP-P5
TOP TP-P5
TO TP-P5
TOP
TOP TP-P5
TOP TP-P5
TOP TP-P5
TOP TP-P5
TOP TP-P5
TOP TP-P5
TOP TP-P5
TPU6K0
TP
TPU6K1
TP
TPU6K2
TP
TPU6K3
TP
TPU6K4
TP
TPU6K5
TP
TPU6K6
TP
TPU6K7
TP
TPU6K8
TP
TPU6K9
TP
TPU6L0
TP
TPU6L1
TP
TPU6L2
TP
TPU6L3
TP
TPU6L4
TP
TPU6L5
TP
TPU6L6
TP
TPU6L7
TP
TPU6L8
TP
TPU6L9
TP
TPU6M0
TP
TPU6M1
TP
TPU6M2
TP
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TPU6M3
TP
TPU6M4
TP
TPU6M5
TP
TPU6M6
TP
TPU6M7
TP
TPU6M8
TP
TPU6M9
TP
TPU6N0
TP
TPU6N1
TP
TPU6N2
TP
TPU6N3
TP
TPU6N4
TP
TPU6N5
TP
TPU6N6
TP
TPU6N7
TP
TPU6N8
TP
TPU6N9
TP
TPU6P0
TP
TPU6P1
TP
TPU6P2
TP
TPU6P3
TP
TPU6P4
TP
TPU6P5
TP
TPU6P6
TP
TPU6P7
TP
TPU6P8
TP
TPU6P9
TP
TPU6Q0
TP
TPU6Q1
TP
TPU6Q2
TP
TPU6Q3
TP
TPU6Q4
TP
TPU6Q5
TP
TPU6Q6
TP
TPU6Q7
TP
TPU6R0
TP
TPU6R1
TP
TPU6R2
TP
TPU6R3
TP
TPU6R4
TP
TPU6R5
TP
TPU6R6
TP
TPU6R7
TP
TPU6R8
TP
TPU6R9
TP
TPU6S0
TP
TPU6S1
TP
TPU6S2
TP
TPU6S3
TP
TPU6S4
TP
TPU6S5
TP
TPU6S6
TP
TPU6S7
TP
TPU6S8
TP
TPU6S9
TP
TPU6T0
TP
TPU6T1
TP
TPU6T2
TP
TPU6T3
TP
TPU6T4
TP
TPU6T5
TP
TPU6T6
TP
TP-P5TOP
TP-P5TOP
TP-P5OP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5T P
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
104
105
74 80
80
IN
80
IN
74 80
IN
80
IN
DMIC_CLK0_1V8_OUT
N
AUD_DMIC0_DATA_CONN
PP1V8_DMIC
DMIC_CLK1_1V8_OUT
AUD_DMIC1_DATA_CONN
GND
1
TOP TP-P5
1
1
TOP TP-P5
1
1
1
TOP TP-P5
TPU6T9
TP
TPU6U0
TP
TPU6U1
TP
TPU6U2
TP
TPU6U3
TP
TPU6U4
TP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TRACKPAD
33 73 85 87
IN
43
IN
34 85
IN
43
IN
82 85
IN
4 85
IN
82 85 117
IN
84 85
IN
82 85 117
IN
84 85
IN
84 85
IN
84 85
IN
84 85
IN
85
IN
IN
IN
85
IN
IPD_LID_OPEN_1V8
I2C_SMC_IPD_1V8_SCL
TPAD_KBD_WAKE_L
I2C_SMC_IPD_1V8_SDA
KBD_INT_L
SPI_TPAD_INT_CONN_L
I2C_KBD_SDA
SPI_TPAD_MOSI_CONN
I2C_KBD_SCL
SPI_TPAD_CS_CONN_L
SPI_TPAD_MISO_CONN
SPI_TPAD_EN_CONN
SPI_TPAD_CLK_CONN
PP5V_S2_TPAD_CONN
PP1V85_S2_IPD
PP3V3_S2_TPAD_ISNS
ACT_GND
GND
1
1
1
1
1
1
TOP TP-P5
1
1
1
1
1
1
1
1
TOP TP-P5
1
TOP TP-P5
1
1
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TPU6U5
TP
TPU6U6
TP
TPU6U7
TP
TPU6U8
TP
TPU6U9
TP
TPU6V0
TP
TPU6V1
TP
TPU6V2
TP
TPU6V3
TP
TPU6V4
TP
TPU6V5
TP
TPU6V6
TP
TPU6V7
TP
TPU6V8
TP
TPU6V9
TP
TPU6W0
TP
TPU6W1
TP
TPU6W2
TP
TPU6W3
TP
TPU6W4
TP
TPU6W5
TP
TPU6W6
TP
TPU6W7
TP
TPU6W8
TP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
DFR
87
IN
87
IN
87
IN
87
IN
87 88
IN
87 88
IN
7 88
IN
87 88
IN
87 88
IN
41
IN
87 88
IN
41
IN
6 87 88
IN
87
IN
41 87 88
IN
87
IN
TP_DFR_TOUCH_PANEL_DETECT
DFR_LID_OPEN_L
DFR_DISP_VSYNC
TP_DFR_TOUCH_RSVD
SPI_1V8_DFR_MISO
SPI_1V8_DFR_CS_L
SPI_1V8_DFR_CLK
SPI_1V8_DFR_MOSI
DFR_1V8_TOUCH_INT_L
I2C_DFR_RES_SCL
DFR_1V8_TOUCH_CLK32K_RESET_L
I2C_DFR_RES_SDA
DFR_1V8_TOUCH_RESET_L
TP_DFR_TOUCH_ROM_WC
PP1V8_AWAKE_DFR
PP5V_S2_DFR_FILT
GND
87
IN
87
IN
87 88
IN
87
IN
6 87 88
IN
8
IN
6 87 88
IN
87
IN
MIPI_DFR_CLK_CONN_FILT_P
MIPI_DFR_CLK_CONN_FILT_N
DFR_1V8_DISP_TE
MIPI_DFR_DATA_CONN_FILT_P
DFR_1V8_DISP_INT
MIPI_DFR_DATA_CONN_FILT_N
DFR_1V8_DISP_RESET_L
PP3V3_AWAKE_DFR
GND
SYNC_MASTER=KELVIN_T668_MLB
PAGE TITLE
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
1
TOP TP-P5
1
1
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
1
1
1
TOP TP-P5
1
TOP TP-P5
1
1
TOP TP-P5
1
TOP TP-P5
1
TOP TP-P5
1
OP TP-P5
1
1
TPU6W9
TP
TPU6X0
TP
TPU6X1
TP
TPU6X2
TP
TPU6X3
TP
TPU6X4
TP
TPU6X5
TP
TPU6X6
TP
TPU6X7
TP
TPU6X8
TP
TPU6X9
TP
TPU6Y0
TP
TPU6Y1
TP
TPU6Y2
TP
TPU6Y3
TP
TPU6Y4
TP
TPU6Y5
TP
TPU6Y6
TP
TPU6Y7
TP
TPU6Y8
TP
TPU6Y9
TP
TPU6Z0
TP
TPU6Z1
TP
TPU6Z2
TP
TPU6Z3
TP
TPU6Z4
TP
TPU6Z5
TP
TPU6Z6
TP
TPU6Z7
TP
TPU6Z8
TP
TPU6Z9
TP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
TP-P5TOP
FCT
73 74
I
AMR_LEFT_OR_ND_1V8
1
TPU699
T
TP-P5TOP
71 72
IN
82 83
IN
GND_BKLT_SGND
KBD_DRIVE_Y8
1
1
TOP TP-P5
1
TOP TP-P5
TPU6T7
TP
TPU6T8
TP
TPU6J5
TP
TP-P5TOP
4
Page 90
UPC RESET
w w w . t e k n i s i - i n d o n e s i a . c o m
RESET
POWER BUTTON
DEBUG_BUTTON
SV000
SKSGPCE010
SM
1
3
DEBUG_BUTTON
PLACE_SIDE=TOP
0.60 MM TALL 0.60 MM TALL 0.60 MM TALL
SV001
SKSWCEE010
SM
2
4
2 1
PMU_ONOFF_L
OUT
RSLOC
DEBUG_BUTTON
PLACE_SIDE=BOTTOM
1.4 MM TALL 1.4 MM TALL
SV002
SKSGPCE010
SM
1
3
GND GND
DEBUG_BUTTON
PLACE_SIDE=TOP
2
4
FORCE DFU
DEBUG_BUTTON
PLACE_SIDE=BOTTOM
1.4 MM TALL 1.4 MM TALL
SV004
SKSGPCE010
SM
1
3
DEBUG_BUTTON
PLACE_SIDE=TOP
2
4
(RESET PMU)
DEBUG_BUTTON
PLACE_SIDE=BOTTOM
1.4 MM TALL
SV006
SKSGPCE010
SM
1
3
GND
DEBUG_BUTTON
PLACE_SIDE=TOP PLACE_SIDE=TOP
2
4
(RESET SOC ONLY)
DEBUG_BUTTON
PLAC _SIDE=BOTTOM PLACE_SIDE=BOTTOM
SV008
SKSGPCE010
M
1
3
GND GND
DEBUG_BUTTON
0.60 MM TALL 0.60 MM TALL
SV003
SKSWCEE010
SM
SV005
SKSWCEE010
SM
2 1
PMU_RSLOC_RST_L
2 1
SOC_FORCE_DFU
5 33 56 89 33 34 82 89 33 34 80 89 34 57 58 100
OUT OUT
SV007
SKSWCEE010
SM
2 1
UPC_PMU_RESET_3V3
OUT
SV009
SKSWCEE010
SM
2
4
2 1
PMU_RESET_L
5 9 33 74 89 100
OUT
PMU SHUTDOWN
DEBUG_BUTTON
PLACE_SIDE=BOTTOM
1.4 MM TALL
SV010
SKSGPCE010
SM
1
3
GND
2
4
PP1V25_S2_DFU_BTN_R
DEBUG_BUTTON
PP1V25_S2
02
RV005
1K
5%
1/20W
201
PP3V3_UPC_PMU_RESET_R
DEBUG_BUTTON
1K
5%
MF MF
201
1
2
1
2
104
PP3V3_AON
RV007
1/20W
DEBUG_BUTTON
PLACE_SIDE=TOP
0.60 MM TALL
SV011
SKSWCEE010
SM
2 1
104
PMU_SHDN
PP1V8_AON_DBGSHDNBTN_R
DEBUG_BUTTON
RV011
1K
1/20W
201
PP1V8_AON
5%
MF
OUT
1
2
33 89
BOM_COST_GROUP=DEBUG
PAGE TITLE
2
SYNC_DATE=06/20/2019 SYNC_MASTER=T668_MLB
DEBUG: BUTTONS
1
Page 91
CHARGER ARKANOID CONN
w w w . t e k n i s i - i n d o n e s i a . c o m
CHGR_DBG
JV100
505070-1222
M-ST-SM
14 13
I2C_SMC_PWR_SDA
43 106
I2C_SMC_PWR_SCL
43 106
15
2 1
4 3
6 5
8 7
10 9
12 11
16
SOC_SOCHOT_L
6 33 89 96 100
33
29 33
33
57 61 89
57 61 89
MPMU_FAULT_OUT_L
PMU_SCRASH_L
PMU_CRASH_L
USB2_UPC0_P1_P
USB2_UPC0_P1_N
1
TP
TP-P55
1
TP
TP-P55
1
TP
TP-P55
1
TP
TP-P55
1
PP
1
PP
TPV190
PLACE_SIDE=TOP
TPV191
PLACE_SIDE=TOP
TPV192
PLACE_SIDE=TOP
TPV194
PLACE_SIDE=TOP
PPV100
PPV101
P4MM
SMP4MM
SM
BOM_COST_GROUP=DEBUG
SYNC_MASTER=T668_MLB
PAGE TITLE
2
SYNC_DATE=06/20/2019
DEBUG: MISC
1
Page 92
AON LEDS (BLUE)
w w w . t e k n i s i - i n d o n e s i a . c o m
101 94 93 92
PP3V8_AON
DBG_LED
998-19870
DSV810
A
BLUE-22.5MCD-2MA
SM
VF_AVG = 2.59 V
XWV810
NO_XNET_CONNECTION=1
XW_P3V8_AON_LED
DBG_LED
RV810
2 1
5% 5%
1/20W
MF
SM
104
2
XWV820
1
NO_XNET_CONNECTION=1
2
SM
1
104
IN IN
XW_PP3V3_AON_LED
DBG_LED
376S00076
QV820
SSM3K16CTAP
SOT883L
1
VGS_MAX 10 V
VTH_MAX 0.9 V
DBG_LED
RV820
2
3
1/20W
2 1
MF
DBG_LED
998-19870
DSV820
K A
BLUE-22.5MCD-2MA
SM
VF_AVG = 2.59 V
2
PP1V8_AON PP3V3_AON
XW_PP1V8_AON_LED
DBG_LED
376S00076
QV830
SSM3K16CTAP
SOT883L
1
VGS_MAX 10 V
VTH_MAX 0.9 V
3
XWV830
NO_XNET_CONNECTION=1
SM
DBG_LED
RV830
6.8K 6.8K 6.8K
1/20W
201 201 201
5%
MF
2
DSV830_D DSV830_R DSV820_D DSV820_R DSV810_D
2
1
DBG_LED
998-19870
DSV830
K A
BLUE-22.5MCD-2MA
SM
VF_AVG = 2.59 V
101 94 93 92
PP3V8_AON
3 34 8
1
2
IPD_PWR_EN
XW_IPD_PWR_EN
DBG_LED
376S00076
QV840
SSM3K16CTAP
SOT883L
VGS_MAX 10 V
VTH_MAX 0.9 V
3
DSV840_R DSV860_D
XWV840
NO_XNET_CONNECTION=1
SM
DBG_LED
RV840
2 1
DSV840_D
5%
1/20W
MF
2
1
DBG_LED
DSV840
K A
MAGENTA-45MCD-2MA
SM
VF_AVG = 2.59 V
102
IN N IN
PP1V25_S2
XW_PP1V225_S2_LED
DBG_LED
376S00076
QV850
SSM3K16CTAP
SOT883L
VGS_MAX 10 V
VTH_MAX 0.9 V
2 3
NO_XNET_CONNECTION=1
DSV850_R
XWV850
DBG_LED
RV850
5%
1/20W
MF
DBGLED_RETURN
94 93 92
S2 LEDS (MAGENTA)
I_MAX = 300 MA
PP3V8_AON
DBGLED_RETURN
MAKE_BASE=TRUE
VOLTAGE=0V
1
RV899
47K
1%
1/20W
MF
201
2
SM
01 4 93 92
1
2
1
PP5V_S2
NO_XNET_CONNECTION=1
XW_PP5V_S2_LED
XWV860
SM
2
1
94 93 92
DBGLED_RETURN
DBG_LED
376S00076
QV860
SSM3K16CTAP
SOT883L
1
VGS_MAX 10 V
DBG_LED
DSV850
2 1
MAGENTA-45MCD-2MA
K A
SM
VF_AVG = 2.59 V
2
VTH_MAX 0.9 V
3
DSV860_R DSV850_D
DBG_LED
RV860
8.2K 8.2K 8.2K
5%
1/20W
MF
201 201 201
2 1
DBG_LED
DSV860
K A
MAGENTA-45MCD-2MA
SM
VF_AVG = 2.59 V
R_MAX = 130 MOHM
998-20409 DBG_LED
DBG_LED
SV899
SSSS810701
SM
3 2
NC
101 94 93 92
PP3V8_AON
101 102 104
IN IN IN
XWV870
SM
2
XWV880
1
2
SM
1
XW_PP1V8_S2_LED XW_PP1V2_S2_LED
376S00076
QV870
SSM3K16CTAP
SOT883L
1
VGS_MAX 10 V
VTH_MAX 0.9 V
DBG_LED
RV870
2
3
DSV870_R DSV870_D DSV880_R DSV890_R DSV890_D DSV880_D
1/20W
2 1
5%
MF
DBG_LED DBG_LED DBG_LED
DSV870
K A
VF_AVG = 2.59 V VF_AVG = 2.59 V VF_AVG = 2.59 V
2
376S00076
QV880
SSM3K16CTAP
SOT883L
1
VTH_MAX 0.9 V
DBG_LED
3
1/20W
2 1
5%
MF
RV880
DSV880
K A
DBGLED_RETURN
94 93 92
S2 LEDS (MAGENTA)
PP3V3_S2 PP1V2_S2 PP1V8_S2
2
XWV890
NO_XNET_CONNECTION=1 NO_XNET_CONNECTION=1 NO_XNET_CONNECTION=1
XW_PP3V3_S2_LED
DBG_LED DBG_LED DBG_LED
376S00076
QV890
SSM3K16CTAP
SOT883L
1
VGS_MAX 10 V VGS_MAX 10 V
VTH_MAX 0.9 V
DBG_LED
RV890
2
3
8.2K 8.2K 8.2K
5%
1/20W
MF
201 201 201
SM
1
DSV890
2 1
K A
MAGENTA 45MCD-2MA MAGENTA-45MCD-2MA MAGENTA-45MCD-2MA
SM SM SM
SYNC_MASTER=T668_MLB
PAGE TITLE
DEBUG: LEDS (1/3)
SYNC_DATE=07/24/2019
DBGLED_RETURN
94 93 92
BOM_COST_GROUP=DEBUG
2
1
Page 93
S2SW LEDS (ORANGE)
w w w . t e k n i s i - i n d o n e s i a . c o m
101 94 93 92
PP3V8_AON
IN IN
1
2
PP1V8_S2SW_VDD1 PP1V06_S2SW_DRAM
XWV960
NO_XNET_CONNECTION=1
SM SM
104 101
2
1
XW_PP1V8_S2SW_DRAM_LED XW_PP1V06_S2SW_DRAM_LED
DBG_LED DBG_LED
376S00076
QV960
SSM3K16CTAP
SOT883L
VGS_MAX 10 V
VTH_MAX 0.9 V
DBG_LED
DBG_LED
DSV960
376S00076
QV970
SSM3K16CTAP
SOT883L
1
VGS_MAX 10 V
VTH_MAX 0.9 V
RV960
3
DSV960_R
2.2K
5%
1/20W
MF
201
2 1
DSV960_D
K
ORANGE-11.5MCD-2MA
A
SM
2
3
NO_XNET_CONNECTION=1
DSV970_R
XWV970
DBG_LED
RV970
2.2K
5%
1/20W
MF
201
2
1
2 1
DSV970_D
DBG_LED
DSV970
K
ORANGE-11.5MCD-2MA
VF_AVG = 1.8 V VF_AVG = 1.8 V
A
SM
101 94 93 92
PP3V8_AON
101 103
2
XWV900
O_XNET_CONNECTION=1
SM
1
XW_PPVDD_DISP_S1_LED XW_PP0V805_S1_VDD_FIXED_LED
DBG_LED
1
RV901
2K
1%
1/20W
MF
201
2
DBG_LED
1
RV911
2K
1%
1/20W
MF
201
2
DBGLED_RETURN
94 93 92
S1 LEDS (YELLOW)
PP0V805_S1_VDD_FIXED PPVDD_DISP_S1
IN IN
2
XWV910
NO XNET_CONNECTION=1
SM
1
DSV900_B
6
2
QV900
1
DBG_LED
RV900
DBG_LED
372S00042
SNST3904DXV6T5G
SOT563
VBE,SAT @ 1 MA ~ 0.6 V
HFE,MIN @ 1 MA = 70
2.2K
5%
1/20W
MF
201
DBG_LED
DSV910_B
DSV900
2 1
DSV900_D DSV900_C DSV910_D DSV910_C
K A
YELLOW-7.2MCD-2MA
SM
VF_AVG = 1.8 V
DBG_LED
3
372S00042
5
QV900
SNST3904DXV6T5G
SOT563
VBE,SAT @ 1 M ~ 0.6 V
4
HFE,MIN @ 1 MA = 70
DBG_LED
RV910
2.2K
5%
1/20W
MF
201
DBG_LED
DSV910
2 1
YELLOW-7.2MCD-2MA
K A
SM
VF_AVG = 1.8 V
DBGLED_RETURN
94 93 92
AWAKE LEDS (GREEN)
101 94 93 92
PP3V8_AON
101 101
PPVDD_PCPU_AWAKE
IN IN
2
XWV920
NO_XNET_CONNECTION=1
SM
1
XW_PPVDD_PCPU_AWAKE_LED XW_PPVDD_GPU_AWAKE_LED
DBG_LED
1
RV921
2K
1%
1/20W
MF
201
2
DSV920_B DSV930_B
DBG_LED
RV920
12K
1/20W
DBG_LED
6
372S00042
2
QV920
SNST3904DXV6T5G
SOT563
VBE,SAT @ 1 MA ~ 0.6 V
1
HFE,MIN @ 1 MA = 70
5%
MF
201
2 1
DSV920_D DSV920_C DSV930_D DSV930_C
DBG_LED
DSV920
K A
GREEN-90MCD-2MA
SM
VF_AVG = 2.53 V
DBG_LED
1
RV931
2K
1%
1/20W
MF
201
2
5
PPVDD_GPU_AWAKE
NO_XNET_CONNECTION=1
DBG_LED
3
372S00042
QV920
SNST3904DXV6T5G
SOT563
VBE,SAT @ 1 MA ~ 0.6 V
4
HFE,MIN @ 1 MA = 70
XWV930
DBG_LED
RV930
12K
5%
1/20W
MF
201
2
SM
1
102
IN IN
2
XWV940
NO_XNET_CONNECTION=1
SM
1
102
PP1V25_AWAKESW_VCCQ PP1V25_AWAKE_IO
2
XWV950
NO_XNET_CONNECTION=1
SM
1
XW_PP1V2_AWAKE_IO_LED XW_PP1V225_AWAKESW_VCCQ_LED
DBG_LED
DSV930
2 1
K A
GREEN-90MCD-2MA
SM
VF_AVG = 2.53 V
2
DBG_LED
376S00076
QV940
SSM3K16CTAP
SOT883L
1
VGS_MAX 10 V
VTH_MAX 0.9 V
DBG_LED
RV940
3
DSV940_R DSV940_D DSV950_R DSV950_D
12K
5%
1/20W
MF
201
2 1
DBG_LED
DSV940
K A
GREEN-90MCD-2MA
SM
VF_AVG = 2.53 V
2
DBG_LED
376S00076
QV950
SSM3K16CTAP
SOT883L
1
VGS_MAX 10 V
VTH_MAX 0.9 V
DBG_LED
RV950
3
12K
5%
1/20W
MF
201
2 1
DBG_LED
DSV950
K A
GREEN-90MCD-2MA
SM
VF_AVG = 2.53 V
SYNC_MASTER=T668_MLB SYNC_DATE=07/24/2019
PAGE TITLE
DEBUG: LEDS (2/3)
DBGLED_RETURN
BOM_COST_GROUP=DEBUG
94 93 92
2
Page 94
MODULE LEDS (WHITE)
w w w . t e k n i s i - i n d o n e s i a . c o m
101 94 93 92
PP3V8_AON
33 71
1
2
BL_PWR_EN
XWW000
NO_XNET_CONNECTION=1
SM
34 70 6 7 88 86 33 62 63
IN
2
1
LCD_PWR_EN
XW_BL_PWR_EN XW_LCD_PWR_EN
DBG_LED
376S00076
QW000
SSM3K16CTAP
SOT883L
VGS_MAX 10 V
3
DSW000_R DSW000_D DSW010_R DSW010_D DSW020_R DSW020_D DSW030_D DSW040_R DSW040_D
DBG_LED
RW000
5%
1/20W
MF
DBG_LED
DSW000
2 1
K A
WHITE 57MCD-2MA
SM
VF_AVG = 2.59 V VF_AVG = 2.59 V VF_AVG = 2.59 V VF_AVG = 2.59 V
2
DBG_LED
376S00076
QW010
SSM3K16CTAP
SOT883L
1
VTH_MAX 0.9 V VTH_MAX 0.9 V
3
XWW010
NO_XNET_CONNECTION=1
SM
DBG_LED
RW010
6.8K
1/20W
2 1
5%
MF
2
1
DBG_LED
DSW010
WHITE-57MCD-2MA
K A
SM
DFR_PWR_EN
2
XWW020
SM
1
XW_DFR_PWR_EN
DBG_LED
376S00076
QW020
SSM3K16CTAP
SOT883L
1
VGS_MAX 10 V VGS_MAX 10 V
VTH_MAX 0.9 V
DBG_LED
RW020
2
3
1/20W
2
5%
MF
DBG_LED
DSW020
A
WHITE-57MCD-2MA
SM
2
TOUCHID_PWR_EN
XW_TOUCHID_PWR_EN
DBG_LED
376S00076
QW030
SSM3K16CTAP
SOT883L
1
VGS_MAX 10 V
VTH_MAX 0.9 V
3
DSW030_R
XWW030
DBG_LED
RW030
5%
1/20W
MF
201 201 201 201
IN IN IN IN
2
SM
1
WLBT_PWR_EN
2
XWW040
NO_XNET_CONNECTION=1 NO_XNET_CONNECTION=1 NO_XNET_CONNECTION=1
SM
1
XW_WLBT_PWR_EN
DBG_LED
376S00076
QW040
SSM3K16CTAP
SOT883L
1
VGS_MAX 10 V
DBG_LED
DSW030
2 1
K A
WHITE-57MCD-2MA
SM
2
VTH_MAX 0.9 V
3
DBG_LED
RW040
6.8K 6.8K 6 8K 6.8K
5%
1/20W
MF
201
2 1
DBG_LED
DSW040
K A
WHITE-57MCD 2MA
SM
VF_AVG = 2.59 V
101 94 93 92
PP3V8_AON
19 56 89
SOC_DFU_STATUS
IN IN
IN
DBGLED_RETURN
94 93 92
STATUS LEDS (WHITE)
5 33 55 89
PMU_ACTIVE_READY
2
XWW050
NO_XNET_CONNECTION=1
SM
1
NO_XNET_CONNECTION=1
XWW070
XW_SOC_DFU_STATUS
DBG_LED
376S00076
QW050
SSM3K16CTAP
SOT883L
1
VGS_MAX 10 V
VTH_MAX 0.9 V
DBG_LED
RW050
2
3
1/20W
2 1
DSW050_D DSW050_R
5%
MF
201 201
DBG_LED
DSW050
K A
WHITE-57MCD-2MA
SM
2
DBG_LED
376S00076
QW070
SSM3K16CTAP
SOT883L
1
VGS_MAX 10 V
VTH_MAX 0.9 V
3
DSW070_R
DBG_LED
RW070
5%
1/20W
MF
2 1
2
SM
1
DSW070_D
WHITE-57MCD-2MA
DBG_LED
DSW070
K A
SM
VF_AVG = 2.59 V VF_AVG = 2.59 V
SOC_SW_DBG XW_PMU_ACTIVE_READY
IN
9
DBG_LED
376S00076
QW080
SSM3K16CTAP
SOT883L
1
VGS_MAX 10 V
VTH_MAX 0.9 V
DBG_LED
RW080
2
3
6.8K 6.8K 6.8K
5%
1/20W
MF
201
2 1
DSW080_D DSW080_R
DBG_LED
DSW080
K A
WHITE-57MCD-2MA
SM
DBGLED_RETURN
94 93 92
SYNC_MASTER=T668_MLB SYNC_DATE=07/24/2019
PAGE TITLE
DEBUG: LEDS (3/3)
BOM_COST_GROUP=DEBUG
Page 95
NOSTUFF
w w w . t e k n i s i - i n d o n e s i a . c o m
P3V8AON HIGH BANDWIDTH CURRENT SENSE AMPLIFIER
NO_XNET_CONNECTION=1
DBG_VMAINISNS
RW200
25
IN
P3V8AON_ISNS1_P
NO_XNET_CONNECTION=1
DBG_VMAI I N
100
0.1%
1/16W
0402
2 1
P3V8_PISUM1_NEG
95
T
RW204
25
IN
P3V8AON_ISNS2_P
NO_XNET CONNECTION=1
DBG_VMAINISNS
100
0.1%
1/16W
0402
2 1
TF
RW206
25
IN
P3V8AON_ISNS3_P
100
0.1%
1/16W
0402
TF
2 1
P3V8_PISUM_POS
DBG_VMAINISNS
RW208
05
0 1%
1/16
MF
0402
DBG_VMAINISNS
RW202
301
0.1%
1/16W
0402
P3V8IDIF1_FB_POS
2 1
MF
103S0194
DBG_VMAINISNS
RW210
1.00K
0.1%
1/16W
MF
402
1
2
103S0194
DBG_VMAINISNS
RW209
1.00K
0.1%
MF
PLACE_NEAR=UW200.8:3MM
NOSTUFF
1
CW204
0.01UF
10%
10V
2
X7R
0201-1
DBG_VMAINISNS
DBG_VMAINISNS
1
CW200
0.1UF
10%
16V
2
X7R-CERM
0402
PP5V_DBG_VMAIN_AMPS
DBG_VMAINISNS
1
CW201
1UF
10%
6.3V
2
CERM
402
95
VOLTAGE=5
PPSUPPLY_P3V8AONISNS_AMP2
PLACE_NEAR=UW220.8:3MM
NOSTUFF
1
CW224
0.01UF
10%
10V
2
X7R
0201-1
BG_VMAINISNS
1
CW220
0.1UF
10%
16V
2
X7R-CERM
0402
DBG_VMAINISNS
1
CW221
1UF
10%
6.3V
2
CERM
402
353S3959
UW200
8
5
V+
6
2 1
P3V8IDIF1_FB_R_POS
V-
NOSTUFF
CW202
15PF
CERM
0402
NOSTUFF
CW203
15PF
CERM
0402
2 1
P3V8IDIF1_FB_R_NEG
OPA2350
MSOP
7
4
2 1
5%
50V
2 1
5%
50V
DBG_VMAINISNS
353S3959
P3V8IDIF1_OUT_POS
114S0092
DBG_VMAINISNS
RW212
49.9
1/16W
MF-LF
114S0092
DBG_VMAINISNS
2 1
1%
402
RW211
49.9
1/16W 1/16W
MF-LF
2 1
1%
402 402
DBG_VMAINISNS
RW215
0
2 1
5%
1/20W
MF
0201
NOSTUFF
RW216
0
2 1
5%
1/20W
MF
0201
NOSTUFF
RW217
0
2 1
5%
1/20W
MF
0201
DBG_VMAINISNS
RW218
0
2 1
5%
1/20W
MF
0201
P3V8IDIF1_SW_POS
P3V8IDIF1_SW_NEG
DBG_VMAINISNS
RW220
2K
2 1
0.1%
1/16W
TF
0402
DBG_VMAINISNS
RW221
2K
2 1
0.1%
1/16W
TF
0402
103S00072
DBG_VMAINISNS
P3V8IDIF2_FB_POS
P3V8IDIF2_FB_NEG
DBG_VMAINISNS
103S00072
RW222
10K
0.1%
1/16W
MF
0402
3
2
RW223
10K
0.1%
1/16W
MF
0402
DBG_VMAINISNS
CW222
1.5PF
2 1
+/-0.1PF
50V
C0G
402
103S00072
DBG_VMAINISNS
RW224
2 1
P3V8IDIF2_FB_R_POS
DBG_VMAINISNS
353S3959
10K
0.1%
1/16W
MF
0402
2 1
P3V8IDIF2_OUT_REF
UW220
8
OPA2350
V+
V-
2 1
MSOP
1
4
P3V8IDIF2_FB_R_NEG
DBG_VMAINISNS
CW223
1.5PF
2 1
DBG_VMAINISNS
RW225
10K
0.1%
1/16W
0402
103S00072
2 1
MF
RW240
0
2 1
PP5V_DBG_VMAIN_AMPS
0%
1/16W
MTL-FILM
0402
116S00006
DBG_VMAINISNS
RW241
0
2 1
PP3V8_DBG_VMAIN_AMPS
0%
1/16W
MTL-FILM
0402
116S00006
NOSTUFF
RW228
0
2 1
PP5V_DBG_VMAIN_AMPS
5%
1/20W
MF
0201
NOSTUFF
RW226
0
2 1
PP3V8_DBG_VMAIN_AMPS
5%
1/20W
MF
0201
DBG_VMAINISNS
RW227
0
2 1
5%
1/20W
MF
0201
P3V8IDIF2_OUT
DBG_VMAINISNS
518S0562
JW222
COAX-2.00MM-U.FL
F-ST-SM1
2
1
3
VER-1
95
95
95
95
NO_XNET_CONNECTION=1
DBG_VMAINISNS
P3V8IDIF1_FB_NEG
RW207
25
IN
P3V8AON_ISNS3_N
NO_XNET_CONNECTION=1
DBG_VMAINISNS
100
0.1%
04 2
/16W
TF
2 1
P3V8_PISUM_NEG
RW205
25
IN
P3V8AON_ISNS2_N
NO_XNET_CONNECTION=1
DBG_ MAINISNS
100
0.1%
1/16W
0402
RW201
25
IN
P3V8AON_ISNS1_N
100
0.1
1/16W
0402
TF
TF
2 1
2 1
P3V8_PISUM1_NEG
95
DBG_VMAINISNS
RW203
1/16W
CHAD NOTES:
EFFECTIVE CURRENT SENSE R = 0.4444 MOHM
1 MOHM || 1 MOHM || 4 MOHM
STAGE 1 GAIN = 11.243
301
0.1%
MF
0402
UW200
8
4
OPA2350
MSOP
1
P3V8IDIF1_OUT_NEG
2
V+
3
V-
+/-0.1PF
50V
C0G
402
STUFF THESE TO ENABLE VMAIN SENSE AMP
2 1
NOTE: IF THESE ARE STUFFED, THEN THERE WILL BE
PP5V_S2
104
PP3V8_AON
101
SOME LEAKAGE IN OFF ONTO 5V_S2 THROUGH UW200
<RDAR://57211269>
NOSTUFF
RW2A0
0
2 1
PP5V_DBG_VMAIN_AMPS
0%
1/16W
MTL-FILM
0402
116S00006
NOSTUFF
RW2A1
0
0%
1/16W
MTL-FILM
0402
116S00006
MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000
VOLTAGE=5V
2 1
PP3V8_DBG_VMAIN_AMPS
MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000
VOLTAGE=3.8V
DBG_VMAINISNS
RW230
100
1/16W
MF-LF
95
1%
402
2 1
P3V8IDIFSP_INP
P3V8IDIFSP_FB
95
SYNC_MASTER=T668_MLB SYNC_DATE=06/20/2019
PAGE TITLE
5
V+
6
V-
DBG_VMAINISNS
353S3959
UW220
8
OPA2350
MSOP
7
4
DBG_VMAINISNS
RW231
100
1/16W
MF-LF
402
P3V8IDIFSP_OUT
2 1
1%
DEBUG: P3V8AON ISENSE
STAGE 1 BANDWIDTH ~ 3.38 MHZ
STAGE 1 OUTPUT SCALE = 5.00 MV/A
STAGE 2 GAIN = 10.00
STAGE 2 BANDWIDTH ~ 3.80 MHZ
STAGE 2 OUTPUT SCALE = 50.0 MV/A
BOM_COST_GROUP=DEBUG
2
1
Page 96
20K LIMITS USB MINI-B
w w w . t e k n i s i - i n d o n e s i a . c o m
FROM BACK POWERING MLB
VIT-C CONN
96
96
61 96
BI
61 96
BI
USB2_ATC0_LS_VITAMINC_P
USB2_ATC0_LS_VITAMINC_N
USB2_ATC0_LS_P
USB2_ATC0_LS_N
DEBUG SPI ACE
SEL OUTPUT
VIT-C CONN
96
96
56 89 96
BI
56 89 96
BI
USB_DBG_LS_VITAMINC_P
USB_DBG_LS_VITAMINC_N
USB_DBG_LS_P
USB_DBG_LS_N
DEBUG SPI ACE
SEL OUTPUT
VIT-C CONN
96
96
60 96
BI
57 96
BI
VITC_RTMR_RESET_L
VITC_RTMR_PWR_EN
ATCRTMR0_RESET_1V8_L
USBC0_3V3LDO_EN
SEL OUTPUT
L VIT-C (M)
H TYPE-C (D)
SOC USB DFU MUX
PP3V3_AON
4
1
2
VITAMIN-C:YES
BYPASS=UX410::5MM
10%
10V
0201
1
2
CX410
0.1UF
X5R-CERM
L VIT-C (M)
H TYPE-C (D)
SOC DBG MUX
PP3V3_AON
104
1
2
VITAMIN-C:YES
BYPASS=UX411::5MM
10%
10V
0201
1
2
CX411
0.1UF
X5R-CERM
L VIT-C (M)
H TYPE-C (D)
PARROT DBG MUX
PP3V3_AON
104
1
VITAMIN-C:YES
BYPASS=UX412::10MM
CX415
0.1UF
10%
10V
X5R-CERM
0201
RTMRMUX_OE_L
ITAMIN-C:YES
1
RX422
20K
5%
1/20W
MF
201
2
2
1
2
VITAMIN-C:YES
RX412
20K
5%
1/20W
MF
201
5
M+
4
M-
UX410
PI3USB102EZLE
7
6
8
VITAMIN-C:YES
TQFN-THICKSTNCL
D+
CRITICAL
D-
VITAMIN-C:YES
OE* SEL
3
RX413
20K
5%
1/20W
MF
201
5
M+
4
M
UX411
PI3USB102EZLE
7
6
8
VITAMIN-C:YES
TQFN-THICKSTNCL
D+
CRITICAL
D-
VITAMIN-C:YES
OE* SEL
RX418
20K
5%
1/20W
MF
201
5
M+
4
M-
UX412
PI3USB102EZLE
7
6
8
TQFN-THICKSTNCL
D+
CRITICAL
D-
VITAMIN-C:YES
OE* SEL
PP3V3_AON_DFUMUX
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.1000
9
2UA MAX IDD
VCC
1
Y+
Y-
GND
USB2_ATC0_LS_MUX_P
2
USB2_ATC0_LS_MUX_N
10
61 96
61 96
P3V3_AON_DBGMUX
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.1000
9
2UA MAX IDD
VCC
1
Y+
Y-
GND
3
USB_DBG_LS_MUX_P
2
USB_DBG_LS_MUX_N
10
56 89 96
56 89 96
PP3V3_AON_PRTMUX
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.1000
9
2UA MAX IDD
VCC
1
Y+
Y-
GND
3
60 96
ATCRTMR0_RESET_MUX_1V8_L
2
USBC0_3V3LDO_EN_MUX
10
ATCRTMR0_RESET_1V8_L
USB2_ATC0_LS_P
USB2_ATC0_LS_N
USB_DBG_LS_P
USB_DBG_LS_N
LVL SHFTR
60 96 107
BI
60 96 107
BI
VITAMIN-C:NO
RX414
0
2 1
5%
1/20W
MF
NO_XNET_CONNECTION=1
201
VITAMIN-C:NO
USB2_ATC0_LS_MUX_P
RX416
0
2 1
5%
1/20W
MF
NO_XNET_CONNECTION=1
201
USB2_ATC0_LS_MUX_N
LVL SHFTR
60 96 107
BI
60 96 107
BI
VITAMIN-C:NO
RX415
0
2 1
5%
1/20W
MF
NO_XNET_C NNECTION=1
201
VITAMIN-C:NO
RX417
0
2 1
5%
1/20W
MF
NO_XNET_CONNECTION=1
VITAMIN-C:NO
201
BI
60 96 107
96 107
RX420
0
2 1
ATCRTMR0_RESET_MUX_1V8_L
5%
1/20W
MF
NO_XNET_CONNECTION=1
201
VITAMIN-C:YES
1
RX410
100K
5%
1/20W
MF
201
2
DFUMUX_SEL
VITAMIN-C:YES
1
RX411
100K
5%
1/20W
MF
201
2
KISMUX_SEL
USB_DBG_LS_MUX_P
USB_DBG_LS_MUX_N
DFUMUX_SEL
VITAMIN-C MK2 CONNECTOR
516S1074
SILK_PART=VITAMIN-C
VITAMIN-C:YES
JX401
AA25D-S038VA1
F-ST-SM
40 39
SOC ATC0 DFU
96 96
96
96
96
SOC KIS DBG
96
107 96 60
PP3V8_AON
101
107 96 60
BYPASS=JX401::10MM BYPASS=JX401::10MM
96
07 96 60
107 96 60
96
107 96 60
VITAMIN C:YES
1
CX405
0.1UF
10%
16V
2
X5R-CERM
0201
9
USB2_ATC0_LS_VITAMINC_P
USB2_ATC0_LS_VITAMINC_N
USB_DBG_LS_VITAMINC_P
USB_DBG_LS_VITAMINC_N
VITAMIN C:YES
1
CX406
0.1UF
10%
16V
2
X5R-CERM
0201
TO SOC
1V2 NUB AOP, S2
47K PD ON SOC PAGE
SOC_DOCK_CONNECT
RFU
RFU
RFU
NC
NC
NC
NC
NC
NC
2 1
4 3
6 5
8 7
10 9
12 11
14 13
16 15
18 17
20 19
22 21
24 23
26 25
28 27
30 29
32 31
34 33
36 35
38 37
42 41
1
2
VITAMIN-C:YES
SOC_SOCHOT_L
DFUMUX_SEL
KISMUX_SEL
SOC_DOCK_CONNECT_VITAMINC
NC_DC_MUX_SEL
SWD_SOC_SWDIO
SWD_SOC_SWCLK
NC_DEBUG_JTAG_SOC_TDO
NC_DEBUG_JTAG_SOC_TDI
UART_DEBUGPRT_R2D
UART_DEBUGPRT_D2R
UART_SMC_DEBUGPRT_R2D
UART_SMC_DEBUGPRT_D2R
VITC_RTMR_RESET_L
VITC_RTMR_PWR_EN
PP1V8_S2
PP1V25_S2
PP5V_S2
VITAMIN-C:YES
CX404
2.2UF
20%
25V
X6S-CERM
0402
BYPASS=JX401::5MM
FROM ACE GPIO 7, PMOS OPEN DRAIN
RX491
100
5%
1/20W
MF
201
RX492
10
5%
1/20W
MF
201
1V2 S2
2 1
UPC0_GPIO7
FROM VITAMIN C
GPIO 7, 1V2 S2
2 1
SOC_DOCK_CONNECT_VITAMINC
104
OUT
6 3 89 91 100
96
96
107
56 57
BI
56 57
OUT
107
IN
107
OUT
56 57
IN
56 57
OUT
56 57
IN
56 57
OUT
96
96
1
CX401
0.1UF
10%
16V
2
X5R-CERM
0201
SWD_SOC_SWDIO
SWD_SOC_SWCLK
KOBA
JTAG_SOC_TDO
JTAG_SOC_TDI
SOC UART
SMC UART
VITAMIN-C:YES
1
CX402
0 1UF
10%
16V
2
X5R-CERM
0201
BYPASS=JX401::5MM
56 57 107
IN OUT
96
101
1
VITAMIN-C:YES VITAMIN-C:YES
1
CX403
0.1UF
10%
16V
2
X5R-CERM
0201
BYPASS=JX401::5MM BYPASS=JX401::5MM
SYNC_DATE=02/03/2020 SYNC_MASTER=MANAN_T668_MLB
PAGE TITLE
DEBUG: VITAMIN-C
USBC0_3V3LDO_EN
57 96
VITAMIN-C:NO
RX421
0
2 1
USBC0_3V3LDO_EN_MUX
5%
1/20W
MF
NO_XNET_CON ECTION=1
01
107 96
BOM_COST_GROUP=DEBUG
2
1 5 6
Page 97
3
w w w . t e k n i s i - i n d o n e s i a . c o m
CHARGE
PPVBAT_AON_CHGR_REG
22 89
SOC PCPU
PPVDD_PCPU_AWAKE
101
CY000
3.0PF
+/-0.1PF
25
NP0-C0G
0201
CY010
3.0PF
+/-0.1PF
25V
NP0-C0G
0201
SOC - DISPLAY
PPVDD_DISP_S1
101
25V
0201
1
2
CY081
NP0-C0G
1
2
CY001
3.0PF
+/-0.1PF
NP0-C0G
1
25V
2
0201 0201
CY002
12PF
5%
25V
NP0-C0G
1
CY003
12PF
2
NP0- 0G
5%
25V
0201
1
2
CY080
3.0PF 12PF
+/-0.1PF
NP0-C0G
5%
25V
0201
1
2
SOC - DCS
PPVDD_DCS_S1
101
CY090
3.0PF
+/-0.1PF
25V
NP0-C0G
0201
5%
25V
0201
1
2
CY092
+/- .1PF
NP0- 0G
1
CY091
12PF
2
NP0-C0G
25V
0201
1
CY093
12PF 3.0PF
2
NP0-C0G
5%
25V
0201
1
2
SOC - VDDQL
PP0V6_S1_VDDQL
101
25V
0201
1
2
PLACE_SIDE=BOTTOM
5%
25V
0201
1
2
CY012
3.0PF
+/-0.1PF
NP0-C0G
1
CY011
12PF
2
NP0-C0G
25V
0201
1
CY013
12PF
2
NP0-C0G
5%
25V
0201
1
2
CY014
3.0PF
+/-0.1PF
NP0-C0G
25V
0201
1
2
PLACE_SIDE=BOTTOM
CY015
12PF
5%
25V
NP0-C0G
0201
1
2
CY0A0
3.0PF
+/-0.1PF
NP0-C0G
CY0A1
12PF
NP0-C0G
5%
25V
0201
1
2
CY0A2
3.0PF
+/-0 1PF
NP0-C0G
25V
0201
1
CY0A3
12PF
2
NP0-C0G
5%
25V
0201
1
2
CY0A4
3.0PF
+/-0.1PF
NP0-C0G
25V
0201
1
CY0A5
12PF
2
NP0-C0G
5%
25V
0201
1
2
CY0A6
3.0PF
+/-0.1PF
NP0-C0G
25V
0201
1
CY0A7
12PF
2
NP0-C0G
5%
25V
0201
1
2
CY0A8
3.0PF
+/-0.1PF
NP0-C0G
25V
0201
1
CY0A9
12PF
2
NP0-C0G
5%
25V
0201
1
2
SOC GPU
PPVDD_GPU_AWAKE
101
SOC - SOC
PPVDD_SOC_S1
101
SOC - VDD1
CY020
3.0PF
+/-0.1PF
25V
NP0-C0G
0201
CY030
3.0PF
+/-0.1PF
25V
NP0-C0G
0201
PLACE_SIDE=BOTTOM
1
5%
25V
2
0201
1
5%
25V
2
0201 0201
CY0AI
12PF
NP0-C0G
CY0B5
12PF
NP0-C0G
25V
0201
25V
0201
1
2
1
2
CY0AA
PLACE_SIDE=BOTTOM
5%
25V
0201
1
2
CY022
3.0PF
+/-0.1PF
NP0-C0G
1
CY021
12PF
2
NP0-C0G
25V
0201
1
CY023
12PF
2
NP0-C0G
1
5%
25V
2
0201
PACK_IGNORE=TRUE
CY024
3.0PF
+/-0.1PF
NP0-C0G
25V
0201
1
CY025
12PF 3.0PF
2
NP0-C0G
5%
25V
0201
1
2
CY026
+/-0.1PF
NP0-C0G
1
2
PLACE_SIDE=BOTTOM
CY027
12PF
5%
25V
NP0-C0G
0201
1
2
SOC - ECPU
PPVDD_ECPU_AWAKE
101
3.0PF
+/-0.1PF
NP0-C0G
CY0B0
5%
25V
0201
1
2
CY032
3.0PF 12PF
+/-0.1PF
NP0-C0G
1
CY031
12PF
2
NP0-C0G
25V
0201
1
2
CY033
NP0-C0G
5%
25V
0201
1
2
CY034
3.0PF
+/-0.1PF
NP0-C0G
25V
0201
1
CY035
12PF
2
NP0-C0G
5%
25V
0201
1
CY036
12PF
2
NP0-C0G
5%
25V
0201
1
2
3.0PF
+/-0.1PF
NP0-C0G
CY0AB
12PF
NP0-C0G
CY0B1
12PF
NP0-C0G
5%
25V
0201
5%
25V
0201
1
2
1
2
CY0AC
3.0PF
+/-0 1PF
NP0-C0
CY0B2
3.0PF
+/-0 1PF
NP0-C0G
2 V
0201
25V
0201
1
CY0AD
12PF
2
1
NP0-C0G
CY0B3
12PF
2
NP0-C0G
1
5%
25V
2
0201
1
5%
25V
2
PACK_IGNORE=TRUE
CY0AJ
3.0PF
+/-0.1PF
NP0 C0G
25V
0201
1
2
PLACE_SIDE=BOTTOM
CY0AK
12PF
5%
25V
NP0-C0G
0201
1
2
SOC - 1.2V CIO SOC - 0.88V S1
PP1V8_S2SW_VDD1
104
SOC - DRAM
PP1V06_S2SW_DRAM
101
CY040
3.0PF
+/-0.1PF
25V
NP0-C0G
0201
CY050
3.0PF
+/-0.1PF
25V
NP0-C0G
0201
PP1V2_S2_CIO
103
5%
25V
0201
1
2
CY042
3.0PF
+/-0.1PF
NP0-C0G
1
CY041
12PF
2
NP0-C0G
25V
0201
1
CY043
12PF
2
NP0-C0G
5%
25V
0201
1
CY0C1
12PF
2
NP0-C0G
5%
25V
0201
1
2
SOC - 1.25V S2
102 98
5%
25V
0201
1
2
CY052
3.0PF
+/-0.1PF
NP0-C0G
1
CY051
12PF
2
NP0-C0G
25V
0201
1
CY053
12PF
2
NP0-C0G
5%
25V
0201
1
2
CY054
3.0PF
+/-0.1PF
NP0-C0G
25V
0201
1
CY055
12PF
2
NP0-C0G
5%
25V
0201
1
2
CY056
3.0PF
+/-0.1PF
NP0-C0G
25V
0201
1
CY057
12PF
2
NP0-C0G
5%
25V
0201
1
2
PP1V25_S2
CY0E0
12PF
5%
25V
NP0-C0G
0201
5%
25V
0 01
1
2
1
CY0E1
12PF
2
PLACE_NEAR=U060 .AY23 2MM PLACE_NEAR=U0600.AP39:2MM
NP0-C0
PP0V88_S1
101
103 14
25V
0201
1
2
CY0D0
3.0PF 12PF
+/-0.1PF
NP0-C0G
SOC - VDD_FIXED
PP0V805_S1_VDD_FIXED
CY0F0
3.0PF 12PF
+/-0.1PF
NP0-C0G
0201
25V
CY0D1
5%
25V
NP0-C0G
0201
1
2
CY0F1
1
2
5%
25V
NP0-C0G
0201
25V
0 01
1
CY0F3
12PF
2
NP0-C0G
1
2
CY0F2
3.0PF
+/-0 1PF
NP0-C0
5%
25V
0201
1
2
CY058
SOC - SOC SRAM
PP0V764_S1_SRAM
101
CY060
SOC - CPU SRAM
PPVDD_CPU_SRAM_AWAKE
101
CY070
3.0PF
+/-0.1PF
25V
NP0-C0G
0201
3.0PF
+/-0.1PF
25V
NP0-C0G
0201
3.0PF
+/-0.1PF
25V
NP0-C0G
0201
5%
25V
0201
5%
25V
0201
5%
25V
0201
1
2
1
2
1
2
CY05A
3.0PF
+/-0.1PF
NP0-C0G
CY062
3.0PF
+/-0.1PF
NP0-C0G
CY072
3.0PF
+/-0.1PF
NP0-C0G
1
CY059
12PF
2
1
NP0-C0G
CY061
12PF
2
1
NP0-C0G
CY071
12PF
2
NP0-C0G
25V
0201
25V
0201
25V
0201
1
CY05B
12PF
2
1
NP0-C0G
CY063
12PF
2
1
NP0-C0G
CY073
12PF
2
NP0-C0G
5%
25V
0201
5%
25V
0201
5%
25V
0201
1
2
1
2
1
2
CY05C
3.0PF
+/-0.1PF
NP0-C0G
CY064
3.0PF
+/-0.1PF
NP0-C0G
25V
0201
25V
0201
1
CY05D
12PF
2
1
NP0-C0G
CY065
12PF
2
5%
25V
0201
5%
25V
0201
1
2
25V
0201
1
CY067
12PF
2
NP0-C0G NP0-C0G NP0-C0G
1
2
CY066
3 0PF
+/ 0.1PF
5%
25V
0201
1
2
SOC - VDDIO12 GRP3
PP1V25_AWAKE_GRP3
11
CY0G1
12PF
5%
25V
NP0-C0G
0201
1
2
SOC - VDDIO12 GRP5
PP1V25_AWAKE_GRP5
11
5%
25V
0201
1
2
CY0G3
12PF
NP0-C0G
102 11
SOC - VDDIO12 GRP4
PP1V25_AWAKE_GRP4
11
CY0G2
SOC - VDDIO18 GRP1
PP1V8_AWAKE
CY0G4
12PF
5%
25V
NP0-C0G
0201
12PF
5%
25V
NP0-C0G
0201
1
2
1
2
SYNC_DATE=11/04/2019 SYNC_MASTER=KEI_T668_MLB
PAGE TITLE
DESENSE (1/3)
BOM_COST_GROUP=DESENSE
3 4
2
1
Page 98
P3V8AON VIN
w w w . t e k n i s i - i n d o n e s i a . c o m
PBUS
PPBUS_VMAIN_VIN_ISNS
105
CY110
CY116
3.0PF
+/-0.1PF
25V
NP0-C0G
0201
12PF
5%
25V
NP0-C0G
0201
PPBUS_AON
101
1
CY115
12PF
25V
2
0201 0201
NP0-C0G
5%
25V
0201
1
2
CY112
3.0PF
+/-0.1PF
NP0-C0G
1
CY111
12PF
2
NP0-C0G
25V
0201
1
CY113
12PF
2
NP0-C0G
25V
0201
1
2
CY114
3.0PF
+/-0.1PF
NP0-C0G
5%
25V
1
2
CY160
3 0PF
+/-0.1PF
NP0-C0G
0201
1
CY161
12PF
2
NP0-C0G
5%
25V
0201
1
2
CY162
3.0PF
+/-0.1PF
NP0-C0G
1
CY163
12PF
25V 25V
2
0201 0201
NP0-C0G
5%
25V
1
2
BUCK 13
0201 0201
5%
25V
1
CY1C1
12PF
2
NP0-C0G NP0-C0G
5%
25V
0201
1
CY1C0
12PF
2
1
CY117
12PF
2
NP0-C0G NP0-C0G
5%
25V
1
CY118
12PF
2
5%
25V
1
CY1C2
12PF
2
0201 0201
5%
25V
1
CY1C3
12PF
2
NP0-C0G NP0-C0G
5%
25V
0201
1
102 7
2
PP1V25_S2
CY170
3.0PF
+/-0.1PF
25
NP0-C0G
0201
1
CY171
12PF
2
NP0-C0G
5%
25V
0201
1
2
CY172
3.0PF
+/-0.1PF
NP0-C0G
25V
0201
1
CY173
12PF
2
NP0-C0G
5%
25V
0201
1
2
CY174
3.0PF 12PF
+/-0.1PF
NP0-C0G NP0-C0G
25V
0201
1
2
CY175
5%
25V
0201
1
2
P3V8AON
PP3V8_AON
101
CY120
3.0PF
+/-0.1PF
25V
NP0-C0G
0201
CY126
3.0PF
+/-0.1PF
25V
NP0-C0G
0201
25V
0201
1
CY177
12PF
2
NP0-C0G
CY176
25V
0201
1
CY125
12PF
2
NP0-C0G
1
CY121
12PF
2
NP0-C0G
5%
25V
0201
1
2
CY122
3.0PF
+/-0.1PF
NP0-C0G
1
CY123
12PF
2
NP0-C0G NP0-C0G
5%
25V
0201
1
2
CY124
3.0PF
+/-0.1PF
5%
25V
0201
1
2
CY12A
3.0PF
+/-0.1PF
NP0-C0G
25V
0201
1
CY12B
12PF
2
NP0-C0G
5%
25V
0201
1
2
3.0PF
+/-0.1PF
NP0-C0
5%
25V
0201
1
2
1V8 AON
25V
0201
1
CY12D
12PF
2
NP0 C0G
1
CY127
12PF
2
NP0-C0G
5%
25V
0201
1
2
CY128
3.0PF
+/-0.1PF
NP -C0
2 V
0201
1
CY129
12PF
2
NP0-C0G
5%
25V
0201
1
2
CY12C
3.0PF
+/-0.1PF
NP0-C0G
5%
2 V
0201
1
PP1V8_AON
104
2
CY180
3.0PF
+/-0.1PF
25V
NP0-C0G
0201
1
2
CY181
3.0PF
+/-0.1PF
NP0-C0G
25V
0201
1
CY182
12PF
2
NP0-C0G
5%
25V
0201
1
CY183
12PF
2
NP0-C0G
5%
25V
0201
1
2
5V S2
PP5V_S2
104
CY130
3.0PF
+/-0.1PF
NP0-C0G
0201
5V S2 VIN
PPBUS_AON_5VS2_VIN_ISNS
105
CY140
3.0PF
+/-0.1PF
NP0-C0G NP0-C0G
0201
25V
25V
1
CY131
12PF
2
1
NP0-C0G
CY141
12PF
2
5%
25V
0201
5%
25V
0201
1
2
25V
0201
1
CY143
12PF
2
NP0-C0G
1
2
CY142
3.0PF
+/-0.1PF
NP0-C0G
5%
25V
0201
1
2
DCIN
PPDCIN_AON_CHGR_R
22 89
LCD BACKLIGHT
PPVOUT_LCDBKLT
104
CY190
3.0PF
+/-0.1PF
25V
NP0-C0G
0201
CY1A0
3PF
+/-0.1PF
100V
C0G
0201
131S00140
1
2
1
CY191
3.0PF
+/-0.1PF
NP0-C0G
CY1A1
12PF
2
131S00041
25V
0201
5%
100V
CERM
0402
1
2
1
2
KBD BACKLIGHT
PPVOUT_KBDLED
104
CY150
3PF
+/-0.1PF
100V
C0G
0201
131S00140
1
CY151
12PF
2
131S00041
5%
100V
CERM
0402
1
DCIN
2
PPDCIN_USBC_AON
101
CY1B0
3.0PF
+/-0.1PF
25V
NP0 C0G
1
2
CY1B1
3.0PF
+/-0.1PF
NP0-C0G
0201 0201
25V
1
2
SYNC_MASTER=KEI_T668_MLB SYNC_DATE=09/30/2019
PAGE TITLE
DESENSE (2/3)
BOM_COST_GROUP=DESENSE
2
1
Page 99
3V3 S2
w w w . t e k n i s i - i n d o n e s i a . c o m
MASTER PMU HIGH SIDE INPUT
PP3V3_S2
104
2V5 AWAKE NAND
PP2V5_AWAKE_NAND
101
CY200
3.0PF
+/-0.1PF
25V
NP0-C0G
0201
CY210
3.0PF
+/-0.1PF
25V
NP0-C0G
0201
PP3V8_AON_MPMU_ISNS_VIN
105
1
5%
25V
2
0201 0201
1
5%
25V
2
0201
CY2D1
12PF
NP0-C0G
5%
25V
0201
5%
25V
1
CY2D0
12PF
2
PP1V8_S2
101
25V
0201
1
CY213
12PF
2
1
2
CY212
3.0PF
+/-0.1PF
NP0-C0G
0201 0201
5%
25V
1
2
NP0-C0G
CY2E0
12PF
NP0-C0G
1
CY201
12PF
2
1
NP0-C0G
CY211
12PF
2
NP0-C0G NP0-C0G
5%
25V
1
2
0V88 AWAKESW NAND
PP0V88_AWAKESW_NAND
102
1V25 AWAKESW VCCQ
PP1V25_AWAKESW_VCCQ
102
CY220
3.0PF
+/-0.1PF
25V
NP0-C0G
0201
CY230
3.0PF
+/-0.1PF
25V
NP0-C0G
0201
25V
0201
25V
0201
1
CY223
12PF
2
1
CY233
12PF
2
NP0-C0G
1
CY221
12PF
2
1
NP0-C0G NP0-C0G
CY231
12PF
2
NP0-C0G
5%
25V
5%
25V
1
2
1
2
CY222
3.0PF
+/-0.1PF
NP0-C0G
CY232
3.0PF
+/-0.1PF
NP0-C0G
0201 0201
0201 0201
5%
25V
5%
25V
1
2
1
2
VMAIN SWITH NODE PHASE 1
P3V8AON_VSW1
25
CY240
12PF
5%
25V
NP0-C0G
0201
VMAIN SWITH NODE PHASE 2
P3V8AON_SW2
24 25
CY250
12PF
5%
25V
NP0-C0G
0201
1
2
1
2
VMAIN SWITH NODE PHASE 3
P3V8AON_SW3
24 25
CY260
12PF
5%
25V
NP0-C0G
SYNC_MASTER=KEI_T668_MLB SYNC_DATE=09/30/2019
PAGE TITLE
1
CY261
12PF
2
NP0-C0G
0201 0201
5%
25V
1
2
DESENSE (3/3)
BOM_COST_GROUP=DESENSE
2
1
Page 100
EMC REQUESTS FOR CAPS ON SOME SIGNALS
w w w . t e k n i s i - i n d o n e s i a . c o m
NO-STUFF'ED UNTIL WE GET CONFIRMATION / DATA IF THEY ARE NEEDED
<RDAR://58576418>
PMU_SYS_ALIVE
33 67 8 10
NOSTUFF
1
CZ000
100PF
5%
50V
2
C0G
0201
PMU_RESET_L
5 9 33 74 89 90
SOC_WDOG
9 33
NOSTUFF
1
CZ001
100PF
5%
50V
2
C0G
0201
NOSTUFF
1
CZ002
100PF
5%
50V
2
C0G
0201
SOC_SOCHOT_L
6 33 89 91 96
UPC_PMU_RESET_3V3
34 57 58 90
NOSTUFF
1
CZ003
100PF
5%
V
2
C0G
0201
NOSTUFF
1
CZ004
100PF
5%
50V
2
C0G
0201
SYNC_MASTER=KEI_T668_MLB SYNC_DATE=10/02/2019
PAGE TITLE
EMC
BOM_COST_GROUP=EMC