Apple macbook pro a1229 Schematic

TABLE_TABLEOFCONTENTS_ITEM

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TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

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TABLE_TABLEOFCONTENTS_ITEM

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TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

ANGLES

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

DATE

APPD

ENG

DATE

APPD

CK

ECN

ZONE

REV

DO NOT SCALE DRAWING

X.XXX

X.XX

XX

DIMENSIONS ARE IN MILLIMETERS

THIRD ANGLE PROJECTION

D

SIZE

APPLICABLE

NOTED AS

MATERIAL/FINISH

NONE

SCALE

DESIGNER

MFG APPD

DESIGN CK

RELEASE

QA APPD

ENG APPD

DRAFTER

METRIC

OF

SHT

DRAWING NUMBER

TITLE

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

Apple Computer Inc.

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

DESCRIPTION OF CHANGE

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DRAWING

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

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TABLE_TABLEOFCONTENTS_ITEM

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TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

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TABLE_TABLEOFCONTENTS_ITEM

DVT

04/02/2007

Schematic / PCB #’s

MANTARO

45

12/21/2006

49

T9_NOME

SMC

44

12/21/2006

47

M75_MLB

Left Clutch Barrel Interconnect

43

12/04/2006

46

M75_MLB

External USB Connector

42

12/07/2006

44

M75_MLB

PATA Connector

41

12/04/2006

43

M75_MLB

FireWire Ports

40

03/07/2007

42

M75_MLB

FireWire Port Power

39

12/04/2006

41

M75_MLB

FireWire PHY (TSB83AA22)

38

12/04/2006

40

M75_MLB

FireWire Link (TSB83AA22)

37

12/21/2006

39

M75_MLB

Ethernet Connector

36

03/19/2007

38

T9_NOME

Yukon Power Control

35

01/25/2007

37

T9_NOME

Ethernet (Yukon)

34

(MASTER)

34

(MASTER)

Left I/O Board Connector

33

(MASTER)

33

(MASTER)

Memory Active Termination

32

03/19/2007

32

M75_MLB

DDR2 SO-DIMM Connector B

31

03/19/2007

31

M75_MLB

DDR2 SO-DIMM Connector A

30

03/19/2007

30

M75_MLB

Clock Termination

29

01/25/2007

29

T9_NOME

Clock (CK505)

28

03/19/2007

28

M75_MLB

SB Misc

27

01/25/2007

27

T9_NOME

SB Decoupling

26

01/25/2007

26

T9_NOME

SB Power & Ground

25

04/02/2007

25

M75_MLB

SB Pwr Mgt, GPIO, Clink

24

01/25/2007

24

T9_NOME

SB PCI, PCIe, DMI, USB

23

01/25/2007

23

T9_NOME

SB Enet, Disk, FSB, LPC

22

03/20/2007

22

M75_MLB

NB Graphics Decoupling

21

12/21/2006

21

T9_NOME

NB Standard Decoupling

20

01/25/2007

20

T9_NOME

NB Grounds

19

01/25/2007

19

T9_NOME

NB Power 2

18

01/25/2007

18

T9_NOME

NB Power 1

17

01/25/2007

17

T9_NOME

NB DDR2 Interfaces

16

01/25/2007

16

T9_NOME

NB Misc Interfaces

15

03/19/2007

15

T9_NOME

NB PEG / Video Interfaces

14

01/25/2007

14

T9_NOME

NB CPU Interface

13

01/22/2007

13

T9_NOME

eXtended Debug Port (XDP)

12

12/07/2006

12

M75_MLB

CPU Decoupling & VID

11

01/25/2007

11

T9_NOME

CPU Power & Ground

10

01/25/2007

10

T9_NOME

CPU FSB

9

08/23/2006

9

(T9_MLB)

Signal Aliases

8

(MASTER)

8

(MASTER)

Power Aliases

7

MASTER

7

MASTER

Functional / ICT Test

6

N/A6

N/A

Revision History

5

N/A5

N/A

BOM Configuration

4

N/A4

N/A

Power Block Diagram

3

08/23/2006

3

(T9_MLB)

Power Block Diagram

2

08/23/2006

2

(T9_MLB)

System Block Diagram

GPU (G84M) Constraints

90

107

01/26/2007

M75_MLB

FireWire Constraints

89

106

01/25/2007

T9_NOME

Clock & SMC Constraints

88

105

01/25/2007

T9_NOME

SB Constraints (2 of 2)

87

104

01/25/2007

T9_NOME

SB Constraints (1 of 2)

86

103

01/25/2007

T9_NOME

Memory Constraints

85

102

01/25/2007

T9_NOME

NB Constraints

84

101

01/25/2007

T9_NOME

CPU/FSB Constraints

83

100

01/25/2007

T9_NOME

Inverter Control IC

82

99

01/23/2007

M75_LIO

Inverter Support

81

98

01/23/2007

M75_LIO

M76 Specific Connectors

80

96

(MASTER)

(MASTER)

LVDS Interface Mux

79

95

03/19/2007

M75_MLB

DVI Display Connector

78

94

03/19/2007

M75_MLB

LVDS Display Connector

77

90

03/19/2007

M75_MLB

GPU (G84M) Core Supply

76

89

03/21/2007

M75_MLB

NV G84M Video Interfaces

75

88

03/19/2007

M75_MLB

GPU Straps

74

87

04/02/2007

M75_MLB

NV G84M GPIO/MIO/Misc

73

86

03/19/2007

M75_MLB

GDDR3 Frame Buffer B

72

85

04/02/2007

M75_MLB

GDDR3 Frame Buffer A

71

84

04/02/2007

M75_MLB

NV G84M Frame Buffer I/F

70

82

03/19/2007

M75_MLB

NV G84M Core/FB Power

69

81

03/19/2007

M75_MLB

NV G84M PCI-E

68

80

03/19/2007

M75_MLB

PBus Supply & Batt. Charger

67

79

03/08/2007

M75_LIO

3.425V G3Hot Supply & Power Control

66

78

04/02/2007

M75_MLB

FW PHY Power Supplies

65

77

12/04/2006

M75_MLB

1.5V Power Supply

64

76

03/05/2007

M75_MLB

1.8V DDR2 Supply

63

75

12/04/2006

M75_MLB

1.25V / 1.05V Power Supply

62

74

03/05/2007

M75_MLB

5V / 3.3V Power Supply

61

73

12/04/2006

M75_MLB

IMVP6 NB Gfx Core Regulator

60

72

03/05/2007

M75_MLB

IMVP6 CPU VCore Regulator

59

71

(MASTER)

(MASTER)

Power FETs

58

70

04/02/2007

M75_MLB

DC-In & Battery Connectors

57

69

(MASTER)

(MASTER)

SPI BootROM

56

61

01/25/2007

T9_NOME

Sudden Motion Sensor (SMS)

55

59

12/04/2006

M75_MLB

ALS Support

54

58

12/04/2006

M75_MLB

Current & Thermal Sensors

53

57

(MASTER)

(MASTER)

Fan Connectors

52

56

12/04/2006

M75_MLB

Thermal Sensors

51

55

03/19/2007

M75_MLB

Current Sensing

50

54

03/19/2007

M75_MLB

Current & Voltage Sensing

49

53

03/19/2007

M75_MLB

SMBus Connections

48

52

(MASTER)

(MASTER)

LPC+ Debug Connector

47

51

12/04/2006

M75_MLB

109

92

M75/M76 Rule Definitions

M76_MLB

02/02/2007

16

1

496415ENGINEERING RELEASED

16

?

04/02/07

109

051-7261

SCHEM,MANTARO,M76

1

PCB

CRITICAL820-2132

PCBF,MLB,M76

CRITICAL

SCH

1

051-7261

SCHEM,MLB,M76

LAST_MODIFIED=Mon Apr 2 12:09:31 2007

TITLE=MLB

ABBREV=DRAWING

(.csa)

Sync

Date

ContentsPage

108

91

M76 Specific Constraints

M76_MLB

02/02/2007

ContentsPage Sync

Date

(.csa)

SMC Support

46

50

04/02/2007

M75_MLB

Date

SyncPage

(.csa)

Contents

1

N/A1

N/A

Table of Contents

Preliminary

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

PG 34

EXPRESS CARD

PG 34

EXT-C

USB

CONNS

EXT-B

PG 34

2.5 GHz

3 - X1

Ln6Ln5Ln4

SATA

PG 80

J9660

J4400

Conn

Conn

Pg 42

PATA

Conn

J9000/10

PG 77

LVDS DISP

3.3 V

100 MHz

1.2 V / 1.5 GHz

Ln2 Ln3Ln1SATA-1 SATA-2SATA-0

MUX

PG 75

U9550

LVDS INTERFACE MUX

PG 79

J9400

DVI DISPLAY CONN

PG 78

PG 75

NV G84M FRAME BUFFER I/F

NV G84M

U8000

VIDEO INTERFACES

1.25V - 0.96V

Core

DVI-INTERFACE

PG 70

U8400,U8450,U8500,U8550

PG 71,72

GDDR3 FRAME BUFFER A/B

PCI-EBUS INTERFACE

PG 68

SDVO

x16 PCI-E

Out

AirPort

Mini PCI-E

LIO BOARD

PG 15

800/1066? MHz

LVDSRGB

PG 15

U6200

Codec

Audio

Pg 59

Conn

Pg 37

E-NET

U3700

J3900

(YUKON ULTRA)

Pg 35

ETHERNET

E-NET

Core

Pg 25

PG 23

CLnk 1

PG 25 PG 24

PCI

J4300

FireWire

Pg 41

Conn

J4310

100 MHz

U4000

8-Bit

FW-PHY

Pg 39

Pg 38

TSB83AA22

33 MHz
32-Bit

U4000

FW-Link

TSB83BA22

PG 23

AZALIA

SMB

PG 25

J3100
J3200

DIMM’s

PG 24

PCI-E

PG 23

IDE

PG 23

PG 24

SATA

U2300

Core 1.05V

SB-ICH8

PG 24

PG 25

CLnk 0

SPIDMI

2.5 GHz

x4 DMI

PG 18~22

DMI

PG 16 PG 16

PG 16

CLnk 0

Misc

U6100

89 67

PG 24

5

USB

34 12

0

LPC

GPIOs

PG 25

CONN

EXT-A

PG 43

J4600

USB

Boot ROM

PG 56

SPI

U2900

CLK CHIP

J3400

LEFT I/O

J9610

IR

PG 80

J9660

Bluetooth

PG 80

A

U4900

BSAB,0 BSB

SMC

Pg 46

ADC Fan

Prt

Ser

SUDDEN MOTION SENSOR

J5650/60

POWER SENSE PG 49-50

FAN CONN

PG 52

PG 55

U5900

J9600

Trackpad/Keyboard

Geyser

PG 80

J4731

WWAN

PG 44

J5100

PG 47

LPC Conn

Right Side

Pg 51U5550

U1400

PCI-E

TV

PG 14

NB-GMCH

1.05 - 1.25V

Core

64-Bit

FSB

PG 11,12

Core ~1.2V

PG 10

2.? GHz

Main Memory

PG 16/17

J1300

PG 13

CPU

U1000

533/667/800? MHz

1.8V - 64 Bits

DDR2 - Dual Channel

ITP/XDP CONN

PG31,32

DIMM

J3100
J3200

U2900

CK 505

PG 29

Clocks TERMS

PG 30

PG 57

Conn

GPU

CPU

U5805

DC/Batt

J6990/50

ALS SENS

PG 54

Temp Sense

U5500

Pg 51
Pg 51

U5570

PG 67

Power

Supply

LEFT CLUTCH BARREL INTERCONN

PG 44

CAMERA

PG 23

SYNC_DATE=08/23/2006

System Block Diagram

051-7261

2

109

16

SYNC_MASTER=(T9_MLB)

Preliminary

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Q7850

Q7096

Q7051

Q7012

Q7002

Q7096

DELAY

C=1UF

R=100K

R=100K

Q7051

C=1UF

DELAY

P5VS0_SS

P3V3S0_SS

C=1UF

C=1UF

R=100K

DELAY

P1V25S0_SS

DELAY

P1V8S0_SS

R=100K

SMC_ADAPTER_EN

Q3801

Q7850

Q7081 Q7081

Q3801

Q3800

R=100K

DELAY

C=1UF

PM_ENET_EN

C=1UF

DELAY

PM_GPUP1V8FET_EN

R=100K

ICH8M

U2300

SLP_S4*

GPIO23

SLP_S3*

GPUVCORE_PGOOD

Q7091

PM_SLP_S3_L

EXTGPU_PWR_EN

PM_SLP_S3_LS5V

Q7851

Q7072

Q7851

Q7091

PM_SLP_S4_L

DELAY

R=100K

DELAY

R=100K

C=1UF

C=1UF

Q7012

Q7002

518S0457

DELAY

C=68NF

R=100K
C=68NF

R=100K

DELAY

P3V3S3_SS

P5VS3_SS

P1V25GPU_SS

P3V3GPU_SS

PM_GPUVCORE_EN

PM_ENET_EN

P1V8GPU_SS

P3V3ENET_SS

Q4260

PGOOD

(UNUSED)

TPS51117

U7400

TP1V25ENET_PGOOD

P3V3ENET_SS

EN_PSV

VOUT

VIN

(UNUSED)

PGOOD

TP1V8S3_PGOOD

U7500

TPS511160

VOUT2

(8A MAX CURRENT)

P1V8_S3_IOUT

PP1V8_S3_ISNS

U5440

A

1.5A FUSE

345.203UF

Q7095

A

Q7080

Q7050

P1V8GPU_SS

PP1V8_GPU

P1V8S0_SS

PP1V8_S0

159.36UF

2.1UF

Q3810

728.6UF

PM_SLP_S4_L

PM_SLP_S3_L

ENA2

S3_VTT_EN

S5_EN

1.8V

VIN

0.9V

VOUT1

U7300

3.3V

TPS51120

VOUT2

SMC_PM_G2_EN

PM_GPUVCORE_EN

ENA1

VIN

5V

PGOOD

GPUVCORE_PGOOD

VOUT1

EN_PSV

VIN

U8900

VOUT

U8995

GPUVCORE_IOUT

(5.5A MAX

(8A MAX CURRENT)

CURRENT)

PP3V3_S5

RSMRST_PWRGD

PP5V_S5

PP1V8_S3

PP0V9_S0

2.7UF

Q7070

Q7030

Q7010

A

V

SMC_GPU_VSENSE

675UF

(18A MAX CURRENT)

PPVCORE_GPU

Q7020

Q7000

J6990

CRITICAL

518S0456

J6950

CRITICAL

87438-1043

PP18V5_DCIN

VIN

BATT_POS

VOUT

PP18V5_G3H_CHGR

8A FUSE

A

LIO_DCIN_ISENSE

PPVBATT_G3H_FET

ENABLES

VIN

ISL6255A

BATTERY CHARGE

BATTERY CHARGER

PBUS SUPPLY /

CHGR_EN

(PAGE 67)

U7900

(PAGE 67)

FET

VOUT

PPVBAT_G3H_CHGR_OUT

U5705

A

M76 POWER SYSTEM ARCHITECTURE

384.1UF

PP1V25_S0

PP5V_S5

P3V3S3_SS

P5VS3_SS

P5VS0_SS

P3V3S0_SS

P1V25S0_SS

P3V3GPU_SS

P3V3ENET_SS

PPVP_FW

PPVIN_FW_3.3VFW

EN

VIN

VIN

SHDN*

LT3470

U7700

22.1UF

6.102UF

PP3V3_ENET

Q7090

P1V25GPU_SS

IN
EN

U3850

VOUT

TPS79501

(PAGE 36)

VOUT

1UF

PP1V9_ENET

PP1V25_GPU

U7720

TPS799195

VOUT

PP3V3_FW

PP1V95_FW

27.11UF

4.2UF

81.3UF

LTC2900

U9590

V4(1.25V)

V3(1.8V)

V2(3.3V)

V1(5V)

3.91UF

PP3V3_GPU

PP3V3_S3

7.2UF

3.4UF

PP3V3_S0

PP3V3_S5

165UF

PP5V_S0

5.9UF

IMVP_VR_ON

VR_ON

ISL9504

CPUVCORE

GFX_VR_EN

V1(3.3V)

V4(1.25V)

V3(1.8V)

V2(3.3V)

PGOOD

RST*

PM_ALL_GPU_PGOOD

4B2
4B1

VR_ON

U7200

VIN

ISL6263

PGOOD

VIN

U7100

VOUT

CLKEN#

VR_PWRGOOD_DELAY

VR_PWRGD_CLKEN_L

U5400

VOUT

U5410

A

A

CPUVCORE_IOUTV(44A MAX CURRENT)

PPVCORE_SO_NB_GFX

(10A MAX CURRENT)

NBGFXCORE_IOUT

U7870

LTC2900

PANEL/BACKLIGHT CONTROL MUX

(0.2A MAX CURRENT)

LVDSCTRLMUX_SEL_GPU_L

U9560

74CBTLV3257

PM_ALL_NBGFX_PGOOD

PLATFORM,CPU RESET

BATTERY ONLY

ACIN WITH/WITHOUT BATTERY

NO AC/BATTERY

BATTERY ONLY,PRESS PWR BUTTON

S0 CPU POWER ON

RST*

U7885

VR_PWRGOOD_DELAY

S0PWRGD_OK

S0 SYSTEM POWER ON

IMVP_VR_ON

SIGNAL DELAY TIME

S3 POWER ON

S5 POWER ON

G3H POWER ON

PWR/RST STATUS

S0_PGOOD_PWROK

7ms

200ms

99ms

STEP

H(S5 ON)

H(S5 ON)

14-18
17,19-24
25-27

BATTERY ONLY:

ADAPTER IN :

L(S5 OFF)

L(S5 OFF)

STEP 06 (S5 POWER STATUS)TRUTH TABLE

01,05-09

01-04

10-13

POWER ON SEQUENCE LIST

PM_SLP_S5_L

PM_SLP_S4_L

PM_SLP_S3_L

08-1

05

PM_SLP_S3_L(P93)

PM_SLP_S4_L(P94)

PM_SLP_S5_L(P95)

U4900

(PAGE 45)

P17(BTN_OUT)

RST*

PWR_BUTTON(P90)

S

4A

PM_ALL_S0_PWRGD

PM_ALL_GFX_PGOOD

U7880

1323.67UF

PPVCORE_SO_CPU

1720UF

U2840

U2830

VR_PWRGD_CLKEN

ALL_SYS_PWRGD

RSMRST_PWRGD

SMC_ONOFF_L

RSMRST_IN(P13)

PWRGD(P12)

PWROK
CL_PWROK

SMC

U1400

RSMRST_OUT(P15)

99ms DLY

IMVP_VR_ON(P16)

PLT_RST*

RESET*

HCPURST*

U1000

MCH

PM_SB_PWROK

PWROK

VRMPWRGD

CLPWROK

CPU

CPUPWRGD(GPIO49)

PWRGOOD

ICH8M

U2300

RSMRST*

PLTRST*

PWRBTN*

PM_SLP_S3_L

SMC_PBUS_VSENSE

EN_PSV

VIN

1.5V

U7600

TPS51117

PGOOD

VOUT

V

Q5315

352.31UF

PP1V5_S0

(8A MAX CURRENT)

PM_SLP_S3_L

EN_PSV

SMC_CPU_VSENSE

P1V5P1V05S0_PGOOD

VIN

U7450

TPS51117

1.05V

VOUT

PGOOD

A

U5420

SHDN*

VIN

3.425V"G3HOT"

NBCORE_IOUT

LT3470

U7800

(PAGE 66)

536.54UF

VOUT

SMC RESET "BUTTON"

(PAGE 46)

(0.2A MAX CURRENT)

PPVCORE_S0_NB_R

RN5VD30A-F

PP3V42_G3H

1175.81UF

PP1V05_S0

U5000

VOUT

SMC_RESET_L

(10A MAX CURRENT)

CPU_PWRGD

FSB_CPURST_L

IMVP_VR_ON

PM_RSMRST_L

PLT_RST_L

PM_PWRBTN_L

10

28

26

27

0.02UF

PP5V_S3

LIO_DCIN_ISENSE

TPS51117

418.1UF

PP1V25_ENET

U5430

P1V25_S0GPU_IOUT

PPBUS_FW_FWPWRSW_F

PGOOD

87438-0832

INRUSH LIMITER

U5705

Q6950

(PAGE 57)

(PAGE 76)

(PAGE 61)

(PAGE 63)

(PAGE 62)

(PAGE 65)

(PAGE 65)

(PAGE 66)

(PAGE 79)

(PAGE 79)

(PAGE 60)

(PAGE 59)

(PAGE 64)

(PAGE 62)

PPBUS_G3H

PPDCIN_G3H

Power Block Diagram

SYNC_DATE=08/23/2006

051-7261

16

109

3

SYNC_MASTER=(T9_MLB)

Preliminary

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Power Block Diagram

051-7261

16

109

4

SYNC_MASTER=N/A

SYNC_DATE=N/A

Preliminary

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Module Parts

Alternate Parts

Bar Code Labels / EEE #’s

M76 BOM Groups

BOM Variants

PCBA,MANTARO4,CTO,VRAM-HY,M76

M76_COMMON,CPU_2_4GHZ,FB_256_HYNIX,M76_CTO,EEE_XZ7

630-8733

COMMON,ALTERNATE,M76_COMMON1,M76_COMMON2,M76_DEBUG,M76_PROGPARTS,ISL6257H

M76_COMMON

EXTGPU_RST_HW,GPU_TMP401,ISL9504B,LVDS_SEL_RESUME,ONEWIRE_PU

M76_COMMON1

M76_COMMON,CPU_2_4GHZ,FB_256_HYNIX,INV_BYPASS,EEE_XWU

630-8549

PCBA,MANTARO2,BTR,VRAM-HY,M76

PCBA,MANTARO3,CTO,VRAM-SAM,M76

M76_COMMON,CPU_2_4GHZ,FB_256_SAMSUNG,M76_CTO,EEE_XZ6

630-8732

P1V8S3_1V825_GPUFB,SLG2AP101,SMS_MOT_DIS,YUKON_ULTRA,VGA_TERM_CONN

M76_COMMON2

M76_CTO

INV_SPLIT,INV_17INCH

SMC_DEBUG_YES,XDP,XDP_CONN,LPCPLUS

M76_DEBUG

BOOTROM_PROG,SMC_PROG

M76_PROGPARTS

SYNC_MASTER=N/A

BOM Configuration

5

051-7261

16

109

SYNC_DATE=N/A

PCBA,MANTARO1,BTR,VRAM-SAM,M76

M76_COMMON,CPU_2_4GHZ,FB_256_SAMSUNG,INV_BYPASS,EEE_X6P

630-7943

FB_256_HYNIX

VRAM_256,VRAM_HYNIX,VRAM_256_HYNIX

IC,NB,CRESTLINE,GM,C0,QS

338S0426 CRITICAL

1

U1400

IC,SMC,DEVELOPMENT,M76

341S2050

U4900

CRITICAL

1

SMC_PROG

Inductor alternate

152S0476 152S0276

ALL

ALL

AOS alternate to Siliconix Si4413

376S0466376S0543

ALL

353S1681

TI alternate to National

353S1294

ALL

376S0451

Fairchild FDW252P alternate to IRF7707

376S0526

Murata alt to Samsung 22uF acoustic caps

138S0603

ALL

138S0602

IC,88E8058,GIGABIT ENET XCVR,64P QFN

338S0386

1

U3700

CRITICAL

IC,68 PIN,CK505,LOW POWER CLOCK GENER

359S0127

1

CRITICAL

U2900

SLG8LP537

IC,ISL9504,SYNC REG CTRL,2PHAS,QFN48,LF

353S1461 ISL9504A

1

CRITICAL

U7100

826-4393 CRITICAL

EEE_X6P

1

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEE:X6P]

826-4393

1

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

EEE_XWU

[EEE:XWU]

1

826-4393 CRITICAL

[EEE:XZ6]

EEE_XZ6

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL826-4393

1

[EEE:XZ7]

EEE_XZ7

LBL,P/N LABEL,PCB,28MM X 6 MM

338S0388 CRITICAL

1

U8000

IC,GPU,NV G84M,BGA

IC,SMC,HS8/2116

338S0274

1

CRITICAL

U4900

SMC_BLANK

IC,SLG2AP101,LW PWR CLK GEN,CK505,QFN68

359S0130

1

U2900

CRITICAL

SLG2AP101

IC,ISL9504B,2PH IMVP6 REG,PMON,QFN48

353S1651

1

U7100

CRITICAL ISL9504B

IC,SB,ICH8M,B1,QS,BGA

338S0427

1

CRITICAL

U2300

ALL

157S0030157S0011

E&E alt to TDK/BiTech magnetics

IC,EFI ROM,DEVELOPMENT,M75

341S2002 CRITICAL

U6100

BOOTROM_PROG

1

1

IC,16MBIT 8-PIN SPI SERIAL FLASH,SOIC8

335S0384 CRITICAL

U6100

BOOTROM_BLANK

1

337S3458 CRITICAL

U1000

CPU_2_4GHZ

IC,MDC,SR,E1,QS,2.4G,35W,800FSB,4M,BGA

U8400,U8450,U8500,U8550

VRAM_256_HYNIX

CRITICAL

4

333S0401

IC,SGRAM,GDDR3,16MX32,700MHZ,136 FBGA

IC,SGRAM,GDDR3,16MX32,700MHZ,136 FBGA

VRAM_256_SAMSUNG

CRITICAL

U8400,U8450,U8500,U8550

4

333S0382

VRAM_256,VRAM_SAMSUNG,VRAM_256_SAMSUNG

FB_256_SAMSUNG

Preliminary

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

3/5/07 -- Changed 1.8V supply feedback resistors R7520 to 21.5K 0.1% and R7521 15.0K 0.1%.%

- FB: Changed FB VREF caps to 2x0.0047uF as required by Nvidia PUN 02736-001-v07 (which requests 1x0.01uF)

- GPU Vcore: Updated setpoints for GPU Vcore based upon Nvidia Vmin (i.e. 1.05V, 1.05V, 1.05V, 1.125V)

Changes since previous major release (13.5.0):

Change 48660 by cerickso@m75_mlb_051-7225_13.5.0_tmp.Ecad on 2007/03/19 20:17:1Changes since previous major release (13.4.0):

13.3.0

15.4.0

15.3.0

15.2.0

15.0.0

Change 49919 by cerickso@cerickso_m75.Ecad on 2007/03/28 14:28:29

3/26/07 -- Removed C7930 and R7903 for space reasons.

3/22/07 -- Added Q7970 for potential battery inrush current.

3/21/07 -- <rdar://problem/5073301> M76: Change GPU Vmin

3/29/07-- Moved XW7580 to XW0980, and R7580 to R0980.

- GPU Straps: Added PCI_DEVID<3..0> pullup straps

Changes since previous fab release (14.0.0):

3/28/07 -- Integrated m75/mlb CSA pg. 87 through

Changed table text notes.

Changed R8925 to 16.9K.

Changed R8924 to 28K.

Removed NOSTUFF BOM option from R8924.

3/21/07 -- <rdar://problem/4838347> EMC - M76 MLB changes

3/21/07 -- Integrated m75/mlb CSA pgs. 84,85 & 89 through:

This fab release is for DVT!

14.8.0

3/31/97 --Added C9951 B2 case size as placeholder for new cap for acoustic noise per Flo Kim.

3/31/97 -- Changed C9950 from 22uF to 10uF for acoustic noise per Flo Kim.

3/28/07 -- Added XW7580 and R7580 for option to tie 1.8V S3 regulator feedback point to input of 1.8V GPU FET.

3/28/07 -- Change BOM option for 1.8V regulator feedback to 1.8V GPU FET input.

3/22/07 -- Added D7903 for voltage ripple on ISL6257 BOOT and PHASE pins.

3/22/07 -- Items relating to <rdar://problem/5061583> Task: Current Surge When Insert Battery Without AC Plugged-In

Changed resistors for M76 Vcore setpoints (i.e. 1.05V, 1.05V, 1.125V, 1.25V)

Change BOM option on L4764 to OMIT and added BOM table entry for 0 ohm resistor at L4764.

Change 48885 by cerickso@m75_mlb_051-7225_14.0.0_tmp.Ecad on 2007/03/20 21:27:14

- Power Control: Tied all 4 5V/3.3V enables (EN1, EN2, EN3 and EN5) together as part of PM_G2_EN

- LVDS Connector: Changed pin 5 of connector from NC to PP3V3_SW_LCD (in case we add extra cable for power - rdar://5024882)

- NB GFX Decoupling: Added R2260 (0.3 ohm, 0603) to bring ESR of regulator output cap in spec (rdar://5000272)

- NB GFX Core: Changed Vcore controller to ISL6263B (part consolidation effort between Apple/Intersil - rdar://5009109)

- GPU FB: Changed unterminated-mode reference voltage to 40% (R8297 -> 1.02k, R8432/82, R8532/82 -> 2.21K)

- Thermal Sensors: Updated topology of EMC1033 filter caps (added C5515 next to IC, moved other caps to connectors)

- FireWire Ports: Changed D4260 to PDS540 for higher current capacity

- SB GPIOs: Changed R2514 from pulldown to pulldown to correct auto power-on issue (Linda card detect GPIO)

Change 47192 by cerickso@m75_mlb_051-7225_12.7.0_tmp.Ecad on 2007/03/06 18:36:54

3/05/07 -- Integrated m75/mlb pages 22,25,28,30-32,50,53-55,72,74,76,78,80-82,84-90,94,95 through:

14.6.0

Changes since previous major release (13.3.0):

14.7.0

Deleted R7525 and made C7525 0805 size, still 0.1uF (132S0201).
Deleted R7615 and made C7615 0603 size, still 0.1uF (132S0100).
Deleted R8915 and made C8915 0603 size, still 0.1uF (132S0100).
3/19/07 -- Changes to low voltage inverter for M76 piezo.
L9950 changed from 152S0527 (15uH, 2.8A, 115mOhm) to 152S0585 (22uH, 2.8A, 129mOhm).

3/19/07 -- Integrated m75/mlb CSA pgs. 55 & 78 through:
Change 48590 by cerickso@m75_mlb_051-7225_13.4.0_tmp.Ecad on 2007/03/19 14:26:14

- Thermal Sensors: Updated U5500 power alias to indicate device should be on S3 rail

- Power Control: Added U7858 to level shift PM_G2_EN to 3.42V to 5V
3/19/07 -- Updated SMC A SMBus information for Left I/O Board and Top-Case.
3/19/07 -- Deleted R7324 and made C7324 0603 size, still 0.1uF (132S0100).

3/19/07 -- Added three 0603 0 ohm resistors R4740-R4742 for EMC return current path.
3/19/07 -- Battery charge current limit circuit changes for max charge current of 4.5A.
3/19/07 -- Integrated m75/mlb CSA pgs. 22 & 78 through:

3/5/07 -- Removed RX3920-RX3927.

13.2.0

13.4.0

14.0.0

Cleaned up unused aliases.

14.1.0

14.2.0

14.5.0
3/19/07 --

3/19/07 --

Changes since previous bom release (12.0.0):

- GPU FB: Changed cal resistors per NVidia PUN (R8290 to 45.3 ohm and R8291 to 24.9 ohm)

- Power Sequencing: Removed U7885/C7885 to take GFX_PGOOD out of PWR_OK chain (rdar://4974927)

- GPU Vcore: NO STUFFed all PWRCTL related components (feature not to be supported)

- GPU Vcore: Updated voltage setpoints to 1.000/1.070/1.125V

- SB GPIOs: Sync’d page25.csa to T9_MLB to get pullup updates

3/5/07 -- Added GPU Vcore VFB resistor BOM table and GCORE_M76 BOM Option to M76_COMMON BOM group.

3/5/07 -- FireWire: Changed to Rev C of TI FireWire MCM (APN: 338S0435)
3/5/07 -- ODD Conn: Changed ODD power FET to FDC606P (from FDC638P) for reduced Rds(on)

3/07/07 -- Integrated m75/mlb pages 25,42,70 through:

Changes since previous major release (12.6.0):

3/07/07 -- Q7080 PP1V8_GPU FET changed for lower Rds on from FDM6296 to RJK0301DPB

3/08/07 -- Battery charge current limit circuit changes.

3/08/07 -- Changed R9950 from 220K to NOSTUFF to improve current and voltage asymmetry ratio.

3/08/07 -- Integrated CSA pg. 55 through:
Change 47450 by cerickso@m75_mlb_051-7225_12.8.0_tmp.Ecad on 2007/03/08 10:49:26
Changes since previous major release (12.7.0):

- Thermal Sensors: Added R5515/R5516 in case low pass filter is needed for EMC1033
3/08/07 -- Integrated CSA pg. 79 through:
Change 47440 by xyang@m75_lio_051-7226_7.9.0_tmp.Ecad on 2007/03/08 10:25:46
Changed Charger PWM limit resistor according to MARC K.’S M70 values

3/12/07 -- Added BOM option P1V8S3_1V825 to M76_COMMON2 BOM group.
3/12/07 -- Modified R7520 and R7521 to use symbols for 0.1% resistors.
Removed OMIT BOM option from R7521.
Changed BOM options for R7520 to choose between 1.8V or 1.825V 0.1% resistors.

3/14/07 -- Removed BOM option for HDCP as feature is removed.

3/14/07 -- Constraints: Constrained WWAN_SIM signals to 50 ohms
3/14/07 -- Integrated m75/mlb CSA pages 55 & 78 through:
Change 48122 by cerickso@cerickso_m75.Ecad on 2007/03/14 15:27:36

- Power Control: Corrected alias connections for 5V/3V3 S5 enable signals

3/14/07 -- Moved =PP1V8_S0_P1V8S0FET from PP1V8_S3_ISNS to PP1V8_S3.

3/15/07 -- Changes to low voltage inverter for M76 piezo.

Integrated m75/mlb CSA pgs. 28,30-32,50,53-55,80-82,84-88,90,94,95 through:
Change 48405 by cerickso@m75_mlb_051-7225_13.3.0_tmp.Ecad on 2007/03/16 12:18:46
Changes since previous major release (13.2.0):

3/19/07 --Integrated t9/mlb_noME CSA pgs. 15 & 38 through:
Change 48372 by wferry@wferry_projects.Ecad on 2007/03/16 09:11:01

Page 15: Sync from main-line (renamed LVDS_VREFx nets).
Page 38: Changed Yukon crystal load caps to 18pF per radar://4946795 (really radar://4945362).
3/19/07 -- Added OMIT BOM option to L4731 and L4741.
3/19/07 -- Added BOM table with 0 Ohm 0603 resistors at L4731,L4741.
3/19/07 -- SMBus: moved Remote Temps from SMC B to SMC A in order to use EMC1043-5.

<rdar://problem/5070179> BOM update: boost circuit open causes MLB & SIMM damage (see 5064997)
Deleted R7364 and made C7364 0603 size, still 0.1uF (132S0100).
Deleted R7420 and R7470 and made C7420 and C7470 0603 size, still 0.1uF (132S0100).

3/08/07 -- Removed =PP1V5_S0_NB_VCCD_CRT alias to PP1V5_S0 since VCCD_CRT is GNDed per CRT disable guidelines.

3/08/07 -- Changed R9811 from 15.0K to 14.0K. This is so that M57 inverter and split inverter can use same backlight table.

3/08/07 -- Changed BOM option on R9960 511K from NOSTUFF to INV_SPLIT to improve current and voltage asymmetry ratio.

3/14/07 -- Moved =PP1V8_GPU_P1V8GPUFET from PP1V8_S3_ISNS to PP1V8_S3. This is to remove the current sense resistor from the GPU 1.8V path.

- Thermal Sensors/Aliases: Changed mounting pads of Th2H sensor connector to left clutch chassis gnd

- Thermal Sensors: Moved remote sensor U5500 to SMC SMBus A and S3 power rail to clear I2C addr clash

Quick submit of T9 noME branch. Major release will follow once changes are properly documented in Radar and revision history.

- NB GFX Decoupling/Power Aliases: Connected VCCD_CRT of NB to GND per CRT disable guidelines

DVT

13.1.0:

Change 46833 by cerickso@m75_mlb_051-7225_12.5.0_tmp.Ecad on 2007/03/02 09:49:13
Changes since previous major release (12.3.0):

Changes since previous major release (12.2.0):

- Left Clutch IC: Updated both I-PEX connectors to new APN (part update for shell plating)

- Power Supplies: Replaced APN 152S0511 with 152S0368 (duplicate APNs for same part - rdar://5009109)

- Thermal Sensors: Updated topology of EMC1033 sensors (removed shorts, changed connector caps to 18pF)

SYNC_DATE=N/A

SYNC_MASTER=N/A

16

051-7261

16

109

6

Preliminary

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

FUNC_TEST

FUNC_TEST

FUNC_TEST

FUNC_TEST

FUNC_TEST

Battery Digital Connector

Other Func Test Points

FUNC_TEST

FUNC_TEST

FUNC_TEST

CPU FSB NO_TESTs

NO_TEST

NB NO_TESTs

GPU NO_TESTs

FUNC_TEST

NO_TEST

NO_TEST

ICT Test Points

Request for 3 test points

Request for 2 test points

Fan Connectors

LPC+ Debug Connector

System Validation TPs

FUNC_TEST

Functional Test Points

(HOST_DETECT_L)

Left I/O Power Connector

Request for at least 10 GND test points

FUNC_TEST

per

2 TPs

NOTE: 10 additional GND test points are
called out separately in these notes.

Current Sense Calibration

RTC Battery Connector

Inverter Connector

IR & Sleep LED Connector

FUNC_TEST

6 TPs, 2 with each of above TP pairs

Left Clutch Barrel Connector

FUNC_TEST

Thermal Diode Connectors

Left ALS

FUNC_TEST

I404

I405

I406

I407

I408

I409

I410

I411

I412

I413

I414

I415

I416

I417

I418

I419

I420

I421

I422

I423

I424

I426

I427

I428

I430

I431

I432

I433

I436

I442

I443

I447

I448

I490

I491

I492

I493

I494

I495

I496

I497

I498

I506

I507

I509

I515

I516
I517

I519

I520

I521

I522

I523

I524

I529

I530

I531

I533

I534

I535

I536

I539
I540

I541

I542

I544

I545

I546

I547

I548

I549

I550
I551

I552

I553

I554

I555

I556

I557

I558 I559

I561

I562

I563

I564

I565
I566

I567

I568

SYNC_DATE=MASTER

SYNC_MASTER=MASTER

7

109

16

051-7261

Functional / ICT Test

TRUE

GND

GND

TRUE

TRUE

GND

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

TRUE

HSTHMSNS_D_N

TRUE

HSTHMSNS_D_P

RSFSTHMSNS_D_P

TRUE

RSFSTHMSNS_D_N

TRUE

CPUTHMSNS_D2_N

TRUE

TRUE

CPUTHMSNS_D2_P

SMC_RESET_L

TRUE

SMC_NMI

TRUE

TRUE

LINDACARD_GPIO

ISENSE_CAL_EN

TRUE

TRUE

=PPVCORE_GPU_REG

TRUE

=PP5V_S3_IR

TRUE

LCDBKLT_PWM

TRUE

=PPVCORE_S0_CPU_REG

TRUE

=PPVCORE_S0_NBGFX_REG

TRUE

=PP5V_S0_ISENSECAL

PP5V_SW_LCDBKLT

TRUE

=GND_CHASSIS_INVERTER

TRUE

TRUE

USB_IR_N

NB_CLK100M_PCIE_P

TRUE

PPBUS_S0_LCDBKLT_FUSED

TRUE

TRUE

FSB_CLK_NB_N
NB_CLKREQ_L

TRUE

NB_CLK100M_PCIE_N

TRUE
TRUE

NB_CLK96M_DOT_P

TRUE

CPU_THERMTRIP_R

NB_CLK100M_DPLLSS_N

TRUE

NB_CLK100M_DPLLSS_P

TRUE

TRUE

NB_CLK96M_DOT_N

GPU_RESET_L

TRUE

NB_RESET_L

TRUE

TRUE

PP5V_S3_CAMERA_F

TRUE

PPVBATT_G3_RTC

=PPBUS_G3H_LIO_CONN

TRUE

PP18V5_DCIN

TRUE

SMC_TCK

TRUE

CPU_PWRGD

TRUE

PM_DPRSLPVR

TRUE
TRUE

CPU_DPSLP_L

TRUE

P1V5P1V05S0_PGOOD

TRUE

CPU_DPRSTP_L

PM_ENET_EN

TRUE

TRUE

PM_SLP_S5_L

PM_S4_STATE_L

TRUE

CPU_DPSLP_L

TRUE

TRUE

PM_BMBUSY_L

TRUE

NB_SB_SYNC_L

TRUE

FSB_DPWR_L

TRUE

FSB_CPUSLP_L

TRUE

FSB_CPURST_L

VR_PWRGOOD_DELAY

TRUE

TRUE

VR_PWRGD_CLKEN

TRUE

PM_STPCPU_L

TRUE

SB_RTC_RST_L

TRUE

PM_SB_PWROK

TRUE

PCI_RST_L

LTALS_OUT

TRUE

PM_SUS_STAT_L

TRUE

TRUE

LPC_AD<2>

TRUE

SMC_TX_L

SMC_MD1

TRUE

TRUE

FAN_LT_PWM

TRUE

=BATT_NEG

TRUE

=BATT_POS

TRUE

=SMBUS_BATT_SDA

SYS_LED_ANODE

TRUE

FSB_A_L<31..3>

TRUE

FSB_ADS_L

TRUE
TRUE

FSB_ADSTB_L<1..0>

FSB_DINV_L<3..0>

TRUE
TRUE

FSB_DRDY_L

TRUE

FSB_DSTB_L_N<3..0>

TRUE

FSB_DSTB_L_P<3..0>

TP_GPU_MIOB_CLKIN

TRUE

LVDS_L_DATA_P<0>

TRUE

TRUE

CPU_STPCLK_L

TRUE

FSB_CLK_NB_P

TRUE

PP5V_S3_WWAN_F

USB_CAMERA_F_P

TRUE

TRUE

USB_CAMERA_F_N

TRUE

SMC_LRESET_L

TRUE

PM_STPPCI_L

PM_LAN_ENABLE

TRUE

ALS_GAIN

TRUE

SMC_TDI

TRUE

TRUE

INT_SERIRQ

TRUE

LPC_AD<3>

FWH_INIT_L

TRUE

SMC_TDO

TRUE

SMC_TMS

TRUE

TRUE

LPC_FRAME_L

TRUE

LPC_AD<0>

TRUE

FAN_RT_TACH

TRUE

FAN_RT_PWM

TRUE

PM_CLKRUN_L

LVDS_L_CLK_P

TRUE

TP_GPU_MIOB_CLKOUT_P

TRUE

TP_GPU_MIOB_CTL3

TRUE

TRUE

NC_NB_NC<1..16>

TRUE

FSB_BNR_L

TRUE

FSB_BREQ0_L

FSB_LOCK_L

TRUE
TRUE

FSB_REQ_L<4..0>

TRUE

FSB_HITM_L

FSB_D_L<63..0>

TRUE

PLT_RST_L

TRUE

SMC_RX_L

TRUE

TRUE

PM_SLP_S3_L

FSB_DBSY_L

TRUE

TRUE

PM_RSMRST_L

TRUE

FSB_CLK_CPU_N

TP_NB_NC<1..16>

FSB_HIT_L

TRUE

PCI_CLK33M_LPCPLUS

TRUE

TRUE

USB_WWAN_F_P

SMC_ONOFF_L

TRUE

PM_SYSRST_L

TRUE

USB_WWAN_F_N

TRUE

TRUE

SMC_BS_ALRT_L

TRUE

SMC_TRST_L

TRUE

FAN_LT_TACH

USB_IR_P

TRUE

TRUE

=PP5V_S0_LPCPLUS

TRUE

=PP3V3_S5_LPCPLUS

TRUE

=SMBUS_BATT_SCL

TRUE

LPC_AD<1>

DEBUG_RESET_L

TRUE

BOOT_LPC_SPI_L

TRUE

IMVP_VR_ON

TRUE

IMVP_DPRSLPVR

TRUE

FSB_CLK_CPU_P

TRUE

TRUE

=PP5V_S0_FAN_LT

IMVP6_VID<6..0>

TRUE

83

66

83

83

83

59

83

83

59

47

47

79

47

45

47

76

59

86

88

88

88

88

88

47

23

59

23

23

46

66

23

83

83

14

28

30

28

46

47

46

83

83

83

83

83

83

83 90

83

88

30

54

47

47

47

47

47

47

47

47

90

83

83

83

83

83

83

28

46

40

83

88

83

88

80

45

57

86

47

88

83

91

91

91

46

47

47

49

49

80

82 49

60

49

82

82

80

30

30

29

30

30

30

68

28

57

46

13

25

10

16

66

45

45

10

25

25

14

14

13

16

28

29

28

25

28

54

45

45

45

47

67

67

57

80

14

14

14

14

14

14

14 79

23

30

91

91

45

29

45

45

46

45

45

46

46

45

45

45

79

14

14

14

14

14

14

24

45

36

14

45

30

14

47

91

46

28

91

46

47

80

47

47

57

45

47

47

59

83

30

52

59

51

51

51

51

51

51

45

45

25

45

8

8

81

8

8

8

81

9

24

16

82

14

16

16

88

23

22

22

88

28

16

44

28

8

57

45

10

16

7

66

10

36

25

25

7

16

16

10

10

10

9

25

25

23

9

24

34

25

23

43

45

52

57

57

48

46

10

10

10

10

10

10

10

74

75

10

14

44

44

44

28

25

25

34

45

25

23

47

45

45

23

23

52

52

25

75

74

74

10

10

10

10

10

10

9

43

25

10

25

10

16

10

30

44

45

25

44

45

45

52

24

8

8

48

23

28

24

45

59

10

8

12

Preliminary

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Yukon EC will not be supported

MAX I = 0.36A

"G3Hot" (Always-Present) Rails

"ENET" Rails

MAX I = ?.??A

Chipset "VCore" Rails

"FW" (FireWire) Rails

5V Rails

"GPU" Rails

1.8V-0.9V Rails3.3V-2.5V Rails

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

8

109

16

051-7261

Power Aliases

=PP1V5_S0_CPU

=PP1V5_S0_LIO

=PP1V5_S0_NB_TVDAC

=PP1V5_S0_REG

=PP1V5_S0_SB

=PP1V5_S0_SB_VCC1_5_A

=PP1V5_S0_SB_VCC1_5_A_ARX
=PP1V5_S0_SB_VCC1_5_A_ATX

=PP1V5_S0_SB_VCC1_5_A_USB_CORE

=PP1V5_S0_SB_VCCUSBPLL

PP1V8_S3

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.8V

MAKE_BASE=TRUE

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP1V8_S3_ISNS

=PP3V3_S5_SB_GPIO

=PP3V3_S5_SMBUS_SB_ME

=PP3V3_S5_REG

=PPVCORE_S0_NB_FOLLOW

=YUKON_EC_PP2V5_ENET

=PP3V3_S5_SB_3V3_VCCSUSHDA

=PP3V3_S0_FET

=PP3V3_S0_P3V3S0FET

=PPBUS_S5_FWPWRSW

=PPVIN_S5_CPU_IMVP_VIN

=PPVIN_ENET_P1V25ENET

=PPVIN_S0_GFXIMVP6

=PPVBATT_G3H_LIO_CONN

=PP3V42_G3H_REG

=PP1V8_GPU_FBIO

=PP1V8_GPU_FBVDDQ

=PP1V8_GPU_FB_VDDQ

=PP1V8_GPU_FB_VDD

=PP3V3_GPU_IFPCD_IOVDD

MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

PP3V3_GPU_TMDS

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 mm

=PP3V3_GPU_HDCP

=PP3V3_GPU_VCORELOGIC

=PP3V3_GPU_PWRCTL

=PP2V5_GPU_LTC2900

=PP3V3_GPU_TMDS

=PP3V3_GPU_VGASYNC

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 mm

PP3V3_GPU

MIN_NECK_WIDTH=0.2 mm

=PP1V8_FW_PHYOSC

=PP1V95_FW_PHY

MAKE_BASE=TRUE

VOLTAGE=1.95V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PP1V95_FW

=PPVIN_FW_P1V95FW

=PP3V3_FW_LATEVG

=PP3V3_FW_LATEVG_ACTIVE

=PP3V3_FW_PHY

=PP1V25_S0_FET

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

PP3V3_ENET

=PP5V_S5_SB

=PP5V_S5_P1V05S0

=PP5V_S5_PWRCTL
=PP5V_S5_GPUVCORE

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

PP1V25_S0

VOLTAGE=1.25V

=PPVOUT_ENET_AVDDLDO

PP1V25_ENET

VOLTAGE=1.25V
MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

=PP5V_S5_REG

=PP1V25_ENET_ISNS

=PP3V42_G3H_LIDSWITCH

=PP3V3_GPU_SMBUS_SMC_0_S0

=PP3V3_GPU_VIDEOMUX

=PP3V3_GPU_LVDS_DDC

=PP3V3_GPU_DVI

=PP1V2_GPU_PEX_PLLXVDD

=PP3V3_GPU_MIO

=PP3V3_GPU_VDD33

=PPVP_FW_PORT0

=PPVP_FW_P3V3FW

=PPVP_FW_CPS

PPVP_FW

VOLTAGE=33V

MIN_NECK_WIDTH=0.3 mm

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

=PP5V_S3_WWAN

=PP5V_S0_P5VS0FET

=PP5V_S3_P5VS3FET

=PP5V_S5_P1V8GPUFET

=PP3V42_G3H_SMBUS_SMC_BSA

=PPVIN_G3H_P3V42G3H

=PP5V_S5_P1V25GPUFET

=PP5V_S5_P1V8S0FET

=PP5V_S3_CAMERA

=PP5V_S5_P1V5S0

=PP5V_S0_CPU_IMVP

PPBUS_FW_FWPWRSW_F

MAKE_BASE=TRUE

=PPBU_S0_P3V3FW

=PP3V3_GPU_DAC

=PP3V3_FW_REG

PPVP_FW_PORTB_UF

MAKE_BASE=TRUE

=PPVP_FW_PORT1

PPVP_FW_PORTA_UF

MAKE_BASE=TRUE

=PPVP_FW_SUMNODE

=PPBUS_S5_FW_FET

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

PP3V3_FW

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 mm

=PPVCORE_GPU_REG

=PP3V3_GPU_TMDSBIAS

=PP5V_S0_LCDBKLT

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.3 mm

PPVCORE_S0_CPU

MIN_LINE_WIDTH=0.6 mm
VOLTAGE=1.25V

=PP5V_S0_DVI_DDC

=PPVCORE_S0_NBGFX_REG

=PPVCORE_S0_NB_GFX

=PP5V_S3_IR
=PP5V_S3_TOPCASE

=PP5V_S5_P1V25ENET

=PPVCORE_S0_CPU_REG

=PP1V2_GPU_PEX_IOVDD

=PP1V2_GPU_PLLVDD

=PP1V2_GPU_VID_PLLVDD

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

PP1V25_GPU

VOLTAGE=1.25V

=PP1V2_GPU_FBPLLAVDD

=PP1V25_GPU_P1V25GPUFET

=PP1V05_S0M_NB_VCCAXM

=PP1V05_S0_REG

=PP0V9_S3M_MEM_DIMMVREFB

=PP1V2_ENET_PHY

=PP1V8_S3_REG

=PP5V_S3_FET

=PPVCORE_S0_CPU

MIN_NECK_WIDTH=0.25 mm
VOLTAGE=1.25V
MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 mm

PPVCORE_S0_NB_GFX

MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.25V

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

PP1V25_ENET_ISNS

=PP1V25_S0_P1V25S0FET

=PP1V25_ENET_REG

=PP3V3_GPU_FET

=PP1V25_S0M_NB_PLL

=PP3V3_S5_SB_CLINK1

=PP3V3_S5_SB

=PP3V3_S5_SB_VCCSUS3_3

=PPVIN_GPU_GPUVCORE

=PP3V3_S5_PWRCTL

=PP3V3_S0_SB_PCI

=PPVIN_S0_P1V05S0

=PPVIN_S5_P5VP3V3

=PP5V_S0_FET

MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm

PP5V_S3

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

PP5V_S5

VOLTAGE=5V
MAKE_BASE=TRUE

=PP5V_S0_SB

=PP5V_S0_FAN_RT

=PP5V_S0_ISENSECAL

=PP5V_S0_LPCPLUS

=PP5V_S0_HDD

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V

PP5V_S0

MIN_LINE_WIDTH=0.6 mm

=PP5V_S0_PCIREQFIX

=PP5V_S0_SB_HPD

=PP5V_S0_ODDPWREN

=PP5V_S0_FAN_LT

=PP5V_S0_GFXIMVP6

=PP3V3_S0_SB_VCC3_3_PCI

=PP3V3_S0_SB_VCC3_3_IDE

=PP3V3_S3_P3V3S3FET

=PP3V3_S5_SB_VCCSUS3_3_USB

=PP3V3_S0_LCD
=PP3V3_GPU_P3V3GPUFET

=PP3V3_S3_RTALS

=PP3V3_S3_P1V8ISNS

=PP3V3_S3_TOPCASE

=PP3V3_S3_BT

=PP3V3_S3_SMS

=PP3V3_S5_P1V5P1V05PG

=PP3V3_S5_ROM

=PP3V3_S5_S5PWRGD

=PP3V3_S5_SB_PM

=PP1V25_ENET_ISNS_R

=PP1V8R2V5_ENET_PHY

MAKE_BASE=TRUE

VOLTAGE=1.9V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PP1V9_ENET

=PP3V3_ENET_PHY

=PP0V9_S0M_MEM_TERM

=PP0V9_S3M_MEM_DIMMVREFA

=PP1V05_S0_CPU

=PP1V25_S0_NB_VCC

=PP1V25_S0_NB_PLL

=PP1V25_S0_NB_VCCDMI

=PP1V25_S0M_NB_VCCA

=PP1V25_S0M_NB_VCC

=PP1V25_GPU_FET

=PPVCORE_GPU

MAKE_BASE=TRUE

VOLTAGE=1.2V

PPVCORE_GPU

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

=PP1V2_GPU_VCOREPWRCTL

=PP1V2_GPU_H_PLLVDD

=PP1V2_GPU_PEX_IOVDDQ

=PP1V8_GPU_IFPX

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.8V

PP1V8_GPU

=PP1V05_S0_NB_FOLLOW

PP1V05_S0

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PP0V9_S3_VTTR_BUF

=PPVCORE_S0_NB_R

=PP0V9_S3M_MEM_NBVREFB

VOLTAGE=0.9V
MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm

PPVCORE_S0_NB_R

=PP1V25R1V05_S0_FSB_NB

=PP1V8_GPU_FET

=PP3V3_GPU_TMDS_FET

=PP1V95_FW_LDO

=PP3V3_S0_SB_VCC3_3_VCCPCORE

=PP3V3_S0_SMBUS_SMC_B_S0

=PP3V3_S0_SMBUS_SB

=PP3V3_S0_SMC

=PP3V3_S0_RSTBUF

=PP3V3_S0_SB_PM

=PP3V3_S0_SB

=PP3V3_S0_SB_VCCGLAN3_3

=PP3V3_S0_SB_VCC3_3_DMI

=PP3V3_S0_SB_GPIO

=PP3V3_S0_NB_FOLLOW

=PP3V3_S0_NB_VCCA_PEG_BG

=PP3V3_S0_NB_VCCHV

=PP3V3_S3_SMBUS_SMC_MGMT

=PPDCIN_G3H

=PPVIN_S5_CPU_IMVP

=PP1V25_S0_SB_DMI

=PP1V05_S0_NB_PCIE
=PP1V05_S0_SB_CPU_IO
=PP1V05_S0_SMC_LS

=PP1V25R1V05_S0_NB_VTT
=PPVCORE_S0_NBCOREISNS

=PPVCORE_S0_SB

=PPVCORE_S0_NB

MAKE_BASE=TRUE

VOLTAGE=0.9V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PP0V9_S3_MEM_VREF

VOLTAGE=0.9V

PP0V9_S0

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

=PP3V3_ENET_AVDDLDO

=PP0V9_S3M_MEM_NBVREFA

=PP0V9_S0_VTT_LDO

=PP1V8_S3M_MEM_NB

=PP5V_S5_P1V8DDRREG

=PP3V3_ENET_FET

=PPVIN_S5_P3V3S5

=PPVIN_S5_P5VS5

=PP1V8_S3_FW
=PP1V8_S3M_MEM_A
=PP1V8_S3M_MEM_B
=PP1V8_S3_ISNS_R
=PP1V8_GPU_P1V8GPUFET
=PP1V8_S0_P1V8S0FET

=PP1V8_S3_ISNS

PPDCIN_G3H

MIN_NECK_WIDTH=0.2 mm
VOLTAGE=18.5V

MIN_LINE_WIDTH=0.4 mm

MAKE_BASE=TRUE

=PPBUS_G3H_LIO_CONN

=PPBUS_S5_P1V8GPUFET

=PP1V8_S0_NB_LVDS

=PP1V8_S3M_NB_VCC

=PPBUS_S0_LCDBKLT

=PPVIN_S0_P1V5S0

=PPVIN_S3_P1V8S3

PPBUS_G3H

MIN_NECK_WIDTH=0.25 mm
MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm
VOLTAGE=12.6V

=PPVBAT_G3H_CHGR_REG

=PPVIN_S0_NB_DPLL

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.8V
MAKE_BASE=TRUE

PP1V8_S0

PP1V5_S0

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.25mm

MAKE_BASE=TRUE

=PP1V8_S0_FET

=PP5V_S5_P1V25S0FET

=PP5V_S3_RTUSB

=PP5V_S0_ODD

=PP5V_S0_KBDLED

=PPVCORE_S0_NBGFX_VSEN

=PP3V3_S0_SB_VCC3_3_SATA

=PP3V3R1V5_S0_SB_VCCHDA

=PP3V3_S3_P1V25ISNS

=PP3V3_S3_SMBUS_SMC_A_S3

=PP3V3_S5_SB_USB

MAKE_BASE=TRUE

PP3V3_S5

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm
VOLTAGE=3.3V

=PP3V3_S3_FET

=PP5V_S3_SYSLED

=PP3V3_S3_REMTHMSNS

VOLTAGE=3.3V

PP3V3_S3

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

=PP3V3_S3_PCI

=PP3V3_S3_FW

=PP3V3_S3_P3V3ENETFET

=PPVIN_S5_SMCVREF

MAKE_BASE=TRUE

VOLTAGE=3.42V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP3V42_G3H

=PP3V42_G3H_PWRCTL

=PP3V3_S5_LPCPLUS

=PP3V3_S5_SMC

=PP3V42_G3H_SMCUSBMUX

=PP3V42_G3H_ACIN

=PP3V42_G3H_SB_RTC

=PP3V3_S0_NBCOREISNS
=PP3V3_S0_ALLSYSPG

=PP3V3_S0_LVDS_MUX
=PP3V3R5V_GPU_GPUISENS

=PPSPD_S0M_MEM_A

=PP3V3_S0_GPUCLKGATE

=PPSPD_S0M_MEM_B
=PP3V3_S0MWOL_SB_CLINK0
=PP3V3_S0MWOL_SB_VCCCL3_3
=PP3V3_S0MWOL_SB_VCCLAN3_3
=PP3V3_S0_PBATTISENS
=PP3V3_S0_PDCISENS

=PP3V3_S0_PWRCTL

=PP3V3_S0_TMPSNSR

=PP3V3_S0_CK505
=PP3V3_S0_IDE

=PP3V3_S0_LPCPLUS

=PP3V3_S0_CPUCOREISNS
=PP3V3_S0_NBGFXCOREISNS
=PP3V3_S0_CPUTHMSNS
=PP3V3_S0_GPUTHMSNS
=PP3V3_S0_FAN_LT
=PP3V3_S0_FAN_RT
=PP3V3_S0_IMVP
=PP3V3_S0_GFXIMVP6

=PP3V3_S0_DDC_LCD
=PP3V3_S0_LCDBKLT

=PP3V3_S0_XDP
=PP3V3_S0M_CK505

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

PP3V3_S0

13

76

59

49

12

21

27

22

21

12

27

27

27

27

27

72

72

41

74

49

60

22

80

49

21

12

27

27

49

47

52

27

27

27

11

21

30

27

25

21

19

27

26

21

27

21

18

91

91

58

57

27

27

47

46

67

27

27

30

30

91

11

34

22

64

27

26

26

26

26

26

25

48

61

21

35

26

58

58

40

59

62

60

67

66

70

69

71

71

75

74

76

66

79

74

78

79

39

39

65

41

40

39

58

27

62

66

76

66

36

61

50

80

48

74

79

78

68

73

73

41

65

39

44

58

58

58

48

66

58

58

44

64

59

40 65

75

65

40 41

40

40

40

7

78

81

78

7

18

7

80

62

7

68

73

73

79

70

58

18

62

32

35

63

58

11

58

62

58

21

25

25

26

76

66

24

62

61

58

27

52

7

7

80

66

42

78

42

7

60

26

26

58

26

77

58

54

50

80

80

55

66

56

46

28

50

35

35

33

31

10

21

21

19

21

21

58

69

76

73

68

75

79

21

63

50

16

14

58

74

65

26

48

48

46

28

28

27

26

26

23

21

19

16

48

57

59

26

21

23

46

19

50

26

18

36

16

63

16

63

36

61

61

38

31

32

50

9

58

50

7

58

22

21

82

64

63

49 67

22

66

91

58

58

43

42

54

60

26

26

50

48

24

91

58

46

51

38

38

36

46

66

7

45

43

57

28

50

66

79

76

31

30

32

25

26

26

53

53

66

53

29

42

47

50

50

51

51

52

52

59

60

77

81

13

29

66

Preliminary

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TM Hole

Digital Ground

RAM door (Torx) holes

Top CPU TM "Hole"

Add 8 blind vias per side to GND

Left CPU

Right CPU

Frame holes

TM Hole

TM Hole

TM Hole

Chassis GNDs

Bottom Left GPU

GND_CHASSIS_BATTCONN_HOLE (to the left of DIMM cutout near board edge)

GND_CHASSIS_RIGHT_FAN_NOTCH (to the left of small well on lower board edge near USB)

All holes are plated through holes with two exceptions:

Chassis connection to be made at the mounting hole east of the LVDS connector

Top Right GPU

Thermal Module Holes

Place next to
Q7080 pin 5

Stuff either R7520 or R0980.

OMIT

195R106

ZT0955

1

OMIT

195R106

ZT0965

1

OMIT

235R126

ZT0930

OMIT

235R126

ZT0935

1

OG-503040

SHLD-SM-LF

SH0925

1
2
3

OMIT

195R106

ZT0900

1

OMIT

195R106

ZT0901

1

195R106

OMIT

ZT0985

1

OMIT

195R106

ZT0975

1

OMIT

195R106

ZT0970

1

OMIT

195R106

ZT0980

1

SM

XW0980

1

2

21.5K

0.1%

P1V8S3_1V825_GPUFB

1/16W
MF-LF
402

R0980

1

2

SYNC_DATE=08/23/2006

Signal Aliases

SYNC_MASTER=(T9_MLB)

9

109

16

051-7261

P1V8S3_1V8_GPUFB

R7580

1

CRITICAL103S0192

RES,MTL FILM,21K,0.1,0402,SM,LF

GND

MIN_NECK_WIDTH=0.25mm

MIN_LINE_WIDTH=0.6mm
VOLTAGE=0V

P1V8S3_FB

=GFX_VR_EN
GFXIMVP6_PGOOD
GFX_VID<4..0>

MAKE_BASE=TRUE

TP_MEM_B_A<15>

=GND_CHASSIS_FW_PORT1

=GND_CHASSIS_DVI_BOT

=GND_CHASSIS_FW_PORT0L

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

VOLTAGE=1.8V

P1V8GPU_FB

=PP1V8_GPU_P1V8GPUFET

MAKE_BASE=TRUE

GND_CHASSIS_LVDS

MIN_NECK_WIDTH=0.25mm

MIN_LINE_WIDTH=0.6mm
VOLTAGE=0V

MIN_NECK_WIDTH=0.25 mm

GND_CHASSIS_INVERTER

MAKE_BASE=TRUE

VOLTAGE=0V

MIN_LINE_WIDTH=0.5 mm

=GND_CHASSIS_J5590

=GND_CHASSIS_LEFTCLUTCH

=GND_CHASSIS_DVI_TOP

MIN_LINE_WIDTH=0.5 mm
VOLTAGE=0V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mm

GND_CHASSIS_RTIO

MAKE_BASE=TRUE

GFXIMVP6_VID<4..0>

MAKE_BASE=TRUE

PM_SB_PWROK

MAKE_BASE=TRUE

VR_PWRGOOD_DELAY

PEG_CLK100M_N

PEG_CLK100M_P

=GND_CHASSIS_INVERTER

MAKE_BASE=TRUE

TP_MEM_A_A<15>

MEM_B_A<15>

MEM_A_A<15>

=NB_CLINK_MPWROK

=SB_CLINK_MPWROK

MAKE_BASE=TRUE

SMC_SMS_INT

=GND_CHASSIS_RTUSB

PLT_RST_L

=SMC_SMS_INT

MAKE_BASE=TRUE

PEG_CLK100M_GPU_P

SMC_ENRGYSTR_LDO_EN

MAKE_BASE=TRUE

PM_ALL_NBGFX_PGOOD

GFX_VR_EN

MAKE_BASE=TRUE

PEG_CLK100M_GPU_N

MAKE_BASE=TRUE

=GND_CHASSIS_FW_PORT0U

=GND_CHASSIS_ENET

PBUS_LDO_EN

PLT_RESET_L

GND_CHASSIS_RIGHT_FAN_NOTCH

MIN_NECK_WIDTH=0.25mm

MIN_LINE_WIDTH=0.6mm
VOLTAGE=0V

GND_CHASSIS_RIGHT_FAN_HOLE

MIN_NECK_WIDTH=0.25mm

MIN_LINE_WIDTH=0.6mm
VOLTAGE=0V

GND_CHASSIS_RAMDOOR_HOLE_1

MIN_NECK_WIDTH=0.25mm

MIN_LINE_WIDTH=0.6mm
VOLTAGE=0V

GND_CHASSIS_RAMDOOR_HOLE_0

MIN_NECK_WIDTH=0.25mm

MIN_LINE_WIDTH=0.6mm
VOLTAGE=0V

GND_CHASSIS_LNDACARD_HOLE

MIN_NECK_WIDTH=0.25mm

MIN_LINE_WIDTH=0.6mm
VOLTAGE=0V

GND_CHASSIS_LIOFLEX_HOLE

MIN_NECK_WIDTH=0.25mm

MIN_LINE_WIDTH=0.6mm
VOLTAGE=0V

GND_CHASSIS_DIMM_NOTCH

MIN_NECK_WIDTH=0.25mm

MIN_LINE_WIDTH=0.6mm
VOLTAGE=0V

GND_CHASSIS_BATTCONN_HOLE

MIN_NECK_WIDTH=0.25mm

MIN_LINE_WIDTH=0.6mm
VOLTAGE=0V

GND_CHASSIS_BATTCONN_HOLE

MAKE_BASE=TRUE

=GND_BATT_CHGND

59

79

28

28

28

58

80

25

16

82

24

68

68

63

16

60

16

41

78

41

8

51

44

78

60

7

7

88

88

7

32

31

16

25

55

43

7

45

30

46

79

60

30

41

37

67

81

9

9

67

Preliminary

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

IN
IN
IN

IN

OUT

IN

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

OUT
OUT

OUT

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI

BI
BI
BI

BI
BI
BI

BI

BI

BI
BI

BI
BI
BI
BI
BI

BI

OUT

OUT

OUT

OUT

OUT

IN

IN
IN
IN
IN
IN

IN
IN

IN
IN

OUT

IN
IN

IN

IN

IN
IN

IN

IN

OUT

BI
BI
BI
BI

LOCK*

INIT*

A20M*

A6*

A3*
A4*

A14*

A16*

REQ0*
REQ1*
REQ2*
REQ3*
REQ4*

BCLK1

BCLK0

THERMTRIP*

THERMDA

PROCHOT*

DBR*

TRST*

TMS

TDO

TDI

TCK

PREQ*

PRDY*

BPM3*

BPM2*

BPM1*

BPM0*

HITM*

HIT*

TRDY*

RS2*

RS1*

RS0*

RESET*

IERR*

BR0*

DBSY*

DRDY*

DEFER*

BNR*

RSVD9

RSVD8

RSVD7

RSVD6

RSVD5

RSVD4

RSVD3

RSVD2

RSVD1

RSVD0

SMI*

LINT1

LINT0

STPCLK*

FERR*

ADSTB1*

A35*

A34*

A33*

A32*

A31*

A30*

A29*

A28*

A19*

A18*

A17*

ADSTB0*

A13*

A12*

BPRI*

A20*
A21*
A22*
A23*
A24*

A26*
A27*

A9*

A8*

A7*

A11*

A25*

THERMDC

IGNNE*

ADS*

A10*

A15*

A5*

NC

1 OF 4

CONTROL

THERMAL

XDP/ITP SIGNALS

H CLK

RESERVED

ADDR GROUP0ADDR GROUP1

ICH

DINV1*

D31*

D30*

D25*

D11*
D12*
D13*
D14*

DSTBP0*
DINV0*

D9*

D8*

D7*

D6*

D19*

D18*

DATBP1*

D0*

D32*
D1*
D2*

D5*

D16*

D20*
D21*
D22*
D23*
D24*

D26*
D27*
D28*
D29*

DSTBN1*

GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6

BSEL0
BSEL1
BSEL2

D33*

D34*

D35*

D36*

D37*

D38*

D39*

D40*

D41*

D42*

D43*

D44*

D45*

D46*

D47*

DSTBN2*
DSTBP2*

DINV2*

D48*

D49*

D50*

D51*

D52*

D53*

D54*

D55*

D56*

D57*

D58*

D59*

D60*

D61*

D62*

D63*

DSTBN3*
DSTBP3*

DINV3*

COMP0
COMP1
COMP2
COMP3

DPRSTP*

DPSLP*

DPWR*

PWRGOOD

SLP*

PSI*

D17*

D4*

D3*

DSTBN0*

D15*

D10*

2 OF 4

DATA GRP 3 DATA GRP 2

MISC

DATA GRP 0DATA GRP 1

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NC

LAYOUT NOTE:

MAKE TRACE LENGTH SHORTER THAN 0.5".

COMP0,2 CONNECT WITH ZO=27.4OHM,

MAKE TRACE LENGTH SHORTER THAN 0.5".

COMP1,3 CONNECT WITH ZO=55OHM,

PM_THRMTRIP#
SHOULD CONNECT TO ICH AND
GMCH WITHOUT T (NO STUB)

0.1" AWAY

PLACE TESTPOINT ON
FSB_IERR_L WITH A GND

0.5" MAX LENGTH FOR CPU_GTLREF

REFERENCED TO GND

PLACE C1000 CLOSE TO CPU_TEST4
PIN. MAKE SURE CPU_TEST4 IS

1%
1/16W

54.9

MF-LF
402

R1002

1

2

68

5%
1/16W

402

MF-LF

R1004

1

2

1/16W

1%

MF-LF

1K

402

R1005

1

2

1%

MF-LF

2.0K

1/16W

402

R1006

1

2

1%

MF-LF

1/16W

54.9

402

R1019

27.4

1/16W
MF-LF

1%

402

R1018

1%

MF-LF

1/16W

54.9

402

R1017

1%

MF-LF

1/16W

27.4

402

R1016

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 59 23 16

7

83 23

7

83 14

7

83 14

7

28

83 23 13

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 30

83 30

83 30

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

83 14

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 14

7

83 13

83 13

83 13

83 13

83 13

83 13

83 13 10

28 13

83 59 46

51

83 46 23 16

83 47 23

83 14 13

7

83 14

83 14

83 14

83 14

83 13 10

83 13 10

83 13 10

83 13 10

91 51

88 30

7

88 30

7

83 23

83 23

83 23

83 23

83 23

7

83 23

83 23

0

1/16W
MF-LF

5%

NOSTUFF

402

R1030

1/16W

5%
MF-LF

1K

NOSTUFF

402

R1007

1

2

1/16W

1%

MF-LF

54.9

402

R1003

1

2

1%

MF-LF

1/16W

54.9

402

R1020

54.9

1/16W
MF-LF

1%

402

R1021

54.9

1/16W
MF-LF

1%

402

R1022

83 14

83 14

83 14

83 14

649

1/16W
MF-LF

1%

402

R1023

1/16W

5%

1K

NOSTUFF

MF-LF

402

R1012

1

2

X5R

NOSTUFF

0.1uF

10%
16V

402

C1000

1

2

OMIT

MEROM

FCBGA

U1000

N3
P5
P2
L2
P4
P1
R1

Y2
U5
R3
W6

A6

U4
Y5
U1
R4
T5
T3
W2
W5
Y4

J4

U2
V4

W3
AA4
AB2
AA3

L5

L4

K5

M3

N2

J1

H1

M1

V1

A22
A21

E2

AD4
AD3
AD1
AC4

G5

F1

C20

E1

H5
F21

A5

G6
E4

D20

C4

B3

C6

B4

H4

B1

AC2
AC1

D21

K3

H2

K2

J3

L1

C1
F3
F4
G3

M4

N5

T2

V3

B2

C3

D2
D22

D3

F6

A3

D5

AC5
AA6
AB3

A24
B25

C7

AB5

G2

AB6

OMIT

MEROM

FCBGA

U1000

B22
B23
C21

R26
U26
AA1
Y1

E22
F24

J24
J23
H22
F26
K22
H23

N22
K25
P26
R23

E26

L23
M24
L22
M23
P25
P23
P22
T24
R24
L25

G22

T25
N25

Y22
AB24
V24
V26
V23
T22
U25
U23

F23

Y25
W22
Y23
W24
W25
AA23
AA24
AB25

AE24
AD24

G25

AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21

E25

AC22
AD23
AF22
AC23

E23
K24
G24

M26

H25

N24

U22

AC20

E5
B5
D24

J26

L26

Y26

AE25

H26

AA26

AF24

AD26

AE6

D6
D7

C23
D25
C24

AF26

AF1
A26

1%

MF-LF

1/16W

54.9

PLACEMENT_NOTE=Place R1024 near ITP connector (if present)

402

R1024

SYNC_DATE=01/25/2007

SYNC_MASTER=T9_NOME

109

051-7261

16

10

CPU FSB

XDP_BPM_L<2>

XDP_BPM_L<5>
XDP_TCK

CPU_THERMD_N

=PP1V05_S0_CPU

=PP1V05_S0_CPU

=PP1V05_S0_CPU

=PP1V05_S0_CPU

XDP_TRST_L

XDP_TDI

XDP_TMS

XDP_TDO

XDP_TCK

FSB_A_L<5>

FSB_A_L<15>

FSB_A_L<10>

FSB_ADS_L

CPU_IGNNE_L

FSB_A_L<25>

FSB_A_L<11>

FSB_A_L<7>
FSB_A_L<8>
FSB_A_L<9>

FSB_A_L<27>

FSB_A_L<26>

FSB_A_L<24>

FSB_A_L<23>

FSB_A_L<22>

FSB_A_L<21>

FSB_A_L<20>

FSB_BPRI_L

FSB_A_L<12>
FSB_A_L<13>

FSB_ADSTB_L<0>

FSB_A_L<17>
FSB_A_L<18>
FSB_A_L<19>

FSB_A_L<28>
FSB_A_L<29>
FSB_A_L<30>
FSB_A_L<31>
FSB_A_L<32>
FSB_A_L<33>
FSB_A_L<34>
FSB_A_L<35>
FSB_ADSTB_L<1>

CPU_FERR_L

CPU_STPCLK_L
CPU_INTR
CPU_NMI
CPU_SMI_L

TP_CPU_RSVD0
TP_CPU_RSVD1
TP_CPU_RSVD2
TP_CPU_RSVD3
TP_CPU_RSVD4
TP_CPU_RSVD5
TP_CPU_RSVD6
TP_CPU_RSVD7
TP_CPU_RSVD8
TP_CPU_RSVD9

FSB_BNR_L

FSB_DEFER_L
FSB_DRDY_L
FSB_DBSY_L

FSB_BREQ0_L

CPU_IERR_L

FSB_CPURST_L
FSB_RS_L<0>
FSB_RS_L<1>
FSB_RS_L<2>
FSB_TRDY_L

FSB_HIT_L
FSB_HITM_L

XDP_BPM_L<0>
XDP_BPM_L<1>

XDP_BPM_L<3>
XDP_BPM_L<4>

XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST_L
XDP_DBRESET_L

CPU_PROCHOT_L
CPU_THERMD_P

PM_THRMTRIP_L

FSB_CLK_CPU_P
FSB_CLK_CPU_N

FSB_REQ_L<4>

FSB_REQ_L<3>

FSB_REQ_L<2>

FSB_REQ_L<1>

FSB_REQ_L<0>

FSB_A_L<16>

FSB_A_L<14>

FSB_A_L<4>

FSB_A_L<3>

FSB_A_L<6>

CPU_A20M_L

CPU_INIT_L

FSB_LOCK_L

FSB_D_L<10>

FSB_D_L<15>
FSB_DSTB_L_N<0>

FSB_D_L<3>
FSB_D_L<4>

FSB_D_L<17>

CPU_PSI_L

FSB_CPUSLP_L

CPU_PWRGD

FSB_DPWR_L

CPU_DPSLP_L

CPU_DPRSTP_L

CPU_COMP<3>

CPU_COMP<2>

CPU_COMP<1>

CPU_COMP<0>

FSB_DINV_L<3>

FSB_DSTB_L_P<3>

FSB_DSTB_L_N<3>

FSB_D_L<63>

FSB_D_L<62>

FSB_D_L<61>

FSB_D_L<60>

FSB_D_L<59>

FSB_D_L<58>

FSB_D_L<57>

FSB_D_L<56>

FSB_D_L<55>

FSB_D_L<54>

FSB_D_L<53>

FSB_D_L<52>

FSB_D_L<51>

FSB_D_L<50>

FSB_D_L<49>

FSB_D_L<48>

FSB_DINV_L<2>

FSB_DSTB_L_P<2>

FSB_DSTB_L_N<2>

FSB_D_L<47>

FSB_D_L<46>

FSB_D_L<45>

FSB_D_L<44>

FSB_D_L<43>

FSB_D_L<42>

FSB_D_L<41>

FSB_D_L<40>

FSB_D_L<39>

FSB_D_L<38>

FSB_D_L<37>

FSB_D_L<36>

FSB_D_L<35>

FSB_D_L<34>

FSB_D_L<33>

CPU_BSEL<2>

CPU_BSEL<1>

CPU_BSEL<0>

TP_CPU_TEST6

CPU_TEST4

TP_CPU_TEST3

CPU_TEST2

CPU_TEST1

CPU_GTLREF

FSB_DSTB_L_N<1>

FSB_D_L<29>

FSB_D_L<28>

FSB_D_L<27>

FSB_D_L<26>

FSB_D_L<24>

FSB_D_L<23>

FSB_D_L<22>

FSB_D_L<21>

FSB_D_L<20>

FSB_D_L<16>

FSB_D_L<5>

FSB_D_L<2>

FSB_D_L<1>

FSB_D_L<32>

FSB_D_L<0>

FSB_DSTB_L_P<1>

FSB_D_L<18>
FSB_D_L<19>

FSB_D_L<6>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>

FSB_DINV_L<0>

FSB_DSTB_L_P<0>

FSB_D_L<14>

FSB_D_L<13>

FSB_D_L<12>

FSB_D_L<11>

FSB_D_L<25>

FSB_D_L<30>
FSB_D_L<31>

FSB_DINV_L<1>

TP_CPU_TEST5

13

13

13

13

12

12

12

12

11

11

11

11

83

83

83

83

83

10

10

10

10

13

13

13

13

13

8

8

8

8

10

10

10

10

10

83

83

83

83

83 83

Preliminary

OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT

OUT

VCC

VSSSENSE

VCCSENSE

VID6

VID5

VID4

VID3

VID2

VID1

VID0

VCCA

VCCP

VCC

3 OF 4

VSS VSS

4 OF 4

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

TBD A (Deep Sleep LFM)

TBD A (Sleep LFM)

TBD A (Auto-Halt/Stop-Grant LFM)

Current numbers from Merom for Santa Rosa EMTS, doc #22221.

TBD A (LFM)

TBD A (HFM)

TBD A (Auto-Halt/Stop-Grant HFM)

TBD A (Sleep HFM)

TBD A (Deep Sleep HFM)

TBD A (Deeper Sleep)
TBD A (Enhanced Deeper Sleep)TBD A (Enhanced Deeper Sleep)

TBD A (Deeper Sleep)

TBD A (Deep Sleep SuperLFM)

TBD A (Deep Sleep HFM)

TBD A (Sleep SuperLFM)

TBD A (Sleep HFM)

TBD A (Auto-Halt/Stop-Grant SuperLFM)

TBD A (Auto-Halt/Stop-Grant HFM)

TBD A (SuperLFM)

18.7 A (LFM)

21.0 A (HFM)

23.0 A (Design Target) 17.0 A (Design Target)

Ultra Low Voltage:Low Voltage:

(CPU INTERNAL PLL POWER 1.5V)

(CPU IO POWER 1.05V)

130 mA

(CPU CORE POWER)

Standard Voltage:

44.0 A (Design Target)

41.0 A (HFM)

16.8 A (Sleep SuperLFM)

16.0 A (Deep Sleep SuperLFM)

4500 mA (before VCC stable)
2500 mA (after VCC stable)

9.4 A (Enhanced Deeper Sleep)

25.5 A (SuperLFM)

30.4 A (LFM)

27.4 A (Auto-Halt/Stop-Grant HFM)

17.0 A (Auto-Halt/Stop-Grant SuperLFM)

27.4 A (Sleep HFM)

25.0 A (Deep Sleep HFM)

11.5 A (Deeper Sleep)

83 12

83 12

83 12

83 12

83 12

83 12

1/16W

1%

100

402

MF-LF

PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.

R1101

1

2

83 12

83 59

83 59

OMIT

MEROM

FCBGA

U1000

A7
A9

B9
B10
B12
B14
B15
B17
B18
B20

C9
C10

A10

C12
C13
C15
C17
C18

D9
D10
D12
D14
D15

A12

D17
D18

E7

E9
E10
E12
E13
E15
E17
E18

A13

E20

F7

F9
F10
F12
F14
F15
F17
F18
F20

A15

AA7
AA9

AA10
AA12
AA13
AA15
AA17
AA18
AA20

AB9

A17

AC10
AB10
AB12
AB14
AB15
AB17
AB18

AB20
AB7
AC7

A18

AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12

A20

AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17

B7

AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

B26
C26

G21
V6

R21
R6
T21
T6
V21
W21

J6
K6
M6
J21
K21
M21
N21
N6

AF7

AD6
AF5
AE5
AF4
AE3
AF3
AE2

AE7

OMIT

MEROM

FCBGA

U1000

A4
A8

B11

W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5

B13

AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8

B16

AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11

B19

AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13

B21

AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16

B24

AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19

C5

AF21
A25
AF25

C8
C11
C14

A11

C16
C19

C2
C22
C25

D1

D4

D8
D11
D13

A14

D16
D19
D23
D26

E3

E6

E8
E11
E14
E16

A16

E19
E21
E24

F5

F8
F11
F13
F16
F19

F2

A19

F22
F25

G4

G1
G23
G26

H3

H6
H21
H24

A23

J2

J5
J22
J25

K1

K4
K23
K26

L3

L6

AF2

L21
L24

M2

M5
M22
M25

N1

N4
N23
N26

B6

P3

P6
P21
P24
R2
R5
R22
R25
T1
T4

B8

T23
T26
U3
U6
U21
U24
V2
V5
V22
V25

100

1%
1/16W

PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.

402

MF-LF

R1100

1

2

109

11

16

051-7261

CPU Power & Ground

SYNC_MASTER=T9_NOME

SYNC_DATE=01/25/2007

CPU_VID<2>
CPU_VID<3>

CPU_VID<5>

=PPVCORE_S0_CPU

CPU_VCCSENSE_N

CPU_VCCSENSE_P

CPU_VID<0>
CPU_VID<1>

=PPVCORE_S0_CPU

CPU_VID<6>

CPU_VID<4>

=PP1V5_S0_CPU

=PP1V05_S0_CPU

49

49

13

12

12

12

11

11

12

10

8

8

8

8

Preliminary

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

4x 330uF, 20x 22uF 0805

CPU VCORE VID CONNECTIONS

CPU VCORE HF AND BULK DECOUPLING

1x 470uF, 6x 0.1uF 0402

VCCP (CPU I/O) DECOUPLING

1x 10uF, 1x 0.01uF

VCCA (CPU AVdd) DECOUPLING

WF: Consider sharing bulk cap with NB Vtt?

22UF

20%

6.3V
805

CERM-X5R

C1206

1

2

470UF

20%

D2T

TANT

2.5V

CRITICAL

C1235

1

2 3

22UF

20%

6.3V
805

CERM-X5R

C1204

1

2

22UF

CERM-X5R
805

6.3V

20%

C1216

1

2

22UF

CERM-X5R
805

6.3V

20%

C1214

1

2

22UF

20%

6.3V
805

CERM-X5R

C1208

1

2

22UF

20%

6.3V
805

CERM-X5R

C1203

1

2

22UF

20%

6.3V
805

CERM-X5R

C1207

1

2

6.3V

22UF

20%
805

CERM-X5R

C1202

1

2

22UF

20%

6.3V
805

CERM-X5R

C1201

1

2

22UF

CERM-X5R
805

6.3V

20%

C1213

1

2

22UF

CERM-X5R

20%

805

6.3V

C1212

1

2

22UF

CERM-X5R
805

6.3V

20%

C1211

1

2

22UF

CERM-X5R

20%

6.3V
805

C1219

1

2

20%
805

6.3V

22UF

CERM-X5R

C1200

1

2

22UF

CERM-X5R

20%

6.3V
805

C1210

1

2

10V
402

CERM

20%

0.1UF

C1236

1

2

22UF

20%

6.3V
805

CERM-X5R

C1205

1

2

22UF

20%

6.3V
805

CERM-X5R

C1209

1

2

22UF

CERM-X5R
805

6.3V

20%

C1215

1

2

22UF

CERM-X5R
805

6.3V

20%

C1217

1

2

10V

0.1UF

402

CERM

20%

C1237

1

2

10V

0.1UF

402

CERM

20%

C1238

1

2

10V

0.1UF

402

CERM

20%

C1239

1

2

10V

0.1UF

402

CERM

20%

C1240

1

2

10V

0.1UF

402

CERM

20%

C1241

1

2

22UF

CERM-X5R

20%

805

6.3V

C1218

1

2

0.01UF

10%
16V

402

CERM

PLACEMENT_NOTE=Place near CPU pin B26.

C1281

1

2

603

10uF

20%

6.3V
X5R

C1280

1

2

CRITICAL

PLACEMENT_NOTE=Place in CPU center cavity.

D2T

TANT

330UF

2.0V

10%

C1250

1

2 3

PLACEMENT_NOTE=Place in CPU center cavity.

D2T

TANT

CRITICAL

330UF

2.0V

10%

C1251

1

2 3

PLACEMENT_NOTE=Place in CPU center cavity.

10%

D2T

TANT

CRITICAL

330UF

2.0V

C1252

1

2 3

PLACEMENT_NOTE=Place in CPU center cavity.

CRITICAL

D2T

TANT

10%

330UF

2.0V

C1253

1

2 3

051-7261

SYNC_DATE=12/07/2006

16

12

109

SYNC_MASTER=M75_MLB

CPU Decoupling & VID

=PP1V05_S0_CPU

=PP1V5_S0_CPU

IMVP6_VID<0..6>

CPU_VID<0..6>

MAKE_BASE=TRUE

=PPVCORE_S0_CPU

13 11

83

49

10

11

59

83

11

8

8

7

11

8

Preliminary

IN

BI

BI

OUT

OUT
IN

BI

IN

IN
IN

OUT

IN

OUT
OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

IN

BI

IN

IN
IN

IN

IN

IN
IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

998-1571

OBSDATA_B0

(OBSDATA_A1)

(OBSDATA_A0)

OBSDATA_C1

SB OC[3]#

OBSFN_C0

NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.

Use with 920-0451 adapter board to support CPU, NB & SB debugging.

Mini-XDP Connector

(VCC_OBS_CD)

OBSDATA_D3

SB GPIO[8]

NB CFG[8]

NB CFG[3]

NB CFG[7]

NB CFG[6]

NB CFG[5]

NB CFG[4]

NB CFG[1]

NB CFG[0] NB CFG[2]

SB OC[4]#

(OBSDATA_A2)

TCK0

(OBSDATA_A3)

NC

OBSFN_C1

OBSDATA_C0

OBSDATA_C2

TDO

TDI

ITPCLK#/HOOK5

RESET#/HOOK6
DBR#/HOOK7

SB OC[0]#

OBSDATA_C3

SB OC[1]#

SB OC[2]#

SB OC[5]#

SB OC[7]#

TCK1

SCL

SDA

OBSDATA_B1

OBSDATA_A1

OBSFN_A1

TRSTn

HOOK3

HOOK2

VCC_OBS_AB

HOOK1

TMS

OBSDATA_D1

OBSDATA_D0

OBSDATA_A3

OBSDATA_B3

OBSDATA_B2

OBSFN_A0

OBSDATA_A0

XDP_PRESENT#

OBSDATA_D2

ITPCLK/HOOK4

on even-numbered side of J1300

Please avoid any obstructions

Direction of XDP module

PWRGD/HOOK0

OBSDATA_A2

NOTE: This is not the standard XDP pinout.

SB OC[6]#

83 23 10

7

XDP

1K

5%
1/16W
MF-LF

402

R1399

1 2

15

15

54.9

1%

MF-LF

402

1/16W

XDP

R1315

1

2

XDP

X5R

0.1uF

10%
16V

402

C1300

1

2

402

1/16W

XDP

5%

10K

MF-LF

R1331

1

2

XDP

1/16W

5%

10K

MF-LF

402

R1330

1

2

XDP

X5R

0.1uF

10%
16V

402

C1301

1

2

28 10

83 10

83 10

83 10

83 10

83 10

83 10

83 10

83 14 10

7

83 10

83 10

83 10

83 10

88 83 30

88 83 30

34 24

24

79 24

24

36 24

24

24

43 24

XDP

1K

5%

MF-LF

402

1/16W

R1303

1 2

XDP_CONN

F-ST-SM

CRITICAL

LTH-030-01-G-D-NOPEGS

J1300

1

10

1112
1314
1516
1718
19

2

20

2122
2324
2526
2728
29

3

30

3132
3334
3536
3738
39

4

40

4142
4344
4546
4748
49

5

50

5152
5354
5556
5758
59

6

60

78
9

83 30 16

83 30 16

16

16

16

16

45 25

16

83 30 16

16

051-7261

109

16

13

SYNC_MASTER=T9_NOME

SYNC_DATE=01/22/2007

eXtended Debug Port (XDP)

=PP3V3_S0_XDP

SMC_WAKE_SCI_L

NB_CFG<8>

XDP_TMS

XDP_CPURST_L

PM_LATRIGGER_L

FSB_CPURST_L

XDP_TDO
XDP_TRST_L

XDP_TCK

XDP_BPM_L<3>

TP_XDP_HOOK3

USB_EXTA_OC_L

SB_GPIO30

XDP_CLK_P

USB_EXTB_OC_L

TP_XDP_HOOK2

WOW_EN

XDP_OBS20

XDP_BPM_L<2>

XDP_BPM_L<0>

NB_BSEL<0>
NB_BSEL<1>

NB_CFG<7>

XDP_PWRGDCPU_PWRGD

NB_BSEL<2>
NB_CFG<3>

=PP1V05_S0_CPU

XDP_CLK_N

XDP_TDI

XDP_DBRESET_L

EXTGPU_LVDS_EN

USB_EXTD_OC_L

SB_GPIO40

XDP_BPM_L<5>
XDP_BPM_L<4>

LVDS_CTRL_CLK

XDP_BPM_L<1>

LVDS_CTRL_DATA

NB_CFG<4>
NB_CFG<5>

NB_CFG<6>

12 11 10

8

83

8

Preliminary

BI

BI
BI

OUT

OUT

BI

BI

BI

BI
BI

BI

BI
BI
BI
BI

BI
BI

BI

BI
BI

BI
BI
BI
BI

BI
BI

OUT

BI

OUT

OUT

OUT

BI
BI
BI
BI
BI

BI
BI

H_D0*

H_D3*

H_D2*

H_D33*
H_D34*
H_D35*

H_D1*

H_D4*

H_D10*

H_A4*
H_A5*
H_A6*
H_A7*
H_A8*

H_A9*
H_A10*
H_A11*
H_A12*
H_A13*
H_A14*
H_A15*
H_A16*
H_A17*
H_A18*
H_A19*
H_A20*
H_A21*
H_A22*
H_A23*
H_A24*
H_A25*
H_A26*
H_A27*
H_A28*
H_A29*
H_A30*
H_A31*
H_A32*
H_A33*
H_A34*
H_A35*

H_ADS*

H_ADSTB0*
H_ADSTB1*

H_A3*

H_D7*
H_D8*
H_D9*

H_D11*
H_D12*
H_D13*
H_D14*
H_D15*
H_D16*
H_D17*
H_D18*
H_D19*
H_D20*
H_D21*
H_D22*
H_D23*

H_D25*
H_D26*
H_D27*
H_D28*
H_D29*
H_D30*

H_D32*

H_D36*
H_D37* H_BNR*
H_D38*

H_BPRI*
H_D39*
H_D40*

H_DEFER*

H_D41*

H_DBSY*
H_D42*
H_D43*
H_D44*

H_DPWR*
H_D45*

H_DRDY*
H_D46* H_HIT*
H_D47*

H_HITM*
H_D48*

H_LOCK*

H_TRDY*

H_D51*
H_D52*
H_D53*

H_DINV0*

H_D54*

H_DINV1*

H_D55*

H_DINV2*

H_D56*

H_DINV3*

H_D57*
H_D58*

H_DSTBN0*

H_D59*

H_DSTBN1*

H_D60*

H_DSTBN2*

H_D61*

H_DSTBN3*

H_D62*
H_D63*

H_DSTBP0*
H_DSTBP1*

H_DSTBP2*
H_SWING
H_RCOMP

H_REQ0*
H_SCOMP H_REQ1*
H_SCOMP*

H_REQ2*

H_REQ3*
H_CPURST*

H_REQ4*
H_CPUSLP*

H_RS0*
H_RS1*

H_AVREF

H_RS2*

H_DVREF

H_D5*
H_D6*

H_D31*

H_BREQ*

H_D24*

H_D49*
H_D50*

H_DSTBP3*

HPLL_CLK

HPLL_CLK*

HOST

(1 OF 10)

BI
BI
BI
BI

BI

IN

IN

IN

OUT
OUT

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI

BI

BI

BI

BI
BI
BI
BI
BI

BI

BI
BI

BI

BI

BI
BI

BI
BI

BI

BI

BI

BI

BI
BI

BI
BI

BI

BI

BI

BI

BI

BI
BI

BI
BI

BI

BI

BI

BI

BI

BI

BI

BI
BI

BI

BI

BI

BI

BI
BI

BI

BI

BI

BI

BI

BI

BI

BI
BI

BI
BI

BI

BI

BI

BI

BI

BI
BI

BI
BI

BI

BI

BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

83 10

7

83 10

7

83 10

7

83 10

83 10

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

402

16V

10%

0.1uF

X5R

C1425

1

2

402

1/16W

1%

MF-LF

2.0K

R1426

1

2

402

1/16W

1%

MF-LF

1K

R1425

1

2

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

83 10

7

83 10

83 10

83 10

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

402

1/16W

1%
MF-LF

54.9

R1420

1

2

402

1/16W

1%

MF-LF

24.9

R1415

1

2

402

1/16W

1%

MF-LF

221

R1410

1

2

402

1/16W

1%

MF-LF

100

R1411

1

2

402

16V

10%

0.1uF

X5R

C1410

1

2

83 10

7

FCBGA

CRESTLINE

OMIT

U1400

G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17

J13

B15
E17
C18
A19
B19
N19

B11
C11
M11
C15
F16
L13

G12
H17
G20

B9

C8
E8
F12

B6
E5

E2
G2

M10
N12

N9
H5

P13

K9
M2

W10

Y8
V4

G7

M3
J1
N5
N3
W6
W9
N2
Y7
Y9
P4

M6

W3
N1

AD12

AE3
AD9
AC9

AC7
AC14
AD11
AC11

H7

AB2

AD7

AB1

Y3
AC6
AE2
AC5
AG3
AJ9
AH8

H3

AJ14

AE9

AE11
AH12

AJ5
AH5
AJ6
AE7
AJ7
AJ2

G4

AE5
AJ3
AH2

AH13

F3

N8

H2

C10

D6

K5
L2
AD13
AE13

H8
K7

M7
K3
AD2
AH11

L7
K2
AC2
AJ10

A9

E4
C6
G10

C2

M14
E13
A11
H13
B12

E12
D7
D8

W1

W2

B3

B7

AM5
AM7

83 10

83 10

83 10

83 10

83 10

7

402

1/16W

1%

MF-LF

54.9

R1421

1

2

83 10

7

88 30

7

88 30

7

83 13 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

83 10

7

SYNC_MASTER=T9_NOME

14

109

16

051-7261

NB CPU Interface

SYNC_DATE=01/25/2007

=PP1V25R1V05_S0_FSB_NB

FSB_D_L<47>

FSB_D_L<3>

FSB_D_L<2>

FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>

FSB_D_L<1>

FSB_D_L<10>

FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>

FSB_D_L<11>

FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>
FSB_D_L<16>
FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>

FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>

FSB_D_L<32>

FSB_D_L<36>
FSB_D_L<37>

FSB_D_L<39>
FSB_D_L<40>

FSB_D_L<42>

FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>

FSB_D_L<48>

FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>

FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>

NB_FSB_SCOMP
NB_FSB_SCOMP_L

FSB_CPURST_L
FSB_CPUSLP_L

FSB_D_L<6>

FSB_D_L<31>

FSB_D_L<24>

FSB_D_L<49>
FSB_D_L<50>

FSB_D_L<12>

FSB_D_L<43>

FSB_D_L<5>

FSB_D_L<4>

FSB_D_L<0>

FSB_D_L<38>

FSB_D_L<41>

FSB_D_L<59>

NB_FSB_SWING
NB_FSB_RCOMP

NB_FSB_VREF

FSB_A_L<3>

FSB_A_L<6>

FSB_A_L<4>
FSB_A_L<5>

FSB_A_L<7>
FSB_A_L<8>
FSB_A_L<9>

FSB_A_L<11>

FSB_A_L<10>

FSB_A_L<12>
FSB_A_L<13>
FSB_A_L<14>
FSB_A_L<15>
FSB_A_L<16>
FSB_A_L<17>
FSB_A_L<18>
FSB_A_L<19>
FSB_A_L<20>
FSB_A_L<21>
FSB_A_L<22>
FSB_A_L<23>
FSB_A_L<24>
FSB_A_L<25>
FSB_A_L<26>
FSB_A_L<27>
FSB_A_L<28>
FSB_A_L<29>

FSB_A_L<32>

FSB_A_L<30>
FSB_A_L<31>

FSB_A_L<33>
FSB_A_L<34>
FSB_A_L<35>

FSB_ADS_L
FSB_ADSTB_L<0>
FSB_ADSTB_L<1>

FSB_BPRI_L

FSB_BNR_L

FSB_BREQ0_L
FSB_DEFER_L
FSB_DBSY_L

FSB_DPWR_L

FSB_CLK_NB_P
FSB_CLK_NB_N

FSB_DRDY_L
FSB_HIT_L
FSB_HITM_L

FSB_TRDY_L

FSB_LOCK_L

FSB_DINV_L<0>
FSB_DINV_L<1>
FSB_DINV_L<2>
FSB_DINV_L<3>

FSB_DSTB_L_N<0>
FSB_DSTB_L_N<1>
FSB_DSTB_L_N<2>
FSB_DSTB_L_N<3>

FSB_DSTB_L_P<0>
FSB_DSTB_L_P<1>
FSB_DSTB_L_P<2>
FSB_DSTB_L_P<3>

FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>
FSB_REQ_L<4>

FSB_RS_L<1>

FSB_RS_L<0>

FSB_RS_L<2>

30

8

Preliminary

IN

IN

OUT

IN

OUT
OUT
OUT

OUT
OUT
OUT

OUT

IN

OUT

OUT

BI

L_BKLT_CTRL

L_VDD_EN

PEG_TX15*

PEG_TX14*

PEG_TX13*

PEG_TX12*

PEG_TX11*

PEG_TX10*

PEG_TX9*

PEG_TX8*

PEG_TX7*

PEG_TX6*

PEG_TX5*

PEG_TX4*

PEG_TX3*

PEG_TX2*

PEG_TX1*

PEG_TX0*

PEG_TX15

PEG_TX14

PEG_TX13

PEG_TX12

PEG_TX11

PEG_TX10

PEG_TX9

PEG_TX8

PEG_TX7

PEG_TX6

PEG_TX5

PEG_TX4

PEG_TX3

PEG_TX2

PEG_TX1

PEG_TX0

PEG_RX14

PEG_RX15*

PEG_RX14*

PEG_RX13*

PEG_RX12*

PEG_RX11*

PEG_RX15

PEG_RX13

PEG_RX12

PEG_RX11

PEG_RX10

PEG_RX9

PEG_RX8

PEG_RX7

PEG_RX6

PEG_RX5

PEG_RX4

PEG_RX3

PEG_RX2

PEG_RX1

PEG_RX0

PEG_RX10*

PEG_RX9*

PEG_RX8*

PEG_RX7*

PEG_RX6*

PEG_RX5*

PEG_RX4*

PEG_RX3*

PEG_RX2*

PEG_RX1*

PEG_RX0*

PEG_COMPI
PEG_COMPO

CRT_DDC_DATA

L_CTRL_DATA

LVDSB_DATA1
LVDSB_DATA2

LVDSB_DATA0

LVDSB_DATA2*

LVDSB_DATA1*

LVDSB_DATA0*

LVDSA_DATA2

LVDSA_DATA0
LVDSA_DATA1

LVDSB_CLK*

LVDS_VREFL

LVDS_IBG

TVC_RTN

TVA_RTN
TVB_RTN

TVC_DAC

TVB_DAC

TVA_DAC

CRT_RED*

CRT_RED

CRT_GREEN*

CRT_GREEN

CRT_BLUE*

CRT_BLUE

CRT_VSYNC

CRT_TVO_IREF

CRT_HSYNC

CRT_DDC_CLK

L_BKLT_EN

L_DDC_CLK

TV_DCONSEL0
TV_DCONSEL1

LVDSA_DATA2*

L_DDC_DATA

LVDSA_DATA1*

LVDSA_DATA0*

LVDSB_CLK

LVDSA_CLK

LVDSA_CLK*

LVDS_VREFH

L_CTRL_CLK

LVDS_VBG

VGA

TV

LVDS

(3 OF 10)

PCI-EXPRESS GRAPHICS

BI

BI

OUT

OUT

IN

IN
IN

IN

IN

IN

IN

IN

IN
IN
IN
IN
IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT
OUT

IN

BI
BI

OUT
OUT
OUT
OUT

OUT
OUT

IN

OUT

OUT

OUT
OUT

OUT

OUT
OUT

OUT

OUT
OUT

IN

OUT
OUT
OUT

OUT

OUT

OUT

BI
BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

recommendation is to float both signals, see Radar #5067636.

a glitch during wake-up on LVDS DATA/CLK pairs. New

Note: SR DG says to tie LVDS_VREFH/L to GND. This causes

If SDVO is used, VCCD_LVDS must remain powered with proper

should connect to GND through 75-ohm resistors.

omit filtering components. Unused DAC outputs

Unused DAC outputs must remain powered, but can

Can leave all signals NC if LVDS is not implemented.

decoupling. Otherwise, tie VCCD_LVDS to GND also.

Tie VCC_TX_LVDS and VCCA_LVDS to GND.

SDVO_FLDSTALL#

SDVO Alternate Function

SDVO_TVCLKIN#
SDVO_INT#

SDVO_TVCLKIN
SDVO_INT
SDVO_FLDSTALL

SDVOB_GREEN

SDVOB_RED

SDVOC_CLKN

SDVOC_BLUE#

SDVOC_GREEN#

SDVOC_RED#

SDVOB_CLKN

SDVOB_BLUE#

SDVOB_GREEN#

SDVOB_RED#

SDVOB_CLKP

SDVOB_BLUE

SDVOC_CLKP

SDVOC_BLUE

SDVOC_GREEN

SDVOC_RED

LVDS Disable

TVDAC rails. VCCA_TVx_DAC and VCCA_DAC_BG can

Component: DACA, DACB & DACC

Composite: DACA only

TV-Out Signal Usage:

Can tie the following rails to GND:

VSYNC and CRT_TVO_IREF to GND.

CRT Disable / TV-Out Enable

TV-Out Disable / CRT Enable
Tie TVx_DAC and TVx_RTN to GND. Must power all

Leave GFX_VID<3..0> and GFX_VR_EN as NC.

Tie VCC_AXG and VCC_AXG_NCTF to GND.

Tie VCCA_DPLLA and VCCA_DPLLB to VCC (VCore).

Tie DPLL_REF_CLK and DPLL_REF_SSCLK to GND.

Can also tie CRT_DDC_*, L_CTRL_*, L_DDC_*, SDVO_CTRL_* and
TV_DCONSELx to GND.

Follow instructions for LVDS and CRT & TV-Out Disable above.

Internal Graphics Disable

and filtered at all times!

NOTE: Must keep VDDC_TVDAC powered

VCCD_CRT, VCCD_QDAC and VCC_SYNC.

VCCA_CRT_DAC, VCCA_DAC_BG, VCCA_TVx_DAC,

All CRT/TVDAC rails must be powered. All

CRT & TV-Out Disable
Tie TVx_DAC, TVx_RTN, R/R#/G/G#/B/B#, HSYNC,

Tie R/R#/G/G#/B/B#, HSYNC and VSYNC to GND.

share filtering with VCCA_CRT_DAC.

S-Video: DACB & DACC only

Tie DPLL_REF_CLK* and DPLL_REF_SSCLK* to VCC (VCore).

rails must be filtered except for VCCA_CRT.

84 68

84 68

24.9

1%
1/16W
MF-LF
402

R1510

1

2

79

84 68

22

22

22

22

22

22

22

84 68

22

22

84 22

FCBGA

CRESTLINE

OMIT

U1400

H32
G32

K33
G35

K29
J29

F33

F29
E29

C32
E33

J40
H39
E39
E40
C37
D35
K40

L41
L43
N41
N40

C45

D46

G50

G51

E50

E51

F48

F49

E42

D44

E44

G44

A47

B47

A45

B45

N43
M43

J50

J51

L50

L51

AC45

AD44

AC41

AD40

AH47

AG46

AG49

AH49

AH45

AG45

AG42

AG41

M47

N47

U44

T45

T49

T50

T41

U40

W45

Y44

W41

Y40

AB50

AB51

Y48

W49

M45

N45

T38

U39

AD47

AC46

AC50

AC49

AD43

AC42

AG39

AH39

AE50

AE49

AH43

AH44

T46

U47

N50

N51

R51

R50

U43

T42

W42

Y43

Y47

W46

Y39

W38

AC38

AD39

M35
P33

E27

F27

G27

J27

K27

L27

13

13

22

22

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

84 68

79

79

84 68

79

79

84 79

84 79

84 79

84 79

84 79

84 79

84 68

84 79

84 79

84 79

84 79

84 79

84 79

84 79

84 79

84 79

84 79

84 68

22

22

22

22

22

22

22

22

SYNC_MASTER=T9_NOME

NB PEG / Video Interfaces

051-7261

16

109

15

SYNC_DATE=03/19/2007

=TV_B_RTN

=TV_B_DAC

LVDS_B_DATA_N<2>

LVDS_B_DATA_N<1>

LVDS_CTRL_DATA

LVDS_CTRL_CLK

TP_LVDS_VBG

PEG_D2R_P<9>

PEG_D2R_P<11>

PEG_D2R_P<10>

PP1V05_S0_NB_VCCPEG

PEG_D2R_N<1>

PEG_D2R_N<6>

TP_LVDS_VREFH

LVDS_A_CLK_N
LVDS_A_CLK_P

LVDS_B_CLK_P

LVDS_A_DATA_N<0>
LVDS_A_DATA_N<1>

LVDS_DDC_DATA

LVDS_A_DATA_N<2>

TV_DCONSEL<1>

TV_DCONSEL<0>

LVDS_DDC_CLK

LVDS_BKLT_EN

CRT_DDC_CLK

=CRT_HSYNC_R
=CRT_TVO_IREF
=CRT_VSYNC_R

=CRT_BLUE
=CRT_BLUE_L
=CRT_GREEN
=CRT_GREEN_L
=CRT_RED
=CRT_RED_L

=TV_A_DAC

=TV_C_DAC

=TV_A_RTN

=TV_C_RTN

LVDS_IBG

TP_LVDS_VREFL

LVDS_B_CLK_N

LVDS_A_DATA_P<1>

LVDS_A_DATA_P<0>

LVDS_A_DATA_P<2>

LVDS_B_DATA_N<0>

LVDS_B_DATA_P<0>

LVDS_B_DATA_P<2>

LVDS_B_DATA_P<1>

CRT_DDC_DATA

PEG_COMP

PEG_D2R_N<0>

PEG_D2R_N<2>
PEG_D2R_N<3>
PEG_D2R_N<4>
PEG_D2R_N<5>

PEG_D2R_N<7>
PEG_D2R_N<8>
PEG_D2R_N<9>
PEG_D2R_N<10>

PEG_D2R_P<0>
PEG_D2R_P<1>
PEG_D2R_P<2>
PEG_D2R_P<3>
PEG_D2R_P<4>
PEG_D2R_P<5>
PEG_D2R_P<6>
PEG_D2R_P<7>
PEG_D2R_P<8>

PEG_D2R_P<12>
PEG_D2R_P<13>

PEG_D2R_P<15>

PEG_D2R_N<11>
PEG_D2R_N<12>
PEG_D2R_N<13>
PEG_D2R_N<14>
PEG_D2R_N<15>

PEG_D2R_P<14>

PEG_R2D_C_P<0>
PEG_R2D_C_P<1>
PEG_R2D_C_P<2>
PEG_R2D_C_P<3>
PEG_R2D_C_P<4>
PEG_R2D_C_P<5>
PEG_R2D_C_P<6>
PEG_R2D_C_P<7>
PEG_R2D_C_P<8>
PEG_R2D_C_P<9>
PEG_R2D_C_P<10>
PEG_R2D_C_P<11>
PEG_R2D_C_P<12>
PEG_R2D_C_P<13>
PEG_R2D_C_P<14>
PEG_R2D_C_P<15>

PEG_R2D_C_N<0>
PEG_R2D_C_N<1>
PEG_R2D_C_N<2>
PEG_R2D_C_N<3>
PEG_R2D_C_N<4>
PEG_R2D_C_N<5>
PEG_R2D_C_N<6>
PEG_R2D_C_N<7>
PEG_R2D_C_N<8>
PEG_R2D_C_N<9>
PEG_R2D_C_N<10>
PEG_R2D_C_N<11>
PEG_R2D_C_N<12>
PEG_R2D_C_N<13>
PEG_R2D_C_N<14>
PEG_R2D_C_N<15>

LVDS_VDD_EN

LVDS_BKLT_CTL

21 19

22

22

Preliminary

IN

IN

CLKREQ*

NC1

NC8

CL_CLK

CL_PWROK

CL_RST*

RSVD6

THERMTRIP*

PM_BM_BUSY*

RSVD4

RSVD3

RSVD7

SM_CKE1

SM_CK0*

SM_CKE0

SM_ODT0

SM_ODT2

SM_RCOMP

SM_RCOMP*

SM_VREF0
SM_VREF1

SM_RCOMP_VOL

SM_CS1*

SM_CS0*

RSVD14

RSVD11

RSVD10

RSVD9

RSVD5

RSVD8

RSVD2

DPLL_REF_CLK*

DPLL_REF_SSCLK

PEG_CLK

DMI_RXN1

DMI_RXN0

DMI_RXN3

DMI_RXN2

DMI_RXP0
DMI_RXP1
DMI_RXP2

DMI_TXN0

DMI_RXP3

DMI_TXN2

DMI_TXN1

DMI_TXP0

DMI_TXN3

DMI_TXP1
DMI_TXP2
DMI_TXP3

PEG_CLK*

RSVD12

CL_DATA

CL_VREF

SDVO_CTRL_CLK

SDVO_CTRL_DATA

ICH_SYNC*

TEST1
TEST2

GFX_VID0
GFX_VID1
GFX_VID2

GFX_VR_EN

GFX_VID3

RSVD20
RSVD21

RSVD24
RSVD25

RSVD27

RSVD34
RSVD35
RSVD36
RSVD37
RSVD38
RSVD39

RSVD41
RSVD42

RSVD40

RSVD43
RSVD44
RSVD45

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13

CFG16

CFG15

CFG14

CFG17
CFG18
CFG19
CFG20

PM_DPRSTP*
PM_EXT_TS0*

PWROK

PM_EXT_TS1*

RSTIN*

DPRSLPVR

NC2

NC4

NC3

NC5

NC7

NC6

NC10

NC9

NC12

NC11

NC13
NC14
NC15
NC16

DPLL_REF_CLK

SM_RCOMP_VOH

SM_ODT3

SM_ODT1

RSVD13

SM_CS2*
SM_CS3*

SM_CK3
SM_CK4

SM_CK4*

SM_CKE3

RSVD1

SM_CKE4

DPLL_REF_SSCLK*

SM_CK3*

SM_CK1*

SM_CK1

SM_CK0

SA_MA14

RSVD22
RSVD23

RSVD26

SB_MA14

SM_CK2
SM_CK2*
SM_CK5
SM_CK5*

(2 OF 10)

RSVD

DDR MUXING

CLK

CFG

DMI

PM

GRAPHICS VID

ME

MISC

NC

OUT
OUT
OUT
OUT
OUT

BI
BI

IN

OUT

BI

BI
OUT
OUT

IN

IN

OUT

OUT
OUT

IN
IN
IN

OUT

OUT
OUT
OUT

BI

OUT

BI

OUT

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT
OUT
OUT

OUT

OUT

OUT
OUT
OUT

OUT
OUT
OUT
OUT

IN

IN
IN

IN

IN

IN

IN

IN
IN
IN
IN

IN
IN

IN

IN

OUT

OUT

OUT

OUT

OUT
OUT

OUT

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NB CFG<8:0> used for debug access

IPU
IPU

NB_CFG<4>
NB_CFG<5>

DMI x2 Select

NOTE: GMCH CL_PWROK input must be PWRGD signal for
PP3V3_S0M, PP3V3_S0MWOL, PP1V8_S3M, PP1V25_S0M,

If ME/AMT is not used, short CL_PWROK to PWROK.

PP1V05_S0M, PP0V9_S3M and PP0V9_S0M.

NB_CFG<18>

NB_CFG<15>

FSB Dynamic
ODT

NB_CFG<17>

NB_CFG<14>

NB_CFG<16>

NB_CFG<11>
NB_CFG<12>
NB_CFG<13>

DMI Lane
Reversal

SDVO/PCIe x1

Concurrent

NB_CFG<20>

NB_CFG<19>

00 = RESERVED

or PCIe x16

11 = Normal Operation

High = Reversed

Low = Only SDVO

NB_CFG<13:12>

High = Both active

Low = Normal

01 = XOR Mode Enabled
10 = All-Z Mode Enabled

High = Enabled
Low = Disabled

See Below
See Below

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

Lane Reversal

PCIe Graphics

NB_CFG<9>

NB_CFG<10>

Low = Reversed

High = Normal

RESERVED

RESERVED

RESERVED

NB_CFG<7>

High = DMIx4

NB_CFG<6>

RESERVED

IPU

Clk used for PEG and DMI

IPD
IPD

IPD

IPU

IPU

IPU

IPU

IPU

IPU

IPU

IPU

IPU

IPU

NB_CFG<8>

NB_CFG<3>

Low = DMIx2

RESERVED

RESERVED

IPU

IPU

NB CFG<13:12> require ICT access

28

7

8

10V

0.1uF

20%
CERM

402

C1616

1

2

10V

0.1uF

20%

CERM

402

C1615

1

2

OMIT

FCBGA

CRESTLINE

U1400

P27
N27

R24
L23
J23
E23
E20
K23
M20
M24
L32
N33

N24

L35

C21
C23
F23
N23
G23
J20
C20

AM49
AK50
AT43
AN49
AM50

G39

AN47
AJ38
AN42
AN46

AM47
AJ39
AN41
AN45

AJ46
AJ41
AM40
AM44

AJ47
AJ42
AM39
AM43

B42
C42
H48
H47

G36

E35
A39
C38
B39
E36

G40

BJ51

E1

A5
C51
B50
A50
A49
BK2

BK51
BK50
BL50
BL49

BL3
BL2
BK1
BJ1

K44
K45

G41
L39
L36
J36

AW49
AV20

P36

AR37
AM36
AL36
AM37

D20

P37

H10
B51

BJ20
BK22
BF19
BH20
BK18
BJ18

R35

BH39
AW20
BK20

C48
D47
B44

N35

C44
A35
B37
B36
B34
C34

AR12
AR13
AM12
AN13

J12

BJ29
BE24

H35
K36

AV29

AW30

BB23

BA23

BF23
BG23

BA25

AW25

AV23

AW23

BC23
BD24

BE29
AY32
BD39
BG37

BG20
BK16
BG16
BE13

BH18
BJ15
BJ14
BE16

BL15
BK14

BK31
BL31

AR49
AW4

A37
R32

N20

9

9

9

9

9

87 25

87 25

9

87 25

22

22

29

7

25

7

5%
1/16W
MF-LF

20K

402

R1691

1

2

5%
1/16W
MF-LF

0

402

R1690

1

2

83 59 25

7

45 32

1/16W

5%
MF-LF

10K

402

R1631

1

2

402

CERM

16V

10%

0.01UF

C1625

1

2

20%
CERM1

6.3V

2.2UF

603

C1624

1

2

402

1/16W

1%
MF-LF

1K

R1624

1

2

3.01K

MF-LF

1/16W

1%

402

R1622

1

2

20%

2.2UF

CERM1

6.3V
603

C1622

1

2

402

CERM

16V

10%

0.01UF

C1623

1

2

MF-LF

1%
1/16W

402

1K

R1620

1

2

1%
1/16W
MF-LF

392

402

R1641

1

2

1%

1K

1/16W
MF-LF
402

R1640

1

2

0.1uF

CERM

10V

20%

402

C1640

1

2

NBCFG_DMI_X2

1/16W
MF-LF

3.9K

5%

402

R1655

1

2

NBCFG_PEG_REVERSE

3.9K

MF-LF

1/16W

5%

402

R1659

1

2

MF-LF

5%
1/16W

3.9K

NBCFG_DYN_ODT_DISABLE

402

R1666

1

2

NBCFG_DMI_REVERSE

5%
1/16W
MF-LF

3.9K

402

R1669

1

2

NBCFG_SDVO_AND_PCIE

3.9K

MF-LF

1/16W

5%

402

R1670

1

2

9

85 33 31

85 33 32

83 30 13

83 30 13

83 30 13

13

13

13

13

16 13

25

7

13

83 46 23 10

45 31

83 59 23 10

7

59 28

9 7

85 31

85 32

85 32

85 31

85 31

85 32

85 32

85 31

85 33 31

85 33 31

85 33 32

85 33 31

85 33 32

85 33 31

85 33 32

85 33 32

85 33 31

85 33 31

85 33 32

85 33 32

402

20

1%
1/16W
MF-LF

R1610

1

2

402

20

MF-LF

1%
1/16W

R1611

1

2

8

88 30

7

88 30

7

22

22

22

22

84 24

84 24

84 24

84 24

84 24

84 24

84 24

84 24

84 24

84 24

84 24

84 24

84 24

84 24

84 24

84 24

10K

5%
1/16W
MF-LF

402

R1630

1

2

NB Misc Interfaces

SYNC_DATE=01/25/2007

SYNC_MASTER=T9_NOME

16

109

16

051-7261

TP_LVDS_A_DATAP3

TP_NB_RSVD<34>

MEM_B_A<14>

TP_NB_RSVD<27>

TP_NB_RSVD<26>

TP_NB_RSVD<25>

=NB_CLK100M_DPLLSS_P
=NB_CLK100M_DPLLSS_N

NB_BSEL<0>

NB_CFG<5>

MEM_CKE<4>

TP_NB_RSVD<1>

MEM_CLK_P<0>

MEM_CLK_N<4>

MEM_CLK_N<3>

MEM_CLK_P<4>

MEM_CLK_P<3>

TP_NB_RSVD<13>

TP_NB_NC<16>

TP_NB_NC<15>

TP_NB_NC<14>

TP_NB_NC<13>

TP_NB_NC<11>
TP_NB_NC<12>

TP_NB_NC<9>
TP_NB_NC<10>

TP_NB_NC<6>
TP_NB_NC<7>

TP_NB_NC<5>

TP_NB_NC<3>

TP_NB_NC<2>

PM_EXTTS_L<0>

NB_CFG<20>

NB_CFG<19>

TP_NB_CFG<18>

TP_NB_CFG<14>
TP_NB_CFG<15>
NB_CFG<16>

TP_NB_CFG<12>

TP_NB_CFG<10>

TP_NB_RSVD<41>

TP_NB_RSVD<23>

TP_NB_RSVD<22>

TP_NB_RSVD<21>

TP_NB_RSVD<20>

NB_TEST2

NB_TEST1

TP_NB_RSVD<2>

TP_NB_RSVD<8>
TP_NB_RSVD<9>
TP_NB_RSVD<10>
TP_NB_RSVD<11>

MEM_CS_L<0>
MEM_CS_L<1>

MEM_CKE<0>

MEM_CLK_N<1>

MEM_CLK_P<1>

MEM_CLK_N<0>

TP_NB_RSVD<7>

TP_NB_RSVD<3>
TP_NB_RSVD<4>

TP_NB_NC<8>

TP_NB_NC<1>

=NB_CLK96M_DOT_P

NB_CLK100M_PCIE_P
NB_CLK100M_PCIE_N

DMI_S2N_P<0>
DMI_S2N_P<1>
DMI_S2N_P<2>

DMI_N2S_N<0>
DMI_N2S_N<1>

DMI_N2S_N<3>

DMI_N2S_N<2>

DMI_N2S_P<0>
DMI_N2S_P<1>
DMI_N2S_P<2>
DMI_N2S_P<3>

GFX_VID<2>

CLINK_NB_DATA
=NB_CLINK_MPWROK
CLINK_NB_RESET_L

SDVO_CTRLCLK
SDVO_CTRLDATA
NB_CLKREQ_L
NB_SB_SYNC_L

TP_MEM_CLKN2
TP_MEM_CLKP5
TP_MEM_CLKN5

PM_BMBUSY_L
CPU_DPRSTP_L

VR_PWRGOOD_DELAY

PM_THRMTRIP_L

MEM_CS_L<2>

MEM_ODT<2>
MEM_ODT<3>

=NB_CLK96M_DOT_N

MEM_CS_L<3>
MEM_ODT<0>

MEM_ODT<1>

TP_NB_RSVD<6>

TP_NB_RSVD<12>

TP_NB_NC<4>

GFX_VID<4>

DMI_S2N_P<3>

DMI_S2N_N<2>

=PP0V9_S3M_MEM_NBVREFB

TP_NB_RSVD<5>

TP_NB_RSVD<24>

TP_MEM_CLKP2

TP_LVDS_A_DATAN3

TP_LVDS_B_DATAP3

MEM_A_A<14>

DMI_S2N_N<0>

TP_NB_RSVD<35>
TP_NB_RSVD<36>

TP_LVDS_B_DATAN3

TP_NB_RSVD<45>

TP_NB_RSVD<42>

DMI_S2N_N<3>

DMI_S2N_N<1>

TP_NB_RSVD<14>

PM_DPRSLPVR

NB_RESET_L

PM_EXTTS_L<1>

NB_CFG<9>

NB_CFG<16>

=PP3V3_S0_NB_VCCHV

NB_CFG<19>

NB_CFG<20>

=PP3V3_S0_NB_VCCHV

TP_NB_CFG<11>

TP_NB_CFG<13>

GFX_VID<3>

=GFX_VR_EN

=PP3V3_S0_NB_VCCHV

TP_NB_CFG<17>

GFX_VID<1>

CLINK_NB_CLK

PP1V25_S0M_NB_VCCAXD

NB_CLINK_VREF

NB_BSEL<2>

NB_BSEL<1>

NB_CFG<3>

NB_CFG<6>
NB_CFG<7>
NB_CFG<8>
NB_CFG<9>

NB_CFG<5>

MEM_RCOMP_L

TP_NB_RSVD<43>
TP_NB_RSVD<44>

NB_CFG<4>

MEM_CKE<1>
MEM_CKE<3>

=PP0V9_S3M_MEM_NBVREFA

MEM_RCOMP_VOL

MEM_RCOMP

=PP1V8_S3M_MEM_NB

MEM_RCOMP_VOH

GFX_VID<0>

21

21

21

19

19

19

21

16

16

16

16

21

18

13

7

7

7

7

7

7

7

7

7

7

7

7

7

16

16

16

7

7

7

16

16

8

16

16

8

8

19

87

16

8

Preliminary

BI

BI
BI
BI
BI
BI

OUT

OUT

OUT

OUT

OUT

BI

OUT

OUT

BI
BI
BI

BI

BI
BI
BI
BI

BI BI

BI
BI
BI
BI
BI

BI
BI
BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI
BI
BI

BI

BI

BI
BI
BI
BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI
BI
BI
BI
BI

BI
BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

BI

OUT

OUT
OUT

OUT

OUT

OUT

OUT
OUT

OUT

OUT

BI

OUT

OUT

OUT

BI

BI

BI
BI
BI

BI

BI

BI

BI
BI
BI

BI
BI

BI

BI
BI

OUT

BI

BI

OUT
OUT

OUT
OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

OUT

SA_DQ0
SA_DQ1
SA_DQ2

SA_DQ4

SA_DQ6

SA_DQ14

SA_CAS*

SA_BS2

SA_DQ63

SA_DQ62

SA_DQ61

SA_DQ60

SA_DQ59

SA_DQ58

SA_DQ57

SA_DQ56

SA_DQ55

SA_DQ54

SA_DQ53

SA_DQ52

SA_DQ51

SA_DQ50

SA_DQ49

SA_DQ48

SA_DQ47

SA_DQ46

SA_DQ44

SA_DQ43

SA_DQ42

SA_DQ41

SA_DQ40

SA_DQ39

SA_DQ38

SA_DQ37

SA_DQ36

SA_DQ34
SA_DQ35

SA_DQ33

SA_DQ32

SA_DQ31

SA_DQ30

SA_DQ28
SA_DQ29

SA_DQ27

SA_DQ26

SA_DQ25

SA_DQ24

SA_DQ23

SA_DQ22

SA_DQ21

SA_DQ20

SA_DQ19

SA_DQ18

SA_DQ17

SA_DQ16

SA_DQ15

SA_DQ13

SA_DQ11
SA_DQ12

SA_DQ10

SA_DQ9

SA_DQ8

SA_DQ7

SA_DQ5

SA_DQ3

SA_BS1

SA_BS0

SA_DQ45

SA_DM0
SA_DM1

SA_DM3

SA_DM2

SA_DM5

SA_DM4

SA_DM7

SA_DM6

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7

SA_DQS1*

SA_DQS0*

SA_DQS2*

SA_DQS4*

SA_DQS3*

SA_DQS5*
SA_DQS6*
SA_DQS7*

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7

SA_MA9

SA_MA8

SA_MA10
SA_MA11
SA_MA12
SA_MA13

SA_RAS*

SA_RCVEN*

SA_WE*

DDR SYSTEM MEMORY A

(4 OF 10)

SB_DQ2

SB_DQ1

SB_DQ5

SB_DM0

SB_DQ0

SB_DQ4

SB_DQ6
SB_DQ7

SB_CAS*

SB_BS2

SB_BS0
SB_BS1

SB_DQ63

SB_DQ62

SB_DQ59

SB_DQ58

SB_DQ56

SB_DQ55

SB_DQ54

SB_DQ53

SB_DQ52

SB_DQ51

SB_DQ50

SB_DQ49

SB_DQ48

SB_DQ47

SB_DQ45
SB_DQ46

SB_DQ44

SB_DQ43

SB_DQ42

SB_DQ41

SB_DQ40

SB_DQ39

SB_DQ38

SB_DQ37

SB_DQ36

SB_DQ34
SB_DQ35

SB_DQ33

SB_DQ32

SB_DQ31

SB_DQ30

SB_DQ28
SB_DQ29

SB_DQ27

SB_DQ26

SB_DQ25

SB_DQ24

SB_DQ23

SB_DQ22

SB_DQ21

SB_DQ20

SB_DQ19

SB_DQ18

SB_DQ17

SB_DQ16

SB_DQ15

SB_DQ14

SB_DQ13

SB_DQ11
SB_DQ12

SB_DQ10

SB_DQ9

SB_DQ8

SB_DQ3

SB_DQ57

SB_DQ61

SB_DQ60

SB_WE*

SB_RCVEN*

SB_RAS*

SB_MA13

SB_MA12

SB_MA11

SB_MA10

SB_MA8
SB_MA9

SB_MA7

SB_MA6

SB_MA5

SB_MA4

SB_MA3

SB_MA2

SB_MA1

SB_MA0

SB_DQS7*

SB_DQS6*

SB_DQS5*

SB_DQS3*
SB_DQS4*

SB_DQS2*

SB_DQS0*
SB_DQS1*

SB_DQS7

SB_DQS6

SB_DQS5

SB_DQS4

SB_DQS3

SB_DQS2

SB_DQS1

SB_DQS0

SB_DM6
SB_DM7

SB_DM4
SB_DM5

SB_DM2
SB_DM3

SB_DM1

(5 OF 10)

DDR SYSTEM MEMORY B

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT
OUT
OUT

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 32

85 32

85 32

85 32

85 32

85 32

85 32

85 32

85 31 85 32

85 32

85 32

85 32

85 32

85 32

85 32

85 32

85 32

85 32

85 31

85 32

85 32

85 32

85 32

85 32

85 32

85 32

85 32

85 32

85 32

85 31

85 32

85 32

85 32

85 32

85 32

85 32

85 32

85 32

85 32

85 32

85 31

85 32

85 32

85 32

85 32

85 32

85 32

85 32

85 32

85 32

85 32

85 31

85 32

85 32

85 32

85 32

85 32

85 32

85 32

85 32

85 32

85 31

85 32

85 32

85 32

85 32

85 32

85 32

85 32

85 33 32

85 33 32

85 33 32

85 31

85 33 32

85 33 32

85 33 32

85 33 32

85 33 32

85 33 32

85 33 32

85 33 32

85 33 32

85 33 32

85 31

85 33 32

85 33 32

85 33 32

85 32

85 32

85 32

85 32

85 32

85 32

85 32

85 31

85 32

85 32

85 32

85 32

85 32

85 32

85 32

85 32

85 32

85 32

85 31

85 32

85 32

85 32

85 32

85 32

85 32

85 32

85 33 32

85 33 32

85 33 32

85 31

85 33 32

OMIT

CRESTLINE

FCBGA

U1400

BB19
BK19
BF29

BL17

AT45
BD44
BD42
AW38
AW13
BG8
AY5
AN6

AR43
AW44

BG47
BJ45
BB47
BG50
BH49
BE45
AW43
BE44
BG42
BE40

BA45

BF44
BH45
BG40
BF40
AR40
AW40
AT39
AW36
AW41
AY41

AY46

AV38
AT38
AV13
AT13
AW11
AV11
AU15
AT11
BA13
BA11

AR41

BE10
BD10

BD8
AY9

BG10

AW9
BD7
BB9
BB5
AY7

AR45

AT5
AT7
AY6
BB7
AR5
AR8
AR9
AN3
AM8

AN10

AT42

AT9
AN9
AM9

AN11

AW47
BB45
BF48

AT46

AT47

BE48

BD47

BB43

BC41

BC37

BA37

BB16

BA16

BH6

BH7

BB2

BC1

AP3

AP2

BJ19
BD20

BC19
BE28
BG30
BJ16

BK27
BH28
BL24
BK28
BJ27
BJ25
BL28
BA28

BE18
AY20

BA19

OMIT

CRESTLINE

FCBGA

U1400

AY17
BG18
BG36

BE17

AR50
BD49
BK45
BL39
BH12
BJ7
BF3
AW2

AP49
AR51

BA49
BE50
BA51
AY49
BF50
BF49
BJ50
BJ44
BJ43
BL43

AW50

BK47
BK49
BK43
BK42
BJ41
BL41
BJ37
BJ36
BK41
BJ40

AW51

BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12
BG12

AN51

BJ10

BL9
BK5
BL5
BK9

BK10

BJ8
BJ6
BF4
BH5

AN50

BG1
BC2
BK3
BE4
BD3
BJ2
BA3
BB3
AR1
AT3

AV50

AY2
AY3
AU2
AT2

AV49
BA50
BB50

AT50

AU50

BD50

BC50

BK46

BL45

BK39

BK38

BJ12

BK12

BL7

BK7

BE2

BF2

AV2

AV3

BC18
BG28

BG17
BE37
BA39
BG13

BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37

AV16
AY18

BC17

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 33 31

85 33 31

85 33 31

85 31

85 33 31

85 31

85 33 31

85 33 31

85 33 31

85 33 31

85 33 31

85 33 31

85 33 31

85 31

85 33 31

85 33 31

85 33 31

85 33 31

85 33 31

85 33 31

85 33 31

85 33 31

85 33 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

85 31

17

109

16

051-7261

NB DDR2 Interfaces

SYNC_MASTER=T9_NOME

SYNC_DATE=01/25/2007

MEM_A_DQ<35>

TP_MEM_A_RCVEN_L TP_MEM_B_RCVEN_L

MEM_B_DQ<39>

MEM_B_BS<0>
MEM_B_BS<1>
MEM_B_BS<2>

MEM_B_DM<0>

MEM_B_CAS_L

MEM_B_DM<1>
MEM_B_DM<2>

MEM_B_DQ<0>
MEM_B_DQ<1>
MEM_B_DQ<2>
MEM_B_DQ<3>
MEM_B_DQ<4>
MEM_B_DQ<5>
MEM_B_DQ<6>
MEM_B_DQ<7>
MEM_B_DQ<8>

MEM_B_DM<3>
MEM_B_DM<4>
MEM_B_DM<5>
MEM_B_DM<6>
MEM_B_DM<7>

MEM_B_DQS_P<1>

MEM_B_DQS_P<0>

MEM_B_DQS_P<4>

MEM_B_DQS_P<3>

MEM_B_DQS_P<2>

MEM_B_DQS_P<6>

MEM_B_DQS_P<5>

MEM_B_DQS_N<1>

MEM_B_DQS_P<7>
MEM_B_DQS_N<0>

MEM_B_DQS_N<3>

MEM_B_DQS_N<2>

MEM_B_DQS_N<4>

MEM_B_DQS_N<6>

MEM_B_DQS_N<5>

MEM_B_DQS_N<7>

MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>

MEM_B_RAS_L

MEM_B_A<13>

MEM_B_WE_L

MEM_B_DQ<9>
MEM_B_DQ<10>
MEM_B_DQ<11>
MEM_B_DQ<12>
MEM_B_DQ<13>
MEM_B_DQ<14>
MEM_B_DQ<15>
MEM_B_DQ<16>
MEM_B_DQ<17>
MEM_B_DQ<18>
MEM_B_DQ<19>
MEM_B_DQ<20>
MEM_B_DQ<21>
MEM_B_DQ<22>
MEM_B_DQ<23>
MEM_B_DQ<24>
MEM_B_DQ<25>
MEM_B_DQ<26>
MEM_B_DQ<27>
MEM_B_DQ<28>
MEM_B_DQ<29>
MEM_B_DQ<30>
MEM_B_DQ<31>
MEM_B_DQ<32>
MEM_B_DQ<33>
MEM_B_DQ<34>
MEM_B_DQ<35>
MEM_B_DQ<36>
MEM_B_DQ<37>
MEM_B_DQ<38>

MEM_B_DQ<40>
MEM_B_DQ<41>
MEM_B_DQ<42>
MEM_B_DQ<43>
MEM_B_DQ<44>
MEM_B_DQ<45>
MEM_B_DQ<46>
MEM_B_DQ<47>
MEM_B_DQ<48>
MEM_B_DQ<49>
MEM_B_DQ<50>
MEM_B_DQ<51>
MEM_B_DQ<52>
MEM_B_DQ<53>
MEM_B_DQ<54>
MEM_B_DQ<55>
MEM_B_DQ<56>
MEM_B_DQ<57>
MEM_B_DQ<58>
MEM_B_DQ<59>
MEM_B_DQ<60>
MEM_B_DQ<61>
MEM_B_DQ<62>
MEM_B_DQ<63>

MEM_A_DQ<0>
MEM_A_DQ<1>
MEM_A_DQ<2>

MEM_A_DQ<4>

MEM_A_DQ<6>

MEM_A_CAS_L

MEM_A_BS<2>

MEM_A_DQ<8>

MEM_A_DQ<7>

MEM_A_DQ<5>

MEM_A_DQ<3>

MEM_A_BS<1>

MEM_A_BS<0>

MEM_A_DM<0>
MEM_A_DM<1>

MEM_A_DM<3>

MEM_A_DM<2>

MEM_A_DM<5>

MEM_A_DM<4>

MEM_A_DM<7>

MEM_A_DM<6>

MEM_A_DQS_P<0>
MEM_A_DQS_P<1>
MEM_A_DQS_P<2>
MEM_A_DQS_P<3>
MEM_A_DQS_P<4>
MEM_A_DQS_P<5>
MEM_A_DQS_P<6>
MEM_A_DQS_P<7>

MEM_A_DQS_N<1>

MEM_A_DQS_N<0>

MEM_A_DQS_N<2>

MEM_A_DQS_N<4>

MEM_A_DQS_N<3>

MEM_A_DQS_N<5>
MEM_A_DQS_N<6>
MEM_A_DQS_N<7>

MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_DQ<9>
MEM_A_DQ<10>
MEM_A_DQ<11>
MEM_A_DQ<12>
MEM_A_DQ<13>
MEM_A_DQ<14>
MEM_A_DQ<15>
MEM_A_DQ<16>
MEM_A_DQ<17>
MEM_A_DQ<18>
MEM_A_DQ<19>
MEM_A_DQ<20>
MEM_A_DQ<21>
MEM_A_DQ<22>
MEM_A_DQ<23>
MEM_A_DQ<24>
MEM_A_DQ<25>
MEM_A_DQ<26>
MEM_A_DQ<27>
MEM_A_DQ<28>
MEM_A_DQ<29>
MEM_A_DQ<30>
MEM_A_DQ<31>
MEM_A_DQ<32>
MEM_A_DQ<33>
MEM_A_DQ<34>

MEM_A_DQ<36>
MEM_A_DQ<37>
MEM_A_DQ<38>
MEM_A_DQ<39>
MEM_A_DQ<40>
MEM_A_DQ<41>
MEM_A_DQ<42>
MEM_A_DQ<43>
MEM_A_DQ<44>
MEM_A_DQ<45>
MEM_A_DQ<46>
MEM_A_DQ<47>
MEM_A_DQ<48>
MEM_A_DQ<49>
MEM_A_DQ<50>
MEM_A_DQ<51>
MEM_A_DQ<52>
MEM_A_DQ<53>
MEM_A_DQ<54>
MEM_A_DQ<55>
MEM_A_DQ<56>
MEM_A_DQ<57>
MEM_A_DQ<58>
MEM_A_DQ<59>
MEM_A_DQ<60>
MEM_A_DQ<61>
MEM_A_DQ<62>
MEM_A_DQ<63>

Preliminary

VCC_SM20

VCC_AXG_NCTF42

VCC_SM9

VCC_SM10

VCC_SM17

VCC_SM16

VCC3

VCC_SM5

VCC_SM8

VCC_AXG_NCTF1
VCC_AXG_NCTF2
VCC_AXG_NCTF3
VCC_AXG_NCTF4
VCC_AXG_NCTF5
VCC_AXG_NCTF6

VCC_AXG_NCTF8

VCC_AXG_NCTF7

VCC_AXG_NCTF10

VCC_AXG_NCTF9

VCC_AXG_NCTF11
VCC_AXG_NCTF12
VCC_AXG_NCTF13
VCC_AXG_NCTF14
VCC_AXG_NCTF15
VCC_AXG_NCTF16

VCC_AXG_NCTF18

VCC_AXG_NCTF17

VCC_AXG_NCTF20

VCC_AXG_NCTF19

VCC_AXG_NCTF21
VCC_AXG_NCTF22

VCC_AXG_NCTF25
VCC_AXG_NCTF26

VCC_AXG_NCTF28

VCC_AXG_NCTF27

VCC_AXG_NCTF29
VCC_AXG_NCTF20
VCC_AXG_NCTF31
VCC_AXG_NCTF32
VCC_AXG_NCTF33
VCC_AXG_NCTF34
VCC_AXG_NCTF35
VCC_AXG_NCTF36

VCC_AXG_NCTF38

VCC_AXG_NCTF37

VCC_AXG_NCTF40

VCC_AXG_NCTF39

VCC_AXG_NCTF41

VCC_AXG_NCTF43
VCC_AXG_NCTF44
VCC_AXG_NCTF45
VCC_AXG_NCTF46

VCC_AXG_NCTF48

VCC_AXG_NCTF47

VCC_AXG_NCTF49
VCC_AXG_NCTF50
VCC_AXG_NCTF51

VCC_AXG_NCTF55

VCC_AXG_NCTF58

VCC_AXG_NCTF57

VCC_AXG_NCTF59

VCC_AXG_NCTF61

VCC_AXG_NCTF60

VCC_AXG_NCTF62
VCC_AXG_NCTF63
VCC_AXG_NCTF64

VCC_AXG_NCTF66

VCC_AXG_NCTF65

VCC_AXG_NCTF67
VCC_AXG_NCTF68
VCC_AXG_NCTF69

VCC_AXG_NCTF71

VCC_AXG_NCTF70

VCC_AXG_NCTF72
VCC_AXG_NCTF73
VCC_AXG_NCTF74

VCC_AXG_NCTF76

VCC_AXG_NCTF75

VCC_AXG_NCTF77
VCC_AXG_NCTF78
VCC_AXG_NCTF79

VCC_AXG_NCTF81

VCC_AXG_NCTF80

VCC_AXG_NCTF82
VCC_AXG_NCTF83

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

VCC_AXG_NCTF56

VCC_AXG_NCTF54

VCC_AXG_NCTF53

VCC_AXG_NCTF52

VCC_AXG1

VCC_AXG2

VCC_AXG3

VCC_AXG4

VCC_AXG5

VCC_AXG6

VCC_AXG7

VCC_AXG8

VCC_AXG9

VCC_AXG10

VCC_AXG11

VCC_AXG12

VCC_AXG13

VCC_AXG14

VCC_AXG15

VCC_AXG16

VCC_AXG17

VCC_AXG18

VCC_AXG19

VCC_AXG20

VCC_AXG21

VCC_AXG22

VCC_AXG23

VCC_AXG24

VCC_AXG25

VCC_AXG26

VCC_AXG27

VCC_AXG28

VCC_AXG29

VCC_AXG30

VCC_AXG31

VCC_AXG32

VCC_AXG33

VCC_AXG34

VCC_SM1

VCC_SM2

VCC_SM3

VCC_SM4

VCC_SM6

VCC_SM7

VCC_SM11

VCC_SM12

VCC_SM13

VCC_SM14

VCC_SM15

VCC_SM18

VCC_SM19

VCC_SM21

VCC_SM22

VCC_SM23

VCC_SM26

VCC_SM27

VCC_SM28

VCC_SM29

VCC_SM30

VCC_SM31

VCC_SM32

VCC_SM33

VCC_SM34

VCC_SM35

VCC_SM36

VCC_SM25

VCC_SM24

VCC1

VCC2

VCC7

VCC8

VCC9

VCC10

VCC11

VCC12

VCC13

VCC_AXG_NCTF24

VCC_AXG_NCTF23

VCC6

VCC5

VCC4

VCC GFX

VCC SM

VCC SM LF

(6 OF 10)

VCC CORE

POWER

VCC GFX NCTF

VCC_NCTF49

VCC_NCTF15

VCC_NCTF2

VCC_NCTF10

VCC_AXM7

VCC_AXM5

VCC_AXM4

VCC_AXM3

VCC_AXM2

VCC_AXM1

VSS_SCB6

VSS_SCB5

VSS_SCB4

VSS_SCB3

VSS_SCB2

VSS_SCB1

VCC_NCTF11
VCC_NCTF12
VCC_NCTF13
VCC_NCTF14

VSS_NCTF21

VSS_NCTF20

VSS_NCTF19

VSS_NCTF18

VSS_NCTF17

VSS_NCTF16

VSS_NCTF15

VSS_NCTF14

VSS_NCTF12

VSS_NCTF11

VSS_NCTF13

VSS_NCTF10

VSS_NCTF9

VSS_NCTF8

VSS_NCTF7

VSS_NCTF6

VSS_NCTF5

VSS_NCTF4

VSS_NCTF3

VSS_NCTF2

VSS_NCTF1

VCC_NCTF22

VCC_NCTF27

VCC_NCTF50

VCC_NCTF47
VCC_NCTF48

VCC_NCTF44

VCC_NCTF43

VCC_NCTF39
VCC_NCTF40

VCC_NCTF38

VCC_NCTF37

VCC_NCTF34
VCC_NCTF35

VCC_NCTF33

VCC_NCTF32

VCC_NCTF31

VCC_NCTF29

VCC_NCTF28

VCC_NCTF26

VCC_NCTF24
VCC_NCTF25

VCC_NCTF23

VCC_NCTF21

VCC_NCTF18
VCC_NCTF19

VCC_NCTF16
VCC_NCTF17

VCC_NCTF3
VCC_NCTF4

VCC_NCTF41
VCC_NCTF42

VCC_NCTF45
VCC_NCTF46

VCC_AXM6

VCC_AXM_NCTF1
VCC_AXM_NCTF2
VCC_AXM_NCTF3
VCC_AXM_NCTF4
VCC_AXM_NCTF5
VCC_AXM_NCTF6
VCC_AXM_NCTF7
VCC_AXM_NCTF8
VCC_AXM_NCTF9
VCC_AXM_NCTF10
VCC_AXM_NCTF11
VCC_AXM_NCTF12
VCC_AXM_NCTF13
VCC_AXM_NCTF14
VCC_AXM_NCTF15
VCC_AXM_NCTF16
VCC_AXM_NCTF17
VCC_AXM_NCTF18
VCC_AXM_NCTF19

VCC_NCTF8

VCC_NCTF20

VCC_NCTF1

VCC_NCTF5
VCC_NCTF6
VCC_NCTF7

VCC_NCTF36

VCC_NCTF30

VCC_NCTF9

VCC AXM NCTF

VCC NCTF

VSS SCBVCC AXM

VSS NCTF

(7 OF 10)

POWER

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

1395 mA (1 ch, 533MHz)

1700 mA (1 ch, 667MHz)

2700 mA (2 ch, 533MHz)

3300 mA (2 ch, 667MHz)

540 mA

1573 mA (Int Graphics)

1310 mA (Ext Graphics)

7700 mA (Int Graphics)

5 mA (standby)

impacting part performance.

These connections can break without

NCTF balls are Not Critical To Function

Current numbers from Crestline EDS, doc #21749.

OMIT

CRESTLINE

FCBGA

U1400

AT35

AH31
AH29
AF32

R30

AT34
AH28

AC31

AC32

AK32
AJ31
AJ28
AH32

R20

AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29

T14

AD20
AD23
AD24
AD28
AF21
AF26
AA31
AH20
AH21
AH23

W13

AH24
AH26
AD31
AJ20
AN14

W14

Y12
AA20
AA23
AA26
AA28

T17

U17
U19
U20
U21
U23
U26
V16
V17
V19
V20

T18

V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23

T19

Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17

T21

AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19

T22

AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21

T23

AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17

T25

AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26

U15

V26
V28
V29
Y31

U16

AU32

BA35
BB33
BC32
BC33
BC35
BD32
BD35
BE32
BE33
BE35

AU33

BF33
BF34
BG32
BG33
BG35
BH32
BH34
BH35
BJ32
BJ33

AU35

BJ34
BK32
BK33
BK34
BK35
BL33
AU30

AV33
AW33
AW35
AY35
BA32
BA33

AW45
BC39
BE39
BD17
BD4
AW8
AT6

OMIT

CRESTLINE

FCBGA

U1400

AT33
AT31
AK29
AK24
AK23
AJ26
AJ23

AL24

AP29
AP31
AP32
AP33
AL29
AL31
AL32
AR31
AR32
AR33

AL26
AL28
AM26
AM28
AM29
AM31
AM32
AM33

AB33

AF36
AH33
AH35
AH36
AH37
AJ33
AJ35
AK33
AK35
AK36

AB36

AK37
AD33
AJ36
AM35
AL33
AL35
AA33
AA35
AA36
AP35

AB37

AP36
AR35
AR36

Y32
Y33
Y35
Y36
Y37
T30
T34

AC33

T35
U29
U31
U32
U33
U35
U36
V32
V33
V36

AC35

V37

AC36
AD35
AD36
AF33

T27

AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15

T37

AR19
AR28

U24
U28
V31
V35
AA19
AB17
AB35

A3
B2
C1
BL1
BL51
A51

402

0.1uF

10V

CERM

20%

C1806

1

2

402

0.1uF

10V

CERM

20%

C1807

1

2

402

X5R

0.22UF

6.3V

20%

C1804

1

2

402

X5R

0.22UF

6.3V

20%

C1805

1

2

402

10%

CERM

1uF

6.3V

C1802

1

2

402

10%

0.47UF

6.3V

CERM-X5R

C1803

1

2

402

10%

CERM

1uF

6.3V

C1801

1

2

18

109

16

051-7261

NB Power 1

SYNC_DATE=01/25/2007

SYNC_MASTER=T9_NOME

=PP1V05_S0M_NB_VCCAXM

NB_VCCSM_LF5

NB_VCCSM_LF7

=PPVCORE_S0_NB

=PP1V05_S0M_NB_VCCAXM

NB_VCCSM_LF1
NB_VCCSM_LF2
NB_VCCSM_LF3
NB_VCCSM_LF4

NB_VCCSM_LF6

=PPVCORE_S0_NB_GFX

=PPVCORE_S0_NB

=PPVCORE_S0_NB_GFX

=PP1V8_S3M_MEM_NB

22

22

21

21

21

22

21 22

21

18

18

18

18

18 18

16

8

8

8

8

8 8

8

Preliminary

VCCA_CRT_DAC1

VTT7
VTT8

VCC_AXD_NCTF

VCCD_CRT

VCC_RXR_DMI1
VCC_RXR_DMI2

VTT1

VCCA_SM_CK2 VCC_TX_LVDS

VCC_HV2

VCC_PEG1
VCC_PEG2
VCC_PEG3

VCC_AXF2

VCC_AXD1
VCC_AXD2

VSSA_LVDS

VCCA_SM5

VCCA_PEG_PLL

VCCA_MPLL

VCCA_HPLL VTT16

VTT17

VTT15

VCCD_LVDS2

VCCD_LVDS1

VCCD_PEG_PLL

VCCD_HPLL

VCCD_QDAC

VCCD_TVDAC

VCCA_TVC_DAC1
VCCA_TVC_DAC2

VCCA_TVB_DAC2

VCCA_TVB_DAC1

VCCA_TVA_DAC2

VCCA_TVA_DAC1

VCCA_SM_CK1

VCCA_SM2

VCCA_SM1

VCCA_SM_NCTF2

VCCA_SM_NCTF1

VCCA_SM11

VCCA_SM10

VCCA_SM9

VCCA_SM8

VCCA_SM7

VCCA_SM4

VCCA_SM3

VSSA_PEG_BG

VCCA_PEG_BG

VCCA_LVDS

VCCA_DPLLB

VCCA_DPLLA

VSSA_DAC_BG

VCCA_DAC_BG

VCC_AXF3

VCC_HV1

VCC_PEG5

VTTLF1

VTTLF3

VTTLF2

VCC_PEG4

VCC_SM_CK3

VCC_SM_CK2

VCC_SM_CK1

VCC_SM_CK4

VCC_DMI

VCC_AXF1

VTT22

VCC_AXD6

VCC_AXD5

VCC_AXD4

VCC_AXD3

VTT19

VTT2

VTT6

VTT5

VTT11

VTT10

VTT9

VTT13

VTT12

VTT14

VTT18

VTT21

VTT20

VTT3
VTT4

VCCA_CRT_DAC2

VCC_SYNC

CRT

AXD

PEG

HV

AXF

VTTLF

VTT

SM CK

DMI

TV/CRT

D

LVDS

A SMA CK

CRT A LVDS

A PEG

PLL

(8 OF 10)

POWER

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

550 mA (533MHz DDR)

640 mA (667MHz DDR)

Current numbers from Crestline EDS, doc #21749.

515 mA

495 mA

850 mA @ 800MHz FSB (1.05V)

35 mA

100 mA

60 mA

30 mA

80 mA

0.4 mA

260 mA

1260 mA

770 mA @ 667MHz FSB (1.05V)

150 mA

TBD mA @ 1067MHz FSB (1.25V)

S0 or S3M is acceptable

S0 or S3M is acceptable

5 mA

150 mA

250 mA

60 mA

40 mA

40 mA

40 mA

10 mA

100 mA

50 mA

5 mA

200 mA

100 mA

100 mA

100 mA

0.47UF

10%
CERM-X5R

402

6.3V

C1911

1

2

0.47UF

10%

6.3V
CERM-X5R
402

C1913

1

2

0.47UF

10%

6.3V
CERM-X5R
402

C1912

1

2

OMIT

FCBGA

CRESTLINE

U1400

AT23
AU28
AU24
AT29
AT25
AT30

AR29

B23
B21
A21

AJ50

C40
B40

AD51
W50
W51
V49
V50

AH50
AH51

BK24
BK23
BJ24
BJ23

J32

A43

A33
B33

A30

B49

H49

AL2

A41

AM2

K50

U51

AW18

AT18
AT17

AV19
AU19
AU18
AU17

AT22
AT21
AT19

BC29
BB29

AR17
AR16

C25
B25
C27
B27
B28
A28

M32

AN2

J41
H42

U48

N28

L29

B32

B41

K49

U13

U1
T13
T11
T10
T9
T7
T6
T5
T3
T2

U12

R3
R2
R1

U11
U9
U8
U7
U5
U3
U2

A7
F2
AH1

051-7261

16

109

19

NB Power 2

SYNC_DATE=01/25/2007

SYNC_MASTER=T9_NOME

NB_VTTLF_CAP2

=PP1V8_S0_NB_VCCD_LVDS

PP1V25_S0_NB_VCCA_DPLLA

PP1V25_S0M_NB_VCCA_HPLL

PP3V3_S0_NB_VCCA_TVDACA

=PP1V5_S0_NB_VCCD_CRT
PP1V5_S0_NB_VCCD_TVDAC

PP1V5_S0_NB_VCCD_QDAC

=PP1V25_S0M_NB_VCCD_HPLL

=GND_NB_VSSA_LVDS

PP3V3_S0_NB_VCCA_DAC_BG

PP1V25_S0M_NB_VCCA_MPLL

NB_VTTLF_CAP1

NB_VTTLF_CAP3

=PP1V25_S0_NB_VCCDMI

=GND_NB_VSSA_DAC_BG

=GND_NB_VSSA_PEG_BG

PP1V8_S0_NB_VCCTXLVDS

PP1V05_S0_NB_VCCPEG

=PP3V3_S0_NB_VCCHV

PP1V05_S0_NB_VCCRXRDMI

PP1V25_S0_NB_VCCAXF

PP1V25_S0M_NB_VCCAXD

PP3V3_S0_NB_VCCA_TVDACC

PP1V25_S0_NB_VCCA_DPLLB

PP3V3_S0_NB_VCCA_TVDACB

=PP1V25R1V05_S0_NB_VTT

PP1V8_S0_NB_VCCTXLVDS

PP3V3_S0_NB_VCCA_CRTDAC

=PP3V3_S0_NB_VCCSYNC

PP1V25_S0M_NB_VCCA_SM_CK

PP1V25_S0_NB_PEGPLL

PP1V8_S3M_NB_VCCSMCK

PP1V25_S0M_NB_VCCA_SM

=PP3V3_S0_NB_VCCA_PEG_BG

21

21

22

21

16

21

21

22

21

22

22

21

22

22

22

22

21

22

22

21

8

22

21

19

15

8

21

21

16

22

22

22

8

19

22

22

21

21

21

21

8

Preliminary

VSS198VSS99

VSS197VSS98

VSS196VSS97

VSS195VSS96

VSS194VSS95

VSS193VSS94

VSS192VSS93

VSS191VSS92

VSS190VSS91

VSS189VSS90

VSS188VSS89

VSS187VSS88

VSS186VSS87

VSS185VSS86

VSS184VSS85

VSS183VSS84

VSS182VSS83

VSS181VSS82

VSS180VSS81

VSS179VSS80

VSS178VSS79

VSS177VSS78

VSS176VSS77

VSS175VSS76

VSS174VSS75

VSS173VSS74

VSS172VSS73

VSS171VSS72

VSS170VSS71

VSS169VSS70

VSS168VSS69

VSS167VSS68

VSS166VSS67

VSS165VSS66

VSS164VSS65

VSS163VSS64

VSS162VSS63

VSS161VSS62

VSS160VSS61

VSS159VSS60

VSS158VSS59

VSS157VSS58

VSS156VSS57

VSS155VSS56

VSS154VSS55

VSS153VSS54

VSS152VSS53

VSS151VSS52

VSS150VSS51

VSS149VSS50

VSS148VSS49

VSS147VSS48

VSS146VSS47

VSS145VSS46

VSS144VSS45

VSS143VSS44

VSS142VSS43

VSS141VSS42

VSS140VSS41

VSS139VSS40

VSS138VSS39

VSS137VSS38

VSS136VSS37

VSS135VSS36

VSS134VSS35

VSS133VSS34

VSS132VSS33

VSS131VSS32

VSS130VSS31

VSS129VSS30

VSS128VSS29

VSS127VSS28

VSS126VSS27

VSS125VSS26

VSS124VSS25

VSS123VSS24

VSS122VSS23

VSS121VSS22

VSS120VSS21

VSS119VSS20

VSS118VSS19

VSS117

VSS116VSS17

VSS115VSS16

VSS114VSS15

VSS113VSS14

VSS112VSS13

VSS111VSS12

VSS110VSS11

VSS109VSS10

VSS108

VSS9

VSS107VSS8

VSS106VSS7

VSS105VSS6

VSS104VSS5

VSS103VSS4

VSS102

VSS101

VSS100

VSS1

VSS18

VSS2
VSS3

VSS

(9 OF 10)

VSS202

VSS289
VSS290
VSS291
VSS292

VSS295

VSS199 VSS287
VSS200 VSS288
VSS201

VSS203
VSS204

VSS293
VSS294

VSS208 VSS296
VSS209 VSS297
VSS210 VSS298
VSS211 VSS299
VSS212 VSS300
VSS213 VSS301
VSS214
VSS215
VSS216 VSS302
VSS217
VSS218
VSS219 VSS303
VSS220
VSS221
VSS222 VSS304
VSS223
VSS224
VSS225 VSS305
VSS226
VSS227
VSS228
VSS229 VSS306
VSS230 VSS307
VSS231 VSS308
VSS232 VSS309
VSS233 VSS310
VSS234 VSS311
VSS235 VSS312
VSS236 VSS313
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243

VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286

VSS207

VSS206

VSS205

(10 OF 10)

VSS

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NOTE: TDE = _P

Crestline Thermal Diode Pins

TDB_SENSE

NOTE: TDB = _N

Mainly for investigation. If not used,
alias these nets directly to GND.

TDB_FORCE

TDE_FORCE

TDE_SENSE

FCBGA

OMIT

CRESTLINE

U1400

A13

AB26

AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43

AB28 AY45

AY47
AY50
B10
B20
B24
B29
B30
B35
B38

AB31

B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12

AC10

BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40

AC13

BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23

AC3

BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24

AC39

BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8

AC43

BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29

AC47

BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37

AD1

BL47
C12
C16
C19
C28
C29
C33
C36
C41

A15

AD21
AD26
AD29

AD3
AD41
AD45
AD49

AD5
AD50

AD8

A17

AE10
AE14

AE6
AF20
AF23
AF24
AF31

AG2
AG38
AG43

A24

AG47
AG50

AH3
AH40
AH41

AH7

AH9
AJ11
AJ13
AJ21

AA21

AJ24
AJ29
AJ32
AJ43
AJ45
AJ49
AK20
AK21
AK26
AK28

AA24

AK31
AK51

AL1
AM11
AM13

AM3

AM4
AM41
AM45

AN1

AA29

AN38
AN39
AN43

AN5

AN7

AP4
AP48
AP50
AR11

AR2

AB20

AR39
AR44
AR47

AR7
AT10
AT14
AT41
AT49

AU1
AU23

AB23

AU29

AU3
AU36
AU49
AU51
AV39
AV48

AW1
AW12
AW16

FCBGA

OMIT

CRESTLINE

U1400

C46
C50

C7
D13
D24

D3
D32
D39
D45
D49
E10
E16
E24
E28
E32
E47
F19
F36

F4
F40
F50

G1
G13
G16
G19
G24
G28
G29
G33
G42
G45
G48

G8
H24
H28

H4
H45
J11
J16

J2
J24
J28
J33
J35
J39

K12
K47

K8

L1
L17
L20
L24
L28

L3
L33
L49
M28
M42
M46
M49

M5
M50

M9
N11
N14
N17
N29
N32
N36
N39
N44
N49

N7
P19

P2
P23

P3
P50
R49
T39
T43
T47
U41
U45
U50

V2

V3

W11
W39
W43
W47
W5
W7
Y13
Y2
Y41
Y45
Y49
Y5
Y50
Y11
P29

T29

T31

T33

R28

AA32
AB32
AD32
AF28
AF29
AT27
AV25
H50

051-7261

16

109

20

NB Grounds

SYNC_MASTER=T9_NOME

SYNC_DATE=01/25/2007

=NB_TDB_SENSE

=NB_TDB_FORCE

=NB_TDE_FORCE

=NB_TDE_SENSE

51

51

51

51

Preliminary

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Placeholder for 5.6nH, 0.9A, 45mOhm max

10uF caps should

Layout Note:

WF: "Place where LVDS

close to MCH

Place L and C

Layout Note:

Placeholder for 2.2nH, 1.4A, 17mOhm

10uF caps should

100 mA

250 mA

50 mA

150 mA

450 mA

be close to MCH
on opposite side.

Layout Note:

be close to MCH
on opposite side.

200 mA200 mA

100 mA

100 mA

100 mA

NOTE: This follower is redundant if VCORE is always 1.05V.

Layout Note: Route to caps, then GND

5 mA (standby)

1395 mA (1ch 533MHz)

1700 mA (1ch 667MHz)

2700 mA (2ch 533MHz)

3300 mA (2ch 667MHz)

675 mA (667MHz DDR2)
585 mA (533MHz DDR2)

515 mA 515 mA

0.4 mA

35 mA

640 mA (667MHz DDR2)
550 mA (533MHz DDR2)

495 mA 495 mA

1260 mA1520 mA

260 mA

Current numbers from Crestline EDS, doc #21749.

GMCH FSB I/O Rail

1310mA (Ext Graphics)

Placeholder for 3.9nH, 1A, 32mOhm

and DDR2 taps." (C2135)

770 mA (667MHz FSB)

GMCH Memory I/O Rail

850 mA (800MHz FSB)

540 mA

GMCH ME Core Power

WF: Matanzas has 2-pin 270uF bulk cap

1573mA (Int Graphics)

GMCH Core Power

0.47UF

10%
CERM-X5R

PLACEMENT_NOTE=Place close to U1400

6.3V
402

C2124

1

2

CERM1

603

2.2uF

PLACEMENT_NOTE=Place close to U1400

20%

6.3V

C2123

1

2

6.3V

20%

CERM

PLACEMENT_NOTE=Place close to U1400

603

4.7uF

C2121

1

2

20%
CERM

402

0.1uF

10V

C2161

1

2

20%
CERM

402

0.1uF

10V

C2165

1

2

2.5V

470UF

D2T

CRITICAL

TANT

20%

C2100

1

2 3

20%
CERM

402

0.1uF

PLACEMENT_NOTE=Place in GMCH cavity

10V

C2113

1

2

X5R

6.3V

20%

402

0.22uF

C2112

1

2

0.22uF

X5R

6.3V

20%

402

C2111

1

2

22UF

805-3

CERM-X5R

6.3V

20%

C2110

1

2

20%

402

0.1uF

10V

PLACEMENT_NOTE=Place in GMCH cavity

CERM

C2114

1

2

20%
CERM

402

0.1uF

10V

PLACEMENT_NOTE=Place in GMCH cavity

C2115

1

2

6.3V

20%

CERM

PLACEMENT_NOTE=Place close to U1400

603

4.7uF

C2122

1

2

22UF

805-3

CERM-X5R

PLACEMENT_NOTE=Place close to U1400

20%

6.3V

C2131

1

2

22UF

805-3

CERM-X5R

PLACEMENT_NOTE=Place close to U1400

20%

6.3V

C2132

1

2

10V
402

CERM

20%

0.1uF

C2135

1

2

402

1%
1/16W
MF-LF

0.51

R2183

1

2

20%
CERM

402

0.1uF

10V

C2191

1

2

MF-LF

1/16W

1%

1.1

402

R2190

1

2

FERR-220-OHM

0805

L2190

1 2

603

X5R

6.3V

20%

10uF

C2190

1

2

20%
CERM

402

0.1uF

10V

C2192

1

2

20%
CERM

402

0.1uF

10V

PLACEMENT_NOTE=Place C2180 by U1400.AN2

C2180

1

2

CRITICAL

330uF

20%

6.3V
POLY

D3L

C2130

1

2

330uF

20%

6.3V
POLY

D3L

CRITICAL

C2120

1

2

X5R

6.3V

10uF

603

20%

C2174

1

2

POLY

20%

220UF

2.5V

CASE-B2

CRITICAL

C2173

1

2

1210

91NH

L2173

1 2

0.1uF

20%
CERM

402

10V

C2197

1

2

1.1

1/16W

1%

MF-LF

402

R2195

1

2

1.0UH-220MA-0.12-OHM

0805

L2195

1 2

X5R

6.3V

20%

10uF

603

C2195

1

2

22UF

805-3

CERM-X5R

20%

6.3V

C2196

1

2

20%
CERM

402

0.1uF

10V

C2160

1

2

1uF

402

10%
10V
X5R

C2171

1

2

10uF

20%

6.3V
X5R
603

C2170

1

2

0

1/10W
MF-LF

5%

603

R2170

1 2

402

1uF

10%
10V
X5R

C2151

1

2

603

0

MF-LF

1/10W

5%

R2150

1 2

FERR-120-OHM-0.2A

0603

NO STUFF

L2150

1 2

22UF

805-3

CERM-X5R

20%

6.3V

C2142

1

2

22UF

805-3

CERM-X5R

NO STUFF

20%

6.3V

C2141

1

2

603

CERM

20%

6.3V

4.7UF

C2143

1

2

330uF

20%

6.3V
POLY

D3L

CRITICAL

C2140

1

2

10V

10%

402

1uF

X5R

C2144

1

2

603

MF-LF

1/10W

5%

0

R2141

1 2

22UF

805-3

CERM-X5R

6.3V

20%

C2145

1

2

5%
1/10W
MF-LF

603

0

R2145

1 2

10V

0.1uF

402

20%
CERM

C2148

1

2

402

10

MF-LF

1%

1/16W

R2186

1 2

SOT23

BAT54E3

D2186

1 3

402

1/16W

1%

MF-LF

10

R2185

1 2

SOT23

BAT54E3

D2185

1 3

22UF

805-3

CERM-X5R

20%

6.3V

NO STUFF

C2150

1

2

CERM1
603

2.2uF

20%

6.3V

NO STUFF

C2146

1

2

FERR-120-OHM-0.2A

0603

L2181

1 2

PLACEMENT_NOTE=Place in GMCH cavity

20%
CERM

402

0.1uF

10V

C2104

1

2

X5R

6.3V

20%

10uF

603

C2177

1

2

X5R

6.3V

20%

402

PLACEMENT_NOTE=Place in GMCH cavity

0.22uF

C2103

1

2

X5R

6.3V

20%

402

PLACEMENT_NOTE=Place in GMCH cavity

0.22uF

C2102

1

2

20%
CERM

402

0.1uF

PLACEMENT_NOTE=Place C2184 by U1400.AM2

10V

C2184

1

2

20%
CERM

402

0.1uF

10V

PLACEMENT_NOTE=Place C2182 by U1400.AL2

C2182

1

2

805-3

CERM-X5R

22UF

20%

6.3V

C2181

1

2

FERR-120-OHM-0.2A

0603

L2183

1 2

805-3

CERM-X5R

22UF

20%

6.3V

C2183

1

2

6.3V

20%

PLACEMENT_NOTE=Place in GMCH cavity

CERM-X5R
805-3

22UF

C2101

1

2

NB Standard Decoupling

SYNC_DATE=12/21/2006

109

21

16

051-7261

SYNC_MASTER=T9_NOME

=PPVCORE_S0_NB

=PP1V05_S0M_NB_VCCAXM

MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.25V

MIN_LINE_WIDTH=0.4 MM

PP1V25_S0M_NB_VCCA_SM

=PP1V8_S3M_MEM_NB

MIN_LINE_WIDTH=0.5 MM
VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_NB_VCCPEG

MAKE_BASE=TRUE

=PP1V25_S0M_NB_VCCA

=PP1V25R1V05_S0_NB_VTT

MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.25V

MIN_LINE_WIDTH=0.4 MM

PP1V25_S0M_NB_VCCA_SM_CK

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_NB_VCCRXRDMI

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.25V

MIN_LINE_WIDTH=0.25 MM

PP1V25_S0M_NB_VCCA_HPLL

=GND_NB_VSSA_PEG_BG

=PP3V3_S0_NB_VCCHV

PP1V25_S0M_NB_VCCA_MPLL

MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.25V

MIN_LINE_WIDTH=0.3 MM

=PP1V25_S0M_NB_PLL

=PP1V25_S0_NB_VCCDMI

PP1V25_S0M_NB_MPLL_RC

MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.25V

MIN_LINE_WIDTH=0.3 MM

=PP1V25_S0M_NB_VCCD_HPLL

=PP3V3_S0_NB_FOLLOW

PP3V3_S0_NB1V05_FOLLOW_R

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM

VOLTAGE=3.3V

PP3V3_S0_NBCORE_FOLLOW_R

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

=PPVCORE_S0_NB_FOLLOW

=PP3V3_S0_NB_VCCA_PEG_BG

VOLTAGE=1.8V

PP1V8_S3M_NB_VCCSMCK_RC

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM

=PP1V05_S0_NB_FOLLOW

=PP1V25_S0_NB_VCC

MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.25V

MIN_LINE_WIDTH=0.4 MM

PP1V25_S0_NB_VCCAXF

=PP1V05_S0_NB_PCIE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V25_S0M_NB_VCCAXD

VOLTAGE=1.25V

=PP1V25_S0_NB_PLL

VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

PP1V25_S0_NB_PEGPLL

VOLTAGE=1.25V

MIN_LINE_WIDTH=0.25 MM

PP1V25_S0_NB_PEGPLL_RC

MIN_NECK_WIDTH=0.2 MM

=PP1V25_S0M_NB_VCC

=PP1V8_S3M_NB_VCC

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

PP1V8_S3M_NB_VCCSMCK

22

18

19

18

18

16

19

19

16

19 19

19

8

8

19

8

15

8

8

19

19

19

19

8

19

8

8

19

8

8

8

8

8

19

8

16

8

19

8

8

19

Preliminary

IN

OUT

EN

NR/FB

IN

GND

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NOTE: This filter is required even if using only external graphics.

100 mA

(1.7V - 5.5V)

100 mA

100 mA

These 2 caps should be
within 6.35 mm of NB edge

Layout Note:

60 mA

Current numbers from Crestline EDS Addendum, doc #20127.

150 mA

110 mA260 mA

Crestline LVDS Support

65 mA

Layout Note: Route to cap, then GND

Vout = 1.25V (Factory Programmed)

7700 mA

VCCD_TVDAC also powers internal thermal sensors.

GMCH Graphics Core Power

2.37K

1%
1/16W
MF-LF

402

R2299

1

2

84 15

1UF

10%

402

CERM

6.3V

C2265

1

2

CRITICAL

SOT23-5

TPS731125

U2265

3

2

1

4

5

10%
16V

402

CERM

0.01UF

C2266

1

2

1/10W

0.300

603

FF

5%

R2260

1

2

NO STUFF

402

5%

4.7

MF-LF

1/16W

R2261

1 2

NO STUFF

20%
CERM

402

0.1uF

10V

C2261

1

2

1/16W

5%

4.7

402

MF-LF

R2262

1 2

0.1uF

20%
CERM

402

10V

C2262

1

2

X5R

6.3V

20%

10UF

603

C2260

1

2

CERM

50V

10%
402

0.001UF

C2223

1

2

0.001UF

CERM

50V

10%
402

C2221

1

2

22000pF-1000mA

16V

NFM18

C2201

2

1 3

20%
CERM

402

10V

0.1uF

C2200

1

2

1210

1.0UH-0.5A

L2220

1 2

CASE-D3L

CRITICAL

POLY

6.3V

20%

220UF

C2220

1

2

0.1uF

20%
CERM

402

10V

PLACEMENT_NOTE=Place in GMCH cavity

C2217

1

2

20%

0.1uF

10V

PLACEMENT_NOTE=Place in GMCH cavity

402

CERM

C2216

1

2

402

10%

PLACEMENT_NOTE=Place in GMCH cavity

6.3V
CERM-X5R

0.47UF

C2215

1

2

20%

6.3V
X5R

PLACEMENT_NOTE=Place in GMCH cavity

10uF

603

C2213

1

2

CRITICAL

6.3V

20%

PLACEMENT_NOTE=Place in GMCH cavity

22UF

CERM-X5R
805-3

C2212

1

2

2.5V
D2T

470UF

20%

TANT

CRITICAL

C2211

1

2 3

20%

2.5V
D2T

TANT

470UF

CRITICAL

C2210

1

2 3

1UF

10%
402

CERM

6.3V

C2226

1

2

6.3V
CERM

10%

1UF

PLACEMENT_NOTE=Place in GMCH cavity

402

C2214

1

2

SYNC_DATE=03/20/2007

NB Graphics Decoupling

051-7261

16

109

22

SYNC_MASTER=M75_MLB

=PPVCORE_S0_NB_GFX

NB_CLK100M_DPLLSS_P

=PP1V8_S0_NB_VCCD_LVDS

=GND_NB_VSSA_LVDS

PP1V8_S0_NB_VCCTXLVDS

MIN_LINE_WIDTH=0.2 MM
VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 MM

=NB_CLK100M_DPLLSS_N

=NB_CLK100M_DPLLSS_P

=NB_CLK96M_DOT_N

=PPVCORE_S0_NB

LVDS_IBG

=PP1V8_S0_NB_LVDS

PP1V25_S0_NB_VCCA_DPLLA

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.25V

VOLTAGE=1.5V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.3 MM

PP1V5_S0_NB_VCCD_TVDAC

MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.25V

MIN_LINE_WIDTH=0.3 MM

PP1V25_S0_NB_VCCA_DPLLB

P1V25S0NBDPLL_NR

MIN_LINE_WIDTH=0.4 MM
VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 MM

PP1V25_S0_NB_DPLL

MIN_NECK_WIDTH=0.2 MM

GND_DPLL_ESR

MIN_LINE_WIDTH=0.4 MM
VOLTAGE=0V

=PPVIN_S0_NB_DPLL

TV_DCONSEL<1>

TV_DCONSEL<0>

SDVO_CTRLDATA

SDVO_CTRLCLK

PP3V3_S0_NB_VCCA_TVDACC

PP3V3_S0_NB_VCCA_TVDACB

PP3V3_S0_NB_VCCA_TVDACA

PP3V3_S0_NB_VCCA_DAC_BG

PP3V3_S0_NB_VCCA_CRTDAC

PP1V5_S0_NB_VCCD_QDAC

CRT_DDC_DATA

CRT_DDC_CLK

=TV_C_RTN

=TV_C_DAC

=TV_B_RTN

=TV_B_DAC

=TV_A_RTN

=TV_A_DAC

=PP3V3_S0_NB_VCCSYNC

=PP1V5_S0_NB_VCCD_CRT

=NB_CLK96M_DOT_P

=GND_NB_VSSA_DAC_BG

=CRT_VSYNC_R
=CRT_TVO_IREF

=CRT_RED_L

=CRT_RED

=CRT_HSYNC_R

=CRT_GREEN_L

=CRT_GREEN

=CRT_BLUE_L

=CRT_BLUE

=PP1V5_S0_NB_TVDAC

NB_CLK100M_DPLLSS_N

TP_LVDS_VREFH

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_VREFLTP_LVDS_VREFL

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_VREFH

88

21

88

18

30

18

30

8

7

19

19

19

16

16

16

8

8

19

19

19

8

15

15

16

16

19

19

19

19

19

19

15

15

15

15

15

15

15

15

19

19

16

19

15

15

15

15

15

15

15

15

15

8

7

15

15

Preliminary

SATA0RXP

SATA0RXN

SATALED*

RTCRST*

HDA_BIT_CLK

DDREQ

RTCX1
RTCX2

DCS1*
DCS3*

IDEIRQ

DDACK*

IORDY

DIOR*
DIOW*

DD11
DD12

DD4

DD2

DD14

DD0

DD15

DD1

DD13

DD5

DD10

DD8

DD3

DD9

LDRQ0*

FWH2/LAD2
FWH3/LAD3

FWH1/LAD1

LDRQ1*/GPIO23

FWH0/LAD0

FWH4/LFRAME*

HDA_SDIN0

HDA_SYNC

SATA1TXN
SATA1TXP

HDA_SDIN1
HDA_SDIN2

RCIN*

SATA0TXP

SATA0TXN

CPUPWRGD/GPIO49

SMI*

A20M*

SATA1RXP

SATA1RXN

SATARBIAS

SATARBIAS*

IGNNE*

DPRSTP*

INTVRMEN

A20GATE

SATA2RXN
SATA2RXP

THRMTRIP*

DPSLP*

INIT*

HDA_RST*

HDA_SDOUT

HDA_DOCK_EN*/GPIO33

SATA2TXN
SATA2TXP

FERR*

NMI

HDA_SDIN3

INTR

SATA_CLKP

SATA_CLKN

DA2

DD6

STPCLK*

TP8

DA0
DA1

HDA_DOCK_RST*/GPIO34

INTRUDER*

LAN_TXD0

LAN100_SLP

LAN_RSTSYNC

LAN_RXD0
LAN_RXD1
LAN_RXD2

DD7

LAN_TXD2

LAN_TXD1

GLAN_DOCK*/GPIO13

GLAN_COMPI
GLAN_COMPO

GLAN_CLK

LAN/GLANIHDA

CPU

RTC

LPC

(1 OF 6)

SATA

IDE

OUT

IN

IN

IN

BI

BI
BI

BI

BI

OUT

OUT

IN

IN

OUT

OUT

IN

IN
OUT
OUT

IN

IN

OUT

OUT

IN

IN

IN

IN

OUT
OUT

IN

OUT

OUT
OUT
OUT

IN
IN
IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT
OUT
OUT

OUT

OUT
OUT

OUT

OUT
OUT

IN

IN

OUT
OUT

OUT

OUT

OUT

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

INT PU

INT PU

INT PU

INT PD

HDA

24.000MHZ CLOCK W/INTERNAL WEAK PD

HDA_BIT_CLK
HDA_RST#
HDA_SDIN[0-2]
HDA_SDOUT
ACZ_SYNC

INTEGRATED PDs
INTEGRATED PD
INTEGRATED PD

INT PDINT PU

INT PD

INT PD

INT PD

INT PD

INT PD

INT PD

INT PU

INT PU

INT PU

NOTE: ALL IDE PINS HAVE INTERNAL 33-OHM SERIES R’S

OMIT

BGA

ICH8M

U2300

AF13
AG26

AG29

AA4
AA1
AB3

Y6
Y5

V1
U2

T4
V6
V5
U1
V2
U6

V3
T1
V4
T5
AB2
T6
T3
R2

Y2

W5

W4
W3

AF26
AE26

AD24

E5
F5
G8
F6

C4

B24

D25
C25

AH21

AJ16

AE10
AG14

AE14

AJ17
AH17
AH15
AD13

AE13

AJ15

Y3

AF27

AE24
AC20

AD22

AF25

Y1

AD21

D22

C21
B21
C22

D21
E20
C20

G9
E6

AD23

AH14

AF23

AG25
AF24

AF6
AF5
AH5
AH6

AG3
AG4
AJ4
AJ3

AF2
AF1
AE4
AE3

AB7
AC6

AF10

AG2

AG1

AG28

AA24

AE27

AA23

28

28

28

7

28

47 45

7

47 45

7

47 45

7

47 45

7

66 28

47 45

7

83 10

402

MF-LF

1/16W

5%

2.2K

NO STUFF

R2304

1

2

402

1%

24.9

MF-LF

1/16W

R2302

1

2

1%

332K

MF-LF
402

1/16W

R2301

1

2

86 80

86 80

86 80

86 80

86 42

86 42

86 42

86 42

86 42

86 42

86 42

86 42

88 30

88 30

42

42

83 59 16 10

7

83 10

7

83 10

83 13 10

7

86 42

86 42

86 42

86 42

86 42

86 42

86 42

86 42

86 42

86 42

86 42

86 42

86 42

86 42

86 42

86 42

86 42

86 42

86 42

86 42

86 42

86 42

86 42

86 42

86 42

83 10

7

83 10

83 10

83 10

83 47 10

83 10

10K

MF-LF
402

5%
1/16W

R2306

1

2

83 46 16 10

PLACEMENT_NOTE=Place R2308 within 50mm of U2300

1%

MF-LF

1/16W

24.9

402

R2308

1 2

86 34

1/16W

1%

332K

402

MF-LF

R2300

1

2

8.2K

5%
1/16W
MF-LF

402

R2303

1

2

86 34

86 34

86 34

86 34

402

MF-LF

1/16W

5%

8.2K

R2310

1

2

1%
1/16W
MF-LF

402

54.9

R2305

1

2

1%
1/16W
MF-LF
402

54.9

PLACEMENT_NOTE=Place R2309 within 50mm of R2308 (NO STUB)

R2309

1

2

402

33

MF-LF1/16W

5%

R2313

1 2

5%

1/16W MF-LF33402

R2314

1 2

1/16W33MF-LF

5% 402

R2315

1 2

5%

1/16W MF-LF

402

33

R2316

1 2

1/16W
402

MF-LF

10K

5%

R2311

1

2

86 42

86 42

16

23

109

051-7261

SYNC_MASTER=T9_NOME

SYNC_DATE=01/25/2007

SB Enet, Disk, FSB, LPC

TP_HDA_SDIN2
TP_HDA_SDIN3

HDA_SDIN0

TP_LAN_D2R<1>

TP_ENET_GLAN_CLK

TP_HDA_SDIN1

SATA_A_D2R_N

HDA_SDOUT

HDA_RST_L

HDA_BIT_CLK
HDA_SYNC

HDA_SDOUT_R

HDA_RST_L_R

HDA_SYNC_R

HDA_BIT_CLK_R

SATA_RBIAS_N
SATA_RBIAS_P

SB_CLK100M_SATA_N
SB_CLK100M_SATA_P

SATA_C_R2D_C_P

SATA_C_R2D_C_N

SATA_C_D2R_N
SATA_C_D2R_P

SATA_B_R2D_C_P

SATA_B_R2D_C_N

TP_LAN_R2D<1>

TP_LAN_D2R<0>

TP_LAN_RSTSYNC

TP_LAN_R2D<0>

TP_HDA_DOCK_RST_L

SATA_B_D2R_N
SATA_B_D2R_P

SATA_A_R2D_C_N
SATA_A_R2D_C_P

TP_SB_SATALED_L

SATA_A_D2R_P

TP_LAN_D2R<2>

TP_SB_TP8

SB_RCIN_L

TP_LPC_DRQ0_L

SB_A20GATE

CPU_FERR_L

=PP3V3_S0_SB_GPIO

=PP1V05_S0_SB_CPU_IO

IDE_PDDREQ

IDE_PDIORDY

IDE_IRQ14

IDE_PDDACK_L

IDE_PDIOR_L
IDE_PDIOW_L

IDE_PDCS1_L
IDE_PDCS3_L

IDE_PDA<2>

IDE_PDA<1>

IDE_PDA<0>

IDE_PDD<14>
IDE_PDD<15>

IDE_PDD<13>

IDE_PDD<11>
IDE_PDD<12>

IDE_PDD<9>
IDE_PDD<10>

IDE_PDD<8>

IDE_PDD<6>
IDE_PDD<7>

IDE_PDD<5>

IDE_PDD<4>

IDE_PDD<3>

IDE_PDD<1>
IDE_PDD<2>

IDE_PDD<0>

CPU_STPCLK_L

CPU_SMI_L

CPU_NMI

CPU_INTR

CPU_INIT_L

CPU_IGNNE_L

CPU_PWRGD

CPU_DPRSTP_L
CPU_DPSLP_L

CPU_A20M_L

CPU_THERMTRIP_R

PM_THRMTRIP_L

EXTGPU_PWR_EN

LPC_FRAME_L

LPC_AD<3>

LPC_AD<1>

LPC_AD<0>

LPC_AD<2>

TP_LAN_R2D<2>

SB_RTC_X1
SB_RTC_X2

SB_RTC_RST_L
SB_SM_INTRUDER_L

SB_LAN100_SLP

SB_INTVRMEN

HDA_DOCK_EN_L

PP3V3_G3_SB_RTC

GLAN_COMP

PP1V5_S0_SB_VCC1_5_B

=PP3V3_S0_SB_GPIO

LAN_ENERGY_DET

25

27

28

27

25

23

26

27

26

23

86

86

86

86

8

8

7

26

87

24

8

Preliminary

SPI_CS1*

PETN1

PERP1

OC4*/GPIO43
OC5*/GPIO29
OC6*/GPIO30
OC7*/GPIO31
OC8*
OC9*

SPI_MOSI

OC0*
OC1*/GPIO40
OC2*/GPIO41
OC3*/GPIO42

PERN5

DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP

DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP

DMI_CLKN
DMI_CLKP

PETP1

USBP9N
USBP9P

PERN2

USBP7N
USBP7P
USBP8N
USBP8P

PETN2

USBP6N
USBP6P

PERP3

USBP4N
USBP4P
USBP5N
USBP5P

PETN3
PETP3

USBP3N
USBP3P

PERN4
PERP4

USBP1N
USBP1P
USBP2N
USBP2P

PETN4
PETP4

USBP0N
USBP0P

PERP5

SPI_MISO

USBRBIAS

USBRBIAS*

PETP5

PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP

SPI_CLK
SPI_CS0*

DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP

DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP

DMI_IRCOMP

DMI_ZCOMP

PERN1

PERP2

PETP2

PERN3

PETN5

PCI_EXPRESS

DIRECT MEDIA INTERFACE

SPI

USB

(2 OF 6)

IN

IN
OUT
OUT

IN

IN
OUT
OUT

IN

IN
OUT
OUT

IN

IN
OUT
OUT

IN

IN

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

IN
IN
OUT
OUT

IN
IN
OUT
OUT

BI
BI

BI

BI

AD4
AD5

AD9

PIRQF*/GPIO3

PIRQE*/GPIO2

AD13

PME*

PCIRST*

GNT2*/GPIO53

C/BE2*

PIRQG*/GPIO4

SERR*

PIRQA*

AD1

REQ1*/GPIO50

C/BE3*

AD11

C/BE1*

AD25
AD26

AD0

AD2

DEVSEL*

AD18

AD21

PAR

GNT0*

AD7

GNT1*/GPIO51

C/BE0*

STOP*

AD20

AD16

GNT3*/GPIO55

TRDY*

IRDY*

AD22

PIRQC*

REQ2*/GPIO52

AD19

PCICLK

PLOCK*

AD15

PIRQB*

PIRQH*/GPIO5

PLTRST*

AD3

AD6

AD8

FRAME*

AD14

AD12

AD10

REQ3*/GPIO54

PIRQD*

AD17

PERR*

REQ0*

AD31

AD27
AD28

AD30

AD29

AD24

AD23

(3 OF 6)

INTERRUPT I/F

PCI

BI

BI

BI
BI
BI

BI

BI

BI
BI
BI

BI

BI

BI
BI
BI

BI

BI

BI
BI
BI

BI

BI

BI
BI
BI

BI

BI

BI
BI
BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

BI

BI

BI

BI

BI
BI

OUT

BI
BI
BI

BI

BI

BI

BI

OUT

IN

BI
BI

IN

IN

IN
IN
IN

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NOTE: GNT[0-3]# have internal 20K pull-ups
enabled only when PCIRST# = 0 and PWROK = 1

If used, ensure GNT2# is not low when PWROK
rises, or PCIe ports 5 & 6 will be disabled.

FireWire INT*

INT PU

INT PU

INT PU

INT PU

INT PU

Provide a pull-down on this GPIO if not used.

R2415 pull-down on GNT0#
selects SPI ROM by default.

SB BOOT BIOS SELECT

I/F
LPC

Nineveh-GLCI

Yukon-PCIE

PCIe Mini Card

SPI

NOTE:

0

GNT0#

1

GNT0# HAS INT PU; ENABLED ONLY WHEN PCIRST#=0 AND PWROK=H
SPI_CS1# HAS INT PU (NOMINAL=20K, SIMULATION=15K-35K)

high for x2)

pull HDA_SYNC

(x2-capable,

Ethernet

(AirPort)

FireWire

ExpressCard

Spares

INT PD

INT PD
INT PD

EHCI1

INT PU
INT PU

INT PU

INT PU

INT PD

INT PD

INT PD
INT PD

INT PD

INT PD

INT PD

INT PD

INT PD

INT PD

EHCI0

INT PD

INT PD

INT PD
INT PD
INT PD
INT PD

INT PD

External C

Camera

AirPort (PCIe Mini-Card)

ExpressCard

External B

Geyser Trackpad/Keyboard

External A

External D / WWAN

Bluetooth

IR

NOTE: USBP[0-9]P/N have internal 15K pull-downs.

1/16W

402

10K

5%

MF-LF

R2408

1

2

5%

10K

402

MF-LF

1/16W

R2407

1

2

MF-LF

1/16W

5%

402

10K

R2400

1

2

5%
MF-LF

402

1/16W

10K

R2409

1

2

1/16W

10K

5%

402

MF-LF

R2401

1

2

10K

MF-LF

1/16W

5%

402

R2402

1

2

5%

MF-LF

10K

1/16W

402

R2404

1

2

5%
1/16W

402

MF-LF

10K

R2403

1

2

OMIT

ICH8M

BGA

U2300

V27
V26
U29
U28

Y27
Y26
W29
W28

AB26
AB25
AA29
AA28

AD27
AD26
AC29
AC28

T26
T25

Y24

Y23

AJ19
AG16
AG15
AE15
AF15
AG17
AD12
AJ18
AD14
AH18

P27

M27

K27

H27

F27

D27

P26

M26

K26

H26

F26

D26

N29

L29

J29

G29

E29

C29

N28

L28

J28

G28

E28

C28

C23
B23
E22

F21

D23

G3
G2
H5
H4
H2
H1
J3
J2
K5
K4
K2
K1
L3
L2
M5
M4
M2
M1
N3
N2

F3

F2

84 16

84 16

84 16

84 16

84 16

84 16

84 16

84 16

84 16

84 16

84 16

84 16

84 16

84 16

84 16

84 16

88 30

88 30

24.9

1/16W MF-LF

4021%

R2413

1 2

86 43

86 43

86 34

86 34

86 44

86 44

86 44

86 44

86 80

7

86 80

7

86 80

86 80

86 80

86 80

86 34

86 34

86 34

86 34

86 34

86 34

1/16W

1%

402

MF-LF

22.6

R2414

1 2

87 34

87 34

87 34

87 34

87 35

87 35

87 35

87 35

86 56

86 56

86 56

86 56

OMIT

BGA

ICH8M

U2300

D20
E19

A12
E16
A14
G16
A15

B6

C11

A9
D11
B12

D19

C12
D10

C7
F13
E11
E13
E12

D8

A6

E8

A20

D6

A3

D17
A21
A19
C19
A18
B16 C17

E15
F16
E17

D16

A17

D7

C18

F18

C10

C8
D9

B10

G6

A7

F9

B5

C5
A10

F8
G11
F12
B3

B7

AG24

G7

A4

E18

B19

A11

F10
C16
C9

87 38

87 38

87 38

87 38

87 38

87 38

87 38

87 38

87 38

87 38

87 38

87 38

87 38

87 38

87 38

87 38

87 38

87 38

87 38

87 38

87 38

87 38

87 38

87 38

87 38

87 38

87 38

87 38

87 38

87 38

87 38

87 38

87 24

87 24

87 24

87 38 24

87 24

87 38 24

87 24

87 38

87 38

87 38

87 38

87 38 24

87 38

28

7

87 38 24

87 38 24

87 24

87 38 24

87 38 24

87 38 24

87 38 24

79 28

9 7

88 30

87 24

10K

1/16W
MF-LF
402

5%

R2405

1

2

10K

MF-LF

5%

1/16W

402

R2406

2

1

1K

MF-LF

1/16W

5%

402

R2415

1

2

8.2K

R2423

1 2

8.2K

R2424

1 2

8.2K

R2425

1 2

8.2K

R2426

1 2

8.2K

R2427

1 2

8.2K

R2428

1 2

8.2K

R2430

1 2

8.2K

R2429

1 2

8.2K

R2432

1 2

8.2K

R2431

1 2

8.2K

R2433

1 2

8.2K

R2437

1 2

8.2K

R2439

1 2

8.2K

R2438

1 2

8.2K

R2436

1 2

8.2K

R2440

1 2

87 24

8.2K

R2441

1 2

43 13

13

34 13

46 34

34

42 24

78

87 38

86 42

13

47

7

79 13

8.2K

R2442

1 2

13

36 13

13

SB PCI, PCIe, DMI, USB

SYNC_MASTER=T9_NOME

16

24

109

051-7261

SYNC_DATE=01/25/2007

DMI_N2S_N<0>
DMI_N2S_P<0>
DMI_S2N_N<0>
DMI_S2N_P<0>

DMI_N2S_N<1>
DMI_N2S_P<1>
DMI_S2N_N<1>
DMI_S2N_P<1>

DMI_N2S_N<2>
DMI_N2S_P<2>
DMI_S2N_N<2>
DMI_S2N_P<2>

DMI_N2S_N<3>
DMI_N2S_P<3>
DMI_S2N_N<3>
DMI_S2N_P<3>

SB_CLK100M_DMI_N
SB_CLK100M_DMI_P

USB_EXTA_N
USB_EXTA_P
USB_MINI_N
USB_MINI_P
USB_EXTD_N
USB_EXTD_P

USB_CAMERA_P

USB_CAMERA_N

USB_IR_N
USB_IR_P
USB_TPAD_N

USB_BT_N

USB_TPAD_P

USB_BT_P
USB_EXTB_N
USB_EXTB_P
USB_EXCARD_N

USB_EXTC_N

USB_EXCARD_P

USB_EXTC_P

PCIE_MINI_R2D_C_N

TP_PCIE_EXCARD_D2R_N

TP_PCIE_B_R2D_C_P

TP_PCIE_B_D2R_P

TP_PCIE_A_D2R_N

SPI_CE_R_L<0>

SPI_SCLK_R

PCIE_ENET_R2D_C_P

PCIE_ENET_R2D_C_N

PCIE_ENET_D2R_P

PCIE_ENET_D2R_N

PCIE_MINI_R2D_C_P

SPI_SO

PCIE_MINI_D2R_P

TP_PCIE_FW_R2D_C_P

TP_PCIE_FW_R2D_C_N

TP_PCIE_FW_D2R_P

TP_PCIE_FW_D2R_N

TP_PCIE_EXCARD_R2D_C_P

TP_PCIE_EXCARD_R2D_C_N

TP_PCIE_EXCARD_D2R_P

TP_PCIE_B_R2D_C_N

TP_PCIE_B_D2R_N

PCIE_MINI_D2R_N

USB_EXTD_OC_L

SPI_SI_R

EXCARD_OC_L

USB_EXTB_OC_L

PM_LATRIGGER_L

TP_PCIE_A_D2R_P
TP_PCIE_A_R2D_C_N

TP_SPI_CE_R_L<1>

DMI_IRCOMP_R

USB_RBIAS

PP1V5_S0_SB_VCC1_5_B

=PP3V3_S0_SB_PCI

PCI_PERR_L

PCI_DEVSEL_L

PCI_SERR_L

ODD_PWR_EN_L

INT_PIRQC_L

INT_PIRQF_L

PCI_LOCK_L
PCI_FW_REQ_L

PCI_FRAME_L
PCI_IRDY_L

PCI_STOP_L

PCI_REQ2_L
INT_PIRQA_L

INT_PIRQB_L

INT_PIRQD_L
INT_PIRQE_L

PCI_TRDY_L

PCI_REQ1_L

TP_PCIE_A_R2D_C_P

SB_GPIO30

USB_EXTC_OC_L

EXTGPU_LVDS_EN

USB_EXTA_OC_L
SB_GPIO40

=PP3V3_S5_SB_USB

MAKE_BASE=TRUE

PCI_FW_GNT_L
BOOT_LPC_SPI_L

TP_PCI_PME_L

TP_SB_GPIO53

PCI_REQ1_L
TP_SB_GPIO51

TP_SB_GPIO55

PCI_FW_REQ_L

PCI_REQ2_L

ODD_RST_5VTOL_L

PCI_C_BE_L<2>

PCI_C_BE_L<0>
PCI_C_BE_L<1>

PCI_C_BE_L<3>

PCI_IRDY_L
PCI_PAR
PCI_RST_L

PCI_PERR_L

PCI_DEVSEL_L

PCI_LOCK_L
PCI_SERR_L
PCI_STOP_L

PCI_FRAME_L

PCI_TRDY_L

PCI_CLK33M_SB

PLT_RST_L

INT_PIRQF_L

INT_PIRQE_L

DVI_HOTPLUG_DET
ODD_PWR_EN_L

PCI_AD<0>

PCI_AD<2>

PCI_AD<1>

PCI_AD<3>
PCI_AD<4>
PCI_AD<5>
PCI_AD<6>

PCI_AD<8>

PCI_AD<7>

PCI_AD<9>
PCI_AD<10>
PCI_AD<11>

PCI_AD<13>

PCI_AD<12>

PCI_AD<14>
PCI_AD<15>
PCI_AD<16>

PCI_AD<18>

PCI_AD<17>

PCI_AD<19>
PCI_AD<20>
PCI_AD<21>
PCI_AD<22>

PCI_AD<24>

PCI_AD<23>

PCI_AD<25>
PCI_AD<26>
PCI_AD<27>
PCI_AD<28>
PCI_AD<29>
PCI_AD<30>
PCI_AD<31>

INT_PIRQB_L

INT_PIRQA_L

INT_PIRQC_L
INT_PIRQD_L

WOW_EN

27

87

87

87

87

87

87

87

87

87

26

38

38

38

42

87

87

87

38

38

38

38

87

87

87

38

87

38

87

34

34

34

34

86

23

8

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

8

Preliminary

OUT
OUT

BI

IN

BI

IN
IN

SMBALERT*/GPIO11

STP_PCI*/GPIO15

BMBUSY*/GPIO0

SYS_RESET*

SUS_STAT*/LPCPD*

QRT_STATE0/GPIO27

THRM*

SMLINK0

GPIO12

SPKR

SDATAOUT1/GPIO48

QRT_STATE1/GPIO28

SLP_S5*

GPIO20

GPIO8

WAKE*

CL_CLK1

BATLOW*

PWROK

SLOAD/GPIO38

SATA2GP/GPIO36

SERIRQ

RI*

CL_DATA1

SLP_S4*

EC_ME_ALERT/GPIO14

TACH0/GPIO17

CLK14

SCLOCK/GPIO22

SATA3GP/GPIO37

SATACLKREQ*/GPIO35

STP_CPU*/GPIO25

WOL_EN/GPIO9

LINKALERT*

SLP_S3*

RSMRST*

TACH3/GPIO7

CLKRUN*/GPIO32

GPIO18

LAN_RST*

CL_VREF1

S4_STATE*/GPIO26

TACH1/GPIO1
TACH2/GPIO6

SATA1GP/GPIO19

SDATAOUT0/GPIO39

SATA0GP/GPIO21

MCH_SYNC*

DPRSLPVR/GPIO16

VRMPWRGD

TP3

TP7

CL_RST*

ME_EC_ALERT/GPIO10

SLP_M*

MEM_LED/GPIO24

PWRBTN*

SUSCLK

CL_VREF0

CK_PWRGD

CLPWROK

CL_DATA0

CL_CLK0

CLK48

SMBCLK
SMBDATA

SMLINK1

MISC

SYS GPIO

SMB

CLOCKS

POWER MGT

CONTROLLER LINK

GPIO

SATA

GPIO

(4 OF 6)

IN
IN

OUT

OUT

OUT

OUT

IN

IN

IN

IN

BI
BI

OUT

IN

IN

IN

IN

IN

OUT

OUT

IN

BI

BI

OUT

BI

BI

BI

IN

IN

OUT
OUT

OUT

IN

OUT

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

See note below

PP1V05_S0M, PP0V9_S3M and PP0V9_S0M.

for XOR chain testing.

INT PU

NOTE: DPRSLPVR HAS INT 20K PD ENABLED
AT BOOT/RESET FOR STRAPPING FUNCTION

Test access required

INT PU

INT PD

INT PD

NOTE: ICH CLPWROK input must be PWRGD signal for

INT PU

until VccCL3_3, VccLAN3_3 and VccLAN1_05

PM_LAN_ENABLE must remain deasseted

have been up for at least 1ms.

PP3V3_S0M, PP3V3_S0MWOL, PP1V8_S3M, PP1V25_S0M,

If ME/AMT is not used, short CLPWROK to PWROK.

30 29

7

30 29

7

47 45

7

35 34

47 45

7

45

45 13

10K

402

MF-LF

1/16W

5%

R2515

1

2

ARB_ONLY

MF-LF

1/16W

5%

0

402

R2516

1

2

402

10K

5%
1/16W
MF-LF

R2511

1

2

402

NOSTUFF

0

5%
1/16W
MF-LF

R2512

1

2

1/16W

402

MF-LF

10K

5%

R2502

1

2

1/16W
MF-LF

5%

10K

402

R2504

1

2

402

MF-LF

1/16W

5%

1K

R2500

1

2

MF-LF

1/16W

5%

8.2K

402

R2507

1

2

MF-LF

1/16W

10K

5%

402

R2506

1

2

MF-LF

5%

8.2K

1/16W

402

R2505

1

2

ICH8M

BGA

OMIT

U2300

AE21

AG12

E1

F23
AE18

F22
AF19

AJ23

D24
AH23

AG9
G5

AH11

E3

AJ14

AF22

AC19

AH12
AE11

AE16

AH20

AG21

AJ13 AJ24

AJ27

C2

AE23

AH25
AD16

AF17

AG27

AH27

AJ12
AJ10
AF11
AG11

AG13

AG10

AJ11
AD10

AF12

AF9

AJ25

AG23
AF21
AD18

AG22

AJ26
AD19

AC17
AE19

AD9

AG18

AE20

F4 D3

AD15

AG8

AJ8
AJ9
AH9

AC13

AJ21

AJ22

AJ20

AE17

AG19

88 30

88 30

46

66 45 40 36

7

MF-LF

NO_REBOOT_MODE

1K

5%
1/16W

402

R2510

1

2

46 45

7

83 59 16

7

28

9 7

45 25

45

7

45

86 48

86 48

47 46 45

7

45 28

7

16

7

28

7

38 25

16

7

66 45

7

29

9

87 16

87 16

MF-LF

1/16W

1%

3.24K

402

R2526

1

2

MF-LF

1/16W

1%

453

402

R2527

1

2

X5R

0.1uF

10%
16V

402

C2500

1

2

4.53K

MF-LF

1%
1/16W

402

R2529

1

2

32.4K

402

MF-LF

1/16W

1%

R2528

1

2

0.1uF

X5R

10%
16V

402

C2501

1

2

87 16

25

5%

MF-LF

402

1/16W

100K

R2523

1

2

86 48

86 48

25

402

1%

MF-LF

10K

1/16W

R2536

1 2

402

8.2K

1/16W
MF-LF

5%

R2544

1 2

402

1%

1/16W

10K

MF-LF

R2545

1 2

402

5%
1/16W
MF-LF

10K

R2525

1

2

47 25

7

25

28 25

29

402

10K

5%
1/16W
MF-LF

R2534

2

1

5%

10K

1/16W
MF-LF

402

R2552

1

2

402

1/16W

5%

MF-LF

10K

R2550

1

2

8.2K

5%
1/16W
MF-LF
402

R2553

1

2

402

MF-LF

5%

8.2K

1/16W

R2551

1

2

45

7

402

10K

1/16W
MF-LF

1%

R2598

1 2

402

10K

1/16W
MF-LF

1%

R2546

1 2

1/16W

5%

402

MF-LF

10K

R2532

2

1

10K

MF-LF

5%

1/16W

402

R2533

2

1

5%

402

10K

MF-LF

1/16W

R2535

2

1

79

402

10K

MF-LF

1/16W

5%

R2547

2

1

MF-LF

1/16W

5%

402

100K

R2524

1

2

402

1%

MF-LF

1/16W

10K

R2530

1 2

402

1%

MF-LF

1/16W

10K

R2531

1 2

402

100K

5%
1/16W
MF-LF

R2514

2

1

402

1%

1/16W

10K

MF-LF

R2596

1 2

402

1%

MF-LF

1/16W

10K

R2597

1 2

SB Pwr Mgt, GPIO, Clink

SYNC_DATE=04/02/2007

SYNC_MASTER=M75_MLB

051-7261

109

25

16

EXTGPU_RST_L

=PP3V3_S0_SB_GPIO

SB_GPIO6

ARB_DETECT_L
FWH_MFG_MODE

LINDACARD_GPIO

=PP3V3_S5_SB

SB_CLINK_VREF0

SB_GPIO36

=PP3V3_S0_SB_GPIO

SB_CRT_TVOUT_MUX_L

RSVD_EXTGPU_LVDS_EN

PM_STPPCI_L

=SB_CLINK_MPWROK

PM_RI_L

CLINK_NB_RESET_L

=PP3V3_S5_SB_CLINK1

SB_CLK48M_USBCTLR
SUS_CLK_SB

TP_CLINK_WLAN_RESET_L

PM_PWRBTN_L

SMB_ME_CLK

SMB_CLK

PM_DPRSLPVR

PM_RI_L

PM_BATLOW_L

SB_GPIO10_CL1

LAN_PHYPC

SB_GPIO14_CL2

=PP3V3_S0MWOL_SB_CLINK0

SMB_DATA

SMB_ME_DATA

PM_SYSRST_L

TP_PM_SLP_S4_L
PM_SLP_S5_L

PM_SB_PWROK

PM_S4_STATE_L

PM_BATLOW_L

TP_CLINK_WLAN_CLK

CLINK_NB_DATA

PM_BMBUSY_L
LINDACARD_GPIO

NB_SB_SYNC_L

PM_SUS_STAT_L

VR_PWRGD_CLKEN

SB_CLK14P3M_TIMER

PM_SLP_S3_L

WOL_EN

SB_GPIO10_CL1

TP_CLINK_WLAN_DATA

SATA_B_DET_L

PM_THRM_L

INT_SERIRQ

PCIE_WAKE_L

PM_CLKRUN_L

PCI_PME_FW_L

TP_SB_TP7

SB_GPIO6

SMC_RUNTIME_SCI_L

LAN_PHYPC
EXTGPU_RST_L

TP_SB_GPIO20

SATA_B_PWR_EN_L
FWH_MFG_MODE
SB_SATA_CLKREQ_L
SB_SLOAD

SB_SDATAOUT<1>

TP_SB_TP3

SMC_WAKE_SCI_L

SB_SPKR

SATA_B_PWR_EN_L

=PP3V3_S5_SB

PCI_PME_FW_L

CLK_PWRGD

PM_RSMRST_L

PM_LAN_ENABLE

PM_STPCPU_L

SB_GPIO18

SB_SCLOCK

SB_SDATAOUT<0>

=PP3V3_S5_SB_GPIO

SB_CLINK_VREF1

SB_GPIO14_CL2

CLINK_NB_CLK

TP_PM_SLP_M_L

ARB_DETECT_L

25

47

27

25

27

28

23

25

25

23

45

25

38

25

8

25

25

25

7

8

87

8

8

25

25

25

25

25

8

36

25

25

25

25

25

8

25

8

87

25

Preliminary

VSS

VSS_NCTF

VSS

(5 OF 6)

VCC1_5_B

V5REF_SUS

VCCDMIPLL

VCC_DMI

VCC3_3

VCC1_05

V5REF

VCCCL1_5

VCCGLANPLL

VCC3_3

VCC1_5_A

VCC3_3

VCCHDA

VCCSUS1_5

VCCSUS3_3

V_CPU_IO

VCC3_3

VCCSUSHDA

VCC1_5_A

VCC3_3

VCCSATAPLL

VCCGLAN3_3

VCCSUS3_3

VCCLAN3_3

VCCCL1_05

VCCSUS1_05

VCCSUS1_5

VCCSUS3_3

VCCA3GP

VCCGLAN1_5

VCCCL3_3

VCCLAN1_05

VCC1_5_A24

VCC1_5_A

VCCRTC

VCC1_5_A

VCCUSBPLL

VCC1_5_A

VCC1_5_A

VCC1_5_A

GLAN POWER

USB CORE

ATX ARX

(6 OF 6)

VCCPSUS

IDE

COREVCCP CORE

PCI

VCCPUSB

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

19 mA S0,
51 mA M1 & WOL

1 mA

80 mA

23 mA

10 mA

19 mA S0,
63 mA M1 & WOL

(VCC1_5_A total)

47 mA

1080 mA

32 mA

(VCCSUS3_3 total)

1 mA S3-S5

44 mA S3-S5

11 mA S0,

117 mA S0,

442 mA

(VCC3_3 total)

1 mA

50 mA

23 mA

1130 mA

NOTE:
VccHDA and VccSusHDA can be 1.5V or 3.3V
depending on VIO of HD Audio interface.

Current figures provided assume 1.5V.

Current numbers from ICH8M Max Power Estimates Rev 2.0, doc #610194.

657 mA

1 mA S0-S5

1 mA

6 uA S0-G3

402

10%

CERM

6.3V

1uF

C2600

1

2

0.1uF

20%
10V
CERM
402

C2601

1

2

OMIT

BGA

ICH8M

U2300

A23

A5

AC26

L13

L15

L26

L27

L4

L5

M12

M13

M14

M15

AC27

M16

M17

M23

M28

M29

M3

N1

N11

N12

N13

AD17

N14

N15

N16

N17

N18

N26

N27

N4

N5

N6

AD20

P12

P13

P14

P15

P16

P17

P23

P28

P29

R11

AD28

R12

R13

R14

R15

R16

R17

R18

R28

R4

T12

AD29

T13

T14

T15

T16

T17

T2

U12

U13

U14

U15

AD3

U16

U17

U23

U26

U27

U3

U5

V13

V15

V28

AD4

V29

W2

W26

W27

Y28

Y29

Y4

AB4

AB23

AB5

AD6

AB6

AD5

U4

W24

AE1

AA2

AE12

AE2

AE22

AD1

AE25

AE5
AE6

AE9
AF14
AF16

AA7

AF18

AF3

AF4

AG5

AG6
AH10
AH13
AH16
AH19

AH2

A25

AF28
AH22
AH24
AH26

AH3

AH4

AH8

AJ5

B11

B14

AB1

B17

B2
B20
B22

B8
C24
C26
C27

C6
D12

AB24

D15
D18

D2

D4
E21
E24

E4

E9
F15
E23

AC11

F28
F29

F7

G1

E2
G10
G13
G19
G23
G25

AC14

G26
G27
H25
H28
H29

H3

H6

J1
J25
J26

AC25

J27

J4

J5
K23
K28
K29

K3

K6

K7
L1

A1
A2

B1
B29

A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29

OMIT

ICH8M

BGA

U2300

A16

T7

G4

AC23
AC24

A13
B13

L14
L16
L17
L18
M11
M18
P11
P18
T11
T18

C13

U18
V17
V14
V11
U11
V18
V16
V12

C14
D14
E14
F14
G14
L11
L12

AE7
AF7

AC10

AC9

AA5
AA6

G12
G17

H7

AC7
AD7

F1

AG7

L6
L7
M6
M7

W23

AH7
AJ7

AC1
AC2
AC3
AC4
AC5

AA25
AA26

E27
F24
F25
G24
H23
H24
J23
J24
K24
K25

AA27

L23
L24
L25
M24
M25
N23
N24
N25
P24
P25

AB27

R24
R25
R26
R27
T23
T24
T27
T28
T29
U24

AB28

W25
V24
U25
Y25
V25
V23

AB29

D28
D29
E25
E26

AF29

AD2

W6
W7
Y7

A8
B15
B18
B4
B9
C15
D13

AC8

D5
E10
E7
F11

AD8
AE8
AF8

AA3
U7
V7
W1

AE28
AE29

G22

A22

F20
G21

R29

B27
A27
B28
B26
A26

B25

A24

AC12

F17
G18

F19
G20

AD25

AJ6

J6
AF20

AC16

J7

C3

AC18

P1
P2
P3
P4
P5
R1
R3
R5
R6

AC21
AC22
AG20
AH28

P6
P7
C1
N7

AD11

D1

SB Power & Ground

SYNC_DATE=01/25/2007

16

26

109

051-7261

SYNC_MASTER=T9_NOME

=PP1V05_S0_SB_CPU_IO

=PP3V3_S0_SB_VCC3_3_VCCPCORE

=PP3V3_S0_SB_VCC3_3_IDE

PP1V5_S0_SB_VCC1_5_B

PP5V_S0_SB_V5REF

VCCCL1_5V

=PPVCORE_S0_SB

=PP1V25_S0_SB_DMI

=PP1V5_S0_SB_VCC1_5_A_ARX

=PP1V5_S0_SB_VCC1_5_A_ATX

=PP3V3_S5_SB_VCCSUS3_3

=PP3V3_S5_SB_VCCSUS3_3_USB

=PP3V3_S0MWOL_SB_VCCLAN3_3

=PP1V5_S0_SB_VCC1_5_A

=PP1V5_S0_SB_VCC1_5_A_USB_CORE

=PP3V3_S0MWOL_SB_VCCCL3_3

=PP1V5_S0_SB_VCCGLAN1_5

PP5V_S5_SB_V5REF_SUS

PP1V5_S0_SB_VCCDMIPLL

PP1V5_S0_SB_VCCGLANPLL

=PP3V3R1V5_S0_SB_VCCHDA

TP_VCCSUS1_5_INTERNAL_REG1

=PP3V3_S0_SB_VCC3_3_SATA

=PP3V3_S5_SB_3V3_VCCSUSHDA

=PP3V3_S0_SB_VCC3_3_DMI

PP1V5_S0_SB_VCCSATAPLL

=PP3V3_S0_SB_VCCGLAN3_3

TP_VCCCL1_05_INTERNAL_REG

TP_VCCSUS1_05_INTERNAL_REG1

TP_VCCSUS1_5_INTERNAL_REG2

TP_VCCSUS1_05_INTERNAL_REG2

TP_VCCLAN1_05_INTERNAL_REG2

TP_VCCLAN1_05_INTERNAL_REG1

PP3V3_G3_SB_RTC

=PP1V5_S0_SB_VCCUSBPLL

=PP3V3_S0_SB_VCC3_3_PCI

27

27

28

23

27

24

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

8

8

8

23

27

8

8

8

8

8

8

8

8

8

8

27

27

27

27

8

8

8

8

27

8

23

8

8

Preliminary

NCNC

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

PLACE < 2.54MM OF SB ON SECONDARY
OR 3.56MM ON PRIMARY NEAR PIN AE29

ICH CORE/VCC1_05 BYPASS
(ICH CORE 1.05V PWR)

(ICH USB PLL 1.5V PWR)

ICH VCCUSBPLL BYPASS

ICH V5REF_SUS Filter & Follower
(ICH Reference for 5V Tolerance on Resume Well Inputs)

1 mA S0-S5

PLACE C2704 < 2.54MM OF PIN G4 OF SB
ON SECONDARY SIDE OR 3.56MM ON PRIMARY

ICH V5REF Filter & Follower
(ICH Reference for 5V Tolerance on Core Well Inputs)

PLACE C2700 & C2705-07 < 2.54MM OF SB

1 mA

1 mA S0-S5

PLACEMENT NOTE:

ICH VCCSATAPLL Filter

PLACEMENT NOTE:

ICH VCC1_5_A/ARX BYPASS
(ICH LOGIC&IO[ARX] 1.5V PWR)

(ICH LOGIC&IO[ATX] 1.5V PWR)

ICH VCC1_5_A/ATX BYPASS

PLACE < 2.54MM OF SB ON SECONDARY OR

3.56MM ON PRIMARY NEAR PINS AE7..AJ7

PLACEMENT NOTE:

PLACEMENT NOTE:

PLACE < 2.54MM OF SB ON SECONDARY OR

PLACEMENT NOTE:

(ICH USB CORE 1.5V PWR)

PLACE < 2.54MM OF SB ON SECONDARY OR

ICH USB CORE/VCC1_5_A BYPASS

3.56MM ON PRIMARY NEAR PINS F1..M7

PLACE C2715 NEAR PIN D1 OF SB

PLACEMENT NOTE:

PLACE NEAR PINS AC23,AC24 OF SB

PLACEMENT NOTE:

PLACEMENT NOTE:

3.56MM ON PRIMARY NEAR PIN AC1..AC5

10 mA

1130 mA

1 mA

50 mA

(ICH CPU I/O 1.05V PWR)

ICH V_CPU_IO BYPASS

PLACE CAPS AT EDGE OF SB

PLACEMENT NOTE:

PLACEMENT NOTE:

F19 AND G20

PLACE CAP UNDER SB NEAR PINS

ICH VCC_PAUX/VCCLAN3_3 BYPASS
(ICH LAN I/F BUFFER 3.3V PWR)

ICH IDE/VCC3_3 BYPASS
(ICH IDE I/O 3.3V PWR)

(ICH PCI I/O 3.3V PWR)

ICH PCI/VCC3_3 BYPASS

(ICH INTEL HDA CORE 3.3V/1.5V PWR)

ICH VCCHDA BYPASS

PLACEMENT NOTE:

PLACEMENT NOTE:

PLACE CAP < 2.54MM OF SB ON SECONDARY
OR 3.56MM ON PRIMARY NEAR PIN AF29

DISTRIBUTE IN PCI SECTION OF SB
NEAR PINS A8 ... F11

PLACEMENT NOTE:

OR 3.56MM ON PRIMARY NEAR PIN AC12

PLACE < 2.54MM OF SB ON SECONDARY

OR 3.56MM ON PRIMARY NEAR PIN AD11

PLACE < 2.54MM OF SB ON SECONDARY

PLACEMENT NOTE:

PLACEMENT NOTE:

OR 3.56MM ON PRIMARY NEAR PIN AD2

PLACE < 2.54MM OF SB ON SECONDARY

PLACEMENT NOTE:

PLACE < 2.54MM OF SB ON SECONDARY OR

3.56MM ON PRIMARY NEAR PINS AA3...Y7

(VCC3_3 Total)

1 mA

PLACEMENT NOTE:

PLACEMENT NOTE:

SECONDARY SIDE OR 3.56MM ON PRIMARY

PLACE CAPS < 2.54MM OF SB ON

PLACEMENT NOTE:

23 mA

47 mA

ICH VCCDMIPLL Filter
(ICH DMI PLL PWR)

23 mA

(ICH SATA PLL PWR)

33 mA

47 mA

ICH VCC1_5_B BYPASS

80 mA

657 mA

(VCC1_5_A Total)

1080 mA

(ICH RTC 3.3V PWR)

ICH VCCRTC BYPASS

(ICH SUSPEND USB 3.3V PWR)

PLACEMENT NOTE:
PLACE CAP NEAR PINS

(ICH SUSPEND 3.3V PWR)

PLACE CAPS NEAR PIN AD25 OF SB

PLACEMENT NOTE:

P6..R6

PLACEMENT NOTE:

(VCCSUS3_3 Total)

442 mA

ICH VCCSUS3_3 BYPASS

(ICH IO,LOGIC 1.5V PWR)

Current numbers from ICH8M Max Power Estimates Rev 2.0, doc #610194.

0.6 uA G3

ICH USB/VCCSUS3_3 BYPASS

(@ 1.5V)

(@ 1.5V)

32 mA

11 mA S0 /
1 mA S3-S5

ICH VCCSUSHDA BYPASS
(ICH INTEL HDA SUSPEND 3.3V/1.5V PWR)

114 mA M1 & WOL

38 mA S0 /

OR 3.56MM ON PRIMARY NEAR PIN AJ6

PLACE CAPS < 2.54MM OF SB ON SECONDARY

DISTRIBUTED BETWEEN AA25..V23

PLACE C2736 NEAR PIN B27..A26

PLACE C2732 NEAR PIN A24

PLACEMENT NOTE:

(ICH GLAN PLL PWR)

ICH VCCGLANPLL Filter

117 mA S0 /

44 mA S3-S5

PLACE CAPS NEAR PINS AC18..AH28

ON SECONDARY SIDE OR 3.56MM ON PRIMARY

ON SECONDARY SIDE OR 3.56MM ON PRIMARY

PLACEMENT NOTE:
PLACE C2703 < 2.54MM OF PIN A16..T7 OF SB

837 mA

CRITICAL

220UF

2.5V
POLY

20%

CASE-B2

C2700

1

2

X5R
402

16V

10%

0.1UF

C2712

1

2

1

1/10W
MF-LF

5%

603

R2700

1 2

4.7UF

6.3V

20%

CERM

603

C2724

1

2

0.1UF

10%
16V

402

X5R

C2722

1

2

SOT-363

BAT54DW

D2702

1

6

5

BAT54DW

SOT-363

D2702

4

3

2

1210

1.0UH-0.5A

L2703

1 2

X5R

6.3V

20%

10UF

603

C2735

1

2

X5R
402

16V

10%

0.1UF

C2703

1

2

1UF

10%
402

CERM

6.3V

C2711

1

2

2.2uF

603

CERM1

20%

6.3V

C2732

1

2

6.3V

20%
CERM

603

4.7uF

C2736

1

2

4.7uF

CERM
603

20%

6.3V

C2733

1

2

X5R
402

16V

10%

0.1UF

C2741

1

2

0.1UF

10%
16V

402

X5R

C2738

1

2

10UH-100MA

0805

L2702

1 2

0.1UF

10%
16V

402

X5R

C2737

1

2

805-3

CERM-X5R

20%

22UF

6.3V

C2739

1

2

X5R
402

16V

10%

0.1UF

C2702

1

2

402

5%

MF-LF

1/16W

0

R2735

1 2

MF-LF

402

100

1/16W

5%

R2702

2

1

10

MF-LF

1/16W

5%

402

R2701

2

1

0.1UF

10%
16V

402

X5R

C2704

1

2

SM

FERR-330-OHM

L2700

1 2

805-3

6.3V
CERM-X5R

22UF

20%

C2705

1

2

805-3

22UF

20%

6.3V
CERM-X5R

C2706

1

2

2.2UF

CERM1

6.3V

20%

603

C2707

402

CERM

16V

0.01UF

10%

C2701

1

2

603

10UF

20%

6.3V
X5R

C2708

1

2

6.3V
CERM
402

1UF

10%

C2717

6.3V
CERM
402

10%

1UF

C2714

1

2

X5R
402

16V

10%

0.1UF

C2715

1

2

X5R
402

16V

10%

0.1UF

C2718

1

2

0.1UF

10%
16V

402

X5R

C2719

1

2

X5R
402

16V

10%

0.1UF

C2721

1

2

0.1UF

10%
16V

402

X5R

C2723

1

2

X5R
402

16V

10%

0.1UF

C2725

1

2

X5R
402

16V

10%

0.1UF

C2726

1

2

0.1UF

10%
X5R

402

16V

C2727

1

2

0.1UF

X5R
402

16V

10%

C2728

1

2

0.1UF

10%
16V

402

X5R

C2729

1

2

0.1UF

10%
16V

402

X5R

C2730

1

2

0.1UF

10%
16V

402

X5R

C2734

1

2

X5R
402

16V

10%

0.1UF

C2731

1

2

SYNC_DATE=01/25/2007

SYNC_MASTER=T9_NOME

SB Decoupling

27

109

16

051-7261

=PP1V5_S0_SB

=PP1V25_S0_SB_DMI

PP1V5_S0_SB_VCCGLANPLL

=PP3V3_S5_SB_VCCSUS3_3

PP3V3_G3_SB_RTC

=PP3V3_S5_SB_VCCSUS3_3_USB

PP1V5_S0_SB_VCCSATAPLL

VOLTAGE=1.5V

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM

PP1V5_S0_SB_VCCDMIPLL

VOLTAGE=1.5V

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM

PP1V5_S0_SB_VCCSATAPLL_F

MIN_LINE_WIDTH=0.5MM
VOLTAGE=1.5V

MIN_NECK_WIDTH=0.25MM

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM
VOLTAGE=1.5V

PP1V5_S0_SB_VCCDMIPLL_F

=PP3V3_S0_SB
=PP5V_S0_SB

MIN_LINE_WIDTH=0.3MM

PP5V_S5_SB_V5REF_SUS

MIN_NECK_WIDTH=0.25MM
VOLTAGE=5V

=PP3V3_S5_SB

=PP3V3_S0_SB_VCC3_3_PCI

=PP3V3_S5_SB_3V3_VCCSUSHDA

=PP3V3R1V5_S0_SB_VCCHDA

=PP3V3_S0_SB_VCC3_3_DMI

=PP3V3_S0_SB_VCC3_3_SATA

=PP3V3_S0_SB_VCC3_3_IDE

=PP3V3_S0MWOL_SB_VCCCL3_3

=PP3V3_S0MWOL_SB_VCCLAN3_3

=PP1V05_S0_SB_CPU_IO

=PPVCORE_S0_SB

=PP1V5_S0_SB_VCCUSBPLL

=PP1V5_S0_SB_VCC1_5_A_USB_CORE

=PP1V5_S0_SB_VCC1_5_A_ARX

=PP1V5_S0_SB_VCC1_5_A_ATX

=PP5V_S5_SB

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.3MM

PP5V_S0_SB_V5REF

VOLTAGE=5V

=PP1V5_S0_SB_VCCGLAN1_5

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

VOLTAGE=1.5V

PP1V5_S0_SB_VCC1_5_B

28

26

26

26

26

26

26

25

26

26

26

26

26

26

26

26

23

26

26

26

26

26

24

8

8

26

8

23

8

26

26

8

8

26

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

26

26

23

Preliminary

OUT

IN

OUT

IN

NCNC

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT
OUT

OUT

OUT

IN

IN

OUT

OUT

IN

A

B

Y

132

A

B

Y

132

IN

IN

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

into isolated signals due to sharp
reset edge and isolating FET Cgs.

that would otherwise be injected

of the system. RC prevents glitch

certain GPU signals from the rest

Coin-Cell Connector

518S0487

CPU VCore ForcePSI

SB RTC Crystal

NC

This part is never stuffed,
it provides a set of pads
on the board to short or

RTC Power Sources

w/ 1K pullup on PM_ALL_GPU_PGOOD)

GPU_IOENABLE_RC is used to isolate

NC

Unbuffered

NC

to solder a reset button.

Platform Reset Connections

NC

Muxed GFX GPU Reset Support

VRMPWRGD Inverter

System Reset "Button"

reset while chip is still powered
and clocks are still running.

This ensures that GPU is put into

ON POWER DOWN:

PCI Reset Connections

PWROK Circuit

fault protection for RTC battery.

NOTE: R2800 and D2805 form the double-

(RC should reach schmitt trigger

run before GPU is released from reset

This delay ensures that GPU clocks

ON POWER UP:

threshold at approx .8 ms nominal

402

20K

MF-LF

5%

1/16W

R2806

1 2

23

402

0.1UF

10V

20%
CERM

C2830

1

2

402

10%

1UF

CERM

6.3V

C2806

1

2

13 10

5%

402

1M

1/16W
MF-LF

R2805

1

2

45 25

7

1/16W
402

5%
MF-LF

10K

R2825

1

2

1K

MF-LF

1/16W

402

5%

R2800

2 1

12pF

402

50V

5%

CERM

C2810

1 2

CERM

402

12pF

50V

5%

C2811

1 2

CRITICAL

SM-2

32.768K

Y2810

2 4

1 3

402

1/16W

5%

MF-LF

0

R2810

1 2

402

5%

10M

MF-LF

1/16W

R2811

1

2

79 24

9 7

402

ITP&XDP

MF-LF

5%

1/16W

1K

R2826

1 2

BAT54DW

SOT-363

D2805

1

4

6

3

5

2

5%

100

MF-LF

1/16W

402

R2862

1 2

402

MF-LF

0

5%

1/16W

R2863

1 2

100

1/16W

5%

402

MF-LF

R2864

1 2

402

1/16W

5%

MF-LF

100

R2860

1 2

402

0.1UF

CERM

20%
10V

C2840

1

2

59 16

9 7

66 46 45

25

9 7

402

0.1UF

CERM

20%
10V

C2880

1

2

0

5%

1/16W

402

MF-LF

R2881

1 2

16

7

47

7

45

7

34

68

7

MC74VHC1G08

SC70

U2880

3

2

1

4

5

MC74VHC1G08

SC70

U2840

3

2

1

4

5

MC74VHC1G00

SC70-5

U2830

3

2

1

4

5

SILK_PART=SYS RST

603

1/10W

0

5%

OMIT

MF-LF

R2820

1

2

38

MF-LF

1/16W

5%

0

402

R2861

1 2

38

100

MF-LF

5%

1/16W

402

R2890

1 2

24

7

79

78

59 10

59

25

7

10K

MF-LF

5%
1/16W

402

R2840

1

2

MF-LF

1/16W

402

5%

10K

R2841

1

2

M-RT-SM

BM02B-ACHKS-GAN-TF-LF-SN-M

CRITICAL

J2800

3

4

1
2

5%

MF-LF

1K

402

1/16W

R2882

1 2

50V

10%
CERM

402

0.001UF

C2882

1

2

1/16W

0

MF-LF

402

5%

R2865

1 2

35

79 30

20%
10V

CERM

402

0.1UF

C2883

12

402

MF-LF

10K

1/16W

5%

R2885

1 2

402

CERM

10%

0.047UF

16V

C2885

1

2

24.3K

1%

402

MF-LF

1/16W

R2886

1

2

US8

74LVC2G132

CRITICAL

U2883

5

6

4

8

3

74LVC2G132

US8

CRITICAL

U2883

1

2

4

8

7

25

66 23

0

1/16W

402

MF-LF

5%

EXTGPU_RST_HW

R2887

1 2

0

402

5%

MF-LF

1/16W

EXTGPU_RST_SW

R2880

1 2

23

7

CERM

402

6.3V

1UF

10%

C2805

1

2

SB Misc

SYNC_MASTER=M75_MLB

109

16

051-7261

28

SYNC_DATE=03/19/2007

=PP3V3_S0_RSTBUF

EXTGPU_RST_QUAL_L

PCI_RST_L

RST_L_AND_GPU_PGOOD

EXTGPU_PWR_EN

EXTGPU_RST_L

PM_SB_PWROK

ENET_RESET_L

LCDBKLT_PLT_RST_L

PLT_RST_L

MAKE_BASE=TRUE

DEBUG_RESET_L

=PP3V3_S5_SB_PM

PCI_FW_RST_L

=GPU_HPD_ENABLE

=GPU_DDC_ENABLE

GPU_RESET_L

=PP3V3_S0_SB_PM

SB_RTC_X2

VR_PWRGOOD_DELAY

=PP3V3_S0_SB_PM

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

PPVBATT_G3_RTC

=PP3V42_G3H_SB_RTC

MIN_NECK_WIDTH=0.2 mm

PPVBATT_G3_RTC_R

MIN_LINE_WIDTH=0.3 mm
VOLTAGE=3.3V

PM_SYSRST_L

XDP_DBRESET_L

SB_RTC_X1

LIO_PLT_RST_L

NB_RESET_L

FW_PLT_RST_L

PP3V3_G3_SB_RTC

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

SB_RTC_RST_L

SB_SM_INTRUDER_L

SMC_LRESET_L

PM_ALL_GPU_PGOOD

VR_PWRGD_CLKEN_L

GPU_PGOOD_RC

RST_L_AND_GPU_PGOOD_L

=PP3V3_S0_RSTBUF

ALL_SYS_PWRGD

VR_PWRGD_CLKEN

SB_RTC_X1_R

IMVP6_PSI_L

CPU_PSI_L

MAKE_BASE=TRUE

MAKE_BASE=TRUE

GPU_IOENABLE_RC

GPU_RESET_R_L

27

28

28 28

26

28

8

8

8

23

8

7

8

23

23

8

Preliminary

IN
IN

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT
OUT
OUT
OUT

IN

BI

OUT

IN

BI

OUT

OUT

IN

IN

IN

IN

OUT

OUT

IN

OUT

OUT

OUT
OUT

OUT
OUT

IN

OUT

VSS_PCI

CLKREQ_7*

CLKREQ_8*

GPU_STOP*

REF_0/FS_C/TEST_SEL

48M/FS_A

DOT_96/27M

DOT_96*/27M_SS

SRC_8*

SRC_8

PCI_5/FCT_SEL

PCIF_0/ITP_EN

VDD_PCI

VDD_48

THRM_PAD

SRC_4*

CLKREQ_3*

SRC_3

SRC_0/LCD_CLK

SRC_0*/LCD_CLK*

CPU_1_MCH*

CPU_1_MCH

CPU_ITP*/SRC_10*

CPU_ITP/SRC_10

VSS_SRC

VSS_REF

VSS_CPU

VSS_48

SDA

PCIF_1

PCI_4

PCI_3

PCI_2

PCI_1

VSS_A

XTAL_OUT

CLKREQ_6*

CLKREQ_5*

CLKREQ_4*

CLKREQ_1*

SCL

CPU_0

SRC_1

SRC_2*

SRC_2

SRC_4

SRC_5*

SRC_5

SRC_7*

SRC_7

SRC_6*

SRC_6

VDD_REF

CPU_0*

SRC_3*

CPU_STOP*

PCI_STOP*

XTAL_IN

VDD_A

FS_B/TEST_MODE

VDD_CPU

SRC_1*

CKPWRGD/PD*

VDD_SRC

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

FW PCI 33MHz

(INT PD*)

(INT PD*)

(INT PU*)

0
1

FCT_SEL

27M

DOT_96+

PIN 6

27M w/SS

DOT_96-

PIN 7

PIN 10

LCD_CLK+

SRC_0+ SRC_0-

PIN 11

LCD_CLK-

(For Internal Graphics)
(For External Graphics)

TP or GPU PGOOD

(INT PU*)

(INT PU*)

GMCH Display PLL A 96MHz (Int GFX)

NOTE: Pin 40 was PGMODE on SLG8LP537. Do not pull low

ICH PCI 33MHz

(INT PU*)

(INT PU*)

(INT PU*)

(INT PU*)

(INT PU*)

Spare 100MHz

From ICH

ICH SIO/LPC/REF 14.318MHz

ICH USB/Audio 48MHz

(Or 27MHz Spread & Non-Spread for Ext GFX)

PCIe Mini Card (AirPort) 100MHz

GMCH DMI/PCIe 100MHz

Spare 33MHz

Spare 33MHz

Spare 33MHz

Linda/LPC+ 33MHz

ExpressCard / Spare 100MHz

SMC LPC 33MHz

GMCH Display PLL B 100MHz (Int GFX)

From ICH

ICH DMI/PCIe 100MHz

ICH SATA 100MHz

GPU PCIe 100MHz (Ext GFX)

ITP/XDP Host Clock (FSB/4)

GMCH Host Clock (FSB/4)

One 0.1uF per power pin (place at pin).

CPU Host Clock (FSB/4)

CPU MHz

133.3

1

0

200.0

0

0
1

RSVD

(400.0)

100.0

(333.3)

166.6

1

0

1

0 0

00

0 1

0

0

1

1

1

1

1

0

1

1

One 10uF cap per rail.

FS_C FS_B FS_A

(266.6)

NEED TO CHECK CAP VALUE

on SLG8LP537 or device is set to CK410M mode.

Yukon PCIe 100MHz

(*) CLKREQ# internal pull-ups/downs only on SLG2AP101, not SLG8LP537.

NOTE: Pin 53 was REF_1 on SLG8LP537.

10UF

X5R
603

20%

6.3V

C2910

1

2

FERR-120-OHM-1.5A

0402

L2902

1 2

0.1UF

X5R
402

10%
16V

C2912

1

2

0.1UF

X5R
402

10%
16V

C2913

1

2

0.1UF

X5R
402

10%
16V

C2915

1

2

0.1UF

X5R
402

10%
16V

C2909

1

2

30 25

7

30 25

7

88 30

88 30

88 30

88 30

88 30

88 30

88 30

88 30

88 30

88 30

88 30

88 30

88 30

88 30

88 30

88 30

88 30

25

88 30

88 30

18pF

5%
50V
CERM
402

C2990

1

2

402

18pF

CERM

5%

50V

C2989

1

2

88 30

88 30

88 30

88 30

48

48

10UF

X5R
603

20%

6.3V

C2907

1

2

0.1UF

X5R
402

10%
16V

C2908

1

2

88 30

30

88 30

0.1UF

X5R
402

10%
16V

C2906

1

2

0.1UF

X5R
402

10%
16V

C2905

1

2

0.1UF

X5R
402

10%
16V

C2904

1

2

0.1UF

X5R
402

10%
16V

C2903

1

2

1UF

CERM
402

10%

6.3V

C2911

1

2

10UF

X5R
603

20%

6.3V

C2901

1

2

0.1UF

X5R
402

10%
16V

C2902

1

2

FERR-120-OHM-1.5A

0402

L2901

1 2

1UF

CERM

402

10%

6.3V

C2900

1

2

2.2

MF-LF

402

5%

1/16W

R2901

1 2

1

MF-LF

402

5%

1/16W

R2902

1 2

10UF

X5R
603

20%

6.3V

C2914

1

2

5%

1/16W

2.2

MF-LF

402

R2900

1 2

88 30

88 30

30

30

30

30

XDP

10K

MF-LF

402

5%

1/16W

R2903

1

2

88 30

88 30

25

88 30

88 30

88 30

88 30

88 30

88 30

16

7

CRITICAL

14.31818

5X3.2-SM

Y2901

1 2

10UF

X5R
603

20%

6.3V

C2916

1

2

FERR-120-OHM-1.5A

0402

L2903

1 2

30

QFN

SLG2AP101

OMIT

U2900

4

2

9

59

20

60

25

40

34

45

44

42

41

37

36

55

6

7

8

53

57
58
63
64
65

56

68

1

54

47
48

10

11

13

14

15

16

18

19

21

22

23

24

26

27

29

30

33

32

69

33843616749121728

35

5

39

46

62
66

52

31

51
50

30

Clock (CK505)

SYNC_MASTER=T9_NOME

SYNC_DATE=01/25/2007

16

109

29

051-7261

CK505_CLKREQ8_L

CK505_SRC6_N

=PP3V3_S0M_CK505

CK505_PCIF0_CLK_ITPEN

CK505_PCI5_CLK_FCTSEL

CK505_SRC7_P
CK505_CLKREQ7_L

CK505_XTAL_OUT

CK505_SRC5_N

PP3V3_S0M_CK505_VDDA_R

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.5mm
MIN_NECK_WIDTH=0.2mm

=PP3V3_S0M_CK505

=PP3V3_S0_CK505

TP_GPU_STOP_L

CK505_REF0_FSC

CK505_48M_FSA

CLK_PWRGD

CK505_DOT96_27M_P

CK505_DOT96_27M_N

CK505_SRC8_N
CK505_SRC8_P

PP3V3_S0M_CK505_VDD48

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.5mm
MIN_NECK_WIDTH=0.2mm

CK505_SRC4_N

CK505_CLKREQ3_L

CK505_SRC3_P

CK505_LVDS_P

CK505_LVDS_N

CK505_CPU1_N
CK505_CPU1_P

CK505_CPU2_ITP_SRC10_N
CK505_CPU2_ITP_SRC10_P

=SMBUS_CK505_SDA

CK505_PCIF1_CLK

CK505_PCI4_CLK

CK505_PCI3_CLK

CK505_PCI2_CLK

CK505_PCI1_CLK

NB_CLKREQ_L

SB_SATA_CLKREQ_L

CK505_CLKREQ1_L

CK505_CPU0_P

CK505_SRC1_P

CK505_SRC1_N

CK505_SRC2_N
CK505_SRC2_P

CK505_SRC4_P

CK505_SRC7_N

PP3V3_S0M_CK505_VDD_CPU_SRC

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.5mm
MIN_NECK_WIDTH=0.2mm

PP3V3_S0M_CK505_VDD_REF

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.5mm
MIN_NECK_WIDTH=0.2mm

PP3V3_S0M_CK505_VDD_PCI

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.5mm
MIN_NECK_WIDTH=0.2mm

CK505_CPU0_N

CK505_SRC3_N

PM_STPCPU_L

PM_STPPCI_L

CK505_FSB_TEST_MODE

CK505_XTAL_IN

MIN_LINE_WIDTH=0.5mm

PP3V3_S0M_CK505_VDDA

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2mm

=SMBUS_CK505_SCL

CK505_SRC5_P

CK505_SRC6_P
CK505_CLKREQ6_L

30

30

29

29

30

8

8

8

Preliminary

IN

IN

IN

IN

IN

IN

OUT

OUT

IN

IN

IN

IN

OUT

OUT

OUT

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

IN

IN

OUT

IN

OUT

OUT

BI

OUT

OUT

IN

IN

IN

IN

OUT

OUT

IN

OUT

IN

IN

IN

OUT

OUT

OUT

IN

IN

OUT

OUT

BI

OUT

OUT

OUT

IN

OUT

OUT

OUT

BI

OUT

OUT

OUT

IN

IN

IN

IN

OUT

OUT

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

G

D

S

IN

SEL

B0

GND

B1

0

1

A

VCC

SEL

B0

GND

B1

0

1

A

VCC

IN

IN

OUT

OUT

IN

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

FS_A, FS_B, FS_C (Host clock freq select)

(ICH8M DMI 100MHZ)

CK505 Configuration Straps

FCT_SEL (GFX clock select)

(TO MCH FS_A)

(ExpressCard 100MHz)

(ICH8M SATA 100MHZ)

0

(FROM CPU FS_B)

(FROM CPU FS_A)

(FROM CPU FS_C)

(TO ICH8M 14.318MHZ)

(TO/FROM CK505)

(TO MCH FS_B)

(TO CK505)

(TO MCH FS_C)

(TO/FROM CK505)

1 1

1

1

1

0

1

0 1

0

0

0 0

0
10

0

1

1

0

0
1

RSVD1

FS_C FS_B FS_A

(400.0)

(333.3)

(266.6)

133.3

100.0

166.6

200.0

CPU MHz

NO STUFF R3082, R3086 & R3090
for manual CPU clk frequency.

SLG8LP536 and CY28545-5)

(TO ICH8M USB 48MHZ)

(CPU HOST 167/200MHZ)

(GMCH HOST 167/200MHZ)

(GPU PCIe 100MHz)

(ENET 100MHZ)

(Ext GFX 27MHz)

(Ext GFX Spread 27MHz)

(ICH8M PCI 33MHZ)

(FIREWIRE PCI 33MHZ)

(SMC PCI 33MHZ)

(Int Gfx LVDS 100MHz)

(Note: HOST/SRC/GFX clock termination removed. Silego SL8GLP536 or equiv. support only)

CLKREQ Controls

(GMCH PEG/DMI 100MHZ)

(Reserved for TPM PCI 33MHZ)
(Spare 33MHZ)

CLK Termination

(WIRELESS PCIe MINI 100MHZ)

(Only 100-200MHz supported by

(LINDA/LPC+ LPC 33MHZ)

(FW 100MHz)

(ITP HOST 167/200MHZ)

Unused Clocks

CLKREQ# pins. Support for SL8GLP537 or equiv. only.

Silego SLG2AP101 has internal pull-ups on all

GPU Clock Gating

NB and SATA CLKREQs are not remappable (and thus
are not shown here).

88 29

88 29

88 29

88 29

88 29

88 29

88 16

7

88 16

7

88 29

88 29

88 29

88 29 88 35

88 35

88 24

88 29

88 29

88 29

88 29

88 29

88 38

88 45

88 24

88 34

88 34 88 29

88 29

88 47

7

88 29

88 24

5%
1/16W
MF-LF

10K

402

R3067

1

2

1K

MF-LF

402

5%

1/16W

R3083

1

2

1/16W

5%

402

MF-LF

1K

R3084

1

2

29

88 29

88 23

88 23

88 29

88 29

NO STUFF

1/16W

5%

402

1K

MF-LF

R3080

1

2

402

0

MF-LF

5%

1/16W

R3082

1 2

83 10

83 10

0

MF-LF

402

5%

1/16W

R3086

1 2

5%

1/16W

NO STUFF

402

1K

MF-LF

R3087

1

2

88 34

88 34

88 29

88 14

7

88 29

88 29

88 29

68

9

68

9

88 14

7

88 29

88 29

88 10

7

88 25

MF-LF

402

5%

1/16W

33

R3032

1 2

88 29

88 10

7

1K

402

5%
1/16W
MF-LF

R3081

1 2

83 16 13

MF-LF

402

1/16W

5%

1K

R3085

1 2

83 16 13

83 10

0

MF-LF

402

5%

1/16W

R3090

1 2

NO STUFF

1K

1/16W

5%

402

MF-LF

R3088

1

2

1K

MF-LF

402

5%

1/16W

R3091

1

2

88 83 13

MF-LF

402

5%
1/16W

1K

R3089

1 2

83 16 13

88 25

MF-LF

5%

1/16W

402

33

R3034

1 2

88 29

88 83 13

402

1/16W

5%

MF-LF

33

R3024

1 2

33

1/16W

5%

402

MF-LF

R3025

1 2

88 22

7

88 22

7

88 29

88 29

MF-LF

5%

1/16W

402

33

R3026

1 2

33

5%
1/16W
MF-LF

402

R3027

1 2

MF-LF

5%

1/16W

402

33

R3028

1 2

402

MF-LF

1/16W

5%

33

R3030

1 2

402

5%
1/16W
MF-LF

10K

R3035

2

1

1/16W

5%

2.2K

402

MF-LF

R3033

2

1

NO STUFF

10K

1/16W
MF-LF

5%

402

R3046

1 2

10K

1/16W
MF-LF

5%

402

NO STUFF

R3047

1 2

34

34

29 25

7

29 25

7

88 29

88 29

29

29

29

29

90 74

90 74

2N7002DW-X-F

SOT-363

SLG8LP537

Q3050

6

2

1

79 30 28

NC7SB3157P6X

SC70

SLG8LP537

U3050

43

1

2

6

5

GPU_SS_EXT

SC70

NC7SB3157P6X

U3055

43

1

2

6

5

GPU_SS_EXT

CERM

20%

0.1UF

10V
402

C3055

1 2

SLG8LP537

20%
10V

CERM

402

0.1UF

C3050

1 2

79

30 28

35

SLG2AP101

0

5%

402

MF-LF

1/16W

R3050

1

2

SLG2AP101

1/16W
MF-LF

402

5%

0

R3055

1

2

29

29

SLG2AP101

0

402

MF-LF

1/16W

5%

R3051

1

2

88 29

88 29

Clock Termination

SYNC_DATE=03/19/2007

16

109

30

051-7261

SYNC_MASTER=M75_MLB

TP_GPU_STOP_L

MAKE_BASE=TRUE

GPU_STOP_L

PM_ALL_GPU_PGOOD

=ENET_CLKREQ_L

ENET_CLKREQ_L

MAKE_BASE=TRUE

TP_CK505_CLKREQ7_L

MAKE_BASE=TRUE

CK505_CLKREQ7_L

EXCARD_CLKREQ_L

MAKE_BASE=TRUE

MINI_CLKREQ_L

MAKE_BASE=TRUE

CK505_CLKREQ6_L

CK505_CLKREQ3_L

CK505_CLKREQ8_L

GPU_CLK27M_SS

=PP3V3_S0_GPUCLKGATE

GPU_CLK27M

GPU_CLK27M_SS_GATED

GPU_CLK27M_GATED

PM_ALL_GPU_PGOOD

PEG_CLKREQ_L

MAKE_BASE=TRUE

CK505_SRC8_P
CK505_SRC8_N

CK505_DOT96_27M_P

CK505_DOT96_27M_N

PCI_CLK33M_LPCPLUS

CK505_LVDS_P
CK505_LVDS_N

NB_CLK100M_DPLLSS_N

MAKE_BASE=TRUE

NB_CLK100M_DPLLSS_P

MAKE_BASE=TRUE

CK505_SRC1_P

CK505_SRC3_P

CK505_CLKREQ1_L

MAKE_BASE=TRUE

PCIE_CLK100M_MINI_P
PCIE_CLK100M_MINI_N

MAKE_BASE=TRUE

NB_CLK100M_PCIE_N

MAKE_BASE=TRUE

FSB_CLK_CPU_P

MAKE_BASE=TRUE

=PP1V25R1V05_S0_FSB_NB

NB_CLK100M_PCIE_P

MAKE_BASE=TRUE

=PP3V3_S0M_CK505

PCIE_CLK100M_EXCARD_N

MAKE_BASE=TRUE

CK505_PCI4_CLK

CK505_PCI2_CLK

TP_CK505_PCI4_CLK

MAKE_BASE=TRUE

MAKE_BASE=TRUE

TP_CK505_PCI2_CLK

PM_STPCPU_L

PM_STPPCI_L

CK505_CLK27M_SS

MAKE_BASE=TRUE

TP_PCIE_CLK100M_SRC7P

MAKE_BASE=TRUE

CK505_SRC4_N

=PP1V25R1V05_S0_FSB_NB

CK505_CPU2_ITP_SRC10_N

MAKE_BASE=TRUE

PCIE_CLK100M_ENET_P

MAKE_BASE=TRUE

PCIE_CLK100M_ENET_N

MAKE_BASE=TRUE

TP_PCIE_CLK100M_SRC7N

CK505_SRC7_N

CK505_SRC7_P

CK505_SRC6_P
CK505_SRC6_N

MAKE_BASE=TRUE

SB_CLK100M_SATA_P
SB_CLK100M_SATA_N

MAKE_BASE=TRUE

CK505_SRC5_P
CK505_SRC5_N

CK505_SRC4_P

CK505_SRC3_N

SB_CLK100M_DMI_N

MAKE_BASE=TRUE

SB_CLK100M_DMI_P

MAKE_BASE=TRUE

CK505_SRC2_N

PEG_CLK100M_GPU_N

MAKE_BASE=TRUE

PEG_CLK100M_GPU_P

MAKE_BASE=TRUE

CK505_CPU2_ITP_SRC10_P

XDP_CLK_N

MAKE_BASE=TRUE

XDP_CLK_P

MAKE_BASE=TRUE

FSB_CLK_NB_N

MAKE_BASE=TRUE

FSB_CLK_NB_P

MAKE_BASE=TRUE

CK505_CPU1_P
CK505_CPU1_N

CK505_CPU0_P
CK505_CPU0_N

FSB_CLK_CPU_N

MAKE_BASE=TRUE

GPU_CLK27M_SS

PCI_CLK33M_SMC

PCI_CLK33M_SB

PCI_CLK33M_FW

CK505_PCI3_CLK

GPU_CLK27M

CK505_PCIF0_CLK_ITPEN

CK505_PCI1_CLK

NB_BSEL<2>

NB_BSEL<1>

CK505_48M_FSA

NB_BSEL<0>

SB_CLK14P3M_TIMER

CK505_REF0_FSC

CPU_BSEL<2>

CPU_BSEL<1>

CPU_BSEL<0>

SB_CLK48M_USBCTLR

CK505_FSC

CK505_FSB_TEST_MODE

=PP1V25R1V05_S0_FSB_NB

CK505_CLK27M

MAKE_BASE=TRUE

CK505_PCIF1_CLK

PCIE_CLK100M_EXCARD_P

MAKE_BASE=TRUE

CK505_SRC2_P

CK505_SRC1_N

=PP3V3_S0_CK505

CK505_PCI5_CLK_FCTSEL

CK505_FSA

30

30

30

90

90

14

29

14

90

90

14

29

30

8

30

8

8

8

30

30

88

8

8

88

Preliminary

VSS7

VSS12

VSS9

KEY

DQ57

DQ51

DQS6

DQ43

DQ42

DQ40

DQ34

DQ1

DQ0

VSS1

DQS0*
DQS0
VSS6
DQ2
DQ3

DQ8
DQ9
VSS10
DQS1*
DQS1

DQ10
DQ11
VSS14

VSS16
DQ16
DQ17
VSS18
DQS2*
DQS2
VSS21
DQ18
DQ19
VSS23
DQ24
DQ25
VSS25
DM3
NC1
VSS27
DQ26
DQ27
VSS29
CKE0
VDD0
NC2
BA2
VDD2
A12
A9
A8
VDD4
A5
A3
A1
VDD6
A10/AP
BA0
WE*
VDD8
CAS*
NC/S1*
VDD10
NC/ODT1
VSS31
DQ32
DQ33
VSS33
DQS4*
DQS4
VSS36

DQ35
VSS38

DQ41
VSS40
DM5
VSS41

VSS43
DQ48
DQ49
VSS45
NC_TEST
VSS47
DQS6*

VSS49
DQ50

VSS51
DQ56

VSS53
DM7
VSS55
DQ58
DQ59
VSS57
SDA
SCL
VDDSPD

DM6

DQ55

DQ61

DQ46
DQ47

DQ12

DM1

DM0

DQ7

DQ13

VSS11

CK0

CK0*

VSS13

DQ14
DQ15

VSS15

VSS17

DQ20
DQ21

VSS19

NC0
DM2

VSS22

DQ22
DQ23

VSS24

DQ28

DQ29
VSS26
DQS3*

DQS3
VSS28

DQ30

DQ31
VSS30

NC/CKE1

VDD1

NC/A15
NC/A14

VDD3

A11

A7
A6

VDD5

A4
A2
A0

VDD7

BA1

RAS*

S0*
VDD9
ODT0

NC/A13

VDD11

NC3

VSS32

DQ36
DQ37

VSS34

DM4

VSS35

DQ38
DQ39

VSS37

DQ44
DQ45

VSS39
DQS5*

DQS5

VSS42

VSS44

DQ52
DQ53

VSS46

CK1
CK1*

VSS48

VSS50

DQ54

VSS52

DQ60

VSS54
DQS7*

DQS7

VSS56

DQ62
DQ63

VSS58

SA0

SA1

DQ5
VSS2

VREF

VSS4

VSS8

VSS0

DQ4

VSS5

DQ6

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Page Notes

Power aliases required by this page:

- =PP0V9_S3M_MEM_DIMMVREFA

- =PP1V8_S3M_MEM_A

- =I2C_SODIMMA_SCL

(NONE)

BOM options provided by this page:

- =I2C_SODIMMA_SDA

- =PPSPD_S0M_MEM_A (2.5V - 3.3V)

NC

ADDR=0xA0(WR)/0xA1(RD)

(For return current)

NC

516-0140

NC

DDR2 Bypass Caps

"Factory" (thru-hole) slot

NC

Signal aliases required by this page:

10%

1UF

CERM

6.3V
402

C3113

1

2

10%

1UF

CERM

6.3V
402

C3112

1

2

6.3V

20%
603

X5R

10UF

C3109

1

2

10%

1UF

CERM

6.3V
402

C3111

1

2

6.3V

20%
603

X5R

10UF

C3108

1

2

10%

1UF

CERM

6.3V
402

C3110

1

2

1UF

CERM

6.3V

10%
402

C3119

1

2

1UF

CERM

6.3V

10%
402

C3118

1

2

10%

1UF

CERM

6.3V
402

C3117

1

2

10%

1UF

CERM

6.3V
402

C3116

1

2

1UF

CERM

6.3V

10%
402

C3121

1

2

1UF

CERM

6.3V

10%
402

C3120

1

2

10%

1UF

CERM

6.3V
402

C3115

1

2

10%

1UF

CERM

6.3V
402

C3114

1

2

10V

20%

402

CERM

0.1uF

C3100

1

2

6.3V

CERM1

603

20%

2.2uF

C3101

1

2

CRITICAL

DDR2-SODIMM-DUAL

F-RT-TH1

J3100

102B

105B

90B89B

101B

100B

99B

98B97B

94B

92B

93B

91B

107B

106B

85B

113B

30B
32B

164B
166B

79B

10B

26B

52B

67B

130B

147B

170B

185B

5B

35B
37B

20B
22B

36B
38B

43B
45B

55B
57B

7B

44B
46B

56B
58B

61B
63B

73B
75B

62B
64B

17B

74B
76B

123B
125B

135B
137B

124B
126B

134B
136B

19B

141B
143B

151B
153B

140B
142B

152B
154B

157B
159B

4B

173B
175B

158B
160B

174B
176B

179B
181B

189B
191B

6B

180B
182B

192B
194B

14B
16B

23B
25B

13B

11B

31B

29B

51B

49B

70B

68B

131B

129B

148B

146B

169B

167B

188B

186B

201

202

116B

86B

84B

80B

119B

115B

50B

69B

83B

120B

163B

114B

108B
110B

198B
200B

197B

195B

81B

117B 118B

82B

87B 88B

95B 96B

103B 104B

111B 112B

199B

1B 2B

27B 28B

33B 34B

39B 40B

41B 42B

47B 48B

3B

53B 54B

59B 60B

65B 66B

71B 72B

77B

8B

78B

121B 122B

127B 128B

132B

133B

138B

139B

144B

145B

149B 150B

155B 156B

161B 162B

165B

168B

171B

9B

172B

177B 178B

183B 184B

187B

190B

193B

196B

12B

15B

18B

21B

24B

109B

31

109

16

051-7261

DDR2 SO-DIMM Connector A

SYNC_MASTER=M75_MLB

SYNC_DATE=03/19/2007

MEM_A_DM<7>

MEM_A_DQS_N<6>

MEM_A_DQ<22>
MEM_A_DQ<19>

=PP1V8_S3M_MEM_A

MEM_A_A<14>

MEM_A_A<15>

MEM_CKE<1>

MEM_A_DM<3>

MEM_A_A<6>

=I2C_SODIMMA_SCL

MEM_A_DQS_N<4>

MEM_A_A<0>

MEM_A_BS<1>

MEM_A_DQ<14>

MEM_A_DM<1>

MEM_A_DQ<2>

MEM_A_DQ<13>

MEM_A_DQS_N<1>
MEM_A_DQS_P<1>

MEM_A_DQ<10>
MEM_A_DQ<11>

MEM_A_DQ<7>
MEM_A_DQ<0>

MEM_A_DQS_N<0>
MEM_A_DQS_P<0>

MEM_A_DQ<4>

MEM_A_DQ<17>
MEM_A_DQ<21>

MEM_A_DQS_N<2>
MEM_A_DQS_P<2>

MEM_A_DQ<23>
MEM_A_DQ<16>

MEM_A_DQ<31>
MEM_A_DQ<27>

MEM_A_DQ<30>
MEM_A_DQ<28>

MEM_CKE<0>

=PP1V8_S3M_MEM_A

MEM_A_BS<2>

MEM_A_A<12>
MEM_A_A<9>
MEM_A_A<8>

MEM_A_A<5>
MEM_A_A<3>
MEM_A_A<1>

MEM_A_A<10>
MEM_A_BS<0>
MEM_A_WE_L

MEM_A_CAS_L
MEM_CS_L<1>

MEM_ODT<1>

MEM_A_DQ<36>
MEM_A_DQ<38>

MEM_A_DQS_P<4>

MEM_A_DQ<37>
MEM_A_DQ<34>

MEM_A_DQ<56>
MEM_A_DQ<59>

MEM_A_DQ<54>

MEM_A_DQS_P<6>

MEM_A_DQ<48>
MEM_A_DQ<53>

MEM_A_DQ<43>
MEM_A_DQ<42>

MEM_A_DM<5>

MEM_A_DQ<46>
MEM_A_DQ<41>

=I2C_SODIMMA_SDA

=PPSPD_S0M_MEM_A

MEM_A_RAS_L
MEM_CS_L<0>

MEM_ODT<0>
MEM_A_A<13>

MEM_A_DQ<39>

MEM_A_DM<4>

MEM_A_DQ<33>
MEM_A_DQ<32>

MEM_A_DQ<63>
MEM_A_DQ<62>

MEM_A_DQS_N<7>
MEM_A_DQS_P<7>

MEM_A_DQ<57>
MEM_A_DQ<61>

MEM_A_DQ<55>
MEM_A_DQ<50>

MEM_CLK_P<1>
MEM_CLK_N<1>

MEM_A_DM<6>

MEM_A_DQ<49>
MEM_A_DQ<52>

MEM_A_DQ<45>
MEM_A_DQ<40>

MEM_A_DQS_N<5>
MEM_A_DQS_P<5>

MEM_A_DQ<44>
MEM_A_DQ<47>

MEM_A_DQ<35>

MEM_A_DQ<8>
MEM_A_DQ<12>

MEM_A_DQ<3>

MEM_A_DM<0>

MEM_CLK_P<0>
MEM_CLK_N<0>

MEM_A_DQ<1>
MEM_A_DQ<5>

MEM_A_DQ<18>
MEM_A_DQ<20>

PM_EXTTS_L<0>
MEM_A_DM<2>

MEM_A_DQ<26>
MEM_A_DQ<24>

MEM_A_DQS_N<3>
MEM_A_DQS_P<3>

MEM_A_DQ<25>
MEM_A_DQ<29>

MEM_A_A<11>
MEM_A_A<7>

MEM_A_A<4>
MEM_A_A<2>

MEM_A_DQ<9>
MEM_A_DQ<15>

MEM_A_DQ<6>

=PP0V9_S3M_MEM_DIMMVREFA

=PP1V8_S3M_MEM_A

MEM_A_DQ<51>

MEM_A_DQ<60>

MEM_A_DQ<58>

91

85

85

85

85

85

85

91

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

91

85

85

85

85

31

33

33

85

33

85

33

33

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

33

31

33

33

33

33

33

33

33

33

33

33

33

33

33

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

33

33

33

33

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

45

85

85

85

85

85

85

85

33

33

33

33

85

85

85

31

85

85

85

17

17

17

17

8

16

9

16

17

17

48

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

16

8

17

17

17

17

17

17

17

17

17

17

17

16

16

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

48

8

17

16

16

17

17

17

17

17

17

17

17

17

17

17

17

17

16

16

17

17

17

17

17

17

17

17

17

17

17

17

17

17

16

16

17

17

17

17

16

17

17

17

17

17

17

17

17

17

17

17

17

17

17

8

8

17

17

17

Preliminary

VSS2

DQS0*

DQ5

VSS0

DQ4

VSS5

DQ6

VSS29

DM0

VSS7

DM1

DQ7

VDD1

DQ30

DQ23

VSS22

NC/ODT1

RAS*

SA1

SA0

VSS58

DQ63

DQ62

VSS56

DQS7

DQS7*

VSS54

DQ60

VSS52

DQ54

VSS50

VSS48

CK1*

CK1

VSS46

DQ53

DQ52

VSS44

VSS42

DQS5

DQS5*

VSS39

DQ45

DQ44

VSS37

DQ39

DQ38

VSS35

DM4

VSS34

DQ37

DQ36

VSS32

NC3

VDD11

NC/A13

ODT0

VDD9

S0*

BA1

VDD7

A0

A2

A4

VDD5

A6

A7

A11

VDD3

NC/A14

NC/A15

NC/CKE1

VSS30

DQ31

DQS3

DQ29

DQ28

VSS24

DQ22

DM2

NC0

VSS19

DQ21

DQ20

VSS17

VSS15

DQ15

DQ14

VSS13

CK0*

CK0

VSS11

DQ13

DQ12

DQ47

DQ46

DQ61

DQ55

DM6

VDDSPD

SCL

SDA

VSS57

DQ59

DQ58

VSS55

DM7

VSS53

DQ56

VSS51

DQ50

VSS49

DQS6*

VSS47

NC_TEST

VSS45

DQ49

DQ48

VSS43

VSS41

DM5

VSS40

DQ41

VSS38

DQ35

VSS36

DQS4

DQS4*

VSS33

DQ33

DQ32

VSS31

VDD10

NC/S1*

CAS*

VDD8

WE*

BA0

A10/AP

VDD6

A1

A3

A5

VDD4

A8

A9

A12

VDD2

BA2

NC2

VDD0

CKE0

DQ27

DQ26

VSS27

NC1

DM3

DQ25

DQ24

VSS23

DQ19

DQ18

VSS21

DQS2

DQS2*

VSS18

DQ17

DQ16

VSS16

VSS14

DQ11

DQ10

VSS12

DQS1

DQS1*

DQ9

DQ8

VSS8

DQ3

DQ2

VSS6

DQS0

VREF

DQ34

DQ40

DQ42
DQ43

DQS6

DQ51

DQ57

KEY

VSS9

DQ1
VSS4

DQ0

VSS1

DQS3*

VSS26

VSS28

VSS25

VSS10

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

- =PP1V8_S3M_MEM_B

- =PPSPD_S0M_MEM_B (2.5V - 3.3V)

- =PP0V9_S3M_MEM_DIMMVREFB

- =I2C_SODIMMB_SDA

- =I2C_SODIMMB_SCL

(NONE)

BOM options provided by this page:

NC

NC

NC

NC

(For return current)

DDR2 Bypass Caps

516S0471

"Expansion" (surface-mount) slot

Signal aliases required by this page:

Power aliases required by this page:

Page Notes

ADDR=0xA4(WR)/0xA5(RD)

Resistor prevents pwr-gnd short

6.3V

10%

1UF

CERM
402

C3213

1

2

6.3V

10%

1UF

CERM
402

C3212

1

2

10UF

X5R
603

20%

6.3V

C3209

1

2

20%

402

CERM

0.1uF

10V

C3211

1

2

10UF

X5R

6.3V

20%
603

C3208

1

2

6.3V

10%

1UF

CERM
402

C3210

1

2

20%
402

CERM

0.1uF

10V

C3219

1

2

20%
402

CERM

0.1uF

10V

C3218

1

2

10V

20%
402

CERM

0.1uF

C3217

1

2

6.3V

10%

1UF

CERM
402

C3216

1

2

20%
402

CERM

0.1uF

10V

C3221

1

2

20%
402

CERM

10V

0.1uF

C3220

1

2

6.3V

10%

1UF

CERM
402

C3215

1

2

6.3V

10%

1UF

CERM
402

C3214

1

2

10K

5%
MF-LF

402

1/16W

R3200

1

2

10V

20%

402

CERM

0.1uF

C3200

1

2

6.3V

CERM1

603

20%

2.2uF

C3201

1

2

F-RT-SM-M9

CRITICAL

DDR2-SODIMM-DUAL

J3200

102A

105A

90A89A

101A

100A

99A

98A97A

94A

92A

93A

91A

107A

106A

85A

113A

30A
32A

164A
166A

79A

10A

26A

52A

67A

130A

147A

170A

185A

5A

35A
37A

20A
22A

36A
38A

43A
45A

55A
57A

7A

44A
46A

56A
58A

61A
63A

73A
75A

62A
64A

17A

74A
76A

123A
125A

135A
137A

124A
126A

134A
136A

19A

141A
143A

151A
153A

140A
142A

152A
154A

157A
159A

4A

173A
175A

158A
160A

174A
176A

179A
181A

189A
191A

6A

180A
182A

192A
194A

14A
16A

23A
25A

13A

11A

31A

29A

51A

49A

70A

68A

131A

129A

148A

146A

169A

167A

188A

186A

201

202

203

204

116A

86A

84A

80A

119A

115A

50A

69A

83A

120A

163A

114A

108A
110A

198A
200A

197A

195A

81A

117A 118A

82A

87A 88A

95A 96A

103A 104A

111A 112A

199A

1A 2A

27A 28A

33A 34A

39A 40A

41A 42A

47A 48A

3A

53A 54A

59A 60A

65A 66A

71A 72A

77A

8A

78A

121A 122A

127A 128A

132A

133A

138A

139A

144A

145A

149A 150A

155A 156A

161A 162A

165A

168A

171A

9A

172A

177A 178A

183A 184A

187A

190A

193A

196A

12A

15A

18A

21A

24A

109A

DDR2 SO-DIMM Connector B

SYNC_DATE=03/19/2007

SYNC_MASTER=M75_MLB

16

051-7261

32

109

MEM_B_CAS_L

MEM_B_DQ<33>

MEM_B_DQS_N<4>

MEM_B_DM<6>

MEM_B_DQ<49>

MEM_B_DQ<44>

MEM_B_A<10>

MEM_CS_L<3>

MEM_ODT<3>

MEM_B_DQ<34>

MEM_B_DQ<36>

MEM_CLK_P<3>
MEM_CLK_N<3>

MEM_B_DQ<52>

MEM_B_DQ<46>

SODIMM_B_SA1

=PPSPD_S0M_MEM_B

MEM_B_DQ<43>

=PPSPD_S0M_MEM_B

MEM_B_A<7>

MEM_B_A<4>

MEM_B_DQS_P<1>

MEM_B_DQ<12>

MEM_B_DQ<6>

MEM_B_DQS_N<1>

MEM_B_DQ<29>

MEM_B_DQ<31>

MEM_B_DQS_P<3>

MEM_B_DQ<58>

PM_EXTTS_L<1>

MEM_B_DQ<41>

MEM_B_DQS_P<5>

MEM_B_DQS_N<5>

MEM_B_DQ<53>

MEM_B_DQ<54>

MEM_B_DQ<63>

MEM_B_DQS_P<7>

MEM_B_DQS_N<7>

MEM_B_DQ<59>

MEM_B_DQ<56>

MEM_B_DQ<39>

MEM_B_DQ<38>

MEM_B_DM<4>

MEM_B_DQ<37>

MEM_B_DQ<32>

MEM_B_A<13>

=PP1V8_S3M_MEM_B

MEM_CS_L<2>

MEM_B_A<2>

MEM_B_A<6>

MEM_B_A<14>

MEM_B_A<15>

MEM_B_DQ<17>

MEM_B_DQ<5>

MEM_CLK_N<4>

MEM_CLK_P<4>

MEM_B_DM<0>

MEM_B_DM<1>

MEM_B_DQ<9>

=I2C_SODIMMB_SCL

=I2C_SODIMMB_SDA

MEM_B_DQ<45>

MEM_B_DQ<42>

MEM_B_DM<5>

MEM_B_DQ<47>

MEM_B_DQ<40>

MEM_B_DQ<55>

MEM_B_DQ<50>

MEM_B_DQS_P<6>

MEM_B_DQS_N<6>

MEM_B_DQ<51>

MEM_B_DQ<48>

MEM_B_DQ<62>

MEM_B_DQ<61>

MEM_B_DM<7>

MEM_B_DQ<60>

MEM_B_DQ<57>

MEM_B_DQ<35>

MEM_B_DQS_P<4>

MEM_B_DQ<4>

MEM_B_WE_L

MEM_B_BS<0>

MEM_B_A<1>

MEM_B_A<3>

MEM_B_A<5>

MEM_B_A<8>

MEM_B_A<9>

MEM_B_A<12>

MEM_B_BS<2>

MEM_CKE<3>

MEM_B_DQ<25>

MEM_B_DQ<27>

MEM_B_DM<3>

MEM_B_DQ<24>

MEM_B_DQ<20>

MEM_B_DQS_P<2>

MEM_B_DQS_N<2>

MEM_B_DQ<19>

MEM_B_DQ<21>

MEM_B_DQ<1>

MEM_B_DQS_P<0>

MEM_B_DQS_N<0>

MEM_B_DQ<2>

MEM_B_DQ<7>

MEM_B_DQ<13>

MEM_B_DQ<10>

MEM_B_DQ<15>

MEM_CKE<4>

MEM_B_BS<1>

MEM_B_DQ<0>

MEM_B_DQ<18>

MEM_B_DM<2>

MEM_B_DQ<16>

MEM_B_DQ<26>
MEM_B_DQ<28>

MEM_B_DQ<30>

MEM_B_A<11>

MEM_B_A<0>

MEM_B_RAS_L

MEM_ODT<2>

MEM_B_DQ<22>

MEM_B_DQS_N<3>

MEM_B_DQ<11>

MEM_B_DQ<14>

MEM_B_DQ<3>

MEM_B_DQ<8>

=PP1V8_S3M_MEM_B

MEM_B_DQ<23>

=PP0V9_S3M_MEM_DIMMVREFB

=PP1V8_S3M_MEM_B

85

85

85

85

85

85

85

91

85

85

85

85

85

85

85

85

85

85

85

85

85

85 85

85

85

85

85

85

91

91

33

85

85

85

85

85

33

33

33

85

85

85

85

85

85

32

85

32

33

33

85 85

85

85

85

85

85

85

45

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

33

32

33

33

33

33

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

33

33

33

33

33

33

33

33

33

33

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

85

33

33

85

85

85

85

85

85

85

33

33

33

33

85

85

85

85

85

85

32

85

32

17

17

17

17

17

17

17

16

16

17

17

16

16

17

17

8

17

8

17

17

17 17

17

17

17

17

17

17

16

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

8

16

17

17

16

9

17

17

16

16

17

17

17

48

48

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

16

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

16

17

17

17

17

17

17

17

17

17

17

17

16

17

17

17

17

17

17

8

17

8

8

Preliminary

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN
IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

One cap for each side of every RPAK, one cap for every two discrete resistors

Ensure CS_L and ODT resistors are close to SO-DIMM connector

402

0.1uF

10V

20%
CERM

C3352

1

2

402

0.1uF

10V

20%
CERM

C3356

1

2

402

0.1uF

10V

20%
CERM

C3354

1

2

402

0.1uF

10V

20%
CERM

C3350

1

2

402

0.1uF

10V

20%
CERM

C3360

1

2

402

0.1uF

10V

20%
CERM

C3364

1

2

402

0.1uF

10V

20%
CERM

C3368

1

2

402

0.1uF

10V

20%
CERM

C3366

1

2

402

0.1uF

CERM

10V

20%

C3362

1

2

402

0.1uF

10V

20%
CERM

C3358

1

2

85 32 17

85 32 17

85 32 16

56

5%

1/16W SM-LF

RP3358

2 7

56

1/16W5%SM-LF

RP3300

3 6

85 31 17

85 32 17

85 31 17

85 32 16

85 31 16

85 31 16

85 32 16

85 31 16

85 31 16

85 32 17

85 31 17

85 31 17

85 31 17

85 31 17

85 31 17

85 31 17

85 31 17

85 31 17

85 31 17

85 31 17

85 31 17

85 31 17

85 31 17

85 31 17

85 31 16

85 31 17

85 32 17

85 32 17

85 32 17

85 32 17

85 32 17

85 32 17

85 32 17

85 32 17

85 32 17

85 32 17

85 32 17

85 31 17

85 32 17

85 32 17

85 32 17

85 32 17

85 32 16

85 32 16

85 32 17

1/16W

402

MF-LF

5%

56

R3370

1 2

85 31 16

56

5%

1/16W SM-LF

RP3346

4 5

SM-LF1/16W

5%

56

RP3330

1 8

56

5%

1/16W SM-LF

RP3342

2 7

5%561/16W SM-LF

RP3330

3 6

5%

SM-LF

56

1/16W

RP3330

4 5

56

5%

1/16W SM-LF

RP3330

2 7

SM-LF

56

5%

1/16W

RP3342

4 5

SM-LF1/16W

5%

56

RP3342

3 6

SM-LF

56

5%

1/16W

RP3342

1 8

56

5%

1/16W SM-LF

RP3358

4 5

1/16W

5%

56

SM-LF

RP3346

3 6

56

5%

1/16W SM-LF

RP3358

3 6

1/16W

5%

56

SM-LF

RP3346

1 8

56

5%

1/16W SM-LF

RP3346

2 7

56

5%

1/16W SM-LF

RP3358

1 8

56

5%

1/16W SM-LF

RP3366

4 5

56

SM-LF

5%

1/16W

RP3366

1 8

SM-LF1/16W

5%

56

RP3366

2 7

56

5%

1/16W SM-LF

RP3350

1 8

56

5%

1/16W SM-LF

RP3334

4 5

SM-LF1/16W

5%

56

RP3338

2 7

56

5%

1/16W SM-LF

RP3354

3 6

SM-LF1/16W

5%

56

RP3354

4 5

1/16W

5%

56

SM-LF

RP3310

1 8

SM-LF1/16W

5%

56

RP3310

4 5

SM-LF1/16W

5%

56

RP3310

2 7

56

5%

1/16W SM-LF

RP3362

3 6

1/16W

5%

56

SM-LF

RP3350

4 5

56

5%

1/16W SM-LF

RP3350

2 7

SM-LF

56

5%

1/16W

RP3354

2 7

56

SM-LF1/16W

5%

RP3350

3 6

1/16W

5%

56

SM-LF

RP3354

1 8

SM-LF1/16W

5%

56

RP3338

4 5

1/16W

5%

56

SM-LF

RP3338

3 6

SM-LF1/16W

5%

56

RP3338

1 8

SM-LF

56

5%

1/16W

RP3334

2 7

SM-LF1/16W

5%

56

RP3334

1 8

1/16W

5%

56

SM-LF

RP3334

3 6

56

5%

1/16W SM-LF

RP3300

4 5

56

SM-LF

5%

1/16W

RP3305

2 7

56

5%

1/16W SM-LF

RP3366

3 6

5%

SM-LF

56

1/16W

RP3300

2 7

56

SM-LF1/16W

5%

RP3310

3 6

56

SM-LF

5%

1/16W

RP3362

2 7

SM-LF1/16W

5%

56

RP3305

4 5

56

SM-LF

5%

1/16W

RP3305

1 8

56

SM-LF1/16W

5%

RP3305

3 6

SM-LF

56

5%

1/16W

RP3300

1 8

56

5%

1/16W SM-LF

RP3362

1 8

1/16W

5%

56

SM-LF

RP3362

4 5

402

56

5%

1/16W MF-LF

R3371

1 2

85 32 16

402

0.1uF

CERM

20%
10V

C3370

1

2

85 31 17

85 31 16

85 31 17

85 32 16

402

0.1uF

10V

20%
CERM

C3348

1

2

402

0.1uF

10V

20%
CERM

C3346

1

2

402

0.1uF

10V

20%
CERM

C3336

1

2

402

0.1uF

10V

20%
CERM

C3334

1

2

CERM
402

10V

0.1uF

20%

C3332

1

2

0.1uF

CERM
402

10V

20%

C3330

1

2

CERM

0.1uF

10V

20%
402

C3312

1

2

402

0.1uF

CERM

20%
10V

C3310

1

2

402

0.1uF

10V

20%
CERM

C3307

1

2

402

0.1uF

10V

20%
CERM

C3305

1

2

402

0.1uF

10V

20%
CERM

C3302

1

2

402

0.1uF

10V

20%
CERM

C3300

1

2

402

0.1uF

10V

20%
CERM

C3344

1

2

402

0.1uF

10V

20%
CERM

C3342

1

2

402

0.1uF

10V

20%
CERM

C3340

1

2

402

0.1uF

10V

20%
CERM

C3338

1

2

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

Memory Active Termination

16

33

109

051-7261

MEM_B_A<10>

MEM_A_A<3>

MEM_B_A<3>

MEM_B_WE_L

MEM_B_CAS_L

MEM_A_A<9>

MEM_B_A<6>

MEM_B_A<0>

MEM_B_BS<0>

MEM_CS_L<1>

MEM_B_RAS_L

MEM_CS_L<3>

MEM_CS_L<0>

MEM_B_A<5>

MEM_B_A<2>

MEM_B_A<12>

MEM_B_A<1>

MEM_A_A<4>

MEM_A_A<12>

MEM_ODT<2>

MEM_A_A<2>

MEM_A_A<1>

MEM_A_A<0>

MEM_ODT<3>

MEM_A_A<5>

MEM_A_A<14>

MEM_A_BS<0>

MEM_A_RAS_L
MEM_A_CAS_L

MEM_A_BS<1>

MEM_A_A<10>

MEM_A_A<13>

MEM_A_A<7>
MEM_A_A<8>

MEM_A_A<6>

MEM_ODT<1>

MEM_ODT<0>

MEM_CKE<4>

MEM_CKE<3>

MEM_CKE<0>
MEM_CKE<1>

MEM_CS_L<2>

MEM_B_BS<1>

MEM_A_WE_L

MEM_B_A<4>

MEM_B_A<14>

MEM_B_A<13>

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<7>

MEM_B_BS<2>

MEM_B_A<11>

MEM_A_BS<2>

=PP0V9_S0M_MEM_TERM

MEM_A_A<11>

8

Preliminary

IN

IN

IN

IN

IN

IN

IN

IN
IN
IN

OUT
OUT
OUT

OUT

OUT
OUT
OUT
OUT

OUT

IN

OUT

OUT

IN

IN

IN

BI

BI
BI

BI
BI

BI
BI

IN
IN

IN
IN

OUT
OUT

OUT
OUT

IN

IN
BI

BI

BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Pull-up on LIO, FETs to GND on MLB

Place caps close to SB

Output to LIO

Left I/O Board Connector

516S0348

Place caps close to SB

NC

86 24

24

24

87 24

87 24

54 45

7

CRITICAL

QT500806-L121-9F

M-ST-SM

J3400

1

10
11 12
13 14
15 16
17 18
19220
21 22
23 24
25 26
27 28
29330
31 32
33 34
35 36
37 38
39440
41 42
43 44
45 46
47 48
49550
51 52
53 54
55 56
57 58
59660
61 62
63 64
65 66
67 68
69770
71 72
73 74
75 76
77 78
79880

81

82 83

84

9

66

45

66

67 57 46 45

24

24 13

54

7

30

30

46 24

46 45

35 25

86 23

86 23

86 23

86 23

86 23

28

46 45

86 24

86 24

86 24

86 24

86 24

86 24

88 30

88 30

88 30

88 30

87 24

87 24

24

24

48

48

48

48

0.1uF

402

10%
16V
X5R

C3421

12

0.1uF

X5R
402

10%
16V

C3420

12

0.1uF

X5R
402

10%
16V

C3411

12

0.1uF

X5R
402

10%
16V

C3410

12

86 24

34

109

16

051-7261

Left I/O Board Connector

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

USB_EXTB_OC_L

SMC_BC_ACOK

USB_EXTB_P

PCIE_CLK100M_MINI_P

PCIE_MINI_R2D_N

USB_EXCARD_P

MAKE_BASE=TRUE

PCIE_EXCARD_D2R_P

PCIE_MINI_R2D_C_P

MAKE_BASE=TRUE

PCIE_EXCARD_R2D_C_N

MAKE_BASE=TRUE

PCIE_EXCARD_D2R_N

PCIE_MINI_D2R_N
PCIE_MINI_D2R_P

PCIE_CLK100M_EXCARD_P

USB_MINI_N
USB_MINI_P

=PP1V5_S0_LIO

TP_PCIE_EXCARD_R2D_C_P

TP_PCIE_EXCARD_R2D_C_N

TP_PCIE_EXCARD_D2R_P

TP_PCIE_EXCARD_D2R_N

PCIE_MINI_R2D_C_N

PCIE_EXCARD_R2D_C_P

MAKE_BASE=TRUE

USB_EXTC_OC_L

LTALS_OUT
LIO_PLT_RST_L

EXCARD_CLKREQ_L
MINI_CLKREQ_L
EXCARD_OC_L
SMC_EXCARD_CP
LIO_S0_EN_L
SMC_EXCARD_PWR_EN
LIO_S3_EN
PCIE_WAKE_L

=SMBUS_LIO_SB_SCL
=SMBUS_LIO_SB_SDA

HDA_SDOUT

HDA_BIT_CLK

HDA_SYNC

HDA_RST_L

=SMBUS_LIO_SMC_SDA

=SMBUS_LIO_SMC_SCL

PCIE_EXCARD_R2D_P

PCIE_EXCARD_R2D_N

PCIE_CLK100M_EXCARD_N

PCIE_CLK100M_MINI_N

USB_EXTC_N

HDA_SDIN0

PCIE_MINI_R2D_P

ALS_GAIN

SYS_ONEWIRE

PM_WLAN_EN_L

USB_EXTC_P

USB_EXTB_N

USB_EXCARD_N

91

87

87

87

8

87

91

91

91

Preliminary

BI
BI

BI
BI

BI
BI

BI
BI

OUT

OUT

IN

IN

IN

OUT

OUT

IN
IN

THRML_PAD

VDDO_TTL1

VMAIN_AVLBL

SWITCH_VAUX

VAUX_AVLBL

LED_DUPLEX*

RSVD_43

RSVD_29

RSVD_25

RSVD_24

NC_64

CTRL12

NC_57

NC_52

NC_51

NC_32

RSET

SWITCH_VCC

AVDDH

AVDD0

AVDD3

VDDO_TTL3

LOM_DISABLE*

VDD0

VDD1

VDD3

VDD4

TX_P

CTRL18

TESTMODE

VDD2

VDD5

VDD7

CLKREQ*

WAKE*

PERST*

MDIP0

MDIP1
MDIN1

MDIP2
MDIN2

MDIP3

XTALI

MDIN3

XTALO

REFCLKP
REFCLKN

RX_N

RX_P

SPI_DO

SPI_CLK

SPI_CS

VPD_DATA

VPD_CLK

TX_N

MDIN0

AVDD1

LED_LINK1000*

VDD6

VDDO_TTL2

VDDO_TTL0

LED_ACT*

LED_LINK10/100*

AVDD2

SPI_DI

ANALOG

PCI EXPRESS

SPI

LED

TWSI

MEDIA

MAIN CLK

TEST/RSVD

IN

OUT
OUT

E2

WC*

NC0

NC1

VCC

VSS

SCL

SDA

IN

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

No link: 60 mA
10 Mbps: 70 mA

- Alias =YUKON_EC_PP2V5_ENET to PP1V8R2V5_ENET_PHY_AVDD, add 1x 0.1uF and 1x 0.001uF caps

- Connect =ENET_CLKREQ_L to clock generator via 0-ohm resistor (BOMOPTION: YUKON_ULTRA)

- Use YUKON_EC and YUKON_ULTRA BOMOPTIONs to select stuffed part

- Use 0-ohm resistors or variable supply to provide 1.8V or 2.5V to =PP1V8R2V5_ENET_PHY

Yukon EC: Pin 42 should be NC (or TP) net.

Page Notes

Power aliases required by this page:

- =PP3V3_ENET_PHY

- =PP1V2_ENET_PHY

(EC / Ultra)
(2.5V / 1.8V)
(2.5V / GND)

NC

NC

NC
NC
NC

NC
NC
NC

(IPD)

(IPU)
(IPU)
(IPU)
(IPU)

(IPU)

NC

NC
NC

NC

NC

NC

EC:AVDD 2.5V

EC:NO CONNECT

100 Mbps: 70 mA

Yukon Ultra

10 Mbps: 179 mA

No link: 4 mA

1000 Mbps: 4 mA

NC

VPD ROM

Yukon EC

100 Mbps: 150 mA

Yukon EC
No link: 171 mA

100 Mbps: 203 mA
1000 Mbps: 426 mA

Yukon Ultra

- =YUKON_EC_PP2V5_ENET

Must be high in S0 state (can use PP3V3_S0 as input)

1000 Mbps: 80 mA

100 Mbps: 4 mA

10 Mbps: 4 mA

Yukon Ultra (1.8V)

10 Mbps: 30 mA

No link: 0 mA

100 Mbps: 40 mA
1000 Mbps: 150 mA

Yukon EC (2.5V)

10 Mbps: 108 mA
100 Mbps: 126 mA
1000 Mbps: 218 mA

No link: 82 mA

Yukon EC: Alias to PP1V8R2V5_ENET_PHY_AVDD, add 1x 0.1uF & 1x 0.001uF caps
Yukon Ultra: Alias to GND

(EC:2.5V)

YUKON_ULTRA - Selects Yukon Ultra RSET.

BOM options provided by this page:

- =ENET_CLKREQ_L (NC/TP for Yukon EC)

Signal aliases required by this page:

- =PP1V8R2V5_ENET_PHY

To support Yukon EC and Ultra on the same board:

YUKON_EC - Selects Yukon EC RSET value.

instructions for dual Yukon EC /
Yukon Ultra schematic support.

NOTE: See bottom of page for

- =ENET_VMAIN_AVLBL (See note by pin)

and magnetics. Can also use BCP69T1 connected to CTRL18 pin 4 for internal VR.

(IPU)

1000 Mbps: 290 mA

10 Mbps: 130 mA

No link: 130 mA

NC

EC:CTRL25

49.9

MF-LF

1%
1/16W

402

SIGNAL_MODEL=EMPTY

R3740

1

2

1/16W

49.9

MF-LF

1%

402

SIGNAL_MODEL=EMPTY

R3741

1

2

87 37

87 37

87 37

87 37

87 37

87 37

87 37

87 37

87 24

87 24

402

0.001UF

50V
CERM

10%

C3740

1

2

402

0.001UF

50V
CERM

10%

C3742

1

2

402

0.001UF

50V
CERM

10%

C3744

1

2

402

0.001UF

50V
CERM

10%

C3746

1

2

49.9

MF-LF

1%

402

SIGNAL_MODEL=EMPTY

1/16W

R3742

1

2

1/16W

49.9

MF-LF

1%

402

SIGNAL_MODEL=EMPTY

R3743

1

2

1/16W

49.9

MF-LF

1%

402

SIGNAL_MODEL=EMPTY

R3747

1

2

1/16W

49.9

MF-LF

1%

402

SIGNAL_MODEL=EMPTY

R3746

1

2

1/16W

49.9

MF-LF

1%

402

SIGNAL_MODEL=EMPTY

R3745

1

2

49.9

MF-LF

1%
1/16W

402

SIGNAL_MODEL=EMPTY

R3744

1

2

16V 402X5R10%

0.1uF

C3735

1 2

402X5R16V10%

0.1uF

C3736

1 2

402X5R

0.1uF

10% 16V

PLACEMENT_NOTE=Place C3730 close to southbridge.

C3730

1 2

0.1uF

10% 16V X5R 402

PLACEMENT_NOTE=Place C3731 close to southbridge.

C3731

1 2

87 24

87 24

28

34 25

30

88 30

88 30

QFN

88E8058

CRITICAL

BOMOPTION=OMIT

U3700

192223

28

8

42

3

4

59

63

62

60

10

18

21

27

31

17

20

26

30

3251525764

5

56

55

16

24
25
29
43

53

54

37
36

35

34

9

11

46

65

50

49

12

271333394448

58

14045

61

47

38
41

6

15
14

66

1%
1/16W
MF-LF
402

4.99K

YUKON_ULTRA

R3765

1

2

603

4.7UF

20%

6.3V
CERM

C3720

1

2

10%
402

0.001UF

CERM

50V

C3724

1

2

X5R

10%
16V

402

0.1UF

C3723

1

2

X5R

10%
16V

0.1UF

402

C3722

1

2

0.1UF

402

16V

10%
X5R

C3721

1

2

CERM

50V

0.001UF

10%

402

C3714

1

2

X5R

10%
16V

402

0.1UF

C3713

1

2

X5R

10%
16V

402

0.1UF

C3712

1

2

0.1UF

402

16V

10%
X5R

C3711

1

2

CERM

4.7UF

603

20%

6.3V

C3710

1

2

10%

402

0.001UF

50V
CERM

C3715

1

2

402

16V

10%
X5R

0.1UF

C3705

1

2

402

16V

10%
X5R

0.1UF

C3704

1

2

0.1UF

402

16V

10%
X5R

C3703

1

2

0.1UF

402

16V

10%
X5R

C3702

1

2

X5R

10%
16V

402

0.1UF

C3701

1

2

CERM

6.3V

20%

4.7UF

603

C3700

1

2

CERM

50V

0.001UF

402

10%

C3708

1

2

CERM

50V

0.001UF

402

10%

C3707

1

2

CERM

50V

0.001UF

402

10%

C3706

1

2

CRITICAL

OMIT

M24C08

SO8

U3780

3

1

2

6

5

8

4

7

0.1UF

402

16V

10%
X5R

C3780

1

2

1/16W
MF-LF

402

5%

4.7K

R3780

1

2

1/16W
MF-LF
402

5%

4.7K

R3781

1

2

1/16W
MF-LF

402

4.7K

5%

R3760

1

2

0402

FERR-120-OHM-1.5A

L3720

1 2

36

36

SYNC_DATE=01/25/2007

SYNC_MASTER=T9_NOME

37

Ethernet (Yukon)

109

16

051-7261

CRITICAL

IC,88E8053,GIGABIT ENET XCVR,64P QFN

338S0270 U37001 YUKON_EC

IC,88E8058,GIGABIT ENET XCVR,64P QFN

YUKON_ULTRA

CRITICALU3700338S0386 1

IC,FLASH,88E8058 ETHERNET VPD,IIC,SO8

341S2060

YUKON_ULTRA

U37801 CRITICAL

U3780

IC,EEPROM,SERIAL IIC,8KBIT,SO8

341S1797 YUKON_EC1 CRITICAL

R3760

RES,4.87K,1%,1/16W,0402,LF

YUKON_EC1114S0285

=PP3V3_ENET_PHY

=YUKON_EC_PP2V5_ENET

=PP1V8R2V5_ENET_PHY

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PP1V8R2V5_ENET_PHY_AVDD

=PP1V2_ENET_PHY

PCIE_ENET_R2D_P

YUKON_VPD_DATA

PCIE_ENET_R2D_C_N

PCIE_ENET_R2D_C_P

PCIE_ENET_D2R_N

PCIE_ENET_D2R_P

PCIE_ENET_R2D_N

PCIE_ENET_D2R_C_N

TP_YUKON_CTRL18
TP_YUKON_CTRL12

=ENET_VMAIN_AVLBL

YUKON_RSET

ENET_LOM_DIS_L

ENET_MDI0 ENET_MDI1 ENET_MDI2 ENET_MDI3

YUKON_VPD_CLK

PCIE_ENET_D2R_C_P

ENET_MDI_P<2>
ENET_MDI_N<2>

ENET_MDI_P<1>

PCIE_CLK100M_ENET_P

ENET_MDI_N<1>

ENET_MDI_N<0>

=ENET_CLKREQ_L

PCIE_CLK100M_ENET_N

PCIE_WAKE_L

ENET_MDI_P<0>

ENET_RESET_L

ENET_CLK25M_XTALI
ENET_CLK25M_XTALO

ENET_MDI_N<3>

ENET_MDI_P<3>

8

8

8

37

8

87

87

87

87

Preliminary

OUT

THRM_PAD

NC

IN1

EN

IN2

OUT1
OUT2

NR/FB

GND

IN

OUT

G

D

S

IN

G

D

S

G

D

S

IN

OUT

G

DS

G

D

S

G

D

S

G

D

S

IN

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

NC

Yukon Crystal

(AC_EN_L)

ENET Enable Generation

1.9V for Yukon Ultra, 2.5V for Yukon EC

NC

Vout = 1.2246V * (1 + Ra / Rb)

(U3850 limit)

500 mA max output

NC

3.3V ENET FET

(PM_SLP_S3_L)

Ultra: Vout = 1.912V

NOTE: S3 term is guaranteed by FET & pull-up source, MUST BE S3 RAIL.

"WLAN" = "S0" || ("S3" && "AC" && "WOW_EN")

WLAN Enable Generation

Yukon AVDDL LDO

Yukon Ultra requires 1.9V on its magnetics to pass compliance tests

EC: Vout = 2.510V

NOTE: S3 term is guaranteed by source of R3800 & Q3810, MUST BE S3 RAIL.

"ENET" = "S0" || ("S3" && "AC" && "WOL_EN")

66

7

LREG_TPS79501DRB

SON

CRITICAL

U3850

8

6

1
2

7

5

3
4

9

1UF

6.3V
CERM

402

10%

C3850

1

2

10%

402

CERM

6.3V

1UF

C3851

1

2

YUKON_ULTRA

402

MF-LF

1/16W

1%

16.9K

R3855

1

2

402

1/16W

1%

30.1K

MF-LF

R3856

1

2

33PF

402

CERM

50V

5%

C3855

1

2

CRITICAL

25.0000M

SM-3.2X2.5MM

Y3860

24

13

18PF

5%
50V

402

CERM

C3861

1

2

18PF

402

50V

5%

CERM

C3860

1

2

35

35

SOT-363

2N7002DW-X-F

Q3800

6

2

1

57 46 45 40

10V

0.22UF

CERM

10%

402

C3800

1

2

2N7002DW-X-F

SOT-363

Q3805

3

5

4

SOT-363

2N7002DW-X-F

Q3805

6

2

1

24 13

34

402

100K

MF-LF

5%

1/16W

R3810

1 2

402

1/16W

5%

MF-LF

10K

R3811

1

2

CERM

0.01UF

402

16V

10%

C3810

12

NTR4101P

SOT-23

Q3810

3

1

2

0.033UF

X5R
402

16V

10%

C3811

1

2

MF-LF

402

10K

1/16W

5%

R3800

1

2

2N7002DW-X-F

SOT-363

Q3801

3

5

4

2N7002DW-X-F

SOT-363

Q3800

3

5

4

SOT-363

2N7002DW-X-F

Q3801

6

2

1

66 45 40 25

7

25

Yukon Power Control

051-7261

16

109

38

SYNC_MASTER=T9_NOME

SYNC_DATE=03/19/2007

114S0363

RES,31.6K,1%,1/16W,402,LF

YUKON_ECR38551

PM_WLAN_EN_L

=PP3V3_S3_P3V3ENETFET

=PP3V3_ENET_FET

P3V3ENET_SS

=PPVOUT_ENET_AVDDLDO

ENETAVDDL_FB

WOW_EN

SMC_ADAPTER_EN

PM_ENET_EN

ENET_CLK25M_XTALO

ENET_CLK25M_XTALI

=PP3V3_ENET_AVDDLDO

AC_EN_L

PM_SLP_S3_L

WOL_EN

PM_ENET_EN_L

8 8

8 8

Preliminary

SYM_VER2

NC2

NC3

NC4

LINE

SIDE

CHIP

SIDE

NC1

SYM_VER2

NC2

NC3

NC4

LINE

SIDE

CHIP

SIDE

NC1

BI

BI

BI

BI

BI

BI

BI

BI

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

sides of the board

Transformers should be
mirrored on opposite

Page Notes

Power aliases required by this page:

Signal aliases required by this page:

BOM options provided by this page:

Short shielded RJ-45

514-0277

(NONE)

(NONE)

Place close to connector

New Series Rs required for European Telecom Compliance

- =GND_CHASSIS_ENET

Place one cap at each pin of transformer

OMIT

NONE

SHORT

NONE
NONE

402

RX3910

1 2

10%

6.3V

1uF

CERM
402

C3903

1

2

1uF

10%
CERM

402

6.3V

C3902

1

2

MF-LF
402

1/16W

5%

75

R3903

1

2

75

MF-LF
402

5%
1/16W

R3902

1

2

1/16W

5%

402

MF-LF

75

R3901

1

2

1/16W
MF-LF

5%

402

75

R3900

1

2

6.3V
402

1uF

10%
CERM

C3901

1

2

1uF

CERM

6.3V

10%
402

C3900

1

2

1000BT-824-00275

CRITICAL

XFR-SM

OMIT

T3900

1

10

11

14

15

16

2

3

6

7

8 9

4
5 12

13

OMIT

CRITICAL

XFR-SM

1000BT-824-00275

T3901

1

10

11

14

15

16

2

3

6

7

8 9

4
5 12

13

87 35

87 35

87 35

87 35

87 35

87 35

87 35

87 35

9

F-RT-TH-RJ45

JM36113-P2054-7F

CRITICAL

J3900

9

10

11

12

1
2
3
4
5
6
7
8

OMIT

NONE

SHORT

NONE
NONE

402

RX3911

1 2

OMIT

NONE

SHORT

NONE
NONE

402

RX3991

1 2

OMIT

NONE

SHORT

NONE
NONE

402

RX3990

1 2

CRITICAL

10%
2KV

CERM

1000PF

1206

C3904

1 2

Ethernet Connector

109

051-7261

39

16

SYNC_MASTER=M75_MLB

SYNC_DATE=12/21/2006

157S0030

2

XFMR,ISO,HALF-PORT,1000T,16P,SMD,2MM

T3900,T3901

CRITICAL

PP1V8R2V5_ENET_PHY_AVDD

ENET_CTAP_COMMON

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

ENETCONN_N<3>

ENETCONN_P<2>

ENETCONN_N<2>

ENETCONN_P<3>

ENETCONN_N<1>

ENETCONN_P<0>

ENETCONN_N<0>

ENETCONN_P<1>

ENET_CTAP2

ENET_CTAP1

ENET_CTAP3

ENET_CTAP0

=GND_CHASSIS_ENET

ENET_MDI_P<0>

ENET_MDI_N<0>

ENET_MDI_P<1>

ENET_MDI_N<1>

ENET_MDI_P<2>

ENET_MDI_N<2>

ENET_MDI_P<3>

ENET_MDI_N<3>

35

91

91

91

91

91

91

91

91

Preliminary

BI

BI
BI
BI
BI

BI

BI

BI
BI

BI
BI

BI
BI
BI

OUT
OUT

IN

IN

IN

OUT

BI

BI

BI

BI

BI

BI

OUT

IN
IN

BI

OUT

SDA

SCL

PCI_AD19

PCI_AD18

PCI_AD17

PCI_AD16

PCI_AD15

PCI_AD14

PCI_AD13

PCI_AD12

PCI_AD11

PCI_AD10

PCI_AD31

PCI_AD30

PCI_AD28
PCI_AD29

PCI_AD27

PCI_AD25
PCI_AD26

PCI_AD24

PCI_AD23

PCI_AD21

PCI_AD20

PCI_AD9

PCI_AD8

PCI_AD7

PCI_AD6

PCI_AD5

PCI_AD4

PCI_AD3

PCI_AD2

PCI_PAR

PCI_CLK
PCI_IDSEL

GND

PCI_AD1

PCI_AD0

VCC

MFUNC

G_RST_L

REG18_1

REG18_0

REG_EN_L

PHY_PINT

PHY_PCLK

PHY_LREQ

PHY_LPS

PHY_LINKON

PHY_LCLK

PHY_D7

PHY_D6

PHY_D5

PHY_D4

PHY_D3

PHY_D1-D1

PHY_D2

PHY_D0-D0

PHY_CTL1-CTL1

PHY_CTL0-CTL0

PCI_ACK64_L

PCI_TRDY_L

PCI_STOP_L

PCI_SERR_L

PCI_RST_L

PCI_REQ64_L

PCI_REQ_L

PCI_PME_L

PCI_PERR_L

PCI_IRDY_L

PCI_INTA_L

PCI_GNT_L

PCI_FRAME_L

PCI_DEVSEL_L

VCCP

PCI_AD22

PCI_C_BE2_L

PCI_C_BE0_L

PCI_C_BE3_L

PCI_C_BE1_L

G

D

S

IN

G

D

S

IN

IN

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

when there’s no power on VCCP

G_RST* is clamped to VCCP

aliased to the same rail)

It must not be taken high

(OK if VCCP and VCC are

G_RST* assertion min 2ms

MFUNC as
a GPIO

Might use

(FW_G_RST_L)

87 24

87 24

87 24

87 24

87 24

87 24

87 24

87 24

87 24

87 24

87 24

87 24

87 24

87 24

25

87 24

88 30

87 24

28

10%

402

X5R

10V

1uF

C4008

1

2

10%

1uF

X5R
402

10V

C4009

1

2

10%

1uF

X5R
402

10V

C4004

1

2

1uF

10%
X5R

402

10V

C4003

1

2

402

X5R

10%

1uF

10V

C4002

1

2

402

X5R

10V

1uF

10%

C4001

1

2

1uF

402

10V
X5R

10%

C4000

1

2

4.7K

5%
1/16W
MF-LF
402

R4002

1

2

4.7K

5%

402

MF-LF

1/16W

R4001

1

2

87 24

39

39

39

39

39

39

5%
1/16W
MF-LF

402

220

R4090

1

2

5%
1/16W
MF-LF

402

1K

R4080

1

2

402

MF-LF

1/16W

5%

220

R4091

1

2

89 39

89 39

89 39

89 39

89 39

402

MF-LF

1/16W

5%

10K

R4010

1

2

BGA

(2 OF 2)

CRITICAL

TSB83AA22CZAJ

U4000

E4

C7

C8

F7F8F9

F10

G6G7G8

G9

G10

H6D6H7H8H9

H10

J8

J9

J10

K10

D7E6E7E8E9

E10

F6

A1

N12

L12
N11

N6
M6
M7
K9
K8
M5
K3
N1
L4
M2

M11

M1
L1
J4
H3
H4
J3
H2
G3
H1
F1

N10

F2
G4

M10
K12

M9
N9
L8
M8

N8
M3
K5
K2

D3

N2
L3
E3

L2

B3
K4

N3

L6
F4

J13

F3

D1
L7
L5
J5

F13
F12

E13
E12

C13
B9
B10
C11
B12
A11
B7
B4
A2
D4
B6
A3

G11
G12

C2

C3
C4

D5D8D9E5F5

H11J6J7

J11

E11

F11

2N7002DW-X-F

SOT-363

Q4070

3

5

4

39

SOT-363

2N7002DW-X-F

Q4070

6

2

1

5%
1/16W
MF-LF
402

100K

R4070

1

2

402

MF-LF

1/16W

5%

10K

R4071

1

2

45

28

22

5%
1/16W
MF-LF

402

R4000

1

2

0.1uF

X5R
402

10%
16V

C4010

1

2

0.1uF

10%
16V
X5R
402

C4011

1

2

87 24

87 24

87 24

87 24

87 24

87 24

87 24

87 24

87 24

87 24

87 24

87 24

87 24

87 24

87 24

87 24

87 24

87 24

87 24

87 24

87 24

87 24

87 24

87 24

87 24

87 24

87 24

87 24

87 24

87 24

FireWire Link (TSB83AA22)

051-7261

16

109

40

SYNC_MASTER=M75_MLB

SYNC_DATE=12/04/2006

=PP3V3_S3_PCI
=PP3V3_S3_FW

INT_PIRQD_L

PCI_FW_GNT_L

PCI_FRAME_L

PCI_ACK64_L

PCI_TRDY_L

PLT_GATED_RST

SMC_RSTGATE_L

FW_G_RST_L

=PP3V3_S3_FW

FW_PLT_RST_L

=PP1V8_S3_FW

FW_DATA<4>

PCI_PAR

PCI_C_BE_L<1>
PCI_C_BE_L<2>

PCI_AD<22>

PCI_C_BE_L<3>

PCI_C_BE_L<0>

PCI_PME_FW_L

PCI_FW_RST_L
PCI_SERR_L
PCI_STOP_L

TP_FW_CTL<0>
TP_FW_CTL<1>

TP_FW_DATA<0>

FW_DATA<2>

TP_FW_DATA<1>

FW_DATA<3>

FW_DATA<5>
FW_DATA<6>
FW_DATA<7>
CLKFW_PHY_LCLK
FW_LINKON
FW_LPS
FW_LREQ

FW_PINT

PCI_AD<0>
PCI_AD<1>

PCI_CLK33M_FW

PCI_AD<2>
PCI_AD<3>
PCI_AD<4>
PCI_AD<5>
PCI_AD<6>
PCI_AD<7>
PCI_AD<8>
PCI_AD<9>

PCI_AD<20>
PCI_AD<21>

PCI_AD<23>
PCI_AD<24>

PCI_AD<26>

PCI_AD<25>

PCI_AD<27>

PCI_AD<29>

PCI_AD<28>

PCI_AD<30>
PCI_AD<31>

PCI_AD<10>
PCI_AD<11>
PCI_AD<12>
PCI_AD<13>
PCI_AD<14>
PCI_AD<15>
PCI_AD<16>
PCI_AD<17>
PCI_AD<18>

FW_PCI_IDSEL

PCI_AD<19>

FW_MFUNC

FW_SDA

FW_SCL

PCI_FW_REQ_L

PCI_DEVSEL_L

PCI_PERR_L

PCI_IRDY_L

PCI_REQ64_L

FW_LLC_PP1V8LDO_EN_L

CLKFW_LINK_PCLK

38

38

8

8

8

8

Preliminary

SE

SM

RESET

D7

D5
D6

D4

D3

D2

CPS

PD

BMODE

PC2

PC0
PC1

LREQ

LPS

DS1
LCLK

DS0

XI

R1

R0

TESTM
TESTW

TPBIAS0
TPBIAS1

TPB1N

TPB1P

TPB0N

TPB0P

TPA1N

TPA1P

TPA0P
TPA0N

PINT

PCLK

AVDD_3P3

DVDD_3P3

DVDD_CORE

PLLVDD_3P3

PLLVDD_CORE

PLLGND

LKON_DS2

CNA

BI
BI

BI
BI

BI
BI

BI
BI

OUT

OUT
OUT

OUT

TRI-ST/NC

VCC

GND

IN

IN

IN

OUT

BI
BI
BI
BI
BI
BI

BI

BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

R4160 provides isolation between R4161 and unpowered LLC.

No need for DS2 pull-down on TSB83AA22A,
as 3rd FireWire port is not pinned out.

Power Class:

Single-port / Desktop systems are Power Class 0 (’000’).

Strap via alias on port page.

Implement 1K pull-up or pull-down on port page.

Multi-port Portable systems are Power Class 4 (’100’).

DSx Straps:

Hi: Data-Strobe only (1394a).
Lo: Beta Mode enable (1394b).

PHY power-up reset.

C4150 with internal
pull-up provides

NC

(IPU)

NC

1MA (MAX) BUS HOLDERS

0.22uF

X5R
402

20%

6.3V

C4150

1

2

402

MF-LF

1/16W

5%

390K

R4155

1

2

CRITICAL

(1 OF 2)

BGA

TSB83AA22CZAJ

U4000

D10

D11G5H5

L9

M12

A5

D13

C9
C10
C12
B13
B11

A6

B8

D12

H12

J12K7K6C5C6

G13

L13

N13

K13

N4

M4

N5

H13

K11

M13

A10

A7

A8

A12
A13

L10

A4

B5

L11
N7

E2

E1

J1

J2

B1

C1

G1

G2

D2
K1

A9

16V

20%

402

CERM

0.01uF

C4110

1

2

10V

10%

402

X5R

1uF

C4102

1

2

1uF

X5R
402

10%
10V

C4121

1

2

89 41

89 41

89 41

89 41

89 41

89 41

89 41

89 41

89 38

41

41

10V

10%

402

X5R

1uF

C4101

1

2

1uF

10V

10%

402

X5R

C4103

1

2

10V

10%

402

X5R

1uF

C4104

1

2

10V

10%

402

X5R

1uF

C4111

1

2

10%
10V

402

X5R

1uF

C4112

1

2

1uF

10V

10%

402

X5R

C4113

1

2

1uF

10V

10%

402

X5R

C4114

1

2

SM

98P3040MHZ

CRITICAL

G4180

2

3 1

4

89 38

89 38

89 38

89 38

38

38

38

38

38

38

5%

1/16W

402

MF-LF

1K

R4145

12

402

5%

MF-LF

1/16W

1K

R4142

12

10V

10%
402

X5R

1uF

C4131

1

2

10V

10%
402

X5R

1uF

C4130

1

2

6.3V

10%
603

CERM1

2.2uF

C4135

1

2

41

402

MF-LF

1/16W

5%

10K

R4156

1

2

402

MF-LF

1/16W

5%

4.7

R4186

1

2

1/16W

5%

402

MF-LF

1

R4100

1 2

1/16W

5%

402

MF-LF

1

R4135

1 2

1

MF-LF

402

5%

1/16W

R4120

1 2

1/16W

5%

402

MF-LF

470

R4161

1

2

1/16W

1%
MF-LF

6.34K

402

R4162

1

2

5%
1/16W
MF-LF

402

1K

R4160

1 2

38

22

MF-LF

402

5%

1/16W

R4180

1 2

6.3V

20%
402

X5R

0.22uF

C4180

1

2

1/16W

5%

402

MF-LF

1K

R4191

1

2

1K

MF-LF
402

5%
1/16W

R4140

1

2

1/16W

5%

402

MF-LF

1K

R4190

1

2

FireWire PHY (TSB83AA22)

SYNC_DATE=12/04/2006

051-7261

16

109

41

SYNC_MASTER=M75_MLB

FWPHY_R0

FW_0_TPBIAS

VOLTAGE=1.86V

=PP3V3_FW_PHY

FW_1_TPBIAS

VOLTAGE=1.86V

CLKFW_LINK_PCLK

FWPHY_TESTM

FW_PINT

FW_0_TPA_P

FW_1_TPA_N

FW_1_TPB_N

FW_1_TPB_P

FWPHY_R1

=PPVP_FW_CPS

FWPHY_DS0
FWPHY_DS1

FWPHY_TESTW

FW_LINKON

FWPHY_CPS

FWPHY_BMODE

FW_0_TPA_N

CLKFW_PHY_LCLK

FW_DATA<2>

FW_DATA<7>

FW_DATA<6>

FW_DATA<5>

FW_DATA<4>

FW_DATA<3>

=FWPHY_DS0

FW_LINKON_R

=FWPHY_PC0

FW_0_TPB_N

FWPHY_CLK98P304

=PP1V8_FW_PHYOSC

PP1V8_FW_PHYOSC_R

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.25 mm
VOLTAGE=1.8V

FWPHY_CLK98P304M_R

FW_LPS

FWPHY_RESET_L

=FWPHY_DS1

FW_LREQ

FW_0_TPB_P

FW_1_TPA_P

PP1V95_FW_PHY_PLLVDD

MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.22 mm
VOLTAGE=1.95V

=PP1V95_FW_PHY

PP3V3_FW_PHY_AVDD

MIN_NECK_WIDTH=0.22 mm

MIN_LINE_WIDTH=0.38 mm
VOLTAGE=3.3V

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm

PP3V3_FW_PHY_PLLVDD

41

8

8

41

8

41

8

Preliminary

V-

V+

S

G

D

S

G

D

GND

SENSEB

OUTA

FAULTB_L

FAULTA_L

ONB

INB

ONA

ONQ1

INA

GATE1A

GATE2A

SENSEA

GATE1B

GATE2B

OUTB

G

D

S

G

D

S

IN

IN

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NC

Late-VG Event Detection

NC

0.020 ohm => 2.4A

Current Limits

is running or on AC.

Enables port power when machine

FWLATEVG_3V_REF Hysteresis:

2.95V when port power is on

2.81V on late Vg event and port power is off

0.033 ohm => 1.5A

0.030 ohm => 1.66A (Ideal)

0.025 ohm => 2A

as +1 if over the limit (at any point during the period)

MAX5944 current limiter trips if integrator (counter)
reaches 16. A new sample (taken every 125 us) is weighted

and -1/128 if under the limit. As a result, the device
tends to trip easily on devices that produce periodic current
spikes. Current limit has been set higher to compensate.

Power aliases required by this page:

- =PPBUS_S5_FWPWRSW (system supply for bus power)

- =PP3V3_FW_LATEVG_ACTIVE

- =PPVP_FW_SUMNODE (power passthru summation node)
Signal aliases required by this page:

(NONE)
BOM options provided by this page:

- FW_PORT_FAULT_PU

Current Limit/Active Late-VG Protection

FireWire Port Power Switch

Page Notes

1/16W

5%

402

MF-LF

2.0M

R4219

1

2

10V

10%

603

CERM-X5R

0.33UF

C4219

1

2

0.1UF

CERM
402

20%
10V

C4210

1

2

200K

MF-LF

402

1%

1/16W

R4210

1 2

LMC7211

SM-LF

U4210

4

3

1

5

2

1/16W

5%

402

MF-LF

10K

R4211

1

2

402

100pF

CERM

5%

50V

C4211

1

2

MF-LF

1/16W

1%

402

10K

R4212

1

2

80.6K

MF-LF
402

1%
1/16W

R4213

1

2

SOD-123

MBR0540XXG

D4219

12

SOT23-3

SI2318DS

CRITICAL

Q4220

3

1

2

SI2318DS

SOT23-3

CRITICAL

Q4225

3

1

2

35V

1uF

10%

805

X7R

CRITICAL

C4225

1

2

CRITICAL

1uF

X7R
805

10%
35V

C4220

1

2

CRITICAL

805

MF

1%

0.25W

0.020

R4220

1 2

CRITICAL

MAX5944

SOIC

U4220

3

11

15

7

14

6

12

1

9

2

10

4

13

5

16

8

MF

1%

0.020

805

0.25W

CRITICAL

R4225

1 2

100K

402

5%
1/16W
MF-LF

FW_PORT_FAULT_PU

R4229

1

2

SOI-LF

CRITICAL

NDS9407

Q4260

5

6

7

8

4

1

2

3

16V

20%

402

CERM

0.01uF

C4260

1

2

402

470K

1/16W

5%
MF-LF

R4260

1

2

2N7002DW-X-F

SOT-363

Q4261

6

2

1

402

1/16W
MF-LF

330K

5%

R4261

1

2

2N7002DW-X-F

SOT-363

Q4261

3

5

4

57 46 45 36

66 45 36 25

7

MINISMDC

CRITICAL

1.5A-24V

F4260

1 2

PWRDI5

PDS340XF

CRITICAL

OMIT

D4260

1

2

3

371S0466

1

DIODE,SCHOTTKY,40V,5A,POWERDI 5,LF

D4260

CRITICAL

16

051-7261

42

109

FireWire Port Power

SYNC_MASTER=M75_MLB

SYNC_DATE=03/07/2007

=PP3V3_FW_LATEVG_ACTIVE

=PPBUS_S5_FW_FET

VOLTAGE=12.6V

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

PPBUS_FW_FWPWRSW_D

VOLTAGE=33V

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

PPVP_FW_PORTA_ISENSE

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V

PPBUS_FW_FWPWRSW_F

=PPBUS_S5_FWPWRSW

FWPWR_EN_L_DIV

PP2V4_FW_LATEVG

LATEVG_EVENT_L

P2V4_FWLATEVG_RC

FWPWR_EN_L

SMC_ADAPTER_EN

PM_SLP_S3_L

FW_PORT_FAULT_L
FW_PORTPWR_DISABLE_L

=PPVP_FW_SUMNODE

FW_PORTA_PWRCTRL

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=33V

PPVP_FW_PORTB_ISENSE

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=33V

PPVP_FW_PORTA_UF

FWLATEGV_3V_REF

FW_PORTB_PWRCTRL

PPVP_FW_PORTB_UF

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=33V

8

8

8

8

41

8

8

8

Preliminary

TPO#

TPI

TPO

TPI#

VGND

VP

SYM_VER-2

SYM_VER-2

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

"Snapback" & "Late VG" Protection

FireWire TPA/TPB pairs to their

(NONE)

- =GND_CHASSIS_FW_PORT0L

Power aliases required by this page:

514S0133

AREF needs to be isolated from all

When a bilingual device is connected to a

ground for speed signaling and connection

Cable Power

(PPVP_FW_PORT1)

Note: Trace PPVP_FW_PORT1 must handle up to 5A

(GND_FW_PORT1_VG)

PORT 1

OUTPUT

INPUT

(PPFW_PORT0_VP)

(GND_FW_PORT0_VG)

514-0255

PORT 0

(TPA-)

(TPA+)

(TPB+)

Note: Trace PPVP_FW_PORT0 must handle up to 5A

1394A

"Snapback" & "Late VG" Protection

beta-only device, there is no DC path

local grounds per 1394b spec

detection currents per 1394b V1.33

BREF should be hard-connected to logic

(FW_PORT1_BREF)

between them (to avoid ground offset issue)

BILINGUAL

NC

NC
VG

VP

TPB+

TPA+

TPA<R>

TPA-

TPB<R>

TPB-

Cable Power

(TPB-)

the necessary aliases to map the

NOTE: This page is expected to contain

Signal aliases required by this page:

FireWire PHY Config Straps

provide the appropriate constraints

constrained on this page. It is

NOTE: FireWire TPA/TPB pairs are NOT

BOM options provided by this page:

properly terminate unused signals.

- =GND_CHASSIS_FW_PORT1

- =GND_CHASSIS_FW_PORT0U

- =PP3V3_FW_LATEVG

- =PPVP_FW_PORT1

Page Notes

Late-VG Protection Power

PP2V4_FWLATEVG needs to be biased

- Port "1" Bilingual (1394B)

Configures PHY for:

- 2-port Portable Power Class (4)

- Port "0" Data-Strobe only (1394A)

Termination

1394b implementation based on Apple
FireWire Design Guide (FWDG 0.6, 5/14/03)

to apply to entire TPA/TPB XNets.

assumed that FireWire PHY page will

appropriate connectors and/or to

- =PPVP_FW_PORT0

- =GND_CHASSIS_FW_EMI_R

(NONE)

R4390 should be 390 Ohms max for a 3.3V rail

to at least 2.1V for FW signal integrity
and should be biased to 2.4V for margin

(Common to all ports)

for snap-back diodes

ESD and late-VG rail

Place close to FireWire PHY

TI PHYs require 1uF even though
FW spec calls out 0.33uF

6.3V

10%
402

CERM

1uF

C4350

1

2

56.2

MF-LF

402

1%

1/16W

R4351

1

2

56.2

MF-LF
402

1%
1/16W

R4350

1

2

SIGNAL_MODEL=EMPTY

56.2

MF-LF

402

1%

1/16W

R4353

1

2

SIGNAL_MODEL=EMPTY

56.2

MF-LF
402

1%
1/16W

R4352

1

2

1/16W

1%

402

MF-LF

4.99K

R4354

1

2

25V

5%

402

CERM

220pF

C4354

1

2

SM

FERR-250-OHM

CRITICAL

L4300

1 2

0.001uF

50V

20%

402

CERM

C4304

1

2

SOT-363

BAV99DW-X-F

DP4300

4

5

3

F-RT-TH-LF

1394A

CRITICAL

J4300

7 8 9 10

4

3

6

5

2

1

0.01uF

20%
603

CERM

50V

C4305

1

2

SOT-363

BAV99DW-X-F

DP4301

4

5

3

X7R

50V

0.01uF

10%

402

C4301

1

2

SOT-363

BAV99DW-X-F

DP4300

1

2

6
X7R
402

10%
50V

0.01uF

C4300

1

2

0.01uF

X7R
402

10%
50V

C4303

1

2

SOT-363

BAV99DW-X-F

DP4301

1

2

6

50V

10%

402

X7R

0.01uF

C4302

1

2

56.2

MF-LF

402

1%

1/16W

R4363

1

2

1/16W

1%

402

MF-LF

4.99K

R4364

1

2

56.2

MF-LF
402

1%
1/16W

R4362

1

2

25V

5%

402

CERM

220pF

C4364

1

2

56.2

MF-LF

402

1%

1/16W

R4361

1

2

6.3V

10%
402

CERM

1uF

C4360

1

2

56.2

402

MF-LF

1%
1/16W

R4360

1

2

NO STUFF

16V

20%
402

CERM

0.01uF

C4317

1

2

50V

10%

603-1

X7R

0.1uF

PLACEMENT_NOTE=Place C4319 close to connector pin 5.

C4319

1

2

MF-LF
402

5%
1/16W

1M

R4319

1

2

0.001uF

50V

20%
402

CERM

C4314

1

2

SM

CRITICAL

FERR-250-OHM

L4310

1 2

0.01uF

50V

20%
603

CERM

C4315

1

2

OMIT

NONE

SHORT

NONE
NONE

402

CX4304

1

2

0.01uF

50V

10%

402

X7R

C4310

1

2

BAV99DW-X-F

SOT-363

DP4310

1

2

6

10%
50V

0.01uF

402

X7R

C4311

1

2

BAV99DW-X-F

SOT-363

DP4310

4

5

3

BAV99DW-X-F

SOT-363

DP4311

1

2

6

BAV99DW-X-F

SOT-363

DP4311

4

5

3

0.01uF

50V

10%

402

X7R

C4313

1

2

50V

10%
X7R

402

0.01uF

C4312

1

2

1/16W

1%

402

MF-LF

332

R4390

1 2

SOT23

MMBZ5227B

CRITICAL

D4390

1

3

CRITICAL

F-RT-SM1

1394B-UG31903

J4310

1

10

11

2

3

4

5

6

7

8

9

90-OHM-100MA

1210-4SM1

CRITICAL

FL4300

1

2 3

4

CRITICAL

1210-4SM1

90-OHM-100MA

FL4301

1

2 3

4

18NH-250MA

CRITICAL

0402

L4360

1 2

CRITICAL

18NH-250MA

0402

L4361

1 2

SIGNAL_MODEL=EMPTY

18NH-250MA

CRITICAL

0402

L4362

1 2

CRITICAL

18NH-250MA

SIGNAL_MODEL=EMPTY

0402

L4363

1 2

OMIT

NONE

SHORT

NONE
NONE

402

CX4305

1

2

OMIT

NONE

SHORT

NONE
NONE

402

CX4306

1

2

OMIT

NONE

SHORT

NONE
NONE

402

CX4307

1

2

OMIT

NONE

SHORT

NONE
NONE

402

CX4302

1

2

OMIT

NONE

SHORT

NONE
NONE

402

CX4303

1

2

OMIT

NONE

SHORT

NONE
NONE

402

CX4300

1

2

OMIT

NONE

SHORT

NONE
NONE

402

CX4301

1

2

051-7261

16

43

109

SYNC_DATE=12/04/2006

SYNC_MASTER=M75_MLB

FireWire Ports

FW_B_TPB_L_N

FW_1_TPA_P

FW_1_TPB_P
FW_1_TPB_N

FW_PORT1_TPB_C

FW_0_TPB_N

FW_PORT0_TPB_C

MAKE_BASE=TRUE

FW_PORT0_TPA_P

MAKE_BASE=TRUE

FW_PORT0_TPA_N

MAKE_BASE=TRUE

FW_PORT0_TPB_N

MAKE_BASE=TRUE

FW_PORT0_TPB_P

FW_PORT1_TPA_P

MAKE_BASE=TRUE

FW_PORT1_TPB_P

MAKE_BASE=TRUE

FW_PORT1_TPA_N

MAKE_BASE=TRUE

MAKE_BASE=TRUE

FW_PORT1_TPB_N

=PP3V3_FW_LATEVG

FW_B_TPA_L_N

=PP3V3_FW_PHY

=FWPHY_DS0

=FWPHY_PC0

FW_0_TPB_P

FW_0_TPBIAS

FW_1_TPA_N

FW_0_TPA_N

FW_0_TPA_P

FW_B_TPA_L_P

FW_1_TPBIAS

VOLTAGE=2.4V

MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm

PP2V4_FW_LATEVG

FW_PORT0_TPB_FL_N

FW_PORT0_TPA_FL_N
FW_PORT0_TPB_FL_P

=PPVP_FW_PORT1

FW_PORT0_TPA_N

FW_PORT0_TPA_FL_P

=PPVP_FW_PORT0

FW_PORT0_TPB_N

=GND_CHASSIS_FW_PORT0L

=GND_CHASSIS_FW_PORT0L

VOLTAGE=33V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PPVP_FW_PORT0

FW_PORT0_TPA_P

PP2V4_FW_LATEVG

FW_PORT0_TPB_P

=GND_CHASSIS_FW_PORT0U

PPVP_FW_PORT1

VOLTAGE=33V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

=GND_CHASSIS_FW_PORT1

PP2V4_FW_LATEVG

FW_PORT1_TPA_P

FW_PORT1_AREF

FW_PORT1_TPA_N

=GND_CHASSIS_FW_PORT1

FW_PORT1_TPB_P

FW_PORT1_TPB_N

FW_B_TPB_L_P

=FWPHY_DS1

89

89

89

89

39

89

89

89

89

41

41

41

41

41

41

39

39

39

39

41

41

41

41

41

41

41

41

8

8

39

39

39

39

39

39

39

39

40

91

91

91

8

41

91

8

41

9

9

41

40

41

9

9

40

41

41

41

41

39

Preliminary

BI
BI

IN

IN

IN

IN

OUT

OUT

OUT

OUT

G

D

S

G

D

S

IN

IN

IN

Y

B

A

SGD

IN

BI

BI

BI

BI

BI

IN

BI

BI

BI

IN IN

IN

OUT

BI
BI
BI
BI

BI
BI
BI
BI

IN

OUT

OUT

IN

OUT

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

10K pull-up to 5V)

(UATA_DSTROBE)

(UATA_CS0*)

Placement note

Place within 12.7mm
from ball of SB

Unused SATA Ports

IDE (ODD) Connector

(UATA_CS1*)

(UATA_STOP)

516S0335

NC

(UATA_HSTROBE)

(SB has internal 5.7k-23.5k
pull-down)

Indicates disk presence

(ODD has internal

23

23

86 23

86 23

86 23

86 23

86 23

86 23

86 23

86 23

2N7002DW-X-F

SOT-363

Q4421

3

5

4

SOT-363

2N7002DW-X-F

Q4421

6

2

1

100K

MF-LF

402

5%

1/16W

R4422

1

2

24

M-ST-SM1-LF

CRITICAL

J4400

1

10
11
12
13
14
15
16
17
18
19

2

20
21
22
23
24
25 26

27

28

29

3

30

31

32

33

34

35

36

37

38

39

4

40

41

42

43

44

45

46

47

48

49

5

50

6
7
8
9

86 23

402

10V

0.068UF

10%

CERM

C4422

1

2

86 24

SC70

MC74VHC1G09

U4430

3

2

1

4

5

1/16W

5%

402

MF-LF

100K

R4430

1

2

FDC606P

SOT-6

CRITICAL

Q4420

1 2 5 6

3

4

86 23

86 23

86 23

86 23

86 23

86 23

42

1%

24.9

1/16W
MF-LF
402

R4460

1

2

86 23

86 23

86 23

86 23 86 23

86 23

1/16W

5%

MF-LF

4.7K

402

R4402

1

2

1/16W

5%

402

MF-LF

6.2K

R4403

1

2

45

33K

5%
1/16W
MF-LF
402

R4410

1

2

5%

402

MF-LF

1/16W

10K

R4420

1

2

86 23

86 23

86 23

86 23

86 23

86 23

86 23

86 23

86 23

86 23

86 23

86 23 86 23

86 23

402

CERM

10%

0.01UF

16V

C4421

1 2

402

5%

MF-LF

1/16W

47K

R4421

1 2

SYNC_DATE=12/07/2006

SYNC_MASTER=M75_MLB

109

44

16

051-7261

PATA Connector

=PP5V_S0_ODD

VOLTAGE=5V

PP5V_ODD

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm

P5VODD_SS

=PP3V3_S0_IDE

ODD_PWR_EN_L

IDE_PDDREQ

IDE_PDIORDY

IDE_IRQ14

SMC_ODD_DETECT

IDE_PDA<0>

IDE_PDD<6>
IDE_PDD<5>

IDE_PDD<1>

IDE_PDIOR_L

IDE_PDA<2>

IDE_PDD<8>
IDE_PDD<9>
IDE_PDD<10>
IDE_PDD<11>

IDE_PDD<12>
IDE_PDD<13>
IDE_PDD<14>
IDE_PDD<15>

IDE_PDIOW_L
IDE_PDDACK_L

IDE_PDA<1>

IDE_PDCS3_L

IDE_PDD<4>

IDE_PDD<3>

IDE_PDD<0>

SATA_C_D2R_N

SATA_C_D2R_P

SATA_B_D2R_N

SATA_B_D2R_P

SATA_C_R2D_C_N

SATA_C_R2D_C_P

SATA_B_R2D_C_N

SATA_B_R2D_C_P

SATA_RBIAS_N

SATA_RBIAS_P

TP_SATA_B_R2DP

MAKE_BASE=TRUE

TP_SATA_C_R2DP

MAKE_BASE=TRUE

MAKE_BASE=TRUE

TP_SATA_C_R2DN

TP_SATA_C_D2RP

MAKE_BASE=TRUE

TP_SATA_B_R2DN

MAKE_BASE=TRUE

TP_SATA_B_D2RN

MAKE_BASE=TRUE

TP_SATA_B_D2RP

MAKE_BASE=TRUE

TP_SATA_C_D2RN

MAKE_BASE=TRUE

SATA_RBIAS

MAKE_BASE=TRUE

ODD_RST_BUF_L

IDE_PDD<7>

IDE_PDD<2>

P5VODD_EN_L

ODD_RST_5VTOL_L

=PP5V_S0_PCIREQFIX

ODD_RST_BUF_L

IDE_PDCS1_L

=PP5V_S0_ODDPWREN

ODD_PWR_EN

8

8

86

8

42

8

Preliminary

OUT

VBUS

D-

D+

GND

IN

IN

OUT

OUT

OUT

EN

OC*

GND

THRML

PAD

VDD

THRM_PAD

GND

0I0 Y0

SEL

1I1

1I0

0I1

Y1

BI

BI

SYM_VER-1

IN

OUT

IN

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Port Power Switch

Right USB Port

Place L4600 and L4605 across moat

514S0115

If power source is S3, can tie EN to IN.

SEL=0 Choose SMC
SEL=1 Choose USB

USB/SMC Debug Mux

CRITICAL

0603

FERR-220-OHM-2A

L4605

1 2

POLY
B2

20%

6.3V

100UF

CRITICAL

C4696

1

2

6.3V

805-1

20%

10uF

CERM

C4695

1

2

10uF

CERM

805-1

20%

6.3V

C4690

1

2

0.1UF

CERM
402

20%
10V

C4691

1

2

16V

20%
402

CERM

0.01uF

C4605

1

2

OMIT

NONE

SHORT

NONE
NONE

402

CX4601

1

2

24 13

UAR2X

F-RT-SM-USB-RGT1

CRITICAL

J4600

1
2
3
4

5
6

7
8

CRITICAL

SC-75

RCLAMP0502B

RTUSB_ESD

D4600

3

12

TPS2051

MSOP

CRITICAL

U4690

4

1

2

3

5

8

7

6

9

PI3USB10

TDFN

CRITICAL

SMC_DEBUG_YES

SIGNAL_MODEL=USB_MUX

U4650

12

10

11

9

157

6

13

2

8

3
4

86 24

86 24

SMC_DEBUG_YES

CERM

402

20%
10V

0.1UF

C4650

1

2

10K

MF-LF
402

5%
1/16W

R4650

1

2

1210-4SM1

90-OHM-100MA

CRITICAL

L4600

1

2 3

4

47 46 45

7

47 46 45

7

45

66

SMC_DEBUG_NO

1/16W
MF-LF

0

5%

402

R4651

1 2

1/16W
MF-LF

5%

402

0

SMC_DEBUG_NO

R4652

1 2

OMIT

NONE

SHORT

NONE
NONE

402

CX4600

1

2

OMIT

NONE

SHORT

NONE
NONE

402

CX4603

1

2

OMIT

NONE

SHORT

NONE
NONE

402

CX4602

1

2

46

109

16

SYNC_MASTER=M75_MLB

SYNC_DATE=12/04/2006

External USB Connector

051-7261

USB_EXTA_OC_L

=PP5V_S3_RTUSB

=PP3V42_G3H_SMCUSBMUX

USB_EXTA_P

USB_EXTA_N

USB2_EXTA_MUXED_N

SMC_TX_L
SMC_RX_L

USB_DEBUGPRT_EN_L

MIN_LINE_WIDTH=0.5 mm

PP5V_S3_RTUSB_F

MIN_NECK_WIDTH=0.5 mm
VOLTAGE=5V

=USB_EXTA_EN

USB2_RT_P

USB2_EXTA_MUXED_P

USB2_RT_N

=GND_CHASSIS_RTUSB

PP5V_S3_RTUSB_ILIM

MIN_NECK_WIDTH=0.5 mm

MIN_LINE_WIDTH=0.5 mm
VOLTAGE=5V

8

8

91

91 91

91

9

Preliminary

SYM_VER-1

BI

BI

BI

BI

SYM_VER-1

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

TABLE_5_ITEM

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

SIM Interconnect

Camera Power

WWAN Power

WWAN_SIM_CLOCK

514S0171

return current loop small

Keep close to FL4745 to keep

514S0172

WWAN USB D-

WWAN Power

WWAN_SIM_DATA

WWAN_SIM_RESET

WWAN_SIM_VCC

NC

WWAN Ground

WWAN TwinAx Shield 2

WWAN Power

NC

WWAN Ground

WWAN Ground

WWAN Ground

NC

return current loop small

Keep close to FL4735 to keep

Camera TwinAx Shield

Camera USB D-

Camera Ground

Camera Ground

Camera Power

Connector shield

WWAN Power

WWAN USB D+

Left Clutch Barrel Interconnect

Camera USB D+

0.01UF

10%
X7R

402

50V

C4730

1

2

OMIT

CRITICAL

FERR-220-OHM-2A

0603

L4731

1 2

50V
402

NO STUFF

0.001uF

CERM

20%

C4731

1

2

0603

CRITICAL

OMIT

FERR-220-OHM-2A

L4741

1 2

0603

FERR-220-OHM-2A

CRITICAL

L4730

1 2

CRITICAL

20347-125E-12

F-RT-SM

J4731

1

10
11
12
13
14
15
16
17
18
19

2

20
21
22
23
24
25

26
27
28
29

3

30

31

32

4
5
6
7
8
9

CRITICAL

90-OHM-100MA

1210-4SM1

FL4745

1

2 3

4

86 24

86 24

X7R
402

0.01UF

10%
50V

C4740

1

2

FERR-220-OHM-2A

CRITICAL

0603

L4740

1 2

NOSTUFF

0.001uF

CERM

402

20%
50V

C4741

1

2

86 24

CRITICAL

20347-110E-12

F-RT-SM

J4732

1

10

11
12

13

14

2
3
4
5
6
7
8
9

0402

CRITICAL

FERR-120-OHM-1.5A

OMIT

L4764

1 2

86

24

MF-LF

0

5%

603

1/10W

R4742

1 2

MF-LF

5%

0

1/10W

603

R4740

1 2

MF-LF

5%

0

1/10W

603

R4741

1 2

90-OHM-100MA

CRITICAL

1210-4SM1

FL4735

1

2 3

4

Left Clutch Barrel Interconnect

47

109

16

051-7261

SYNC_MASTER=M75_MLB

SYNC_DATE=12/21/2006

CRITICAL116S0004

RES,MF,1/16W,0OHM,5,0402,SM,LF

L4764

1

CRITICAL113S0022

L4731,L4741

2

RES,MF,1/10W,0OHM,5,0603,SM,LF

WWAN_SIM_RESET

USB_WWAN_F_N
USB_WWAN_F_P

=GND_CHASSIS_LEFTCLUTCH

PPVCC_WWAN_SIM

USB_CAMERA_N

USB_CAMERA_P

MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V

MIN_LINE_WIDTH=0.25 mm

PP5V_S3_CAMERA_F

WWAN_SIM_CLOCK

USB_CAMERA_F_N

WWAN_SIM_RESET

WWAN_SIM_DATA

USB_EXTD_NUSB_WWAN_N

MAKE_BASE=TRUE

USB_EXTD_P

=PP5V_S3_CAMERA

USB_CAMERA_F_P

WWAN_SIM_DATA

MIN_LINE_WIDTH=0.25 mm
VOLTAGE=5V

MIN_NECK_WIDTH=0.2 mm

PP5V_S3_WWAN_F

USB_WWAN_P

MAKE_BASE=TRUE

=PP5V_S3_WWAN

=GND_CHASSIS_LEFTCLUTCH

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.2 mm

PPVCC_WWAN_SIM

VOLTAGE=3.3V

WWAN_SIM_CLOCK

80

80

91

91

44

91

91

91

91

91

44

91

44

7

7

9

44

7

44

7

44

44

8

7

44

7

8

9

44

44

Preliminary

IN

IN

IN

OUT

OUT

OUT

IN

IN

OUT

IN
IN
IN
IN
IN
IN
IN
IN

IN

IN

OUT

IN

OUT

OUT

P16

P51

P50

P42/SDA1

P97/IRQ15*/SDA0

P95/IRQ14*

P94/IRQ13*

P93/IRQ12*

P92/IRQ0*

P91/IRQ1*

P86/IRQ5*/SCK1/SCL1

P83/LPCPD*

P82/CLKRUN*

P80/PME*

P35/LRESET*

P34/LFRAME*

P10

P12
P13
P14
P15

P17

P31/LAD1

P30/LAD0

P32/LAD2
P33/LAD3

P36/LCLK
P37/SERIRQ

P44/TMO1

P77/AN7

P76/AN6

P81/GA20

P96/EXCL

P11

P47/PWX1/PWM1

P45
P46/PWX0/PWM0

P40/TMIO

P43/TMI1/EXSCK1

P27

P26

P25

P24

P23

P22

P21

P20

P41/TMO0

P52/SCL0

P60/KIN0*
P61/KIN1*
P62/KIN2*
P63/KIN3*
P64/KIN4*

P65/KIN5*
P66/IRQ6*/KIN6*
P67/IRQ7*/KIN7*

P70/AN0
P71/AN1
P72/AN2
P73/AN3
P74/AN4
P75/AN5

P84/IRQ3*/TXD1
P85/IRQ4*/RXD1

P90/IRQ2*

(1 OF 4)

PA2/KIN10*/PS2AC
PA3/KIN11*/PS2AD

PA5/KIN13*/PS2BD

PA4/KIN12*/PS2BC

PB2
PB3
PB4

PE0

PG6/EXIRQ14*/EXSDAB

PG5/EXIRQ13*/EXSCLA

PH1/EXIRQ7*

PH0/EXIRQ6*

PG7/EXIRQ15*/EXSCLB

PG4/EXIRQ12*/EXSDAA

PH3/EXEXCL

PH2/FWE

PB5

PF4/PWM4

PF2/IRQ10*/TMOY

PG2/EXIRQ10*/SDA2

PG0/EXIRQ8*/TMIX

PF7/PWM7

PC3/TIOCD0/TCLKB/WUE11*

PH5

PB7

PB6

PH4

PF5/PWM5
PF6/PWM6

PG1/EXIRQ9*/TMIY

PA6/KIN14*/PS2CC
PA7/KIN15*/PS2CD

PD0/AN8
PD1/AN9
PD2/AN10
PD3/AN11
PD4/AN12
PD5/AN13
PD6/AN14
PD7/AN15

PF0/IRQ8*/PWM2
PF1/IRQ9*/PWM3

PB0/LSMI*
PB1/LSCI

PC0/TIOCA0/WUE8*
PC1/TIOCB0/WUE9*
PC2/TIOCC0/TCLKA/WUE10*

PC4/TIOCA1/WUE12*
PC5/TIOCB1/TCLKC/WUE13*
PC6/TIOCA2/WUE14*
PC7/TIOCB2/TCLKD/WUE15*

PG3/EXIRQ11*/SCL2

PF3/IRQ11*/TMOX

PA1/KIN9*/PA2DD

PA0/KIN8*/PA2DC

PE1*/ETCK
PE2*/ETDI
PE3*/ETDO
PE4*/ETMS

(2 OF 4)

VCL

AVREF

VCC

VCC

VCC

AVCC

XTAL
EXTAL

AVCC

VCC

MD1
MD2

NMI

RES*

ETRST*

AVREF

AVSS

VSS

(3 OF 4)

NC22

NC21

NC20

NC19

NC18

NC17

NC16

NC15

NC14

NC13

NC12

NC9

NC6

NC11

NC10

NC8

NC7

NC5

NC4

NC3

NC2

NC1

NC0

(4 OF 4)

OUT
OUT

BI

IN

IN

OUT

BI

BI

OUT

OUT

IN

IN

OUT

OUT

IN

OUT
OUT
OUT
OUT

IN

IN

IN

IN

IN
IN

IN

IN

IN
IN

IN

IN

IN

IN

OUT

IN

IN

OUT
OUT
OUT
OUT

BI
BI
BI
BI
BI
BI

OUT
OUT

OUT

OUT

IN

IN

OUT

IN

IN

IN

OUT
OUT

BI

BI

OUT

IN

OUT

OUT

OUT

IN

BI
BI
BI
BI

IN
IN
IN

OUT

BI

IN
IN
IN
IN
BI

BI

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(OC)

(OC)

(OC)

(OC)

(OC)

(OC)

(OC)

(DEBUG_SW_2)

(OC)

(OC)

(OC)
(OC)

(OC)

(OC)

(OC)

(OC)

pins designed as outputs can be left floating,

NOTE: Unused pins have "SMC_Pxx" names. Unused

those designated as inputs require pull-ups.

(DEBUG_SW_3)

NC

NC

NC

NC

NC
NC

NC

NC

NC

NC
NCNC

NC

NC
NC
NC

NC

NC

NC
NC
NC
NC
NC

NOTE: SMS Interrupt can be active high or low, rename net accordingly.
If SMS interrupt is not used, pull up to SMC rail.

(DEBUG_SW_1)

(OC)

805-3

CERM-X5R

6.3V

20%

22UF

C4902

1

2

47 46 25

7

47 46

7

80 46

7

CERM-X5R

0.47UF

PLACEMENT_NOTE=Place C4907 close to U4900 pin F1

10%
402

6.3V

C4907

1

2

CERM

10V

0.1UF

402

20%

C4903

1

2

PLACEMENT_NOTE=Place C4920 close to U4900 pins N14,N15

CERM

10V

0.1UF

402

20%

C4920

1

2

PLACEMENT_NOTE=Place R4999 close to U4900 pins N14,N15

MF-LF

5%

1/16W

4.7

402

R4999

1 2

CERM

10V

0.1UF

402

20%

C4904

1

2

SM

XW4900

1

2

25

59

7

CERM

10V

0.1UF

402

20%

C4905

1

2

25

7

46

66 46 28

38

CERM

10V

0.1UF

402

20%

C4906

1

2

49

49

49

49

49

49

49

49

57 46

7

67 57 46 34

47 46 45 43

7

47 46 45 43

7

57 46 40 36

66

OMIT

SMC_H8S2116

BGA

U4900

B12
C13
A15
B14
B15
C14
D12
C15

D13
D14
D15
E12
E14
E15
E13
F14

D9
C9
A9
B9
D8
C8
A8
D7

A5
B5
D5
C3
B1
C2
D3
C1

G1
G4
F2

L13
L14
L15
K12
K13
K14
J12
J13

N12
R13
P13
R14
P14
R15
N13
P15

C7
A7
B7
D6
C6
A6
B6

K4
J2
J1
J3
J4
H2
H1
G2

SMC_H8S2116

BGA

OMIT

U4900

R3
P3
R2
N3
R1
N2
M4
N1

B10
A10
D10
A11
B11
C11
A12
D11

G14
G15
G13
G12
H14
H15
H13
H12

M11
P11
R11
N11
P10
R10
N10
M10

M3
M2
M1
L4
L2

M7
P6
R6
N6
M6
R5
P5
N5

P9
R9
N9
P8
R8
M8
P7
R7

E1
F3
K2
C4
D4
B3

OMIT

SMC_H8S2116

BGA

U4900

N14

N15

M14

M15

P12
R12

L1

B2

E2
K1

F4

E3

P2P1J15A1F1

D1P4R4

F12

F13

B13

A13

A4B4D2

A2

OMIT

SMC_H8S2116

BGA

U4900

G3
H3

K15
J14

F15
A14
C12
C10
C5
A3
B8
E4

K3

H4
M9
N8

L3
N4
M5

N7
M12
M13
L12

67 46

67 46

48

1/16W

5%

MF-LF

10K

402

R4909

1

2

47

7

47

7

1/16W

5%

10K

402

MF-LF

R4901

1

2

10K

MF-LF

5%
1/16W

402

R4902

1

2

1/16W

5%
MF-LF

0

NO STUFF

402

R4903

1

2

1/16W

5%
MF-LF

10K

402

R4998

1

2

43

46 34

32 16

25

49

7

42

46 34

34

25

46

52

52

46

46

46

46

52

52

55

55

49

55

54

54

49

47 46

7

46

47 46

7

47 46

7

47 46

7

80 46

67

46

67

46

48

48

48

48

48

48

46

46

54 34

7

55

49

47 46 45 43

7

47 46 45 43

7

46

9

46

46

46

47 25

7

31 16

28 25

7

47

7

25 13

47 25

7

25

7

46

47 23

7

47 23

7

47 23

7

47 23

7

47 23

7

28

7

88 30

54

48

66 40 36 25

7

66 25

7

46 25

7

46

48

48

46

051-7261

16

109

49

SMC

SYNC_MASTER=T9_NOME

SYNC_DATE=12/21/2006

SMC_LRESET_L

SMC_TX_L

PM_SUS_STAT_L

SMC_RX_L
SMB_MGMT_CLK

SMC_NB_1V8_ISENSE

SMC_PG0

SMC_PH4

SMC_P64

SMC_P63

SMC_P62

SMC_ADAPTER_EN

SMC_GPU_ISENSE

SMC_P14

SMC_P67

PM_LAN_PWRGD

SMC_GFX_THROTTLE_L

SMC_P45

SMC_P43

SMC_SYS_LED

SMC_WAKE_SCI_L
SMC_P81

SMC_DCIN_ISENSE
SMC_PBUS_VSENSE
SMC_BATT_ISENSE
SMC_NB_1V25_ISENSE

PM_SLP_S5_L

SMC_ONOFF_L

PM_CLKRUN_L

SMC_GPU_VSENSE

PP3V3_S5_AVREF_SMC

SMC_TCK

SMC_PF0
SMC_PF1
SMC_LID

SMB_BSA_CLK

SMC_TMS

SMC_TDO

SMC_BATT_VSET
SMC_SYS_ISET

PM_SLP_S3_L

PM_PWRBTN_L

SMC_PROCHOT_3_3_L

=SMC_SMS_INT

SMB_A_S3_CLK

SMC_FAN_2_TACH

SMS_Y_AXIS
SMS_Z_AXIS
SMC_ANALOG_ID

SMC_FAN_1_CTL

IMVP_VR_ON

SMC_P20
SMC_P21

PM_RSMRST_L

ALS_RIGHT

ALS_LEFT

SMC_NB_CORE_ISENSE

SMS_X_AXIS

SMC_FAN_3_TACH

SMC_FAN_0_CTL

PM_EXTTS_L<1>

USB_DEBUGPRT_EN_L

SMC_P46

SMC_P44

INT_SERIRQ

SMB_0_S0_CLK

SMC_RX_L

SMC_TX_L

SMC_SYS_KBDLED

SMB_MGMT_DATA

PCI_CLK33M_SMC

LPC_FRAME_L

LPC_AD<3>

LPC_AD<2>

LPC_AD<1>

LPC_AD<0>

SMC_BATT_CHG_EN

SMC_BATT_TRICKLE_EN_L

ALL_SYS_PWRGD

SMC_RSTGATE_L

RSMRST_PWRGD

SMC_P27

SMC_P26

SMC_P23

SMC_KBC_MDE

SMC_TRST_L

SMC_NMI

SMC_VCL

PM_EXTTS_L<0>

SMC_PA0
SMC_PA1

=PP3V3_S5_SMC

SMC_MD1

PP3V3_S5_SMC_AVCC

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.20 MM

GND_SMC_AVSS

SMC_RESET_L
SMC_XTAL

SMC_EXTAL

SMC_PM_G2_EN

SMC_CPU_ISENSE
SMC_CPU_VSENSE

SMC_BC_ACOK
SMC_BS_ALRT_L

PM_S4_STATE_L

SMC_SUS_CLK
SMB_0_S0_DATA

SMC_CASE_OPEN

SMC_TDI

SMB_BSA_DATA

SMB_A_S3_DATA

SMB_B_S0_DATA

SMC_PROCHOT

SMB_B_S0_CLK

SMC_THRMTRIP

ALS_GAIN

SMC_FWE

SMS_ONOFF_L

PM_BATLOW_L

SYS_ONEWIRE

SMC_PB0

SMC_EXCARD_PWR_EN

SMC_EXCARD_CP

SMC_RUNTIME_SCI_L
SMC_ODD_DETECT
ISENSE_CAL_EN

SMC_EXCARD_OC_L
SMC_GFX_OVERTEMP_L

SMC_FAN_2_CTL
SMC_FAN_3_CTL
SMC_FAN_0_TACH
SMC_FAN_1_TACH

SMC_SYS_VSET

SMC_BATT_ISET

PM_SYSRST_L

SMC_PF3

SMC_P22

PM_LAN_ENABLE

54

46

49

46

46

46

46

46

46

46

46

46

46

46

46

46

46

46

46

46

46

46

46

46

46

8

46

46

46

46 46

46

Preliminary

G

D

S

IN

OUT

GND

NC

CD

GND

OUT

VDD

OUT

IN

OUT

OUT

IN

OUT

IN

BI

OUT

IN

G

D

S

G

D

S

OUT

IN

OUT

OUT

IN

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

S5 Rail PWRGD Circuit

Reports when 5V S5 and 3.3V S5 are in regulation

SMC Reset "Button" / Brownout Detect

SMC Crystal Circuit

Debug Power "Button"

System (Sleep) LED Circuit

TPS51120 PGOOD threshold 87-93% (2.87 - 3.07V)

TPS51120 PGOOD threshold 87-93% (4.35 - 4.65V)

NC

TO SMC

TO CPU

SMC FSB to 3.3V Level Shifting

LAN PWRGD Circuit

SMC AVREF Supply

10V

0.1uF

402

20%

CERM

C5000

1

2

SOT-363

2N7002DW-X-F

Q5059

6

2

1

10%

6.3V
CERM-X5R
402

0.47UF

C5020

1

2

0.01UF

10%
16V

402

CERM

C5026

1

2

6.3V

20%
X5R

603

10uF

C5025

1

2

CRITICAL

REF3133

SOT23-3

VR5020

3

1 2

MF-LF

402

5%

1/16W

0

R5095

1 2

10K

1/16W5%MF-LF

402

R5070

1 2

100K

MF-LF

5%

1/16W

402

R5071

1 2

10K

5%

MF-LF1/16W

402

R5072

1 2

402

10K

1/16W5%MF-LF

R5073

1 2

402

1/16W MF-LF

5%

100K

R5074

1 2

ONEWIRE_PU

402

1/16W5%MF-LF

2.0K

R5075

1 2

402

100K

1/16W5%MF-LF

R5076

1 2

402

10K

1/16W5%MF-LF

R5077

1 2

402

MF-LF

5%

1/16W

10K

R5078

1 2

402

MF-LF1/16W

5%

10K

R5079

1 2

402

MF-LF

5%

1/16W

10K

R5080

1 2

402

MF-LF

5%

1/16W

10K

R5083

1 2

402

MF-LF

5%

1/16W

10K

R5084

1 2

10K

4025%

MF-LF1/16W

R5085

1 2

10K

402

MF-LF

5%

1/16W

R5086

1 2

1/16W MF-LF

402

470K

5%

R5087

1 2

MF-LF

4025%

1/16W

10K

R5088

1 2

CRITICAL

5X3.2-SM

20.00MHZ

Y5010

1

2

RN5VD30A-F

SOT23-5

CRITICAL

U5000

5

3

4

1

2

1/16W5%MF-LF

402

100K

R5089

1 2

1/16W MF-LF

402

100K

5%

R5090

1 2

47 45

7

402

10K

1/16W5%MF-LF

R5082

1 2

10K

1/16W5%MF-LF

402

R5081

1 2

45

83 23 16 10

80

7

OMIT

1/10W

0

MF-LF

5%

603

R5001

1

2

OMIT

1/10W

0

MF-LF

5%

603

R5015

1

2

100K

1/16W

5%

402

MF-LF

R5045

1

2

61 45

CERM

50V

10%

0.0022UF

402

C5045

1

2

61

SOT-363-LF

MMDT3904XF

Q5060

5

3

4

3.3K

402

5%
1/16W
MF-LF

R5061

1

2

SOT-363-LF

MMDT3904XF

Q5060

2

6

1

402

MF-LF

5%

1/16W

3.3K

R5062

1 2

5%
1/16W
MF-LF
402

470

R5060

1

2

83 59 10

45

45

2N7002DW-X-F

SOT-363

Q5059

3

5

4

402

MF-LF

5%

1/16W

100K

R5091

1 2

402

1/16W MF-LF

5%

100K

R5093

1 2

402

1/16W5%MF-LF

100K

R5092

1 2

2N7002

SOT23-LF

Q5032

3

1

2

10K

1/16W5%MF-LF

402

R5096

1 2

10K

1/16W5%MF-LF

402

R5094

1 2

MF-LF

1/16W

100K

NO STUFF

402

5%

R5097

1

2

0

402

5%

MF-LF

1/16W

R5098

1 2

45 66 45 28

9

402

1K

MF-LF

5%
1/16W

R5000

1

2

80 46 45

7

SOT23-LF

2N3906

Q5030

1

3

2

1/16W

100

MF-LF

5%

402

R5030

1

2

1/16W
MF-LF

402

2.21K

1%

R5031

1

2

45

MF-LF

402

1/16W

1%

9.53K

R5032

1

2

CERM

402

5%

50V

15pF

C5010

1 2

50V

CERM

402

15pF

5%

C5011

1 2

402

CERM

16V

0.01UF

10%

C5001

1

2

353S1278353S1381

Intersil ISL60002-33

ALL

SMC Support

SYNC_MASTER=M75_MLB

50

109

16

051-7261

SYNC_DATE=04/02/2007

SMC_P45

MAKE_BASE=TRUE

SUS_CLK_SB

SMC_P81
SMC_PF0
SMC_PF1

SMC_EXCARD_OC_L

=PP3V3_S5_SMC

SMC_PH4

SMC_BATT_TRICKLE_EN_L

SMC_ADAPTER_EN

SMC_MANUAL_RST_L

SMC_EXTAL

=PP3V3_S0_SMC

SMC_P67

SMC_PG0

SMC_THRMTRIP

PM_THRMTRIP_L

SMC_PROCHOT

CPU_PROCHOT_L_R

CPU_PROCHOT_L

CPU_PROCHOT_BUF

=PP1V05_S0_SMC_LS

SMC_P44

MAKE_BASE=TRUE

TP_SMC_P44

SMC_P43

MAKE_BASE=TRUE

TP_SMC_P43

SMC_P27

TP_SMC_P27

MAKE_BASE=TRUE

SMC_P26

TP_SMC_P26

MAKE_BASE=TRUE

SMC_P23

TP_SMC_P23

MAKE_BASE=TRUE

SMC_P22

MAKE_BASE=TRUE

TP_SMC_P22

SMC_P21

TP_SMC_P21

MAKE_BASE=TRUE

SMC_GFX_THROTTLE_L

TP_SMC_GFX_THROTTLE_L

MAKE_BASE=TRUE

SMC_GFX_OVERTEMP_L

TP_SMC_GFX_OVERTEMP_L

MAKE_BASE=TRUE

SMC_FAN_3_CTL

TP_SMC_FAN_3_CTL

MAKE_BASE=TRUE

SMC_FAN_3_TACH

TP_SMC_FAN_3_TACH

MAKE_BASE=TRUE

SMC_FAN_2_TACH

TP_SMC_FAN_2_TACH

MAKE_BASE=TRUE

SMC_FAN_2_CTL

TP_SMC_FAN_2_CTL

MAKE_BASE=TRUE

SMC_XTAL

SYS_LED_ILIM

=PP5V_S3_SYSLED

SYS_LED_ANODE

SYS_LED_L_VDIV

SMC_RESET_L

VOLTAGE=3.3V

PP3V3_S5_AVREF_SMC

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PM_SUS_STAT_L

SMC_EXCARD_CP

SMC_BC_ACOK

PM_SLP_S5_L

=P3V3S5_PGOOD

=P5VS5_PGOOD

MAKE_BASE=TRUE

RSMRST_PWRGD

EXCARD_OC_L

SMC_SYS_LED

SYS_LED_L

SMC_CASE_OPEN

SMC_PA0
SMC_PA1
SMC_PB0

SMC_ONOFF_L

SMC_TX_L

SMC_FWE

SMC_LID

SMC_RX_L

SYS_ONEWIRE
SMC_BS_ALRT_L

SMC_TDO

SMC_TMS

SMC_TDI
SMC_TCK

SMC_PF3

MAKE_BASE=TRUE

TP_SMC_BATT_VSET

SMC_BATT_VSET

TP_SMC_SYS_VSET

MAKE_BASE=TRUE

SMC_SYS_VSET

SMC_P20

MAKE_BASE=TRUE

TP_SMC_P20

TP_SMC_P14

MAKE_BASE=TRUE

SMC_P14

=PP3V3_S0_SMC

SMC_PROCHOT_3_3_L

=PP3V3_S5_SMC

=PPVIN_S5_SMCVREF

ALL_SYS_PWRGD

SMC_ONOFF_L

SMC_SUS_CLK

PM_LAN_PWRGD

TP_SMC_P62

MAKE_BASE=TRUE

SMC_P62

TP_SMC_P46

MAKE_BASE=TRUE

SMC_P46

TP_SMC_P64

MAKE_BASE=TRUE

SMC_P64

MAKE_BASE=TRUE

TP_SMC_P63

SMC_P63

MAKE_BASE=TRUE

TP_SMC_P81
TP_SMC_PF0

MAKE_BASE=TRUE

TP_SMC_PF1

MAKE_BASE=TRUE

MAKE_BASE=TRUE

SMC_ENRGYSTR_LDO_EN

SMC_BATT_CHG_EN

=PP3V3_S5_S5PWRGD

GND_SMC_AVSS

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V

57

47

67

80

47

47

46

45

45

57

45

46

45

45

57

47

47

47

47

46

54

45

67

40

46

25

45

45

25

34

45

43

80

43

45

45

45

45

45

45

46 45

67

49

45

25

45

45

45

45

8

45

45

36

45

8

45

45

8

45

45

45

45

45

45

45

45

45

45

45

45

45

8

45

7

34

34

7

24

45

45

45

45

7

7

45

45

7

34

7

7

7

7

7

45

45

45

45

45

8 8

8

45

45

45

45

45

45

8

45

Preliminary

BI

BI

IN

IN

OUT
OUT
OUT

OUT

OUT

IN

IN

BI

BI

OUT
OUT
OUT

OUT

IN

IN

OUT

IN

OUT

BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

516S0394

LPC+ Connector

FWH_INIT_L Generation

45 23

7

45 25

7

88 30

7

46 45 25

7

45 25

7

24

7

46 45

7

45

7

45

7

28

7

45 23

7

45 23

7

45 23

7

46 45

7

46 45

7

45

7

25

7

LPCPLUS

SOT-363-LF

MMDT3904XF

Q5190

5

3

4

MMDT3904XF

SOT-363-LF

PLACEMENT_NOTE=Place Q5190 close to R5190

LPCPLUS

Q5190

2

6

1

402

5%
1/16W
MF-LF

LPCPLUS

330

R5192

1

2

1.3K

402

MF-LF

1/16W

5%

LPCPLUS

R5191

1

2

PLACEMENT_NOTE=Place R5190 to minimize CPU_INIT_L stub

1/16W

5%

MF-LF

402

330

LPCPLUS

R5190

1 2

83 23 10

46 45 43

7

46 45 43

7

46 45

7

46 45

7

QT500306-L021-9F

M-ST-SM

LPCPLUS

CRITICAL

J5100

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

31

32

33

34

4

5

6

7

8

9

45 23

7

SYNC_MASTER=M75_MLB

16

109

51

051-7261

LPC+ Debug Connector

SYNC_DATE=12/04/2006

CPU_INIT_R_L

=PP3V3_S0_LPCPLUS

CPU_INIT_L

SMC_TX_L

SMC_MD1

SMC_TDO

SMC_TRST_L

DEBUG_RESET_L

LINDACARD_GPIO

SMC_RX_L

SMC_NMI

SMC_RESET_L

SMC_TCK

SMC_TDI

PM_SUS_STAT_L

INT_SERIRQ

LPC_AD<3>

LPC_AD<2>

PCI_CLK33M_LPCPLUS

FWH_INIT_L

CPU_INIT_LS3V3

SMC_TMS

BOOT_LPC_SPI_L

PM_CLKRUN_L

LPC_FRAME_L

LPC_AD<1>

LPC_AD<0>

=PP5V_S0_LPCPLUS

=PP3V3_S5_LPCPLUS

8

8

8

7

7

7

Preliminary

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(MASTER)

(Address determined by ARP)

Left I/O SMBus Connections:

SMC

(Write: 0xA0 Read: 0xA1)

(Write: 0xD2 Read: 0xD3)

ExpressCard Slot

U2300

(MASTER?)

ICH8-M

(See Table)

Left I/O

J3400

ICH8-M

U2300

(MASTER)

Battery

TMP401: U5550

(MASTER)

U4900

SO-DIMM "A"

U4900

SMC

SMC

(MASTER)

J3100

J3200

CY28545-5: U2900

(Write: 0xA4 Read: 0xA5)

ICH8-M ME SMBus Connections

Clock Chip

U5900

SMS

SO-DIMM "B"

ICH8-M SMBus Connections

J6950

J3400

SMC "Management" SMBus Connections

GPU Temp (Ext)

SMC

(Write: 0x98 Read: 0x99)

U4900

Remote Temps

EMC1045-5: U5500

(Write: 0x98 Read: 0x99)

Left I/O Board

J9600

Top-Case

NOTE: SMC RMT bus remains powered and may be active in S3 state

SMC "A" SMBus Connections

TMP275

(Write: 0x9E Read: 0x9F)

Left I/O SMBus Connections:

M35B - TMP106

(See Table)

(Write: 0x90 Read: 0x91)

Left ALS - TMP106

(Write: 0x92 Read: 0x93)

(Write: 0x9E Read: 0x9F)

G84M: U8000

GPU Temp (Int)

(MASTER)

U4900

TMP106:U5750

Battery Charger

(Write: 0x92 Read: 0x93)

EMC1043-5: U5570

CPU Temp

(Write: 0x98 Read: 0x99)

SMC "B" SMBus Connections

(MASTER)

U4900

SMC

(Write: 0x30 Read: 0x31)

The bus formerly known as "Battery B"

(Write: 0x16 Read: 0x17)

SMC "Battery A" SMBus Connections

SMC "0" SMBus Connections

4.7K

402

MF-LF

5%

1/16W

R5200

1

2

4.7K

402

MF-LF

1/16W

5%

R5201

1

2

1/16W

402

5%

MF-LF

4.7K

R5280

1

2

5%
1/16W
MF-LF
402

4.7K

R5281

1

2

MF-LF
402

1/16W

5%

4.7K

R5291

1

2

1/16W

4.7K

402

5%

MF-LF

R5290

1

2

5%
MF-LF

402

1/16W

3.3K

R5261

1

2

5%

MF-LF

1/16W

402

3.3K

R5260

1

2

MF-LF

1/16W

4.7K

402

5%

R5271

1

2

MF-LF

4.7K

1/16W

5%

402

R5270

1

2

MF-LF

5%

4.7K

1/16W
402

R5251

1

2

1/16W

402

5%

MF-LF

4.7K

R5250

1

2

402

MF-LF

1/16W

5%

10K

R5231

1

2

MF-LF

1/16W

402

5%

10K

R5230

1

2

SMBus Connections

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

16

52

109

051-7261

SMB_B_S0_DATA

SMB_B_S0_CLK

=I2C_CPUTHMSNS_SDA

=I2C_CPUTHMSNS_SCL

=SMBUS_TMPSNSR_SDA

=SMBUS_TMPSNSR_SCL

SMBUS_SMC_B_S0_SDA

MAKE_BASE=TRUE

MAKE_BASE=TRUE

SMBUS_SMC_B_S0_SCL

=PP3V3_S0_SMBUS_SMC_B_S0

=GPU_I2CS_SCL
=GPU_I2CS_SDA

SMBUS_SMC_0_S0_SDA

MAKE_BASE=TRUE

SMBUS_SMC_MGMT_SCL

MAKE_BASE=TRUE

SMBUS_SMC_A_S3_SCL

MAKE_BASE=TRUE

SMBUS_SMC_A_S3_SDA

MAKE_BASE=TRUE

=SMBUS_REMTHMSNS_SDA

=SMBUS_REMTHMSNS_SCL

=PP3V3_GPU_SMBUS_SMC_0_S0

SMB_A_S3_CLK
SMB_A_S3_DATA

=SMBUS_GPUTHMSNS_SCL
=SMBUS_GPUTHMSNS_SDA

=SMBUS_LIO_SMC_SCL
=SMBUS_LIO_SMC_SDA

=SMBUS_BATT_SCL

SMBUS_SMC_0_S0_SCL

MAKE_BASE=TRUE

=PP3V42_G3H_SMBUS_SMC_BSA

SMB_0_S0_DATA

=I2C_TOPCASE_SCL

SMB_0_S0_CLK

=PP3V3_S0_SMBUS_SB

=I2C_SODIMMB_SCL

=SMBUS_CK505_SDA

SMB_DATA

SMB_CLK

SMB_BSA_CLK
SMB_BSA_DATA

SMB_MGMT_CLK
SMB_MGMT_DATA

=SMBUS_BATT_SDA

=I2C_SMS_SDA

=I2C_SMS_SCL

=PP3V3_S3_SMBUS_SMC_MGMT

=PP3V3_S5_SMBUS_SB_ME

SMBUS_SB_ME_SCL

MAKE_BASE=TRUE

SMBUS_SB_ME_SDA

MAKE_BASE=TRUE

SMB_ME_DATA

SMB_ME_CLK

=SMBUS_LIO_SB_SDA

SMBUS_SMC_BSA_SCL

MAKE_BASE=TRUE

SMBUS_SMC_BSA_SDA

MAKE_BASE=TRUE

=I2C_TOPCASE_SDA

=PP3V3_S3_SMBUS_SMC_A_S3

SMBUS_SMC_MGMT_SDA

MAKE_BASE=TRUE

=SMBUS_CK505_SCL

=SMBUS_LIO_SB_SCL

=I2C_SODIMMB_SDA

=I2C_SODIMMA_SCL
=I2C_SODIMMA_SDA

MAKE_BASE=TRUE

SMBUS_SB_SCL

MAKE_BASE=TRUE

SMBUS_SB_SDA

57

86

86

57

86

86

45

45

51

51

53

53

88

88

8

75

75

88

88

88

88

51

51

8

45

45

51

51

34

34

7

88

8

45

80 45

8

32

29

25

25

45

45

45

45

7

55

55

8

8

25

25

34

88

88

80

8

88

29

34

32

31

31

Preliminary

IN

OUT

N-CHN

S

D

G

P-CHN

G

D

S

D

S

G

IN

D

S

G

ININ

IN

OUT

OUT

OUT

IN

OUT

IN

OUT

IN IN

OUT

OUTOUT

OUT

IN

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Enables PBUS VSense divider when high.

S0/GPU 1.25V Current Sense Filter

Place RC close to SMCPlace RC close to SMC

NB 1.8V Current Sense Filter

PBUS Voltage Sense & Filter

Place RC close to SMC

Rthevanin = 4573 ohms

Place RC close to SMC

Battery (PBUS) Current Sense Filter

Place RC close to SMC

Place RC close to SMC

DCIN Current Sense Filter

Place RC close to SMC

CPU Current Sense Filter

Place RC close to SMC

Switches in fixed load on power supplies to calibrate current sense circuits

Current Sense Calibration Circuit

Place RC close to SMC

GPU Current Sense Filter

Place RC close to SMC

NB Core Current Sense Filter

GPU Voltage Sense / Filter

CPU Voltage Sense / Filter

Place RC close to SMC

Place short near U8000 center

Place short near U1000 center

NB GFX Current Sense Filter

45

7

402

MF-LF

1/16W

5%

100K

R5327

1

2

5%
1/16W
MF-LF

402

100K

R5315

1

2

45

27.4K

1%
1/16W
MF-LF

402

R5385

1

2

6.3V

0.22UF

402

X5R

20%

C5385

1

2

5.49K

402

MF-LF

1/16W

1%

R5386

1

2

FDG6332C_NL

SC70-6

Q5315

6

2

1

FDG6332C_NL

SC70-6

Q5315

3

5

4

MICROFET3X3

CRITICAL

FDM6296

Q5320

5

4

1 2 3

4.53K

402

MF-LF

1%

1/16W

ISL9504B

R5331

1 2

66 59

1.00

1%

1/4W

MF-LF

1206

R5322

1

2

CRITICAL

FDM6296

MICROFET3X3

Q5322

5

4

1 2 3

50 50

5%
1/16W
MF-LF

402

100K

R5316

1

2

SC70-5

SN74AHCT1G125DCKRE4

U5327

2

3 1

5

4

1K

402

5%

MF-LF

1/16W

R5328

12

402

CERM

10V

20%

0.1UF

C5327

1 2

1/16W

4.53K

402

MF-LF

1%

R5365

1 2

50

20%
X5R

402

0.22UF

6.3V

C5365

1

2

45

45

402

X5R

6.3V

20%

0.22UF

C5359

1

2

4.53K

402

MF-LF

1%

1/16W

R5359

1 2

45

1%

MF-LF

402

4.53K

1/16W

R5370

1 2

6.3V

0.22UF

402

X5R

20%

C5370

1

2

50 45

0.22UF

6.3V
X5R

20%

402

C5375

1

2

4.53K

MF-LF

1/16W

1%

402

R5375

1 2

76

45

20%
X5R

0.22UF

6.3V
402

C5380

1

2

1%

MF-LF

402

4.53K

1/16W

R5380

1 2

53 53

1%
1/16W
MF-LF

402

4.53K

R5390

1 2

20%
X5R

402

0.22UF

6.3V

C5390

1

2

45

45

20%
X5R

402

0.22UF

6.3V

C5340

1

2

1/16W

1%
MF-LF

402

4.53K

R5340

1 2

45

X5R
402

6.3V

20%

0.22UF

C5335

1

2

4.53K

1/16W

1%

MF-LF

402

R5335

1 2

45

6.3V
X5R

20%

402

0.22UF

C5330

1

2

ISL9504A

402

4.53K

MF-LF

1%

1/16W

R5330

1 2

50

SM

XW5359

1 2

45

1/16W
MF-LF

4.53K

1%

402

R5309

1 2

0.22UF

20%

6.3V
X5R
402

C5309

1

2

SM

XW5309

1 2

1.00

1%

1/4W

MF-LF

1206

R5320

1

2

SYNC_DATE=03/19/2007

SYNC_MASTER=M75_MLB

Current & Voltage Sensing

051-7261

16

109

53

ISENSE_CAL_EN_LS5V

GPUCORE_ISENSE_CAL

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.50 mm

=PPVCORE_GPU_REG

SMC_NBGFXCORE_ISENSE

MAKE_BASE=TRUE

SMC_ANALOG_ID

NBGFXCORE_IOUT

NBCORE_IOUT

SMC_NBGFXCORE_ISENSE

GND_SMC_AVSS

SMC_NB_CORE_ISENSE

GND_SMC_AVSS

P1V8_S3_IOUT

=PPVCORE_S0_CPU

GPUVCORE_IOUT

=PPVCORE_S0_CPU_REG

GND_SMC_AVSS

SMC_GPU_ISENSE

LIO_DCIN_ISENSE

SMC_NB_1V8_ISENSE

SMC_DCIN_ISENSE

GND_SMC_AVSS

GND_SMC_AVSS GND_SMC_AVSS

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.50 mm

CPUVCORE_ISENSE_CAL

SMC_BATT_ISENSE

GND_SMC_AVSS

GND_SMC_AVSS

LIO_BATT_ISENSE

GND_SMC_AVSS

=PPVCORE_GPU_REG

SMC_CPU_VSENSE

CPUVSENSE_IN

SMC_GPU_VSENSE

GPUVSENSE_IN

PPBUS_G3H

GND_SMC_AVSS

PPBUS_G3H_VSENSE

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.20 mm

GND_SMC_AVSS

P1V25_S0GPU_IOUT

SMC_NB_1V25_ISENSE

SMC_PBUS_VSENSE

PBUSVSENS_EN_DIV

=PBUSVSENS_EN

PBUSVSENS_EN_L

CPUVCORE_IOUT

SMC_CPU_ISENSE

IMVP6_IMON

=PP5V_S0_ISENSECAL

ISENSE_CAL_EN_LS5V_R

ISENSE_CAL_EN

76

54

54

54

54

54 54 54

54

54

76

54

54

49

49

49

12

59

49

49

49 49 49

49

49

49

49

49

8

46

46

11

8

46

46

46 46 46

46

46

8

46

46

8

7

49

49

45

45

8

7

45

45

45 45 45

45

45

7

8

45

45

66

7

Preliminary

OUT

R1-

R1+

R2

V-

V+

+

IN

IN

OUT

R1-

R1+

R2

V-

V+

+

OUT

IN

IN

OUT

R1-

R1+

R2

V-

V+

+

OUT

R1-

R1+

R2

V-

V+

+

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Gain = 100:1

Gain = 100:1

Gain = 100:1

Gain = 165:1

402

MF-LF

1/16W

1%

2.0K

R5441

1

2

SM

XW5425

1

2

SM

XW5426

1

2

SM

XW5445

1

2

SM

XW5446

1

2

SM

XW5435

1

2

SM

XW5436

1

2

10

1/16W
MF-LF

1%

402

R5410

1 2

10%
16V
X5R
402

0.1UF

C5410

1

2

49

0.001UF

CERM

402

10%
50V

C5412

1

2

402

1%
1/16W
MF-LF

100K

R5412

1

2

CRITICAL

INA326EA-250

MSOP

U5410

3

2

6

1

8

5

4

7

MF-LF
402

1/16W

1%

2.0K

R5411

1

2

60

60

CRITICAL

0.002

1206

1/4W

1%

MF-LF

R5445

1 2

470PF

50V

10%

402

CERM

C5400

1 2

1/16W

1%

402

MF-LF

1M

R5400

1 2

10V

20%

402

CERM

0.1UF

C5401

1

2

40.2K

1/16W

402

1%

MF-LF

R5402

1 2

10V

20%

CERM

402

0.1UF

NO STUFF

C5403

1

2

CRITICAL

SOT23-5

LMV2011MF

U5400

3

4

1

5

2

1/16W

1%

402

MF-LF

1M

R5404

1 2

470PF

50V

10%

402

CERM

C5405

12

1/16W

402

40.2K

1%

MF-LF

R5403

1 2

402

CERM

NO STUFF

10V

20%

0.1UF

C5404

1

2

49

402

1%

MF-LF

1/16W

10

R5420

1 2

0.1UF

402

X5R

16V

10%

C5420

1

2

50V

10%
402

CERM

0.001UF

C5422

1

2

MSOP

INA326EA-250

CRITICAL

U5420

3

2

6

1

8

5

4

7

MF-LF

1/16W

1%

100K

402

R5422

1

2

22UF

20%

6.3V
CERM-X5R
805-3

C5426

1

2

22UF

20%

6.3V
CERM-X5R
805-3

C5425

1

2

1/16W

1%

402

MF-LF

2.0K

R5421

1

2

MF-LF

1%

1/4W
1206

0.002

CRITICAL

R5425

1 2

49

59

59

402

1%

MF-LF

1/16W

10

R5430

1 2

49

50V

10%

402

CERM

0.001UF

C5432

1

2

0.002

1/4W

MF-LF

1%

1206

CRITICAL

R5435

1 2

0.1UF

402

X5R

16V

10%

C5430

1

2

402

1%
1/16W
MF-LF

165K

R5432

1

2

22UF

20%

6.3V
CERM-X5R
805-3

C5436

1

2

CRITICAL

MSOP

INA326EA-250

U5430

3

2

6

1

8

5

4

7

22UF

20%

6.3V
CERM-X5R
805-3

C5435

1

2

1%
1/16W

402

MF-LF

2.0K

R5431

1

2

MF-LF

10

1%

402

1/16W

R5440

1 2

49

10%
402

CERM

50V

0.001UF

C5442

1

2

0.1UF

402

X5R

16V

10%

C5440

1

2

CERM-X5R

22UF

20%

6.3V
805-3

C5446

1

2

CERM-X5R

22UF

20%

6.3V
805-3

C5445

1

2

MSOP

INA326EA-250

CRITICAL

U5440

3

2

6

1

8

5

4

7

MF-LF

1/16W

1%

402

100K

R5442

1

2

051-7261

16

109

54

Current Sensing

SYNC_MASTER=M75_MLB

SYNC_DATE=03/19/2007

=PP3V3_S0_NBGFXCOREISNS

P1V8ISNS_R1_N

P1V8ISNS_N

=PP3V3_S0_CPUCOREISNS

CPUVCORE_IOUT

CPUCOREISNS_P

IMVP6_DROOP

P1V25ISNS_R1_N

PP3V3_S3_P1V25ISNS_VCC

MIN_NECK_WIDTH=0.2mm
VOLTAGE=3.3V

MIN_LINE_WIDTH=0.25mm

P1V25ISNS_R2

P1V25_S0GPU_IOUT

=PP3V3_S3_P1V25ISNS

P1V25ISNS_N

=PP1V25_ENET_ISNS

=PP1V25_ENET_ISNS_R

P1V8ISNS_R1_P

PP3V3_S3_P1V8ISNS_VCC

MIN_NECK_WIDTH=0.2mm

MIN_LINE_WIDTH=0.25mm
VOLTAGE=3.3V

P1V8ISNS_R2

NBCOREISNS_R1_N

NBCOREISNS_R1_P

NBCOREISNS_P

NBCOREISNS_N

=PPVCORE_S0_NBCOREISNS

NBCOREISNS_R2

=PP3V3_S0_NBCOREISNS

P1V8_S3_IOUT

NBGFXISNS_R1_P

PP3V3_S0_NBGFXISNS_VCC

MIN_LINE_WIDTH=0.25mm
VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2mm

NBGFXISNS_R2

NBGFXISNS_R1_N

NBGFXCORE_IOUT

GFXIMVP6_PHASE_VSUM

GFXIMVP6_VO

P1V25ISNS_R1_P

P1V25ISNS_P

PP3V3_S0_NBCOREISNS_VCC

MIN_NECK_WIDTH=0.2mm
VOLTAGE=3.3V

MIN_LINE_WIDTH=0.25mm

=PPVCORE_S0_NB_R

=PP3V3_S3_P1V8ISNS

NBCORE_IOUT

P1V8ISNS_P

CPUCOREISNS_N

IMVP6_VO

=PP1V8_S3_ISNS_R

=PP1V8_S3_ISNS

8

8

8

8 8

91

8

8

91

8

8

91

8 8

Preliminary

BI
BI
BI
BI

GND

VDD

SDATA

SCLK

THM*

ALERT*/

D+
D-

THM2*

BI

BI

BI

BI

OUT

IN

VDD

SMDATA

SMCLK

GND

DP1
DN1

DP2
DN2

VDD

SMDATA

SMCLK

GND

DP1
DN1

DP2
DN2

BI
BI

OUT

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Placement note:

to IC pins as possible

Keep 2 caps as close

(TG0H)

Place near GPU

GPU/Heat Pipe & Bottom Case Skin Thermal Sensor

Placement note:

518S0487

(TC0D)

GPU Die Thermal Sensor

Placement note:

Keep 2 caps as close to
connectors as possible

Place on left side of fan cutout

518S0487

(Th2H)

(TG0T)

NB Thermal Diodes Not Used

(Reserved for CPU heatpipe sensor)

CPU T-Diode Thermal Sensor

(TG0P)

(Th1H)

Place U5550 near GPU

Placement note:

(Th0H)

(TC0P)

518S0487

Placement note:

20

20

20

20

0.1uF

CERM
402

20%
10V

C5500

1

2

47

MF-LF

5%

1/16W

402

R5500

1 2

NO STUFF

402

CERM

50V

18PF

5%

C5510

1

2

NO STUFF

5%

18PF

CERM
402

50V

C5520

1

2

BM02B-ACHKS-GAN-TF-LF-SN-M

CRITICAL

M-RT-SM

J5510

3

4

1
2

M-RT-SM

CRITICAL

BM02B-ACHKS-GAN-TF-LF-SN-M

J5520

3

4

1
2

GPU_TMP401

10K

5%
MF-LF

1/16W
402

R5552

1

2

MF-LF

402

5%

10K

1/16W

GPU_TMP401

R5551

1

2

GPU_TMP401

16V

10%

402

X5R

0.1UF

C5550

1

2

GPU_TMP401

0.001UF

10%

402

CERM

50V

C5560

1

2

GPU_TMP401

499

1%
1/16W
MF-LF

402

R5560

1 2

GPU_TMP401

402

MF-LF

1/16W

1%

499

R5561

1 2

GPU_TMP401

MSOP

TMP401

CRITICAL

U5550

6

3

2

5

8
7

4

1

CRITICAL

BM02B-ACHKS-GAN-TF-LF-SN-M

M-RT-SM

J5590

3

4

1
2

48

48

48

48

91 74

74

10%
50V

CERM

0.0022uF

402

C5511

1

2

CRITICAL

EMC1043-5

MSOP

U5500

2

4

1

3

5

8
7

6

402

0.0022uF

CERM

50V

10%

C5521

1

2

CRITICAL

EMC1043-5

MSOP

U5570

2

4

1

3

5

8
7

6

48

48

402

CERM

20%

0.1uF

10V

C5570

1

2

402

47

1/16W

5%

MF-LF

R5570

1 2

402

CERM

50V

10%

0.0022uF

C5590

1

2

402

CERM

50V

10%

470PF

C5580

1

2

91 10

10

SYNC_MASTER=M75_MLB

051-7261

16

109

55

Thermal Sensors

SYNC_DATE=03/19/2007

=NB_TDB_FORCE
=NB_TDB_SENSE

=NB_TDE_FORCE

=NB_TDE_SENSE

=SMBUS_GPUTHMSNS_SCL
=SMBUS_GPUTHMSNS_SDA

=PP3V3_S3_REMTHMSNS

=I2C_CPUTHMSNS_SCL
=I2C_CPUTHMSNS_SDA

CPU_THERMD_N

CPU_THERMD_P

PP3V3_S0_CPUTHMSNS_R

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V

CPUTHMSNS_D2_P

GPUTHMSNS_ALERT_L
GPUTHMSNS_THM_L

=PP3V3_S0_CPUTHMSNS

GPUTHMSNS_D_P

GPU_TDIODE_N

GPUTHMSNS_D_N

GPU_TDIODE_P

=PP3V3_S0_GPUTHMSNS

CPUTHMSNS_D2_N

=GND_CHASSIS_J5590

RSFSTHMSNS_D_P

RSFSTHMSNS_D_N

HSTHMSNS_D_N

HSTHMSNS_D_P

PP3V3_S3_REMTHMSNS_R

MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V

=SMBUS_REMTHMSNS_SCL
=SMBUS_REMTHMSNS_SDA

91

91

91

8

7

8

91

8

7

9

7

7

7

7

Preliminary

G

S D

G

S D

IN

OUT OUT

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

518S0369

Right Fan

Left Fan

518S0369

MF-LF

5%

402

47K

1/16W

R5650

1

2

47K

402

MF-LF

5%

1/16W

R5655

1 2

1/16W

5%

47K

MF-LF

402

R5660

1

2

5%
1/16W
MF-LF

47K

402

R5665

1 2

100K

1/16W

5%

MF-LF

402

R5651

1

2

SOT-363

2N7002DW-X-F

Q5660

3

5

4

1/16W

402

MF-LF

5%

100K

R5661

1

2

2N7002DW-X-F

SOT-363

Q5660

6

2

1

M-RT-SM

SM04B-ACH

CRITICAL

J5650

5

6

1
2
3
4

M-RT-SM

SM04B-ACH

CRITICAL

J5660

5

6

1
2
3
4

45

45 45

45

SYNC_DATE=12/04/2006

SYNC_MASTER=M75_MLB

56

109

051-7261

16

Fan Connectors

SMC_FAN_1_CTL

SMC_FAN_1_TACH

SMC_FAN_0_CTL

SMC_FAN_0_TACH

=PP3V3_S0_FAN_LT

FAN_RT_PWM

=PP5V_S0_FAN_RT

FAN_RT_TACH

=PP3V3_S0_FAN_RT

FAN_LT_PWM

FAN_LT_TACH

=PP5V_S0_FAN_LT

8

8

7

8

7

8

7

7

7

Preliminary

GND

OUT

VIN+ VIN-

V+

ALERT

A0

SCL

SDA

GNDS

V+

GND

OUT

VIN+ VIN-

V+

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Temp Sensor has address x92,x93

Placement Note:

Place near R8308

Place sensor on

DCIn Current Sense

Q8301 and Q8302

bottom side
near L8300 and

Place near R8307

Placement Note:

Battery Charger Thermal Sensor

(Tm0P) R:0x93,W:0x92

Battery Current Sense

402

5%

0

MF-LF

1/16W

R5751

1

2

NO STUFF

5%
1/16W
MF-LF
402

0

R5750

1

2

CRITICAL

SOT23-5

INA193

U5705

2

15

3 4

10%

6.3V
CERM

1uF

402

C5715

1

2

6.3V

10%
CERM

402

1uF

C5705

1

2

10V
CERM

0.1uF

20%

402

C5750

1

2

WCSP-6

CRITICAL

TMP106

U5750

C2

B2

A2

B1

A1

C1

CRITICAL

SOT23-5

INA193

U5715

2

15

3 4

SYNC_DATE=(MASTER)

57

109

SYNC_MASTER=(MASTER)

Current & Thermal Sensors

051-7261

16

CHGR_CSO_R_P

=PP3V3_S0_TMPSNSR

=PP3V3_S0_PBATTISENS

CHGR_CSI_R_N

=PP3V3_S0_PDCISENS

CHGR_CSI_P

LIO_DCIN_ISENSE

=SMBUS_TMPSNSR_SDA

=SMBUS_TMPSNSR_SCL

TMPSNSR_A0

LIO_BATT_ISENSE

CHGR_CSO_R_N

67

8

8

67

8

67

49

48

48

49

67

Preliminary

V+

V-

G

D

S

IN

OUT

OUT

IN

IN

OUT

IN

THRML

CAP

SW

LED

VIN

CTRL

PAD

GND

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Right ALS Circuit

RTALS_OP_IN and RTALS_OP_COMP need to be matched

Keyboard LED Driver

Left ALS circuit has 1K series-R

Left ALS Filter

WF: This circuit does not use return, can tie cathode to GND on topcase flex

MAX4236EUTT

SOT23-6-LF

CRITICAL

U5805

3

4

1

5

6

2

CERM

402

20%
10V

0.1UF

C5805

1

2

120K

MF-LF
402

5%
1/16W

R5806

1

2

0.22UF

X5R
402

20%

6.3V

C5806

1

2

15.0K

MF-LF
402

1%
1/16W

R5807

1

2

1K

MF-LF

402

1%

1/16W

R5808

1

2

MF-LF

402

1%

1/16W

1K

R5801

1 2

BS520EOF

TH

CRITICAL

PD5800

1

2

5.1M

MF-LF

402

5%

1/16W

R5800

1

2

0.01UF

CERM

20%
16V

402

C5800

1

2

2N7002

SOT23-LF

Q5808

3

1

2

45 34

7

45

4.53K

MF-LF

402

1%

1/16W

R5810

1 2

0.22UF

X5R

20%

6.3V
402

C5810

1

2

45

6.3V

20%

402

X5R

0.22UF

C5830

1

2

1/16W

1%

402

MF-LF

3.48K

R5830

1 2

34

7

CRITICAL

10UH-0.58A

DE2812C-SM

L5850

1 2

10V

1UF

20%

603

CERM

C5850

1

2

MF-LF

5%

1/16W

10K

402

R5852

1

2

45

402

1/16W

10

1%
MF-LF

R5855

1

2

80

X5R

1UF

25V

10%

603

C5855

1

2

80

CRITICAL

LT3491

DFN

U5850

4

6

2

5

3

7

1

ALS Support

58

109

051-7261

16

SYNC_MASTER=M75_MLB

SYNC_DATE=12/04/2006

KBDLED_CAP

=PP5V_S0_KBDLED

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.3 MM

KBDLED_SW

LTALS_OUT

ALS_GAIN

RTALS_OP_COMP

=PP3V3_S3_RTALS

ALS_RT_OUT

ALS_RIGHT

GND_SMC_AVSS

RTALS_OP_IN

RTALS_PHOTODIODE

RTALS_GAIN_L

GND_SMC_AVSS

ALS_LEFT

KBDLED_ANODE

SMC_SYS_KBDLED

KBDLED_RETURN

54

54

49

49

46

46

8

8

45

45

Preliminary

CS*

SCL/SCLK

ADDR/SDI

MOT_ENABLE

ENABLE

VDD

X
Y
Z

FF/MOT

SDA/SDO

GND

IN

OUT
OUT
OUT

OUT

BI

BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

placed on board bottom-side:

Top-through View

placed on board top-side:

Desired orientation when

+Y+Y

+X

1

Package Top

+Z (dn)

1

+X

Alias SCL/SDA to GND if using analog outputs only

I2C addresses:

ADDR high => 0x32, 0x33

ADDR low => 0x30, 0x31

+Z (up)

Desired orientation when

APN:338S0354

0.1uF

CERM
402

20%
10V

C5900

1

2

402

X5R

16V

10%

0.033UF

C5902

1

2

402

X5R

16V

10%

0.033UF

C5903

1

2

CRITICAL

LGA

KXPS5-2050

U5900

3

2

6

11

10

12

5

4

11314

7
8
9

10K

MF-LF

402

5%

1/16W

R5900

1

2

45

45

45

45

1/16W

5%

402

MF-LF

0

SMS_MOT_EN

R5901

1

2

0

5%
1/16W
MF-LF
402

SMS_MOT_DIS

R5902

1

2

5%

1/16W

MF-LF

402

100K

R5903

1

2

9

48

48

402

0.033UF

16V

10%
X5R

C5901

1

2

59

109

16

051-7261

Sudden Motion Sensor (SMS)

SYNC_MASTER=M75_MLB

SYNC_DATE=12/04/2006

SMS_X_AXIS

=I2C_SMS_SDA

SMS_Y_AXIS

=I2C_SMS_SCL

=PP3V3_S3_SMS

SMC_SMS_INT

SMS_MOT_EN

SMS_Z_AXIS

SMS_ONOFF_L

8

Preliminary

SO

VDD

CE*

SCK

VSS

HOLD*

SI

WP*

OUT

IN

IN IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

CERM

20%
10V

0.1UF

402

C6100

1

2

402

1/16W

5%

3.3K

MF-LF

R6101

1

2

402

1/16W

5%

MF-LF

3.3K

R6100

1

2

PLACEMENT_NOTE=Place R6114 within 12.7mm of U6100

15

MF-LF

5%

1/16W

402

R6114

1 2

OMIT

SST25VF016B

SOI

16MBIT

CRITICAL

U6100

1

7

6

5

2

8

4

3

86 24

MF-LF

5%

1/16W

15

402

PLACEMENT_NOTE=Place R6190 within 12.7mm of U2300

R6190

1 2

402

MF-LF

5%

1/16W

15

PLACEMENT_NOTE=Place R6191 within 12.7mm of U2300

R6191

1 2

86 24

86 24

PLACEMENT_NOTE=Place R6193 within 12.7mm of U2300

MF-LF

5%

1/16W

15

402

R6193

1 2

86 24

SYNC_MASTER=T9_NOME

SYNC_DATE=01/25/2007

051-7261

16

109

61

SPI BootROM

=PP3V3_S5_ROM

SPI_SI_R

SPI_SO

SPI_HOLD_L

SPI_A_SI_R

SPI_WP_L

SPI_A_SO_R

SPI_SCLK

SPI_CE_L<0>

SPI_SCLK_R

SPI_CE_R_L<0>

8

86

86

86

86

Preliminary

BI

OUT

V-

V+

S3
S2

D1

D2

D3

D4

GATE

S1

G

D

S

BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

518S0457

<R2a>

Vref = 1.23V
Vth = 13.0V

<R1b> <R1a>

Vth = (Vref / (R2b / (R1b + R2b))

Vref = 3.42V * (R2a / (R1a + R2a))

Worst case Vth: min:12.47V, max: 13.54V

(HOST_DETECT_L)

518S0456

ACIN Detection

Inrush Limiter

Battery Connector

DC-In Connector

to A52 adapter for system load detection.

System must provide 10K-70K impedance

NOTE: R6910 is on LIO.

REQ of R6910 (on LIO), R6912, & R6913 is 36.9K.

Assuming 1% variance for R6910-R6915 and 3.42V:

<R2b>

48

7

87438-0832-BLK

M-RT-SM

CRITICAL

J6990

1
2
3
4
5
6
7
8

1SS355

SOD-323

D6901

1 2

46

45

7

805

MF-LF

1/8W

47

5%

R6907

1 2

402

8V-100PF

NO STUFF

DZ6962

1

2

8V-100PF

402

NO STUFF

DZ6963

1

2

402

NO STUFF

8V-100PF

DZ6961

1

2

NO STUFF

8V-100PF

402

DZ6960

1

2

CRITICAL

LMC7211

SM-LF

U6900

4

3

1

5

2

SI4413ADY-E3

SO-8

CRITICAL

Q6950

5

6

7

8

4

1

2

3

0.22uF

25V

20%

603

X5R

C6950

1

2

1/16W

5%

402

1M

MF-LF

R6916

12

1/16W

1%

402

MF-LF

102K

R6914

1

2

1/16W

1%

402

MF-LF

57.6K

R6915

1

2

102K

MF-LF

402

1/16W

1%

R6912

1

2

10.7K

1%
1/16W
MF-LF

402

R6913

1

2

10V

20%

0.1uF

402

CERM

C6910

1

2

1%

402

MF-LF

1/16W

470K

R6921

1

2

402

1/16W

5%

MF-LF

330K

R6950

1

2

SOT23-LF

2N7002

Q6910

3

1

2

SC70

MC74VHC1G08

U6950

3

2

1

4

5

87438-1043-BLK

M-RT-SM

CRITICAL

J6950

1

10

2
3
4
5
6
7
8
9

48

7

051-7261

SYNC_MASTER=(MASTER)

DC-In & Battery Connectors

69

109

16

SYNC_DATE=(MASTER)

=PPBUS_G3H_LIO_CONN

=PPBATTPOS_G3H_BATT_CONN

MAKE_BASE=TRUE

BATT_POS

MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.25mm

=PP18V5_G3H_INRUSH

MIN_LINE_WIDTH=0.2mm
MIN_NECK_WIDTH=0.2mm

ACIN_ENABLE_DIV_L

PP18V5_DCIN

ACIN_ENABLE_DIV2_L

=PP3V42_G3H_ACIN

ACOK_AND_PS_ON

SMC_ADAPTER_EN

MIN_LINE_WIDTH=0.50mm
MIN_NECK_WIDTH=0.20mm

VOLTAGE=18.5V

PPDCIN_G3H_R

=PPDCIN_G3H

SMC_BC_ACOK

ACIN_DIV

MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.2mm

MAKE_BASE=TRUE

VOLTAGE=18.5V

PP18V5_G3H_CHGR

=PP18V5_G3H_CHGR

ACIN_1V20_REF

SMC_BS_ALRT_L

MIN_LINE_WIDTH=0.60mm

PP18V5_DCIN

MIN_NECK_WIDTH=0.20mm

VOLTAGE=18.5V

=BATT_POS

=SMBUS_BATT_SCL

=SMBUS_BATT_SDA

=PPBATTNEG_G3H_BATT_CONN

BATT_NEG

MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.25mm

MIN_LINE_WIDTH=0.6mm

=BATT_NEG

46

67

45

46

8

57

67

40

45

57

67

67

7

7

8

36

8

34

67

7

7

7

Preliminary

D

SG

D

SG

D

SG

D

SG

D

SG

D

SG

D

SG

G

D

S

G

D

S

G

D

S

G

D

S

G

D

S

D

S

G

D

S

G

D

S

G

IN

IN

IN

IN

IN

IN

IN

IN

IN

D

SG

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

3.3V S3 FET

5V S3 FET

1.8V S0 FET

1.25V S0 FET

3.3V S0 FET

3.3V GPU FET

1.8V GPU FET

PBUS used for lower Rds(on)

1.25V GPU FET

5V S0 FET

SSM6N15FE

SOT563

Q7091

3

5

4

SOT563

SSM6N15FE

Q7081

3

5

4

SSM6N15FE

SOT563

Q7081

6

2

1

SSM6N15FE

SOT563

Q7051

3

5

4

SSM6N15FE

SOT563

Q7051

6

2

1

SSM6N15FE

SOT563

Q7096

3

5

4

SSM6N15FE

SOT563

Q7096

6

2

1

2N7002DW-X-F

SOT-363

Q7002

6

2

1

2N7002DW-X-F

SOT-363

Q7012

6

2

1

SOT-363

2N7002DW-X-F

Q7002

3

5

4

SOT-363

2N7002DW-X-F

Q7012

3

5

4

2N7002

SOT23-LF

Q7072

3

1

2

CRITICAL

IRF7707PBF

TSSOP

Q7020

1 5 8

4

2 3 6 7

FDC638P

CRITICAL

SM-LF

Q7000

1

2

5

6

3

4

CRITICAL

SOT23

FDC637AN

Q7090

1
2
5
6

3

4

CRITICAL

FDC638P

SM-LF

Q7070

1

2

5

6

3

4

CRITICAL

FDC638P

SM-LF

Q7030

1

2

5

6

3

4

CRITICAL

FDC638P

SM-LF

Q7010

1

2

5

6

3

4

CRITICAL

SOT23

FDC637AN

Q7050

1
2
5
6

3

4

CRITICAL

SOT23

FDC637AN

Q7095

1
2
5
6

3

4

CRITICAL

LFPAK

RJK0301DPB

Q7080

5

4

1 2 3

CERM-X5R
402

10%

0.15UF

6.3V

C7090

1

2

66

1/16W
MF-LF

1%

402

499

R7083

1 2

402

10%
CERM-X5R

6.3V

0.15UF

C7080

1

2

5%

100K

1/16W

402

MF-LF

R7082

1 2

15.0K

1%
1/16W
MF-LF

402

R7080

1 2

0.1UF

402

CERM

20%
10V

C7083

1 2

1%

MF-LF

1/16W

402

69.8K

R7081

1

2

402

1%

499

MF-LF

1/16W

R7093

1 2

66

16V

0.01UF

CERM

402

10%

C7070

1 2

1UF

10%
10V
X5R
402

C7071

1

2

402

MF-LF

1/16W

5%

100K

R7070

1 2

10K

5%
1/16W
MF-LF

402

R7072

1

2

66

0.15UF

6.3V
CERM-X5R

10%

402

C7050

1

2

MF-LF

1/16W

499

1%

402

R7053

1 2

1/16W
MF-LF

1%

402

499

R7098

1 2

6.3V
CERM-X5R

10%

402

0.15UF

C7096

1

2

5%

1/16W

100K

402

MF-LF

R7092

1 2

5%

100K

402

MF-LF

1/16W

R7052

1 2

10V

0.1UF

20%

402

CERM

C7053

1 2

1%
1/16W
MF-LF

402

15.0K

R7050

1 2

MF-LF

1/16W

1%

69.8K

402

R7051

1

2

5%

100K

MF-LF

1/16W

402

R7097

1 2

402

1%

15.0K

MF-LF

1/16W

R7096

1 2

402

CERM

20%
10V

0.1UF

C7095

1 2

402

CERM

20%

0.1UF

10V

C7093

1 2

402

MF-LF

1/16W

1%

69.8K

R7095

1

2

66

66

10%
10V

0.068UF

CERM

402

C7001

1

2

16V

0.01UF

CERM

402

10%

C7000

1 2

402

69.8K

1%
1/16W
MF-LF

R7091

1

2

10K

5%
1/16W
MF-LF

402

R7002

1

2

47K

5%

402

MF-LF

1/16W

R7000

1 2

66

16V

0.01UF

CERM

402

10%

C7010

1 2

16V
X5R

0.033UF

10%

402

C7011

1

2

402

MF-LF

1/16W

5%

100K

R7010

1 2

10K

5%
1/16W
MF-LF

402

R7012

1

2

66

10%

402

CERM

0.01UF

16V

C7020

1 2

CERM

0.068UF

10%
10V

402

C7021

1

2

47K

5%
1/16W
MF-LF

402

R7020

1 2

402

MF-LF

1/16W

5%

10K

R7022

1

2

15.0K

402

MF-LF

1/16W

1%

R7090

1 2

66

10%

402

CERM

0.01UF

16V

C7030

1 2

16V

0.033UF

10%
X5R

402

C7031

1

2

100K

5%
1/16W
MF-LF

402

R7030

1 2

402

MF-LF

1/16W

5%

10K

R7032

1

2

66

SSM6N15FE

SOT563

Q7091

6

2

1

SYNC_MASTER=M75_MLB

SYNC_DATE=04/02/2007

Power FETs

16

70

051-7261

109

P1V8GPU_SS

=PP1V8_GPU_P1V8GPUFET

P3V3S3_SS

=PP3V3_S3_FET

P3V3GPU_SS

=PP3V3_GPU_P3V3GPUFET

=PP3V3_GPU_FET

=PP3V3_S0_P3V3S0FET

=PP3V3_S0_FET

=P5VS0_EN

P5VS3_SS

=PP5V_S0_P5VS0FET

P5VS0_SS

=P3V3GPU_EN

P3V3GPU_EN_L

=P3V3S0_EN

P3V3S0_EN_L

P5VS0_EN_L

=P3V3S3_EN

P3V3S3_EN_L

P5VS3_EN_L

=P5VS3_EN

P1V8GPU_EN_L_RC

P1V8GPU_EN_L

=P1V25GPU_EN

P1V25GPU_EN_L

=P1V25S0_EN

P1V25S0_EN_L

P1V25S0_EN_L_RC

P1V25S0_SS_RC

=PP5V_S5_P1V25S0FET

=PP5V_S5_P1V8GPUFET

P1V25GPU_SS_RC

P3V3S0_SS

=PP1V25_GPU_FET

P1V25GPU_SS

P1V25GPU_EN_L_RC

P1V25S0_SS

=PP1V25_S0_FET

=P1V8GPU_EN

=PP1V25_GPU_P1V25GPUFET

=PP5V_S5_P1V25GPUFET

=P1V8S0_EN

=PP1V8_S0_P1V8S0FET

=PP1V8_S0_FET

P1V8S0_SS

P1V8S0_EN_L_RC

=PP5V_S5_P1V8S0FET

P1V8S0_EN_L

P1V8S0_SS_RC

=PP5V_S3_P5VS3FET

=PP5V_S3_FET

=PP1V8_GPU_FET

P1V8GPU_SS_RC

=PPBUS_S5_P1V8GPUFET

=PP1V25_S0_P1V25S0FET

=PP5V_S0_FET

=PP3V3_S3_P3V3S3FET

9 8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

Preliminary

IN

IN

IN

OUT
IN
OUT

IN

IN

IN

IN

IN

IN

IN

OUT
OUT

IN

IN

OUT

VID0

DPRSTP*

NC

VW

COMP

FB

FB2

RBIAS

VR_TT*
NTC

VR_ON
PGOOD

PSI*

RTN

VSEN

DFB

DROOP

VO

OCSET

VSUM

ISEN2

VID1

VID3
VID2

VID4

VID5

VID6

PGND2

VIN VDD

PVCC

LGATE2

PHASE2

UGATE2

ISEN1

PGND1

LGATE1

UGATE1

PHASE1

BOOT1
BOOT2

3V3

VDIFF

SOFT

DPRSLPVR

TPAD

GND

CLK_EN*

IMON

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

DPRSLPVR

DPRSTP*

(IMVP6_VSUM)

(ISL9504A)

(PGD_IN)

44A MAX CURRENT

(IMVP6_PHASE1)

These caps are for Q7100

CCM

Mode

DCM
DCM

CCM

1-Phase
1-Phase

2-Phase

Operation

1-Phase

PSI*

1
0

0

1

0
0

10

1

0

1

1

(IMVP6_PHASE2)

(IMVP6_ISEN1)

(IMVP6_ISEN2)

(IMVP6_VO)

(IMVP6_VO)

(GND)

(GND)

(IMVP6_COMP)

(IMVP6_VW)

These caps are for Q7102

spot of reg circuit.

Place R7126 in hot

LAYOUT NOTE:

(IMVP6_NTC)

(GND_IMVP6_SGND)

(IMVP6_FB)

(GND_IMVP6_SGND)

CERM

NO STUFF

0.0022UF

10%
50V

402

C7100

1

2

10K

1/16W
MF-LF

1%

402

R7100

1 2

402

10%

0.22UF

10V

CERM

C7103

1 2

SM

XW7104

12

20%

0.22UF

25V
603

X5R

C7115

1

2

83

23 16 10

7

83 25 16

7

28

28

45

7

28 16

9 7

SM

XW7102

12

10K

1/16W
MF-LF

1%

402

R7105

1 2

402

10%

0.22UF

10V

CERM

C7104

1 2

NO STUFF

CERM
402

50V

10%

0.0022UF

C7102

1

2

20%

603

X5R

25V

0.22UF

C7127

1

2

1/16W
MF-LF

1%

402

10

R7120

1 2

402

1/16W
MF-LF

10

1%

R7112

1 2

X5R

10%

1UF

10V
402

C7126

1

2

402

10

MF-LF

1/16W

1%

R7121

1 2

0.1uF

16V
402

10%
X5R

C7130

1

2

499

1/16W

402

1%

MF-LF

R7119

1 2

402

ISL9504B

CERM

50V

10%

0.001UF

C7107

1

2

ISL9504B

402

MF-LF

1/16W

1%

6.81K

R7110

1

2

CERM

6.3V

20%
603

4.7uF

C7135

1

2

CERM

402

16V

0.01uF

10%

C7110

1

2

ISL9504B

402

1%
1/16W
MF-LF

1K

R7113

1

2

ISL9504B

402

MF-LF

1/16W

1%

1K

R7109

1

2

ISL9504B

402

50V

220PF

X7R-CERM

10%

C7113

1

2

ISL9504B

402

1/16W
MF-LF

1%

97.6K

R7114

1

2

402

MF-LF

1/16W

5%

1

R7104

1

2

MF-LF

1/16W

5%

1

402

R7107

1

2

CERM

402

50V

10%

NO STUFF

0.001uF

C7116

1

2

3.09K

402

1/16W
MF-LF

1%

R7117

1 2

50V
CERM
402

5%

180pF

C7129

1

2

MF-LF

1%
1/16W

402

1K

R7118

1

2

402

MF-LF

1%

1/16W

2.61K

R7130

1

2

11K

402

1/16W
MF-LF

1%

R7115

1

2

0.22UF

10%

402

6.3V

CERM-X5R

C7128

1

2

0.015UF

X7R

10%
402

16V

C7134

1

2

402

0

1/16W
MF-LF

5%

R7122

1 2

0.047UF

16V
402

SIGNAL_MODEL=EMPTY

10%

CERM

C7131

1

2

CERM
402

16V

0.01uF

10%

NO STUFF

C7132

1

2

5%

1/16W

402

MF-LF

0

R7123

1 2

CERM

402

16V

0.01uF

10%

C7133

1

2

0.22UF

6.3V

20%

402

X5R

C7121

1

2

SM

XW7100

1 2

3.65K

MF-LF
603

1%
1/10W

R7101

1

2

3.65K

1/10W
603

MF-LF

1%

R7106

1

2

SM-IHLP

0.36UH-30A-1.2M-OHM

CRITICAL

L7100

1 2

SM-IHLP

0.36UH-30A-1.2M-OHM

CRITICAL

L7101

1 2

0.1UF

25V
X5R
402

10%

C7196

1

2

83 12

7

83 12

7

83 12

7

83 12

7

83 12

7

83 12

7

83 12

7

ISL9504B

402

CERM

50V

10%

0.001UF

C7106

1

2

ISL9504B

CERM
402

50V

10%

470PF

C7114

1

2

ISL9504B

402

MF-LF

1%

1/16W

255

R7111

1

2

402

16V

10%

0.015UF

X7R

C7105

1

2

13.3K

1/16W

1%
MF-LF

402

R7116

1

2

25V

10%
X5R

603

1UF

C7109

1

2

CRITICAL

10KOHM-5%

0603-LF

R7131

1

2

1/16W
402

MF-LF

1%

147K

R7108

1

2

1/16W

402

1%

MF-LF

4.02K

R7127

1

2

MF-LF
402

1/16W

5%

2.0K

R7197

1

2

SM

XW7103

1 2

SM

XW7101

1 2

59 50

59 50

83 11

83 11

CRITICAL

402

470K

R7126

1

2

402

5%

MF-LF

0

1/16W

R7198

1 2

83 46 10

NO STUFF

402

5%
MF-LF

68

1/16W

R7199

1

2

OMIT

QFN

ISL9504BCRZ

U7100

48

36
26

47

10

17

45

46

16

11

12

21

3

24

23

32

30

25

6

8

33

29

1

34

28

2

31

4

15

7

49

35

27

22

13

37

38

39

40

41

42

43

20

18

44

5

14

19

9

LFPAK

RJK0305DPB

CRITICAL

Q7100

5

4

1 2 3

LFPAK

RJK0301DPB

CRITICAL

Q7103

5

4

1 2 3

LFPAK

RJK0305DPB

CRITICAL

Q7102

5

4

1 2 3

RJK0301DPB

CRITICAL

LFPAK

Q7105

5

4

1 2 3

LFPAK

RJK0301DPB

CRITICAL

Q7104

5

4

1 2 3

RJK0301DPB

LFPAK

CRITICAL

Q7101

5

4

1 2 3

POLY

20%

CRITICAL

25V

22UF

CASE-D2-LF

C7117

1

2

CASE-D2-LF

20%

POLY

CRITICAL

25V

22UF

C7153

1

2

22UF

20%

CRITICAL

POLY

25V

CASE-D2-LF

C7155

1

2

1UF

603

X5R

10%
25V

C7154

1

2

66 49

I848I849

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

IMVP6 CPU VCore Regulator

051-7261

16

71

109

IMVP6_VO

=PPVCORE_S0_CPU_REG

IMVP6_UGATE1

VR_PWRGOOD_DELAY
IMVP6_VR_TT_L

IMVP6_FB2

IMVP6_VDIFF

IMVP6_PHASE2

IMVP6_SOFT
IMVP6_RBIAS

IMVP6_FB

MIN_LINE_WIDTH=0.50 MM
VOLTAGE=0V

MIN_NECK_WIDTH=0.20 MM

GND_IMVP6_SGND

=PP5V_S0_CPU_IMVP

VOLTAGE=3.3V

PP3V3_S0_IMVP6_3V3

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM

=PPVIN_S5_CPU_IMVP

=PPVIN_S5_CPU_IMVP_VIN

=PP3V3_S0_IMVP

IMVP6_NTC

CPU_DPRSTP_L

IMVP6_VID<5>

IMVP6_COMP

MIN_NECK_WIDTH=0.2 MM

PPVIN_S5_IMVP6_VIN

MIN_LINE_WIDTH=0.25 MM
VOLTAGE=18.5V

CPU_PROCHOT_L

IMVP_VR_ON

IMVP6_VID<0>

IMVP6_VID<2>

IMVP6_IMON

IMVP6_VID<1>

IMVP6_VID<4>
IMVP6_VID<3>

PM_DPRSLPVR

IMVP6_NTC_R

IMVP6_PSI_L

MIN_LINE_WIDTH=1.5 MM

IMVP6_PHASE2

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

IMVP6_BOOT2

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

IMVP6_UGATE2

MIN_NECK_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.5 MM

IMVP6_LGATE2

VR_PWRGD_CLKEN_L

CPU_VCCSENSE_P

CPU_VCCSENSE_N

IMVP6_VSUM2

IMVP6_VSUM1

IMVP6_COMP_RC

IMVP6_VDIFF_RC

IMVP6_VO_R

IMVP6_VO2

IMVP6_VO1

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM

IMVP6_VSUM2
IMVP6_VO2

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM

IMVP6_VID<6>

MIN_LINE_WIDTH=0.25 MM

PP5V_S0_IMVP6_VDD

MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V

MIN_NECK_WIDTH=0.25 MM

IMVP6_VO1

MIN_LINE_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.25 MM

IMVP6_LGATE1

MIN_LINE_WIDTH=0.25 MM

IMVP6_BOOT1

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=1.5 MM

IMVP6_PHASE1

MIN_NECK_WIDTH=0.2 MM

IMVP6_FB2

MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MM

IMVP6_VDIFF

MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MM

IMVP6_RBIAS

MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MM

IMVP6_SOFT

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_DFB

MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MM

IMVP6_VO

IMVP6_FB

MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_DROOP

MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MM

IMVP6_OCSET

IMVP6_DROOP

IMVP6_DFB

IMVP_DPRSLPVR

IMVP6_VSEN_N

IMVP6_VSEN_P

IMVP6_OCSET

IMVP6_ISEN2

IMVP6_LGATE2

IMVP6_UGATE2

IMVP6_ISEN1

IMVP6_PHASE1

IMVP6_BOOT2

IMVP6_BOOT1

IMVP6_LGATE1

IMVP6_VSUM

IMVP6_VW

IMVP6_VW

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_COMP

MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MMMIN_LINE_WIDTH=0.25 MM

IMVP6_VSUM1

MIN_LINE_WIDTH=0.5 MM

IMVP6_UGATE1

MIN_NECK_WIDTH=0.2 MM

IMVP6_ISEN1

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

IMVP6_ISEN2

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

IMVP6_VSEN_N

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

IMVP6_VSEN_P

49

8

59

59

83

83

83

83 83

7

59

59

59

59

59

59

59

8

8

8

8

59

59

59

59

59

59

59

59

59

59

59 59

59

59

59

59

59

59

59

59

50

59

50

59

59

7

59

59

59

59

59

59

59

59

59

59

59

59

59

59 59

59

59 59

59 59

Preliminary

OUT

IN
IN

IN

IN

IN

IN

S

D

G

OUT
OUT

OCSET

VO

DFB

COMP

VSUM

DROOP

RTN

VDIFF

PGND

VSS

THRM_PAD

VSEN

FDE

AF_EN

VID4

SOFT

FB

VW

VR_ON

VID3

VID2

PGOOD
VID0

LGATE

UGATE

PHASE

BOOT

RBIAS

VIN

PVCC

VID1

VDD

IMON

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

IN RENDER SUSPEND STATE, AUDIO FILTER

(Q7250 limit)

10A max output

Vout according to VID

(GFXIMVP6_FDE)

(GFXIMVP6_AF_EN)

WHEN GFXIMVP6_FDE = 1

ENABLED WHEN GFXIMVP6_AF_EN = 1

(GFXIMVP6_VO)

(NB VID3)

(NB VID2)

100K pull-down on VR_EN per Crestline Issue #306022.

NOTE: Intel recommendation to stuff 30K pull-up and

ENTER DIODE-EMULATION-MODE IN ALL STATES

(NB VID1)

(NB VID0)

(GND)

(GFXIMVP6_VO)
(GFXIMVP6_PHASE_VSUM)

VO=Sense-, PHASE_VSUM=Sense+

(VO/PHASE_VSUM offpage flags for current sensing)

(GFXIMVP6_AGND)

(GFXIMVP6_AGND)

402

1/16W

1%

MF-LF

150K

R7202

2 1

CERM

402

16V

0.01uF

10%

C7203

12

0

MF-LF

5%

1/16W

402

R7251

1 2

0.22uF

10V

CERM

402

10%

C7256

1

2

402

1/16W

1%

MF-LF

6.98K

R7222

1

2

CERM
402

50V

10%

0.001UF

C7222

1

2

CERM
402

10%
50V

470pF

NO STUFF

C7233

1

2

CERM

402

50V

10%

0.001UF

C7221

1

2

CERM
402

0.0033UF

50V

10%

C7220

1

2

330pF

50V

10%

402

CERM

C7271

1 2

0.1uF

10%
16V

402

X5R

C7272

1

2

750

1/16W

1%

MF-LF

402

R7277

1 2

SM

XW7200

1 2

1K

5%
1/16W

402

MF-LF

R7271

1

2

402

1/16W

5%

MF-LF

0

R7232

1 2

PLACEMENT_NOTE=Place R7220 at NB

402

1/16W

5%

MF-LF

0

R7220

1 2

402

PLACEMENT_NOTE=Place R7221 at NB

1/16W

5%

MF-LF

0

R7221

1 2

0.001UF

CERM
402

50V

10%

C7223

1

2

402

1/16W

5%

MF-LF

1K

R7250

1

2

1/16W

402

1%

MF-LF

10

R7200

1 2

X5R
402

10%
10V

1uF

C7200

1

2

1uF

10V

10%

402

X5R

C7201

1

2

10%

0.01uF

16V
402

CERM

C7202

1

2

680pF

50V

10%

402

CERM

C7251

1

2

402

MF-LF

NO STUFF

5%

1/16W

10K

R7204

1

2

MF-LF

402

1/16W

5%

20K

NO STUFF

R7203

2 1

402

1/16W

5%

MF-LF

10K

R7205

1

2

NO STUFF

402

1/16W

5%

10K

MF-LF

R7206

1

2

402

1/16W

5%
MF-LF

10K

R7207

1

2

SM

XW7201

1

2

SM

XW7202

1

2

5%

1/16W

402

MF-LF

1

R7208

1 2

X5R
603

10UF

6.3V

20%

C7266

1

2

X5R

20%

6.3V
603

10UF

C7265

1

2

15.0K

MF-LF

1%

1/16W

402

R7270

1 2

1/16W
MF-LF

1%

402

3.01K

R7272

2

1

0.47UH-26A

IHLP2525CZ-SM

CRITICAL

L7200

1 2

CRITICAL

POLY

CASE-D2-LF

20%

22UF

25V

C7252

603

1UF

X5R

25V

10%

C7253

1

2

603

1UF

10%
X5R

25V

C7254

1

2

402

1/16W

1%
MF-LF

158K

R7230

1

2

CERM
402

50V

5%

120PF

C7232

1

2

402

1/16W

1%
MF-LF

2.21K

R7233

1

2

402

1/16W

1%
MF-LF

3.65K

R7231

1

2

0

402

1/16W

5%
MF-LF

NO STUFF

R7201

2

1

402

10%
50V

820PF

CERM

C7230

12

CERM

402

10%
50V

680PF

C7231

1 2

9

60

9

60

9

60

9

60

9

60

9

22K

MF-LF

402

1/16W

5%

R7291

1

2

402

1/16W
MF-LF

22K

5%

R7292

1

2

22K

MF-LF

402

1/16W

5%

R7294

1

2

402

1/16W

5%

100K

MF-LF

R7296

1

2

402

1/16W

5%

30K

MF-LF

R7295

1

2

402

1/16W

5%

22K

MF-LF

R7293

1

2

60

9

SI7114DN

PWRPK-1212-8

CRITICAL

Q7250

5

4

1 2 3

SI7108DNS

CRITICAL

PWRPK-1212-8

Q7251

5

4

1 2 3

CRITICAL

TANT
D2T

10%

330UF

2.0V

C7260

1

23

1%

MF-LF

1/4W

0.002

1206

R7260

1 2

402-1

CERM

5%

68PF

50V

C7273

1

2

50

50

QFN

ISL6263B

CRITICAL

U7200

30

17

5

11

10

6

32

28

21

3

20

31

19

22

1

9

2

33

18

16

7

23
24
25
26
27

14

12

29

8

15

13

4

SYNC_DATE=03/05/2007

16

051-7261

SYNC_MASTER=M75_MLB

109

72

IMVP6 NB Gfx Core Regulator

GFXIMVP6_OCSET

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

GFXIMVP6_VO

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

GFXIMVP6_DFB

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_COMP

MIN_NECK_WIDTH=0.2MM

GFXIMVP6_VSUM

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_DROOP

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_VSEN_N

MIN_NECK_WIDTH=0.2MM

GFXIMVP6_VDIFF_R

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

GND_GFXIMVP6_AGND

VOLTAGE=0V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_VSEN_P

GFXIMVP6_FDE

GFXIMVP6_AF_EN

GFXIMVP6_VID<4>

GFXIMVP6_SOFT

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_FB

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_VW

MIN_NECK_WIDTH=0.2MM

GFX_VR_EN

GFXIMVP6_VID<3>

GFXIMVP6_VID<2>

GFXIMVP6_PGOOD

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.3MM

GFXIMVP6_LGATE

GFXIMVP6_UGATE

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.3MM

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.6MM

GFXIMVP6_PHASE

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_BOOT

MIN_NECK_WIDTH=0.2MM

GFXIMVP6_RBIAS

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_VIN

MIN_NECK_WIDTH=0.2MM

PP5V_S0_GFXIMVP6_PVCC

MIN_LINE_WIDTH=0.3MM
VOLTAGE=5V

GFXIMVP6_VID<1>

PP5V_S0_GFXIMVP6_VDD

MIN_LINE_WIDTH=0.3MM
VOLTAGE=5V

MIN_NECK_WIDTH=0.2MM

GFXIMVP6_IMON

=PP3V3_S0_GFXIMVP6

MIN_NECK_WIDTH=0.3MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_PHASE_VSUM

GFXIMVP6_VID<3>

GFX_VR_EN

GFXIMVP6_VID<4>

GFXIMVP6_VID<2>

GFXIMVP6_VID<1>

=PPVIN_S0_GFXIMVP6

=PP3V3_S0_GFXIMVP6

GFXIMVP6_BOOT_RC

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.3MM

=PPVCORE_S0_NBGFX_VSEN

MIN_NECK_WIDTH=0.3MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_VDIFF

MIN_NECK_WIDTH=0.3MM

GFXIMVP6_COMP_RC

MIN_LINE_WIDTH=0.3MM

MIN_NECK_WIDTH=0.3MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_VDIFF_RC

=PP5V_S0_GFXIMVP6

PPVCORE_S0_NBGFXSENSE_R

MIN_LINE_WIDTH=0.6MM
VOLTAGE=1.0V

MIN_NECK_WIDTH=0.3MM

=PPVCORE_S0_NBGFX_REG

GFXIMVP6_VID<0>

GFXIMVP6_VID<0>

60

60

60

60

60

60

60

8

60

91

9

9

9

9

9

8

8

8

8

8

7

9

Preliminary

GND

THRML_PAD

SKIPSEL
TONSEL

V5FILT

VIN

VREG5

VREG3

VREF2

EN5
EN3

VBST2

DRVH2

LL2

CS2

DRVL2

VO2

PGND2

COMP2

VFB2

PGOOD2

EN2

DRVH1

LL1

DRVL1

CS1

VO1

PGND1

VFB1
COMP1

PGOOD1

EN1

VBST1

SYM (3 OF 3)

IN

IN

IN

OUT
OUT

IN

S

D

G

S

D

G

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

100mA max load when EN5 high

50uA max load when EN5 & EN3 high

TPS51120 LDO/Buffer outputs

(Available for system use)

Vout = 3.3V

(L7360 limit)

EN3 can float or tie to VREG5 for automatic 3.3V LDO enable

NOTE: EN5 can float or tie to VIN for automatic 5V LDO enable

When both are low TPS51120 VIN current drops from 100-150uA to 10-20uA.

(L7320 limit)

8A max output

Vout = 5.0V

3.3V Fixed

5V Fixed

5.5A max output

10%
X5R

603

25V

1UF

C7300

1

2

CRITICAL

IHLP

4.7UH

L7360

1 2

1UF

25V

10%
X5R

603

C7341

1

2

50V

10%

0.1UF

603-1

X7R

C7364

1

2

X5R
603

10UF

6.3V

20%

C7390

1

2

50V

0.1UF

10%

603-1

X7R

C7324

1

2

D3L

330UF

20%

CRITICAL

POLY

6.3V

C7352

1

2

805-2

10UF

10V

CERM

20%

C7350

1

2

805-2

10UF

10V

20%
CERM

C7351

1

2

SM

XW7300

1 2

6.3V

150UF

CASE-B2

CRITICAL

POLY

20%

C7392

1

2

POLY

20%

CRITICAL

25V

22UF

CASE-D2-LF

C7340

1

2

10%
X5R

603

1UF

25V

C7381

1

2

CRITICAL

20%

POLY

22UF

25V

CASE-D2-LF

C7380

1

2

2.2UH-14A

IHLP2525CZ-SM

CRITICAL

L7320

1 2

CRITICAL

LLP

TPS51120

U7300

2 7

23 18

27

14

25 16

29 12

10

9

5

26 15

24 17

30 11

32

33

31

20

28 13

3 6

22

1 8

4

19

21

4.22K

1/16W
402

MF-LF

1%

R7325

1

2

3.57K

MF-LF

402

1/16W

1%

R7365

1

2

6.3V

20%

10UF

X5R
603

C7303

1

2

10UF

20%

6.3V
X5R
603

C7305

1

2

MF-LF

1/16W
402

4.7

5%

R7306

1

2

402

10%
10V
X5R

1UF

C7306

1

2

66

66

66

46

46

66

402

CERM

50V

20%

0.001UF

C7302

1

2

SI7114DN

CRITICAL

PWRPK-1212-8

Q7360

5

4

1 2 3

CRITICAL

PWRPK-1212-8

SI7108DNS

Q7365

5

4

1 2 3

SI7114DN

PWRPK-1212-8

CRITICAL

Q7320

5

4

123

SI7108DNS

CRITICAL

PWRPK-1212-8

Q7325

5

4

123

PLACEMENT_NOTE=Place XW7360 next to C7390.

SM

XW7360

1

2

PLACEMENT_NOTE=Place XW7320 next to C7350.

SM

XW7320

1

2

SM

XW7325

1 2

SM

XW7365

1 2

5V / 3.3V Power Supply

SYNC_DATE=12/04/2006

SYNC_MASTER=M75_MLB

051-7261

16

109

73

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P5VS5_VBST

=PPVIN_S5_P5VP3V3

MIN_NECK_WIDTH=0.20 mm

PP5V_S5_P5VP3V3_LDO

VOLTAGE=5V

MIN_LINE_WIDTH=0.25 mm

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P3V3S5_VBST

=PP3V3_S5_REG

P5VP3V3_VREG3

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P5VS5_DRVH

GATE_NODE=TRUE

P5VS5_DRVL

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE

P5VS5_CS

=PP5V_S5_REG

PP2V0_S5_P5VP3V3_BUF

VOLTAGE=2V

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

PP5V_S5_P5VP3V3_V5FILT

VOLTAGE=5V

SWITCH_NODE=TRUE

P5VS5_LL

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P5VS5_VO

MIN_NECK_WIDTH=0.2 mm

GND_P5VS5_PGND

MIN_LINE_WIDTH=0.6 mm
VOLTAGE=0V

P3V3S5_VO

P3V3S5_CS

P3V3S5_DRVH

MIN_LINE_WIDTH=0.6 mmGATE_NODE=TRUE
MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P3V3S5_DRVL

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

P3V3S5_LL

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

=PPVIN_S5_P3V3S5

=PPVIN_S5_P5VS5

GND_P3V3S5_PGND

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

VOLTAGE=0V

=P3V3S5_EN

=P5VP3V3_EN5

=P5VP3V3_EN3

=P3V3S5_PGOOD

=P5VS5_PGOOD

=P5VS5_EN

MIN_NECK_WIDTH=0.2 mm

GND_P5VP3V3_SGND

MIN_LINE_WIDTH=0.6 mm
VOLTAGE=0V

8

8 8

8 8

Preliminary

OUT

IN

THRM_PAD

VFB

TRIP

VOUT

EN_PSV

GND

PGND

V5DRV

V5FILT

DRVL

DRVH

LL

TON

VBST

PGOOD

SYM (2 OF 2)

S

D

G

OUT

IN

THRM_PAD

VFB

TRIP

VOUT

EN_PSV

GND

PGND

V5DRV

V5FILT

DRVL

DRVH

LL

TON

VBST

PGOOD

SYM (2 OF 2)

S

D

G

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

<Ra>

Vout = 0.75V * (1 + Ra / Rb)

(P1V25ENET_VFB)

Vout = 1.051V
10A max output
(L7460? limit)

8A max output

<Rb>

Vout = 0.75V * (1 + Ra / Rb)

<Rb>

(L7410? limit)

(GND)

(P1V25ENET_TON)

Vout = 1.2496V

(P1V05S0_VFB)

<Ra>

(P1V05S0_TON)

(GND)

6.81K

1/16W
402

MF-LF

1%

R7405

1

2

66

66

200

MF-LF

1%

1/16W

402

R7401

1 2

SM

XW7400

1

2

QFN

CRITICAL

TPS51117RGY_QFN14

U7400

13

9

1

7

12

8

6

15

2

11

10

4

14

5

3

603

X5R

16V

10%

2.2UF

C7401

1

2

402

X5R

10%
10V

1UF

C7400

1

2

PWRPK-1212-8

CRITICAL

SI7108DNS

Q7411

5

4

1 2 3

50V

10%

603-1

X7R

0.1UF

C7420

1

2

CRITICAL

PWRPK-1212-8

SI7114DN

Q7410

5

4

1 2 3

2.2UH-14A

CRITICAL

IHLP2525CZ-SM

L7410

1 2

1/16W
MF-LF
402

1%

200K

R7421

1

2

CASE-D2-LF

22UF

25V

20%

POLY

CRITICAL

C7440

1

2

X5R

25V

1UF

10%

603

C7445

1

2

402

MF-LF

1/16W

1%

12.1K

R7431

1

2

402

MF-LF

1%

8.06K

1/16W

R7430

1

2

5%
402

CERM

NO STUFF

100PF

50V

C7430

1

2

SM

PLACEMENT_NOTE=Place XW7430 close to C7415.

XW7430

1

2

6.3V

20%

10UF

603

X5R

C7415

1

2

1/16W
402

1%
MF-LF

5.62K

R7455

1

2

66

66

200

1%

402

MF-LF

1/16W

R7451

1 2

SM

XW7450

1

2

TPS51117RGY_QFN14

QFN

CRITICAL

U7450

13

9

1

7

12

8

6

15

2

11

10

4

14

5

3

16V

2.2UF

10%

603

X5R

C7451

1

2

1UF

402

X5R

10V

10%

C7450

1

2

PWRPK-1212-8

SI7108DNS

CRITICAL

Q7461

5

4

1 2 3

50V

10%

603-1

X7R

0.1UF

C7470

1

2

PWRPK-1212-8

SI7114DN

CRITICAL

Q7460

5

4

1 2 3

IHLP2525CZ-SM

CRITICAL

1.0UH-22A

L7460

1 2

1/16W
MF-LF

1%

200K

402

R7471

1

2

CRITICAL

22UF

CASE-D2-LF

25V

20%

POLY

C7490

1

2

X5R

25V

1UF

603

10%

C7495

1

2

402

MF-LF

1/16W

1%

14.0K

R7481

1

2

MF-LF

402

1%

5.62K

1/16W

R7480

1

2

100PF

NO STUFF

5%

402

CERM

50V

C7480

1

2

SM

PLACEMENT_NOTE=Place XW7480 close to C7465.

XW7480

1

2

X5R

20%
603

6.3V

10UF

C7465

1

2

POLY
CASE-B2

20%

330UF

2.0V

CRITICAL

C7410

10%

CRITICAL

TANT
D2T

330UF

2.0V

C7460

1

23

SM

XW7401

1

2

SM

XW7451

1

2

1.25V / 1.05V Power Supply

SYNC_MASTER=M75_MLB

051-7261

16

74

SYNC_DATE=03/05/2007

109

GND_P1V25ENET_SGND

VOLTAGE=0V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

=P1V25ENET_EN

MIN_LINE_WIDTH=0.25 mm

P1V25ENET_VBST

MIN_NECK_WIDTH=0.2 mm

P1V25ENET_VFB
P1V25ENET_TRIP

=P1V25ENET_PGOOD

MIN_NECK_WIDTH=0.2 mm

P1V25ENET_DRVL

GATE_NODE=TRUE MIN_LINE_WIDTH=0.6 mm

P1V05S0_VFB

PP5V_S5_P1V25ENET_V5FILT

MIN_LINE_WIDTH=0.6 mm
VOLTAGE=5V

MIN_NECK_WIDTH=0.2 mm

=PP5V_S5_P1V05S0

=P1V05S0_PGOOD

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

P1V25ENET_LL

MIN_LINE_WIDTH=0.6 mm

=PPVIN_ENET_P1V25ENET

=PPVIN_S0_P1V05S0

MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V

P1V25ENET_PGND

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V

MIN_LINE_WIDTH=0.6 mm

P1V05S0_PGND

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP5V_S5_P1V05S0_V5FILT

VOLTAGE=5V

PP1V05_S0_VDDQSNS

=PP1V05_S0_REG

=P1V05S0_EN

PP1V25_ENET_VDDQSNS

=PP1V25_ENET_REG

=PP1V25_ENET_REG

MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE MIN_LINE_WIDTH=0.6 mm

P1V25ENET_DRVH

P1V25ENET_TON

=PP5V_S5_P1V25ENET

=PP1V05_S0_REG

MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE MIN_LINE_WIDTH=0.6 mm

P1V05S0_DRVL

MIN_NECK_WIDTH=0.2 mm

SWITCH_NODE=TRUE

P1V05S0_LL

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE MIN_LINE_WIDTH=0.6 mm

P1V05S0_DRVH

MIN_LINE_WIDTH=0.25 mm

P1V05S0_VBST

MIN_NECK_WIDTH=0.2 mm

P1V05S0_TON

P1V05S0_TRIP

GND_P1V05S0_SGND

VOLTAGE=0V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

62

62

62

62

8

8

8

8

8

8

8

8

Preliminary

MODE

VDDQSNS

COMP

NC0
NC1

VTTSNS

VTT

VTTREF

PGOOD

S3
S5

VTTGND

THRM_PAD

GND

CS_GND

PGND

CS

LL

DRVL

DRVH

VDDQSET

VBST

VLDOINV5FILT

V5IN

SYM (2 OF 2)

IN
IN
OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

Vout = VTTREF

(P1V8S3_VDDQSNS)

NC
NC

10mA max load
Vout = VDDQSNS/2

(P1V8S3_FB)

<Rb>

(L7530 limit)

Place at pin 23

<Ra>

(P1V8S3_CSGND)

Vout = 0.75V * (1 + Ra / Rb)

18A max output

Vout = 1.80V or 1.825V

VDDQ PGOOD

VDDQ/VTTREF Enable

VTT Enable

(P1V8S3_DRVH)

C7545

Place next to

(P1V8S3_LL)

(P1V8S3_DRVL)

50V

10%

X7R-CERM

805

0.1UF

C7525

P1V8S3_1V825

0.1%

21.5K

1/16W
MF-LF
402

R7520

1

2

402

15.0K

1/16W
MF-LF

0.1%

R7521

1

2

20%

POLY

2.5V

330UF

CRITICAL

CASE-C2

C7540

1

2

330UF

CRITICAL

20%
POLY

CASE-C2

2.5V

C7541

1

2

10%

603

1UF

X5R

25V

C7532

1

2

100PF

50V
402

NO STUFF

CERM

5%

C7520

1

2

CRITICAL

TPS51116

QFN

U7500

6

16

17

21

19

3

20

4

7

12

18

13

10
11

25

14

15

22

9

8

23

24

1

5

2

X5R

10%
10V

1UF

402

C7505

1

2

402

MF-LF

5%

4.7

1/16W

R7505

1 2

805-3

CERM-X5R

22UF

6.3V

20%

CRITICAL

C7561

1

2

805-3

CERM-X5R

22UF

6.3V

20%

CRITICAL

C7560

1

2

SM

XW7560

1 2

SM

XW7535

1 2

0.033UF

10%
402

X5R

16V

C7550

1

2

66

10V

20%

CERM

10UF

805-2

C7500

1

2

66

1/16W

6.81K

1%

402

MF-LF

R7510

1

2

66

CRITICAL

22UF

25V

20%

CASE-D2-LF

POLY

C7530

1

2

CRITICAL

20%

22UF

POLY

CASE-D2-LF

25V

C7531

1

2

LFPAK

RJK0305DPB

CRITICAL

Q7530

5

4

1 2 3

CRITICAL

LFPAK

RJK0303DPB

Q7535

5

4

1 2 3

IHLP4040DZ11-SM

1.0UH-20A

CRITICAL

L7530

1 2

6.3V
603

X5R

20%

10UF

C7545

1

2

CRITICAL

RJK0303DPB

LFPAK

Q7536

5

4

1 2 3

SM

XW7545

1

2

10UF

6.3V
X5R
603

20%

C7501

1

2

SM

XW7500

1

2

603

1/10W

1

5%

MF-LF

R7526

1 2

SYNC_DATE=12/04/2006

16

109

75

051-7261

1.8V DDR2 Supply

SYNC_MASTER=M75_MLB

1

CRITICAL P1V8S3_1V8103S0192

RES,MTL FILM,21K,0.1,0402,SM,LF

R7520

P1V8S3_CS

P1V8S3_VDDQSNS

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

VOLTAGE=1.8V

P1V8S3_FB

P1V8S3_CSGND

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

SWITCH_NODE=TRUE

P1V8S3_LL

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

P1V8S3_DRVH

GATE_NODE=TRUE

GND_P1V8DDRREG_SGND

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V

=PPVIN_S3_P1V8S3

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

GATE_NODE=TRUE

P1V8S3_DRVL

=P0V9S0_EN

P1V8S3_VBST

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP5V_S5_P1V8DDRREG_V5FILT

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V

=PP1V8_S3_REG

DDRREG_VTTSNS

=PP0V9_S0_VTT_LDO

=P1V8S3_PGOOD

=P1V8S3_EN

MIN_NECK_WIDTH=0.2 mm

P1V8S3_DRVH_R

GATE_NODE=TRUE
MIN_LINE_WIDTH=0.6 mm

=PP0V9_S3_VTTR_BUF

=PP5V_S5_P1V8DDRREG

=PP1V8_S3_REG

63

63

9

8

8

8

8

8

8

Preliminary

IN

OUT

THRM_PAD

VFB

TRIP

VOUT

EN_PSV

GND

PGND

V5DRV

V5FILT

DRVL

DRVH

LL

TON

VBST

PGOOD

SYM (2 OF 2)

S

D

G

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(P1V5S0_TON)

<Ra>

<Rb>

(P1V5S0_VFB)

Vout = 0.75V * (1 + Ra / Rb)

(GND)

(L7620 limit)

8A max output

Vout = 1.50V

CERM

5%

402

50V

100PF

NO STUFF

C7610

1

2

50V

10%

603-1

X7R

0.1UF

C7615

1

2

CRITICAL

POLY

20%
25V

22UF

CASE-D2-LF

C7620

1

2

POLY

20%

CASE-D2E-LF

330UF

2.5V

CRITICAL

C7632

1

2

66

66

402

X5R

1UF

10V

10%

C7600

1

2

1%

402

MF-LF

1/16W

200

R7601

1 2

X5R
603

10%

2.2UF

16V

C7601

1

2

200K

1%

402

MF-LF

1/16W

R7619

1

2

CRITICAL

TPS51117RGY_QFN14

QFN

U7600

13

9

1

7

12

8

6

15

2

11

10

4

14

5

3

603

10%

1UF

25V
X5R

C7621

1

2

CRITICAL

SI7114DN

PWRPK-1212-8

Q7620

5

4

1 2 3

CRITICAL

PWRPK-1212-8

SI7108DNS

Q7625

5

4

1 2 3

PLACEMENT_NOTE=Place XW7620 close to L7620.

SM

XW7620

1

2

SM

XW7600

1 2

1/16W
402

1%
MF-LF

6.04K

R7605

1

2

6.3V

20%

10UF

X5R
603

C7630

1

2

MF-LF

402

10K

1%

1/16W

R7610

1

2

1%

10K

402

MF-LF

1/16W

R7611

1

2

CRITICAL

IHLP2525CZ-SM

1.0UH-22A

L7620

1 2

1.5V Power Supply

SYNC_DATE=03/05/2007

SYNC_MASTER=M75_MLB

109

76

051-7261

16

PP1V5_S0_VDDQSNS

=PP1V5_S0_REG

P1V5S0_TRIP

=PP1V5_S0_REG

GND_P1V5S0_SGND

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=0V

MIN_NECK_WIDTH=0.2 mm

PP5V_S5_P1V5S0_V5FILT

MIN_LINE_WIDTH=0.6 mm
VOLTAGE=5V

=P1V5S0_PGOOD

=PPVIN_S0_P1V5S0

=P1V5S0_EN

=PP5V_S5_P1V5S0

P1V5S0_VFB

MIN_NECK_WIDTH=0.2 mm

P1V5S0_DRVL

MIN_LINE_WIDTH=0.6 mmGATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P1V5S0_DRVH

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

P1V5S0_LL

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.25 mm

P1V5S0_VBST

P1V5S0_TON

64

64 8 8

8

8

Preliminary

OUT

IN

NR

NC

THRML

EN

GND

PAD

FB

BIAS

SW

SHDN*

NC

VIN

BOOST

GND

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(Switcher limit)

200mA max output

<Ra>

NC

<Rb>

Vout = 3.316V

Vout = 1.25V * (1 + Ra / Rb)

3.3V FW PHY Supply

NC

Backup power in case of FW bus
VP short to keep PHY powered.

1.95V FW PHY Supply

4V

20%
402

X5R

2.2uF

C7722

1

2

16V

10%
402

CERM

0.01uF

C7721

1

2

6.3V

10%
402

CERM

1uF

C7720

1

2

SON

TPS799195

CRITICAL

U7720

4

3

6

5

2

1

7

402

MF-LF

1/16W

1%

324K

R7710

1

2

1/16W

1%

402

MF-LF

196K

R7711

1

2

50V

5%

402

CERM

22pF

C7710

1

2

402

20%
X5R

6.3V

0.22uF

C7705

1

2

50V

X7R-CERM

10%

1206

4.7UF

C7700

1

2

CRITICAL

TSOT23-8

LT3470

U7700

7

6

8

4

2

1 5

3

SMD20E40C-X-F

SC-59

D7700

1

2

3

33uH

CDPH4D19F-SM

CRITICAL

L7700

1 2

CRITICAL

6.3V

20%

22UF

CERM-X5R
805-3

C7701

1

2

SYNC_MASTER=M75_MLB

FW PHY Power Supplies

SYNC_DATE=12/04/2006

051-7261

16

109

77

=PP1V95_FW_LDO

P1V95FW_NR

P3V3FW_SW

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=33V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PPVIN_FW_P3V3FW

=PPVP_FW_P3V3FW

=PPVIN_FW_P1V95FW

=PPBU_S0_P3V3FW

P3V3FW_BOOST

P3V3FW_FB

=PP3V3_FW_REG

8

8

8

8

8

Preliminary

FB

BIAS

SW

SHDN*

NC

VIN

BOOST

GND

OUT
OUT OUT

OUT

OUT
OUT

OUT

OUT

OUT

OUT
OUT

OUT

OUT
OUT

OUT

OUT
OUT

OUT

IN

IN

OUT

OUT

OUT
OUT

IN

OUT

VPG

V2

V4

V3

VREF RST*

CRT

THRM_PAD

GND

PBR*

V1

OUT
OUT

G

D

S

OUT

G

D

S

Y

B

A

Y

B

A

IN

G

D

S

OUT

G

D

S

IN

IN

IN

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(PM_ENET_EN)

TPS51117 PGOOD does not
deassert while GPU
VIDs are changing

SB GPIO has ability to force all GPU rails off

(PM_SLP_S3_L)

up in the following order:

2) 3.3V

3) Vcore

4) 1.8V

(EXTGPU_PWR_EN)

R7853 acts as pull-up for open-drain GPIO.

supplies and PGOOD revalidate

GPU core voltage.

To CPU IMVP6

Reports when 1.5V S0 and 1.05V S0 are in regulation

1.5V / 1.05V PWRGD Circuit

PM_SLP_S3_LPM_SLP_S4_L

SMC_PM_G2_ENABLE

Run (S0)

Supply needs to guarantee 3.31V delivered to SMC VRef generator

State

Soft-Off (S5)

Sleep (S3)

Battery Off (G3Hot)

0

1

1
1

0
0

1

1

0

0

0

1

Vout = 3.425

<Rb>

NC

Vout = 1.25V * (1 + Ra / Rb)

Unused PGOOD Signals

<Ra>

3.425V "G3Hot" Supply

Does not include GFX rails

NC

Trst = 4.6ms/nF
Trst = 216ms

1) 1.2V

G84M GPU requires rails to come

TPS51117 PGOOD threshold 92.5-97.5% (1.36 - 1.46V)

TPS51117 PGOOD threshold 92.5-97.5% (0.98 - 1.02V)

Fast wake glitch filter. Should

PP1V2_GPU needs to ramp

LTC2900 typical threshold is 93.5% (4.675V, 3.086V, 1.685V, 1.120V)

(Switcher limit)

200mA max output

not be necessary to stuff if GPU

before 99ms SMC timer expires.

first via RC control

Need to ensure that

(PM_S4_STATE_L)

NOTE: 0.9V/2.5V is not checked!

Other S0 Rails PWRGD Circuit

Power Control Signals

TSOT23-8

LT3470

CRITICAL

U7800

7

6

8

4

2

1 5

3

10UF

X5R

1206-1

10%
25V

C7800

1

2

6.3V

20%

22UF

CERM-X5R
805-3

C7815

1

2

200K

MF-LF
402

1%
1/16W

R7811

1

2

100K

402

5%

MF-LF

1/16W

R7865

1

2

58

58 62

35

63

49

64

34

58

58

58

63

SC70

MC74VHC1G08

U7880

3

2

1

4

5

43

34

61

58

58

10V

20%
402

CERM

0.1UF

C7880

1

2

36

7

28 23

59 49

NO STUFF

0.047UF

16V

10%
402

CERM

C7853

1

2

62

61

61

64

61

MF-LF
402

5%
1/16W

0

ISL9504A

R7866

1

2

0.1UF

402

CERM

20%
10V

C7873

1

2

1%
1/16W

402

MF-LF

93.1K

R7871

1

2

1%
MF-LF

402

1/16W

9.53K

R7870

1

2

CRITICAL

DFN

LTC2900

U7870

3

6

5

4

11

2

10

1

9

7

8

CERM

402

10%

0.047UF

16V

C7875

1

2

402

100K

1/16W

1%
MF-LF

R7874

1

2

124K

1/16W

1%

402

MF-LF

R7873

1

2

0.1UF

20%
10V

CERM

402

C7872

12

1/16W
MF-LF
402

5%

10K

R7875

1

2

CERM

10V
402

20%

0.1UF

C7871

1

2

0.1uF

10V

20%

CERM

402

C7870

1

2

58

58

2N7002DW-X-F

SOT-363

Q7851

3

5

4

76 74

SOT-363

2N7002DW-X-F

Q7851

6

2

1

100K

402

5%
1/16W
MF-LF

R7852

1

2

10K

402

5%
1/16W
MF-LF

R7854

1

2

MC74VHC1G09

SC70

U7850

3

2

1

4

5

10K

MF-LF

1/16W

402

5%

R7859

1

2

402

5%

MF-LF

1/16W

10K

R7855

1 2

6.3V

0.47UF

10%

402

CERM-X5R

C7855

1

2

0.047UF

16V

10%
402

CERM

NO STUFF

C7859

1

2

MC74VHC1G09

SC70

U7858

3

2

1

4

5

NO STUFF

1/16W
MF-LF

5%

402

0

R7860

12

62

5%

MF-LF

1/16W

402

100K

R7851

1

2

402

MF-LF

5%

1/16W

10K

R7850

1

2

SOT-363

2N7002DW-X-F

Q7850

6

2

1

46 45 28

348K

MF-LF
402

1%
1/16W

R7810

1

2

CRITICAL

S1024AS-SM

33UH-0.39A

L7810

1 2

2N7002DW-X-F

SOT-363

Q7850

3

5

4

76

22pF

CERM

402

5%

50V

C7810

1

2

100K

MF-LF

5%

402

1/16W

R7856

1

2

45

40 36 25

7

10K

MF-LF

402

5%

1/16W

R7857

1

2

45 25

7

100K

MF-LF

402

1/16W

5%

R7858

1

2

45

0.22uF

X5R
402

20%

6.3V

C7805

1

2

1/16W

5%

402

MF-LF

10K

R7853

1

2

SYNC_DATE=04/02/2007

SYNC_MASTER=M75_MLB

16

78

109

051-7261

3.425V G3Hot Supply & Power Control

=PP3V42_G3H_PWRCTL

SMC_PM_G2_EN

MAKE_BASE=TRUE

PM_G2_EN

MAKE_BASE=TRUE

PM_SLP_S3_LS5V

PM_SLP_S3_DELAY_L

MAKE_BASE=TRUE

=PP3V3_S5_PWRCTL

=PM_SLP_S3_DELAY_L

=P1V25ENET_EN

=P3V3GPU_EN

=PVCOREGPU_EN

PP1V8_S0

=P0V9S0_EN

=P1V25GPU_EN

=P1V05S0_PGOOD

=P1V5S0_PGOOD

MAKE_BASE=TRUE

P1V5P1V05S0_PGOOD

IMVP6_IMON

S0PGOOD_CRT

S0PGOOD_VPG

PP5V_S0

PP1V25_S0

MAKE_BASE=TRUE

TP_P1V8S3_PGOOD

TP_P1V25ENET_PGOOD

MAKE_BASE=TRUE

ALL_SYS_PWRGD

=P3V3ENET_EN

=P1V8S3_PGOOD

=P3V3S3_EN

=P1V25ENET_PGOOD

P3V42G3H_FB

P3V42G3H5_BOOST

=PPVIN_G3H_P3V42G3H

=P5VS3_EN

=PP3V3_S5_P1V5P1V05PG

=PP3V3_S0_ALLSYSPG

PP3V3_S0

S0PGOOD_VREF

S0PGOOD_P1V2_DIV

=GPUVCORE_EN

MAKE_BASE=TRUE

PM_GPUVCORE_EN

=P1V8GPU_EN

PM_GPUP1V8FET_EN

MAKE_BASE=TRUE

PVCOREGPU_EN_L

=PP3V3_GPU_PWRCTL

=P1V5S0_EN
=P1V05S0_EN

=PBUSVSENS_EN

=P1V25S0_EN

=ENET_VMAIN_AVLBL

=GPUVCORE_PGOOD

=PP5V_S5_PWRCTL

=P3V3S0_EN

=P5VS0_EN

=PP3V3_S0_PWRCTL

LIO_S0_EN_L

=P1V8S0_EN

PM_SLP_S3_L

MAKE_BASE=TRUE

PM_ENET_EN

MAKE_BASE=TRUE

=P1V8S3_EN

=USB_EXTA_EN
LIO_S3_EN

MAKE_BASE=TRUE

P1V8S3_EN

PM_S4_STATE_L

MAKE_BASE=TRUE

EXTGPU_PWR_EN

MAKE_BASE=TRUE

S0PGOOD_PWROK

=P3V3S5_EN

=P5VS5_EN

=P5VP3V3_EN5
=P5VP3V3_EN3

=PP3V42_G3H_REG

MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.5 mm

P3V42G3H_SW

91

8

8

8

7

8

8

63

62

8

8

8

8

8 8

8

8

Preliminary

S3
S2

D1

D2

D3

D4

GATE

S1

V-

V+

+

-

VDDP

VDD

ACLIM

ICM

ICOMP
VCOMP
VADJ
CELLS

CSOP

CHLIM

CSON

ACPRN

VREF

SGATE

CSIN

DCIN

BGATE

BOOT

UGATE

LGATE

PHASE

DCSET

PGND

THRML_PAD

DCPRN

CSIP

EN

ACSET

GND

D

SG

D

SG

D

SG

D

SG

D

SG

D

SG

D

SG

D

S G

D

G S

GND

VCC

PGOOD

OUT

FB

IN

SHDN*

I.C.

THRML

PAD

S3
S2

D1

D2

D3

D4

GATE

S1

S3
S2

D1

D2

D3

D4

GATE

S1

S3
S2

D1

D2

D3

D4

GATE

S1

TABLE_5_ITEM

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

As shown, Ichg = 4.5A max

Battery Charge Current Limit

Adapter Input Current Limit

353S1244

NC

VOLTAGE FOLLOWER GUARANTEES CURRENT LIMIT CIRCUITS

SINKING CURRENT FROM VREF.

ARE PROVIDED WITH SUFFICIENT CURRENT WITHOUT

As shown, Isys =~4.6A max

Battery Charge FETs

Energy Star LDO

PBus Supply & Battery Charger

10A MAX, LIMITED BY L7900, Q7901

SM

XW7900

1 2

402

MF-LF

1/16W

1%

3.01K

R7902

1 2

10%

CERM

1uF

6.3V
402

C7912

1

2

6.3V

10%

402

CERM

1uF

C7911

1 2

IRLML5203-2.6A

SM

S

D

G

Q7940

3

1

2

25V
CERM

20%

603

0.1UF

C7940

1

2

MF-LF

3.01K

1/16W

1%

402

R7960

1 2

16V

10%

402

CERM

0.047UF

C7961

1

2

3.16K

1/16W

1%

402

MF-LF

R7962

1 2

0.1UF

16V
X7R-CERM

10%

402

C7962

1

2

1/16W

1%

402

MF-LF

20.0K

R7963

1

2

1.96K

402

MF-LF

1/16W

1%

R7966

1

2

2525

CRITICAL

27

3W

5%
MF

R7920

1 2

1%

402

MF-LF

11.3K

1/16W

R7941

1

2

1/16W

402

MF-LF

1%

110K

R7940

1

2

CRITICAL

SO-8

SI4413ADY-E3

Q7921

5

6

7

8

4

1

2

3

8AMP-24V

CRITICAL

1206

F7902

1 2

26.7K

MF-LF
402

1%
1/16W

R7967

1

2

402

NOSTUFF

680pF

50V

10%

CERM

C7915

1 2

5%

402

MF-LF

1/16W

2.2

R7903

1 2

ISL6255A

270

MF-LF

402

5%

1/16W

R7904

1 2

NOSTUFF

0.1UF

25V

20%
603

CERM

C7907

1

2

10V

10%
402

CERM

0.22uF

C7925

1

2

1/16W

1%

402

MF-LF

470K

R7930

1

2

1/16W

0.5%

603

49.9

MF-LF

R7970

1 2

CERM

10%

603

0.0022uF

50V

C7970

1

2

100K

1/16W

1%

402

MF-LF

R7944

1

2

MF-LF

1/8W

5%

805

47

R7921

1 2

1/16W

1%

402

MF-LF

100K

R7924

1

2

1W

0.5%

0612

MF

0.02

R7907

1 2

SM

XW7901

1

2

SM

XW7902

1

2

1SS355

SOD-323

D7921

1 2

CRITICAL

POLY

25V

20%

22UF

CASE-D2-LF

C7908

1

2

16V

10%
603

X5R

1UF

C7910

1

2

LFPAK

RJK0305DPB

CRITICAL

Q7901

5

4

1 2 3

CRITICAL

RJK0305DPB

LFPAK

Q7902

5

4

1 2 3

1/16W

1%

402

MF-LF

3.48K

R7968

1

2

402

MF-LF

1/16W

5%

10K

R7969

1

2

10%
16V

402

X5R

0.1uF

C7941

1

2

1/16W

5%

402

MF-LF

10K

R7979

1

2

SM

XW7904

1

2

SM

XW7903

1

2

1/16W

1%

402

MF-LF

56.2K

ISL6257H

R7992

1

2

ISL6255A

34.8K

MF-LF
402

1%
1/16W

R7993

1

2

SC70-5

HPA00141AIDCKR

CRITICAL

U7901

1

3

4

2

5

0.1UF

10V

20%
402

CERM

C7980

1

2

25V

20%

CASE-D2-LF

POLY

22UF

CRITICAL

C7906

1

2

25V

10%
805

X5R-CERM

2.2UF

CRITICAL

C7916

1

2

CRITICAL

2.2UF

X5R-CERM

25V

10%
805

C7917

1

2

25V

20%

CASE-D2-LF

POLY

22UF

CRITICAL

C7905

1

2

ELEC

20%
16V

100UF

NOSTUFF

6.3X5.5SM1

CRITICAL

C7909

1

2

CRITICAL

4.7UH-10.2A

FDA1254-SM

L7900

1

2

3

ISL6257H

402

CERM

470PF

10%
50V

C7990

1

2

402

10%
50V

ISL6255A

0.0033uF

CERM

C7991

1

2

ISL6255A

ISL6255AHRZ

CRITICAL

QFN

U7900

8

23
27

17

14

2

7

20

19

22

21

25

24
28

1

10

5

3

12

11

16

18

29

15

9

4

26

13

6

SOT563

SSM6N15FE

Q7960

6

2

1

SSM6N15FE

SOT563

Q7960

3

5

4

SOT563

SSM6N15FE

Q7961

6

2

1

SSM6N15FE

SOT563

Q7961

3

5

4

BAV99T-X-F

SOT-523-3

D7940

1

2

3

SOT563

SSM6N15FE

Q7924

3

5

4

SOT563

SSM6N15FE

Q7922

3

5

4

SOT563

SSM6N15FE

Q7922

6

2

1

SSM6N15FE

SOT563

Q7924

6

2

1

SOD-VESM

SSM3K15FV

Q7950

3

1

2

1/16W

1%

402

MF-LF

100K

R7950

1

2

1UF

X5R
603

10%
25V

C7950

1

2

603

25V

10%
X5R

1UF

C7951

1

2

1/16W

402

200K

1%

MF-LF

R7952

1

2

19.6K

1%

MF-LF

402

1/16W

R7953

1

2

SOT-323

BAT54CW-X-F

D7950

1

2

3

MAX8719

TDFN

U7950

3

2

7

1

8

5

6

9

4

1/16W

5%

402

MF-LF

100K

R7954

1

2

590

1%
MF-LF

1/16W
402

R7964

1

2

MMBZ5235B

CRITICAL

SOT23

D7903

1 3

SO-8

SI4413ADY-E3

CRITICAL

Q7970

5

6

7

8

4

1

2

3

402

470K

5%

MF-LF

1/16W

R7971

1 2

330K

1/16W
MF-LF

402

5%

R7972

1 2

0.1UF

402

25V
X5R

10%

C7971

1 2

0.033uF

16V

10%

402

X5R

C7900

1 2

1000PF

25V
402

10%
X7R

C7901

12

CRITICAL

SI4413ADY-E3

SO-8

Q7900

5

6

7

8

4

1

2

3

NOSTUFF

1/16W

1%

402

MF-LF

100K

R7910

1

2

10V

20%

402

CERM

0.1UF

C7904

1

2

CRITICAL

B0530WXF

SOD-123

D7900

12

1/16W

5%

402

MF-LF

4.7

R7900

1 2

25V

20%

603

CERM

0.1UF

C7903

1 2

0.0082uF

402

25V

10%
X7R

C7902

1

2

5%

402

18

1/16W
MF-LF

R7905

1 2

1W

0.5%

0612

MF

0.01

R7908

1 2

MF-LF

1/16W

5%

402

2.2

R7906

1 2

SI4413ADY-E3

SO-8

CRITICAL

Q7920

5

6

7

8

4

1

2

3

1/16W

5%

402

MF-LF

330K

R7931

1

2

1/16W

1%

402

39.2K

MF-LF

R7922

1

2

1/16W

1%

402

MF-LF

35.7K

R7923

1

2

16V

10%

402

CERM

0.01uF

C7920

1

2

402

0.1uF

10%
X5R

16V

C7921

1

2

NOSTUFF

16V

20%

402

CERM

0.01UF

C7924

1

2

NOSTUFF

16V

10%

402

CERM

0.01UF

C7922

1

2

10%

0.001UF

402

CERM

50V

C7927

1

2

PBus Supply & Batt. Charger

SYNC_MASTER=M75_LIO

051-7261

16

109

79

SYNC_DATE=03/08/2007

0 OHM,5%,1/16W,0402,SMD,LF

116S0004

R7904

1

ISL6257H

ISL6257H,BATT CHGR,28P,QFN,LF

353S1510

U7900

1

CRITICALISL6257H

MIN_LINE_WIDTH=0.6mm

PPVBATT_G3H_FET

MIN_NECK_WIDTH=0.25mm
VOLTAGE=12.6V

CHGR_SGND

=PPVBAT_G3H_CHGR_REG

CHGR_ICM_R

CHGR_SGND

=PP18V5_G3H_CHGR

CHGR_PHASE

MIN_NECK_WIDTH=0.2mm

MIN_LINE_WIDTH=0.6mm

SWITCH_NODE=TRUE

CHGR_LGATE

MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.2mm

CHGR_SGND

CHGR_ICOMP

CHGR_ACLIM

CHGR_ICM

CHGR_VDD

CHGR_ACSET

CHGR_VCOMP

CHGR_DCIN

CHGR_CHLIM
CHGR_VREF

LDO_FDBK

=PPVBAT_G3H_CHGR_REG

MIN_NECK_WIDTH=0.25mm
VOLTAGE=12.6V

MIN_LINE_WIDTH=0.6mm

PPVBATT_G3H_PRE

PPVBATT_G3H_FET_D

MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.25mm
VOLTAGE=12.6V

INRUSH_EN_DIV_L

=BATT_POS

MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.25mm

=PPVBATT_G3H_LIO_CONN

=BATT_NEG

=GND_BATT_CHGND

CHGR_ACSET_D

SMC_BATT_TRICKLE_EN_L

MIN_NECK_WIDTH=0.2mm

MIN_LINE_WIDTH=0.6mm

CHGR_UGATE

CHGR_ACPRN
CHGR_ACSET

CHGR_BOOT

MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.2mm

MIN_NECK_WIDTH=0.2mm

MIN_LINE_WIDTH=0.2mm

CHGR_SGATE

CHGR_VDDP

CHGR_CSI_N

CHGR_DCIN

MIN_NECK_WIDTH=0.25mm

MIN_LINE_WIDTH=0.6mm

PPVDCIN_G3H_R

NO_TEST=TRUE

CHGR_CSI_R_N

=PP3V42_G3H_ACIN

CHGR_VREF_VF

=PP3V42_G3H_ACIN

CHGR_SGND

=PP3V42_G3H_ACIN

SMC_SYS_ISET_L

=PP3V42_G3H_ACIN

CHGR_VREF

CHGR_PHASE_R

CHGR_CSI_P

NO_TEST=TRUE

CHGR_CSO_R_P

CHGR_BOOT_R

CHGR_VDD

CHGR_SGND

SMC_SYS_ISET

SMC_BATT_ISET

MIN_NECK_WIDTH=0.25mm

MIN_LINE_WIDTH=0.6mm

PPVDCIN_G3H_PRE

CHGR_CSO_P

CHGR_CSO_N

CHGR_VREF_VF

PPVBAT_G3H_CHGR_OUT

MIN_NECK_WIDTH=0.25mm

MIN_LINE_WIDTH=0.6mm

CHGR_VCOMP_C

CHGR_CSO_R_N

NO_TEST=TRUE

NO_TEST=TRUE

NC_CHGR_BGATE

CHGR_ACLIM_R

CHGR_ACLIM

TP_CHGR_DCSET

TP_CHGR_VADJ

CHGR_VDDP

CHGR_ACPRN

TCHG_EN_DIV2_L

SMC_BC_ACOK

SMC_BATT_CHG_EN

CHG_EN_DIV2_L

CHGR_ACPRN

MIN_NECK_WIDTH=0.25mm

PPVBATT_G3H_DIO

VOLTAGE=12.6V

MIN_LINE_WIDTH=0.5mm

TP_CHGR_DCPRN

CHGR_EN

NC

MIN_NECK_WIDTH=0.2mm

MIN_LINE_WIDTH=0.2mm

CHG_EN_DIV_L

PBUS_LDO_EN

=PP18V5_G3H_CHGR

NC

MIN_NECK_WIDTH=0.2MM

LDO_OUT

MIN_LINE_WIDTH=0.5MM

CHGR_VDD

CHGR_CSO_R_N

CHGR_EN

CHGR_SGND

CHGR_CHLIM_R

SMC_BATT_ISET_L

CHGR_CSO_N

CHGR_CSO_P

CHGR_SGND

CHGR_CHLIM

CHGR_VREF_VF

MIN_LINE_WIDTH=0.2mm
MIN_NECK_WIDTH=0.2mm

TCHG_EN_DIV_L

PPVBAT_G3H_CHGR_OUT

57

67

67

67

67

46

67

67

67

57

57

46

57

57

57

57

67

45

46

67

67

67

8

67

57

67

67

67

67

67

67

67

8

7

8

7

9

45

67

67

67

67

53

8

67

8

67

8

8

67

53

53

67

67

45

45

67

67

67

67

53

67

67

67

34

45

67

67

9

57

67

53

67

67

67

67

67

67

67

67

Preliminary

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

PEX_TX0

PEX_TX0_L

PEX_RX4

PEX_RX0

PEX_TX1PEX_RX1

PEX_RX2 PEX_TX2

PEX_RX3 PEX_TX3

PEX_TX4

PEX_TX5PEX_RX5

PEX_TX6PEX_RX6

PEX_RX7 PEX_TX7

PEX_TX8PEX_RX8

PEX_TX9PEX_RX9

PEX_TX10PEX_RX10

PEX_TX11PEX_RX11

PEX_TX12PEX_RX12

PEX_TX13PEX_RX13

PEX_TX14PEX_RX14

PEX_TX15PEX_RX15

PEX_TSTCLK_OUTPEX_REFCLK

PEX_TX1_L

PEX_TX2_L

PEX_TX3_L

PEX_TX4_L

PEX_TX5_L

PEX_TX6_L

PEX_TX7_L

PEX_TX8_L

PEX_TX9_L

PEX_TX10_L

PEX_TX11_L

PEX_TX12_L

PEX_TX13_L

PEX_TX14_L

PEX_TX15_L

PEX_TSTCLK_OUT_L

PEX_RST_L

PEX_REFCLK_L

PEX_RX15_L

PEX_RX14_L

PEX_RX13_L

PEX_RX12_L

PEX_RX11_L

PEX_RX10_L

PEX_RX9_L

PEX_RX8_L

PEX_RX7_L

PEX_RX6_L

PEX_RX5_L

PEX_RX4_L

PEX_RX3_L

PEX_RX2_L

PEX_RX1_L

PEX_RX0_L

PCI-EXPRESS BUS INTERFACE

NC

PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5
PEX_IOVDD_6

PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8

PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11

PEX_PLLAVDD
PEX_PLLDVDD

PEX_PLLGND

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN
IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

PEX 1.2V Current = 2A

250mA

Page Notes

Power aliases required by this page:

(NONE)

(NONE)

180mA

20mA

1500mA

BOM options provided by this page:

Signal aliases required by this page:

- =PP1V2_GPU_PEX_IOVDD

- =PP1V2_GPU_PEX_IOVDDQ

- =PP1V2_GPU_PEX_PLLXVDD

84 15

X5R 402

0.1uF

16V10%

C8081

1 2

0.1uF

X5R16V10% 402

C8082

1 2

84 15

84 15

0.1uF

40216V10% X5R

C8079

1 2

402

0.1uF

X5R16V10%

C8080

1 2

84 15

84 15

402

0.1uF

X5R16V10%

C8077

1 2

402X5R16V10%

0.1uF

C8078

1 2

84 15

84 15

402

0.1uF

X5R16V10%

C8075

1 2

402

0.1uF

X5R16V10%

C8076

1 2

84 15

84 15

402

0.1uF

X5R16V10%

C8073

1 2

402

0.1uF

X5R16V10%

C8074

1 2

84 15

40210% 16V X5R

0.1uF

C8020

1 2

84 15

402

0.1uF

X5R16V10%

C8071

1 2

402

0.1uF

X5R16V10%

C8072

1 2

84 15

84 15

402

0.1uF

X5R16V10%

C8069

1 2

402

0.1uF

X5R16V10%

C8070

1 2

84 15

84 15

402

0.1uF

X5R16V10%

C8067

1 2

10%

0.1uF

16V X5R 402

C8021

1 2

402

0.1uF

X5R16V10%

C8068

1 2

84 15

84 15

402

0.1uF

X5R16V10%

C8065

1 2

402

0.1uF

X5R16V10%

C8066

1 2

84 15

84 15

402

0.1uF

X5R16V10%

C8063

1 2

402

0.1uF

X5R16V10%

C8064

1 2

84 15

10% 16V X5R

0.1uF

402

C8050

1 2

84 15

402

0.1uF

X5R16V10%

C8061

1 2

0.1uF

402X5R16V10%

C8062

1 2

84 15

84 15

402

0.1uF

X5R16V10%

C8059

1 2

402

0.1uF

X5R16V10%

C8060

1 2

84 15

84 15

402

0.1uF

X5R16V10%

C8057

1 2

10% 16V X5R 402

0.1uF

C8051

1 2

0.1uF

402X5R16V10%

C8058

1 2

10% 16V X5R

0.1uF

402

C8048

1 2

10% 16V X5R

0.1uF

402

C8049

1 2

16V X5R10%

0.1uF

402

C8046

1 2

NB8P-GS-W-A2

BGA

(1 OF 8)

OMIT

U8000

AH14
AJ14

AH15

AK13
AK14

AM14
AM15

AL23
AL24

AM24
AM25

AK25
AK26

AL26
AL27

AM27
AM28

AL28
AL29

AL15
AL16

AK16
AK17

AL17
AL18

AM18
AM19

AK19
AK20

AL20
AL21

AM21
AM22

AK22
AK23

AM12
AM11

AJ15
AK15

AH16
AG16

AG23
AH23

AK24
AJ24

AJ25
AH25

AH26
AG26

AK27
AJ27

AJ28
AH27

AG17
AH17

AG18
AH18

AK18
AJ18

AJ19
AH19

AG20
AH20

AG21
AH21

AK21
AJ21

AJ22
AH22

NB8P-GS-W-A2

BGA

(2 OF 8)

OMIT

U8000

A26

M5
U6
V1
V3
V4
V5
V6
W1
W3
W4

A28

W5
Y5

Y6
AC26
AD26
AE26
AG12
AH13
AH31
AH32

B32

AM8
AM9

D1

D31
D32

F1

F6

G8

AD23
AF23
AF24
AF25
AG24
AG25

AC16

AF21
AF22

AC17
AC21
AC22
AE18
AE21
AE22
AF12
AF18

AF15
AE15
AE16

6.3V

20%

603

4.7UF

CERM

C8001

1

2

6.3V

10%

1UF

402

CERM

C8003

1

2

10V

0.1UF

20%
CERM

402

C8004

1

2

40210% 16V X5R

0.1uF

C8047

1 2

10V

0.1UF

402

CERM

20%

C8005

1

2

603

6.3V

20%

4.7UF

CERM

C8016

1

2

CERM

4.7UF

20%

6.3V
603

C8015

1

2

CERM-X5R

22UF

6.3V
805

20%

C8000

1

2

10% 16V X5R 402

0.1uF

C8044

1 2

CERM
402

10%

6.3V

1UF

C8002

1

2

CERM-X5R

20%

805

6.3V

22UF

C8006

1

2

4.7UF

603

20%

6.3V
CERM

C8007

1

2

402

1UF

6.3V

10%
CERM

C8008

1

2

CERM
402

1UF

10%

6.3V

C8009

1

2

402

CERM

20%

0.1UF

10V

C8010

1

2

402

0.1UF

10V

20%
CERM

C8011

1

2

CERM
402

10V

20%

0.1UF

C8017

1

2

10% X5R

0.1uF

40216V

C8045

1 2

CERM

4.7UF

20%

6.3V
603

C8013

1

2

0.1UF

20%
10V

402

CERM

C8014

1

2

CERM

4.7UF

20%

6.3V
603

C8012

1

2

0603

10NH-600MA

L8015

1 2

0603

10NH-600MA

L8012

1 2

10% 16V X5R

0.1uF

402

C8042

1 2

10% 16V X5R

0.1uF

402

C8043

1 2

10% 16V X5R

0.1uF

402

C8040

1 2

10% 16V X5R

0.1uF

402

C8041

1 2

10% 16V X5R

0.1uF

402

C8038

1 2

10% 16V X5R 402

0.1uF

C8039

1 2

10% 16V X5R

0.1uF

402

C8036

1 2

10% 16V X5R

0.1uF

402

C8037

1 2

10% 16V X5R

0.1uF

402

C8034

1 2

10% 16V X5R

0.1uF

402

C8035

1 2

10% 16V X5R

0.1uF

402

C8032

1 2

10% X5R

0.1uF

40216V

C8033

1 2

10% 16V X5R

0.1uF

402

C8030

1 2

10% 16V X5R 402

0.1uF

C8031

1 2

10% 16V X5R

0.1uF

402

C8028

1 2

10% 16V X5R

0.1uF

402

C8029

1 2

10% 16V X5R

0.1uF

402

C8026

1 2

0.1uF

10% 16V X5R 402

C8027

1 2

16V X5R

0.1uF

40210%

C8024

1 2

10% 16V X5R

0.1uF

402

C8025

1 2

0.1uF

10% X5R 40216V

C8022

1 2

0.1uF

10% 16V X5R 402

C8023

1 2

84 15

84 15

84 15

84 15

84 15

84 15

84 15

84 15

84 15

84 15

84 15

84 15

84 15

84 15

84 15

84 15

84 15

84 15

84 15

84 15

84 15

84 15

84 15

84 15

84 15

84 15

84 15

84 15

84 15

84 15

84 15

84 15

30

9

30

9

28

7

10% 16V X5R

0.1uF

402

C8055

1 2

10% 16V X5R

0.1uF

402

C8056

1 2

84 15

84 15

84 15

84 15

402

0.1uF

X5R16V10%

C8085

1 2

402X5R16V10%

0.1uF

C8086

1 2

84 15

84 15

402

0.1uF

X5R16V10%

C8083

1 2

402

0.1uF

X5R16V10%

C8084

1 2

84 15

051-7261

16

109

80

SYNC_MASTER=M75_MLB

SYNC_DATE=03/19/2007

NV G84M PCI-E

PEG_R2D_P<5>

PEG_R2D_P<3>

PEG_R2D_C_N<3>

TP_GPU_PEXTSTCLK_N

=PP1V2_GPU_PEX_PLLXVDD

PEG_R2D_C_N<15>

PEG_R2D_C_P<7>

PEG_R2D_N<6>

PEG_D2R_C_N<8>

PEG_D2R_C_N<11>

PEG_D2R_N<5>

PEG_D2R_C_P<14>

PEG_D2R_N<8>

PEG_D2R_P<9>

PEG_D2R_P<10>

PEG_D2R_P<13>

PEG_D2R_N<6>

PEG_D2R_C_P<7>

PEG_D2R_N<1>

PEG_D2R_N<12>

PEG_D2R_P<0>

PEG_D2R_N<0>

PEG_D2R_P<1>

PEG_D2R_N<2>

PEG_D2R_P<2>

PEG_D2R_N<3>

PEG_D2R_P<3>

PEG_D2R_N<4>

PEG_D2R_P<4>

PEG_D2R_P<5>

PEG_D2R_P<6>

PEG_D2R_P<7>

PEG_D2R_N<7>

PEG_D2R_P<8>

PEG_D2R_N<9>

PEG_D2R_N<10>

PEG_D2R_N<11>

PEG_D2R_P<11>

PEG_D2R_P<12>

PEG_D2R_P<14>

PEG_D2R_P<15>

PEG_D2R_N<14>

PEG_D2R_N<15>

PEG_D2R_N<13>

PEG_D2R_C_P<0>
PEG_D2R_C_N<0>

PEG_D2R_C_P<1>

PEG_D2R_C_P<2>

PEG_D2R_C_P<3>

PEG_D2R_C_P<4>

PEG_D2R_C_P<5>

PEG_D2R_C_P<6>

PEG_D2R_C_P<8>

PEG_D2R_C_P<9>

PEG_D2R_C_P<10>

PEG_D2R_C_P<11>

PEG_D2R_C_P<12>

PEG_D2R_C_N<1>

PEG_D2R_C_N<2>

PEG_D2R_C_N<3>

PEG_D2R_C_N<4>

PEG_D2R_C_N<5>

PEG_D2R_C_N<6>

PEG_D2R_C_N<7>

PEG_D2R_C_N<9>

PEG_D2R_C_N<10>

PEG_D2R_C_N<12>

PEG_D2R_C_N<14>

PEG_R2D_N<0>

PEG_R2D_N<3>

PEG_R2D_N<2>

PEG_R2D_N<1>

PEG_R2D_N<4>

PEG_R2D_N<7>

PEG_R2D_N<8>

PEG_R2D_N<9>

PEG_R2D_N<5>

PEG_R2D_N<12>

PEG_R2D_N<15>

PEG_R2D_N<14>

PEG_R2D_P<0>

PEG_R2D_P<1>

PEG_R2D_P<2>

PEG_R2D_P<4>

PEG_R2D_C_N<0>

PEG_R2D_C_P<0>

PEG_R2D_C_N<1>

PEG_R2D_C_N<2>

PEG_R2D_C_P<2>

PEG_R2D_C_P<3>

PEG_R2D_C_P<4>

PEG_R2D_C_P<5>

PEG_R2D_C_N<4>

PEG_R2D_P<6>

PEG_R2D_P<7>

PEG_R2D_P<8>

PEG_R2D_P<9>

PEG_R2D_P<10>

PEG_R2D_P<12>

PEG_R2D_P<13>

PEG_R2D_P<14>

PEG_R2D_C_P<6>

PEG_R2D_C_N<5>

PEG_R2D_C_N<6>

PEG_R2D_C_N<7>

PEG_R2D_C_N<8>

PEG_R2D_C_P<8>

PEG_R2D_C_N<9>

PEG_R2D_C_P<9>

PEG_R2D_C_N<10>

PEG_R2D_C_P<10>

PEG_R2D_C_P<11>

PEG_R2D_C_P<13>

PEG_R2D_C_P<14>

PEG_R2D_C_N<13>

PEG_R2D_P<15>

PEG_R2D_C_P<15>

PEG_R2D_C_N<14>

PEG_CLK100M_GPU_P

GPU_RESET_L

PEG_D2R_C_P<15>
PEG_D2R_C_N<15>

TP_GPU_PEXTSTCLK_P

PEG_CLK100M_GPU_N

PEG_R2D_C_N<12>

PEG_R2D_C_P<12>

PEG_D2R_C_N<13>

PEG_R2D_N<13>

PEG_R2D_C_N<11>

PEG_D2R_C_P<13>

PEG_R2D_N<11>

PEG_R2D_P<11>

PEG_R2D_N<10>

PP1V2_GPU_PEX_PLLDVDD_F

MIN_NECK_WIDTH=0.25 mm
VOLTAGE=1.2V

MIN_LINE_WIDTH=0.25 mm

VOLTAGE=1.2V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

PP1V2_GPU_PEX_PLLAVDD_F

=PP1V2_GPU_PEX_IOVDDQ
=PP1V2_GPU_PEX_IOVDD

PEG_R2D_C_P<1>

84

84

8

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84 84

84

84 84

84

84

84

84

8

8

Preliminary

FBVTT

FBVDDQ

GND_SENSE

VDD_SENSE

VDD_LP

VDD

FBVDD

GND

GND

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

???A @ ???/???MHz Core/Mem Clk for VDD

- =PPVCORE_GPU

- =PP1V8_GPU_FBVDDQ

(NONE)
BOM options provided by this page:

(NONE)

Signal aliases required by this page:

Power aliases required by this page:

Page Notes

???A @ ???MHz 1.8V GDDR3

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC
NC
NC
NC

NC

402

10%

1UF

6.3V
CERM

C8101

1

2

402

10%

1UF

6.3V
CERM

C8100

1

2

NB8P-GS-W-A2

BGA

(7 OF 8)

OMIT

U8000

A12

A9
AA32
AD32
AG32
AK32
C32
F32
J32
M32
R32

A18
A21
A24
A27
A3
A30
A6

AA25

G22
H11
H12
H15
H18
H21
H22
L25
L26
M25

AA26

M26
R25
R26
V25
V26

AB25
AB26
G11
G12
G15
G18
G21

AA23

K12
K21
K22
K24
K9
L23
M23
T25
U25

AB23
H16
H17
J10
J23
J24
J9
K11

M21

K16

P16
P17
P19
R16
R17
T13
T14
T15
T18
T19

K17

U13
U14
U15
U18
U19
V16
V17
W13
W14
W16

N13

W17
W19
Y13
Y14
Y16
Y17
Y19
Y20

N14
N16
N17
N19
P13
P14

P20
T20
T23
U20
U23
W20

N20

NB8P-GS-W-A2

(8 OF 8)

BGA

OMIT

U8000

AE17

AG11

J16
J17
J2
J31
K10
K23
K29
K4
L27
L6

AB27

M12
M2
M31
N15
N18
N29
N4
P15
P18
P27

AB6

P6
R13
R14
R15
R18
R19
R2
R20
R31
T16

AC10

T17
T24
T29
T4
U16
U17
U24
U29
U8
V13

AC23

V14
V15
V18
V19
V2
V20
V31
W15
W18
W27

AC29

W6
Y15
Y18
Y29
Y4

AC4
AD16
AD17

AD2

AE27

AD31
AA12

AA2
AA21
AA31
AG13
AG14
AG15
AG19

AG2

AE6

AG22
AG31

AG8
AH24
AJ10
AJ13
AJ16
AJ17
AJ20
AJ23

AF11

AJ26
AJ29

AJ4

AJ7

AK2
AK28
AK31
AL10
AL11
AL14

AF26

AL19
AL22
AL25

AL3

AL6

AL9
AM10
AM13
AM16
AM17

AF29

AM20
AM23
AM26
AM29

B12

B15

B18

B21

B24

B27

AF4

B3

B30

B6
B9

C2
C31
D10
D13

D16
D17

AF7

D20
D23
D26
D29
D4
D7
F11
F14
F19
F2

AG10

F22
F25
F31
F8
G26
G29
G4
G7
H27
H6

402

10%

1UF

6.3V
CERM

C8102

1

2

CERM
402

10V

20%

0.1UF

C8107

1

2

10V

0.1UF

402

CERM

20%

C8112

1

2

0.1UF

CERM
402

10V

20%

C8117

1

2

402

CERM

20%

0.1UF

10V

C8106

1

2

CERM
402

20%

0.1UF

10V

C8105

1

2

402

0.1UF

CERM

10V

20%

C8110

1

2

10V

0.1UF

CERM
402

20%

C8111

1

2

0.1UF

402

CERM

10V

20%

C8116

1

2

0.1UF

CERM
402

10V

20%

C8115

1

2

20%

402

CERM

0.1UF

10V

C8104

1

2

0.1UF

402

CERM

10V

20%

C8109

1

2

0.1UF

CERM
402

10V

20%

C8114

1

2

0.1UF

402

CERM

10V

20%

C8113

1

2

0.1UF

CERM
402

10V

20%

C8108

1

2

402

20%

0.1UF

CERM

10V

C8103

1

2

0.47UF

6.3V

10%

CERM-X5R

402

C8160

1

2

CERM-X5R

10%

6.3V

0.47UF

402

C8166

1

2

0.1UF

20%
10V

402

CERM

C8159

1

2

CERM

6.3V

20%

603

4.7UF

C8151

1

2

0.1UF

20%
10V

402

CERM

C8158

1

2

10V

20%

0.1UF

402

CERM

C8165

1

2

10V

20%

0.1UF

402

CERM

C8164

1

2

CERM

6.3V

20%

603

4.7UF

C8150

1

2

0.1UF

20%
10V

402

CERM

C8157

1

2

10V

20%

0.1UF

CERM

402

C8163

1

2

10V

20%

0.1UF

402

CERM

C8162

1

2

0.1UF

20%
10V

402

CERM

C8156

1

2

10V

20%
CERM

402

0.1UF

C8122

1

2

0.1UF

10V

20%

402

CERM

C8121

1

2

0.1UF

10V

20%
CERM

402

C8120

1

2

20%

0.1UF

10V
CERM
402

C8119

1

2

0.1UF

10V

20%

402

CERM

C8118

1

2

0.47UF

6.3V

10%

CERM-X5R

402

C8161

1

2

CERM-X5R

10%

6.3V

0.47UF

402

C8167

1

2

402

0.47UF

6.3V

10%

CERM-X5R

C8169

1

2

402

0.47UF

6.3V

10%

CERM-X5R

C8168

1

2

402

0.47UF

6.3V

10%

CERM-X5R

C8171

1

2

402

0.47UF

6.3V

10%

CERM-X5R

C8170

1

2

SYNC_MASTER=M75_MLB

NV G84M Core/FB Power

81

109

051-7261

16

SYNC_DATE=03/19/2007

TP_GPU_GND_SENSE

TP_GPU_VDD_SENSE

=PPVCORE_GPU

=PP1V8_GPU_FBVDDQ

8

8

Preliminary

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT
OUT

OUT

OUT

OUT

OUT
OUT

OUT

OUT

OUT
OUT

BI

BI

BI

BI

BI

BI

BI
BI

BI

BI

BI

BI

BI

BI
BI

BI

BI

BI

BI
BI

BI

BI

BI
BI

BI

BI
BI

BI
BI

BI
BI

BI

BI
BI

BI

BI

BI

BI
BI

BI
BI

BI

BI

BI

BI

BI

BI

BI

BI

BI
BI

BI

BI

BI

BI
BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

FBAD20

FBAD22

FBAD1
FBAD2

FBAD18

FBAD0

FBAD3

FBAD5
FBAD6
FBAD7
FBAD8
FBAD9
FBAD10
FBAD11
FBAD12
FBAD13
FBAD14
FBAD15
FBAD16
FBAD17

FBAD19

FBAD21

FBAD23
FBAD24
FBAD25
FBAD26
FBAD27

FBAD29
FBAD30

FBAD32
FBAD33
FBAD34
FBAD35
FBAD36
FBAD37
FBAD38
FBAD39
FBAD40
FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
FBAD48
FBAD49
FBAD50
FBAD51
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63

FBA_PLLAVDD
FBA_PLLGND

FBAD31

FBCAL_PD_VDDQ

FBCAL_PU_GND

FBAD28

FBAD4

FBADQS_WP0
FBADQS_WP1

FBADQS_WP3

FBADQS_WP2

FBADQS_WP6

FBADQS_WP5

FBADQS_WP4

FBADQS_WP7

FBA_DEBUG

FBADQS_RN2

FBADQS_RN1

FBADQS_RN0

FBADQS_RN4

FBADQS_RN3

FBADQS_RN5

FBADQS_RN7

FBADQS_RN6

FBA_CLK0

FBA_CLK0_L

FBA_CLK1_L

FBA_CLK1

FBADQM1

FBADQM0

FBADQM3

FBADQM2

FBADQM6

FBADQM5

FBADQM4

FBADQM7

FBA_CMD0

FBA_CMD2

FBA_CMD1

FBA_CMD5

FBA_CMD3
FBA_CMD4

FBA_CMD7

FBA_CMD6

FBA_CMD8

FBA_CMD10

FBA_CMD9

FBA_CMD13

FBA_CMD12

FBA_CMD11

FBA_CMD15

FBA_CMD14

FBA_CMD18

FBA_CMD17

FBA_CMD16

FBA_CMD20

FBA_CMD19

FBA_CMD23

FBA_CMD22

FBA_CMD21

FBA_CMD25

FBA_CMD24

FBA_CMD28

FBA_CMD26
FBA_CMD27

READ STROBE

WRITE STROBE

MEMORY INTERFACE A

OUT

OUT

OUT
OUT

OUT
OUT

OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT

OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT

FB_VREF

FBCAL_TERM_GND

FBC_PLLGND

FBC_PLLAVDD

FBCD63

FBCD62

FBCD61

FBCD60

FBCD59

FBCD58

FBCD57

FBCD56

FBCD55

FBCD53

FBCD51

FBCD50

FBCD49

FBCD48

FBCD47

FBCD46

FBCD45

FBCD44

FBCD43

FBCD41

FBCD40

FBCD39

FBCD38

FBCD37

FBCD36

FBCD35

FBCD34

FBCD33

FBCD32

FBCD31

FBCD30

FBCD29

FBCD28

FBCD27

FBCD26

FBCD25

FBCD24

FBCD23

FBCD22

FBCD21

FBCD20

FBCD19

FBCD18

FBCD17

FBCD16

FBCD15

FBCD11

FBCD9

FBCD8

FBCD7

FBCD6

FBCD5

FBCD4

FBCD3

FBCD2

FBCD1

FBCD10

FBCD42

FBCD0

FBCD54

FBCD52

FBCD13

FBCD12

FBCD14

FBCDQS_RN0
FBCDQS_RN1
FBCDQS_RN2
FBCDQS_RN3
FBCDQS_RN4
FBCDQS_RN5
FBCDQS_RN6
FBCDQS_RN7

FBCDQS_WP1
FBCDQS_WP2

FBCDQS_WP0

FBCDQS_WP4

FBCDQS_WP3

FBCDQS_WP6
FBCDQS_WP7

FBCDQS_WP5

FBC_DEBUG

FBCDQM7

FBC_CLK1

FBC_CLK0

FBC_CLK0_L

FBC_CLK1_L

FBCDQM0
FBCDQM1
FBCDQM2
FBCDQM3
FBCDQM4
FBCDQM5
FBCDQM6

FBC_CMD4

FBC_CMD3

FBC_CMD6

FBC_CMD5

FBC_CMD9

FBC_CMD8

FBC_CMD7

FBC_CMD11

FBC_CMD10

FBC_CMD14

FBC_CMD13

FBC_CMD12

FBC_CMD16

FBC_CMD15

FBC_CMD19

FBC_CMD18

FBC_CMD17

FBC_CMD21

FBC_CMD20

FBC_CMD22

FBC_CMD24

FBC_CMD23

FBC_CMD27

FBC_CMD26

FBC_CMD25

FBC_CMD28

FBC_CMD1

FBC_CMD0

FBC_CMD2

MEMORY INTERFACE B

WRITE STROBE

READ STROBE

OUT

OUT

OUT

OUT

BI
BI
BI
BI
BI
BI
BI
BI

IN
IN
IN
IN
IN
IN

IN

IN

OUT

OUT

OUT

OUT

OUT
OUT
OUT
OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

IN
IN
IN
IN
IN
IN
IN
IN

OUT
OUT
OUT

OUT

OUT

OUT
OUT
OUT

G

D

S

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NC

NC

- =PP1V2_GPU_FBPLLAVDD

(NONE)

(NONE)

- =PP1V8_GPU_FBIO

Power aliases required by this page:

Signal aliases required by this page:

BOM options provided by this page:

Page Notes

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

74

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 71

90 71

90 71

90 71

90 71

NB8P-GS-W-A2

BGA

OMIT

(3 OF 8)

U8000

P28
R28
Y27
AA27

P32
U27

T31
U32
W29
W30
T27
V28
V30
U31
R27
V29

P31

T30
W28
R29
R30
P29
U28
Y32
Y30
V32

U30
Y31
W32
W31
T32
V27
T28

AC27

G25
G24

N27
M27

N30
N32
L31
L30
J30
L32
H30
K30
H31
F30

N28

H32
E31
D30
E30
H28
H29
E29
J27
F27
E27

L29

E28

F28
AD29
AE29
AD28
AC28
AB29
AA30

Y28
AB30

K27

AM30
AF30
AJ31
AJ30
AJ32
AK29
AM31
AL30
AE32
AE30

K28

AE31
AD30
AC31
AC32
AB32
AB31
AG27
AF28
AH28
AG28

J29

AG29
AD27
AF27
AE28

J28

P30

N31

M29
M30
G30
F29
AA29
AK30
AC30
AG30

M28
K32
G31
G27
AA28
AL31
AF31
AH29

L28
K31
G32
G28
AB28
AL32
AF32
AH30

K26
H26

402

CERM

10V

0.1UF

20%

C8201

1

2

90 71

74

90 71

90 71

90 71

90 71

90 71

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

74

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

74

10K

402

MF-LF

1/16W

5%

R8200

1

2

90 72

10K

402

MF-LF

1/16W

5%

R8250

1

2

1/16W
MF-LF

1%

402

40.2

R8292

12

24.9

1/16W

402

MF-LF

1%

R8291

1

2

NB8P-GS-W-A2

BGA

(4 OF 8)

OMIT

U8000

E32

E13
F13
F18
E17

C13
A16

C15
B16
F17
C19
D15
C17
A17
C16
D14
F16

A13

C14
C18
E14
B13
E15
F15
A20
C20
A15

B17
B20
A19
B19
B14
E16
A14

F12

G10

G9

J26

B7
A7

D12

D9
E12
D11

E8

D8

E7

F7

D6

D5

C7

D3

E4

C3

B4
C10
B10

C8
A10
C11
C12

A2

A11
B11
B28
C27
C26
B26
C30
B31
C29
A31

B2

D28
D27
F26
D24
E23
E26
E24
F23
B23
A23

C4

C25
C23
A22
C22
C21
B22
E22
D22
D21
E21

A5

E18
D19
D18
E19

B5

F9
F10

A4
E11
F5
C9
C28
F24
C24
E20

C6
E9
E6
A8
B29
E25
A25
F21

C5
E10
E5
B8
A29
D25
B25
F20

402

X5R

10%

0.1uF

16V

C8296

1

2

1%

1/16W

402

MF-LF

1.07K

R8295

1

2

FERR-220-OHM

0402

L8200

1 2

45.3

1/16W
MF-LF

1%

402

R8290

12

6.3V
CERM

603

20%

4.7UF

C8200

1

2

10K

MF-LF

1/16W

5%

402

R8201

1

2

10K

402

MF-LF

1/16W

5%

R8251

1

2

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 71

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

90 72

SOT-363

2N7002DW-X-F

Q8295

3

5

4

2.49K

1%
1/16W
MF-LF

402

R8296

1

2

1.02K

1%
1/16W
MF-LF

402

R8297

1

2

74 72 71

16

051-7261

109

82

SYNC_DATE=03/19/2007

NV G84M Frame Buffer I/F

SYNC_MASTER=M75_MLB

FB_VREF_UNTERM

GPU_FB_VREF_UNTERM_L

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm

GPU_FB_VREF

=PP1V8_GPU_FBIO

FB_B_WDQS<7>

FB_B_DQ<32>

FB_B_DQ<31>

TP_FBC_CMD28

TP_FBC_CMD27

FB_B_WDQS<6>

FB_B_WDQS<1>
FB_B_WDQS<2>

FB_B_WDQS<4>

FB_B_WDQS<3>

FB_B_WDQS<5>

FB_B_RDQS<5>
FB_B_RDQS<6>
FB_B_RDQS<7>

FB_B_WDQS<0>

FB_B_RDQS<0>
FB_B_RDQS<1>
FB_B_RDQS<2>
FB_B_RDQS<3>
FB_B_RDQS<4>

FB_B_DQM_L<4>

FB_B_DQM_L<7>

FB_B_DQM_L<6>

FB_B_DQM_L<5>

FB_B_DQM_L<3>

FB_B_CLK_N<1>

FB_B_DQM_L<2>

FB_B_DQM_L<1>

FB_B_DQM_L<0>

FB_B_CLK_N<0>

FB_B_CLK_P<0>

FB_B_CLK_P<1>

TP_FBC_DEBUG

=PP1V8_GPU_FBIO

FB_A_DQ<35>

FB_A_CLK_N<1>

FB_A_CLK_P<1>

TP_FBA_CMD28

TP_FBA_CMD27

FB_A_CLK_N<0>

FB_A_CLK_P<0>

FB_A_WDQS<7>

FB_A_WDQS<6>

FB_A_WDQS<5>

FB_A_WDQS<4>

FB_A_WDQS<3>

FB_A_WDQS<2>

FB_A_WDQS<1>

FB_A_WDQS<0>

FB_A_RDQS<7>

FB_A_RDQS<6>

FB_A_RDQS<5>

FB_A_RDQS<4>

FB_A_RDQS<3>

FB_A_RDQS<2>

FB_A_RDQS<1>

FB_A_RDQS<0>

FB_A_DQM_L<7>

FB_A_DQM_L<6>

FB_A_DQM_L<5>

FB_A_DQM_L<4>

FB_A_DQM_L<3>

FB_A_DQM_L<2>

FB_A_DQM_L<1>

FB_A_DQM_L<0>

FBCAL_PU_GND

TP_FBA_DEBUG

FBCAL_PD_VDDQ

FB_A_CKE

FB_A_DQ<5>

FB_A_BA<2>
FB_A_CS0_L

FB_A_DQ<2>

FB_A_DQ<1>

FB_B_DQ<63>FB_A_DQ<63>

FB_A_DQ<54>
FB_A_DQ<55>
FB_A_DQ<56>
FB_A_DQ<57>
FB_A_DQ<58>
FB_A_DQ<59>
FB_A_DQ<60>
FB_A_DQ<61>
FB_A_DQ<62>

FB_A_DQ<44>
FB_A_DQ<45>
FB_A_DQ<46>
FB_A_DQ<47>
FB_A_DQ<48>
FB_A_DQ<49>
FB_A_DQ<50>
FB_A_DQ<51>
FB_A_DQ<52>
FB_A_DQ<53>

FB_A_DQ<34>

FB_A_DQ<36>
FB_A_DQ<37>
FB_A_DQ<38>
FB_A_DQ<39>
FB_A_DQ<40>
FB_A_DQ<41>
FB_A_DQ<42>
FB_A_DQ<43>

FB_A_DQ<33>

FB_A_DQ<25>
FB_A_DQ<26>

FB_A_DQ<28>
FB_A_DQ<29>
FB_A_DQ<30>
FB_A_DQ<31>
FB_A_DQ<32>

FB_A_DQ<13>
FB_A_DQ<14>
FB_A_DQ<15>
FB_A_DQ<16>
FB_A_DQ<17>
FB_A_DQ<18>
FB_A_DQ<19>
FB_A_DQ<20>
FB_A_DQ<21>

FB_A_DQ<4>

FB_A_DQ<7>
FB_A_DQ<8>

FB_A_DQ<10>
FB_A_DQ<11>
FB_A_DQ<12>

FB_A_DQ<0>

FB_B_DQ<62>

FB_B_DQ<56>

FB_B_DQ<52>

FB_B_DQ<60>

FB_B_DQ<14>

FB_B_DQ<12>
FB_B_DQ<13>

FB_B_DQ<54>

FB_B_UMA<2>
FB_B_UMA<4>

FB_B_BA<2>

FB_B_DQ<0>

FB_B_BA<1>

FB_B_DQ<42>

FB_B_LMA<4>

FB_B_DQ<10>

FB_B_DQ<1>
FB_B_DQ<2>
FB_B_DQ<3>
FB_B_DQ<4>
FB_B_DQ<5>
FB_B_DQ<6>
FB_B_DQ<7>
FB_B_DQ<8>
FB_B_DQ<9>

FB_B_DQ<11>

FB_B_DQ<15>
FB_B_DQ<16>

FB_B_DQ<19>

FB_B_DQ<22>
FB_B_DQ<23>
FB_B_DQ<24>
FB_B_DQ<25>
FB_B_DQ<26>
FB_B_DQ<27>
FB_B_DQ<28>
FB_B_DQ<29>
FB_B_DQ<30>

FB_B_DQ<33>
FB_B_DQ<34>
FB_B_DQ<35>
FB_B_DQ<36>
FB_B_DQ<37>
FB_B_DQ<38>
FB_B_DQ<39>
FB_B_DQ<40>
FB_B_DQ<41>

FB_B_DQ<44>
FB_B_DQ<45>
FB_B_DQ<46>

FB_B_DQ<49>
FB_B_DQ<50>

FB_B_DQ<57>
FB_B_DQ<58>
FB_B_DQ<59>

FB_B_DQ<61>

FB_B_RAS_L
FB_B_LMA<5>

FB_B_MA<11>
FB_B_CAS_L
FB_B_WE_L

FB_B_UMA<5>
TP_FB_B_MA12

FB_B_MA<7>
FB_B_MA<10>

FB_B_MA<6>
FB_B_LMA<2>
FB_B_MA<8>
FB_B_LMA<3>
FB_B_MA<1>
TP_FB_B_MA13

FB_A_MA<9>

FB_A_LMA<2>

TP_FB_A_MA13

FB_A_MA<0>

FB_A_MA<11>

FB_A_UMA<3>

FB_A_RAS_L
FB_A_LMA<5>
FB_A_BA<1>

FB_B_DQ<17>
FB_B_DQ<18>

FB_B_DQ<20>
FB_B_DQ<21>

FB_A_UMA<4>

FB_B_BA<0>

FB_B_UMA<3>

FB_B_CS0_L

FB_A_UMA<2>

FB_B_DQ<43>

FB_B_DQ<51>

FB_B_DQ<55>

FB_A_LMA<4>

FB_A_MA<10>

FB_A_MA<7>

FB_A_UMA<5>

FB_A_WE_L

FB_A_DRAM_RST

FB_A_CAS_L

FB_A_BA<0>

TP_FB_A_MA12

FBCAL_TERM_GND

FB_B_DQ<53>

FB_A_LMA<3>

FB_A_MA<8>

FB_A_MA<1>

FB_A_MA<6>

FB_B_DQ<47>
FB_B_DQ<48>

FB_B_MA<9>

FB_B_MA<0>

FB_B_CKE

FB_B_DRAM_RST

FB_A_DQ<22>

FB_A_DQ<24>

FB_A_DQ<27>

FB_A_DQ<23>

FB_A_DQ<9>

FB_A_DQ<6>

FB_A_DQ<3>

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

PP1V2_GPU_FBA_PLL_F

VOLTAGE=1.2V

=PP1V2_GPU_FBPLLAVDD

70

70

8

74

74

8

74

74

8

Preliminary

DQ1

DQ0

DQ2
DQ3

DQ5
DQ6

DQ4

DQ8

DQ7

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21

DQ24

DQ23

DQ22

DQ25
DQ26
DQ27

DQ29

DQ28

DQ30
DQ31

RDQS3

RDQS2

RDQS1

RDQS0

SEN
RESET

MF

ZQ

RAS*

CAS*

WE*

CS*

CK*

A9

A6
A7

A3
A4

A2

A0
A1

CK

WDQS2

WDQS1

WDQS0

WDQS3

BA0

BA2

BA1

RFU1
RFU2

DM3

DM2

DM1

DM0

A5

A11

A8/AP

A10

CKE

MFHIGH

MFHIGH

MFHIGH

(1 OF 2)

VSS0
VSS1
VSS2

VSS5

VSS3
VSS4

VSS7

VSS6

VSSA0
VSSA1

VSSQ0
VSSQ1
VSSQ2
VSSQ3

VSSQ5
VSSQ6

VSSQ4

VSSQ7
VSSQ8

VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14

VSSQ16

VSSQ15

VSSQ17
VSSQ18
VSSQ19VDDQ19

VDDQ20
VDDQ21

VREF1

VREF0

VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15

VDDQ18

VDDQ16
VDDQ17

VDDQ9

VDDA1

VDDQ0
VDDQ1
VDDQ2

VDDQ5

VDDQ3
VDDQ4

VDDQ6
VDDQ7
VDDQ8

VDD0
VDD1
VDD2

VDD5

VDD3
VDD4

VDD6
VDD7

VDDA0

(2 OF 2)

IN

IN

IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT
OUT
OUT
OUT

IN

IN

IN

IN
IN

IN

IN

OUT

OUT
OUT

OUT

IN

IN

IN

IN
IN

IN

IN
IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

DQ1

DQ0

DQ2
DQ3

DQ5
DQ6

DQ4

DQ8

DQ7

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21

DQ24

DQ23

DQ22

DQ25
DQ26
DQ27

DQ29

DQ28

DQ30
DQ31

RDQS3

RDQS2

RDQS1

RDQS0

SEN
RESET

MF

ZQ

RAS*

CAS*

WE*

CS*

CK*

A9

A6
A7

A3
A4

A2

A0
A1

CK

WDQS2

WDQS1

WDQS0

WDQS3

BA0

BA2

BA1

RFU1
RFU2

DM3

DM2

DM1

DM0

A5

A11

A8/AP

A10

CKE

MFHIGH

MFHIGH

MFHIGH

(1 OF 2)

VSS0
VSS1
VSS2

VSS5

VSS3
VSS4

VSS7

VSS6

VSSA0
VSSA1

VSSQ0
VSSQ1
VSSQ2
VSSQ3

VSSQ5
VSSQ6

VSSQ4

VSSQ7
VSSQ8

VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14

VSSQ16

VSSQ15

VSSQ17
VSSQ18
VSSQ19VDDQ19

VDDQ20
VDDQ21

VREF1

VREF0

VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15

VDDQ18

VDDQ16
VDDQ17

VDDQ9

VDDA1

VDDQ0
VDDQ1
VDDQ2

VDDQ5

VDDQ3
VDDQ4

VDDQ6
VDDQ7
VDDQ8

VDD0
VDD1
VDD2

VDD5

VDD3
VDD4

VDD6
VDD7

VDDA0

(2 OF 2)

BI
BI
BI
BI

BI
BI
BI
BI
BI

BI
BI
BI
BI
BI

BI
BI
BI
BI
BI

BI
BI
BI
BI
BI

BI

BI
BI
BI
BI

BI

IN
IN

BI

BI

IN
IN

G

D

S

G

D

S

IN IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Connect to designated pin, then GND

NC
NC

U8400.J12

U8400.J1

U8400.J12

U8400.J1

(NONE)

(NONE)

- =PP1V8_S0_FB_VDD

- =PP1V8_S0_FB_VDDQ

NC

NC

Connect to designated pin, then GND

Page Notes

Power aliases required by this page:

Signal aliases required by this page:

BOM options provided by this page:

1/16W

1%

402

MF-LF

2.37K

R8430

1

2

402

1/16W

1%

MF-LF

5.49K

R8431

1

2

0.1uF

X5R
402

10%
16V

C8403

1

2

X5R
402

10%
16V

0.1uF

C8402

1

2

0.1uF

X5R
402

10%
16V

C8404

1

2

402

0.1uF

X5R

10%
16V

C8401

1

2

402

16V

10%
X5R

0.1uF

C8422

1

2

X5R

16V

10%
402

0.1uF

C8423

1

2

0.1uF

16V

10%
402

X5R

C8424

1

2

0.1uF

X5R
402

10%
16V

C8425

1

2

X5R
402

10%
16V

0.1uF

C8426

1

2

CRITICAL

OMIT

FBGA

K4J52324QC-BC20

16MX32-GDDR3-500MHZ

U8400

K9

H11

K11

L9

K10

M9
K4
H2
K3
L4
K2
M4

G9
G4
H3

F9

J11
J10

H9

F4

E3
E10
N10
N3

B2
B3

C11
C10
E11
F10
F11
G10
M11
L10
N11
M10

C2

R11
R10
T11
T10
M2
L3
N2
M3
R2
R3

C3

T2
T3

E2
F3
F2
G3
B11
B10

A9

H10

D3
D10
P10

P3

V9

J2

J3

V4

D2
D11
P11

P2

H4

A4

OMIT

CRITICAL

16MX32-GDDR3-500MHZ

K4J52324QC-BC20

FBGA

U8400

A2

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

J4
J9
N1
N4
N9

N12

R1
R4
R9

R12

C1

V1

V12

C4
C9

C12

E1
E4
E9

E12

H1

H12

A3
A10
G1
G12
L1
L12
V3
V10

J1
J12

B1
B4

L2
L11
P1
P4
P9
P12
T1
T4
T9
T12

B9
B12
D1
D4
D9
D12
G2
G11

MF-LF
402

5%
1/16W

100

R8449

1

2

243

MF-LF

402

1%

1/16W

R8448

1

2

MF-LF
402

1%
1/16W

121

R8445

1

2

121

MF-LF

402

1%

1/16W

R8446

1

2

CERM

25V

0.0047uF

10%

402

C8433

1

2

0.1uF

16V

10%
X5R

402

C8421

1

2

0.1uF

X5R
402

10%
16V

C8415

1

2

0.1uF

X5R
402

16V

10%

C8410

1

2

1/16W

402

MF-LF

1K

5%

R8440

1

2

121

1%
MF-LF

402

1/16W

R8447

1

2

1/16W

402

MF-LF

121

1%

R8444

1

2

MF-LF

1%

121

402

1/16W

R8443

1

2

1/16W

402

MF-LF

121

1%

R8442

1

2

90 70

90 70

90 70

90

70

90 70

90 70

90 70

90 70

90 70

90

70

90 70

90

70

90

70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90

70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 71 70

90 71 70

90 71 70

90 71 70

90 71 70

90 71 70

90 71 70

90 71 70

90 71 70

90 70

90 70

90 71 70

90 71 70

90 71 70

90 71 70

90 71 70

90 71 70

90 71 70

90 70

90 70

90 70

90 70

90 71 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 71 70

90 71 70

90 71 70

90

70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 71 70

90 71 70

90 71 70

90 71 70

90 71

70

90

70

90 71

70

90 70

90 71 70

90 71 70

90 71 70

90 71 70

90 71 70

90 71 70

90 70

90 70

90 70

90 70

90 71 70

90

71 70

5%

1K

1/16W

402

MF-LF

R8490

1

2

1/16W

402

MF-LF

121

1%

R8492

1

2

16V
402

X5R

0.1uF

10%

C8471

1

2

16V

10%
402

X5R

0.1uF

C8472

1

2

1/16W

1%

402

MF-LF

243

R8498

1

2

1/16W

5%

402

MF-LF

100

R8499

1

2

CRITICAL

FBGA

K4J52324QC-BC20

16MX32-GDDR3-500MHZ

OMIT

U8450

K9

H11

K11

L9

K10

M9
K4
H2
K3
L4
K2
M4

G9
G4
H3

F9

J11
J10

H9

F4

E3
E10
N10
N3

B2
B3

C11
C10
E11
F10
F11
G10
M11
L10
N11
M10

C2

R11
R10
T11
T10
M2
L3
N2
M3
R2
R3

C3

T2
T3

E2
F3
F2
G3
B11
B10

A9

H10

D3
D10
P10

P3

V9

J2

J3

V4

D2
D11
P11

P2

H4

A4

1%

121

MF-LF
402

1/16W

R8493

1

2

121

1/16W

1%

402

MF-LF

R8495

1

2

1/16W

402

MF-LF

121

1%

R8494

1

2

121

1/16W
402

MF-LF

1%

R8497

1

2

121

1/16W

1%

402

MF-LF

R8496

1

2

16V

10%
402

X5R

0.1uF

C8473

1

2

16V

10%
402

X5R

0.1uF

C8474

1

2

16V

10%
402

X5R

0.1uF

C8475

1

2

CRITICAL

OMIT

16MX32-GDDR3-500MHZ

K4J52324QC-BC20

FBGA

U8450

A2

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

J4
J9
N1
N4
N9

N12

R1
R4
R9

R12

C1

V1

V12

C4
C9

C12

E1
E4
E9

E12

H1

H12

A3
A10
G1
G12
L1
L12
V3
V10

J1
J12

B1
B4

L2
L11
P1
P4
P9
P12
T1
T4
T9
T12

B9
B12
D1
D4
D9
D12
G2
G11

16V

10%
402

X5R

0.1uF

C8476

1

2

16V

10%

402

0.1uF

X5R

C8451

1

2

16V

10%
X5R

0.1uF

402

C8452

1

2

16V

10%

402

X5R

0.1uF

C8460

1

2

16V

10%

402

X5R

0.1uF

C8453

1

2

16V

10%

402

X5R

0.1uF

C8465

1

2

16V

10%

402

X5R

0.1uF

C8454

1

2

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

22UF

CERM-X5R

805

20%

6.3V

C8400

1

2

CERM-X5R

20%

6.3V
805

22UF

C8420

1

2

20%

6.3V
805

22UF

CERM-X5R

C8450

1

2

805

20%

6.3V

22UF

CERM-X5R

C8470

1

2

16V

10%

402

0.01UF

CERM

C8446

1

2

16V

10%

402

0.01UF

CERM

C8496

1

2

2.21K

1/16W

1%

MF-LF

402

R8432

1

2

SOT-363

2N7002DW-X-F

Q8400

3

5

4

CERM

25V

0.0047uF

402

10%

C8483

1

2

2N7002DW-X-F

SOT-363

Q8400

6

2

1

402

10%

0.0047uF

25V
CERM

C8481

1

2

2.21K

1/16W

1%

MF-LF

402

R8482

1

2

2.37K

MF-LF

402

1%

1/16W

R8480

1

2

5.49K

MF-LF

1%

1/16W

402

R8481

1

2

74

72 71 70

74

72 71 70

10%

402

0.0047uF

25V
CERM

C8431

1

2

109

051-7261

16

84

GDDR3 Frame Buffer A

SYNC_MASTER=M75_MLB

SYNC_DATE=04/02/2007

FB_A1_VREF

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

FB_A0_VREF

FB_A_MA<0>

FB_A_UMA<3>

FB_VREF_UNTERM

FB_A_CLK1_TERM

FB_VREF_UNTERM

FB_A0_VREF_UNTERM_L

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

FB_A_CLK0_TERM

=PP1V8_GPU_FB_VDDQ

FB_A_MA<1>

FB_A_LMA<3>

FB_A_MA<7>

FB_A_MA<9>

FB_A_CLK_N<0>

FB_A0_ZQ

FB_A_DRAM_RST

FB_A_DQ<32>
FB_A_DQ<36>

FB_A_DQ<53>

FB_A_DQ<49>

FB_A_DQ<55>

FB_A_DQ<51>

FB_A_DQ<52>

FB_A_CS0_L
FB_A_WE_L
FB_A_CAS_L

FB_A_WDQS<0>
FB_A_WDQS<1>
FB_A_WDQS<2>
FB_A_WDQS<3>

FB_A_BA<0>

FB_A0_SEN

=PP1V8_GPU_FB_VDD

FB_A_UMA<5>

FB_A_CLK_N<1>

FB_A_CKE

FB_A_WE_L

FB_A_CKE

FB_A_RAS_L

FB_A_DQ<42>

FB_A_DQ<45>

FB_A_DQ<46>

FB_A_DQ<47>

FB_A_DQ<40>

FB_A_DQ<60>

FB_A_DQ<63>

FB_A_DQ<57>

FB_A_DQ<58>

FB_A_DQ<56>

FB_A_RDQS<0>
FB_A_RDQS<1>

FB_A_RDQS<3>

FB_A_DQM_L<1>

FB_A_BA<2>

FB_A_DQ<4>

FB_A_DQ<1>

FB_A_DQ<2>

FB_A_DQ<7>
FB_A_DQ<3>

FB_A_DQ<5>

FB_A_DQ<8>

FB_A_DQ<6>

FB_A_DQ<9>
FB_A_DQ<10>
FB_A_DQ<11>
FB_A_DQ<12>
FB_A_DQ<15>
FB_A_DQ<14>
FB_A_DQ<13>
FB_A_DQ<17>
FB_A_DQ<18>
FB_A_DQ<16>
FB_A_DQ<20>
FB_A_DQ<21>
FB_A_DQ<19>

FB_A_DQ<25>

FB_A_DQ<23>

FB_A_DQ<22>

FB_A_DQ<27>

FB_A_DQ<24>

FB_A_DQ<26>

FB_A_DQ<31>

FB_A_DQ<29>
FB_A_DQ<30>

FB_A_BA<1>

FB_A_DQM_L<3>

FB_A_DQM_L<2>

FB_A_DQM_L<0>

FB_A_MA<10>

FB_A_DQ<62>

FB_A_DQ<59>

FB_A_DQ<61>

FB_A_DQ<44>
FB_A_DQ<41>
FB_A_DQ<43>
FB_A_DQ<50>
FB_A_DQ<48>

FB_A_DQ<34>

FB_A_DQ<54>

FB_A_DQ<33>
FB_A_DQ<35>

FB_A_DQ<37>
FB_A_DQ<39>
FB_A_DQ<38>

FB_A_RDQS<5>

FB_A_RDQS<7>

FB_A1_SEN

FB_A_DRAM_RST

FB_A_MA<9>

FB_A_MA<6>
FB_A_MA<7>

FB_A_MA<1>

FB_A_WDQS<6>

FB_A_WDQS<5>

FB_A_WDQS<7>

FB_A_WDQS<4>
FB_A_BA<0>

FB_A_BA<1>

FB_A_DQM_L<4>

FB_A_DQM_L<6>

FB_A_DQM_L<5>

FB_A_DQM_L<7>

FB_A_MA<8>

FB_A_MA<10>

FB_A_RDQS<2>

FB_A_MA<11>

FB_A_MA<8>

FB_A1_ZQ

FB_A_RAS_L

FB_A_CAS_L

FB_A_CS0_L

FB_A_MA<11>

FB_A_DQ<0>

FB_A_DQ<28>

FB_A_BA<2>

FB_A_MA<6>

FB_A_LMA<2>

FB_A_CLK_P<0>

FB_A_LMA<4>

FB_A1_MF

FB_A_CLK_P<1>

FB_A_UMA<2>

FB_A_UMA<4>

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm

FB_A1_VREF_UNTERM_L

=PP1V8_GPU_FB_VDDQ

FB_A_RDQS<4>

FB_A_RDQS<6>

=PP1V8_GPU_FB_VDD

FB_A_MA<0>

FB_A_LMA<5>

FB_A0_MF

72

72

72

72

71

71

71

71

8

8

8

8

Preliminary

DQ1

DQ0

DQ2
DQ3

DQ5
DQ6

DQ4

DQ8

DQ7

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21

DQ24

DQ23

DQ22

DQ25
DQ26
DQ27

DQ29

DQ28

DQ30
DQ31

RDQS3

RDQS2

RDQS1

RDQS0

SEN
RESET

MF

ZQ

RAS*

CAS*

WE*

CS*

CK*

A9

A6
A7

A3
A4

A2

A0
A1

CK

WDQS2

WDQS1

WDQS0

WDQS3

BA0

BA2

BA1

RFU1
RFU2

DM3

DM2

DM1

DM0

A5

A11

A8/AP

A10

CKE

MFHIGH

MFHIGH

MFHIGH

(1 OF 2)

VSS0
VSS1
VSS2

VSS5

VSS3
VSS4

VSS7

VSS6

VSSA0
VSSA1

VSSQ0
VSSQ1
VSSQ2
VSSQ3

VSSQ5
VSSQ6

VSSQ4

VSSQ7
VSSQ8

VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14

VSSQ16

VSSQ15

VSSQ17
VSSQ18
VSSQ19VDDQ19

VDDQ20
VDDQ21

VREF1

VREF0

VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15

VDDQ18

VDDQ16
VDDQ17

VDDQ9

VDDA1

VDDQ0
VDDQ1
VDDQ2

VDDQ5

VDDQ3
VDDQ4

VDDQ6
VDDQ7
VDDQ8

VDD0
VDD1
VDD2

VDD5

VDD3
VDD4

VDD6
VDD7

VDDA0

(2 OF 2)

IN

IN

IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT
OUT
OUT
OUT

IN

IN

IN

IN
IN

IN

IN

OUT

OUT
OUT

OUT

IN

IN

IN

IN
IN

IN

IN
IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

DQ1

DQ0

DQ2
DQ3

DQ5
DQ6

DQ4

DQ8

DQ7

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21

DQ24

DQ23

DQ22

DQ25
DQ26
DQ27

DQ29

DQ28

DQ30
DQ31

RDQS3

RDQS2

RDQS1

RDQS0

SEN
RESET

MF

ZQ

RAS*

CAS*

WE*

CS*

CK*

A9

A6
A7

A3
A4

A2

A0
A1

CK

WDQS2

WDQS1

WDQS0

WDQS3

BA0

BA2

BA1

RFU1
RFU2

DM3

DM2

DM1

DM0

A5

A11

A8/AP

A10

CKE

MFHIGH

MFHIGH

MFHIGH

(1 OF 2)

VSS0
VSS1
VSS2

VSS5

VSS3
VSS4

VSS7

VSS6

VSSA0
VSSA1

VSSQ0
VSSQ1
VSSQ2
VSSQ3

VSSQ5
VSSQ6

VSSQ4

VSSQ7
VSSQ8

VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14

VSSQ16

VSSQ15

VSSQ17
VSSQ18
VSSQ19VDDQ19

VDDQ20
VDDQ21

VREF1

VREF0

VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15

VDDQ18

VDDQ16
VDDQ17

VDDQ9

VDDA1

VDDQ0
VDDQ1
VDDQ2

VDDQ5

VDDQ3
VDDQ4

VDDQ6
VDDQ7
VDDQ8

VDD0
VDD1
VDD2

VDD5

VDD3
VDD4

VDD6
VDD7

VDDA0

(2 OF 2)

BI
BI
BI
BI

BI
BI
BI
BI
BI

BI
BI
BI
BI
BI

BI
BI
BI
BI
BI

BI
BI
BI
BI
BI

BI

BI
BI
BI
BI

BI

IN
IN

BI

BI

IN
IN

G

D

S

G

D

S

IN IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Connect to designated pin, then GND

Page Notes

Power aliases required by this page:

BOM options provided by this page:

Signal aliases required by this page:
(NONE)

(NONE)

- =PP1V8_S0_FB_VDD

- =PP1V8_S0_FB_VDDQ

NC
NC NC

NC

Connect to designated pin, then GND

U8500.J1

U8500.J12

U8500.J1

U8500.J12

16V

10%
X5R

0.1uF

402

C8503

1

2

16V

10%

402

X5R

0.1uF

C8502

1

2

16V

10%

402

X5R

0.1uF

C8504

1

2

402

16V

10%
X5R

0.1uF

C8501

1

2

16V

10%
402

X5R

0.1uF

C8522

1

2

16V

10%
402

X5R

0.1uF

C8523

1

2

16V

10%
402

X5R

0.1uF

C8524

1

2

16V

10%
402

X5R

0.1uF

C8525

1

2

10%
X5R

0.1uF

402

16V

C8526

1

2

16MX32-GDDR3-500MHZ

K4J52324QC-BC20

FBGA

OMIT

CRITICAL

U8500

K9

H11

K11

L9

K10

M9
K4
H2
K3
L4
K2
M4

G9
G4
H3

F9

J11
J10

H9

F4

E3
E10
N10
N3

B2
B3

C11
C10
E11
F10
F11
G10
M11
L10
N11
M10

C2

R11
R10
T11
T10
M2
L3
N2
M3
R2
R3

C3

T2
T3

E2
F3
F2
G3
B11
B10

A9

H10

D3
D10
P10

P3

V9

J2

J3

V4

D2
D11
P11

P2

H4

A4

CRITICAL

OMIT

FBGA

K4J52324QC-BC20

16MX32-GDDR3-500MHZ

U8500

A2

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

J4
J9
N1
N4
N9

N12

R1
R4
R9

R12

C1

V1

V12

C4
C9

C12

E1
E4
E9

E12

H1

H12

A3
A10
G1
G12
L1
L12
V3
V10

J1
J12

B1
B4

L2
L11
P1
P4
P9
P12
T1
T4
T9
T12

B9
B12
D1
D4
D9
D12
G2
G11

1/16W

5%

402

MF-LF

100

R8549

1

2

1/16W

1%

402

MF-LF

243

R8548

1

2

16V

10%
X5R

0.1uF

402

C8521

1

2

16V

10%

402

X5R

0.1uF

C8515

1

2

16V

10%

402

X5R

0.1uF

C8510

1

2

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90

70

90 70

90

70

90

70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 72 70

90 72 70

90 72 70

90 72 70

90 72 70

90 72 70

90 72 70

90 72 70

90 72 70

90 70

90 70

90 72 70

90 72 70

90 72 70

90 72 70

90 72 70

90 72 70

90 72 70

90 70

90 70

90 70

90 70

90 72 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 72 70

90 72 70

90 72 70

90

70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 72 70

90 72 70

90 72 70

90 72 70

90 72 70

90

70

90 72 70

90

70

90 72 70

90 72 70

90 72 70

90 72 70

90 72 70

90 72 70

90 70

90 70

90 70

90 70

90

72 70

90

72 70

X5R
402

10%
16V

0.1uF

C8571

1

2

X5R
402

10%
16V

0.1uF

C8572

1

2

1/16W

402

MF-LF

243

1%

R8598

1

2

1/16W
402

MF-LF

5%

100

R8599

1

2

16MX32-GDDR3-500MHZ

K4J52324QC-BC20

OMIT

CRITICAL

FBGA

U8550

K9

H11

K11

L9

K10

M9
K4
H2
K3
L4
K2
M4

G9
G4
H3

F9

J11
J10

H9

F4

E3
E10
N10
N3

B2
B3

C11
C10
E11
F10
F11
G10
M11
L10
N11
M10

C2

R11
R10
T11
T10
M2
L3
N2
M3
R2
R3

C3

T2
T3

E2
F3
F2
G3
B11
B10

A9

H10

D3
D10
P10

P3

V9

J2

J3

V4

D2
D11
P11

P2

H4

A4

10%
402

X5R

16V

0.1uF

C8573

1

2

16V

10%
402

X5R

0.1uF

C8574

1

2

X5R
402

10%
16V

0.1uF

C8575

1

2

K4J52324QC-BC20

OMIT

CRITICAL

FBGA

16MX32-GDDR3-500MHZ

U8550

A2

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

J4
J9
N1
N4
N9

N12

R1
R4
R9

R12

C1

V1

V12

C4
C9

C12

E1
E4
E9

E12

H1

H12

A3
A10
G1
G12
L1
L12
V3
V10

J1
J12

B1
B4

L2
L11
P1
P4
P9
P12
T1
T4
T9
T12

B9
B12
D1
D4
D9
D12
G2
G11

X5R
402

10%
16V

0.1uF

C8576

1

2

0.1uF

X5R
402

10%
16V

C8551

1

2

0.1uF

X5R
402

10%
16V

C8552

1

2

16V

10%

402

X5R

0.1uF

C8560

1

2

16V

10%

402

X5R

0.1uF

C8553

1

2

16V

10%

402

X5R

0.1uF

C8565

1

2

0.1uF

X5R
402

10%
16V

C8554

1

2

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

90 70

20%

6.3V
805

22UF

CERM-X5R

C8500

1

2

CERM-X5R

20%

6.3V
805

22UF

C8520

1

2

CERM-X5R

20%

6.3V
805

22UF

C8550

1

2

CERM-X5R

22UF

20%

6.3V
805

C8570

1

2

121

1%

402

1/16W
MF-LF

R8546

1

2

121

1%
MF-LF

402

1/16W

R8547

1

2

1/16W

121

1%

MF-LF

402

R8544

1

2

MF-LF
402

1%
1/16W

121

R8545

1

2

402

MF-LF

121

1%

1/16W

R8542

1

2

5%

MF-LF

402

1/16W

1K

R8540

1

2

MF-LF

1%

121

402

1/16W

R8543

1

2

121

MF-LF

402

1%

1/16W

R8596

1

2

121

1%
MF-LF

402

1/16W

R8597

1

2

MF-LF
402

121

1%
1/16W

R8595

1

2

1%

121

MF-LF

402

1/16W

R8594

1

2

1%

121

MF-LF

402

1/16W

R8592

1

2

1/16W
402

MF-LF

1%

121

R8593

1

2

MF-LF

402

1/16W

1K

5%

R8590

1

2

16V

10%

402

0.01UF

CERM

C8596

1

2

0.01UF

CERM

402

10%
16V

C8546

1

2

5.49K

MF-LF

1%

1/16W

402

R8531

1

2

2.21K

1/16W

1%

MF-LF

402

R8532

1

2

402

10%

0.0047uF

25V
CERM

C8531

1

2

CERM

25V

0.0047uF

402

10%

C8533

1

2

2N7002DW-X-F

SOT-363

Q8500

3

5

4

2.37K

MF-LF

402

1%

1/16W

R8530

1

2

402

1/16W

1%

MF-LF

5.49K

R8581

1

2

2.21K

402

MF-LF

1%

1/16W

R8582

1

2

1/16W

1%

402

MF-LF

2.37K

R8580

1

2

10%

402

0.0047uF

25V
CERM

C8581

1

2

CERM

25V

0.0047uF

10%

402

C8583

1

2

SOT-363

2N7002DW-X-F

Q8500

6

2

1

74

72 71 70

74

72 71 70

GDDR3 Frame Buffer B

85

109

16

051-7261

SYNC_MASTER=M75_MLB

SYNC_DATE=04/02/2007

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm

FB_B1_VREF

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

FB_B0_VREF

=PP1V8_GPU_FB_VDDQ

FB_B1_VREF_UNTERM_L

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

FB_B_DQM_L<0>

FB_B_WDQS<4>

FB_B_CLK1_TERM

FB_B_CLK_P<0>

FB_B_MA<0>

FB_B_DQM_L<4>

FB_B_DQM_L<5>

FB_B_DQ<53>

FB_B_MA<11>

FB_B_MA<10>

FB_B_MA<9>

FB_B_MA<8>

FB_B_MA<7>

FB_B_UMA<5>

FB_B_UMA<4>

FB_B_UMA<3>

FB_B_MA<6>

FB_B_CLK_P<1>
FB_B_CLK_N<1>

FB_B_DQ<40>

FB_B_DQ<44>
FB_B_DQ<36>
FB_B_DQ<39>

FB_B_MA<1>

FB_B_MA<7>

FB_B_MA<9>
FB_B_MA<10>

FB_B_CKE

FB_B_CLK_N<0>
FB_B_CS0_L
FB_B_WE_L

FB_B_WDQS<2>

FB_B_MA<11>

FB_B_DQ<17>

FB_B_RDQS<4>

FB_B_DQ<5>

FB_B_DQ<4>

FB_B_DQ<25>

FB_B_DQ<16>

FB_B_DQ<19>

FB_B_DQ<18>

FB_B_DQM_L<3>

FB_B_RDQS<0>

FB_B_RDQS<3>

FB_B_RDQS<1>

FB_B0_ZQ

FB_B0_SEN

FB_B_DQ<15>

FB_B1_ZQ

FB_B_DQ<58>

FB_B_DQ<45>

FB_B_MA<1>

FB_B_DQ<60>

FB_B_DQ<56>

FB_B_BA<0>
FB_B_BA<1>

FB_B_DQ<23>
FB_B_DQ<20>

FB_B_DQ<21>

FB_B_DQ<8>

FB_B_DQ<22>

FB_B_DQ<12>
FB_B_DQ<9>
FB_B_DQ<10>
FB_B_DQ<13>
FB_B_DQ<14>

FB_B_DQ<11>
FB_B_DQ<24>
FB_B_DQ<28>
FB_B_DQ<29>
FB_B_DQ<31>
FB_B_DQ<30>

FB_B_DQ<2>

FB_B_DQ<27>

FB_B_DQ<26>

FB_B_DQ<1>
FB_B_DQ<6>
FB_B_DQ<0>
FB_B_DQ<7>

FB_B_DQ<3>

FB_B_MA<6>

FB_B_MA<0>

FB_B_WDQS<3>

FB_B_WDQS<1>

FB_B_WDQS<0>

FB_B_DQM_L<1>

FB_B_DQM_L<2>

FB_B_MA<8>

FB_B_DQ<50>

FB_B_DQ<49>

FB_B_DQ<48>
FB_B_DQ<51>

FB_B_DQ<55>
FB_B_DQ<54>

FB_B_DQ<52>

FB_B_DQ<42>
FB_B_DQ<41>

FB_B_DQ<43>
FB_B_DQ<46>
FB_B_DQ<47>

FB_B_DQ<37>
FB_B_DQ<38>
FB_B_DQ<34>
FB_B_DQ<32>

FB_B_DQ<63>

FB_B_DQ<33>

FB_B_DQ<61>
FB_B_DQ<59>
FB_B_DQ<62>

FB_B_DQ<57>

FB_B_RDQS<7>

FB_B_RDQS<6>

FB_B_DRAM_RST

FB_B_WDQS<5>

FB_B_WDQS<6>

FB_B_WDQS<7>
FB_B_BA<0>

FB_B_BA<1>

FB_B_DQM_L<7>

FB_B_DQM_L<6>

FB_B_BA<2> FB_B_BA<2>

FB_B_RDQS<5>

FB_B_DQ<35>

FB_B1_SEN

FB_B_CAS_L

FB_B_CKE

FB_B_CS0_L
FB_B_WE_L
FB_B_CAS_L
FB_B_RAS_L

FB_B_LMA<5>

FB_B_LMA<4>

FB_B_LMA<2>
FB_B_LMA<3>

FB_B_UMA<2>

FB_B_RDQS<2>

FB_B_DRAM_RST

FB_B_RAS_L

FB_B0_MF FB_B1_MF

=PP1V8_GPU_FB_VDD=PP1V8_GPU_FB_VDD

FB_B_CLK0_TERM

FB_B0_VREF_UNTERM_L

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm

FB_VREF_UNTERM FB_VREF_UNTERM

=PP1V8_GPU_FB_VDDQ

72

72 72

72 71

71 71

71

8

8 8

8

Preliminary

VDD33_1
VDD33_2
VDD33_3
VDD33_4
VDD33_5
VDD33_6
VDD33_7
VDD33_8
VDD33_9
VDD33_10
VDD33_11
VDD33_12
VDD33_13

ROM_SCLK
ROM_SI
ROM_SO

TESTMODE
SWAPRDY_A

MIOA_VDDQ_1
MIOA_VDDQ_2
MIOA_VDDQ_3
MIOA_VDDQ_4
MIOA_VDDQ_5
MIOB_VDDQ_1
MIOB_VDDQ_2
MIOB_VDDQ_3
MIOB_VDDQ_4
MIOB_VDDQ_5

MIOA_VREF
MIOB_VREF

MIOACAL_PD_VDDQ
MIOACAL_PU_GND

MIOBCAL_PD_VDDQ
MIOBCAL_PU_GND

PLLVDD
PLLGND

H_PLLVDD

VID_PLLVDD

XTALIN
XTALOUT

XTALOUTBUFF

XTALSSIN

GPIO0
GPIO1
GPIO2
GPIO3

GPIO9

GPIO11

SPDIF

STEREO

JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS

MIOA_CLKOUT

MIOA_CTL3

MIOA_DE

MIOAD0
MIOAD1
MIOAD2
MIOAD3
MIOAD4
MIOAD5
MIOAD6
MIOAD7
MIOAD8

MIOAD9
MIOAD10
MIOAD11

MIOA_HSYNC
MIOA_VSYNC

MIOB_CLKIN

MIOB_CLKOUT

MIOB_CTL3

MIOB_DE

MIOBD0

MIOBD1

MIOBD2

MIOBD3

MIOBD4

MIOBD5

MIOBD6

MIOBD7

MIOBD8

MIOBD9
MIOBD10
MIOBD11

MIOB_HSYNC
MIOB_VSYNC

THERMDP
THERMDN

GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO10

GPIO12

GPIO13

GPIO14

BUFRST_L

JTAG_TRST_L

MIOA_CLKOUT_L

MIOB_CLKOUT_L

ROMCS_L

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Typically <??mA

40mA

Page Notes

Power aliases required by this page:

- =PP3V3_GPU_VDD33

- =PP3V3_GPI_MIO

- =PP1V2_GPU_PLLVDD

- =PP1V2_GPU_H_PLLVDD

- =PP1V2_GPU_VID_PLLVDD

(NONE)

(IPD)

40mA

40mA

Signal aliases required by this page:
(NONE)

BOM options provided by this page:

NB8P-GS-W-A2

OMIT

(6 OF 8)

BGA

U8000

F3

K3
H1

H5
F4
E3
U3
U4

K5
G5
E2
J5
G6
K6
E1
D2

G23

AJ11
AK12
AL12
AK11
AL13

R4
P4
P3
P1

R3

M7
M8
R8
T8
U9

L2

R1

L1
L3

P2
N2

L4
L5

N1
N3
M1
M3
P5
N6
N5
M4

AE4
AD4
AD5
AD3
AD1

AF3

AA8
AB7
AB8
AC6
AC7

Y2

AE3

Y1
Y3

AC3
AC1

AB4
AA5

AC2
AB2
AB1
AA1
AB3
AA3
AC5
AB5

U10

T9

AA7

W2

AA6

AA4

J6
T3

M6

H2

J1

K1

AC11

L10

L7
L8

M10

AC12
AC24
AD24
AE11
AE12

H7
J7
K7

T10

U1
U2

T2

T1

402

5%

MF-LF

1/16W

10K

R8696

1 2

MF-LF

5%

1/16W

402

100K

R8695

1

2

CERM-X5R

6.3V

10%

0.47UF

402

C8601

1

2

CERM-X5R

6.3V

10%

0.47UF

402

C8602

1

2

10%

402

16V
X5R

0.1uF

C8636

1

2

20%

6.3V
CERM

603

4.7UF

C8635

1

2

0402

FERR-220-OHM

L8635

1 2

FERR-220-OHM

0402

L8640

1 2

402

X5R

16V

10%

0.1uF

C8617

1

2

10K

402

1/16W

5%

MF-LF

R8616

1

2

10K

1/16W

402

MF-LF

5%

R8617

1

2

402

MF-LF

1/16W

1%

49.9

R8620

1

2

402

1%

49.9

MF-LF

1/16W

R8622

1

2

402

MF-LF

1/16W

1%

49.9

R8621

1

2

0.1uF

10%
16V
X5R
402

C8619

1

2

10K

5%
1/16W
MF-LF
402

R8618

1

2

10K

5%

402

MF-LF

1/16W

R8619

1

2

402

CERM

1UF

10%

6.3V

C8611

1

2

CERM

1UF

10%

402

6.3V

C8610

1

2

1%
1/16W
MF-LF
402

49.9

R8623

1

2

0.1uF

X5R

16V
402

10%

C8631

1

2

4.7UF

603

CERM

6.3V

20%

C8630

1

2

0402

FERR-220-OHM

L8630

1 2

4.7UF

603

CERM

6.3V

20%

C8633

1

2

10%

402

16V
X5R

0.1uF

C8641

1

2

20%

6.3V
CERM

603

4.7UF

C8640

1

2

4.7UF

603

CERM

6.3V

20%

C8643

1

2

20%

6.3V
CERM

603

4.7UF

C8637

1

2

CERM-X5R

6.3V

10%

0.47UF

402

C8600

1

2

NV G84M GPIO/MIO/Misc

SYNC_DATE=03/19/2007

86

109

16

051-7261

SYNC_MASTER=M75_MLB

GPU_GPIO_7

GPU_GPIO_5

GPU_GPIO_3

=PP1V2_GPU_PLLVDD

VOLTAGE=1.2V

PP1V2_GPU_H_PLLVDD_F

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

GPU_ROM_CS_L

GPU_GPIO_13

GPU_MIOB_D<1>

GPU_MIOB_D<0>

GPU_MIOB_CLKIN

GPU_THERMD_P

GPU_MIOB_HSYNC

TP_GPU_JTAG_TRST_L

GPU_GPIO_12

GPU_GPIO_10

GPU_GPIO_8

GPU_GPIO_4

GPU_THERMD_N

TP_GPU_JTAG_TMS

TP_GPU_JTAG_TDO

TP_GPU_JTAG_TDI

TP_GPU_JTAG_TCK

GPU_SPDIF

GPU_GPIO_9

GPU_GPIO_2

GPU_GPIO_0

GPU_STEREO
TP_GPU_BUFRST_L

GPU_TESTMODE_PD

GPU_ROM_SO

GPU_ROM_SCLK

GPU_GPIO_14

GPU_GPIO_11

GPU_GPIO_1

GPU_GPIO_6

GPU_MIOA_CLKOUT_P
GPU_MIOA_CLKOUT_N
GPU_MIOA_CTL3
GPU_MIOA_DE
GPU_MIOA_D<0>
GPU_MIOA_D<1>
GPU_MIOA_D<2>
GPU_MIOA_D<3>
GPU_MIOA_D<4>
GPU_MIOA_D<5>

GPU_MIOA_D<9>
GPU_MIOA_D<10>
GPU_MIOA_D<11>
GPU_MIOA_HSYNC

GPU_MIOB_VSYNC

GPU_MIOB_D<11>

GPU_MIOB_D<9>

GPU_MIOB_D<8>

GPU_MIOB_D<7>

GPU_MIOB_D<6>

GPU_MIOB_D<5>

GPU_MIOB_D<4>

GPU_MIOB_D<3>

GPU_MIOB_D<2>

GPU_MIOB_DE

GPU_MIOB_CTL3

GPU_MIOB_CLKOUT_N

GPU_MIOB_CLKOUT_P

GPU_MIOB_D<10>

GPU_XTALSSIN

GPU_ROM_SI

GPU_MIOA_PD_VDDQ
GPU_MIOA_PU_GND

GPU_MIOB_PD_VDDQ
GPU_MIOB_PU_GND

GPU_MIOA_PD_VDDQ
GPU_MIOB_PD_VDDQ

GPU_MIOB_PU_GND

GPU_MIOA_PU_GND

GPU_MIOA_D<8>

GPU_MIOA_D<7>

GPU_XTALIN
GPU_XTALOUT

GPU_XTALOUTBUFF

GPU_MIOA_D<6>

GPU_MIOA_VSYNC

GPU_MIOB_VREF

GPU_MIOA_VREF

=PP3V3_GPU_MIO

VOLTAGE=1.2V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

PP1V2_GPU_PLLVDD_F

=PP1V2_GPU_H_PLLVDD

PP1V2_GPU_VID_PLLVDD_F

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm
VOLTAGE=1.2V

=PP1V2_GPU_VID_PLLVDD

=PP3V3_GPU_MIO

GPU_SWAPRDY_A

=PP3V3_GPU_VDD33

74

74

73

73

74

74

74

8

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

73

73

73

73

73

73

73

73

74

74

74

74

74

74

74

8

8

8

8

8

Preliminary

IN

IN

IN

IN

IN

IN

IN

DB

DC

DD

EN_L

IN

S2D

S1D

S2C

S1C

S2B

S1B

S2A

S1A

DA

VCC

GND

THRML

PAD

OUT

OUT

OUT

OUT

OUT

OUT

IN

G

D S

G

D

S

OUT

OUT

BI

BI

GND

VCC

NC

NC

SDA

SCL

NC

NC

OUT

OUT

OUT

OUT

TABLE_ALT_ITEM

TABLE_5_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

TMDS Backdrive Protection

(BIOS ROM PRESENT)

Analog Video Mux

PCI_DEVID3

Place Rs
near GPU

Unused Clocks

RAMCFG0
RAMCFG1
RAMCFG2
RAMCFG3

3GIO_PADCFG1
3GIO_PADCFG2

PEX_PLL_EN_TERM

VID1

NC

SUBVENDOR

MEM_VID

MEM_VREF
SLI_SYNC

AC_DET

PWR_CTL0

GPIOs

HPD1

VID0

FAN_PWM

THERM

Native Func

Place Rs

3GIO_PADCFG3

Renamed signals

Unused signals

Unused I2C Buses

Config Straps

LCD0_BL_PWM

I2CS ties into SMBus connection page

(I2CS requires pullups even if not used)

HPD0

HDCP Support

NC

IS

LCD0_BL_EN

LCD0_VDD

PWR_CTL1

3GIO_PADCFG0

PCI_DEVID0

Supported straps:

MIOA_D<5..2>

MIOB_DE

MIOA_HSYNC
MIOB_D<7>

BAR2_SIZE

PCI_IOBAR

SLOT_CLOCK_CFG

USER<3..0>
ROMTYPE<1..0>

near GPU

MIOB_VSYNC, MIOB_D<10>

PCI_DEVID3
PCI_DEVID0

PCI_DEVID<4>

MIOB_CTL3, MIOB_D<3,5>

Straps not supported:

78

5%

MF-LF

402

1K

NO STUFF

1/16W

R8728

1

2

NO STUFF

402

5%
1/16W
MF-LF

10K

R8726

1

2

VRAM_128

5%
1/16W
MF-LF

402

10K

R8724

1

2

MF-LF

402

5%

1/16W

10K

R8722

1

2

VRAM_SAMSUNG

10K

5%
1/16W
MF-LF

402

R8720

1

2

1/16W

10K

MF-LF

5%

402

R8727

1

2

VRAM_256

5%
1/16W
MF-LF

402

10K

R8725

1

2

NO STUFF

10K

402

5%
1/16W
MF-LF

R8723

1

2

1/16W

10K

5%

MF-LF

402

VRAM_HYNIX

R8721

1

2

5%
1/16W
MF-LF

402

1K

NO STUFF

R8729

1

2

NO STUFF

402

MF-LF

1/16W

5%

1K

R8730

1

2

402

MF-LF

1/16W

NO STUFF

5%

1K

R8731

1

2

NO STUFF

1/16W

5%

MF-LF

402

1K

R8732

1

2

MF-LF

1/16W

1K

5%

402

R8733

1

2

GPU_SS_INT

10K

MF-LF

1/16W

5%

402

R8781

1

2

MF-LF

1/16W

5%

402

10K

R8780

1

2

1%

150

402

MF-LF

1/16W

R8745

1

2

1%

150

MF-LF

1/16W

402

R8744

1

2

402

MF-LF

1/16W

1%

150

R8743

1

2

90 75

90 75

90 75

90 75

90 75

90 75

1%

150

402

MF-LF

1/16W

R8742

1

2

1%

150

MF-LF

1/16W

402

R8741

1

2

1/16W

1%

150

402

MF-LF

R8740

1

2

OMITCRITICAL

TS3V330

QFN

U8700

4

7

9

12

15

8

1

2

5

11

14

3

6

10

13

17

16

90 78

90 78

90 78

10V

0.1UF

20%

402

CERM

C8700

1 2

1/16W
MF-LF
402

10K

5%

R8700

1

2

76

76

76

76 66

5%

MF-LF

402

1/16W

100K

R8791

1

2

CRITICAL

SOT-23

SI2305DS

Q8790

3

1

2

SOT-363

2N7002DW-X-F

Q8925

3

5

4

MF-LF
402

5%
1/16W

10K

R8790

1

2

76

76

HDCP

10V

0.1UF

20%

402

CERM

C8770

1 2

HDCP

1/16W

5%

MF-LF

402

10K

R8770

1

2

10K

402

MF-LF

5%

1/16W

HDCP

R8771

1

2

75

75

CRITICAL

SOI

AT88SC080C

HDCP

U8770

4

12

3

76

5

8

72 71 70

MF-LF

1/16W

5%

1K

402

R8737

1

2

402

MF-LF

1/16W

5%

1K

R8734

1

2

MF-LF

402

5%

1/16W

1K

R8735

1

2

5%

1K

1/16W

402

MF-LF

R8736

1

2

79

79

79

353S1579 353S1718

ALL (U8700)

TS3V330 alt to TS3V340

353S1718

1

U8700

CRITICAL

IC,TS3V340,QUAD VIDEO SW,QFN16

SYNC_MASTER=M75_MLB

SYNC_DATE=04/02/2007

051-7261

16

109

87

GPU Straps

GPU_MIOB_D<9>
GPU_MIOA_D<6>

GPU_GPIO_11

GPU_GPIO_9

GPU_GPIO_7

GPU_GPIO_6

GPU_GPIO_5

GPU_GPIO_4

GPU_GPIO_3

TP_GPU_GSTATE<0>

MAKE_BASE=TRUE

=PP3V3_GPU_TMDS

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_I2CA_SDA

GPU_I2CA_SDA

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_I2CA_SCL

GPU_I2CA_SCL

TP_FB_A_MA13

TP_FB_B_MA12

TP_FB_B_MA13

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_FB_A_MA13

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_FB_B_MA12

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_FB_B_MA13GPU_I2CC_SDA

GPU_I2CC_SCL

GPU_I2CB_SDA

GPU_XTALOUT

GPU_SPDIF

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_SPDIF

GPU_STEREO

GPU_XTALSSIN

MAKE_BASE=TRUE

GPU_CLK27M_SS_GATED

GPU_THERMD_P

MAKE_BASE=TRUE

GPU_TDIODE_P

GPU_XTALIN

MAKE_BASE=TRUE

GPU_CLK27M_GATED

MAKE_BASE=TRUE

GPU_PANEL_DDC_CLK

MAKE_BASE=TRUE

GPU_DVI_DDC_CLK

MAKE_BASE=TRUE

GPU_DVI_DDC_DATA

MAKE_BASE=TRUE

GPU_PANEL_DDC_DATA

GPU_TV_Y_VGA_G

GPU_TV_COMP_VGA_B

GPU_TV_C_VGA_R

MAKE_BASE=TRUE

GPU_HPD

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_GPIO_1

MAKE_BASE=TRUE

GPU_BL_PWM

MAKE_BASE=TRUE

GPU_BKLT_EN

GPU_PANEL_EN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

GPU_VGA_EN_L

NO_TEST=TRUE

NC_GPU_GPIO_8

MAKE_BASE=TRUE

TP_GPU_GSTATE<1>

MAKE_BASE=TRUE

GPU_VCORE_VID0

MAKE_BASE=TRUE

GPU_GPIO_14

GPU_GPIO_10

MAKE_BASE=TRUE

GPU_VCORE_VID2

=GPUVCORE_EN

=PP3V3_GPU_TMDS_FET

GPU_TMDS_PWREN_L

MAKE_BASE=TRUE

GPU_VCORE_PWRCTL0
GPU_VCORE_PWRCTL1

MAKE_BASE=TRUE

TP_FB_A_MA12

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_FB_A_MA12

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_STEREO

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_XTALOUT

GPU_I2CB_SCL

GPU_THERMD_N

MAKE_BASE=TRUE

GPU_TDIODE_N

LVDS_U_DATA_N<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_U_DATAN<3>

LVDS_L_DATA_P<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_L_DATAP<3>

GPU_CSYNC

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_CSYNC

LVDS_L_DATA_N<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_L_DATAN<3>

GPU_MIOA_CLKOUT_P

MAKE_BASE=TRUE

TP_GPU_MIOA_CLKOUT_P

GPU_MIOA_D<7>

GPU_MIOA_D<5..2>

GPU_MIOA_D<11..10>

GPU_G2

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_G2

GPU_B2

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_B2

GPU_R2

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_R2

GPU_H2SYNC

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_H2SYNC

GPU_MIOA_CLKOUT_N

MAKE_BASE=TRUE

TP_GPU_MIOA_CLKOUT_N

GPU_MIOA_CTL3

MAKE_BASE=TRUE

TP_GPU_MIOA_CTL3

GPU_MIOA_DE

GPU_MIOA_HSYNC

GPU_V2SYNC

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_V2SYNC

MAKE_BASE=TRUE

TP_GPU_MIOB_CLKOUT_P

MAKE_BASE=TRUE

TP_GPU_MIOB_CLKOUT_N

MAKE_BASE=TRUE

TP_GPU_MIOB_DE

MAKE_BASE=TRUE

TP_GPU_MIOB_CLKIN

LVDS_U_DATA_P<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_U_DATAP<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_FBA_CMD27

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_FBC_CMD27 TP_FBC_CMD27

TP_FBA_CMD27

TP_FBA_CMD28

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_FBA_CMD28

TP_FBC_CMD28

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_FBC_CMD28

GPU_ROM_SO

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_ROM_SO

GPU_ROM_SI

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_ROM_SI

GPU_ROM_SCLK

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_ROM_SCLK

GPU_ROM_CS_L

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_ROM_CS_L

GPU_MIOB_D<1>

GPU_GPIO_13

GPU_I2CH_SDA

=PP3V3_GPU_HDCP

GPU_I2CH_SCL

MAKE_BASE=TRUE

GPU_VCORE_VID1

MAKE_BASE=TRUE

FB_VREF_UNTERM

GPU_VGA_G

GPU_GPIO_8

GPU_VGA_EN_L

GPU_TV_COMP

GPU_TV_Y

GPU_TV_C

GPU_IFPD_CLK_P

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_IFPD_CLK_P

GPU_IFPD_CLK_N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_IFPD_CLK_N

MAKE_BASE=TRUE

TP_GPU_MIOB_D<10>

GPU_MIOB_VSYNC

MAKE_BASE=TRUE

TP_GPU_MIOB_VSYNC

GPU_XTALOUTBUFF

GPU_XTALSSIN

GPU_MIOA_D<8>

GPU_MIOB_D<8>

=PP3V3_GPU_MIO

GPU_GPIO_12

GPU_GPIO_2

GPU_GPIO_1

GPU_GPIO_0

GPU_MIOA_D<0>

GPU_MIOA_D<9>

GPU_MIOB_D<0>

GPU_VGA_B

GPU_VGA_R

GPU_MIOB_HSYNC

GPU_MIOA_D<1>

=PP3V3_GPU_MIO

GPU_MIOB_D<3>

GPU_MIOB_D<11>

GPU_MIOB_D<5>
GPU_MIOB_D<4>

=PP3V3_GPU_VIDEOMUX

GPU_MIOB_D<10>

MAKE_BASE=TRUE

TP_GPU_MIOB_D<2>

GPU_MIOB_D<7..6>

GPU_MIOB_CTL3

GPU_MIOB_CLKOUT_P

GPU_MIOB_CLKIN

GPU_MIOA_VSYNC

MAKE_BASE=TRUE

TP_GPU_MIOA_VSYNC

GPU_MIOB_DE
GPU_MIOB_D<2>

MAKE_BASE=TRUE

TP_GPU_MIOB_D<7..6>

GPU_MIOB_CLKOUT_N

MAKE_BASE=TRUE

TP_GPU_MIOA_HSYNC

MAKE_BASE=TRUE

TP_GPU_MIOA_D<11..10>

MAKE_BASE=TRUE

TP_GPU_MIOA_D<7>

MAKE_BASE=TRUE

TP_GPU_MIOA_D<5..2>

MAKE_BASE=TRUE

TP_GPU_MIOA_DE

MAKE_BASE=TRUE

TP_GPU_MIOB_CTL3

74

74

74

90

91

90

90

90

90

90

74

73

73

73

73

73

73

73

73

73

73

73

8

75

75

70

70

70 75

75

75

73

73

73

73

30

73 51

73 30

79

78

78

79

74

73

73

8

70 75

73

51

75

75

75

75

73

73

73

73

75

75

75

75

73

73

73

73

75

7

7

75

70

70

70

70

73

73

73

73

73

73

8

73

74

75

75

73

73

73

73

73

8

73

73

73

73

73

73

73

73

73

8

73

73

73

73

8

73

73

73

73

73

73

73

73

73

7

Preliminary

OUT
OUT
OUT

OUT
OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT
OUT
OUT

OUT

OUT

OUT

OUT

OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT

BI
BI

BI
BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IFPA_TXD0

I2CB_SDA

I2CB_SCL

I2CA_SDA

I2CA_SCL

DACC_VSYNC

DACC_HSYNC

DACC_BLUE

DACC_GREEN

DACC_RED

DACB_CSYNC

DACB_BLUE

DACB_GREEN

DACB_RED

DACA_VSYNC

DACA_HSYNC

DACA_BLUE

DACA_GREEN

DACA_RED

IFPD_TXD6

IFPD_TXD5

IFPD_TXD4

IFPD_TXC

IFPC_TXD2

IFPC_TXD1

IFPC_TXD0

IFPC_TXC

IFPB_TXD7

IFPB_TXD6

IFPB_TXD5

IFPB_TXD4

IFPB_TXC

IFPA_TXD3

IFPA_TXD2

IFPA_TXD1

IFPA_TXC

I2CS_SDA

I2CS_SCL

I2CH_SDA

I2CH_SCL

I2CC_SDA

I2CC_SCL

DACC_RSET

DACC_VREF

DACC_IDUMP

DACC_VDD

DACB_RSET

DACB_VREF

DACB_IDUMP

DACB_VDD

DACA_RSET

DACA_VREF

DACA_IDUMP

DACA_VDD

IFPCD_RSET

IFPCD_VPROBE

IFPCD_PLLGND

IFPCD_PLLVDD

IFPD_IOVDD

IFPC_IOVDD

IFPAB_RSET

IFPAB_VPROBE

IFPAB_PLLGND

IFPB_IOVDD

IFPA_IOVDD

IFPAB_PLLVDD

IFPA_TXC_L

IFPA_TXD0_L

IFPA_TXD1_L

IFPA_TXD2_L

IFPA_TXD3_L

IFPB_TXC_L

IFPB_TXD4_L

IFPB_TXD5_L

IFPB_TXD6_L

IFPB_TXD7_L

IFPC_TXC_L

IFPC_TXD0_L

IFPC_TXD1_L

IFPC_TXD2_L

IFPD_TXC_L

IFPD_TXD4_L

IFPD_TXD5_L

IFPD_TXD6_L

OUT
OUT

OUT

BI
BI
BI
BI
BI
BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Power aliases required by this page:

Signal aliases required by this page:

Sum of peak currents: 240mA

20mA peak per diff pair

200mA peak for all pairs

20mA peak per diff pair

Place at AD6

BOM options provided by this page:

- =PP3V3_GPU_IFPCD_IOVDD

120mA peak

150mA peak

40mA peak

Place at AE7

40mA peak

Place at AF9 Place at AF8

Composite/S-Video VGA Component

Comp B Pb

Y G Y

C R Pr

(NONE)

(NONE)

- =PP1V8_GPU_IFPX

- =PP3V3_GPU_DAC

I2CS must be pulled up if not used
I2CS addr fixed at 0x9E,0x9F

Page Notes

160mA peak for all pairs

Sum of peak currents: 390mA

120mA peak

MF-LF
402

1%
1/16W

1K

NO STUFF

R8850

1

2

FERR-220-OHM

0402

L8805

1 2

20%

0.1UF

10V
402

CERM

C8806

1

2

FERR-220-OHM

0402

L8815

1 2

FERR-220-OHM

0402

L8830

1 2

FERR-220-OHM

0402

L8820

1 2

FERR-220-OHM

0402

NO STUFF

L8840

1 2

90 74

90 74

90 74

90 79

90 79

90 79

90 74

90 74

90 79

90 79

90 79

90 79

90 79

90 79

90 79

7

90 79

7

90 79

90 79

90 79

90 79

90 79

90 74

90 74

90 78

90 78

90 78

90 78

90 78

90 78

90 78

90 78

90 78

90 78

90 78

90 78

90 78

90 78

90 78

90 78

74

74

74

74

4.7UF

20%

CERM

6.3V
603

C8805

1

2

4.7UF

603

CERM

6.3V

20%

C8820

1

2

74

74

74

74

74

90 74

90 74

90 74

NB8P-GS-W-A2

BGA

OMIT

(5 OF 8)

U8000

AH12

AJ12

AF10

AG9

AH11

AH9

AD10

AH10

AK10

T6

U5

T5V7

R6

R7

V8

R5

AE5

AG6

AG7

AG4

AF6

AF5

AD7

AH4

AG5

K2
J3

H4
J4

G2
G1
G3
H3
C1
B1

AF9 AK9

AJ9

AH6
AJ6
AH8
AH7
AJ8
AK8
AJ5
AH5

AD9

AC9

AL5

AM4

AF8

AK4
AL4

AM6
AM5
AM7
AL7
AK6
AK5
AK7
AL8

AD6 AM2

AM3

AE2
AE1
AF1
AF2
AG1
AH1

AB10

AA10

AH3

AK3

AE7

AG3
AH2

AK1
AJ1
AL2
AL1
AJ2
AJ3

74

74

1/16W
402

MF-LF

124

1%

R8852

1

2

1/16W
402

MF-LF

124

1%

R8853

1

2

1/16W
MF-LF
402

124

1%

R8854

1

2

74

0.1UF

CERM
402

20%
10V

C8852

1

2

0.1UF

10V

20%
CERM

402

C8853

1

2

0.1UF

10V

20%
CERM

402

C8854

1

2

74

74

74

74

48

48

20%

0.1UF

10V
402

CERM

C8821

1

2

20%

0.1UF

10V
CERM
402

C8831

1

2

20%

6.3V
CERM
603

4.7UF

C8830

1

2

20%
10V
CERM
402

0.1UF

C8841

1

2

4.7UF

603

CERM

6.3V

20%

NO STUFF

C8840

1

2

20%

6.3V
CERM

603

4.7UF

C8845

1

2

4.7UF

CERM

603

6.3V

20%

C8815

1

2

20%

0.1UF

10V
402

CERM

C8801

1

2

4.7UF

20%

CERM

6.3V
603

C8800

1

2

0402

FERR-220-OHM

L8800

1 2

402

CERM

10V

0.1UF

20%

C8803

1

2

CERM
402

0.01UF

16V

20%

NO STUFF

C8856

1

2

CERM
402

0.01UF

16V

20%

NO STUFF

C8855

1

2

402

CERM

10V

0.1UF

20%

C8813

1

2

20%

0.1UF

10V
402

CERM

C8811

1

2

20%

6.3V
603

CERM

4.7UF

C8810

1

2

0402

FERR-220-OHM

L8810

1 2

20%

0.1UF

10V
402

CERM

C8816

1

2

MF-LF
402

1%
1/16W

1K

NO STUFF

R8851

1

2

051-7261

16

109

88

NV G84M Video Interfaces

SYNC_MASTER=M75_MLB

SYNC_DATE=03/19/2007

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

PP1V8_GPU_IFPCD_PLLVDD_F

VOLTAGE=1.8V

LVDS_U_CLK_N

=PP3V3_GPU_DAC

=PP1V8_GPU_IFPX

GPU_VGA_G

GPU_G2
GPU_B2

GPU_I2CC_SDA

GPU_I2CC_SCL

GPU_DACC_RSET

GPU_DACC_VREF

GPU_IFPAB_VPROBE
GPU_IFPCD_VPROBE

GPU_DACB_VREF
GPU_DACC_VREF

GPU_DACA_RSET GPU_DACA_VREF

GPU_IFPAB_RSET
GPU_IFPCD_RSET

GPU_DACC_RSET

GPU_DACB_RSET

=PP3V3_GPU_IFPCD_IOVDD

MIN_LINE_WIDTH=0.4 mm

PP1V8_GPU_IFPAB_IOVDD_F

MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.8V

PP1V8_GPU_IFPAB_PLLVDD_F

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.8V

MIN_LINE_WIDTH=0.4 mm

PP3V3_GPU_IFPCD_IOVDD_F

MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

PP3V3_GPU_DACA_VDD_F

MIN_LINE_WIDTH=0.35 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V

PP3V3_GPU_DACB_VDD_F

MIN_LINE_WIDTH=0.35 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V

PP3V3_GPU_DACC_VDD_F

MIN_LINE_WIDTH=0.35 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V

LVDS_L_DATA_P<0>

GPU_I2CB_SDA

GPU_I2CB_SCL

GPU_I2CA_SDA

GPU_I2CA_SCL

GPU_V2SYNC

GPU_H2SYNC

GPU_R2

GPU_CSYNC

GPU_TV_COMP

GPU_TV_Y

GPU_TV_C

GPU_VGA_VSYNC

GPU_VGA_HSYNC

GPU_VGA_B

GPU_VGA_R

TMDS_DATA_P<5>

TMDS_DATA_P<4>

TMDS_DATA_P<3>

GPU_IFPD_CLK_P

TMDS_DATA_P<2>

TMDS_DATA_P<1>

TMDS_DATA_P<0>

TMDS_CLK_P

LVDS_U_DATA_P<3>

LVDS_U_DATA_P<2>

LVDS_U_DATA_P<1>

LVDS_U_DATA_P<0>

LVDS_U_CLK_P

LVDS_L_DATA_P<3>

LVDS_L_DATA_P<2>

LVDS_L_DATA_P<1>

LVDS_L_CLK_P

GPU_DACB_RSET

GPU_DACB_VREF

GPU_DACA_RSET

GPU_DACA_VREF

GPU_IFPCD_RSET

GPU_IFPCD_VPROBE

GPU_IFPAB_RSET

GPU_IFPAB_VPROBE

LVDS_L_CLK_N

LVDS_L_DATA_N<0>

LVDS_L_DATA_N<1>

LVDS_L_DATA_N<2>

LVDS_L_DATA_N<3>

LVDS_U_DATA_N<0>

LVDS_U_DATA_N<1>

LVDS_U_DATA_N<2>

LVDS_U_DATA_N<3>

TMDS_CLK_N

TMDS_DATA_N<0>

TMDS_DATA_N<1>

TMDS_DATA_N<2>

GPU_IFPD_CLK_N

TMDS_DATA_N<3>

TMDS_DATA_N<4>

TMDS_DATA_N<5>

=GPU_I2CS_SDA

=GPU_I2CS_SCL

GPU_I2CH_SDA

GPU_I2CH_SCL

8

8

75

75

75

75

75

75

75 75

75

75

75

75

8

75

75

75

75

75

75

75

75

Preliminary

OUT

V-

V+

+

-

THRM_PAD

VFB

TRIP

VOUT

EN_PSV

GND

PGND

V5DRV

V5FILT

DRVL

DRVH

LL

TON

VBST

PGOOD

SYM (2 OF 2)

IN

OUT

G

D

S

G

D

S

G

D

S

IN

IN

IN

IN

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

<Re><Rd>

<Rb>

<Ra>

(GPUVCORE_VFB)

VID1 VID0

- - -

1.050V (max batt)

1.050V (rsvd state)

Y Y -

Y - -

C D E State

VID2

0

0 1

0

1

1 1

0
0

1

Y Y Y

Place near C8940

Vout = 1.25V - 0.96V

(=PPVCORE_GPU_REG)

(GPUVCORE_VFB)

(L8920 limit)

18A max output

(GND)

(=PPVCORE_GPU_REG)

GPU VCore Current Sense

1

(GPUVCORE_TON)

GPU VCore Regulator

Vout = 0.75V * (1 + Ra / Req)
Vout(min) = 0.75V * (1 + Ra / Rb)
Req = Rb || Rc || Rd || Re

<Rc>

All other states not defined

1.125V (balanced)

1.250V (max perf)

GPU VCore Setpoints

0

2.87K

1/16W
MF-LF

1%

402

R8921

1

2

7.15K

402

1%

MF-LF

1/16W

R8922

1

2

603

X5R

10UF

20%

6.3V

C8940

1

2

NO STUFF

402

25V
X7R

1000pF

10%

C8921

1

2

NO STUFF

1%

402

61.9K

MF-LF

1/16W

R8923

1

2

10%

470pF

CERM

402

50V

C8998

12

49

10%

CERM

470pF

50V
402

C8992

12

1/16W

1%

1M

MF-LF

402

R8998

1 2

1/16W
MF-LF

1%

1M

402

R8992

1 2

6.3V

10%

402

CERM

1uF

C8995

1

2

20.0K

MF-LF

402

1/16W

1%

R8993

1 2

MF-LF

402

20.0K

1%

1/16W

R8991

1 2

PLACEMENT_NOTE=Place R8990 close to L8920

1/16W
MF-LF

402

1%

649

R8990

1

2

PLACEMENT_NOTE=Place R8994 close to L8920

NO STUFF

1%

1K

402

MF-LF

1/16W

R8994

1 2

PLACEMENT_NOTE=Place C8990 close to L8920

402

6.3V

0.47UF

CERM-X5R

10%

C8990

12

PLACEMENT_NOTE=Place R8997 close to L8920

CRITICAL

10KOHM-5%

0603-LF

R8997

1

2

MF-LF

1/16W

1K

1%

402

R8996

1

2

5%

100PF

402

50V
CERM

NO STUFF

C8920

1

2

CASE-D2-LF

22UF

25V

20%

POLY

CRITICAL

C8930

1

2

CRITICAL

RJK0305DPB

LFPAK

Q8920

5

4

1 2 3

LFPAK

RJK0301DPB

CRITICAL

Q8922

5

4

1 2 3

RJK0301DPB

LFPAK

CRITICAL

Q8921

5

4

1 2 3

CRITICAL

IHLP4040DZ11-SM

1.0UH-20A

L8920

1 2

PLACEMENT_NOTE=Place C8991 close to L8920

10%

402

6.3V

0.22UF

CERM-X5R

C8991

12

HPA00141AIDCKR

SC70-5

CRITICAL

U8995

1

3

4

2

5

402

MF-LF

1/16W

1%

200K

R8919

1

2

50V

10%

603-1

X7R

0.1UF

C8915

1

2

10%
603

X5R

16V

1uF

C8900

1

2

CRITICAL

TPS51117RGY_QFN14

QFN

U8900

13

9

1

7

12

8

6

15

2

11

10

4

14

5

3

2.2UF

603

X5R

10%
16V

C8901

1

2

SM

XW8900

1 2

74 66

66

MF-LF

10.5K

1%

402

1/16W

R8905

1

2

200

402

MF-LF

1/16W

1%

R8901

1

2

1/16W

5%

402

7.5K

MF-LF

R8973

1 2

SOT-363

2N7002DW-X-F

Q8923

3

5

4

SOT-363

2N7002DW-X-F

Q8923

6

2

1

402

MF-LF

5%

1/16W

7.5K

R8974

1 2

2N7002DW-X-F

SOT-363

Q8925

6

2

1

7.5K

402

MF-LF

5%

1/16W

R8975

1 2

74

100K

5%

MF-LF

1/16W

402

R8970

1

2

100K

1/16W
MF-LF

402

5%

R8971

1

2

74

402

MF-LF

1/16W

1%

28K

R8924

1

2

MF-LF

1/16W

16.9K

402

1%

R8925

1

2

20%
10V
CERM
402

0.1UF

C8973

1

2

20%
10V
CERM
402

0.1UF

C8974

1

2

20%
10V
CERM
402

0.1UF

C8975

1

2

5%

402

MF-LF

1/16W

100K

R8972

1

2

74

X5R

25V

1UF

10%

603

C8932

1

2

CRITICAL

POLY

20%
25V

CASE-D2-LF

22UF

C8931

1

2

TANT

D2T

10%

330UF

2.0V

CRITICAL

C8942

1

2 3

CRITICAL

2.0V

330UF

10%

D2T

TANT

C8943

1

23

SM

XW8920

1

2

74

74

NO STUFF

1.5K

1/16W
MF-LF
402

5%

R8967

1

2

NO STUFF

1K

5%
MF-LF

1/16W
402

R8962

1

2

NO STUFF

1%

1/16W

4.99K

MF-LF

402

R8960

1 2

NO STUFF

1%

4.99K

402

MF-LF

1/16W

R8965

1 2

NO STUFF

402

CERM

0.01UF

10%
16V

C8961

1 2

NO STUFF

16V

CERM

10%

0.01UF

402

C8966

1 2

NO STUFF

402

MF-LF

1/16W

5%

1K

R8966

1

2

NO STUFF

1K

5%

MF-LF

1/16W

402

R8961

1

2

NO STUFF

402

1/16W
MF-LF

5%

1.5K

R8963

1

2

NO STUFF

1/16W
402

5%
MF-LF

1K

R8968

1

2

NO STUFF

402

MF-LF

5%

1/16W

10K

R8964

1 2

NO STUFF

10K

1/16W

5%

MF-LF

402

R8969

1 2

NO STUFF

SOT-363-LF

MMDT3904XF

Q8927

5

3

4

NO STUFF

MMDT3904XF

SOT-363-LF

Q8927

2

6

1

1%

53.6K

402

MF-LF

1/16W

NO STUFF

R8927

1

2

402

MF-LF

53.6K

1/16W

1%

NO STUFF

R8926

1

2

SM

XW8901

1

2

GPU (G84M) Core Supply

SYNC_MASTER=M75_MLB

SYNC_DATE=03/21/2007

89

109

051-7261

16

=PPVCORE_GPU_REG

GPUVCORE_VFB_D

GPUVCORE_VFB_E

GPUVCORE_VFB_PC0

=PP5V_S5_GPUVCORE

GPUVCORE_TON

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.25 mm

GPUVCORE_VBST

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm

GPUVCORE_LL

MIN_NECK_WIDTH=0.2 mm

GPU_VCORE_PWRCTL0

PVCORE_GPU_NTC

=PP3V3_GPU_VCORELOGIC

GPU_VCORE_VID2_RC

GPU_VCORE_VID1_RC

GND_GPUVCORE_SGND

GPUISENS_NTC

=PP3V3R5V_GPU_GPUISENS

GPUVCORE_IOUT

GPUISENS_NEG

GPUISENS_POS

GPUISENS_RC

=GPUVCORE_EN

GND_GPUVCORE_SGND

=GPUVCORE_PGOOD

MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE

GPUVCORE_DRVH

MIN_LINE_WIDTH=0.6 mm

=PPVIN_GPU_GPUVCORE

GPUVCORE_TRIP

GPU_VCORE_VID0

GPUVCORE_VFB_PC0

GPUVCORE_VFB_PC1

GND_GPUVCORE_SGND

GPU_VCORE_VID1

GND_GPUVCORE_SGND

PC0_BIAS_B

PC1_BIAS_B

GPU_VCORE_PWRCTL1

=PP1V2_GPU_VCOREPWRCTL

PC0_BIAS

PC0_DIV

PC1_BIAS

PC1_DIV

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm
VOLTAGE=5V

PP5V_S5_GPUVCORE_V5FILT

GPUVCORE_VFB_PC1

GND_GPUVCORE_SGND

GPU_VCORE_VID2

GPU_VCORE_VID0_RC

PPVCORE_GPU_XW

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.25 mm
VOLTAGE=1.25V

GPUVCORE_DRVL

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

GPUVCORE_VFB_C

GPUVCORE_VFB

GND_GPUVCORE_SGND

MIN_LINE_WIDTH=0.6 mm
VOLTAGE=0V

MIN_NECK_WIDTH=0.25 mm

49

8 7

76

8

8

76

8

76

8

76

76

76

76

8

76

76

76

Preliminary

D

S

G

G

D

S

IN

SYM_VER-1

SYM_VER-1

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

518S0289

Panel has 2K pull-ups

no-panel case (development).

100K pull-ups are for

LCD (LVDS) INTERFACE

50V

20%

402

CERM

0.001uF

C9010

1

2

402

CERM

50V

0.001uF

20%

C9001

1

2

FERR-250-OHM

SM

CRITICAL

L9000

50V

10%

402

CERM

0.0022uF

C9000

1 2

1/16W

5%

402

MF-LF

100K

R9001

1/16W

5%

402

MF-LF

100K

R9000

1

2

TSOP-LF

SI3443DV

Q9000

1

2

5

63

4

SOT23-LF

2N7002

Q9001

3

1

2

1/16W

5%

402

100K

MF-LF

R9094

1

2

1/16W

5%

402

MF-LF

100K

R9011

1

2

1/16W

5%

MF-LF

100K

402

R9010

1

2

79

CRITICAL

F-RT-SM

MSC-RB30-5-FA

J9000

33

34

1

10
11
12
13
14
15
16
17
18
19

2

20
21
22
23
24
25
26
27
28
29

3

30

4
5
6
7
8
9

CRITICAL

1210-4SM1

90-OHM-100MA

PLACEMENT_NOTE=Place close to connector.

L9010

1

2 3

4

PLACEMENT_NOTE=Place close to connector.

90-OHM-100MA

1210-4SM1

CRITICAL

L9011

1

2 3

4

90

109

16

051-7261

LVDS Display Connector

SYNC_MASTER=M75_MLB

SYNC_DATE=03/19/2007

VOLTAGE=3.3V

PP3V3_SW_LCD

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

LVDS_L_CLK_CONN_F_N
LVDS_L_CLK_CONN_F_P

LVDS_U_CLK_CONN_F_N
LVDS_U_CLK_CONN_F_P

=PP3V3_S0_DDC_LCD

LVDS_CONN_DDC_CLK
LVDS_CONN_DDC_DATA

PP3V3_SW_LCD_UF

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm
VOLTAGE=3.3V

LCD_PWREN_L_RC

LCD_PWREN_L

LVDS_L_DATA_CONN_P<0>

LVDS_L_DATA_CONN_N<0>

LVDS_U_DATA_CONN_N<0>

LVDS_L_DATA_CONN_P<2>

LVDS_L_DATA_CONN_N<2>

LVDS_L_DATA_CONN_P<1>

LVDS_L_DATA_CONN_N<1>

LVDS_U_DATA_CONN_P<0>

LVDS_U_DATA_CONN_N<1>
LVDS_U_DATA_CONN_P<1>

LVDS_U_DATA_CONN_N<2>
LVDS_U_DATA_CONN_P<2>

LVDS_L_CLK_CONN_N

LVDS_L_CLK_CONN_P

LVDS_PANEL_EN

LVDS_U_CLK_CONN_N

LVDS_U_CLK_CONN_P

=PP3V3_S0_LCD

91

91

91

91

91

91

91

91

91

91

91

91

91

91

91

91

91

91

8

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

79

8

Preliminary

G

SD

G

SD

SYM_VER-1

G

SD

SYM_VER-1

SYM_VER-1

SYM_VER-1

SYM_VER-1

SYM_VER-1

SYM_VER-1

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

G

S

D

G

S

D

IN

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(Place close to GPU)

TMDS Filtering

(DACB TV Y)

(DACB TV COMP)

(DACB TV C)

(Place close to connector)

ANALOG FILTERING

PLACE CLOSE TO CONNECTOR

VGA SYNC Buffers

(PP5V_S0_DDC)

GPU Isolation / Level-Shift

Isolation required for DVI->ADC Adapter

DVI DDC Current Limit

DVI INTERFACE

(55mA requirement per DVI spec)

514-0278

1/16W

5%

402

MF-LF

10K

R9421

1

2

1/16W

5%

402

MF-LF

10K

R9420

1

2

SOT-363

2N7002DW-X-F

Q9411

6

2

1

SOT-363

2N7002DW-X-F

Q9411

3

5

4

1/16W

5%

402

MF-LF

270K

R9422

1

2

100pF

CERM
402

5%
50V

C9413

1

2

4.7K

MF-LF
402

5%
1/16W

R9412

1

2

4.7K

MF-LF

402

5%

1/16W

R9410

1

2

50V

5%

402

CERM

100pF

C9411

1

2

0.01uF

CERM

603

20%
50V

C9410

1

2

CRITICAL

SM-1

400-OHM-EMI

L9410

1 2

SM-LF

0.5AMP-13.2V

CRITICAL

F9410

1 2

B0530WXF

SOD-123

D9410

1 2

100pF

CERM
402

5%
50V

C9414

1

2

100

MF-LF

402

5%

1/16W

R9411

1 2

100

MF-LF

402

5%

1/16W

R9413

1 2

1/16W

5%

402

MF-LF

100

R9414

1 2

3.3pF

CERM
402

0.25%
50V

C9441

1

2

1%

1/16W

150

MF-LF

402

VGA_TERM_FILTER

R9442

1

2

150

MF-LF

402

1%

1/16W

VGA_TERM_FILTER

R9440

1

2

150

1/16W

1%

402

MF-LF

VGA_TERM_FILTER

R9441

1

2

3.3pF

CERM
402

0.25%
50V

C9442

1

2

50V

0.25%
402

CERM

3.3pF

C9440

1

2

1/16W

5%

402

MF-LF

33

R9450

1 2

1/16W

5%

402

MF-LF

33

R9451

1 2

CRITICAL

QH11121-RIG02-4F

F-RT-TH-DVI

J9400

C1

C2

C3

C4

C5AC5B

31

32

33

34

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

3

4

5

6

7

8

9

1/16W

5%

402

MF-LF

20K

R9415

1

2

NO STUFF

MF-LF

402

SIGNAL_MODEL=EMPTY

49.9

1%

1/16W

R9486

1

2

49.9

NO STUFF

1/16W

1%

402

MF-LF

SIGNAL_MODEL=EMPTY

R9482

1

2

49.9

NO STUFF

1/16W

1%

402

MF-LF

SIGNAL_MODEL=EMPTY

R9478

1

2

0

MF-LF

402

5%

1/16W

R9473

1 2

1/16W

5%

402

MF-LF

0

R9472

1 2

49.9

NO STUFF

MF-LF

402

1%

1/16W

SIGNAL_MODEL=EMPTY

R9470

1

2

NO STUFF

MF-LF

402

1%

SIGNAL_MODEL=EMPTY

1/16W

49.9

R9466

1

2

370-OHM

CRITICAL

PLACEMENT_NOTE=Place close to connector.

SM

L9472

1

2 3

4

10V

20%
402

CERM

0.1uF

C9451

1

2

10V

20%
402

CERM

0.1uF

C9450

1

2

SC70

MC74VHC1G08

PLACEMENT_NOTE=Place close to connector.

U9450

3

2

1

4

5

PLACEMENT_NOTE=Place close to connector.

SC70

MC74VHC1G08

U9451

3

2

1

4

5

1%

1/16W

402

MF-LF

49.9

NO STUFF

SIGNAL_MODEL=EMPTY

R9462

1

2

SOT-363

2N7002DW-X-F

Q9415

6

2

1

1/16W

5%

402

MF-LF

270K

R9423

1

2

PLACEMENT_NOTE=Place close to connector.

CRITICAL

1210-4SM1

90-OHM-100MA

L9460

1

2 3

4

90-OHM-100MA

1210-4SM1

CRITICAL

PLACEMENT_NOTE=Place close to connector.

L9464

1

2 3

4

1210-4SM1

90-OHM-100MA

CRITICAL

PLACEMENT_NOTE=Place close to connector.

L9468

1

2 3

4

CRITICAL

PLACEMENT_NOTE=Place close to connector.

1210-4SM1

90-OHM-100MA

L9480

1

2 3

4

CRITICAL

1210-4SM1

90-OHM-100MA

PLACEMENT_NOTE=Place close to connector.

L9476

1

2 3

4

1210-4SM1

PLACEMENT_NOTE=Place close to connector.

90-OHM-100MA

CRITICAL

L9484

1

2 3

4

24

90 75

90 75

90 75

90 75

90 75

90 75

90 75

90 75

90 75

90 75

90 75

90 75

90 75

90 75

90 75

90 75

90 74

90 74

90 74

74

74

SOT-363

2N7002DW-X-F

Q9414

6

2

1

SOT-363

2N7002DW-X-F

Q9414

3

5

4

28

74

NO STUFF

0.01UF

10%

402

CERM

16V

C9462

1

2

CERM

402

10%

0.01UF

16V

NO STUFF

C9466

1

2

16V

0.01UF

NO STUFF

CERM

402

10%

C9470

1

2

NO STUFF

CERM

402

10%

0.01UF

16V

C9478

1

2

NO STUFF

CERM

402

10%

0.01UF

16V

C9482

1

2

16V

0.01UF

10%

402

CERM

NO STUFF

C9486

1

2

16V

0.01UF

10%

402

CERM

NO STUFF

C9474

1

2

49.9

NO STUFF

MF-LF

402

1%

1/16W

SIGNAL_MODEL=EMPTY

R9474

1

2

MEA2010P-SM

210MHZ

CRITICAL

FL9440

27

36

45

18

NONE

NONE

SHORT

NONE
402

OMIT

CX9491

1

2

NONE

SHORT

NONE
402

NONE

OMIT

CX9490

1

2

402

NONE

SHORT

NONE
NONE

OMIT

CX9492

1

2

OMIT

402

NONE

SHORT

NONE
NONE

CX9493

1

2

OMIT

NONE

SHORT

NONE
NONE

402

CX9403

1

2

402

NONE

NONE

SHORT

NONE

OMIT

CX9402

1

2

402

NONE

NONE
NONE

SHORT

OMIT

CX9401

1

2

402

NONE

NONE

SHORT

NONE

OMIT

CX9400

1

2

402

MF-LF

1%

49.9

NO STUFF

1/16W

R9463

12

NO STUFF

49.9

1%

1/16W MF-LF

402

R9467

12

NO STUFF

49.9

1%

1/16W MF-LF

402

R9471

12

NO STUFF

402

MF-LF1/16W

1%

49.9

R9475

12

NO STUFF

49.9

1%

1/16W MF-LF

402

R9479

12

NO STUFF

49.9

1%

1/16W MF-LF

402

R9483

12

1/16W

NO STUFF

49.9

1%

MF-LF

402

R9487

12

1%

1/16W

150

MF-LF

402

VGA_TERM_CONN

R9443

1

2

402

150

1%

MF-LF

1/16W

VGA_TERM_CONN

R9445

1

2

402

MF-LF

150

1/16W

1%

VGA_TERM_CONN

R9444

1

2

051-7261

16

109

94

DVI Display Connector

SYNC_MASTER=M75_MLB

SYNC_DATE=03/19/2007

TMDS_DATA_N<0>

TMDS_DATA_R0

TMDS_DATA_N<1>

TMDS_DATA_R1

TMDS_DATA_N<2>

VGA_B

VGA_G

VGA_R

=GND_CHASSIS_DVI_BOT

=GND_CHASSIS_DVI_TOP

TMDS_DATA_R2

TMDS_DATA_F_P<2>

GPU_TV_C_VGA_R

TMDS_DATA_N<4>

TMDS_DATA_N<5>

TMDS_CLK_F_N

GPU_TV_Y_VGA_G

TMDS_DATA_F_N<5>

TMDS_DATA_F_P<5>

TMDS_DATA_F_N<0>

=GPU_HPD_ENABLE

GPU_HPD

GPU_DVI_DDC_DATA

GPU_HPD_BILAT

=PP3V3_GPU_DVI

DVI_HOTPLUG_DET

=PP5V_S0_SB_HPD

GPU_DVI_DDC_CLK

DVI_DDC_DATA_R

VOLTAGE=5V

PP5V_S0_DDC_F

MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm

DVI_DDC_DATA

DVI_DDC_CLK

VOLTAGE=5V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

PP5V_S0_DDC_PULLUPS

=PP5V_S0_DVI_DDC

DVI_HPD_R

VGA_VSYNC

TMDS_CLK_F_P

TMDS_CLK_F_N

TMDS_DATA_F_N<2>
TMDS_DATA_F_N<1>

TMDS_DATA_F_N<0>

TMDS_DATA_F_P<2>TMDS_DATA_F_P<0>
TMDS_DATA_F_P<1>

TMDS_DATA_F_N<4>

TMDS_DATA_F_P<4>

TMDS_DATA_F_N<5>

TMDS_DATA_F_P<5>

=PP3V3_GPU_VGASYNC

VGA_VSYNC

VGA_VSYNC_R

VGA_HSYNC

VGA_HSYNC_R

TMDS_DATA_F_P<4>

TMDS_DATA_F_N<4>

TMDS_DATA_N<3>

TMDS_DATA_F_P<3>

TMDS_DATA_F_N<3>

TMDS_DATA_F_P<1>

TMDS_DATA_F_N<1>

TMDS_DATA_F_N<2>

TMDS_CLK_F_P

VGA_B

VGA_R

GPU_TV_COMP_VGA_B

VGA_G

=PP3V3_GPU_VGASYNC

TMDS_DATA_F_P<0>

GPU_VGA_HSYNC

GPU_VGA_VSYNC

=PP3V3_GPU_TMDSBIAS

=PP3V3_GPU_TMDSBIAS

=PP3V3_GPU_TMDSBIAS

=PP3V3_GPU_TMDSBIAS

=PP3V3_GPU_TMDSBIAS

=PP3V3_GPU_TMDSBIAS

VGA_HSYNC

DVI_HPD

PP5V_S0_DDC

VOLTAGE=5V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

DVI_DDC_CLK_R

TMDS_DATA_F_P<3>

TMDS_DATA_F_N<3>

=GND_CHASSIS_DVI_BOT

TMDS_CLK_R_N

=PP3V3_GPU_TMDSBIAS

TMDS_DATA_P<0>

TMDS_CLK_P

TMDS_CLK_CMF

TMDS_DATA_P<2>

TMDS_DATA_P<1>

TMDS_DATA_P<3>

TMDS_DATA_R3

TMDS_DATA_R4

TMDS_DATA_R5

TMDS_CLK_N

TMDS_DATA_P<5>

TMDS_DATA_P<4>

TMDS_CLK_R_P

91

91

91

78

91

91

91

91

91

91

91

91

91

91

91

91 91

91

91

91

91

91

78

91

91

91

91

91

91

91

91

91

91

91

91

91

78

91

78

78

78

78

78

78

91

91

91

78

78

78

78

78

9

9

78

78

78

78

78

8

8

8

78

78

78

78

78

78

78 78

78

78

78

78

78

8

78

91

78

91

78

78

78

78

78

78

78

78

78

78

78

8

78

8

8

8

8

8

8

78

78

78

9

91

8

91

Preliminary

SYM_VER-3

GND

SEL

DB19*

DB18*

DB17*

DB16*

DB15*

DB14*

DB13*

DB12*

DB11*

DB10*

DB9* DH19

DH14

DH13

DH12

DH11

DH10

DH9

DH15
DH16
DH17
DH18

DB4*
DB5*
DB6*
DB7*
DB8*

DB0*
DB1*
DB2*
DB3*

DH4

DH3

DH2

DH1

DH0

DH8

DH7

DH6

DH5

DA15
DA16
DA17
DA18
DA19

DA13
DA14

DA12

DA11

DA10

DA5
DA6
DA7
DA8
DA9

DA0
DA1
DA2
DA3
DA4

VDD

G

S D

G

S D

IN

IN

OUT

BIBI

BI

OUT
OUT
OUT

OUT

OUT

OUT
OUT
OUT
OUT
OUT
OUT

OUT

OUT

OUT
OUT
OUT

IN
IN
IN
IN
IN
IN
IN
IN

IN
IN
IN

IN
IN

IN
IN
IN
IN
IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN
IN
IN
IN
IN

IN
IN

IN
IN
IN

IN

IN

OUT

OUT

OUT

OUT

VPG

V2

V4

V3

VREF RST*

CRT

THRM_PAD

GND

PBR*

V1

OUT

G

D

S

G

D

S

IN

IN

IN

V+

V-

1B1

4B2

2B1
2B2
3B1
3B2
4B1

1B2

1A

2A

3A

4A

OE*

S

THRML

PAD

GND

VCC

SYM_VER-2

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Trst = 1.5ms

LTC2900 typical threshold is 93.5% (3.055V, 2.325V, 1.685V, 1.120V)

Mux Select Conditioning

GPU DDC Pass FETs

PGOOD delays are provided.

(Ext. GFX)

(Ext. GFX)

(Int. GFX)

NC

(Int. GFX)

Trst = 4.6ms/nF

LO=xB1

HI=xB2

be eliminated if GPIO moved to resume well.

should be before platform reset deasserts). Could

GPU power rails have come up and are valid (which

rails until GPIO switches back to default state and

is on SB core well. Keeps PGOOD looking at non-GPU

NOTE: NAND-gate required if EXTGPU_LVDS_EN GPIO

Alias to 3.3V if not used->

Panel/Backlight Control Mux

NOTE: New H/W and S/W challenge since NB gfx might
be powered off if using external GPU. S/W will have
to guarantee that the "other" device is ready before
a switch can occur. If mux select GPIO is still on a
core well, this could mean powering up IG supply will
be necessary before going to sleep to keep PGOODs valid.

transitions and ICHx will honor whatever

observed PGOOD will not change during S3

timer. If mux select on resume well, then

for PGOODs to be valid at end of 99 ms SMC

or <99ms PGOOD assertion time is required

and AND-gate is implemented, glitch filter

(32 us). If mux select is on core well

can create an S3 duration of 1 RTC clock

Fast wake condition is worst case. ICHx

NOTE: SEL = LOW selects port B

NC

LVDS I/F Mux

NB LVDS I/F

NC

NC

NC

GPU LVDS I/F

LVDS Data Mux Power Supply

LTC2900 provides programmable reset delay which is required to play nice with ICHx PGOOD circuit

PGOOD Monitor for GPU Rails

402

MF-LF

5%
1/16W

470K

R9596

1

2

BGA-LF

CRITICAL

CBTV4020

U9550

F1
H1
K1
K3
K4
K6
J7

K9
J10
G10
E10
C10
A10

A8

A7

A5

B4

A2

B1

D1

G1

J1

K2

J4

K5

K7

K8
K10
H10
F10
D10
B10

A9

B7

A6

A4

A3

A1

C1

E1

F2
H2
J2
J3
J5
J6
J8
J9
H9
F9
E9
C9
B9
B8
B6
B5
B3
B2
C2
E2

C5C6D2

D9G2G9H5H6

E3

E8F3F8

SOT-363

2N7002DW-X-F

Q9570

6

2

1

2N7002DW-X-F

SOT-363

Q9570

3

5

4

20%
10V

0.1UF

CERM

402

C9593

1

2

402

20%
10V

0.1UF

CERM

C9591

1

2

1K

1/16W
MF-LF
402

5%

R9595

1

2

74

15

77

77 74

15

91 77

91 77

91 77

91 77

91 77

91 77

91 77

91 77

91 77

91 77

91 77

91 77

91 77

91 77

91 77

91 77

74

15

74

15

74

15

79 30 28

9

84 15

84 15

84 15

84 15

84 15

84 15

84 15

84 15

84 15

84 15

84 15

84 15

84 15

84 15

84 15

90 75

90 75

90 75

7

90 75

90 75

90 75

7

90 75

90 75

90 75

90 75

90 75

90 75

90 75

90 75

90 75

84 15

90 75

81

77

CRITICAL

DFN

LTC2900

U9590

3

6

5

4

11

2

10

1

9

7

8

1/16W
MF-LF
402

124K

1%

R9593

1

2

100K

402

1/16W

1%
MF-LF

R9594

1

2

330PF

10%
50V

402

CERM

C9595

1

2

0.1UF

20%
10V

CERM

402

C9592

12

79 30 28

10K

MF-LF

402

5%

1/16W

R9562

1

2

MF-LF

402

1/16W

10K

5%

R9545

1

2

5%

10K

MF-LF

402

1/16W

R9544

1

2

SOT-363

2N7002DW-X-F

Q9540

6

2

1

SOT-363

2N7002DW-X-F

Q9540

3

5

4

402

LVDS_SEL_RESUME

MF-LF

0

1/16W

5%

R9541

1 2

402

5%

1/16W

0

MF-LF

LVDS_SEL_CORE

R9542

1 2

0.1UF

LVDS_SEL_CORE

402

CERM

10V

20%

C9561

12

28 24

9 7

25

24 13

LVDS_SEL_RESUME

MF-LF

1/16W

5%

402

0

R9543

1 2

MF-LF

0

1/16W

5%

402

LVDS_SEL_CORE

R9563

1 2

MC74VHC1G00

LVDS_SEL_CORE

SC70-5

U9561

3

2

1

4

5

10K

1%
1/16W
MF-LF

402

R9555

1

2

CRITICAL

MAX4236EUTT

SOT23-6-LF

U9555

3

4

1

5

6

2

CERM

20%

0.1UF

10V
402

C9555

12

31.6K

402

MF-LF

1/16W

1%

R9556

1

2

0.1UF

402

CERM

10V

20%

C9556

1

2

10V

20%
402

CERM

0.1UF

C9550

1

2

0.1UF

CERM

402

20%
10V

C9560

1

2

15.8K

MF-LF

402

1%

1/16W

R9570

1

2

15.8K

1%

MF-LF

402

1/16W

R9571

1

2

CRITICAL

QFN

74CBTLV3257

U9560

42

3

75

6

911

10

1214

13

15

8117

16

1/16W

5%

402

MF-LF

10K

R9560

1

2

100K

MF-LF

402

5%

1/16W

R9561

1

2

10V

20%

CERM

402

0.1uF

C9590

1

2

1%
MF-LF

402

1/16W

28K

R9590

1

2

1%
1/16W

402

71.5K

MF-LF

R9591

1

2

SYNC_DATE=03/19/2007

SYNC_MASTER=M75_MLB

16

051-7261

95

109

LVDS Interface Mux

GPU_BKLT_EN
LVDS_BKLT_EN
GPU_BL_PWM

=PP2V5_GPU_LTC2900
PP1V8_GPU

=PP3V3_S0_LVDS_MUX

P2V5_S0_VREF

VOLTAGE=2.5V

PP2V5_S0_LVDS_MUX

MIN_NECK_WIDTH=0.10 mm

MIN_LINE_WIDTH=0.25 mm

LVDS_U_DATA_P<2>

LVDS_U_CLK_P

LVDS_U_CLK_N

LVDS_U_DATA_N<1>

LVDS_U_DATA_P<1>

LVDS_A_CLK_P

LVDS_B_DATA_P<0>

LVDS_B_DATA_N<2>
LVDS_B_DATA_N<0>

LVDS_A_DATA_P<2>

LVDS_A_DATA_P<0>

LVDS_A_DATA_N<0>

LVDS_A_CLK_N

LVDS_A_DATA_P<1>

LVDS_A_DATA_N<1>

LVDS_A_DATA_N<2>

LVDS_B_DATA_P<1>

LVDS_B_DATA_P<2>

LVDS_B_CLK_P

LVDS_B_CLK_N

LVDS_B_DATA_N<1>

LVDS_U_DATA_P<0>

LVDS_U_DATA_N<0>

LVDS_U_DATA_N<2>

LVDS_L_CLK_P
LVDS_L_CLK_N

LVDS_L_DATA_N<0>
LVDS_L_DATA_P<0>
LVDS_L_DATA_P<2>

LVDS_L_DATA_P<1>

LVDS_L_DATA_N<1>

LVDS_L_DATA_N<2>

LVDS_U_DATA_CONN_P<0>

LVDS_U_DATA_CONN_N<2>
LVDS_U_DATA_CONN_N<0>

LVDS_L_DATA_CONN_P<0>

LVDS_L_DATA_CONN_N<0>

LVDS_L_CLK_CONN_N

LVDS_L_CLK_CONN_P

LVDS_L_DATA_CONN_P<1>

LVDS_L_DATA_CONN_N<1>

LVDS_L_DATA_CONN_N<2>

LVDS_L_DATA_CONN_P<2>

LVDS_U_DATA_CONN_P<1>
LVDS_U_DATA_CONN_N<1>

LVDS_U_CLK_CONN_N
LVDS_U_CLK_CONN_P
LVDS_U_DATA_CONN_P<2>

LVDSDATAMUX_SEL_GPU_L

PP2V5_S0_LVDS_MUX

LVDSDATAMUX_SEL_GPU_L

LVDSCTRLMUX_SEL_GPU_L

GPU_PGOOD_P1V2_DIV

EXTGPU_LVDS_SEL

EXTGPU_LVDS_EN_QUAL

EXTGPU_LVDS_EN

GPU_PGOOD_VREF

GPU_PGOOD_VPG

PM_ALL_GPU_PGOOD

GPU_PGOOD_CRT

PM_ALL_GPU_PGOOD

LVDS_BKLT_CTL

LVDS_VDD_EN

TP_PM_ALL_GFX_PGOOD

LCDBKLT_PWREN

GPU_PANEL_EN

LCDBKLT_PWM_UNBUF

LVDS_PANEL_EN

LVDSCTRLMUX_SEL_GPU_L

PM_ALL_NBGFX_PGOOD

=PP3V3_S0_LVDS_MUX

PLT_RST_L

=PP3V3_S0_LVDS_MUX

LVDS_DDC_DATA

=GPU_DDC_ENABLE

GPU_PANEL_DDC_CLK

MAKE_BASE=TRUE

LVDS_CONN_DDC_DATA

MAKE_BASE=TRUE

LVDS_CONN_DDC_CLK

=PP3V3_GPU_LVDS_DDC

PP1V25_GPU

PP2V5_S0_LVDS_MUX

EXTGPU_LVDS_EN33_L

GPU_PANEL_DDC_DATA

LVDS_DDC_CLK

PP3V3_GPU

=PP3V3_S0_LVDS_MUX

RSVD_EXTGPU_LVDS_EN

79

79

79

79

8

8

8

79

79

79

79

79

79

8

8

28

8

8

79

8

8

Preliminary

BI
BI

IN

IN

IN

OUT

OUT

BI

BI

SYM_VER-1

SYM_VER-1

OUT

IN

BI
BI

OUT

OUT

BI
BI

OUT

BI

BI

BI
BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

No Connect

GND
+5V
PWM

NC

NC

INV_15INCH
INV_17INCH?

INV_SPLIT

518S0474

516S0350

NC

518S0369

518S0487

IR & Sleep LED Connector

NC

BOM Options:

INV_BYPASS

"Antenna" Pad

Inverter Connectors

No Connect

No Connect

VFB (Voltage Sense)

IFB (Current Sense)

Bridge 1

Bridge 2

Split Inverter

PBUS

Classic Inverter

Bluetooth (M13P) & SATA HDD Flex Connector

516S0350

Top-Case Connector

86 24

7

CRITICAL

M-ST-SM

QT500166-L020

J9660

1

10

1112
1314
1516

2

34
56
78
9

86 24

7

86 23

86 23

402

25V

CERM

0.0047uF

10%

PLACEMENT_NOTE=Place C9661 next to C9660

C9661

2 1

10%
25V

0.0047uF

CERM

402

PLACEMENT_NOTE=Place C9660 close to southbridge

C9660

2 1

46

7

86 23

86 23

86 24

86 24

1210-4SM1

90-OHM-100MA

PLACEMENT_NOTE=Place FL9660 close to southbridge

FL9665

PLACEMENT_NOTE=Place FL9665 close to J9660

90-OHM-100MA

1210-4SM1

FL9660

25V

0.0047uF

402

CERM

10%

PLACEMENT_NOTE=Place C9665 close to J9660

C9666

2 1

0.0047uF

10%

CERM

25V
402

PLACEMENT_NOTE=Place C9666 next to C9665

C9665

2 1

HS8806F-B

CRITICAL

M-RT-SM

J9610

7

8

1
2
3
4
5
6

54

54

48

48

QT500166-L020

CRITICAL

M-ST-SM

J9600

1

10
11 12
13 14
15 16

2

3 4
5 6
7 8
9

46 45

46 45

7

86 24

86 24

CRITICAL

SC-75

RCLAMP0502B

D9600

3

1

2

81

82 81

82 81

82

82

M-RT-SM

SM04B-ACH

J9650

5

6

1
2
3
4

INV_SPLIT

M-RT-SM

BM02B-ACHKS-GAN-TF-LF-SN-M

J9655

3

4

1
2

M76 Specific Connectors

SYNC_MASTER=(MASTER)

96

109

16

051-7261

SYNC_DATE=(MASTER)

=PP3V3_S3_TOPCASE

KBDLED_RETURN

=I2C_TOPCASE_SDA

SATA_A_R2D_P

=GND_CHASSIS_LEFTCLUTCH

INV_P5V_HV_IFB

USB_IR_P

=PP3V42_G3H_LIDSWITCH

USB_TPAD_N

USB_TPAD_P

SATA_A_R2D_C_P

SATA_A_R2D_C_N

USB_BT_P

USB_BT_N

=PP5V_S0_HDD

SATA_A_D2R_A_N

=PP3V3_S3_BT

SATA_A_D2R_N

SATA_A_D2R_A_P

SATA_A_R2D_N

SATA_A_R2D_UF_N

SATA_A_R2D_UF_P

SATA_A_D2R_UF_P

SATA_A_D2R_UF_N

SATA_A_D2R_P

=PP5V_S3_IR

USB_IR_N

SYS_LED_ANODE

=PP5V_S3_TOPCASE

SMC_LID

SMC_ONOFF_L

=I2C_TOPCASE_SCL

INV_HV_PIN5

KBDLED_ANODE

INV_GND_HV

=GND_CHASSIS_LEFTCLUTCH

INV_PWR_HV

INV_PWM_HV_VFB

80

80

44

8

44

8

86

9

8

8

8

86

91

91

91

91

7

8

9

Preliminary

IN

P-CHN

SGD

D

S

G

N-CHN

VEE

VCC

OUT

OUT

IN

IN

IN

OUT

IN

IN

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

WF:1.12V? (17")

x.xV reference
WF:0.5V?

x.xV reference

.

WF:0.92V? (15")

WF:Why 0603?

WF:Can we remove?

PLT_RST_L input ensures backlight
PWM does not glitch during RESET.

79

NTZD3155C

SOT-563

Q9805

3

5

4

SOT-563

NTZD3155C

Q9805

6

2

1

INV_SPLIT

SSOP-5

TA75S393F

U9830

1

3

4

5

2

MF-LF

402

1/16W

1%

INV_SPLIT

15.0K

R9811

1 2

1%
1/16W
MF-LF

INV_SPLIT

402

3.32K

R9814

1

2

10%
16V

402

CERM-X5R

0.022UF

INV_SPLIT

C9855

1

2

100K

1/16W

402

MF-LF

1%

INV_SPLIT

R9854

1

2

MF-LF
402

1%
1/16W

332K

INV_SPLIT

R9850

1

2

MF-LF

1/16W

1%

68.1K

INV_SPLIT

402

R9812

1

2

47.0K

1/16W

1%

402

MF-LF

INV_SPLIT

R9855

1

2

10K

1/16W

1%

402

MF-LF

INV_SPLIT

R9853

1

2

1/16W

1%

402

MF-LF

100K

INV_SPLIT

R9851

1

2

CERM

5%

100PF

50V
402

INV_SPLIT

C9850

1

2

INV_SPLIT

0.01UF

X7R

603-1

10%
50V

C9822

1

2

INV_SPLIT

MF-LF

402

1/16W

1%

3.32K

R9825

1

2

INV_SPLIT
1SS387

SOD-523

D9835

1

2

0.0022UF

INV_SPLIT

CERM

50V
402

10%

C9820

1

2

1%

1M

MF-LF

1/16W

402

INV_SPLIT

R9821

1

2

402

MF-LF

INV_SPLIT

4.7K

1/16W

1%

R9835

1

2

5.1M

603

MF-LF

1/10W

INV_SPLIT

5%

R9834

1 2

SOD-523

INV_SPLIT

1SS387

D9845

1 2

MF-LF

1%

100K

1/16W

402

INV_SPLIT

R9845

1

2

INV_SPLIT

402

16V

10%
X7R

0.015UF

C9845

1

2

INV_SPLIT

3.65K

402

MF-LF

1/16W

1%

R9842

1

2

MF-LF

1/16W

1%

402

1.21K

INV_SPLIT

R9843

1

2

100PF

INV_SPLIT

CERM

5%

402

50V

C9821

1

2

402

1%

20.0K

INV_SPLIT

1/16W
MF-LF

R9810

1

2

1%

100K

402

1/16W
MF-LF

INV_SPLIT

R9832

1

2

INV_SPLIT

1/16W
MF-LF

402

1%

9.09K

R9830

1

2

402

1/16W

15.0K

INV_SPLIT

1%

MF-LF

R9820

1

2

INV_SPLIT

20.0K

1%

MF-LF

402

1/16W

R9833

1 2

INV_SPLIT

0.022UF

402

16V

10%
CERM-X5R

C9832

1

2

MF-LF

402

1/16W

1K

INV_SPLIT

1%

R9831

1

2

5%

100PF

INV_SPLIT

402

50V

CERM

C9840

1

2

INV_SPLIT

1%
1/16W
MF-LF
402

100K

R9840

1

2

200K

INV_SPLIT

1/16W

1%

402

MF-LF

R9841

1

2

INV_SPLIT

TA75W393FU

SSOP

U9820

2

3

1

8

4

SSOP

INV_SPLIT

TA75W393FU

U9820

6

5

7

8

4

INV_SPLIT

SC81

MA3S132D0L

D9825

3

1

2

UP04601

SSMINI6-F1

INV_SPLIT

Q9850

2

6

1

UP04601

SSMINI6-F1

INV_SPLIT

Q9850

5

3

4

82

82

82

INV_SPLIT

SOT-363

HN2D01FU

D9850

52

INV_SPLIT

HN2D01FU

SOT-363

D9850

61

INV_SPLIT

SOT-363

HN2D01FU

D9850

4 3

SOT-363

HN2D01FU

INV_SPLIT

D9930

4

3

82 80

82 80

82

80

10UF

20%
X5R

603

6.3V

C9830

1

2

INV_SPLIT

1/16W

402

MF-LF

1%

11.3K

R9813

1

2

MF-LF

1/16W

5%

100K

402

R9805

2

1

MF-LF

402

5%

1/16W

100K

R9806

1

2

79

MC74VHC1G08

SC70

U9800

3

2

1

4

5

0.1uF

402

10V

20%

CERM

C9800

1

2

9

SYNC_DATE=01/23/2007

SYNC_MASTER=M75_LIO

051-7261

16

109

98

Inverter Support

=PP3V3_S0_LCDBKLT

PLT_RESET_L

INV_STBY

INV_HV_PIN5

INV_UNNAMED_H

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V

PP5V_SW_LCDBKLT

INVERTER_SGND

INV_DIM_DIV

INV_DIM

INVERTER_SGND

LCDBKLT_PWM_UNBUF

INV_PWM_R

INV_LOSC

PXVX_UNNAMED_B

INV_UNNAMED_L

PP4V5_SW_VREG

INVERTER_SGND

INV_UNNAMED_C

INV_UNNAMED_E

INV_UNNAMED_G

INV_UNNAMED_A

PP4V5_SW_VREG

INV_P5V_HV_IFB

INV_PWM_HV_VFB

INV_UNNAMED_I

INV_VCHOP

INV_UNNAMED_J

PXVX_UNNAMED_A

INV_UNNAMED_D

LCDBKLT_PWREN_L

=PP5V_S0_LCDBKLT

LCDBKLT_PWREN

INV_UNNAMED_K

LCDBKLT_PWM

82

82

82

82

82

82

82

8

7

81

81

81

81

81

8

7

Preliminary

BI

BI

BI

BI

D

S

G

N-CHN

P-CHN

SGD

IN

IN

LOSC

TIMER

ROSC

GND

STBY

ERRV

DIM

VCHOP

VREG

FREF

FRATE

LPC

FBI

OVP

NGATE2

PGATE2

PGND

NGATE1

VCC

PGATE1

D

S

G

N-CHN

S

D

G

P-CHN

S

D

G

P-CHN

D

S

G

N-CHN

IN

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Split Inverter: VFB (Voltage Sense)

Classic Inverter: +5V

Split Inverter: Bridge

Classic Inverter: GND

Classic Inverter: PBUS

Classic Inverter: PWM

Split Inverter: IFB (Current Sense)

Split Inverter: Bridge

(PPBUS_S0_LCDBKLT_FUSED)

(INV_LOSC)

0402-LF

CRITICAL

FERR-120-OHM-1.5A

INV_BYPASS

L9993

12

81 80

81 80

80

80

CRITICAL

0402-LF

INV_BYPASS

FERR-120-OHM-1.5A

L9992

1 2

20%
50V

INV_BYPASS

402

CERM

0.001uF

C9991

1

2

IHLP2525CZ-SM

INV_SPLIT

22UH-2.8A-129MOHM

L9950

1 2

1%
MF-LF

1/16W

15.0K

402

INV_17INCH

R9932

1

2

2AMP-32V-44MOHM

603

F9900

1 2

INV_SPLIT

NTZD3155C

SOT-563

Q9905

6

2

1

NTZD3155C

SOT-563

INV_SPLIT

Q9905

3

5

4

100PF

CERM

5%

402

50V

INV_SPLIT

C9932

1

2

1/16W
402

1%
MF-LF

INV_SPLIT

33.2

R9961

1

2

1%

MF-LF

1/16W

33.2

INV_SPLIT

402

R9951

1 2

CASE-B2

INV_SPLIT

20%
TANT

10UF

16V

C9951

1

2

205

INV_SPLIT

1%

MF-LF

402

1/16W

R9930

1

2

50V
402

0.001UF

CERM

10%

INV_SPLIT

C9924

1

2

INV_SPLIT

39.2K

1/16W

402

MF-LF

1%

R9924

1

2

CERM

10%
50V

402

0.0022UF

INV_SPLIT

C9925

1

2

INV_SPLIT

5.1M

5%

402

MF-LF

1/16W

R9925

1

2

1%

MF-LF

402

1/16W

511K

INV_SPLIT

R9960

1

2

INV_SPLIT

2.2UF

805

X5R-CERM

25V

10%

C9900

1

2

INV_SPLIT

5%

MF-LF

402

10M

1/16W

R9912

1

2

INV_SPLIT

MF-LF

1/16W

402

1%

10K

R9923

1 2

X5R

10V

10%

402

INV_SPLIT

1UF

C9923

1 2

10%
16V

402

CERM

0.01UF

INV_SPLIT

C9922

1

2

INV_SPLIT

1/16W

1%

402

MF-LF

1M

R9922

1

2

1/16W
MF-LF
402

1%

150K

INV_SPLIT

R9921

1

2

MF-LF

402

1%

1/16W

64.9K

INV_SPLIT

R9920

1

2

16V

X5R-CERM

0805

10%

10UF

NOSTUFF

C9950

1

2

1/16W

100K

402

MF-LF

5%

INV_SPLIT

R9910

1

2

402

MF-LF

INV_SPLIT

1/16W

20

1%

R9900

1 2

INV_SPLIT

10%

402

50V
CERM

0.0033UF

C9910

1

2

10K

INV_SPLIT

1/16W

1%

402

MF-LF

R9911

1

2

81

50V

10%

402

CERM

0.0022UF

INV_SPLIT

C9919

1

2

10%
X7R

50V

INV_SPLIT

0.01UF

603-1

C9918

1

2

INV_SPLIT

1%

402

1/16W
MF-LF

75K

R9917

1

2

1UF

10%
10V
X5R
402

INV_SPLIT

C9916

1

2

603

10%

6.3V
X5R-CERM

4.7UF

INV_SPLIT

C9915

1

2

0.0027UF

50V

10%

402

CERM

INV_SPLIT

C9914

1

2

1/16W
MF-LF

402

1%

5.11

INV_SPLIT

R9913

1

2

81

INV_SPLIT

CERM

402-LF

20%

2.2UF

6.3V

C9913

1

2

402

MF-LF

10M

5%

1/16W

R9950

1

2

BD9828FV

SSOP

INV_SPLIT

CRITICAL

U9900

16

17

7

9

10

15

11

8

2

5

6

1

4

3

12

14

13

20

19

18

HN2D01FU

SOT-363

INV_SPLIT

D9930

61

INV_SPLIT

SOT-363

HN2D01FU

D9930

52

NO STUFF

1.43M

1%
MF-LF

1/16W
402

R9931

1

2

INV_SPLIT

100K

5%

MF-LF

1/16W

402

R9905

1 2

5%
MF-LF

100K

1/16W
402

INV_SPLIT

R9906

1

2

SI7501DN

INV_SPLIT

PWRPK-1212-8

Q9950

5

4

3

INV_SPLIT

SI7501DN

PWRPK-1212-8

Q9950

6

2

1

SI7501DN

PWRPK-1212-8

INV_SPLIT

Q9960

6

2

1

INV_SPLIT

PWRPK-1212-8

SI7501DN

Q9960

5

4

3

81

81

INV_BYPASS

20%

0.001uF

50V
CERM
402

C9992

1

2

FERR-120-OHM-1.5A

INV_BYPASS

0402-LF

CRITICAL

L9991

1 2

SM

XW9950

12

INV_BYPASS

0.001uF

20%
CERM

402

50V

C9993

1

2

INV_BYPASS

0.001uF

20%
50V
CERM
402

C9994

1

2

0402-LF

FERR-120-OHM-1.5A

CRITICAL

INV_BYPASS

L9994

12

99

051-7261

109

16

SYNC_MASTER=M75_LIO

SYNC_DATE=01/23/2007

Inverter Control IC

114S0319

RES,11.3K,1%,1/16W,MF,402,LF

INV_15INCH

1 R9932

MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V

MIN_LINE_WIDTH=0.4 mm

PPBUS_S0_LCDBKLT_FUSED

MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V

MIN_LINE_WIDTH=0.4 mm

PPBUS_S0_INVERTER_VCC

INV_VCHOP

INV_ERRV

INV_DIM

INV_LOSC

INV_STBY

INVERTER_SGND

INV_TIMER

PP4V5_SW_VREG

VOLTAGE=4.5V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

INV_PGATE1

MIN_NECK_WIDTH=0.25 mm

MIN_NECK_WIDTH=0.25 mm

INV_NGATE2

MIN_LINE_WIDTH=0.25 mm

INV_ROSC

VOLTAGE=12.6V

INV_UNNAMED_Z

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm

SWITCH_NODE=TRUE

INV_P5V_HV_IFB

=GND_CHASSIS_INVERTER

INV_FBI_R

INV_LPC

INV_FRATE

INV_FBI

INV_OVP

INV_NGATE2_R

INV_NGATE1_R

INV_PGATE2

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

MIN_NECK_WIDTH=0.25 mm

INVERTER_SGND

MIN_LINE_WIDTH=0.4 mm
VOLTAGE=0V

LCDBKLT_PWM

INV_PWR_HV

MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V
SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.4 mm

INV_GND_HV

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.4 mm
VOLTAGE=12.6V

PP5V_SW_LCDBKLT

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm

PPBUS_SW_INVERTER

VOLTAGE=12.6V

INV_PWR_EN_L

PP5V_SW_LCDBKLT

INV_FREF

INV_VREG_RC

INV_PWM_HV_VFB

=PPBUS_S0_LCDBKLT

INV_PWR_EN_DIV_L

MIN_LINE_WIDTH=0.25 mm

INV_NGATE1

MIN_NECK_WIDTH=0.25 mm

82

82

82

9

82

81

81

81

7

81

81

7

81

7

7

7

8

Preliminary

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

(FSB_CPURST_L)

(See above)

specifying a target differential impedance.

Intel says to route with 7 mil spacing without

NOTE: 7 mil gap is for VCCSense pair, which

(See above)

ELECTRICAL_CONSTRAINT_SET

SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.2 & 4.3

All FSB signals with impedance requirements are 55-ohm single-ended.

NOTE: Design Guide allows closer spacing if signal lengths can be shortened.

Design Guide recommends FSB signals be routed only on internal layers.

Worst-case spacing is 2:1 within Data bus, with 3:1 spacing to the DSTBs.

DG recommends at least 25 mils, >50 mils preferred

SPACING

NET_TYPE

PHYSICAL

CPU / FSB Net Properties

(See above)

(See above)

Worst-case spacing is 2:1 within Addr bus, with 3:1 spacing to the ADSTBs.

DSTB complementary pairs are spaced 1:1 and routed as differential pairs.

NOTE: Design Guide does not indicate FSB spacing to other signals, assumed 3:1.

SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4

Some signals require 27.4-ohm single-ended impedance.

Most CPU signals with impedance requirements are 55-ohm single-ended.

CPU Signal Constraints

Design Guide recommends each strobe/signal group is routed on the same layer.

FSB (Front-Side Bus) Constraints

*

FSB_DATA2DATA

?

=2:1_SPACING

* Y

=27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE

CPU_27P4S

7 MIL 7 MIL

=1:1_DIFFPAIR

FSB_DSTB_55S

=1:1_DIFFPAIR=1:1_DIFFPAIR

=55_OHM_SE

*

=55_OHM_SE =55_OHM_SE

?

*

CPU_GTLREF

25 MIL

25 MIL

?

CPU_COMP

*

?

CPU_VCCSENSE

*

25 MIL

?

=3:1_SPACING

*

FSB_ADDR2ADSTB

?

=3:1_SPACING

FSB_ADSTB

*

?

=2:1_SPACING

FSB_ADDR2ADDR

*

=55_OHM_SE

FSB_55S

=STANDARD

=55_OHM_SE

*

=55_OHM_SE =55_OHM_SE

=STANDARD

SYNC_DATE=01/25/2007

CPU/FSB Constraints

SYNC_MASTER=T9_NOME

100 109

16

051-7261

*

FSB_DATA2DSTB

?

=3:1_SPACING

=3:1_SPACING

*

FSB_DSTB

?

?

FSB_ADDR

=3:1_SPACING

*

?

=2:1_SPACING

*

FSB_COMMON

FSB_ADDR2ADSTB

FSB_ADDR

FSB_ADSTB

*

FSB_DATA2DATA

FSB_DATA

*

FSB_DATA

FSB_ADDR2ADDR

*

FSB_ADDR FSB_ADDR

FSB_DSTBFSB_DATA

*

FSB_DATA2DSTB

CPU_55S

=55_OHM_SE=55_OHM_SE

*

=55_OHM_SE

Y =STANDARD =STANDARD

=2:1_SPACING

?

*

CPU_ITP

=3:1_SPACING

FSB_DATA

*

?

=2:1_SPACING

?

CPU_2TO1

*

NB_BSEL<1>

CPU_55S

CPU_2TO1

CPU_DPRSTP_L

CPU_55S

CPU_2TO1

CPU_DPRSTP_L

CPU_COMP<2>

CPU_COMP CPU_COMP

CPU_27P4S

CPU_COMPCPU_COMP

CPU_COMP<1>

CPU_55S

CPU_FROM_SB

CPU_DPSLP_L

CPU_55S

CPU_BSEL0

CPU_BSEL<0>

CPU_2TO1

CPU_55S

CPU_55S

CPU_STPCLK_L

CPU_FROM_SB

CPU_COMP

CPU_27P4S

CPU_COMP<0>

CPU_COMP

CPU_FROM_SB

CPU_SMI_L

CPU_55S

CPU_55S

CPU_INIT_L

CPU_INIT_L

CPU_FROM_SB

CPU_A20M_L

CPU_55S

CPU_NMI

CPU_55S

CPU_FROM_SB

CPU_55S

CPU_INTR

CPU_FROM_SB

CPU_PWRGD

CPU_55S

CPU_PWRGD

CPU_PROCHOT_L

CPU_PROCHOT_L

CPU_2TO1

CPU_55S

CPU_FERR_L

CPU_FERR_L

CPU_55S

FSB_55S

FSB_ADSTB

FSB_ADSTB_L<0>

FSB_ADSTB0

FSB_A_L<35..17>

FSB_ADDR_GROUP1

FSB_55S

FSB_ADDR
FSB_ADSTB

FSB_ADSTB1

FSB_ADSTB_L<1>

FSB_55S

FSB_ADDR_GROUP0

FSB_55S

FSB_A_L<16..3>

FSB_ADDR

FSB_DSTB_L_N<3>

FSB_DSTBFSB_DSTB_55S

FSB_DSTB_L_N<2>

FSB_DSTB_55S FSB_DSTB

FSB_DSTB_L_P<2>

FSB_DSTB

FSB_DSTB2

FSB_DSTB_55S

FSB_DINV_L<2>

FSB_DATA_GROUP2

FSB_DATA

FSB_55S

FSB_COMMON

FSB_HIT_L

FSB_55S

FSB_COMMON

FSB_DATA_GROUP1

FSB_DATA

FSB_55S

FSB_DINV_L<1>

FSB_DSTB1

FSB_DSTB

FSB_DSTB_L_P<1>

FSB_DSTB_55S

FSB_55S

FSB_DATA_GROUP0

FSB_DATA

FSB_D_L<15..0>

FSB_DSTB_L_N<1>

FSB_DSTBFSB_DSTB_55S

FSB_DINV_L<3>

FSB_DATA_GROUP3

FSB_55S

FSB_DATA

FSB_COMMON

FSB_BNR_L

FSB_COMMON

FSB_55S

FSB_DSTB0

FSB_DSTB

FSB_DSTB_L_P<0>

FSB_DSTB_55S

FSB_DSTB

FSB_DSTB_L_N<0>

FSB_DSTB_55S

FSB_D_L<63..48>

FSB_DATA_GROUP3

FSB_55S

FSB_DATA

FSB_DSTB_L_P<3>

FSB_DSTB

FSB_DSTB3

FSB_DSTB_55S

FSB_ADDR

FSB_ADDR_GROUP0

FSB_55S

FSB_REQ_L<4..0>

FSB_COMMON

FSB_DEFER_L

FSB_COMMON

FSB_55S

FSB_CPURST_L

FSB_CPURST_L

FSB_COMMON

FSB_55S

FSB_COMMON

FSB_HITM_L

FSB_COMMON

FSB_55S

FSB_COMMON

FSB_DPWR_L

FSB_COMMON

FSB_55S

FSB_COMMON

FSB_DRDY_L

FSB_COMMON

FSB_55S

FSB_COMMON

FSB_LOCK_L

FSB_COMMON

FSB_55S

FSB_COMMON

FSB_RS_L<2..0>

FSB_COMMON

FSB_55S

FSB_DATA_GROUP0

FSB_55S

FSB_DATA

FSB_DINV_L<0>

FSB_COMMON

FSB_55S

FSB_BREQ0_L

FSB_COMMON

FSB_COMMON

FSB_55S

FSB_DBSY_L

FSB_COMMON

FSB_COMMON

FSB_ADS_L

FSB_COMMON

FSB_55S

FSB_COMMON

FSB_55S

FSB_BPRI_L

FSB_COMMON

FSB_COMMON

FSB_TRDY_L

FSB_COMMON

FSB_55S

FSB_DATA_GROUP1

FSB_DATA

FSB_D_L<31..16>

FSB_55S

FSB_DATA

FSB_DATA_GROUP2

FSB_D_L<47..32>

FSB_55S

CPU_2TO1

CPU_BSEL<1>

CPU_BSEL1

CPU_55S

CPU_55S

CPU_BSEL2

CPU_2TO1

CPU_BSEL<2>

CPU_IERR_L

CPU_55S

CPU_IERR_L

CPU_FROM_SB

CPU_IGNNE_L

CPU_55S

PM_THRMTRIP_L

CPU_2TO1

CPU_55S

PM_THRMTRIP_L
FSB_CPUSLP_L

CPU_55S

FSB_CPUSLP_L
PM_DPRSLPVR

CPU_2TO1

PM_DPRSLPVR

CPU_55S

CPU_2TO1

CPU_55S

IMVP_DPRSLPVR

CPU_55S

CPU_GTLREF

CPU_GTLREF

CPU_GTLREF

NB_BSEL<0>

CPU_2TO1

CPU_55S

CPU_COMP<3>

CPU_COMP

CPU_55S

CPU_COMP

CPU_55S

NB_BSEL<2>

CPU_2TO1

CPU_55S CPU_ITP

XDP_BPM_L5

XDP_BPM_L<5>

CLK_FSB

CLK_FSB_100D

XDP_CLK_N

XDP_CLK_P

CLK_FSB_100D

CLK_FSB

CPU_ITPCPU_55S

XDP_CPURST_L

IMVP6_VID<6..0>

CPU_2TO1

CPU_55S

CPU_VCCSENSE

CPU_VCCSENSE_N

CPU_VCCSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_VCCSENSE_P

CPU_VCCSENSE

CPU_27P4S

CPU_27P4S

IMVP6_VSEN_N

CPU_VCCSENSE

IMVP6_VSEN_P

CPU_VCCSENSE

CPU_27P4S

XDP_BPM_L<4..0>

XDP_BPM_L

CPU_ITPCPU_55S

CPU_55S CPU_ITP

XDP_TRST_L

XDP_TRST_L

CPU_55S CPU_ITP

XDP_TCK

XDP_TCK

CPU_55S CPU_ITP

XDP_TMS

XDP_TMS

CPU_55S CPU_ITP

XDP_TDO

XDP_TDO

CPU_55S CPU_ITP

XDP_TDI

XDP_TDI

CPU_2TO1

CPU_VID<6..0>

CPU_55S

59 23

23

14

46

59

30

16

23

23

47

13

59

14

14

14

14

14

14

14

14

14

14

14

14

14

14

14

14

14

14

14

14

13

14

14

14

14

14

14

14

14

14

14

23

14

25

30

30

88

88

59

16

10

10

30

10

23

23

23

23

23

10

46

23

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

14

10

10

10

10

10

14

10

10

10

10

14

14

10

10

30

30

23

16

10

16

59

16

16

13

30

30

12

59

59

13

13

13

13

13

13

12

13

7

10

10

7

10

7

10

10

10

10

10

10

7

10

10

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

10

7

7

7

7

7

10

7

7

7

7

10

10

7

7

10

10

10

10

10

7

7

7

10

13

10

13

10

13

13

13

7

11

11

59

59

10

10

10

10

10

10

11

Preliminary

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LVDS signals are 100-ohm +/- 20% differential impedence.

- 37.5-ohm +/- 15% from GMCH to first termination resistor.

- 50-ohm +/- 15% from first to second termination resistor.

- 55-ohm +/- 15% from second termination resistor to connector.
CRT_HSYNC/CRT_VSYNC signals are 55-ohm +/- 15% single-ended impedence.

CRT & TVDAC signal single-ended impedence varies by location:

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 8.1 - 8.3.

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 7.2, 9.2 & 10.5

DG Says 40 mil spacing minimum

NET_TYPE

SPACING

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

PCI-Express / DMI Bus Constraints

Video Signal Constraints

DG Says 40 mil spacing minimum

DG Says 30 mil spacing minimum

?

*

25 MIL

CRT_SYNC

TVDAC_2TVDAC

TVDACTVDAC

*

*

CRT_SYNC CRT_SYNC

CRT_SYNC2SYNC

=50_OHM_SE =50_OHM_SE=50_OHM_SE

=STANDARD* =STANDARD

=50_OHM_SE

CRT_50S

=100_OHM_DIFF

*

=100_OHM_DIFF

DMI_100D

=100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

PCIE_100D

=100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF

*

=100_OHM_DIFF

NB Constraints

SYNC_DATE=01/25/2007

101 109

16

051-7261

SYNC_MASTER=T9_NOME

=55_OHM_SE =55_OHM_SE=55_OHM_SE

CRT_55S

=55_OHM_SE

=STANDARD* =STANDARD

20 MIL

PCIE

*

?

TVDAC_2TVDAC

*

?

20 MIL

*

?

CRT_SYNC2SYNC

20 MIL

CRT 25 MIL

*

?

=100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF

*

LVDS_100D

=100_OHM_DIFF

TVDAC

25 MIL

*

?

CRT_2CRT

*

?

20 MIL

20 MIL

LVDS

*

?

DMI 20 MIL

?

*

CRT_2CRT

CRTCRT

*

TVDAC

CRT_50S

TV_A_DAC

TV_A_DAC

CRT_SYNC

CRT_55S

CRT_SYNC

CRT_VSYNC_R

CRT_50S

TV_C_DAC

TVDAC

TV_C_DAC

CRT_50S

TV_B_DAC

TVDAC

TV_B_DAC

CRT_RED

CRT

CRT_50S

CRT_RED

CRT_GREEN

CRT

CRT_50S

CRT_GREEN

CRT_BLUE

CRT

CRT_50S

CRT_BLUE

CRT

CRT_TVO_IREF

CRT_TVO_IREF

DMI_100D

DMI

DMI_N2S_N<3..0>

DMI

DMI_100D

DMI_S2N_P<3..0>

DMI_S2N

DMI

DMI_100D

DMI_S2N_N<3..0>

LVDS_IBG

LVDS_IBG

LVDS

LVDS_B_DATA3 LVDS

LVDS_100D

LVDS_B_DATA_N<3>

PCIE

PCIE_100D

PEG_D2R_N<15..0>

PCIE_100D

PEG_D2R_C_N<15..0>

PCIE

PCIE

PCIE_100D

PEG_R2D_C_N<15..0>

PCIE

PCIE_100D

PEG_R2D_C_P<15..0>

LVDS

LVDS_A_CLK

LVDS_A_CLK_N

LVDS_100D

LVDS_A_DATA

LVDS_A_DATA_P<2..0>

LVDS_100D

LVDS

LVDS_A_DATA

LVDS_A_DATA_N<2..0>

LVDS_100D

LVDS

LVDS_A_CLK

LVDS_A_CLK_P

LVDS

LVDS_100D

PCIE

PCIE_100D

PEG_D2R

PEG_D2R_P<15..0>

PCIE

PCIE_100D

PEG_R2D_N<15..0>

PCIE

PCIE_100D

PEG_R2D

PEG_R2D_P<15..0>

LVDS_A_DATA3

LVDS_A_DATA_N<3>

LVDS

LVDS_100D

LVDS_A_DATA3

LVDS_A_DATA_P<3>

LVDS

LVDS_100D

LVDS_100D

LVDS_B_CLK

LVDS_B_CLK_P

LVDS

LVDS_B_DATA3

LVDS_B_DATA_P<3>

LVDS_100D

LVDS

DMI_100D

DMI_N2S

DMI

DMI_N2S_P<3..0>

PCIE

PCIE_100D

PEG_D2R_C_P<15..0>

CRT_SYNC

CRT_55S

CRT_SYNC

CRT_HSYNC_R

LVDS_B_CLK

LVDS_B_CLK_N

LVDS

LVDS_100D
LVDS_100D

LVDS_B_DATA

LVDS_B_DATA_P<2..0>

LVDS

LVDS_B_DATA

LVDS_B_DATA_N<2..0>

LVDS

LVDS_100D

24

24

24

22

68

68

68

79

79

79

79

68

79

24

79

79

79

16

16

16

15

15

68

15

15

15

15

15

15

15

68

68

15

16

68

15

15

15

Preliminary

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

Memory Net Properties

NET_TYPE

SPACING

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

Need to support MEM_*-style wildcards!

DDR2 Memory Bus Constraints

*

MEM_DATA2MEM

MEM_DATA

MEM_CLK

=1.5:1_SPACING

MEM_DATA2DATA

*

?

MEM_DQS2MEM

*

=3:1_SPACING

?

MEM_CTRL

MEM_CTRL2MEM

MEM_CLK

*

MEM_CMD2MEM

MEM_CMD

*

MEM_DQS

*

MEM_CMD MEM_CMD

MEM_CMD2CMD

MEM_CMD2MEM

*

=3:1_SPACING

?

MEM_CTRL2CTRL

=2:1_SPACING

*

?

MEM_DATA2MEM =3:1_SPACING

*

?

*

MEM_CMD

MEM_CMD2MEM

MEM_DATA

102 109

16

051-7261

Memory Constraints

SYNC_MASTER=T9_NOME

SYNC_DATE=01/25/2007

=45_OHM_SE =45_OHM_SE =45_OHM_SE

MEM_45S

=STANDARD

=45_OHM_SE

=STANDARD*

=55_OHM_SE =55_OHM_SE =55_OHM_SE

*

MEM_55S

=STANDARD =STANDARD

=55_OHM_SE

=70_OHM_DIFF

=70_OHM_DIFF=70_OHM_DIFF =70_OHM_DIFF

* =70_OHM_DIFF =70_OHM_DIFF

MEM_70D

MEM_CMD

*

MEM_CMD2MEM

MEM_CLK

MEM_CTRL2CTRL

MEM_CTRL

*

MEM_CTRL

MEM_DATA

MEM_CTRL2MEM

*

MEM_CTRL

MEM_DQS

MEM_CTRL

*

MEM_CTRL2MEM

MEM_CTRL2MEM

*

=3:1_SPACING

?

*

MEM_DATA

MEM_DATA2MEM

MEM_CTRL

MEM_CMD

*

MEM_CTRL2MEM

MEM_CTRL

MEM_DATA2DATA

MEM_DATAMEM_DATA

*

MEM_DATA2MEM

MEM_DATA

*

MEM_DQS

MEM_DATA2MEM

MEM_DATA

*

MEM_CMD

*

=4:1_SPACING

MEM_CLK2MEM

?

*

MEM_CLK2MEM

MEM_CLKMEM_CLK

MEM_CLK2MEM

MEM_CLK

*

MEM_DATA

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

MEM_85D

=85_OHM_DIFF

=85_OHM_DIFF*

=85_OHM_DIFF

25 MIL

MEM_2OTHER

*

?

MEM_2OTHER

MEM_CLK

**

*

MEM_CLK2MEM

MEM_CTRL

MEM_CLK

MEM_CMD2CMD

*

=1.5:1_SPACING

?

*

MEM_CLK

MEM_CLK2MEM

MEM_DQS

*

MEM_CLK

MEM_CLK2MEM

MEM_CMD

*

MEM_CMD

MEM_CMD2MEM

MEM_CTRL

MEM_DQS

MEM_DQS2MEM

*

MEM_CLK

MEM_DQS

MEM_DQS2MEM

*

MEM_CTRL

*

MEM_DQS2MEM

MEM_DQS MEM_CMD
MEM_DQS

MEM_DQS2MEM

*

MEM_DATA

*

MEM_DQS2MEM

MEM_DQS MEM_DQS

MEM_2OTHER

MEM_DQS

**

MEM_2OTHER

MEM_DATA

* *

MEM_2OTHER

MEM_CMD

**

MEM_2OTHER

MEM_CTRL

* *

MEM_A_CNTL

MEM_45S

MEM_CTRL

MEM_CKE<1..0>

MEM_A_CMD

MEM_A_CAS_L

MEM_55S MEM_CMD

MEM_CMD

MEM_A_CMD

MEM_A_WE_L

MEM_55S

MEM_DATA

MEM_55SMEM_A_DQ_BYTE0

MEM_A_DQ<7..0>

MEM_55S

MEM_DATA

MEM_A_DQ_BYTE2

MEM_A_DQ<23..16>

MEM_DATA

MEM_55SMEM_A_DQ_BYTE1

MEM_A_DQ<15..8>

MEM_55S

MEM_DATA

MEM_A_DQ_BYTE6

MEM_A_DQ<55..48>

MEM_A_DQ_BYTE7

MEM_A_DQ<63..56>

MEM_55S

MEM_DATA

MEM_55S

MEM_A_DM1

MEM_DATA

MEM_A_DM<1>

MEM_DATA

MEM_55S

MEM_A_DM0

MEM_A_DM<0>

MEM_55S

MEM_DATA

MEM_A_DM2

MEM_A_DM<2>

MEM_A_DM<4>

MEM_55S

MEM_DATA

MEM_A_DM4

MEM_55S

MEM_DATA

MEM_A_DM3

MEM_A_DM<3>

MEM_A_DM<6>

MEM_55S

MEM_DATA

MEM_A_DM6

MEM_A_DQS_P<0>

MEM_A_DQS0

MEM_DQSMEM_85D

MEM_A_DQS_N<0>

MEM_DQSMEM_85D

MEM_A_DQS_N<1>

MEM_DQSMEM_85D

MEM_A_DQS_P<1>

MEM_A_DQS1

MEM_DQSMEM_85D

MEM_A_DQS3

MEM_A_DQS_P<3>

MEM_DQSMEM_85D

MEM_A_DQS2

MEM_A_DQS_P<2>

MEM_DQSMEM_85D

MEM_A_DQS_N<2>

MEM_DQSMEM_85D

MEM_A_DQS4

MEM_A_DQS_P<4>

MEM_DQSMEM_85D

MEM_A_DQS_N<3>

MEM_DQSMEM_85D

MEM_A_DQS_N<5>

MEM_DQSMEM_85D

MEM_A_DQS_N<4>

MEM_DQSMEM_85D

MEM_A_DQS5

MEM_A_DQS_P<5>

MEM_DQSMEM_85D

MEM_A_DQS6

MEM_A_DQS_P<6>

MEM_DQSMEM_85D

MEM_70D MEM_CLK

MEM_CLK_N<5..3>
MEM_CKE<4..3>

MEM_CTRL

MEM_45S

MEM_B_CNTL

MEM_CTRL

MEM_45S

MEM_CS_L<3..2>

MEM_B_CNTL

MEM_CMDMEM_55S

MEM_B_A<14..0>

MEM_B_CMD

MEM_CMDMEM_55S

MEM_B_WE_L

MEM_B_CMD

MEM_55S

MEM_DATA

MEM_B_DQ_BYTE1

MEM_B_DQ<15..8>

MEM_DATA

MEM_55SMEM_B_DQ_BYTE0

MEM_B_DQ<7..0>

MEM_55S

MEM_DATA

MEM_B_DQ_BYTE3

MEM_B_DQ<31..24>

MEM_55S

MEM_DATA

MEM_B_DQ_BYTE2

MEM_B_DQ<23..16>

MEM_55S

MEM_DATA

MEM_B_DQ_BYTE4

MEM_B_DQ<39..32>

MEM_55S

MEM_DATA

MEM_B_DQ_BYTE6

MEM_B_DQ<55..48>

MEM_55S

MEM_DATA

MEM_B_DQ_BYTE5

MEM_B_DQ<47..40>

MEM_DATA

MEM_55S

MEM_B_DM0

MEM_B_DM<0>

MEM_55S

MEM_DATA

MEM_B_DQ_BYTE7

MEM_B_DQ<63..56>

MEM_55S

MEM_DATA

MEM_B_DM2

MEM_B_DM<2>

MEM_55S

MEM_DATA

MEM_B_DM1

MEM_B_DM<1>

MEM_55S

MEM_DATA

MEM_B_DM3

MEM_B_DM<3>

MEM_55S

MEM_DATA

MEM_B_DM5

MEM_B_DM<5>

MEM_55S

MEM_DATA

MEM_B_DM4

MEM_B_DM<4>

MEM_55S

MEM_DATA

MEM_B_DM6

MEM_B_DM<6>

MEM_55S

MEM_DATA

MEM_B_DM7

MEM_B_DM<7>

MEM_DQSMEM_85D

MEM_B_DQS0

MEM_B_DQS_P<0>

MEM_DQSMEM_85D

MEM_B_DQS1

MEM_B_DQS_P<1>

MEM_DQSMEM_85D

MEM_B_DQS_N<0>

MEM_DQSMEM_85D

MEM_B_DQS2

MEM_B_DQS_P<2>

MEM_DQSMEM_85D

MEM_B_DQS_N<1>

MEM_DQSMEM_85D

MEM_B_DQS_N<2>

MEM_DQSMEM_85D

MEM_B_DQS_N<3>

MEM_DQSMEM_85D

MEM_B_DQS3

MEM_B_DQS_P<3>

MEM_DQSMEM_85D

MEM_B_DQS_N<4>

MEM_DQSMEM_85D

MEM_B_DQS4

MEM_B_DQS_P<4>

MEM_DQSMEM_85D

MEM_B_DQS5

MEM_B_DQS_P<5>

MEM_DQSMEM_85D

MEM_B_DQS6

MEM_B_DQS_P<6>

MEM_DQSMEM_85D

MEM_B_DQS_N<5>

MEM_DQSMEM_85D

MEM_B_DQS7

MEM_B_DQS_P<7>

MEM_DQSMEM_85D

MEM_B_DQS_N<6>

MEM_DQSMEM_85D

MEM_B_DQS_N<7>

MEM_CLK_N<2..0>

MEM_CLKMEM_70D

MEM_A_CNTL

MEM_CS_L<1..0>

MEM_45S

MEM_CTRL

MEM_A_CNTL

MEM_ODT<1..0>

MEM_CTRL

MEM_45S

MEM_55S

MEM_A_CMD

MEM_A_A<14..0>

MEM_CMD

MEM_55S

MEM_A_CMD

MEM_A_BS<2..0>

MEM_CMD

MEM_A_CMD

MEM_A_RAS_L

MEM_55S MEM_CMD

MEM_55S

MEM_DATA

MEM_A_DQ_BYTE3

MEM_A_DQ<31..24>
MEM_A_DQ<39..32>

MEM_55S

MEM_DATA

MEM_A_DQ_BYTE4

MEM_A_DQ<47..40>

MEM_55S

MEM_DATA

MEM_A_DQ_BYTE5

MEM_A_DM<7>

MEM_A_DM7

MEM_55S

MEM_DATA

MEM_A_DM<5>

MEM_55S

MEM_DATA

MEM_A_DM5

MEM_CLK_P<2..0>

MEM_A_CLK

MEM_70D MEM_CLK

MEM_A_DQS_N<7>

MEM_85D MEM_DQS

MEM_70D MEM_CLK

MEM_B_CLK

MEM_CLK_P<5..3>

MEM_A_DQS7

MEM_A_DQS_P<7>

MEM_DQSMEM_85D

MEM_A_DQS_N<6>

MEM_DQSMEM_85D

MEM_CMDMEM_55S

MEM_B_CAS_L

MEM_B_CMD

MEM_CMDMEM_55S

MEM_B_RAS_L

MEM_B_CMD

MEM_CMDMEM_55S

MEM_B_CMD

MEM_B_BS<2..0>

MEM_CTRL

MEM_45S

MEM_ODT<3..2>

MEM_B_CNTL

33

33

33

33

33

33

33

32

33

33

33

31

33

33

33

33

33

33

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

32

32

32

17

32

32

32

32

32

32

32

32

32

32

32

32

32

32

32

32

32

32

32

32

32

32

32

32

32

32

32

32

32

32

32

32

32

31

31

31

17

31

31

31

31

31

31

31

31

31

32

31

31

32

32

32

32

16

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

16

16

16

16

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

16

16

16

16

17

17

17

17

17

17

17

16

17

16

17

17

17

17

17

16

Preliminary

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

SOURCE: Santa Platform DG, Rev 1.0 (#21112), Section 10.17

SOURCE: Napa Platform DG, Rev 0.9 (#17978), Section 10.9.1

Internal Interface Constraints

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 10.13.2

PHYSICAL

SPACING

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

DG says minimum spacing 50 mils to clocks

USB 2.0 Interface Constraints

Disk Interface Constraints

HD Audio Interface Constraints

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.7 & 10.9

=55_OHM_SE

HDA_55S

=55_OHM_SE

*

=55_OHM_SE =55_OHM_SE

=STANDARD =STANDARD

=55_OHM_SE =55_OHM_SE

SMB_55S

*

=55_OHM_SE=55_OHM_SE

=STANDARD =STANDARD

=55_OHM_SE

SATA_55S

=55_OHM_SE

=STANDARD

=55_OHM_SE =55_OHM_SE

=STANDARD*

=55_OHM_SE =55_OHM_SE=55_OHM_SE =55_OHM_SE

SPI_55S

* =STANDARD =STANDARD

=55_OHM_SE =55_OHM_SE

*

IDE_55S

=STANDARD=STANDARD

=55_OHM_SE=55_OHM_SE

SB Constraints (1 of 2)

051-7261

16

109103

SYNC_DATE=01/25/2007

SYNC_MASTER=T9_NOME

USB_2CLK

25 MIL

*

?

SATA

*

20 MIL

?

=90_OHM_DIFF =90_OHM_DIFF=90_OHM_DIFF

=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF

*

USB_90D

=55_OHM_SE

USB_60S

=55_OHM_SE=55_OHM_SE=55_OHM_SE

=STANDARD=STANDARD*

=3:1_SPACING

SMB

*

?

*

SPI

=1.8:1_SPACING

?

*

?

USB 20 MIL

HDA

=1.8:1_SPACING

?

*

=1.8:1_SPACING

?

IDE

*

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

*

=100_OHM_DIFF

=100_OHM_DIFF

SATA_100D

=100_OHM_DIFF

USB_EXTA_MUXED_P

USB

USB_90D

USB_EXTA_MUXED_N

USB

USB_90D

USB_90D

USB

USB_EXTA_P

USB_EXTA

USB_90D

USB

USB_EXTA_N

SPI_55S

SPI

SPI_CE_L<1>

SPI_CE_R_L<1>

SPI_CE_L1

SPI

SPI_55S

SPI_55S

SPI

SPI_CE_L<0>

SPI_55S

SPI

SPI_CE_L0

SPI_CE_R_L<0>

SPI_B_SO_R

SPI_55S

SPI

SPI_B_SO

SPI_55S

SPI

SPI_A_SO_R

SPI

SPI_55S

SPI

SPI_55S

SPI_SO

SPI_SO

SPI

SPI_55S

SPI_B_SI_R

SPI_55S

SPI

SPI_A_SI_R

SPI

SPI_55S

SPI_SI

SPI

SPI_55S

SPI_SI

SPI_SI_R

SPI_55S

SPI

SPI_B_SCLK_R

SPI

SPI_55S

SPI_A_SCLK_R

SPI_55S

SPI

SPI_SCLK

SMB_55S

SMB

SMB_ME_DATA

SMB_SB_ME_SDA

SPI_SCLK

SPI_55S

SPI

SPI_SCLK_R

SMB

SMB_55S

SMB_ME_CLK

SMB_SB_ME_SCL

SMB_SB_SDA

SMB

SMB_55S

SMB_DATA

SMB_55S

SMB

SMB_SB_SCL

SMB_CLK

USB_RBIAS

USB_RBIAS

USB_60S

USB_90D

USB_EXTC_N

USB

USB_EXTC_P

USB_EXTC

USB

USB_90D

USB_EXCARD_N

USB

USB_90D

USB_EXCARD_P

USB_EXCARD

USB

USB_90D

USB_EXTB_N

USB

USB_90D

USB_EXTB_P

USB_EXTB

USB

USB_90D

USB_IR_N

USB_90D

USB

USB_IR_P

USB_IR

USB_90D

USB

USB_TPAD_N

USB_90D

USB

USB_TPAD_P

USB_TPAD

USB_90D

USB

USB_BT_N

USB_90D

USB

USB_BT_P

USB_BT

USB_90D

USB

USB_CAMERA_N

USB_90D

USB

USB_CAMERA_P

USB_CAMERA

USB_90D

USB

USB_EXTD_N

USB_90D

USB

USB_EXTD_P

USB_90D

USB

USB_EXTD

USB_MINI_N

USB

USB_90D

USB_MINI_P

USB_MINI

USB_90D

USB

HDA_55S

HDA_RST_L

HDA

HDA_RST_L

HDA_55S

HDA

HDA_RST_L_R

HDA_SDIN0

HDA

HDA_55S

HDA_SDIN0

HDA

HDA_SDIN_CODEC

HDA_55S

SATA_RBIAS

SATA_55S

SATA_RBIAS

SATA_100D

SATA

SATA_C_D2R_C_P

SATA

SATA_C_D2R_P

SATA_100D

SATA_C_D2R

SATA_C_R2D_C_N

SATA

SATA_100D

IDE_CNTL

IDE_55S

IDE

IDE_PDDACK_L

IDE_55S

IDE

IDE_PDIOR_L

IDE_PDIOR_L

HDA_BIT_CLK_R

HDA_55S

HDA

SATA_B_R2D_N

SATA_100D

SATA

SATA_B_D2R_P

SATA

SATA_100D

SATA_B_D2R

SATA_A_R2D_C_N

SATA

SATA_100D

SATA_A_R2D_C_P

SATA_A_R2D

SATA_100D

SATA

SATA

SATA_B_R2D_P

SATA_100D

SATA_100D

SATA_B_D2R_N

SATA

IDE_PDIORDY

IDE_PDIORDY

IDE_55S

IDE

SATA

SATA_A_D2R_C_P

SATA_100D

SATA

SATA_A_D2R_C_N

SATA_100D

ODD_RST_5VTOL_L

IDE_RST_L

IDE_55S

IDE

SATA_A_D2R_N

SATA

SATA_100D

IDE_PDD<15..0>

IDE_55S

IDE

IDE_PDD

SATA_B_R2D_C_N

SATA

SATA_100D

SATA_A_R2D_N

SATA

SATA_100D

SATA_A_R2D_P

SATA_100D

SATA

IDE_PDA<2..0>

IDE_55SIDE_PDA

IDE

SATA_A_D2R

SATA_A_D2R_P

SATA_100D

SATA

IDE_IRQ14

IDE_IRQ14

IDE_55S

IDE

IDE_PDDREQ

IDE_CNTL

IDE

IDE_55S

IDE_PDCS3_L

IDE_55S

IDE

IDE_PDCS

IDE_PDCS1_L

IDE_55S

IDE

IDE_PDCS

IDE_PDIOW_L

IDE

IDE_55S

IDE_CNTL

SATA

SATA_B_R2D_C_P

SATA_B_R2D

SATA_100D

HDA_SYNC

HDA_55S

HDA

HDA_SYNC

HDA_55S

HDA

HDA_SYNC_R

HDA_SDOUT_R

HDA_55S

HDA

HDA_SDOUT

HDA_SDOUT

HDA

HDA_55S

HDA_BIT_CLK

HDA_55S

HDA

HDA_BIT_CLK

SATA

SATA_C_R2D_P

SATA_100D

SATA_C_R2D_C_P

SATA_C_R2D

SATA

SATA_100D

SATA

SATA_100D

SATA_B_D2R_C_N

SATA_100D

SATA_B_D2R_C_P

SATA

SATA_100D

SATA

SATA_C_D2R_C_N

SATA_C_D2R_N

SATA_100D

SATA

SATA

SATA_C_R2D_N

SATA_100D

80

80

43

43

56

56

56

48

56

48

48

48

34

34

34

34

34

34

24

24

80

80

80

80

44

44

44

44

34

34

34

34

42

42

42

42

42

80

80

42

42

42

80

42

42

42

80

42

42

42

42

42

42

34

34

34

42

42

24

24

56

24

56

24

56

24

56

25

24

25

25

25

24

24

24

24

24

24

24

7

7

24

24

24

24

24

24

24

24

24

24

23

23

23

42

23

23

23

23

23

23

23

23

23

23

24

23

23

23

80

80

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

Preliminary

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

SPACING

PHYSICAL

SOURCE: Based on Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.27.1.5-7, 10.29 & 10.30

Ethernet (Yukon) Constraints

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.27.1.5-7, 10.29 & 10.30

Controller Link (AMT) Constraints

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.18.1 & 10.19

PCI Bus Constraints

SYNC_MASTER=T9_NOME

SYNC_DATE=01/25/2007

SB Constraints (2 of 2)

104 109

16

051-7261

=55_OHM_SE =55_OHM_SE

=STANDARD

PCI_55S

*

=55_OHM_SE

=STANDARD

=55_OHM_SE

CLINK_12MIL

300 MILS

5 MILS

12 MILS

=STANDARD* =STANDARD

=STANDARD

25 MILS

ENET_MDI

*

?

=100_OHM_DIFF

*

ENET_100D

=100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF

=100_OHM_DIFF

=1.8:1_SPACING

*

CLINK

?

=55_OHM_SE

CLINK_55S

=STANDARD

=55_OHM_SE

*

=55_OHM_SE=55_OHM_SE

=STANDARD

12 MILS

CLINK_VREF

*

?

*

=2:1_SPACING

PCI

?

PCIE

PCIE_100D

PCIE_FW_D2R_N

PCIE_MINI_R2D_C_N

PCIE_100D

PCIE

PCIE_A_D2R_P

PCIE

PCIE_100D

PCIE_A_D2R

PCIE

PCIE_100D

PCIE_A_R2D

PCIE_A_R2D_C_P

PCI

PCI_55S

INT_PIRQB_L

INT_PIRQB_L

INT_PIRQA_L

PCI

PCI_55S

INT_PIRQA_L

PCI_TRDY_L

PCI

PCI_55S

PCI_CNTL

SB_CLINK_VREF0

CLINK_12MIL

CLINK_VREF

SB_CLINK_VREF0

SB_CLINK_VREF1

CLINK_12MIL

CLINK_VREF

SB_CLINK_VREF1

PCIE_ENET_R2D_C_P

PCIE

PCIE_100D

PCIE_ENET_R2D

GLAN_COMP

GLAN_COMP

CLINK_NB_RESET_L

CLINK

CLINK_55S

CLINK_NB_RESET_L

CLINK_WLAN_CLK

CLINK_55S

CLINK

CLINK_WLAN

CLINK_55S

CLINK

CLINK_WLAN

CLINK_WLAN_DATA

CLINK_VREF

CLINK_12MIL

NB_CLINK_VREF

NB_CLINK_VREF

CLINK

CLINK_WLAN_RESET_L

CLINK_WLAN_RESET_L

CLINK_55S

CLINK_NB_DATA

CLINK_55S

CLINK

CLINK_NB

CLINK_55S

CLINK_NB_CLK

CLINK

CLINK_NB

ENET_MDI

ENET_MDI_P<3>

ENET_MDI

ENET_100D

ENET_MDI_N<3>

ENET_MDI

ENET_100D

ENET_MDI

ENET_MDI_P<2>

ENET_100D

ENET_MDI

ENET_100D

ENET_MDI_N<1>

ENET_MDI

ENET_MDI_N<2>

ENET_MDI

ENET_100D

ENET_MDI

ENET_100D

ENET_MDI_N<0>

ENET_MDI ENET_MDI

ENET_MDI_P<1>

ENET_100D

PCIE

PCIE_100D

PCIE_ENET_D2R_C_N

ENET_MDI

ENET_100D

ENET_MDI

ENET_MDI_P<0>

PCIE_ENET_D2R_C_P

PCIE

PCIE_100D

PCIE_ENET_D2R_P

PCIE_ENET_D2R

PCIE

PCIE_100D

PCIE_ENET_D2R_N

PCIE

PCIE_100D

PCIE_ENET_R2D_P

PCIE

PCIE_100D

PCIE_ENET_R2D_C_N

PCIE_100D

PCIE

PCIE_ENET_R2D_N

PCIE

PCIE_100D

PCIE

PCIE_100D

PCIE_FW_D2R_P

PCIE_FW_D2R

PCIE_100D

PCIE

PCIE_MINI_R2D_C_P

PCIE_MINI_R2D

PCIE

PCIE_100D

PCIE_MINI_D2R_P

PCIE_MINI_D2R

PCIE

PCIE_100D

PCIE_MINI_D2R_N

PCIE_100D

PCIE

PCIE_FW_R2D_C_N

PCIE_B_D2R_N

PCIE

PCIE_100D

PCIE_B_D2R_P

PCIE

PCIE_100D

PCIE_B_D2R

PCIE_100D

PCIE_B_R2D_C_N

PCIE

PCI_REQ2_L

PCI

PCI_55S

PCI_REQ2_L

PCI_GNT2_L

PCI

PCI_55S

PCI_GNT2_L

PCI_FW_REQ_L

PCI_FW_REQ_L

PCI

PCI_55S

PCI_SERR_L

PCI_55S

PCI

PCI_CNTL

PCI_PERR_L

PCI

PCI_55S

PCI_CNTL

PCI_DEVSEL_L

PCI

PCI_55S

PCI_CNTL

PCI

PCI_55S

PCI_CNTL

PCI_IRDY_L

PCI_LOCK_L

PCI

PCI_55S

PCI_LOCK_L

PCIE

PCIE_100D

PCIE_A_R2D_C_N

PCI

INT_PIRQF_L

PCI_55S

INT_PIRQF_L

PCI

INT_PIRQE_L

PCI_55S

INT_PIRQE_L

PCI_GNT1_L

PCI

PCI_55S

PCI_GNT1_L

PCI_REQ1_L

PCI

PCI_55S

PCI_REQ1_L

PCI_FW_GNT_L

PCI_FW_GNT_L

PCI

PCI_55S

PCI_C_BE_L<3..0>

PCI

PCI_55S

PCI_C_BE_L

PCI_AD<31..21>

PCI

PCI_55S

PCI_AD

PCI_PAR

PCI

PCI_55S

PCI_AD

PCI_AD<20>

PCI

PCI_55S

PCI_AD20

PCI_AD<19>

PCI

PCI_55S

PCI_AD19

PCI_AD<18..0>

PCI_55S

PCI

PCI_AD

PCI_STOP_L

PCI

PCI_55S

PCI_CNTL

PCI_FRAME_L

PCI

PCI_55S

PCI_CNTL

PCIE

PCIE_100D

PCIE_EXCARD_R2D_C_N

PCIE_A_D2R_N

PCIE

PCIE_100D

PCIE

PCIE_100D

PCIE_EXCARD_R2D_C_P

PCIE_EXCARD_R2D

PCIE_B_R2D

PCIE_100D

PCIE_B_R2D_C_P

PCIE

PCI

PCI_55S

INT_PIRQD_L

INT_PIRQD_L

PCI

PCI_55S

INT_PIRQC_L

INT_PIRQC_L

PCIE

PCIE_100D

PCIE_EXCARD_D2R_P

PCIE_EXCARD_D2R

PCIE_100D

PCIE

PCIE_FW_R2D_C_P

PCIE_FW_R2D

PCIE

PCIE_100D

PCIE_EXCARD_D2R_N

34

38

35

25

25

25

37

37

37

37

37

37

37

37

35

35

35

34

34

34

38

38

38

38

38

38

38

38

38

38

38

38

38

38

38

24

24

24

24

25

25

24

23

16

16

16

16

35

35

35

35

35

35

35

35

35

35

24

24

35

24

35

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

34

34

24

24

34

34

Preliminary

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

(CK505_SRC5)

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

NET_TYPE

SMC SMBus Net Properties

SPACING

(CK505_SRC4)
(CK505_SRC4)
(CK505_SRC5)

(CK505_SRC8)
(CK505_SRC8)

(CK505_SRC3)

(CK505_SRC3)

(CK505_SRC2)

(CPU_BSEL0)

Clock Net Properties

ELECTRICAL_CONSTRAINT_SET

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 14.1 - 14.6

SPACING

NET_TYPE

(CPU_BSEL2)

(CPU_BSEL0)

PHYSICAL

CK505 PCI5 is project-specific

CK505 PCI4 is project-specific

CK505 SRC7 is project-specific

(CK505_NB)

(CK505_PCIF1)

(CK505_PCIF0)

(CK505_ITP)

(CK505_SRC1)
(CK505_SRC1)

(CPU_BSEL2)

(CK505_LVDS)
(CK505_LVDS)

(CK505_SRC6)

(CK505_SRC6)

(CK505_SRC2)

(CK505_PCI3)

(CPU_BSEL2)

(CPU_BSEL0)

(CK505_DOT96)

(CK505_DOT96)

(CK505_PCI1)
(CK505_PCI2)

(CK505_ITP)

(CK505_NB)

(CK505_CPU)
(CK505_CPU)

Clock Signal Constraints

=100_OHM_DIFF

*

=100_OHM_DIFF=100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFFCLK_PCIE_100D

=100_OHM_DIFF

CLK_SLOW

?

*

10 MIL

=55_OHM_SE

=STANDARD=STANDARD

=55_OHM_SE

*

=55_OHM_SE

CLK_SLOW_55S

=55_OHM_SE

*

?

CLK_PCIE

20 MIL

?

CLK_FSB

*

25 MIL

* =STANDARD

CLK_MED_55S

=55_OHM_SE =55_OHM_SE

=STANDARD

=55_OHM_SE=55_OHM_SE

?

CLK_MED

*

20 MIL

CLK_FSB_100D

*

=100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

SYNC_DATE=01/25/2007

SYNC_MASTER=T9_NOME

105 109

16

051-7261

Clock & SMC Constraints

CK505_SRC8_P

CLK_PCIE

CK505_SRC8

CLK_PCIE_100D
CLK_PCIE_100D

CK505_SRC8_N

CLK_PCIE

CK505_SRC6_P

CLK_PCIE_100D

CK505_SRC6

CLK_PCIE

CK505_SRC4_N

CLK_PCIE

CLK_PCIE_100D

CK505_SRC4_P

CLK_PCIE

CLK_PCIE_100D

CK505_SRC4

CLK_PCIE_100D

CK505_SRC5_N

CLK_PCIE

CK505_SRC6_N

CLK_PCIE_100D

CLK_PCIE

CK505_SRC7_N

CLK_PCIE

CLK_PCIE_100D

FSB_CLK_CPU_N

CLK_FSB

CLK_FSB_100D

FSB_CLK_NB_P

CLK_FSB

CLK_FSB_100D

FSB_CLK_NB_N

CLK_FSB

CLK_FSB_100D
CLK_FSB_100D

CLK_FSB

XDP_CLK_P

PCI_CLK33M_TPM

CLK_MED

CLK_MED_55S

CK505_FSC

CLK_MED_55S

CLK_MED

CLK_PCIE_100D

CLK_PCIE

SB_CLK100M_DMI_N

NB_CLK96M_DOT_P

CLK_PCIE

CLK_PCIE_100D

NB_CLK96M_DOT_N

CLK_PCIE

CLK_PCIE_100D

CLK_PCIE_100D

PEG_CLK100M_P

CLK_PCIE

CLK_PCIE

CLK_PCIE_100D

PCIE_CLK100M_EXCARD_P

SB_CLK100M_DMI_P

CLK_PCIE

CLK_PCIE_100D

PEG_CLK100M_N

CLK_PCIE

CLK_PCIE_100D

CLK_PCIE_100D

CLK_PCIE

NB_CLK100M_DPLLSS_N

CLK_MED

SB_CLK48M_USBCTLR

CLK_MED_55S

PCI_CLK33M_SMC

CLK_MED

CLK_MED_55S

PCI_CLK33M_FW

CLK_MED

CLK_MED_55S

PCI_CLK33M_LPCPLUS

CLK_MED

CLK_MED_55S

PCI_CLK33M_SB

CLK_MED

CLK_MED_55S

CK505_SRC3_N

CLK_PCIE

CLK_PCIE_100D

CK505_SRC5_P

CLK_PCIE_100D

CK505_SRC5

CLK_PCIE

CK505_LVDS_P

CLK_PCIE

CLK_PCIE_100D

CK505_LVDS

CK505_SRC1_P

CLK_PCIE

CLK_PCIE_100D

CK505_SRC1

CK505_PCIF0_CLK_ITPEN

CLK_MED

CK505_PCIF0 CLK_MED_55S

CK505_PCI2

CLK_MED

CLK_MED_55S

CK505_PCI2_CLK

CLK_MED

CLK_MED_55S

CK505_PCI3

CK505_PCI3_CLK

CLK_MED

CLK_MED_55S

CK505_PCI4

CK505_PCI4_CLK
CK505_PCI5_CLK_FCTSEL

CLK_MED

CK505_PCI5

CLK_MED_55S

CLK_PCIE

CLK_PCIE_100D

CK505_SRC1_N

CK505_LVDS_N

CLK_PCIE

CLK_PCIE_100D

CLK_PCIE_100D

CLK_PCIE

CK505_DOT96_27M_N

CK505_48M_FSA

CLK_MED

CLK_MED_55S

CLK_FSB_100D

CK505_CPU1_N

CLK_FSB

CK505_NB
CK505_ITP

CLK_FSB_100D

CLK_FSB

CK505_CPU2_ITP_SRC10_P

CLK_FSB_100D

CK505_ITP

CK505_CPU2_ITP_SRC10_N

CLK_FSB

CLK_FSB_100D

CK505_CPU0_N

CLK_FSB

CK505_CPU
CK505_NB CLK_FSB_100D

CK505_CPU1_P

CLK_FSB

CK505_REF0_FSC

CLK_MED

CLK_MED_55S

CK505_DOT96_27M_P

CLK_PCIE

CLK_PCIE_100D

CK505_DOT96

CK505_SRC2_N

CLK_PCIE

CLK_PCIE_100D

CK505_SRC2_P

CLK_PCIE

CLK_PCIE_100D

CK505_SRC2

CK505_SRC3_P

CK505_SRC3

CLK_PCIE

CLK_PCIE_100D

CLK_FSB

XDP_CLK_N

CLK_FSB_100D

CK505_PCI1

CLK_MED

CLK_MED_55S

CK505_PCI1_CLK

CLK_MED

CLK_MED_55S

CK505_PCIF1_CLK

CK505_PCIF1

CLK_FSB_100D

CLK_FSB

CK505_CPU0_P

CK505_CPU

CK505_SRC7_P

CLK_PCIE_100D

CLK_PCIE

CK505_SRC7

FSB_CLK_CPU_P

CLK_FSB

CLK_FSB_100D

CK505_FSA

CLK_MED_55S

CLK_MED

NB_CLK100M_DPLLSS_P

CLK_PCIE

CLK_PCIE_100D

CLK_MED_55S

CLK_MED

SB_CLK14P3M_TIMER

CLK_PCIE

PCIE_CLK100M_EXCARD_N

CLK_PCIE_100D

PCIE_CLK100M_ENET_N

CLK_PCIE

CLK_PCIE_100D

PCIE_CLK100M_ENET_P

CLK_PCIE

CLK_PCIE_100D

PCIE_CLK100M_MINI_P

CLK_PCIE

CLK_PCIE_100D

NB_CLK100M_PCIE_P

CLK_PCIE

CLK_PCIE_100D

SB_CLK100M_SATA_N

CLK_PCIE

CLK_PCIE_100D

SB_CLK100M_SATA_P

CLK_PCIE

CLK_PCIE_100D

SMB_55S

SMB

SMBUS_SMC_A_S3_SDA

SMBUS_SMC_A_S3_SDA

SMB_55S

SMB

SMBUS_SMC_A_S3_SCL

SMBUS_SMC_A_S3_SCL

SMB

SMB_55S

SMBUS_SMC_B_S0_SCL

SMBUS_SMC_B_S0_SCL

SMB

SMB_55S

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_0_S0_SCL

SMB_55S

SMB

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_0_S0_SDA

SMB

SMB_55S

SMBUS_SMC_BSA_SCL

SMBUS_SMC_BSA_SCL

SMB_55S

SMB

SMBUS_SMC_MGMT_SCL

SMBUS_SMC_MGMT_SCL

SMB_55S

SMB

SMBUS_SMC_B_S0_SDA

SMBUS_SMC_B_S0_SDA

SMB_55S

SMB

SMBUS_SMC_BSA_SDA

SMBUS_SMC_BSA_SDA

SMB

SMB_55S

SMBUS_SMC_MGMT_SDA

SMBUS_SMC_MGMT_SDA

CLK_PCIE

CLK_PCIE_100D

PCIE_CLK100M_MINI_N

NB_CLK100M_PCIE_N

CLK_PCIE

CLK_PCIE_100D

30

30

30

83

30

47

83

30

30

30

30

30

30

30

30

30

30

30

30

10

14

14

30

30

34

30

22

30

45

38

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

10

22

30

34

35

35

34

16

30

30

34

16

29

29

29

29

29

29

29

29

7

7

7

13

30

24

7

7

9

30

24

9

7

25

30

30

7

24

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

13

29

29

29

29

7

30

7

25

30

30

30

30

7

23

23

48

48

48

48

48

48

48

48

48

48

30

7

Preliminary

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

Port 2 Not Used

SPACING

FireWire Net Properties

PHYSICAL

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

FireWire Interface Constraints

?

*FW

=2:1_SPACING

*

=3:1_SPACING

?

FW_TP

=110_OHM_DIFF

*

=110_OHM_DIFF

=110_OHM_DIFF =110_OHM_DIFF

FW_110D

=110_OHM_DIFF =110_OHM_DIFF

=55_OHM_SE =55_OHM_SE

=STANDARD=STANDARD

=55_OHM_SE=55_OHM_SE

FW_55S

*

FireWire Constraints

051-7261

16

109106

SYNC_MASTER=T9_NOME

SYNC_DATE=01/25/2007

FW_LPS

FW_LPS

FW

FW_55S
FW_55S

FW

FW_LREQ

FW_LREQ

CLK_MED_55S

CLK_MED

FWPHY_CLK98P304M_XI

CLK98P304M_FW_XI_R

FW_D_CTL

FW_55S

FW

FW_LINK<7..0>

CLK_MED_55S

CLK_MED

CLKFW_PHY_PCLK

FW_PCLK CLK_MED

CLK_MED_55S

CLKFW_LINK_PCLK

FW_LCLK CLK_MED

CLK_MED_55S

CLKFW_LINK_LCLK

FW

FW_55S

FW_CTL<1..0>

FW_D_CTL

FW_55S

FW

FW_LKON

FW_LKON

FW_0_TPA_N

FW_110D

FW_TP

FW_0_TPA

FW_1_TPB

FW_TP

FW_110D

FW_1_TPB_N

FW_1_TPB

FW_TP

FW_110D

FW_1_TPB_P

CLK_MED

CLK_MED_55S

CLK98P304M_FW_XI

FW_0_TPB

FW_110D

FW_0_TPB_N

FW_TP

FW_TP

FW_110D

FW_0_TPA

FW_0_TPA_P

FW_PINT

FW_55S

FW

FW_PINT

FW_55S

FW

FW_LKON_R

FW_0_TPB

FW_110D

FW_TP

FW_0_TPB_P

CLK_MED

CLK_MED_55S

CLKFW_PHY_LCLK

FW_TP

FW_110D

FW_1_TPA_P

FW_1_TPA

FW_TP

FW_110D

FW_1_TPA_N

FW_1_TPA

39

39

39

41

41

41

41

41

39

41

39

41

41

38

38

38

39

39

39

39

39

38

39

38

39

39

Preliminary

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

G84M Net Properties

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

NET_TYPE NET_TYPE

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

GDDR3 FB C/D Net PropertiesGDDR3 FB A/B Net Properties

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

(CK505_DOT96)

GDDR3 Frame Buffer Signal Constraints

Video Signal Constraints

SPACING

SPACING SPACING

=2.5:1_SPACING

*

?

GDDR3_CLK

=2.5:1_SPACING

*

?

GDDR3_CMD

=2.5:1_SPACING

GDDR3_DATA

*

?

=100_OHM_DIFF =100_OHM_DIFF

TMDS_100D

=100_OHM_DIFF

*

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=50_OHM_SE

=STANDARD

VGA_50S

=50_OHM_SE

=STANDARD*

=50_OHM_SE=50_OHM_SE

=STANDARD

VGA_55S

* =STANDARD

=55_OHM_SE=55_OHM_SE =55_OHM_SE=55_OHM_SE

VGA_SYNC

?

*

20 MIL

=50_OHM_SE=50_OHM_SE

=STANDARD=STANDARD

=50_OHM_SE

*

GDDR3_50SE

=50_OHM_SE

20 MILVGA

*

?

TMDS

?

*

20 MIL

=2.5:1_SPACING

*

GDDR3_DQS

?

=80_OHM_DIFF

*

GDDR3_80D

=80_OHM_DIFF =80_OHM_DIFF

=80_OHM_DIFF =80_OHM_DIFF=80_OHM_DIFF

=STANDARD=STANDARD

12.7 MM

=50_OHM_SE

=50_OHM_SE

*

GDDR3_40R50SE

=40_OHM_SE

SYNC_DATE=01/26/2007

SYNC_MASTER=M75_MLB

GPU (G84M) Constraints

107 109

16

051-7261

TMDS_100D

TMDS

TMDS_CLK_N

TMDS_CLK

TMDS_100D

TMDS

TMDS_CLK_P

TMDS_CLK

LVDS_100D

LVDS

LVDS_U_DATA_P<3..0>

LVDS_100D

LVDS

LVDS_U_CLK_N

LVDS_100D

LVDS_L_DATA_N<3..0>

LVDS

LVDS_L_CLK_N

LVDS_100D

LVDS

CK505_CLK27MSS

GPU_CLK27M_SS

CLK_SLOWCLK_SLOW_55S

GDDR3_CLK

FB_A_CLK_P<0>

FB_A_CLK_P

GDDR3_80D

GDDR3_CLK

FB_A_CLK_N<0>

GDDR3_80D

FB_B_CLK_P

FB_A_CLK_P<1>

GDDR3_CLKGDDR3_80D

FB_AB_CMD GDDR3_CMD

FB_A_BA<2..0>

GDDR3_40R50SE

GDDR3_CMDFB_AB_CMD

FB_A_WE_L

GDDR3_40R50SE

FB_A_LMA<5..2>

GDDR3_CMD

FB_A_CMD

GDDR3_50SE

FB_B_DQ<31..24>

FB_C_DQ_BYTE3

GDDR3_50SE GDDR3_DATA

FB_B_DQ<23..16>

FB_C_DQ_BYTE2

GDDR3_50SE GDDR3_DATA

FB_B_DQ<7..0>

FB_C_DQ_BYTE0

GDDR3_50SE GDDR3_DATA

FB_AB_CMD

FB_A_CS0_L

GDDR3_CMD

GDDR3_40R50SE

GDDR3_CMD

FB_AB_CMD_PD

FB_A_CKE

GDDR3_40R50SE

FB_AB_CMD GDDR3_CMD

FB_A_RAS_L

GDDR3_40R50SE

GDDR3_CLK

FB_A_CLK_N<1>

GDDR3_80D

FB_B_DQM_L<7>

FB_D_DQM3

GDDR3_50SE GDDR3_DATA

FB_B_DQM_L<5>

FB_D_DQM1

GDDR3_50SE GDDR3_DATA

FB_B_DQM_L<6>

FB_D_DQM2

GDDR3_50SE GDDR3_DATA

FB_B_DQM_L<4>

FB_D_DQM0

GDDR3_50SE GDDR3_DATA

FB_B_DQ<63..56>

FB_D_DQ_BYTE3

GDDR3_50SE GDDR3_DATA

FB_B_DQ<55..48>

FB_D_DQ_BYTE2

GDDR3_50SE GDDR3_DATA

FB_B_DQ<39..32>

FB_D_DQ_BYTE0

GDDR3_50SE GDDR3_DATA

FB_B_DQ<47..40>

FB_D_DQ_BYTE1

GDDR3_50SE GDDR3_DATA

FB_D_RDQS2

GDDR3_DQS

FB_B_RDQS<6>

GDDR3_50SE

FB_D_RDQS3

GDDR3_DQS

FB_B_RDQS<7>

GDDR3_50SE

FB_D_RDQS1

FB_B_RDQS<5>

GDDR3_DQS

GDDR3_50SE

FB_D_WDQS2

GDDR3_DQS

FB_B_WDQS<6>

GDDR3_50SE

FB_D_WDQS3

GDDR3_DQS

FB_B_WDQS<7>

GDDR3_50SE

FB_D_WDQS1

GDDR3_DQS

FB_B_WDQS<5>

GDDR3_50SE

FB_D_WDQS0

GDDR3_DQS

FB_B_WDQS<4>

GDDR3_50SE

FB_B_DQM_L<3>

FB_C_DQM3

GDDR3_50SE GDDR3_DATA

FB_C_DQM0

FB_B_DQM_L<0>

GDDR3_50SE GDDR3_DATA

FB_C_RDQS2

GDDR3_DQS

FB_B_RDQS<2>

GDDR3_50SE

FB_C_RDQS3

GDDR3_DQS

FB_B_RDQS<3>

GDDR3_50SE

FB_C_RDQS1

GDDR3_DQS

FB_B_RDQS<1>

GDDR3_50SE

FB_C_WDQS2

GDDR3_DQS

FB_B_WDQS<2>

GDDR3_50SE

FB_C_WDQS3

GDDR3_DQS

FB_B_WDQS<3>

GDDR3_50SE

FB_C_WDQS1

GDDR3_DQS

FB_B_WDQS<1>

GDDR3_50SE

FB_C_WDQS0

GDDR3_DQS

FB_B_WDQS<0>

GDDR3_50SE

FB_CD_CMD_PD

GDDR3_CMD

FB_B_DRAM_RST

GDDR3_40R50SE

FB_CD_CMD_PD

GDDR3_CMD

FB_B_CKE

GDDR3_40R50SE

GDDR3_CMD

FB_B_CS0_L

FB_CD_CMD

GDDR3_40R50SE

GDDR3_CMD

FB_B_CAS_L

FB_CD_CMD

GDDR3_40R50SE

GDDR3_CMD

FB_B_WE_L

FB_CD_CMD

GDDR3_40R50SE

GDDR3_CMD

FB_B_RAS_L

FB_CD_CMD

GDDR3_40R50SE

GDDR3_CMD

FB_B_MA<11..6>

FB_CD_CMD

GDDR3_40R50SE

GDDR3_CMD

FB_B_BA<2..0>

FB_CD_CMD

GDDR3_40R50SE

GDDR3_CMD

FB_B_MA<1..0>

FB_CD_CMD

GDDR3_40R50SE

GDDR3_CLK

FB_B_CLK_N<1>

GDDR3_80D

GDDR3_CLK

FB_B_CLK_P<1>

FB_D_CLK_P

GDDR3_80D

GDDR3_CLK

FB_B_CLK_P<0>

FB_C_CLK_P

GDDR3_80D

GDDR3_CLK

FB_B_CLK_N<0>

GDDR3_80D

GDDR3_CMDFB_AB_CMD

FB_A_MA<11..6>

GDDR3_40R50SE

GDDR3_CMD

FB_A_CAS_L

FB_AB_CMD

GDDR3_40R50SE

FB_A_WDQS1

GDDR3_DQS

FB_A_WDQS<1>

GDDR3_50SE

FB_A_WDQS3

GDDR3_DQS

FB_A_WDQS<3>

GDDR3_50SE

FB_A_WDQS<2>

FB_A_WDQS2

GDDR3_DQS

GDDR3_50SE

FB_A_RDQS1

GDDR3_DQS

FB_A_RDQS<1>

GDDR3_50SE

FB_A_RDQS0

FB_A_RDQS<0>

GDDR3_DQS

GDDR3_50SE

FB_A_RDQS2

GDDR3_DQS

FB_A_RDQS<2>

GDDR3_50SE

FB_A_DQM0

FB_A_DQM_L<0>

GDDR3_50SE GDDR3_DATA

FB_A_DQM2

FB_A_DQM_L<2>

GDDR3_50SE GDDR3_DATA

FB_A_DQM1

FB_A_DQM_L<1>

GDDR3_50SE GDDR3_DATA

GDDR3_DQS

FB_B_WDQS0

FB_A_WDQS<4>

GDDR3_50SE

FB_B_WDQS3

GDDR3_DQS

FB_A_WDQS<7>

GDDR3_50SE

FB_B_RDQS1

GDDR3_DQS

FB_A_RDQS<5>

GDDR3_50SE

FB_B_RDQS0

GDDR3_DQS

FB_A_RDQS<4>

GDDR3_50SE

FB_B_RDQS3

GDDR3_DQS

FB_A_RDQS<7>

GDDR3_50SE

FB_B_RDQS2

GDDR3_DQS

FB_A_RDQS<6>

GDDR3_50SE

FB_B_DQ_BYTE1

FB_A_DQ<47..40>

GDDR3_50SE GDDR3_DATA

FB_B_DQ_BYTE0

FB_A_DQ<39..32>

GDDR3_50SE GDDR3_DATA

FB_A_DQM_L<6>

GDDR3_50SE GDDR3_DATA

FB_B_DQM2

FB_C_RDQS0

GDDR3_DQS

FB_B_RDQS<0>

GDDR3_50SE

FB_B_UMA<5..2>

GDDR3_CMD

FB_D_CMD

GDDR3_50SE

FB_B_LMA<5..2>

GDDR3_CMD

FB_C_CMD

GDDR3_50SE

FB_D_RDQS0

GDDR3_DQS

FB_B_RDQS<4>

GDDR3_50SE

FB_B_DQM_L<2>

FB_C_DQM2

GDDR3_50SE GDDR3_DATA

FB_B_DQM_L<1>

FB_C_DQM1

GDDR3_50SE GDDR3_DATA

FB_B_DQ<15..8>

FB_C_DQ_BYTE1

GDDR3_50SE GDDR3_DATA

FB_A_DQ<31..24>

FB_A_DQ_BYTE3

GDDR3_50SE GDDR3_DATA

FB_A_DQ<23..16>

FB_A_DQ_BYTE2

GDDR3_50SE GDDR3_DATA

FB_A_DQ<15..8>

FB_A_DQ_BYTE1

GDDR3_50SE GDDR3_DATA

FB_A_RDQS<3>

FB_A_RDQS3

GDDR3_DQS

GDDR3_50SE

FB_A_UMA<5..2>

GDDR3_CMD

GDDR3_50SE

FB_B_CMD

FB_A_WDQS0

GDDR3_DQS

FB_A_WDQS<0>

GDDR3_50SE

FB_AB_CMD GDDR3_CMD

FB_A_MA<1..0>

GDDR3_40R50SE

FB_A_DQM3

FB_A_DQM_L<3>

GDDR3_50SE GDDR3_DATA

CLK_SLOW_55S

GPU_CLK27M

CLK_SLOW

FB_B_DQM0

FB_A_DQM_L<4>

GDDR3_50SE GDDR3_DATA

FB_B_DQ_BYTE3

FB_A_DQ<63..56>

GDDR3_50SE GDDR3_DATA

FB_B_WDQS2

GDDR3_DQS

FB_A_WDQS<6>

GDDR3_50SE

GDDR3_CMD

FB_A_DRAM_RST

GDDR3_40R50SE

FB_AB_CMD_PD

FB_A_DQ<7..0>

FB_A_DQ_BYTE0

GDDR3_50SE GDDR3_DATA

FB_B_WDQS1

GDDR3_DQS

FB_A_WDQS<5>

GDDR3_50SE

FB_B_DQ_BYTE2

FB_A_DQ<55..48>

GDDR3_50SE GDDR3_DATA

FB_B_DQM1

FB_A_DQM_L<5>

GDDR3_50SE GDDR3_DATA

LVDS_100D

LVDS

LVDS_U_CLK_P

LVDS_U_DATA_N<3..0>

LVDS_100D

LVDS

GPU_VGA_G

VGA

VGA_50S

VGA

GPU_TV_COMP_VGA_B

VGA_B_TV_COMP

VGA_50S

TMDS_100D

TMDS_DATA_N<5..0>

TMDS

TMDS_DATA

VGA

GPU_TV_C_VGA_R

VGA_50S

VGA_R_TV_C

LVDS_L_DATA_P<3..0>

LVDS_100D

LVDS

TMDS_100D

TMDS

TMDS_DATA_P<5..0>

TMDS_DATA

VGA

GPU_TV_Y_VGA_G

VGA_G_TV_Y

VGA_50S

GPU_VGA_R

VGA

VGA_50S

GPU_VGA_B

VGA

VGA_50S

VGA_50S

GPU_TV_COMP

VGA

VGA_50S

GPU_TV_Y

VGA

VGA

VGA_50S

GPU_TV_C

VGA_SYNC

VGA_55S

GPU_VGA_VSYNC

VGA_SYNC

GPU_VGA_HSYNC

VGA_55S

VGA_SYNCVGA_SYNC

FB_B_DQM3

FB_A_DQM_L<7>

GDDR3_50SE GDDR3_DATA

LVDS_L_CLK_P

LVDS_100D

LVDS

GPU_CLK27M_SS_GATED

CLK_SLOWCLK_SLOW_55S

GPU_CLK27M_GATED

CLK_SLOWCLK_SLOW_55S

79

79

79

79

75

79

78

78

75

79

75

79

71

71

71

71

71

71

72

72

72

71

71

71

71

72

72

72

72

72

72

72

72

72

72

72

72

72

72

72

72

72

72

72

72

72

72

72

72

72

72

72

72

72

72

72

72

72

72

72

72

72

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

72

72

72

72

72

72

72

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

79

75

75

78

78

78

74

78

78

75

75

75

75

75

78

78

71

75

74

74

75

75

74

75

74

75

30

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

70

30

70

70

70

70

70

70

70

70

75

74

74

74

75

74

7

75

74

74

74

74

74

74

75

75

70

7

30

30

Preliminary

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

(VGA_SYNC)

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

SPACING

NET_TYPE

(PCIE_MINI)

(PCIE_MINI)

(PCIE_EXCARD)

(PCIE_EXCARD)

(SATA_A_D2R)

(SATA_A_D2R)

(SATA_A_R2D)

(SATA_A_R2D)

(USB_CAMERA)
(USB_CAMERA)

(USB_EXTD)

(USB_EXTD)

(USB_EXTA)

(USB_EXTA)

(USB_EXTA)

(USB_EXTA)

(VGA_G_TV_C)

(VGA_SYNC)
(VGA_SYNC)

(VGA_SYNC)

M76 Specific Net Properties

(VGA_B_TV_COMP)

(VGA_R_TV_Y)

Memory Constraint Relaxations

Allow 0.127 mm necks for >0.127 mm lines for GMCH fanout.

SIM Card Constraints

Alternate diffpair width/gap through BGA fanout areas (95-ohm diff)

Graphics Constraint Relaxations

Allow 0.1 mm necks for >0.1 mm lines between thru-hole SO-DIMM pins.

I118

I119

*

GND

=STANDARD

?

0.20 MM

*

1000

PWR_P2MM

MEM_CTRL GND_P2MM

GND

*

GND_P2MM

MEM_DQS

*

GND

*

GND

CPU_VCCSENSE

GND_P2MM

CLK_MED

FW_POWER

*

GND_P2MM

*

2.54 MM

0.100 MM

MEM_45S

MEM_70D

0.100 MM

ISL10

2.54 MM

=50_OHM_SE

=50_OHM_SE

*

WWAN_SIM

=50_OHM_SE =50_OHM_SE =50_OHM_SE

=50_OHM_SE

=2:1_SPACING

WWAN_SIM

*

?

100_DIFF_BGA

TMDS_100D

*

100_DIFF_BGA

LVDS_100D

*

100_DIFF_BGA

PCIE_100D

*

MEM_85D 2.54 MM

0.100 MM

ISL4,ISL10

0.127 MM

6.35 MM

BOTTOM

MEM_70D

USB

*

PWR_P2MMSB_POWER

*

GND

LVDS

GND_P2MM

PWR_P2MM

*

SB_POWER

SATA

*

SB_POWERCLK_PCIE PWR_P2MM
SB_POWER

DMI

*

PWR_P2MM

GNDUSB

*

GND_P2MM

GND_P2MM

GND

*

SATA

PCIE

GND

*

GND_P2MM

GND

*

DMI

GND_P2MM

CLK_PCIE

GND

*

GND_P2MM

GND_P2MM

*

GND

CLINK_VREF

GND_P2MM

CLK_MED

*

GND

PP1V8_MEM

MEM_DATA

*

PWR_P2MM
PWR_P2MM

PP1V8_MEM

MEM_DQS

*

MEM_CTRL

PP1V8_MEM

*

PWR_P2MM

*

MEM_CMD

PWR_P2MM

PP1V8_MEM

PP1V8_MEM

*

MEM_CLK

PWR_P2MM

GND_P2MMMEM_DATA

GND

*

*

GND

GND_P2MM

MEM_CMD

GND_P2MM

GND

*

MEM_CLK

*

1000

0.20 MM

GND_P2MM

?

*

=STANDARDPP1V8_MEM

PWR_P2MM

ENET_POWER

*

ENET_MDI

GND

*

GND_P2MMENET_MDI

GND_P2MM

GND

*

CPU_GTLREF

GND_P2MM

*

GND

CLK_FSB

=2:1_SPACING

*

?

THERM

?

SENSE

=2:1_SPACING

*

ENETCONN

25 MILS

?

*

GND_P2MM

*

GND

FSB_DSTB

GND_P2MM

*

GND

CPU_COMP

=55_OHM_SE =55_OHM_SE

*

=55_OHM_SE

=1:1_DIFFPAIR =1:1_DIFFPAIR

THERM_1TO1_55S

=1:1_DIFFPAIR

=1:1_DIFFPAIR

=55_OHM_SE

=1:1_DIFFPAIR=1:1_DIFFPAIR

=55_OHM_SE

*

=55_OHM_SE

SENSE_1TO1_55S

M76 Specific Constraints

SYNC_DATE=02/02/2007

SYNC_MASTER=M76_MLB

108 109

16

051-7261

GND

GND

FW_POWER

ENET_POWER

WWAN_SIM_DATA

WWAN_SIMWWAN_SIM

VGA_SYNC

VGA_55S

VGA_HSYNC

VGA_R

VGA

VGA_50S

TMDS_100D

TMDS

TMDS_DATA_F_P<5..0>

TMDS_100D

TMDS

TMDS_DATA_F_N<5..0>

TMDS_CLK_F_N

TMDS

TMDS_100D

TMDS_CLK_F_P

TMDS_100D

TMDS

TMDS_CLK_R_N

TMDS_100D

TMDS

TMDS_CLK_R_P

TMDS

TMDS_100D

LVDS_U_DATA_CONN_N<3..0>

LVDS_100D

LVDS

LVDS_100D

LVDS_U_CLK_CONN_N

LVDS
LVDS

LVDS_U_DATA_CONN_P<3..0>

LVDS_100D

LVDS_100D

LVDS

LVDS_U_CLK_CONN_P

LVDS_L_DATA_CONN_P<3..0>

LVDS_100D

LVDS

LVDS_100D

LVDS_L_DATA_CONN_N<3..0>

LVDS

LVDS

LVDS_100D

LVDS_L_CLK_CONN_P

LVDS

LVDS_100D

LVDS_L_CLK_CONN_N

LVDS_100D

LVDS

LVDS_L_CLK_CONN_F_N

LVDS_100D

LVDS

LVDS_L_CLK_CONN_F_P

THERM

THERM_DIFFPAIR

RSFSTHMSNS_D_P

THERM_1TO1_55S

THERM

THERM_DIFFPAIR

HSTHMSNS_D_P

THERM_1TO1_55S

THERM_DIFFPAIR

THERM

REMTHMSNS_DX_P

THERM_1TO1_55S

THERM

THERM_DIFFPAIR

GPUTHMSNS_D_P

THERM_1TO1_55S

THERM

THERM_DIFFPAIR

GPU_TDIODE_P

THERM_1TO1_55S

THERM

THERM_DIFFPAIR

CPU_THERMD_P

THERM_1TO1_55S

THERM_DIFFPAIR

THERM

CPUTHMSNS_D2_P

THERM_1TO1_55S

SENSE_DIFFPAIR

SENSE

P1V25ISNS_P

SENSE_1TO1_55S

SENSE

SENSE_DIFFPAIR

P1V8ISNS_P

SENSE_1TO1_55S

SENSE_DIFFPAIR

SENSE

NBCOREISNS_P

SENSE_1TO1_55S

USB_90D

USB

USB_CAMERA_F_N

SENSE

SENSE_DIFFPAIR

GFXIMVP6_VSEN_P

SENSE_1TO1_55S

USB_CAMERA_F_P

USB_90D

USB

USB_WWAN_F_N

USB

USB_90D

USB_WWAN_F_P

USB

USB_90D

USB2_RT_N

USB_90D

USB

USB2_RT_P

USB_90D

USB

USB2_EXTA_MUXED_N

USB_90D

USB

USB2_EXTA_MUXED_P

USB

USB_90D

SATA_A_D2R_UF_N

SATA_100D

SATA

SATA_A_D2R_UF_P

SATA_100D

SATA

SATA_A_R2D_UF_N

SATA_100D

SATA

SATA_A_R2D_UF_P

SATA_100D

SATA

FW_PORT0_TPB_FL_N

FW_TP

FW_110D

FW_PORT0_TPB_FL_P

FW_TP

FW_110D

FW_PORT0_TPA_FL_N

FW_TP

FW_110D

ENETCONN_N<3..0>

ENETCONN

ENET_100D

FW_TP

FW_PORT0_TPA_FL_P

FW_110D

ENET_MDI_R_N<3..0>

ENET_100D

ENET_MDI

ENETCONN_P<3..0>

ENET_100D

ENETCONN

ENET_MDI_R_P<3..0>

ENET_100D

ENET_MDI

PCIE

PCIE_MINI_R2D_P

PCIE_100D

PCIE_MINI_R2D_N

PCIE_100D

PCIE

PCIE_EXCARD_R2D_N

PCIE

PCIE_100D

PCIE_100D

PCIE_EXCARD_R2D_P

PCIE

WWAN_SIM_CLOCK

WWAN_SIMWWAN_SIM

PP3V3_S0

SB_POWER

PP3V3_S5

SB_POWER

PP1V8_MEM

=PP1V8_S3M_MEM_B

PP1V8_MEM

=PP1V8_S3M_MEM_A

VGA_SYNC

VGA_55S

VGA_VSYNC

VGA_SYNC

VGA_VSYNC_R

VGA_55S

VGA_SYNC

VGA_HSYNC_R

VGA_55S

VGA_B

VGA

VGA_50S

VGA_G

VGA

VGA_50S

SB_POWER

PP1V5_S0

79

79

79

79

79

79

79

79

51

51

74

51

51

44

44

44

44

66

32

31

44

78

78

78

78

78

78

78

78

77

77

77

77

77

77

77

77

77

77

7

7

51

51

10

7

50

50

50

7

60

7

7

7

43

43

43

43

80

80

80

80

41

41

41

37

41

37

34

34

34

34

44

8

8

8

8

78

78

78

78

78

8

Preliminary

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_BOARD_INFO

VERSION

ALLEGRO

(MIL or MM)

BOARD UNITS

BOARD LAYERS

BOARD AREAS

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEMTABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

Default width/spacing is 100-ohm differential, but pairs can neck to 95-ohms without DRC.

NOTE: 100_DIFF_BGA is for select 100-ohm differential pairs with routing difficulties through BGAs.

M75/M76 Board-Specific Spacing & Physical Constraints

0.200 MM

0.080 MM0.080 MM

ISL3,ISL4

100_OHM_DIFF

0.200 MM

Y

0.080 MM

Y

100_OHM_DIFF

0.080 MM

0.200 MM 0.200 MM

ISL9,ISL10

0.330 MM0.330 MM

ISL9,ISL10

Y

0.077 MM 0.077 MM

110_OHM_DIFF

0.220 MM

ISL3,ISL4

0.220 MM

0.102 MM0.102 MM

90_OHM_DIFF

Y

N =STANDARD =STANDARD

=STANDARD

*

=STANDARD=STANDARD

90_OHM_DIFF

0.125 MM

ISL2,ISL11

85_OHM_DIFF

Y

0.125 MM 0.125 MM

0.125 MM

0.125 MM

Y

85_OHM_DIFF

ISL3,ISL4

0.101 MM 0.101 MM

0.125 MM

0.140 MM 0.140 MM

0.125 MM 0.125 MM

80_OHM_DIFF

TOP,BOTTOM

Y

=STANDARD =STANDARD

85_OHM_DIFF

*

=STANDARD

=STANDARD =STANDARDN

0.125 MM0.125 MM

TOP,BOTTOM

85_OHM_DIFF

Y

0.125 MM 0.125 MM

0.101 MM

0.125 MM

Y

85_OHM_DIFF

0.101 MM

0.125 MM

ISL9,ISL10

45_OHM_SE

* Y =STANDARD =STANDARD

=STANDARD

0.105 MM 0.105 MM

0.125 MM

Y

70_OHM_DIFF

0.149 MM

0.125 MM

ISL9,ISL10

0.149 MM

Y

70_OHM_DIFF

0.185 MM 0.185 MM

0.125 MM 0.125 MM

ISL2,ISL11

ISL2,ISL11

100_OHM_DIFF

0.099 MM

Y

0.200 MM 0.200 MM

0.099 MM

ISL9,ISL10

0.220 MM0.220 MM

0.102 MM0.102 MM

90_OHM_DIFF

Y

0.330 MM

0.089 MM0.089 MM

0.330 MM

Y

110_OHM_DIFF

TOP,BOTTOM

0.330 MM

0.089 MM0.089 MM

ISL2,ISL11

110_OHM_DIFF

0.330 MM

Y

*

0.2 MM

?

2:1_SPACING

90_OHM_DIFF

TOP,BOTTOM

0.220 MM0.220 MM

0.130 MM0.130 MM

Y

0.200 MM0.200 MM

0.099 MM0.099 MM

TOP,BOTTOM

100_OHM_DIFF

Y

0.115 MM 0.115 MM

0.125 MM0.125 MM

80_OHM_DIFF

Y

ISL9,ISL10

0.115 MM0.115 MM

0.125 MM 0.125 MM

80_OHM_DIFF

YISL3,ISL4

Y

70_OHM_DIFF

ISL3,ISL4

0.149 MM 0.149 MM

0.125 MM 0.125 MM

=STANDARD

Y*

1:1_DIFFPAIR

=STANDARD =STANDARD

0.1 MM 0.1 MM

0.131 MM0.131 MM

40_OHM_SE =STANDARD

=STANDARD=STANDARDY*

4:1_SPACING

0.4 MM

*

?

=STANDARD

* Y =STANDARD =STANDARD

0.090 MM 0.090 MM

50_OHM_SE

Y

TOP,BOTTOM

45_OHM_SE

0.150 MM 0.150 MM

TOP,BOTTOM

55_OHM_SE

Y

0.100 MM 0.100 MM

0.076 MM

55_OHM_SE

0.250 MM

ISL2,ISL11

Y

=DEFAULT=DEFAULT

12.7 MM

=DEFAULT=DEFAULT

Y*

STANDARD

=55_OHM_SE

DEFAULT

=55_OHM_SE

0 MM0 MM

*

30 MM

Y

=STANDARD

0.076 MM

=STANDARD

0.076 MM

* =STANDARDY

55_OHM_SE

TOP,BOTTOM

Y

50_OHM_SE

0.125 MM 0.125 MM

TOP,BOTTOM

Y

27P4_OHM_SE

0.335 MM 0.335 MM

0.185 MM0.185 MM

40_OHM_SE

TOP,BOTTOM

Y

* Y =STANDARD

27P4_OHM_SE

=STANDARD

=STANDARD

0.240 MM 0.240 MM

=STANDARD

*

70_OHM_DIFF

=STANDARD

=STANDARD=STANDARDN

=STANDARD

TOP,BOTTOM

0.125 MM

Y

70_OHM_DIFF

0.185 MM 0.185 MM

0.125 MM

=STANDARD=STANDARD

80_OHM_DIFF

N

=STANDARD

*

=STANDARD =STANDARD

0.140 MM 0.140 MM

0.125 MM 0.125 MM

80_OHM_DIFF

ISL2,ISL11

Y

90_OHM_DIFF

ISL2,ISL11

Y

0.130 MM 0.130 MM

0.220 MM 0.220 MM

ISL3,ISL4

Y

0.077 MM 0.077 MM

0.330 MM 0.330 MM

110_OHM_DIFF

N =STANDARD =STANDARD

110_OHM_DIFF

*

=STANDARD=STANDARD =STANDARD

?

DEFAULT

*

0.1 MM

*

?

BGA_P2MM =DEFAULT
BGA_P3MM

?

=DEFAULT

*

*

BGA_P1MM

?

=DEFAULT

?

=DEFAULT

*

STANDARD

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

NO_TYPE,BGA

MM

15.5.1

CLK_SLOW

*

BGA_P2MM

BGA

FSB_DSTB BGA_P3MMFSB_DSTB

BGA

1.8:1_SPACING

*

?

0.18 MM

1.5:1_SPACING

0.15 MM

*

?

0.25 MM

*

?

2.5:1_SPACING

0.3 MM

3:1_SPACING

*

?

BGA_P2MM

*

CLK_PCIE

BGA

**

BGA_P1MM

BGA

MEM_CLK

BGA_P2MM

*

BGA

CLK_FSB

*

BGA_P2MM

BGA

*

CLK_MED

BGA_P2MM

BGA

M75/M76 Rule Definitions

SYNC_DATE=02/02/2007

SYNC_MASTER=M76_MLB

051-7261

16

109109

TOP,BOTTOM

Y

0.085 MM

0.140 MM

100_DIFF_BGA

0.140 MM

0.085 MM

ISL2,ISL11

Y

100_DIFF_BGA

ISL9,ISL10

Y

0.075 MM

0.125 MM

100_DIFF_BGA

ISL3,ISL4 Y

0.075 MM

0.125 MM

100_DIFF_BGA

*

=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF

100_DIFF_BGA

=STANDARD

*

=STANDARD

100_OHM_DIFF

=STANDARD

=STANDARD=STANDARDN

Preliminary