Apple macbook pro a1129 Schematic

ANGLES

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

DATE

APPD

ENG

DATE

APPD

CK

ECN

ZONE

REV

DO NOT SCALE DRAWING

X.XXX

X.XX

XX

DIMENSIONS ARE IN MILLIMETERS

THIRD ANGLE PROJECTION

D

SIZE

APPLICABLE

NOTED AS

MATERIAL/FINISH

NONE

SCALE

DESIGNER

MFG APPD

DESIGN CK

RELEASE

QA APPD

ENG APPD

DRAFTER

METRIC

OF

SHT

DRAWING NUMBER

TITLE

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

Apple Computer Inc.

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

DESCRIPTION OF CHANGE

TABLE_TABLEOFCONTENTS_ITEM

DRAWING

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEADTABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEMTABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

02/02/2007

Schematic / PCB #’s

MANTARO

ALIASES RESOLVED

SMC

T9_NOME

49

12/21/2006

45

Left Clutch Barrel Interconnect

M75_MLB

47

12/21/2006

44

External USB Connector

M75_MLB

46

12/04/2006

43

PATA Connector

M75_MLB

44

12/07/2006

42

FireWire Ports

M75_MLB

43

12/04/2006

41

FireWire Port Power

M75_MLB

42

12/04/2006

40

FireWire PHY (TSB83AA22)

M75_MLB

41

12/04/2006

39

FireWire Link (TSB83AA22)

M75_MLB

40

12/04/2006

38

Ethernet Connector

M75_MLB

39

12/21/2006

37

Yukon Power Control

T9_NOME

38

01/25/2007

36

Ethernet (Yukon)

T9_NOME

37

01/25/2007

35

Left I/O Board Connector

(MASTER)

34

(MASTER)

34

Memory Active Termination

(MASTER)

33

(MASTER)

33

DDR2 SO-DIMM Connector B

M75_MLB

32

01/26/2007

32

DDR2 SO-DIMM Connector A

M75_MLB

31

01/26/2007

31

Clock Termination

M75_MLB

30

01/26/2007

30

Clock (CK505)

T9_NOME

29

01/25/2007

29

SB Misc

M75_MLB

28

01/30/2007

28

SB Decoupling

T9_NOME

27

01/25/2007

27

SB Power & Ground

T9_NOME

26

01/25/2007

26

SB Pwr Mgt, GPIO, Clink

T9_NOME

25

01/25/2007

25

SB PCI, PCIe, DMI, USB

T9_NOME

24

01/25/2007

24

SB Enet, Disk, FSB, LPC

T9_NOME

23

01/25/2007

23

NB Graphics Decoupling

(MASTER)

22

(MASTER)

22

NB Standard Decoupling

T9_NOME

21

12/21/2006

21

NB Grounds

T9_NOME

20

01/25/2007

20

NB Power 2

T9_NOME

19

01/25/2007

19

NB Power 1

T9_NOME

18

01/25/2007

18

NB DDR2 Interfaces

T9_NOME

17

01/25/2007

17

NB Misc Interfaces

T9_NOME

16

01/25/2007

16

NB PEG / Video Interfaces

T9_NOME

15

01/25/2007

15

NB CPU Interface

T9_NOME

14

01/25/2007

14

eXtended Debug Port (XDP)

T9_NOME

13

01/22/2007

13

CPU Decoupling & VID

M75_MLB

12

12/07/2006

12

CPU Power & Ground

T9_NOME

11

01/25/2007

11

CPU FSB

T9_NOME

10

01/25/2007

10

Signal Aliases

(T9_MLB)

9

08/23/2006

9

Power Aliases

(MASTER)

8

(MASTER)

8

Functional / ICT Test

MASTER

7

MASTER

7

Revision History

N/A

6 N/A

6

BOM Configuration

N/A

5 N/A

5

Power Block Diagram

N/A

4 N/A

4

Power Block Diagram

(T9_MLB)

3

08/23/2006

3

System Block Diagram

(T9_MLB)

2

08/23/2006

2

90

M75_MLB

01/26/2007

107

GPU (G84M) Constraints

89

T9_NOME

01/25/2007

106

FireWire Constraints

88

T9_NOME

01/25/2007

105

Clock & SMC Constraints

87

T9_NOME

01/25/2007

104

SB Constraints (2 of 2)

86

T9_NOME

01/25/2007

103

SB Constraints (1 of 2)

85

T9_NOME

01/25/2007

102

Memory Constraints

84

T9_NOME

01/25/2007

101

NB Constraints

83

T9_NOME

01/25/2007

100

CPU/FSB Constraints

82

M75_LIO

01/23/2007

99

Inverter Control IC

81

M75_LIO

01/23/2007

98

Inverter Support

80

(MASTER)

96

M76 Specific Connectors

79

M75_MLB

01/26/2007

95

LVDS Interface Mux

78

M75_MLB

01/26/2007

94

DVI Display Connector

77

M75_MLB

01/26/2007

90

LVDS Display Connector

76

M75_MLB

01/26/2007

89

GPU (G84M) Core Supply

75

M75_MLB

01/26/2007

88

NV G84M Video Interfaces

74

M75_MLB

01/26/2007

87

GPU Straps

73

M75_MLB

01/26/2007

86

NV G84M GPIO/MIO/Misc

72

M75_MLB

01/26/2007

85

GDDR3 Frame Buffer B

71

M75_MLB

01/26/2007

84

GDDR3 Frame Buffer A

70

M75_MLB

01/26/2007

82

NV G84M Frame Buffer I/F

69

M75_MLB

01/26/2007

81

NV G84M Core/FB Power

68

M75_MLB

01/26/2007

80

NV G84M PCI-E

67

M75_LIO

01/23/2007

79

PBus Supply & Batt. Charger

66

M75_MLB

01/26/2007

78

3.425V G3Hot Supply & Power Control

65

M75_MLB

12/04/2006

77

FW PHY Power Supplies

64

M75_MLB

12/04/2006

76

1.5V Power Supply

63

M75_MLB

12/04/2006

75

1.8V DDR2 Supply

62

M75_MLB

12/04/2006

74

1.25V / 1.05V Power Supply

61

M75_MLB

12/04/2006

73

5V / 3.3V Power Supply

60

M75_MLB

12/04/2006

72

IMVP6 NB Gfx Core Regulator

59

(MASTER)

71

IMVP6 CPU VCore Regulator

58

M75_MLB

01/23/2007

70

Power FETs

57

(MASTER)

69

DC-In & Battery Connectors

56

T9_NOME

01/25/2007

61

SPI BootROM

55

M75_MLB

12/04/2006

59

Sudden Motion Sensor (SMS)

54

M75_MLB

12/04/2006

58

ALS Support

53

(MASTER)

57

Current & Thermal Sensors

52

M75_MLB

12/04/2006

56

Fan Connectors

51

M75_MLB

01/26/2007

55

Thermal Sensors

50

M75_MLB

01/26/2007

54

Current Sensing

49

M75_MLB

01/26/2007

53

Current & Voltage Sensing

48

(MASTER)

52

SMBus Connections

47

M75_MLB

12/04/2006

51

LPC+ Debug Connector

02/02/2007

M76_MLB

M75/M76 Rule Definitions

92

109

(.csa)

Date

Page Contents SyncContents Sync

Date

(.csa)

Page Page Contents

Date

Sync

(.csa)

02/02/2007

M76_MLB

M76 Specific Constraints

91

108

Table of Contents

N/A

1 N/A

1

CRITICAL

SCH

1

051-7261

SCHEM,MLB,M76

LAST_MODIFIED=Fri Feb 2 12:41:32 2007

TITLE=MLB

ABBREV=DRAWING

PCBF,MLB,M76

1

PCB

CRITICAL820-2132

46

M75_MLB

01/26/2007

50

SMC Support

10.0.0

1

? ??

??

051-7261

92

SCHEM,MANTARO,M76

http://24hcongnghe.org

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

PG 23

CAMERA

PG 44

LEFT CLUTCH BARREL INTERCONN

Supply

Power

PG 67

U5570

Pg 51

U5500

Temp Sense

PG 54

ALS SENS

J6990/50

DC/Batt

U5805

CPU GPU

Conn

PG 57

PG 30

TERMSClocks

PG 29

CK 505

U2900

J3200

J3100

DIMM

PG31,32

ITP/XDP CONN

DDR2 - Dual Channel

1.8V - 64 Bits

533/667/800? MHz

U1000

CPU

PG 13

J1300

PG 16/17

Main Memory

2.? GHz

PG 10

Core ~1.2V

PG 11,12

FSB

64-Bit

Core

1.05 - 1.25V

NB-GMCH

PG 14

TV

PCI-E

U1400

U5550 Pg 51

Right Side

LPC Conn

PG 47

J5100

PG 44

WWAN

J4731

PG 80

Geyser

Trackpad/Keyboard

J9600

U5900

PG 55

PG 52

FAN CONN

POWER SENSE PG 49-50

J5650/60

SUDDEN MOTION SENSOR

Ser Prt

FanADC

Pg 46

SMC

BSBB,0 BSA

U4900

A

PG 80

Bluetooth

J9660

PG 80

IR

J9610

LEFT I/O J3400

CLK CHIP

U2900

SPI

PG 56

Boot ROM

USB

J4600

PG 43

EXT-A

CONN

PG 25

GPIOs

LPC

0

2 14 3

USB

5

PG 24

7 69 8

U6100

Misc

CLnk 0

PG 16

PG 16PG 16

DMI

PG 18~22

x4 DMI

2.5 GHz

DMI SPI

CLnk 0

PG 25

PG 24

SB-ICH8

Core 1.05V

U2300

SATA

PG 24

PG 23

IDE

PG 23

PCI-E

PG 24

DIMM’s

J3200

J3100

PG 25

SMB

AZALIA

PG 23

TSB83BA22

FW-Link

U4000

32-Bit

33 MHz

TSB83AA22

Pg 38

Pg 39

FW-PHY

8-Bit

U4000

100 MHz

J4310

Conn

Pg 41

FireWire

J4300

PCI

PG 24PG 25

CLnk 1

PG 23

Pg 25

Core

E-NET

ETHERNET

Pg 35

(YUKON ULTRA)

J3900

U3700

E-NET

Pg 37

Conn

Pg 59

Audio Codec

U6200

PG 15

RGB LVDS

800/1066? MHz

PG 15

LIO BOARD

Mini PCI-E

AirPort

Out

x16 PCI-E

SDVO

PG 68

PCI-EBUS INTERFACE

GDDR3 FRAME BUFFER A/B

PG 71,72

U8400,U8450,U8500,U8550

PG 70

DVI-INTERFACE

Core

1.25V - 0.96V

VIDEO INTERFACES

U8000

NV G84M

NV G84M FRAME BUFFER I/F

PG 75

PG 78

DVI DISPLAY CONN

J9400

PG 79

LVDS INTERFACE MUX

U9550

PG 75

MUX

SATA-0 SATA-2SATA-1 Ln1 Ln3Ln2

1.2 V / 1.5 GHz

100 MHz

3.3 V

LVDS DISP

PG 77

J9000/10

Conn

PATA

Pg 42

Conn

J4400

J9660

PG 80

SATA

Ln4 Ln5 Ln6

3 - X1

2.5 GHz

PG 34

EXT-B

CONNS

USB

EXT-C

PG 34

EXPRESS CARD

PG 34

SYNC_MASTER=(T9_MLB)

10.0.0

92

2

051-7261

System Block Diagram

SYNC_DATE=08/23/2006

http://24hcongnghe.org

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

PPDCIN_G3H

PPBUS_G3H

(PAGE 62)

(PAGE 64)

(PAGE 59)

(PAGE 60)

(PAGE 79)

(PAGE 66)

(PAGE 65)

(PAGE 62)

(PAGE 63)

(PAGE 61)

(PAGE 76)

(PAGE 57)

Q6950

U5705

INRUSH LIMITER

87438-0832

PGOOD

PPBUS_FW_FWPWRSW_F

P1V25_S0GPU_IOUT

U5430

PP1V25_ENET

418.1UF

TPS51117

LIO_DCIN_ISENSE

PP5V_S3

0.02UF

27

26

28

10

PM_PWRBTN_L

PLT_RST_L

PM_RSMRST_L

IMVP_VR_ON

FSB_CPURST_L

CPU_PWRGD

(10A MAX CURRENT)

SMC_RESET_L

VOUT

U5000

PP1V05_S0

1175.81UF

PP3V42_G3H

RN5VD30A-F

PPVCORE_S0_NB_R

(0.2A MAX CURRENT)

(PAGE 46)

SMC RESET "BUTTON"

VOUT

536.54UF

(PAGE 66)

U7800

LT3470

NBCORE_IOUT

3.425V"G3HOT"

VIN

SHDN*

U5420

A

PGOOD

VOUT

1.05V

TPS51117

U7450

VIN

P1V5P1V05S0_PGOOD

SMC_CPU_VSENSE

EN_PSV

PM_SLP_S3_L

(8A MAX CURRENT)

PP1V5_S0

352.31UF

Q5315

V

VOUT

PGOOD

TPS51117

U7600

1.5V

VIN

EN_PSV

SMC_PBUS_VSENSE

PM_SLP_S3_L

PWRBTN*

PLTRST*

RSMRST*

U2300

ICH8M

PWRGOOD

CPUPWRGD(GPIO49)

CPU

CLPWROK

VRMPWRGD

PWROK

PM_SB_PWROK

MCH

U1000

HCPURST*

RESET*

PLT_RST*

IMVP_VR_ON(P16)

99ms DLY

RSMRST_OUT(P15)

U1400

SMC

CL_PWROK

PWROK

PWRGD(P12)

RSMRST_IN(P13)

SMC_ONOFF_L

RSMRST_PWRGD

ALL_SYS_PWRGD

VR_PWRGD_CLKEN

U2830

U2840

1720UF

PPVCORE_SO_CPU

1323.67UF

U7880

PM_ALL_GFX_PGOOD

PM_ALL_S0_PWRGD

4A

S

PWR_BUTTON(P90)

RST*

P17(BTN_OUT)

(PAGE 45)

U4900

PM_SLP_S5_L(P95)

PM_SLP_S4_L(P94)

PM_SLP_S3_L(P93)

05

08-1

PM_SLP_S3_L

PM_SLP_S4_L

PM_SLP_S5_L

POWER ON SEQUENCE LIST

10-13

01-04 01,05-09

STEP 06 (S5 POWER STATUS)TRUTH TABLE

L(S5 OFF) L(S5 OFF)

ADAPTER IN :

BATTERY ONLY:

25-27

17,19-24

14-18

H(S5 ON) H(S5 ON)

STEP

99ms 200ms 7ms

S0_PGOOD_PWROK

PWR/RST STATUS G3H POWER ON S5 POWER ON S3 POWER ON

SIGNAL DELAY TIME

IMVP_VR_ON

S0 SYSTEM POWER ON

S0PWRGD_OK VR_PWRGOOD_DELAY

U7885

RST*

S0 CPU POWER ON

BATTERY ONLY,PRESS PWR BUTTON

NO AC/BATTERY

ACIN WITH/WITHOUT BATTERY

BATTERY ONLY

PLATFORM,CPU RESET

PM_ALL_NBGFX_PGOOD

74CBTLV3257

U9560

LVDSCTRLMUX_SEL_GPU_L

(0.2A MAX CURRENT)

PANEL/BACKLIGHT CONTROL MUX

LTC2900

U7870

NBGFXCORE_IOUT

(10A MAX CURRENT)

PPVCORE_SO_NB_GFX

(44A MAX CURRENT)

V

CPUVCORE_IOUT

A

U5410

VOUT

U5400

VR_PWRGD_CLKEN_L

VR_PWRGOOD_DELAY

CLKEN#

VOUT

U7100

VIN

PGOOD

ISL6263

VIN

U7200

VR_ON

4B1

4B2

PM_ALL_GPU_PGOOD

RST*

PGOOD

V2(3.3V) V3(1.8V) V4(1.25V)

V1(3.3V)

GFX_VR_EN

CPUVCORE

ISL9504

VR_ON

IMVP_VR_ON

5.9UF

PP5V_S0

165UF

PP3V3_S5

PP3V3_S0

3.4UF

7.2UF

PP3V3_S3

PP3V3_GPU

3.91UF

V1(5V) V2(3.3V) V3(1.8V) V4(1.25V)

U9590

LTC2900

81.3UF

4.2UF

27.11UF

PP1V95_FW

PP3V3_FW

VOUT

TPS799195 U7720

PP1V25_GPU

PP1V9_ENET

1UF

VOUT

(PAGE 36)

TPS79501

VOUT

U3850

EN

IN

P1V25GPU_SS

Q7090

PP3V3_ENET

6.102UF

22.1UF

U7700

LT3470

SHDN*

VIN

EN

PPVIN_FW_3.3VFW

PPVP_FW

P3V3ENET_SS

P3V3GPU_SS

P1V25S0_SS

P3V3S0_SS

P5VS0_SS

P5VS3_SS

P3V3S3_SS

PP5V_S5

PP1V25_S0

384.1UF

M76 POWER SYSTEM ARCHITECTURE

A

U5705

PPVBAT_G3H_CHGR_OUT

VOUT

FET

(PAGE 67)

U7900

(PAGE 67)

CHGR_EN

PBUS SUPPLY /

BATTERY CHARGER

BATTERY CHARGE

ISL6255A

VIN

ENABLES

PPVBATT_G3H_FET

LIO_DCIN_ISENSE

A

8A FUSE

PP18V5_G3H_CHGR

VOUT

BATT_POS

VIN

PP18V5_DCIN

87438-1043

CRITICAL

J6950

518S0456

CRITICAL

J6990

Q7000

Q7020

PPVCORE_GPU

(18A MAX CURRENT)

675UF

SMC_GPU_VSENSE

V

A

Q7010

Q7030

Q7070

2.7UF

PP0V9_S0

PP1V8_S3

PP5V_S5

RSMRST_PWRGD

PP3V3_S5

CURRENT)

(8A MAX CURRENT)

(5.5A MAX

GPUVCORE_IOUT

U8995

VOUT

U8900

VIN

EN_PSV

VOUT1

GPUVCORE_PGOOD

PGOOD

5V

VIN

ENA1

PM_GPUVCORE_EN

SMC_PM_G2_EN

VOUT2

TPS51120

3.3V

U7300

VOUT1

0.9V

VIN

1.8V

S5_EN

S3_VTT_EN

ENA2

PM_SLP_S3_L

PM_SLP_S4_L

728.6UF

Q3810

2.1UF

159.36UF

PP1V8_S0

P1V8S0_SS

PP1V8_GPU

P1V8GPU_SS

Q7050

Q7080

A

Q7095

345.203UF

1.5A FUSE

A

U5440

PP1V8_S3_ISNS

P1V8_S3_IOUT

(8A MAX CURRENT)

VOUT2

TPS511160

U7500

TP1V8S3_PGOOD

PGOOD

(UNUSED)

VIN

VOUT

EN_PSV

P3V3ENET_SS

TP1V25ENET_PGOOD

U7400

TPS51117

(UNUSED)

PGOOD

Q4260

P3V3ENET_SS

P1V8GPU_SS

PM_ENET_EN

PM_GPUVCORE_EN

P3V3GPU_SS

P1V25GPU_SS

P5VS3_SS

P3V3S3_SS

DELAY

R=100K

C=68NF

R=100K

C=68NF

DELAY

518S0457

Q7002

Q7012

C=1UF

R=100K

DELAY

R=100K

DELAY

PM_SLP_S4_L

Q7091

Q7851

Q7072

Q7851

PM_SLP_S3_LS5V

EXTGPU_PWR_EN

PM_SLP_S3_L

Q7091

GPUVCORE_PGOOD

SLP_S3*

GPIO23

SLP_S4*

U2300

ICH8M

R=100K

PM_GPUP1V8FET_EN

DELAY

C=1UF

PM_ENET_EN

C=1UF

DELAY

R=100K

Q3800 Q3801

Q7081Q7081

Q7850

Q3801

SMC_ADAPTER_EN

R=100K

P1V8S0_SS

DELAY

P1V25S0_SS

DELAY

R=100K

C=1UF

P3V3S0_SS

P5VS0_SS

DELAY

C=1UF

Q7051

R=100K

R=100K C=1UF

DELAY

Q7096

Q7002

Q7012

Q7051

Q7096

Q7850

SYNC_MASTER=(T9_MLB)

3

92

10.0.0

051-7261

SYNC_DATE=08/23/2006

Power Block Diagram

http://24hcongnghe.org

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

SYNC_DATE=N/A

SYNC_MASTER=N/A

4

92

10.0.0

051-7261

Power Block Diagram

http://24hcongnghe.org

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

M76 BOM Groups

Bar Code Labels / EEE #’s

Module Parts

BOM Variants

Alternate Parts

ALL

152S0276152S0476

Inductor alternate

138S0602

ALL

138S0603

Murata alt to Samsung 22uF acoustic caps

ALL

AOS alternate to Siliconix Si4413

376S0543 376S0466

ALL

376S0526

Fairchild FDW252P alternate to IRF7707

376S0451

ALL

E&E alt to TDK/BiTech magnetics

157S0011 157S0030

353S1294

TI alternate to National

353S1681

ALL

IC,16MBIT 8-PIN SPI SERIAL FLASH,SOIC8

BOOTROM_BLANK

U6100

1

CRITICAL335S0384

IC,EFI ROM,DEVELOPMENT,M75

1

BOOTROM_PROG

U6100

CRITICAL341S2002

VRAM_256_SAMSUNG

CRITICAL

U8400,U8450,U8500,U8550

4

333S0350

IC,SGRAM,GDDR3,16MX32,700MHZ,136 FBGA

CPU_2_4GHZ

U1000

CRITICAL

1

337S3458

IC,MDC,SR,E1,QS,2.4G,35W,800FSB,4M,BGA

VRAM_256_HYNIX

CRITICAL

U8400,U8450,U8500,U8550

4

333S0351

IC,SGRAM,GDDR3,16MX32,700MHZ,136 FBGA

[EEE:X6P]

LBL,P/N LABEL,PCB,28MM X 6 MM

826-4393

1

EEE_X6P

CRITICAL

SMC_DEBUG_YES,XDP,XDP_CONN,LPCPLUS

M76_DEBUG

U8400,U8450,U8500,U8550

VRAM_256_INFINEON

CRITICAL

4

333S0377

IC,SGRAM,GDDR3,16MX32,600MHZ,136 FBGA

M76_PROGPARTS

BOOTROM_PROG,SMC_PROG

359S0130

IC,SLG2AP101,LW PWR CLK GEN,CK505,QFN68

SLG2AP101

CRITICAL

U2900

1

IC,88E8058,GIGABIT ENET XCVR,64P QFN

CRITICAL

U3700

1

338S0386

IC,SMC,DEVELOPMENT,M76

SMC_PROG

1

CRITICAL

U4900

341S2050

IC,SMC,HS8/2116

SMC_BLANK

U4900

CRITICAL

1

338S0274

IC,68 PIN,CK505,LOW POWER CLOCK GENER

SLG8LP537

U2900

CRITICAL

1

359S0127

IC,ISL9504B,2PH IMVP6 REG,PMON,QFN48

ISL9504BCRITICAL

U7100

1

353S1651

IC,NB,CRESTLINE,GM,C0,QS

U1400

1

CRITICAL338S0426

IC,GPU,NV G84M,BGA

U8000

1

CRITICAL338S0388

LBL,P/N LABEL,PCB,28MM X 6 MM

EEE_XZ7

[EEE:XZ7]

1

826-4393 CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

EEE_XZ6

[EEE:XZ6]

CRITICAL

1

826-4393

IC,ISL9504B,2PH IMVP6 REG,PMON,QFN48

U7100

CRITICAL

1

ISL9504A353S1461

IC,SB,ICH8M,B1,QS,BGA

U2300

CRITICAL

1

338S0427

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEE:XWU]

EEE_XWU

CRITICAL

1

826-4393

SYNC_MASTER=N/A

BOM Configuration

5

051-7261

10.0.0

92

SYNC_DATE=N/A

PCBA,MANTARO1,BTR,VRAM-SAM,M76

630-7943

M76_COMMON,CPU_2_4GHZ,VRAM_256_SAMSUNG,VRAM_256,VRAM_SAMSUNG,INV_BYPASS,EEE_X6P

INV_SPLIT,INV_17INCH

M76_CTO

P1V8S3_1V825,SLG2AP101,SMS_MOT_DIS,YUKON_ULTRA,VGA_TERM_CONN

M76_COMMON2

630-8549

PCBA,MANTARO2,BTR,VRAM-HY,M76

M76_COMMON,CPU_2_4GHZ,VRAM_256_HYNIX,VRAM_256,VRAM_HYNIX,INV_BYPASS,EEE_XWU

M76_COMMON1

EXTGPU_RST_SW,GPU_SS_EXT,GPU_TMP401,HDCP,ISL9504B,LVDS_SEL_RESUME,ONEWIRE_PU

M76_COMMON

COMMON,ALTERNATE,M76_COMMON1,M76_COMMON2,M76_DEBUG,M76_PROGPARTS,ISL6257H

630-8733

M76_COMMON,CPU_2_4GHZ,VRAM_256_HYNIX,VRAM_256,VRAM_HYNIX,M76_CTO,EEE_XZ7

PCBA,MANTARO4,CTO,VRAM-HY,M76

630-8732

PCBA,MANTARO3,CTO,VRAM-SAM,M76

M76_COMMON,CPU_2_4GHZ,VRAM_256_SAMSUNG,VRAM_256,VRAM_SAMSUNG,M76_CTO,EEE_XZ6

http://24hcongnghe.org

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

through

EVT

7.2.0:

7.1.0:

Change 41000 by wferry@t9_mlb_noME_951-0475_6.2.0_tmp.Ecad on 2007/01/21 20:34:18

1/22/07 -- Changed alias name to =PP3V3_S3_P3V3ENETFET.

- Clock Termination: Added R3051 for Silego 537/101 compatibility

Changes since previous major release (9.4.0):

- Added support for WOL_EN GPIO (pg. 38).

Ethernet:

- Added mobile support for Wake-on-Wireless with WOW_EN GPIO (pp. 13,24).

AirPort:

Clocking:

- Removed VCCGLANPLL RLC filter since GLAN is not used in noME (pg. 27).

Southbridge:

mini-XDP:

EVT release for M75 LIO

Change 41322 by xyang@xyang_m57.Ecad on 2007/01/23 15:41:38

1/23/07 -- Integrated CSA pages 79,98,99 of m75/lio through:

7.3.0:

- BOM: Selected P1V8S3_1V825 BOMOPTION to lift voltage at FB memories

- BOM: Added BOMOPTIONs for SLG2AP101 (primary) and SLG8LP537 (backup)

1/22/07 -- L2700 had the same net on both pins due to bad alias, which eliminated filtering on PP1V5_S0_SB_VCC1_5_B.

1/22/07 -- Changed reference designators of R3920-R3927 to RX3920-RX3927.

1/22/07 -- Changed R7455 from 3.74K (114S0273) to 4.32K (114s0279) to adjust current limit.

- Clocks: Changed U2900 to SLG2AP101 as primary clock chip (T9_noME change 40975)

1/23/07 -- Integrated m75/mlb CSA pages 28,30-32,50,53-55,70,78,80-82,84-89,90,94-95,107

1/23/07 -- C9822 & C9918 changed from 0.01uF 20% 50V CERM to 0.01uF 10% 50V X7R

1/23/07 -- C7908 changed from 33uF,20%,16V to 22uF,20%, 25V. 1/23/07 -- R7953 changed from 21K to 19.6K. 1/23/07 -- U7950.5 PGOOD output is now NC.

1/24/07 -- Updated APN for latest 2.4GHz CPU, NB, and SB. 1/24/07 -- Corrected APN for SLG2AP101. 1/24/07 -- Fixed circular alias on =PP3V3_S0_LCD so that it only points to PP3V3_S5.

1/25/07 -- Integrated t9/mlb_noME CSA pages 10,11,14-20,23-27,29,37,38,61,100-106

Change 41249 by wferry@wferry_projects.Ecad on 2007/01/23 10:35:37

8.0.0:

8.1.0:

through:

Change 41249 by wferry@wferry_projects.Ecad on 2007/01/23 10:35:37

Integrated m75/mlb CSA pages 28,30-32,50,53-55,78,80-82,84-89,90,94,95,107-109

8.3.0:

values.

8.2.0:

through:

1/30/07 -- Changed R9921 from 182K (114S0436) to 64.9K (114S0428) per Flo Kim.

1/30/07 -- Changed R9920 from 68.1K (114S0396) to 64.9K (114S0394) per Flo Kim.

1/30/07 -- Added BOM option INV_SPLIT to J9655, 2 pin inverter connector.

1/30/07 -- Added 376S0526 (FDW252P) as alternate to 376S0451 (IRF7707) on Q7020.

- SB Misc: Renamed hardware/software GPU reset selector BOMOPTIONs to EXTGPU_RST_SW/HW

- SB Misc: Added EXTGPU_PWR_EN as part of hardware-based GPU reset qualification logic

Changes since previous fab release (11.0.0):

Submitting as minor release so changes can make M76 EVT

Change 42529 by cerickso@cerickso_m75.Ecad on 2007/01/30 15:04:57

1/30/07 -- Integrated m75/mlb CSA page 28 through

1/26/07 -- ODD: Replaced PCIREQ pass FET with OD buffer to correct a corner case during PLTRST

1/26/07 -- Updated PP5V_S0 aliases to support PCIREQ changes.

as not yet been integrated into M75 main-line).

Updated page 108, now M76-specific. Based on M75 page submitted 1/24.

Change 42002 by wferry@wferry_projects.Ecad on 2007/01/26 14:16:14

1/26/07 -- Integrated wferry/m76/mlb CSA page 108,109 through:

1/25/07 -- Moved =PP5V_S0_ODD to PP5V_S5 for layout reasons. Enable is still on S0.

1/25/07 -- Added BOM options for GPU straps.

Changes since previous major release (10.2.0):

This is second fab release for EVT!

Change 41851 by cerickso@m75_mlb_051-7225_11.0.0_tmp.Ecad on 2007/01/25 18:43:57

match latest m75/mlb page108.csa, as well as removing property assignments to nets not in M76 netlist.

108: Assigning new 100_DIFF_BGA rule to LVDS, TMDS and PCIe nets in "BGA" constraint areas. Also some net property fixes t

109: Added 100_DIFF_BGA rule defining 100-ohm for outer layers and 95-ohm for inner layers using tighter line width & spaci

Page 109 also sync’ed from wferry_m75/mlb, no changes from 1/24 submission (this remains a shared page, though I believe it

- Current Sensing: Updated gain of PP1V25_ENET current sense amplifier to 165 (R5432 to 165K)

1/30/07 -- Corrected location of Q7020.

8.4.0:

1/22/07 -- Changed U2900 to SLG2AP101 (primary) and SLG8LP537 (backup)

Change 41155 by cerickso@m75_mlb_051-7225_9.5.0_tmp.Ecad on 2007/01/22 16:50:43

Page 38: Changed C3860 & C3861 from 27pF to 22pF per Quanta M75 Proto characterization

1/31/07 -- Changed L7810 from 152S0301 to 152S0558 for package height restriction. This is the 3.42V regulator inductor.

1/31/07 -- Added BOM option EXTGPU_RST_SW to BOM group M76_COMMON1. 1/31/07 -- Added GPU NO_TEST properties on LVDS_L_DATA_P/N[0]

1/31/07 -- Added BOM table for U4000 to use TI PHY 338S0435.

1/31/07 -- Added OMIT to U4000.

9.0.0:

1/31/07 -- Added OMIT to U4000.

2/2/07 -- NO_TEST properties on GPU signals: LVDS_L_CLK_P,LVDS_L_DATA_P<0>,TP_GPU_MIOB_CLKIN,TP_GPU_MIOB_CLKOUT_P,TP-GPU_MIOB

2/2/07 -- Page 109: Changed 100_DIFF_BGA rule to call out 100-ohm differential impedance by default, but allow necks to 95

2/2/07 -- Page 108: Changed PCIe, LVDS & TMDS to call out 100_DIFF_BGA rule in all area types, not just BGA, since Allegro

hm differential values (0.085mm lines / 0.140mm spacing outer layers, 0.075mm/0.125mm inner layers)

2/2/07 -- Updated pages 108 & 109, used to generate rule version 0.4.0.

Change 43022 by wferry@wferry_projects.Ecad on 2007/02/01 16:54:10

2/2/07 -- Integrated CSA pages 108,109 of m76/mlb through

2/1/07 -- CPU IMVP6 Regulator: Changed L7100 and L7101 from 152S0517 to 152S0433 per Steve Sfarzo for greater EDP peak current (CPU turbo speed mode). 2/1/07 -- Added R9951 and R9961, both 33.2 1% 0402 per Flo Kim for split inverter.

_CTL3

10.0.0:

9.1.0:

1/22/07 -- Changed R7526 from 5.6 Ohms (113s0320) to 1 Ohms(113s0023) to improve driver performance.

1/22/07 -- Changed pull-ups on SMC "B" SMBus signals from 4.7K to 3.3K (R5260 and R5261 from 116s0082 to 116s0078).

- Power Sequencing improvements (pg. 38).

- Changed CK505 from SLG8LP537 to SLG2AP101 (pp. 29, 30).

- Connected floating power ball (U2300.AC24) (pg. 26).

- Removed final ITP BOMOPTIONs, now only XDP remains (pp. 28, 29).

1/22/07 -- Integrated t9/mlb_noME CSA pages 10,11,13-20,23-27,29,37,38,61 through:

1/22/07 -- Added signal PM_WLAN_EN_L on J3400.8.

1/22/07 -- Updated power block diagram.

1/18/07 -- Added BOM option ISL9504B to some components. They can be stuffed differently for ISL9504.

1/18/07 -- Changed C5901, C5902, and C5903 to 132s0131, 0.033UF, X5R, 10%, 16V.

1/18/07 -- Added OMIT BOM option to R3920-R3927 shorts.

1/18/07 -- Changed BOM option to ISL9504B, to use 353S1651 for U7100, CPU IMVP6 regulator.

01/12/07 -- Released for Proto (Schem Rev 07, PCB Rev 01)

See Perforce change notes for updates before Proto Release

PROTO

6

92

10.0.0

051-7261

Revision History

SYNC_MASTER=N/A

SYNC_DATE=N/A

http://24hcongnghe.org

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

FUNC_TEST

FUNC_TESTFUNC_TEST

FUNC_TEST

Left ALS

FUNC_TEST

Left I/O Power Connector

NOTE: 10 additional GND test points are called out separately in these notes.

RTC Battery Connector

FUNC_TEST

Inverter Connector

per

2 TPs

LPC+ Debug Connector

Fan Connectors

FUNC_TEST

(HOST_DETECT_L)

Battery Digital Connector

Functional Test Points

Other Func Test Points

FUNC_TEST

6 TPs, 2 with each of above TP pairs

FUNC_TEST

Current Sense Calibration

FUNC_TEST

Request for at least 10 GND test points

NO_TEST

CPU FSB NO_TESTs

NO_TEST

Left Clutch Barrel Connector

FUNC_TEST

IR & Sleep LED Connector

Request for 2 test points Request for 3 test points

System Validation TPs

Thermal Diode Connectors

ICT Test Points

NB NO_TESTs

NO_TEST

GPU NO_TESTs

I404

I405

I406

I407

I408

I409

I410

I411

I412

I413

I414

I415

I416

I417

I418

I419

I420

I421

I422

I423

I424

I426

I427

I428

I430

I431

I432

I433

I436

I442

I443

I447

I448

I490

I491

I492

I493

I494

I495

I496

I497

I498

I506

I507

I509

I515

I516 I517

I519

I520

I521

I522

I523

I524

I529

I530

I531

I533

I534

I535

I536

I539 I540

I541

I542

I544

I545

I546

I547

I548

I549

I550 I551

I552

I553

I554

I555

I556

I557

I558 I559

I561

I562

I563

I564

I565 I566

SYNC_DATE=MASTER

SYNC_MASTER=MASTER

7

92

10.0.0

051-7261

Functional / ICT Test

LVDS_L_CLK_P

TRUE

LVDS_L_DATA_P<0>

TRUE

TP_GPU_MIOB_CLKIN

TRUE

TP_GPU_MIOB_CLKOUT_P

TRUE

TP_GPU_MIOB_CTL3

TRUE

NC_NB_NC<1..16>

FSB_ADS_L

TRUE

FSB_BNR_L

TRUE

FSB_BREQ0_L

TRUE

FSB_DSTB_L_P<3..0>

FSB_LOCK_L

TRUE

FSB_REQ_L<4..0>

TRUE

FSB_HITM_L

TRUE

FSB_D_L<63..0>

TRUE

USB_IR_N

SYS_LED_ANODE

TRUE

PM_ENET_EN

TRUE TRUE

P1V5P1V05S0_PGOOD

PLT_RST_L

TRUE

CPU_STPCLK_L

PM_BMBUSY_L

TRUE

PM_LAN_ENABLE

TRUE

CPU_DPSLP_L

TRUE

CPU_DPSLP_L

LTALS_OUT

TRUE

ALS_GAIN

TRUE

SMC_RX_L

TRUE

NB_CLK100M_DPLLSS_P

TRUE

NB_CLK100M_DPLLSS_N

TRUE

CPU_THERMTRIP_R

TRUE

PM_SLP_S3_L

TRUE

GND_CHASSIS_INVERTER

FSB_DSTB_L_N<3..0>

TRUE

FSB_DRDY_L

TRUE

FSB_DBSY_L

TRUE

FSB_CPURST_L

FSB_DPWR_L

TRUE

NB_CLK100M_PCIE_P

NB_CLKREQ_L

TRUE

FSB_CLK_NB_N

TRUE

FSB_CLK_NB_P

TRUE

SMC_LRESET_L

TRUE

GPU_RESET_L

TRUE

NB_RESET_L

TRUE

NB_SB_SYNC_L

TRUE

PM_STPPCI_L

TRUE

PCI_RST_L

TRUE

CPU_PWRGD

TRUE

PM_DPRSLPVR

TRUE

PM_RSMRST_L

TRUE

PM_SB_PWROK

TRUE

SB_RTC_RST_L

FSB_CPUSLP_L

TRUE

VR_PWRGOOD_DELAY

TRUE

VR_PWRGD_CLKEN

TRUE

PM_STPCPU_L

TRUE

CPU_DPRSTP_L

TRUE

FSB_CLK_CPU_N

TP_NB_NC<1..16>

FSB_A_L<31..3>

TRUE

FSB_ADSTB_L<1..0>

FSB_DINV_L<3..0>

TRUE

FSB_HIT_L

TRUE

PPVCORE_S0_NB_GFX

TRUE

PPBUS_G3H

PP5V_S0

TRUE

PPVCORE_GPU

TRUE

PP5V_S3_WWAN_F

TRUE

USB_CAMERA_F_P

ISENSE_CAL_EN

TRUE

PPVCORE_S0_CPU

TRUE

LINDACARD_GPIO

SMC_NMI

TRUE

SMC_TCK

TRUE

PM_SUS_STAT_L

TRUE

INT_SERIRQ

TRUE

LPC_AD<2>

TRUE

PCI_CLK33M_LPCPLUS

FWH_INIT_L

TRUE

USB_WWAN_F_P

SMC_ONOFF_L

TRUE

PM_SYSRST_L

TRUE

USB_WWAN_F_N

TRUE

PP5V_S3_CAMERA_F

TRUE

SMBUS_SMC_BSA_SDA

TRUE

PP18V5_DCIN

TRUE

SMC_BS_ALRT_L

TRUE

USB_CAMERA_F_N

TRUE

PPVBATT_G3_RTC

REMTHMSNS_DX_P

TRUE TRUE

REMTHMSNS_DX_N

TRUE

CPUTHMSNS_D2_P

TRUE

FAN_RT_PWM

TRUE

SMC_TRST_L

TRUE

FAN_LT_TACH

TRUE

PP5V_S3

TRUE

USB_IR_P

TRUE

PPBUS_SO_LCDBKLT

TRUE

PP5V_SW_LCDBKLT

TRUE

LCDBKLT_PWM

SMC_MD1

TRUE TRUE

SMC_TX_L

CPUTHMSNS_D2_N

TRUE

FAN_RT_TACH

TRUE

PP5V_S0

TRUE

PP3V42_G3H

TRUE

FAN_LT_PWM

TRUE

BATT_POS

TRUE

SMBUS_SMC_BSA_SCL

TRUE

LPC_AD<1>

SMC_RESET_L

TRUE

DEBUG_RESET_L

TRUE

PCI_FW_GNT_L

TRUE

LPC_AD<0>

TRUE

LPC_FRAME_L

IMVP_VR_ON

TRUE

IMVP_DPRSLPVR

TRUE

NB_CLK96M_DOT_N

TRUE

NB_CLK100M_PCIE_N

FSB_CLK_CPU_P

TRUE

NB_CLK96M_DOT_P

TRUE

GND

SMC_TDI

TRUE

LPC_AD<3>

SMC_TDO

TRUE

SMC_TMS

TRUE

PM_CLKRUN_L

TRUE

PP5V_S0

TRUE

IMVP6_VID<6..0>

TRUE

PM_SLP_S5_L

PM_S4_STATE_L

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

81

82

80

76

78

67

66

64

60

80

60

63

59

67

59

66

62

58

66

58

63

61

54

57

54

58

60

52

48

52

49

59

49

47

49

66

81

88

45

83

58

47

59

80

47

46

47

58

79

83

47

30

40

82

83

88

83

59

88

60

57

42

76

49

47

88

58

47

42

45

88

87

88

42

45

90

83

86

66

28

83

23

54

46

29

36

80

83

14

83

30

23

59

28

83

28

30

23

30

83

22

49

27

69

12

47

46

47

88

80

45

57

46

86

46

27

43

57

47

30

47

27

83

46

43

79

74

14

80

62

64

24

23

25

45

10

54

45

22

35

44

14

13

14

29

45

68

28

25

29

28

13

25

45

25

28

14

16

28

29

16

29

14

18

40

8

49

91

49

11

47

46

45

47

91

46

28

91

48

46

91

47

44

80

82

47

45

8

28

67

48

45

46

47

38

45

59

83

29

46

45

46

45

8

59

45

34

75

73

10

24

46

36

62

9

10

16

25

7

34

43

16

23

25

9

10

16

14

28

16

25

24

10

16

25

9

23

10

9

25

10

16 10

10

8

7

8

44

45

8

25

45

25

23

30

47

44

45

25

44

45

57

45

44

28

51

52

45

52

8

24

81

45

43

51

52

7

8

52

57

45

23

45

28

24

23

45

59

88

16

10

88

45

23

45

25

7

12

25

http://24hcongnghe.org

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Yukon EC will not be supported

Chipset "VCore" Rails

1.8V-0.9V Rails "FW" (FireWire) Rails

5V Rails

"GPU" Rails

"ENET" Rails

MAX I = ?.??A

MAX I = 0.36A

3.3V-2.5V Rails

"G3Hot" (Always-Present) Rails

Power Aliases

051-7261

10.0.0

92

8

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

PP3V3_S5

PP3V3_S0

PP3V3_S3

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP3V3_S3

MAKE_BASE=TRUE

VOLTAGE=3.3V

PPBUS_G3H

PP3V3_S5

PPBUS_G3H PPBUS_G3H PPBUS_G3H

PPBUS_G3H

PPDCIN_G3H

PP3V42_G3H

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

PP1V05_S0

MAKE_BASE=TRUE

PP1V05_S0

PP1V8_GPU

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

PP1V25_S0

PP1V8_GPU

PP3V3_GPU_TMDS

MIN_LINE_WIDTH=0.4 mm

MAKE_BASE=TRUE

PP3V3_GPU_TMDS

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

PP3V3_GPU

MIN_NECK_WIDTH=0.2 mm

PP3V3_GPU

MIN_LINE_WIDTH=0.4 mm VOLTAGE=3.3V

MAKE_BASE=TRUE

PP1V95_FW

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.95V MAKE_BASE=TRUE

PP3V3_FW

PP1V8_S3_ISNS

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V

PP1V8_S3

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 mm MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm

PP1V8_S3

PP1V8_S3_ISNS

PP1V8_S0

PP1V25_S0

PP0V9_S0

MAKE_BASE=TRUE

PP3V3_ENET

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

PP3V3_ENET PP3V3_ENET

PP5V_S5

PP5V_S5 PP5V_S5

PPBUS_G3H

PP1V5_S0

VOLTAGE=1.25V

PP1V25_S0

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

PP1V25_S0

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

PP1V5_S0

PP1V05_S0 PP1V05_S0

PP1V05_S0

PPVCORE_S0_NB_R

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

VOLTAGE=0.9V

PP0V9_S3_MEM_VREF

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

VOLTAGE=0.9V

PP3V3_ENET

PP1V9_ENET

MAKE_BASE=TRUE

VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP1V25_ENET

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V MAKE_BASE=TRUE

PP1V8_S0

PP5V_S5

PP1V25_ENET_ISNS

PP3V42_G3H

PP1V8_S0

PP1V95_FW

PP3V3_GPU

GND

PP1V05_S0

PP1V25_GPU

PP3V3_GPU

PPVP_FW_PORTA_UF

PPVP_FW

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.3 mm VOLTAGE=33V

PPVP_FW

PP5V_S3

PP5V_S5

PP3V42_G3H

MIN_LINE_WIDTH=0.4 mm

MAKE_BASE=TRUE

PPDCIN_G3H

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=3.42V

MIN_NECK_WIDTH=0.2 mm MAKE_BASE=TRUE

PP3V42_G3H

MIN_LINE_WIDTH=0.3 mm

PP3V42_G3H

PPDCIN_G3H

PP5V_S5 PP5V_S5

PP3V3_S5

PP5V_S5

PP5V_S3

PP5V_S5

PP5V_S0

MAKE_BASE=TRUE

PPBUS_FW_FWPWRSW_F PPBUS_FW_FWPWRSW_F

PP3V3_GPU

PP3V3_FW

PPVP_FW_PORTB_UF

MAKE_BASE=TRUE

PPVP_FW_PORTB_UF

PPVP_FW_PORTA_UF

MAKE_BASE=TRUE

PPVP_FW

MIN_LINE_WIDTH=0.4 mm

MAKE_BASE=TRUE

PP3V3_FW

MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

PPVCORE_GPU

PP1V25_GPU

PP3V3_GPU_TMDS

PP5V_S0

VOLTAGE=1.25V

MIN_LINE_WIDTH=0.6 mm

PPVCORE_S0_CPU

MIN_NECK_WIDTH=0.3 mm MAKE_BASE=TRUE

PP5V_S0

PPVCORE_S0_NB_GFX

PPVCORE_S0_NB_GFX PPVCORE_S0_NB_GFX

PP5V_S3 PP5V_S3

PP5V_S5

PPVCORE_S0_CPU

PP3V3_GPU_TMDS

PP1V8_GPU

PP1V25_GPU

PP1V25_GPU PP1V25_GPU PP1V25_GPU

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.2V

PP1V25_GPU

PP1V25_ENET_ISNS

PP1V9_ENET

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.9V

PP1V8_S0

PP1V05_S0

PPVCORE_S0_NB_R

PP0V9_S3_MEM_VREF PP0V9_S3_MEM_VREF

PP0V9_S3_MEM_VREF

PP0V9_S3_MEM_VREF PP0V9_S3_MEM_VREF

PP1V25_ENET

PP1V8_S3_ISNS

PP1V8_S3_ISNS PP1V8_S3_ISNS

PP1V8_S3_ISNS

PP1V8_S3 PP1V8_S3

PP1V8_S3

PP5V_S3

PPVCORE_S0_CPU

PPVCORE_S0_NB_GFX

MIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUE

VOLTAGE=1.25V

MIN_NECK_WIDTH=0.25 mm

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 mm

PP1V25_ENET_ISNS

PP1V25_ENET

PP3V3_GPU

PP3V42_G3H

PP1V25_ENET

PP1V9_ENET

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

PP0V9_S0

VOLTAGE=0.9V

PP0V9_S0

PPVCORE_GPU

MIN_NECK_WIDTH=0.2 mm

PPVCORE_GPU

VOLTAGE=1.2V

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

PP1V25_S0

PP1V5_S0

PP1V25_S0

PP1V5_S0

PPDCIN_G3H

PP3V3_S5

PPBUS_G3H

PPBUS_G3H PPBUS_G3H

PP3V3_S5

PP3V3_S0

PP3V3_S0 PP3V3_S0

PP3V3_S0 PP3V3_S0 PP3V3_S0

PP3V3_S0

PPBUS_G3H

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V

PPBUS_G3H

MAKE_BASE=TRUE

PP5V_S5

PP5V_S0

PP5V_S5

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

VOLTAGE=5V

MIN_NECK_WIDTH=0.2 mm

PP5V_S3

PP5V_S5

MIN_NECK_WIDTH=0.2 mm MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm VOLTAGE=5V

PP5V_S5

PP5V_S0

MIN_LINE_WIDTH=0.6 mm

PP5V_S0

VOLTAGE=5V

MIN_NECK_WIDTH=0.2 mm MAKE_BASE=TRUE

PP5V_S0

PP3V3_S0

PP3V3_S3

PP3V3_S5

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

PP3V3_S5

MAKE_BASE=TRUE

PP3V3_S5 PP3V3_S5

PP3V3_S3

PP3V3_S3 PP3V3_S3 PP3V3_S3

PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3

PP3V3_S0

PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0

PP3V3_S0

MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm

PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0

PP3V3_S0

PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0

91

81

79

77

76

66

60

59

58

53

52

51

50

48

47

46

42

62

42

32

82

50

82

50

81

50

82

32

82

81

32

91

31

76

91

76

46

76

46

91

80

46

91

76

91

31

76

80

31

91

31

77

30

67

77

67

30

67

30

77

78

30

77

67

77

30

67

78

30

77

30

66

29

64

66

64

80

27

64

27

80

27

80

66

27

80

66

64

66

29

64

66

29

66

29

61

28

63

61

63

67

26

76

63

26

76

67

26

76

67

76

61

76

60

76

26

67

61

63

61

28

63

76

60

76

60

28

61

28

58

27

62

58

62

66

23

79

66

62

91

23

66

79

23

79

66

58

66

59

79

59

66

23

79

66

91

58

62

58

27

62

66

59

66

59

27

58

27

56

26

80

61

56

61

57

21

78

64

61

64

21

64

57

78

21

78

64

57

64

56

64

58

78

58

64

21

78

57

64

56

61

56

26

61

64

58

64

58

26

80

56

80

26

48

25

58

60

48

60

48

19

79

76

63

60

34

19

63

48

76

19

76

63

48

63

48

63

54

76

54

63

79

19

76

48

34

48

60

48

25

60

63

54

63

54

25

58

48

58

25

46

24

55

59

46

59

47

18

75

66

75

91

66

62

59

27

66

27

18

62

47

75

18

79

75

62

47

62

46

62

52

75

52

62

75

79

18

91

75

47

66

27

66

27

46

59

46

24

59

62

52

62

52

24

55

46

55

24

28

23

54

58

28

58

46

14

72

58

72

74

58

63

58

61

58

26

58

26

14

50

61

46

74

14

76

74

80

61

46

61

28

61

80

61

49

74

49

59

49

80

61

59

72

76

14

50

58

63

80

59

74

46

58

26

58

26

28

58

28

23

58

61

49

61

80

61

49

23

54

28

54

23

27

21

50

50 50

57

27

57

45

13

71

27

71

73

65

50

66

27

58

57

22

27

22

13

22

63

66

58

45

66

73

13

73

58

45

58

27

58

47

73

65 65

76

47

49

47

60

58

49

71

73

66

13

22

63

50

58

49

73

45

76

27

22

27

22

27

57

27

21

57

58

47

58

47

21

50

27

50

21

26

19

48

48 48

49

26

49

67

43

12

70

26

70

78

66

41

21

38

21

58

26

43

49

19

26

19

12

21

32

62

58

43

58

66

12

70

66

65

46

43

67

43

26

43

46

43

42

66

41

65

41

69

78

42

12

42

22

46

43

12

78

70

58

12

21

32

62

21

38

46

12

62

66

43

62

69

26

19

26

19

67

26

49

26

19

49

43

42

43

46

43

42

19

48

26

48

19

25

16

38

38 38

40

25

40

66

28

11

69

21

69

75

58

65

40

18

32

18

22

21

63

36

42

40

12

21

12

11

18

31

36

50

22

42

58

28

22

65

58

11

68

58

41

40

44

42

28

66

28

42

25

42

44

42

27

65 65

58

40

41 41

41

40

49

75

27

11

27

18

44

42

11

75

69

68

58

36

22

11

18

31

50

18

32

44

11

58

50

58

28

50

36

63

63 49

49

21

12

21

12

66

25

40

25

16

40

42

27

42

44

42

27

16

38

25

38

16

24

13

36

36 36

8

24

8

57

8

10

58

19

58

74

48

39

16

31

16

19

33

35

27

8

11

19

11

10

16

35

19

27

50

8

19

39

48

10

58

48

40

39

8

27

8

57

8

27

24

27

8

27

8

40 40

48

39

40 40

40

39

8

74

8

27

8

74

58

50

35

19

10

16

35

16

31

8

50

35

48

8

35

33

8

19

11

19

11

57

24

8

24

13

8

27

8

27

8

27

8

13

36

24

36

13

8

8 8

7

8

7

8

7

8

7

8

7

8

7

8

7

8

7

8

7

8

7

8 8

8

8 8

8

7

8

7

8

7

8

7

8 8 8

8

7

8

8 7

7

8

7

8

7

8

7

8

7

8

7

8

http://24hcongnghe.org

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Frame holes

TM Hole

Chassis GNDs

Thermal Module Holes

Bottom Left GPU

Left CPU TM Hole

RAM door (Torx) holes

Chassis connection to be made at the mounting hole east of the LVDS connector

Right CPU

Top CPU TM "Hole"

Add 8 blind vias per side to GND

Digital Ground

Top Right GPU

GND_CHASSIS_BATTCONN_HOLE (to the left of DIMM cutout near board edge)

GND_CHASSIS_RIGHT_FAN_NOTCH (to the left of small well on lower board edge near USB)

All holes are plated through holes with two exceptions:

195R106

ZT0955

1

195R106

ZT0965

1

235R126

ZT0930

235R126

ZT0935

1

SHLD-SM-LF

OG-503040

SH0925

1 2 3

195R106

ZT0900

1

195R106

ZT0901

1

195R106

ZT0985

1

195R106

ZT0975

1

195R106

ZT0970

1

195R106

ZT0980

1

SYNC_DATE=08/23/2006

051-7261

10.0.0

92

9

SYNC_MASTER=(T9_MLB)

Signal Aliases

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.25mm VOLTAGE=0V

GND

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.25mm VOLTAGE=0V

GND

MIN_NECK_WIDTH=0.25mm VOLTAGE=0V

MIN_LINE_WIDTH=0.6mm

GND

GND_CHASSIS_RTIO

MIN_NECK_WIDTH=0.25 mm MAKE_BASE=TRUE

VOLTAGE=0V

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=0V

GND

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25mm

GND

MIN_LINE_WIDTH=0.6mm VOLTAGE=0V

VOLTAGE=0V

GND

MIN_NECK_WIDTH=0.25mm

MIN_LINE_WIDTH=0.6mm

VOLTAGE=0V

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.25mm

GND

MAKE_BASE=TRUE

GND

MIN_NECK_WIDTH=0.25mm VOLTAGE=0V

MIN_LINE_WIDTH=0.6mm

GND

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.25mm VOLTAGE=0V

GFXIMVP6_VID<4..0>

MAKE_BASE=TRUE

PM_SB_PWROK

MAKE_BASE=TRUE

VR_PWRGOOD_DELAY

MAKE_BASE=TRUE

PEG_CLK100M_GPU_N

PEG_CLK100M_GPU_P

GND_CHASSIS_INVERTER

TP_MEM_A_A<15>

MAKE_BASE=TRUE

GND_CHASSIS_INVERTER

TP_MEM_B_A<15>

TP_MEM_A_A<15>

VR_PWRGOOD_DELAY

PM_SB_PWROK

GND_CHASSIS_RTIO

SMC_SMS_INT

MAKE_BASE=TRUE

GND_CHASSIS_RTIO

PM_ALL_NBGFX_PGOOD

PLT_RST_L

GFX_VR_EN

SMC_SMS_INT

PEG_CLK100M_GPU_P

MAKE_BASE=TRUE

SMC_ENRGYSTR_LDO_EN

GFX_VID<4..0>

PM_ALL_NBGFX_PGOOD

MAKE_BASE=TRUE

GFX_VR_EN

MAKE_BASE=TRUE

PEG_CLK100M_GPU_N

GND_CHASSIS_INVERTER

MAKE_BASE=TRUE

VOLTAGE=0V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

GND_CHASSIS_RTIO

PLT_RST_L SMC_ENRGYSTR_LDO_EN

TP_MEM_B_A<15>

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6mm VOLTAGE=0V

GND

MIN_NECK_WIDTH=0.2mm

81 81

78

59

88

82

59

78

79

88

82

78

79

43

28

68

80

28

43

28

68

67

68

80

43

28

67

41

25

16

30

44

16

25

41

55

41

79

24

60

55

30

46

79

60

30

44

41

24

46

37

9

29

9

31

9

32

31

9

37

45

37

60

9

16

45

29

45

60

16

29

9

37

9

45

32

9

60

7

9

7

9

7

9

7

9

7

9

16

9

7

9

7

9

http://24hcongnghe.org

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

IN IN IN

IN

OUT

IN

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT

OUT

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI

BI BI BI

BI

BI BI

BI BI BI BI BI

BI

OUT

IN

IN IN IN IN IN

IN IN

OUT

IN IN

IN

IN IN

IN

OUT

BI BI BI BI

LOCK*

INIT*

A20M*

A6*

A3* A4*

A14*

A16*

REQ0* REQ1* REQ2* REQ3* REQ4*

BCLK1

BCLK0

THERMTRIP*

THERMDA

PROCHOT*

DBR*

TRST*

TMS

TDO

TDI

TCK

PREQ*

PRDY*

BPM3*

BPM2*

BPM1*

BPM0*

HITM*

HIT*

TRDY*

RS2*

RS1*

RS0*

RESET*

IERR*

BR0*

DBSY*

DRDY*

DEFER*

BNR*

RSVD9

RSVD8

RSVD7

RSVD6

RSVD5

RSVD4

RSVD3

RSVD2

RSVD1

RSVD0

SMI*

LINT1

LINT0

STPCLK*

FERR*

ADSTB1*

A35*

A34*

A33*

A32*

A31*

A30*

A29*

A28*

A19*

A18*

A17*

ADSTB0*

A13*

A12*

BPRI*

A20* A21* A22* A23* A24*

A26* A27*

A9*

A8*

A7*

A11*

A25*

THERMDC

IGNNE*

ADS*

A10*

A15*

A5*

NC

1 OF 4

CONTROL

THERMAL

XDP/ITP SIGNALS

H CLK

RESERVED

ADDR GROUP0ADDR GROUP1

ICH

DINV1*

D31*

D30*

D25*

D11* D12* D13* D14*

DSTBP0* DINV0*

D9*

D8*

D7*

D6*

D19*

D18*

DATBP1*

D0*

D32* D1* D2*

D5*

D16*

D20* D21* D22* D23* D24*

D26* D27* D28* D29*

DSTBN1*

GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6

BSEL0 BSEL1 BSEL2

D33*

D34*

D35*

D36*

D37*

D38*

D39*

D40*

D41*

D42*

D43*

D44*

D45*

D46*

D47*

DSTBN2* DSTBP2*

DINV2*

D48*

D49*

D50*

D51*

D52*

D53*

D54*

D55*

D56*

D57*

D58*

D59*

D60*

D61*

D62*

D63*

DSTBN3* DSTBP3*

DINV3*

COMP0 COMP1 COMP2 COMP3

DPRSTP*

DPSLP*

DPWR*

PWRGOOD

SLP*

PSI*

D17*

D4*

D3*

DSTBN0*

D15*

D10*

2 OF 4

DATA GRP 3 DATA GRP 2

MISC

DATA GRP 0DATA GRP 1

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NC

LAYOUT NOTE:

MAKE TRACE LENGTH SHORTER THAN 0.5".

COMP0,2 CONNECT WITH ZO=27.4OHM,

MAKE TRACE LENGTH SHORTER THAN 0.5".

COMP1,3 CONNECT WITH ZO=55OHM,

PM_THRMTRIP# SHOULD CONNECT TO ICH AND GMCH WITHOUT T (NO STUB)

0.1" AWAY

PLACE TESTPOINT ON FSB_IERR_L WITH A GND

0.5" MAX LENGTH FOR CPU_GTLREF

REFERENCED TO GND

PLACE C1000 CLOSE TO CPU_TEST4 PIN. MAKE SURE CPU_TEST4 IS

402

MF-LF

54.9

1/16W

1%

R1002

1

2

MF-LF 402

1/16W

5%

68

R1004

1

2

402

1K

MF-LF

1%

1/16W

R1005

1

2

402

1/16W

2.0K

MF-LF

1%

R1006

1

2

402

54.9

1/16W MF-LF

1%

R1019

402

1%

MF-LF

1/16W

27.4

R1018

402

54.9

1/16W MF-LF

1%

R1017

402

27.4

1/16W MF-LF

1%

R1016

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

16 23 59 83

7

23 83

7

14 83

7

14 83

28 59

7

13 23 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

30 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

13 83

10 13 83

13 28

46 59 83

51

16 23 46 83

23 47 83

7

13 14 83

14 83

10 13 83

51 91

7

29 30 88

7

29 30 88

23 83

7

23 83

402

NOSTUFF

5%

MF-LF

1/16W

0

R1030

402

NOSTUFF

1K

MF-LF

5% 1/16W

R1007

1

2

402

54.9

MF-LF

1%

1/16W

R1003

1

2

402

54.9

1/16W MF-LF

1%

R1020

402

1%

MF-LF

1/16W

54.9

R1021

402

1%

MF-LF

1/16W

54.9

R1022

14 83

402

1%

MF-LF

1/16W

649

R1023

402

MF-LF

NOSTUFF

1K

5%

1/16W

R1012

1

2

402

16V

10%

0.1uF

NOSTUFF

X5R

C1000

1

2

FCBGA

MEROM

OMIT

U1000

N3 P5 P2 L2 P4 P1 R1

Y2 U5 R3 W6

A6

U4 Y5 U1 R4 T5 T3 W2 W5 Y4

J4

U2 V4

W3 AA4 AB2 AA3

L5

L4

K5

M3

N2

J1

H1

M1

V1

A22 A21

E2

AD4 AD3 AD1 AC4

G5

F1

C20

E1

H5 F21

A5

G6 E4

D20

C4

B3

C6

B4

H4

B1

AC2 AC1

D21

K3

H2

K2

J3

L1

C1 F3 F4 G3

M4

N5

T2

V3

B2

C3

D2 D22

D3

F6

A3

D5

AC5 AA6 AB3

A24 B25

C7

AB5

G2

AB6

FCBGA

MEROM

OMIT

U1000

B22 B23 C21

R26 U26 AA1 Y1

E22 F24

J24 J23 H22 F26 K22 H23

N22 K25 P26 R23

E26

L23 M24 L22 M23 P25 P23 P22 T24 R24 L25

G22

T25 N25

Y22 AB24 V24 V26 V23 T22 U25 U23

F23

Y25 W22 Y23 W24 W25 AA23 AA24 AB25

AE24 AD24

G25

AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21

E25

AC22 AD23 AF22 AC23

E23 K24 G24

M26

H25

N24

U22

AC20

E5 B5 D24

J26

L26

Y26

AE25

H26

AA26

AF24

AD26

AE6

D6 D7

C23 D25 C24

AF26

AF1 A26

402

PLACEMENT_NOTE=Place R1024 near ITP connector (if present)

54.9

1/16W MF-LF

1%

R1024

CPU FSB

10

10.0.0

051-7261

92

SYNC_MASTER=T9_NOME

SYNC_DATE=01/25/2007

XDP_BPM_L<2>

XDP_BPM_L<5> XDP_TCK

CPU_THERMD_N

PP1V05_S0

XDP_TRST_L

XDP_TDI

XDP_TMS

XDP_TDO

XDP_TCK

FSB_A_L<5>

FSB_A_L<15>

FSB_A_L<10>

FSB_ADS_L

CPU_IGNNE_L

FSB_A_L<25>

FSB_A_L<11>

FSB_A_L<7> FSB_A_L<8> FSB_A_L<9>

FSB_A_L<27>

FSB_A_L<26>

FSB_A_L<24>

FSB_A_L<23>

FSB_A_L<22>

FSB_A_L<21>

FSB_A_L<20>

FSB_BPRI_L

FSB_A_L<12> FSB_A_L<13>

FSB_ADSTB_L<0>

FSB_A_L<17> FSB_A_L<18> FSB_A_L<19>

FSB_A_L<28> FSB_A_L<29> FSB_A_L<30> FSB_A_L<31> FSB_A_L<32> FSB_A_L<33> FSB_A_L<34> FSB_A_L<35> FSB_ADSTB_L<1>

CPU_FERR_L

CPU_STPCLK_L CPU_INTR CPU_NMI CPU_SMI_L

TP_CPU_RSVD0 TP_CPU_RSVD1 TP_CPU_RSVD2 TP_CPU_RSVD3 TP_CPU_RSVD4 TP_CPU_RSVD5 TP_CPU_RSVD6 TP_CPU_RSVD7 TP_CPU_RSVD8 TP_CPU_RSVD9

FSB_BNR_L

FSB_DEFER_L FSB_DRDY_L FSB_DBSY_L

FSB_BREQ0_L

CPU_IERR_L

FSB_CPURST_L FSB_RS_L<0> FSB_RS_L<1> FSB_RS_L<2> FSB_TRDY_L

FSB_HIT_L FSB_HITM_L

XDP_BPM_L<0> XDP_BPM_L<1>

XDP_BPM_L<3> XDP_BPM_L<4>

XDP_TDI XDP_TDO XDP_TMS XDP_TRST_L XDP_DBRESET_L

CPU_PROCHOT_L CPU_THERMD_P

PM_THRMTRIP_L

FSB_CLK_CPU_P FSB_CLK_CPU_N

FSB_REQ_L<4>

FSB_REQ_L<3>

FSB_REQ_L<2>

FSB_REQ_L<1>

FSB_REQ_L<0>

FSB_A_L<16>

FSB_A_L<14>

FSB_A_L<4>

FSB_A_L<3>

FSB_A_L<6>

CPU_A20M_L

CPU_INIT_L

FSB_LOCK_L

FSB_D_L<10>

FSB_D_L<15> FSB_DSTB_L_N<0>

FSB_D_L<3> FSB_D_L<4>

FSB_D_L<17>

CPU_PSI_L

FSB_CPUSLP_L

CPU_PWRGD

FSB_DPWR_L

CPU_DPSLP_L

CPU_DPRSTP_L

CPU_COMP<3>

CPU_COMP<2>

CPU_COMP<1>

CPU_COMP<0>

FSB_DINV_L<3>

FSB_DSTB_L_P<3>

FSB_DSTB_L_N<3>

FSB_D_L<63>

FSB_D_L<62>

FSB_D_L<61>

FSB_D_L<60>

FSB_D_L<59>

FSB_D_L<58>

FSB_D_L<57>

FSB_D_L<56>

FSB_D_L<55>

FSB_D_L<54>

FSB_D_L<53>

FSB_D_L<52>

FSB_D_L<51>

FSB_D_L<50>

FSB_D_L<49>

FSB_D_L<48>

FSB_DINV_L<2>

FSB_DSTB_L_P<2>

FSB_DSTB_L_N<2>

FSB_D_L<47>

FSB_D_L<46>

FSB_D_L<45>

FSB_D_L<44>

FSB_D_L<43>

FSB_D_L<42>

FSB_D_L<41>

FSB_D_L<40>

FSB_D_L<39>

FSB_D_L<38>

FSB_D_L<37>

FSB_D_L<36>

FSB_D_L<35>

FSB_D_L<34>

FSB_D_L<33>

CPU_BSEL<2>

CPU_BSEL<1>

CPU_BSEL<0>

TP_CPU_TEST6

CPU_TEST4

TP_CPU_TEST3

CPU_TEST2

CPU_TEST1

CPU_GTLREF

FSB_DSTB_L_N<1>

FSB_D_L<29>

FSB_D_L<28>

FSB_D_L<27>

FSB_D_L<26>

FSB_D_L<24>

FSB_D_L<23>

FSB_D_L<22>

FSB_D_L<21>

FSB_D_L<20>

FSB_D_L<16>

FSB_D_L<5>

FSB_D_L<2>

FSB_D_L<1>

FSB_D_L<32>

FSB_D_L<0>

FSB_DSTB_L_P<1>

FSB_D_L<18> FSB_D_L<19>

FSB_D_L<6> FSB_D_L<7> FSB_D_L<8> FSB_D_L<9>

FSB_DINV_L<0>

FSB_DSTB_L_P<0>

FSB_D_L<14>

FSB_D_L<13>

FSB_D_L<12>

FSB_D_L<11>

FSB_D_L<25>

FSB_D_L<30> FSB_D_L<31>

FSB_DINV_L<1>

TP_CPU_TEST5

62

50

46

30

27

26

23

21

19

18

14

13

12

11

83

10

13

8

10

83

83 83

http://24hcongnghe.org

OUT OUT OUT OUT OUT OUT OUT

OUT

VCC

VSSSENSE

VCCSENSE

VID6

VID5

VID4

VID3

VID2

VID1

VID0

VCCA

VCCP

VCC

3 OF 4

VSS VSS

4 OF 4

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

TBD A (Deep Sleep LFM)

TBD A (Sleep LFM)

TBD A (Auto-Halt/Stop-Grant LFM)

Current numbers from Merom for Santa Rosa EMTS, doc #22221.

TBD A (LFM)

TBD A (HFM)

TBD A (Auto-Halt/Stop-Grant HFM)

TBD A (Sleep HFM)

TBD A (Deep Sleep HFM)

TBD A (Deeper Sleep) TBD A (Enhanced Deeper Sleep)TBD A (Enhanced Deeper Sleep)

TBD A (Deeper Sleep)

TBD A (Deep Sleep SuperLFM)

TBD A (Deep Sleep HFM)

TBD A (Sleep SuperLFM)

TBD A (Sleep HFM)

TBD A (Auto-Halt/Stop-Grant SuperLFM)

TBD A (Auto-Halt/Stop-Grant HFM)

TBD A (SuperLFM)

18.7 A (LFM)

21.0 A (HFM)

23.0 A (Design Target) 17.0 A (Design Target)

Ultra Low Voltage:Low Voltage:

(CPU INTERNAL PLL POWER 1.5V)

(CPU IO POWER 1.05V)

130 mA

(CPU CORE POWER)

Standard Voltage:

44.0 A (Design Target)

41.0 A (HFM)

16.8 A (Sleep SuperLFM)

16.0 A (Deep Sleep SuperLFM)

4500 mA (before VCC stable) 2500 mA (after VCC stable)

9.4 A (Enhanced Deeper Sleep)

25.5 A (SuperLFM)

30.4 A (LFM)

27.4 A (Auto-Halt/Stop-Grant HFM)

17.0 A (Auto-Halt/Stop-Grant SuperLFM)

27.4 A (Sleep HFM)

25.0 A (Deep Sleep HFM)

11.5 A (Deeper Sleep)

12 83

PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.

MF-LF 402

100

1% 1/16W

R1101

1

2

12 83

59 83

FCBGA

MEROM

OMIT

U1000

A7 A9

B9 B10 B12 B14 B15 B17 B18 B20

C9 C10

A10

C12 C13 C15 C17 C18

D9 D10 D12 D14 D15

A12

D17 D18

E7

E9 E10 E12 E13 E15 E17 E18

A13

E20

F7

F9 F10 F12 F14 F15 F17 F18 F20

A15

AA7 AA9

AA10 AA12 AA13 AA15 AA17 AA18 AA20

AB9

A17

AC10 AB10 AB12 AB14 AB15 AB17 AB18

AB20 AB7 AC7

A18

AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12

A20

AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17

B7

AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20

B26 C26

G21 V6

R21 R6 T21 T6 V21 W21

J6 K6 M6 J21 K21 M21 N21 N6

AF7

AD6 AF5 AE5 AF4 AE3 AF3 AE2

AE7

FCBGA

MEROM

OMIT

U1000

A4 A8

B11

W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5

B13

AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8

B16

AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11

B19

AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13

B21

AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16

B24

AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19

C5

AF21 A25 AF25

C8 C11 C14

A11

C16 C19

C2 C22 C25

D1

D4

D8 D11 D13

A14

D16 D19 D23 D26

E3

E6

E8 E11 E14 E16

A16

E19 E21 E24

F5

F8 F11 F13 F16 F19

F2

A19

F22 F25

G4

G1 G23 G26

H3

H6 H21 H24

A23

J2

J5 J22 J25

K1

K4 K23 K26

L3

L6

AF2

L21 L24

M2

M5 M22 M25

N1

N4 N23 N26

B6

P3

P6 P21 P24 R2 R5 R22 R25 T1 T4

B8

T23 T26 U3 U6 U21 U24 V2 V5 V22 V25

MF-LF 402

PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.

1/16W

1%

100

R1100

1

2

SYNC_DATE=01/25/2007

SYNC_MASTER=T9_NOME

CPU Power & Ground

051-7261

10.0.0

11 92

CPU_VID<2> CPU_VID<3>

CPU_VID<5>

PPVCORE_S0_CPU

CPU_VCCSENSE_N

CPU_VCCSENSE_P

CPU_VID<0> CPU_VID<1>

PPVCORE_S0_CPU

CPU_VID<6>

CPU_VID<4>

PP1V5_S0

PP1V05_S0

62 50 46 30

27 26

91

23

64

21

34

19

59

27

18

49

26

14

12

22

13

11

19

12

8

12

10

7

8

http://24hcongnghe.org

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

4x 330uF, 20x 22uF 0805

CPU VCORE VID CONNECTIONS

CPU VCORE HF AND BULK DECOUPLING

1x 470uF, 6x 0.1uF 0402

VCCP (CPU I/O) DECOUPLING

1x 10uF, 1x 0.01uF

VCCA (CPU AVdd) DECOUPLING

WF: Consider sharing bulk cap with NB Vtt?

CERM-X5R 805

6.3V

20%

22UF

C1206

1

2

CRITICAL

2.5V TANT

D2T

20%

470UF

C1235

1

2 3

CERM-X5R 805

6.3V

20%

22UF

C1204

1

2

20%

6.3V 805

CERM-X5R

22UF

C1216

1

2

20%

6.3V 805

CERM-X5R

22UF

C1214

1

2

CERM-X5R 805

6.3V

20%

22UF

C1208

1

2

CERM-X5R 805

6.3V

20%

22UF

C1203

1

2

CERM-X5R 805

6.3V

20%

22UF

C1207

1

2

CERM-X5R 805

20%

22UF

6.3V

C1202

1

2

CERM-X5R 805

6.3V

20%

22UF

C1201

1

2

20%

6.3V 805

CERM-X5R

22UF

C1213

1

2

6.3V 805

20% CERM-X5R

22UF

C1212

1

2

20%

6.3V 805

CERM-X5R

22UF

C1211

1

2

805

6.3V

20% CERM-X5R

22UF

C1219

1

2

CERM-X5R

22UF

6.3V 805

20%

C1200

1

2

805

6.3V

20% CERM-X5R

22UF

C1210

1

2

0.1UF

20% CERM

402

10V

C1236

1

2

CERM-X5R 805

6.3V

20%

22UF

C1205

1

2

CERM-X5R 805

6.3V

20%

22UF

C1209

1

2

20%

6.3V 805

CERM-X5R

22UF

C1215

1

2

20%

6.3V 805

CERM-X5R

22UF

C1217

1

2

20% CERM

402

0.1UF

10V

C1237

1

2

20% CERM

402

0.1UF

10V

C1238

1

2

20% CERM

402

0.1UF

10V

C1239

1

2

20% CERM

402

0.1UF

10V

C1240

1

2

20% CERM

402

0.1UF

10V

C1241

1

2

6.3V 805

20% CERM-X5R

22UF

C1218

1

2

PLACEMENT_NOTE=Place near CPU pin B26.

CERM 402

16V

10%

0.01UF

C1281

1

2

X5R

6.3V

20%

10uF

603

C1280

1

2

10%

2.0V

330UF

TANT

D2T

PLACEMENT_NOTE=Place in CPU center cavity.

CRITICAL

C1250

1

2 3

10%

2.0V

330UF

CRITICAL

TANT

D2T

PLACEMENT_NOTE=Place in CPU center cavity.

C1251

1

2 3

2.0V

330UF

CRITICAL

TANT

D2T

10%

PLACEMENT_NOTE=Place in CPU center cavity.

C1252

1

2 3

2.0V

330UF

10%

TANT

D2T

CRITICAL

PLACEMENT_NOTE=Place in CPU center cavity.

C1253

1

2 3

CPU Decoupling & VID

SYNC_MASTER=M75_MLB

9212

10.0.0

SYNC_DATE=12/07/2006

051-7261

PP1V05_S0

PP1V5_S0

IMVP6_VID<0..6>

CPU_VID<0..6>

MAKE_BASE=TRUE

PPVCORE_S0_CPU

62 50 46 30 27

26 23

91

21

64

19

34

18

27

14

26

59

13

22

49

11

19

83

11

10

11

59

83

8

7

11

7

http://24hcongnghe.org

IN

BI

OUT

OUT IN

BI

IN

IN IN

OUT

IN

OUT OUT

OUT

IN

BI

IN

BI

IN

IN IN

IN

IN IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

998-1571

OBSDATA_B0

(OBSDATA_A1)

(OBSDATA_A0)

OBSDATA_C1

SB OC[3]#

OBSFN_C0

NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.

Use with 920-0451 adapter board to support CPU, NB & SB debugging.

Mini-XDP Connector

(VCC_OBS_CD)

OBSDATA_D3

SB GPIO[8]

NB CFG[8]

NB CFG[3]

NB CFG[7]

NB CFG[6]

NB CFG[5]

NB CFG[4]

NB CFG[1]

NB CFG[0] NB CFG[2]

SB OC[4]#

(OBSDATA_A2)

TCK0

(OBSDATA_A3)

NC

OBSFN_C1

OBSDATA_C0

OBSDATA_C2

TDO

TDI

ITPCLK#/HOOK5

RESET#/HOOK6 DBR#/HOOK7

SB OC[0]#

OBSDATA_C3

SB OC[1]#

SB OC[2]#

SB OC[5]#

SB OC[7]#

TCK1

SCL

SDA

OBSDATA_B1

OBSDATA_A1

OBSFN_A1

TRSTn

HOOK3

HOOK2

VCC_OBS_AB

HOOK1

TMS

OBSDATA_D1

OBSDATA_D0

OBSDATA_A3

OBSDATA_B3

OBSDATA_B2

OBSFN_A0

OBSDATA_A0

XDP_PRESENT#

OBSDATA_D2

ITPCLK/HOOK4

on even-numbered side of J1300

Please avoid any obstructions

Direction of XDP module

PWRGD/HOOK0

OBSDATA_A2

NOTE: This is not the standard XDP pinout.

SB OC[6]#

7

10 23 83

402

MF-LF

1/16W

5%

1K

XDP

R1399

1 2

15

XDP

1/16W

402

MF-LF

1%

54.9

R1315

1

2

402

16V

10%

0.1uF

X5R

XDP

C1300

1

2

MF-LF

10K

5%

XDP

1/16W 402

R1331

1

2

402

MF-LF

10K

5%

1/16W

XDP

R1330

1

2

402

16V

10%

0.1uF

X5R

XDP

C1301

1

2

10 28

10 83

7

10 14 83

10 83

29 30 83 88

24 34

24

24 79

24

24 36

24

24 43

1/16W

402

MF-LF

5%

1K

XDP

R1303

1 2

LTH-030-01-G-D-NOPEGS

CRITICAL

F-ST-SM

XDP_CONN

J1300

1

10

1112 1314 1516 1718 19

2

20

2122 2324 2526 2728 29

3

30

3132 3334 3536 3738 39

4

40

4142 4344 4546 4748 49

5

50

5152 5354 5556 5758 59

6

60

78 9

16 30 83

16

25 45

16

16 30 83

16

eXtended Debug Port (XDP)

SYNC_DATE=01/22/2007

SYNC_MASTER=T9_NOME

13

10.0.0

92

051-7261

PP3V3_S0

SMC_WAKE_SCI_L

NB_CFG<8>

XDP_TMS

XDP_CPURST_L

PM_LATRIGGER_L

FSB_CPURST_L

XDP_TDO XDP_TRST_L

XDP_TCK

XDP_BPM_L<3>

TP_XDP_HOOK3

USB_EXTA_OC_L

SB_GPIO30

XDP_CLK_P

USB_EXTB_OC_L

TP_XDP_HOOK2

WOW_EN

XDP_OBS20

XDP_BPM_L<2>

XDP_BPM_L<0>

NB_BSEL<0> NB_BSEL<1>

NB_CFG<7>

XDP_PWRGDCPU_PWRGD

NB_BSEL<2> NB_CFG<3>

PP1V05_S0

XDP_CLK_N

XDP_TDI

XDP_DBRESET_L

EXTGPU_LVDS_EN

USB_EXTD_OC_L

SB_GPIO40

XDP_BPM_L<5> XDP_BPM_L<4>

LVDS_CTRL_CLK

XDP_BPM_L<1>

LVDS_CTRL_DATA

NB_CFG<4> NB_CFG<5>

NB_CFG<6>

91

81 79 77 76 66 60 59 58 53 52 51 50 48 47 46 42

62

32

50

31

46

30

29

27

28

26

27

23

26

21

25

19

24

18

23

14

21

12

19

11

16

10

8

83

8

http://24hcongnghe.org

BI

BI BI

OUT

BI

BI BI

BI

BI BI BI BI

BI BI

BI

BI BI

BI BI BI BI

BI BI

OUT

BI

OUT

BI BI BI BI BI

BI BI

H_D0*

H_D3*

H_D2*

H_D33* H_D34* H_D35*

H_D1*

H_D4*

H_D10*

H_A4* H_A5* H_A6* H_A7* H_A8*

H_A9* H_A10* H_A11* H_A12* H_A13* H_A14* H_A15* H_A16* H_A17* H_A18* H_A19* H_A20* H_A21* H_A22* H_A23* H_A24* H_A25* H_A26* H_A27* H_A28* H_A29* H_A30* H_A31* H_A32* H_A33* H_A34* H_A35*

H_ADS*

H_ADSTB0* H_ADSTB1*

H_A3*

H_D7* H_D8* H_D9*

H_D11* H_D12* H_D13* H_D14* H_D15* H_D16* H_D17* H_D18* H_D19* H_D20* H_D21* H_D22* H_D23*

H_D25* H_D26* H_D27* H_D28* H_D29* H_D30*

H_D32*

H_D36* H_D37* H_BNR* H_D38*

H_BPRI* H_D39* H_D40*

H_DEFER*

H_D41*

H_DBSY* H_D42* H_D43* H_D44*

H_DPWR* H_D45*

H_DRDY* H_D46* H_HIT* H_D47*

H_HITM* H_D48*

H_LOCK*

H_TRDY*

H_D51* H_D52* H_D53*

H_DINV0*

H_D54*

H_DINV1*

H_D55*

H_DINV2*

H_D56*

H_DINV3*

H_D57* H_D58*

H_DSTBN0*

H_D59*

H_DSTBN1*

H_D60*

H_DSTBN2*

H_D61*

H_DSTBN3*

H_D62* H_D63*

H_DSTBP0* H_DSTBP1*

H_DSTBP2* H_SWING H_RCOMP

H_REQ0* H_SCOMP H_REQ1* H_SCOMP*

H_REQ2*

H_REQ3* H_CPURST*

H_REQ4* H_CPUSLP*

H_RS0* H_RS1*

H_AVREF

H_RS2*

H_DVREF

H_D5* H_D6*

H_D31*

H_BREQ*

H_D24*

H_D49* H_D50*

H_DSTBP3*

HPLL_CLK

HPLL_CLK*

HOST

(1 OF 10)

BI BI BI BI

BI

IN

OUT OUT

BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI

BI BI BI BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

X5R

0.1uF

10% 16V

402

C1425

1

2

2.0K

MF-LF

1%

1/16W

402

R1426

1

2

1K

MF-LF

1%

1/16W

402

R1425

1

2

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

54.9

MF-LF

1% 1/16W

402

R1420

1

2

24.9

MF-LF

1%

1/16W

402

R1415

1

2

221

MF-LF

1%

1/16W

402

R1410

1

2

100

MF-LF

1%

1/16W

402

R1411

1

2

X5R

0.1uF

10% 16V

402

C1410

1

2

7

10 83

OMIT

CRESTLINE

FCBGA

U1400

G17 C14 K16 B13 L16 J17 B14 K19 P15 R17 B16 H20 L19 D17 M17 N16 J19 B18 E19 B17

J13

B15 E17 C18 A19 B19 N19

B11 C11 M11 C15 F16 L13

G12 H17 G20

B9

C8 E8 F12

B6 E5

E2 G2

M10 N12

N9 H5

P13

K9 M2

W10

Y8 V4

G7

M3 J1 N5 N3 W6 W9 N2 Y7 Y9 P4

M6

W3 N1

AD12

AE3 AD9 AC9

AC7 AC14 AD11 AC11

H7

AB2

AD7

AB1

Y3 AC6 AE2 AC5 AG3 AJ9 AH8

H3

AJ14

AE9

AE11 AH12

AJ5 AH5 AJ6 AE7 AJ7 AJ2

G4

AE5 AJ3 AH2

AH13

F3

N8

H2

C10

D6

K5 L2 AD13 AE13

H8 K7

M7 K3 AD2 AH11

L7 K2 AC2 AJ10

A9

E4 C6 G10

C2

M14 E13 A11 H13 B12

E12 D7 D8

W1

W2

B3

B7

AM5 AM7

10 83

7

10 83

54.9

MF-LF

1%

1/16W

402

R1421

1

2

7

10 83

7

29 30 88

7

29 30 88

7

10 13 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

SYNC_DATE=01/25/2007

NB CPU Interface

051-7261

10.0.0

9214

SYNC_MASTER=T9_NOME

PP1V05_S0

FSB_D_L<47>

FSB_D_L<3>

FSB_D_L<2>

FSB_D_L<33> FSB_D_L<34> FSB_D_L<35>

FSB_D_L<1>

FSB_D_L<10>

FSB_D_L<7> FSB_D_L<8> FSB_D_L<9>

FSB_D_L<11>

FSB_D_L<13> FSB_D_L<14> FSB_D_L<15> FSB_D_L<16> FSB_D_L<17> FSB_D_L<18> FSB_D_L<19> FSB_D_L<20> FSB_D_L<21> FSB_D_L<22> FSB_D_L<23>

FSB_D_L<25> FSB_D_L<26> FSB_D_L<27> FSB_D_L<28> FSB_D_L<29> FSB_D_L<30>

FSB_D_L<32>

FSB_D_L<36> FSB_D_L<37>

FSB_D_L<39> FSB_D_L<40>

FSB_D_L<42>

FSB_D_L<44> FSB_D_L<45> FSB_D_L<46>

FSB_D_L<48>

FSB_D_L<51> FSB_D_L<52> FSB_D_L<53> FSB_D_L<54> FSB_D_L<55> FSB_D_L<56> FSB_D_L<57> FSB_D_L<58>

FSB_D_L<60> FSB_D_L<61> FSB_D_L<62> FSB_D_L<63>

NB_FSB_SCOMP NB_FSB_SCOMP_L

FSB_CPURST_L FSB_CPUSLP_L

FSB_D_L<6>

FSB_D_L<31>

FSB_D_L<24>

FSB_D_L<49> FSB_D_L<50>

FSB_D_L<12>

FSB_D_L<43>

FSB_D_L<5>

FSB_D_L<4>

FSB_D_L<0>

FSB_D_L<38>

FSB_D_L<41>

FSB_D_L<59>

NB_FSB_SWING NB_FSB_RCOMP

NB_FSB_VREF

FSB_A_L<3>

FSB_A_L<6>

FSB_A_L<4> FSB_A_L<5>

FSB_A_L<7> FSB_A_L<8> FSB_A_L<9>

FSB_A_L<11>

FSB_A_L<10>

FSB_A_L<12> FSB_A_L<13> FSB_A_L<14> FSB_A_L<15> FSB_A_L<16> FSB_A_L<17> FSB_A_L<18> FSB_A_L<19> FSB_A_L<20> FSB_A_L<21> FSB_A_L<22> FSB_A_L<23> FSB_A_L<24> FSB_A_L<25> FSB_A_L<26> FSB_A_L<27> FSB_A_L<28> FSB_A_L<29>

FSB_A_L<32>

FSB_A_L<30> FSB_A_L<31>

FSB_A_L<33> FSB_A_L<34> FSB_A_L<35>

FSB_ADS_L FSB_ADSTB_L<0> FSB_ADSTB_L<1>

FSB_BPRI_L

FSB_BNR_L

FSB_BREQ0_L FSB_DEFER_L FSB_DBSY_L

FSB_DPWR_L

FSB_CLK_NB_P FSB_CLK_NB_N

FSB_DRDY_L FSB_HIT_L FSB_HITM_L

FSB_TRDY_L

FSB_LOCK_L

FSB_DINV_L<0> FSB_DINV_L<1> FSB_DINV_L<2> FSB_DINV_L<3>

FSB_DSTB_L_N<0> FSB_DSTB_L_N<1> FSB_DSTB_L_N<2> FSB_DSTB_L_N<3>

FSB_DSTB_L_P<0> FSB_DSTB_L_P<1> FSB_DSTB_L_P<2> FSB_DSTB_L_P<3>

FSB_REQ_L<0> FSB_REQ_L<1> FSB_REQ_L<2> FSB_REQ_L<3> FSB_REQ_L<4>

FSB_RS_L<1>

FSB_RS_L<0>

FSB_RS_L<2>

62 50 46 30 27

26 23 21 19 18 13 12 11 10

8

http://24hcongnghe.org

IN

OUT

IN

OUT OUT OUT

IN IN

OUT OUT OUT

OUT

IN

OUT

BI

L_BKLT_CTRL

L_VDD_EN

PEG_TX15*

PEG_TX14*

PEG_TX13*

PEG_TX12*

PEG_TX11*

PEG_TX10*

PEG_TX9*

PEG_TX8*

PEG_TX7*

PEG_TX6*

PEG_TX5*

PEG_TX4*

PEG_TX3*

PEG_TX2*

PEG_TX1*

PEG_TX0*

PEG_TX15

PEG_TX14

PEG_TX13

PEG_TX12

PEG_TX11

PEG_TX10

PEG_TX9

PEG_TX8

PEG_TX7

PEG_TX6

PEG_TX5

PEG_TX4

PEG_TX3

PEG_TX2

PEG_TX1

PEG_TX0

PEG_RX14

PEG_RX15*

PEG_RX14*

PEG_RX13*

PEG_RX12*

PEG_RX11*

PEG_RX15

PEG_RX13

PEG_RX12

PEG_RX11

PEG_RX10

PEG_RX9

PEG_RX8

PEG_RX7

PEG_RX6

PEG_RX5

PEG_RX4

PEG_RX3

PEG_RX2

PEG_RX1

PEG_RX0

PEG_RX10*

PEG_RX9*

PEG_RX8*

PEG_RX7*

PEG_RX6*

PEG_RX5*

PEG_RX4*

PEG_RX3*

PEG_RX2*

PEG_RX1*

PEG_RX0*

PEG_COMPI PEG_COMPO

CRT_DDC_DATA

L_CTRL_DATA

LVDSB_DATA1 LVDSB_DATA2

LVDSB_DATA0

LVDSB_DATA2*

LVDSB_DATA1*

LVDSB_DATA0*

LVDSA_DATA2

LVDSA_DATA0 LVDSA_DATA1

LVDSB_CLK*

LVDS_VREFL

LVDS_IBG

TVC_RTN

TVA_RTN TVB_RTN

TVC_DAC

TVB_DAC

TVA_DAC

CRT_RED*

CRT_RED

CRT_GREEN*

CRT_GREEN

CRT_BLUE*

CRT_BLUE

CRT_VSYNC

CRT_TVO_IREF

CRT_HSYNC

CRT_DDC_CLK

L_BKLT_EN

L_DDC_CLK

TV_DCONSEL0 TV_DCONSEL1

LVDSA_DATA2*

L_DDC_DATA

LVDSA_DATA1*

LVDSA_DATA0*

LVDSB_CLK

LVDSA_CLK

LVDSA_CLK*

LVDS_VREFH

L_CTRL_CLK

LVDS_VBG

VGA

TV

LVDS

(3 OF 10)

PCI-EXPRESS GRAPHICS

BI

OUT

IN

IN IN

IN

IN IN IN IN IN

IN

OUT

IN

OUT

IN

OUT

IN

OUT

OUT OUT

IN

BI BI

OUT OUT OUT OUT

OUT OUT

IN

OUT

OUT OUT

OUT

OUT OUT

OUT

OUT OUT

IN

OUT OUT OUT

OUT

BI BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

SDVO_FLDSTALL#

SDVO Alternate Function

SDVO_TVCLKIN# SDVO_INT#

SDVO_TVCLKIN SDVO_INT SDVO_FLDSTALL

SDVOB_GREEN

SDVOB_RED

SDVOC_CLKN

SDVOC_BLUE#

SDVOC_GREEN#

SDVOC_RED#

SDVOB_CLKN

SDVOB_BLUE#

SDVOB_GREEN#

SDVOB_RED#

SDVOB_CLKP

SDVOB_BLUE

SDVOC_CLKP

SDVOC_BLUE

SDVOC_GREEN

SDVOC_RED

If SDVO is used, VCCD_LVDS must remain powered with proper

LVDS Disable

Tie VCC_TX_LVDS and VCCA_LVDS to GND.

TVDAC rails. VCCA_TVx_DAC and VCCA_DAC_BG can

should connect to GND through 75-ohm resistors.

Component: DACA, DACB & DACC

Composite: DACA only

TV-Out Signal Usage:

Can tie the following rails to GND:

VSYNC and CRT_TVO_IREF to GND.

CRT Disable / TV-Out Enable

TV-Out Disable / CRT Enable Tie TVx_DAC and TVx_RTN to GND. Must power all

Leave GFX_VID<3..0> and GFX_VR_EN as NC.

Tie VCC_AXG and VCC_AXG_NCTF to GND.

Tie VCCA_DPLLA and VCCA_DPLLB to VCC (VCore).

Tie DPLL_REF_CLK and DPLL_REF_SSCLK to GND.

Can also tie CRT_DDC_*, L_CTRL_*, L_DDC_*, SDVO_CTRL_* and TV_DCONSELx to GND.

Follow instructions for LVDS and CRT & TV-Out Disable above.

Internal Graphics Disable

and filtered at all times!

NOTE: Must keep VDDC_TVDAC powered

VCCD_CRT, VCCD_QDAC and VCC_SYNC.

VCCA_CRT_DAC, VCCA_DAC_BG, VCCA_TVx_DAC,

omit filtering components. Unused DAC outputs

All CRT/TVDAC rails must be powered. All

CRT & TV-Out Disable Tie TVx_DAC, TVx_RTN, R/R#/G/G#/B/B#, HSYNC,

Tie R/R#/G/G#/B/B#, HSYNC and VSYNC to GND.

share filtering with VCCA_CRT_DAC.

Unused DAC outputs must remain powered, but can

S-Video: DACB & DACC only

Can leave all signals NC if LVDS is not implemented.

decoupling. Otherwise, tie VCCD_LVDS to GND also.

Tie DPLL_REF_CLK* and DPLL_REF_SSCLK* to VCC (VCore).

rails must be filtered except for VCCA_CRT.

68 84

402

MF-LF

1/16W

1%

24.9

R1510

1

2

79

68 84

22 84

OMIT

CRESTLINE

FCBGA

U1400

H32 G32

K33 G35

K29 J29

F33

F29 E29

C32 E33

J40 H39 E39 E40 C37 D35 K40

L41 L43 N41 N40

C45

D46

G50

G51

E50

E51

F48

F49

E42

D44

E44

G44

A47

B47

A45

B45

N43 M43

J50

J51

L50

L51

AC45

AD44

AC41

AD40

AH47

AG46

AG49

AH49

AH45

AG45

AG42

AG41

M47

N47

U44

T45

T49

T50

T41

U40

W45

Y44

W41

Y40

AB50

AB51

Y48

W49

M45

N45

T38

U39

AD47

AC46

AC50

AC49

AD43

AC42

AG39

AH39

AE50

AE49

AH43

AH44

T46

U47

N50

N51

R51

R50

U43

T42

W42

Y43

Y47

W46

Y39

W38

AC38

AD39

M35 P33

E27

F27

G27

J27

K27

L27

13

68 84

79

68 84

77 79

79 84

68 84

79 84

68 84

SYNC_DATE=01/25/2007

15 92

10.0.0

051-7261

NB PEG / Video Interfaces

SYNC_MASTER=T9_NOME

GND

LVDS_B_DATA_N<2>

LVDS_B_DATA_N<1>

LVDS_CTRL_DATA

LVDS_CTRL_CLK

TP_LVDS_VBG

PEG_D2R_P<9>

PEG_D2R_P<11>

PEG_D2R_P<10>

PP1V05_S0_NB_VCCPEG

PEG_D2R_N<1>

PEG_D2R_N<6>

GND

LVDS_A_CLK_N LVDS_A_CLK_P

LVDS_B_CLK_P

LVDS_A_DATA_N<0> LVDS_A_DATA_N<1>

LVDS_CONN_DDC_DATA

LVDS_A_DATA_N<2>

GND

LVDS_CONN_DDC_CLK

LVDS_BKLT_EN

GND

GND GND GND

GND GND GND GND GND GND

GND

LVDS_IBG

GND

LVDS_B_CLK_N

LVDS_A_DATA_P<1>

LVDS_A_DATA_P<0>

LVDS_A_DATA_P<2>

LVDS_B_DATA_N<0>

LVDS_B_DATA_P<0>

LVDS_B_DATA_P<2>

LVDS_B_DATA_P<1>

GND

PEG_COMP

PEG_D2R_N<0>

PEG_D2R_N<2> PEG_D2R_N<3> PEG_D2R_N<4> PEG_D2R_N<5>

PEG_D2R_N<7> PEG_D2R_N<8> PEG_D2R_N<9> PEG_D2R_N<10>

PEG_D2R_P<0> PEG_D2R_P<1> PEG_D2R_P<2> PEG_D2R_P<3> PEG_D2R_P<4> PEG_D2R_P<5> PEG_D2R_P<6> PEG_D2R_P<7> PEG_D2R_P<8>

PEG_D2R_P<12> PEG_D2R_P<13>

PEG_D2R_P<15>

PEG_D2R_N<11> PEG_D2R_N<12> PEG_D2R_N<13> PEG_D2R_N<14> PEG_D2R_N<15>

PEG_D2R_P<14>

PEG_R2D_C_P<0> PEG_R2D_C_P<1> PEG_R2D_C_P<2> PEG_R2D_C_P<3> PEG_R2D_C_P<4> PEG_R2D_C_P<5> PEG_R2D_C_P<6> PEG_R2D_C_P<7> PEG_R2D_C_P<8> PEG_R2D_C_P<9> PEG_R2D_C_P<10> PEG_R2D_C_P<11> PEG_R2D_C_P<12> PEG_R2D_C_P<13> PEG_R2D_C_P<14> PEG_R2D_C_P<15>

PEG_R2D_C_N<0> PEG_R2D_C_N<1> PEG_R2D_C_N<2> PEG_R2D_C_N<3> PEG_R2D_C_N<4> PEG_R2D_C_N<5> PEG_R2D_C_N<6> PEG_R2D_C_N<7> PEG_R2D_C_N<8> PEG_R2D_C_N<9> PEG_R2D_C_N<10> PEG_R2D_C_N<11> PEG_R2D_C_N<12> PEG_R2D_C_N<13> PEG_R2D_C_N<14> PEG_R2D_C_N<15>

LVDS_VDD_EN

LVDS_BKLT_CTL

21 19

http://24hcongnghe.org

IN

CLKREQ*

NC1

NC8

CL_CLK

CL_PWROK

CL_RST*

RSVD6

THERMTRIP*

PM_BM_BUSY*

RSVD4

RSVD3

RSVD7

SM_CKE1

SM_CK0*

SM_CKE0

SM_ODT0

SM_ODT2

SM_RCOMP

SM_RCOMP*

SM_VREF0 SM_VREF1

SM_RCOMP_VOL

SM_CS1*

SM_CS0*

RSVD14

RSVD11

RSVD10

RSVD9

RSVD5

RSVD8

RSVD2

DPLL_REF_CLK*

DPLL_REF_SSCLK

PEG_CLK

DMI_RXN1

DMI_RXN0

DMI_RXN3

DMI_RXN2

DMI_RXP0 DMI_RXP1 DMI_RXP2

DMI_TXN0

DMI_RXP3

DMI_TXN2

DMI_TXN1

DMI_TXP0

DMI_TXN3

DMI_TXP1 DMI_TXP2 DMI_TXP3

PEG_CLK*

RSVD12

CL_DATA

CL_VREF

SDVO_CTRL_CLK

SDVO_CTRL_DATA

ICH_SYNC*

TEST1 TEST2

GFX_VID0 GFX_VID1 GFX_VID2

GFX_VR_EN

GFX_VID3

RSVD20 RSVD21

RSVD24 RSVD25

RSVD27

RSVD34 RSVD35 RSVD36 RSVD37 RSVD38 RSVD39

RSVD41 RSVD42

RSVD40

RSVD43 RSVD44 RSVD45

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13

CFG16

CFG15

CFG14

CFG17 CFG18 CFG19 CFG20

PM_DPRSTP* PM_EXT_TS0*

PWROK

PM_EXT_TS1*

RSTIN*

DPRSLPVR

NC2

NC4

NC3

NC5

NC7

NC6

NC10

NC9

NC12

NC11

NC13 NC14 NC15 NC16

DPLL_REF_CLK

SM_RCOMP_VOH

SM_ODT3

SM_ODT1

RSVD13

SM_CS2* SM_CS3*

SM_CK3 SM_CK4

SM_CK4*

SM_CKE3

RSVD1

SM_CKE4

DPLL_REF_SSCLK*

SM_CK3*

SM_CK1*

SM_CK1

SM_CK0

SA_MA14

RSVD22 RSVD23

RSVD26

SB_MA14

SM_CK2 SM_CK2* SM_CK5 SM_CK5*

(2 OF 10)

RSVD

DDR MUXING

CLK

CFG

DMI

PM

GRAPHICS VID

ME

MISC

NC

OUT OUT OUT OUT OUT

BI BI

IN

OUT

BI

BI OUT OUT

IN

OUT

OUT OUT

IN IN IN OUT

OUT OUT OUT

BI

OUT

BI

OUT

IN

OUT

OUT OUT OUT

OUT

OUT OUT OUT

OUT OUT OUT OUT

IN

IN IN

IN

IN IN IN IN

IN IN

IN

OUT

OUT OUT

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NB CFG<8:0> used for debug access

IPU IPU

NB_CFG<4> NB_CFG<5>

DMI x2 Select

NOTE: GMCH CL_PWROK input must be PWRGD signal for PP3V3_S0M, PP3V3_S0MWOL, PP1V8_S3M, PP1V25_S0M,

If ME/AMT is not used, short CL_PWROK to PWROK.

PP1V05_S0M, PP0V9_S3M and PP0V9_S0M.

NB_CFG<18>

NB_CFG<15>

FSB Dynamic ODT

NB_CFG<17>

NB_CFG<14>

NB_CFG<16>

NB_CFG<11> NB_CFG<12> NB_CFG<13>

DMI Lane Reversal

SDVO/PCIe x1

Concurrent

NB_CFG<20>

NB_CFG<19>

00 = RESERVED

or PCIe x16

11 = Normal Operation

High = Reversed

Low = Only SDVO

NB_CFG<13:12>

High = Both active

Low = Normal

01 = XOR Mode Enabled 10 = All-Z Mode Enabled

High = Enabled Low = Disabled

See Below See Below

RESERVED

Lane Reversal

PCIe Graphics

NB_CFG<9>

NB_CFG<10>

Low = Reversed

High = Normal

RESERVED

NB_CFG<7>

High = DMIx4

NB_CFG<6>

RESERVED

IPU

Clk used for PEG and DMI

IPD IPD

IPD

IPU

NB_CFG<8>

NB_CFG<3>

Low = DMIx2

RESERVED

IPU

NB CFG<13:12> require ICT access

7

28

8

16 31 32 63

402

CERM

20%

0.1uF

10V

C1616

1

2

402

CERM

20%

0.1uF

10V

C1615

1

2

CRESTLINE

FCBGA

OMIT

U1400

P27 N27

R24 L23 J23 E23 E20 K23 M20 M24 L32 N33

N24

L35

C21 C23 F23 N23 G23 J20 C20

AM49 AK50 AT43 AN49 AM50

G39

AN47 AJ38 AN42 AN46

AM47 AJ39 AN41 AN45

AJ46 AJ41 AM40 AM44

AJ47 AJ42 AM39 AM43

B42 C42 H48 H47

G36

E35 A39 C38 B39 E36

G40

BJ51

E1

A5 C51 B50 A50 A49 BK2

BK51 BK50 BL50 BL49

BL3 BL2 BK1 BJ1

K44 K45

G41 L39 L36 J36

AW49 AV20

P36

AR37 AM36 AL36 AM37

D20

P37

H10 B51

BJ20 BK22 BF19 BH20 BK18 BJ18

R35

BH39 AW20 BK20

C48 D47 B44

N35

C44 A35 B37 B36 B34 C34

AR12 AR13 AM12 AN13

J12

BJ29 BE24

H35 K36

AV29

AW30

BB23

BA23

BF23 BG23

BA25

AW25

AV23

AW23

BC23 BD24

BE29 AY32 BD39 BG37

BG20 BK16 BG16 BE13

BH18 BJ15 BJ14 BE16

BL15 BK14

BK31 BL31

AR49 AW4

A37 R32

N20

9

60

25 87

7 9

16 28 59

25 87

7

29

7

25

402

20K

MF-LF

1/16W

5%

R1691

1

2

402

0

MF-LF

1/16W

5%

R1690

1

2

7

25 59 83

32 45

402

10K

MF-LF

5% 1/16W

R1631

1

2

0.01UF

10% 16V

CERM

402

C1625

1

2

603

2.2UF

6.3V CERM1

20%

C1624

1

2

1K

MF-LF

1% 1/16W

402

R1624

1

2

402

1% 1/16W MF-LF

3.01K

R1622

1

2

603

6.3V CERM1

2.2UF

20%

C1622

1

2

0.01UF

10% 16V

CERM

402

C1623

1

2

1K

402

1/16W

1% MF-LF

R1620

1

2

402

392

MF-LF

1/16W

1%

R1641

1

2

402

MF-LF

1/16W

1K

1%

R1640

1

2

402

20% 10V

CERM

0.1uF

C1640

1

2

402

5%

3.9K

MF-LF

1/16W

NBCFG_DMI_X2

R1655

1

2

402

5% 1/16W MF-LF

3.9K

NBCFG_PEG_REVERSE

R1659

1

2

402

NBCFG_DYN_ODT_DISABLE

3.9K

1/16W

5% MF-LF

R1666

1

2

402

3.9K

MF-LF

1/16W

5%

NBCFG_DMI_REVERSE

R1669

1

2

402

5% 1/16W MF-LF

3.9K

NBCFG_SDVO_AND_PCIE

R1670

1

2

31 33 85

32 33 85

13 30 83

13

13 16

7

25

13

10 23 46 83

31 45

7

10 23 59 83

7 9

16 28 59

31 85

32 85

31 85

32 85

31 85

31 33 85

32 33 85

31 33 85

32 33 85

31 33 85

32 33 85

31 33 85

32 33 85

MF-LF

1/16W

1%

20

402

R1610

1

2

1/16W

1%

MF-LF

20

402

R1611

1

2

8

16 31 32 63

7

29 30 88

7

29 30 88

8

18 21 22 50

7

22 29 30 88

7

22 29 30 88

24 84

402

MF-LF

1/16W

5%

10K

R1630

1

2

051-7261

10.0.0

9216

SYNC_MASTER=T9_NOME

SYNC_DATE=01/25/2007

NB Misc Interfaces

TP_LVDS_A_DATAP3

TP_NB_RSVD<34>

MEM_B_A<14>

TP_NB_RSVD<27>

TP_NB_RSVD<26>

TP_NB_RSVD<25>

NB_CLK100M_DPLLSS_P NB_CLK100M_DPLLSS_N

NB_BSEL<0>

NB_CFG<5>

MEM_CKE<4>

TP_NB_RSVD<1>

MEM_CLK_P<0>

MEM_CLK_N<4>

MEM_CLK_N<3>

MEM_CLK_P<4>

MEM_CLK_P<3>

TP_NB_RSVD<13>

TP_NB_NC<16>

TP_NB_NC<15>

TP_NB_NC<14>

TP_NB_NC<13>

TP_NB_NC<11> TP_NB_NC<12>

TP_NB_NC<9> TP_NB_NC<10>

TP_NB_NC<6> TP_NB_NC<7>

TP_NB_NC<5>

TP_NB_NC<3>

TP_NB_NC<2>

PM_EXTTS_L<0>

NB_CFG<20>

NB_CFG<19>

TP_NB_CFG<18>

TP_NB_CFG<14> TP_NB_CFG<15> NB_CFG<16>

TP_NB_CFG<12>

TP_NB_CFG<10>

TP_NB_RSVD<41>

TP_NB_RSVD<23>

TP_NB_RSVD<22>

TP_NB_RSVD<21>

TP_NB_RSVD<20>

NB_TEST2

NB_TEST1

TP_NB_RSVD<2>

TP_NB_RSVD<8> TP_NB_RSVD<9> TP_NB_RSVD<10> TP_NB_RSVD<11>

MEM_CS_L<0> MEM_CS_L<1>

MEM_CKE<0>

MEM_CLK_N<1>

MEM_CLK_P<1>

MEM_CLK_N<0>

TP_NB_RSVD<7>

TP_NB_RSVD<3> TP_NB_RSVD<4>

TP_NB_NC<8>

TP_NB_NC<1>

GND

NB_CLK100M_PCIE_P NB_CLK100M_PCIE_N

DMI_S2N_P<0> DMI_S2N_P<1> DMI_S2N_P<2>

DMI_N2S_N<0> DMI_N2S_N<1>

DMI_N2S_N<3>

DMI_N2S_N<2>

DMI_N2S_P<0> DMI_N2S_P<1> DMI_N2S_P<2> DMI_N2S_P<3>

GFX_VID<2>

CLINK_NB_DATA VR_PWRGOOD_DELAY CLINK_NB_RESET_L

GND GND NB_CLKREQ_L NB_SB_SYNC_L

TP_MEM_CLKN2 TP_MEM_CLKP5 TP_MEM_CLKN5

PM_BMBUSY_L CPU_DPRSTP_L

VR_PWRGOOD_DELAY

PM_THRMTRIP_L

MEM_CS_L<2>

MEM_ODT<2> MEM_ODT<3>

PPVCORE_S0_NB_R

MEM_CS_L<3> MEM_ODT<0>

MEM_ODT<1>

TP_NB_RSVD<6>

TP_NB_RSVD<12>

TP_NB_NC<4>

GFX_VID<4>

DMI_S2N_P<3>

DMI_S2N_N<2>

PP0V9_S3_MEM_VREF

TP_NB_RSVD<5>

TP_NB_RSVD<24>

TP_MEM_CLKP2

TP_LVDS_A_DATAN3

TP_LVDS_B_DATAP3

MEM_A_A<14>

DMI_S2N_N<0>

TP_NB_RSVD<35> TP_NB_RSVD<36>

TP_LVDS_B_DATAN3

TP_NB_RSVD<45>

TP_NB_RSVD<42>

DMI_S2N_N<3>

DMI_S2N_N<1>

TP_NB_RSVD<14>

PM_DPRSLPVR

NB_RESET_L

PM_EXTTS_L<1>

NB_CFG<9>

NB_CFG<16>

PP3V3_S0

NB_CFG<19>

NB_CFG<20>

PP3V3_S0

TP_NB_CFG<11>

TP_NB_CFG<13>

GFX_VID<3>

GFX_VR_EN

PP3V3_S0

TP_NB_CFG<17>

GFX_VID<1>

CLINK_NB_CLK

PP1V25_S0M_NB_VCCAXD

GND

NB_CLINK_VREF

NB_BSEL<2>

NB_BSEL<1>

NB_CFG<3>

NB_CFG<6> NB_CFG<7> NB_CFG<8> NB_CFG<9>

NB_CFG<5>

MEM_RCOMP_L

TP_NB_RSVD<43> TP_NB_RSVD<44>

NB_CFG<4>

MEM_CKE<1> MEM_CKE<3>

PP0V9_S3_MEM_VREF

MEM_RCOMP_VOL

MEM_RCOMP

PP1V8_S3_ISNS

MEM_RCOMP_VOH

91

81

79

77

76

66

60

59

58

53

52

51

50

48

47

46

42

32

31

30

29

28

27

26

25

24

23

21

58

19

50

16

21

16

13

21

18

13

7

16

7

16

8

16

8

19

87

16

8

http://24hcongnghe.org

BI

BI BI BI BI BI

OUT

BI

OUT

BI BI BI

BI

BI BI BI BI

BI BI

BI BI BI BI BI

BI BI BI

BI

BI BI BI

BI

BI BI BI BI

BI

BI BI BI BI BI

BI BI

BI

OUT

BI

OUT

OUT OUT

OUT

OUT OUT

OUT

BI

OUT

BI

BI BI BI

BI

BI BI BI

BI BI

BI

BI BI

OUT

BI

OUT OUT

OUT

BI

OUT

SA_DQ0 SA_DQ1 SA_DQ2

SA_DQ4

SA_DQ6

SA_DQ14

SA_CAS*

SA_BS2

SA_DQ63

SA_DQ62

SA_DQ61

SA_DQ60

SA_DQ59

SA_DQ58

SA_DQ57

SA_DQ56

SA_DQ55

SA_DQ54

SA_DQ53

SA_DQ52

SA_DQ51

SA_DQ50

SA_DQ49

SA_DQ48

SA_DQ47

SA_DQ46

SA_DQ44

SA_DQ43

SA_DQ42

SA_DQ41

SA_DQ40

SA_DQ39

SA_DQ38

SA_DQ37

SA_DQ36

SA_DQ34 SA_DQ35

SA_DQ33

SA_DQ32

SA_DQ31

SA_DQ30

SA_DQ28 SA_DQ29

SA_DQ27

SA_DQ26

SA_DQ25

SA_DQ24

SA_DQ23

SA_DQ22

SA_DQ21

SA_DQ20

SA_DQ19

SA_DQ18

SA_DQ17

SA_DQ16

SA_DQ15

SA_DQ13

SA_DQ11 SA_DQ12

SA_DQ10

SA_DQ9

SA_DQ8

SA_DQ7

SA_DQ5

SA_DQ3

SA_BS1

SA_BS0

SA_DQ45

SA_DM0 SA_DM1

SA_DM3

SA_DM2

SA_DM5

SA_DM4

SA_DM7

SA_DM6

SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7

SA_DQS1*

SA_DQS0*

SA_DQS2*

SA_DQS4*

SA_DQS3*

SA_DQS5* SA_DQS6* SA_DQS7*

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7

SA_MA9

SA_MA8

SA_MA10 SA_MA11 SA_MA12 SA_MA13

SA_RAS*

SA_RCVEN*

SA_WE*

DDR SYSTEM MEMORY A

(4 OF 10)

SB_DQ2

SB_DQ1

SB_DQ5

SB_DM0

SB_DQ0

SB_DQ4

SB_DQ6 SB_DQ7

SB_CAS*

SB_BS2

SB_BS0 SB_BS1

SB_DQ63

SB_DQ62

SB_DQ59

SB_DQ58

SB_DQ56

SB_DQ55

SB_DQ54

SB_DQ53

SB_DQ52

SB_DQ51

SB_DQ50

SB_DQ49

SB_DQ48

SB_DQ47

SB_DQ45 SB_DQ46

SB_DQ44

SB_DQ43

SB_DQ42

SB_DQ41

SB_DQ40

SB_DQ39

SB_DQ38

SB_DQ37

SB_DQ36

SB_DQ34 SB_DQ35

SB_DQ33

SB_DQ32

SB_DQ31

SB_DQ30

SB_DQ28 SB_DQ29

SB_DQ27

SB_DQ26

SB_DQ25

SB_DQ24

SB_DQ23

SB_DQ22

SB_DQ21

SB_DQ20

SB_DQ19

SB_DQ18

SB_DQ17

SB_DQ16

SB_DQ15

SB_DQ14

SB_DQ13

SB_DQ11 SB_DQ12

SB_DQ10

SB_DQ9

SB_DQ8

SB_DQ3

SB_DQ57

SB_DQ61

SB_DQ60

SB_WE*

SB_RCVEN*

SB_RAS*

SB_MA13

SB_MA12

SB_MA11

SB_MA10

SB_MA8 SB_MA9

SB_MA7

SB_MA6

SB_MA5

SB_MA4

SB_MA3

SB_MA2

SB_MA1

SB_MA0

SB_DQS7*

SB_DQS6*

SB_DQS5*

SB_DQS3* SB_DQS4*

SB_DQS2*

SB_DQS0* SB_DQS1*

SB_DQS7

SB_DQS6

SB_DQS5

SB_DQS4

SB_DQS3

SB_DQS2

SB_DQS1

SB_DQS0

SB_DM6 SB_DM7

SB_DM4 SB_DM5

SB_DM2 SB_DM3

SB_DM1

(5 OF 10)

DDR SYSTEM MEMORY B

BI

OUT OUT OUT

BI

OUT

BI

OUT

BI

BI BI BI BI BI BI BI BI BI BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

31 85

32 85

31 85 32 85

32 85

31 85

32 85

31 85

32 85

31 85

32 85

31 85

32 85

31 85

32 85

32 33 85

31 85

32 33 85

31 85

32 33 85

32 85

31 85

32 85

31 85

32 85

32 33 85

31 85

32 33 85

FCBGA

CRESTLINE

OMIT

U1400

BB19 BK19 BF29

BL17

AT45 BD44 BD42 AW38 AW13 BG8 AY5 AN6

AR43 AW44

BG47 BJ45 BB47 BG50 BH49 BE45 AW43 BE44 BG42 BE40

BA45

BF44 BH45 BG40 BF40 AR40 AW40 AT39 AW36 AW41 AY41

AY46

AV38 AT38 AV13 AT13 AW11 AV11 AU15 AT11 BA13 BA11

AR41

BE10 BD10

BD8 AY9

BG10

AW9 BD7 BB9 BB5 AY7

AR45

AT5 AT7 AY6 BB7 AR5 AR8 AR9 AN3 AM8

AN10

AT42

AT9 AN9 AM9

AN11

AW47 BB45 BF48

AT46

AT47

BE48

BD47

BB43

BC41

BC37

BA37

BB16

BA16

BH6

BH7

BB2

BC1

AP3

AP2

BJ19 BD20

BC19 BE28 BG30 BJ16

BK27 BH28 BL24 BK28 BJ27 BJ25 BL28 BA28

BE18 AY20

BA19

FCBGA

CRESTLINE

OMIT

U1400

AY17 BG18 BG36

BE17

AR50 BD49 BK45 BL39 BH12 BJ7 BF3 AW2

AP49 AR51

BA49 BE50 BA51 AY49 BF50 BF49 BJ50 BJ44 BJ43 BL43

AW50

BK47 BK49 BK43 BK42 BJ41 BL41 BJ37 BJ36 BK41 BJ40

AW51

BL35 BK37 BK13 BE11 BK11 BC11 BC13 BE12 BC12 BG12

AN51

BJ10

BL9 BK5 BL5 BK9

BK10

BJ8 BJ6 BF4 BH5

AN50

BG1 BC2 BK3 BE4 BD3 BJ2 BA3 BB3 AR1 AT3

AV50

AY2 AY3 AU2 AT2

AV49 BA50 BB50

AT50

AU50

BD50

BC50

BK46

BL45

BK39

BK38

BJ12

BK12

BL7

BK7

BE2

BF2

AV2

AV3

BC18 BG28

BG17 BE37 BA39 BG13

BG25 AW17 BF25 BE25 BA29 BC28 AY28 BD37

AV16 AY18

BC17

31 85

31 33 85

31 85

31 33 85

31 85

31 33 85

31 85

31 33 85

31 85

SYNC_DATE=01/25/2007

SYNC_MASTER=T9_NOME

NB DDR2 Interfaces

051-7261

10.0.0

9217

MEM_A_DQ<35>

TP_MEM_A_RCVEN_L TP_MEM_B_RCVEN_L

MEM_B_DQ<39>

MEM_B_BS<0> MEM_B_BS<1> MEM_B_BS<2>

MEM_B_DM<0>

MEM_B_CAS_L

MEM_B_DM<1> MEM_B_DM<2>

MEM_B_DQ<0> MEM_B_DQ<1> MEM_B_DQ<2> MEM_B_DQ<3> MEM_B_DQ<4> MEM_B_DQ<5> MEM_B_DQ<6> MEM_B_DQ<7> MEM_B_DQ<8>

MEM_B_DM<3> MEM_B_DM<4> MEM_B_DM<5> MEM_B_DM<6> MEM_B_DM<7>

MEM_B_DQS_P<1>

MEM_B_DQS_P<0>

MEM_B_DQS_P<4>

MEM_B_DQS_P<3>

MEM_B_DQS_P<2>

MEM_B_DQS_P<6>

MEM_B_DQS_P<5>

MEM_B_DQS_N<1>

MEM_B_DQS_P<7> MEM_B_DQS_N<0>

MEM_B_DQS_N<3>

MEM_B_DQS_N<2>

MEM_B_DQS_N<4>

MEM_B_DQS_N<6>

MEM_B_DQS_N<5>

MEM_B_DQS_N<7>

MEM_B_A<0> MEM_B_A<1> MEM_B_A<2> MEM_B_A<3> MEM_B_A<4> MEM_B_A<5> MEM_B_A<6> MEM_B_A<7> MEM_B_A<8> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11> MEM_B_A<12>

MEM_B_RAS_L

MEM_B_A<13>

MEM_B_WE_L

MEM_B_DQ<9> MEM_B_DQ<10> MEM_B_DQ<11> MEM_B_DQ<12> MEM_B_DQ<13> MEM_B_DQ<14> MEM_B_DQ<15> MEM_B_DQ<16> MEM_B_DQ<17> MEM_B_DQ<18> MEM_B_DQ<19> MEM_B_DQ<20> MEM_B_DQ<21> MEM_B_DQ<22> MEM_B_DQ<23> MEM_B_DQ<24> MEM_B_DQ<25> MEM_B_DQ<26> MEM_B_DQ<27> MEM_B_DQ<28> MEM_B_DQ<29> MEM_B_DQ<30> MEM_B_DQ<31> MEM_B_DQ<32> MEM_B_DQ<33> MEM_B_DQ<34> MEM_B_DQ<35> MEM_B_DQ<36> MEM_B_DQ<37> MEM_B_DQ<38>

MEM_B_DQ<40> MEM_B_DQ<41> MEM_B_DQ<42> MEM_B_DQ<43> MEM_B_DQ<44> MEM_B_DQ<45> MEM_B_DQ<46> MEM_B_DQ<47> MEM_B_DQ<48> MEM_B_DQ<49> MEM_B_DQ<50> MEM_B_DQ<51> MEM_B_DQ<52> MEM_B_DQ<53> MEM_B_DQ<54> MEM_B_DQ<55> MEM_B_DQ<56> MEM_B_DQ<57> MEM_B_DQ<58> MEM_B_DQ<59> MEM_B_DQ<60> MEM_B_DQ<61> MEM_B_DQ<62> MEM_B_DQ<63>

MEM_A_DQ<0> MEM_A_DQ<1> MEM_A_DQ<2>

MEM_A_DQ<4>

MEM_A_DQ<6>

MEM_A_CAS_L

MEM_A_BS<2>

MEM_A_DQ<8>

MEM_A_DQ<7>

MEM_A_DQ<5>

MEM_A_DQ<3>

MEM_A_BS<1>

MEM_A_BS<0>

MEM_A_DM<0> MEM_A_DM<1>

MEM_A_DM<3>

MEM_A_DM<2>

MEM_A_DM<5>

MEM_A_DM<4>

MEM_A_DM<7>

MEM_A_DM<6>

MEM_A_DQS_P<0> MEM_A_DQS_P<1> MEM_A_DQS_P<2> MEM_A_DQS_P<3> MEM_A_DQS_P<4> MEM_A_DQS_P<5> MEM_A_DQS_P<6> MEM_A_DQS_P<7>

MEM_A_DQS_N<1>

MEM_A_DQS_N<0>

MEM_A_DQS_N<2>

MEM_A_DQS_N<4>

MEM_A_DQS_N<3>

MEM_A_DQS_N<5> MEM_A_DQS_N<6> MEM_A_DQS_N<7>

MEM_A_A<0> MEM_A_A<1> MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5> MEM_A_A<6> MEM_A_A<7>

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_DQ<9> MEM_A_DQ<10> MEM_A_DQ<11> MEM_A_DQ<12> MEM_A_DQ<13> MEM_A_DQ<14> MEM_A_DQ<15> MEM_A_DQ<16> MEM_A_DQ<17> MEM_A_DQ<18> MEM_A_DQ<19> MEM_A_DQ<20> MEM_A_DQ<21> MEM_A_DQ<22> MEM_A_DQ<23> MEM_A_DQ<24> MEM_A_DQ<25> MEM_A_DQ<26> MEM_A_DQ<27> MEM_A_DQ<28> MEM_A_DQ<29> MEM_A_DQ<30> MEM_A_DQ<31> MEM_A_DQ<32> MEM_A_DQ<33> MEM_A_DQ<34>

MEM_A_DQ<36> MEM_A_DQ<37> MEM_A_DQ<38> MEM_A_DQ<39> MEM_A_DQ<40> MEM_A_DQ<41> MEM_A_DQ<42> MEM_A_DQ<43> MEM_A_DQ<44> MEM_A_DQ<45> MEM_A_DQ<46> MEM_A_DQ<47> MEM_A_DQ<48> MEM_A_DQ<49> MEM_A_DQ<50> MEM_A_DQ<51> MEM_A_DQ<52> MEM_A_DQ<53> MEM_A_DQ<54> MEM_A_DQ<55> MEM_A_DQ<56> MEM_A_DQ<57> MEM_A_DQ<58> MEM_A_DQ<59> MEM_A_DQ<60> MEM_A_DQ<61> MEM_A_DQ<62> MEM_A_DQ<63>

http://24hcongnghe.org

VCC_SM20

VCC_AXG_NCTF42

VCC_SM9 VCC_SM10

VCC_SM17

VCC_SM16

VCC3

VCC_SM5

VCC_SM8

VCC_AXG_NCTF1 VCC_AXG_NCTF2 VCC_AXG_NCTF3 VCC_AXG_NCTF4 VCC_AXG_NCTF5 VCC_AXG_NCTF6

VCC_AXG_NCTF8

VCC_AXG_NCTF7

VCC_AXG_NCTF10

VCC_AXG_NCTF9

VCC_AXG_NCTF11 VCC_AXG_NCTF12 VCC_AXG_NCTF13 VCC_AXG_NCTF14 VCC_AXG_NCTF15 VCC_AXG_NCTF16

VCC_AXG_NCTF18

VCC_AXG_NCTF17

VCC_AXG_NCTF20

VCC_AXG_NCTF19

VCC_AXG_NCTF21 VCC_AXG_NCTF22

VCC_AXG_NCTF25 VCC_AXG_NCTF26

VCC_AXG_NCTF28

VCC_AXG_NCTF27

VCC_AXG_NCTF29 VCC_AXG_NCTF20 VCC_AXG_NCTF31 VCC_AXG_NCTF32 VCC_AXG_NCTF33 VCC_AXG_NCTF34 VCC_AXG_NCTF35 VCC_AXG_NCTF36

VCC_AXG_NCTF38

VCC_AXG_NCTF37

VCC_AXG_NCTF40

VCC_AXG_NCTF39

VCC_AXG_NCTF41

VCC_AXG_NCTF43 VCC_AXG_NCTF44 VCC_AXG_NCTF45 VCC_AXG_NCTF46

VCC_AXG_NCTF48

VCC_AXG_NCTF47

VCC_AXG_NCTF49 VCC_AXG_NCTF50 VCC_AXG_NCTF51

VCC_AXG_NCTF55

VCC_AXG_NCTF58

VCC_AXG_NCTF57

VCC_AXG_NCTF59

VCC_AXG_NCTF61

VCC_AXG_NCTF60

VCC_AXG_NCTF62 VCC_AXG_NCTF63 VCC_AXG_NCTF64

VCC_AXG_NCTF66

VCC_AXG_NCTF65

VCC_AXG_NCTF67 VCC_AXG_NCTF68 VCC_AXG_NCTF69

VCC_AXG_NCTF71

VCC_AXG_NCTF70

VCC_AXG_NCTF72 VCC_AXG_NCTF73 VCC_AXG_NCTF74

VCC_AXG_NCTF76

VCC_AXG_NCTF75

VCC_AXG_NCTF77 VCC_AXG_NCTF78 VCC_AXG_NCTF79

VCC_AXG_NCTF81

VCC_AXG_NCTF80

VCC_AXG_NCTF82 VCC_AXG_NCTF83

VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7

VCC_AXG_NCTF56

VCC_AXG_NCTF54

VCC_AXG_NCTF53

VCC_AXG_NCTF52

VCC_AXG1 VCC_AXG2 VCC_AXG3 VCC_AXG4 VCC_AXG5 VCC_AXG6 VCC_AXG7 VCC_AXG8 VCC_AXG9 VCC_AXG10 VCC_AXG11 VCC_AXG12 VCC_AXG13 VCC_AXG14 VCC_AXG15 VCC_AXG16 VCC_AXG17 VCC_AXG18 VCC_AXG19 VCC_AXG20 VCC_AXG21 VCC_AXG22 VCC_AXG23 VCC_AXG24 VCC_AXG25 VCC_AXG26 VCC_AXG27 VCC_AXG28 VCC_AXG29 VCC_AXG30 VCC_AXG31 VCC_AXG32 VCC_AXG33 VCC_AXG34

VCC_SM1 VCC_SM2 VCC_SM3 VCC_SM4

VCC_SM6 VCC_SM7

VCC_SM11 VCC_SM12 VCC_SM13 VCC_SM14 VCC_SM15

VCC_SM18 VCC_SM19

VCC_SM21 VCC_SM22 VCC_SM23

VCC_SM26 VCC_SM27 VCC_SM28 VCC_SM29 VCC_SM30 VCC_SM31 VCC_SM32 VCC_SM33 VCC_SM34 VCC_SM35 VCC_SM36

VCC_SM25

VCC_SM24

VCC1 VCC2

VCC7 VCC8 VCC9 VCC10 VCC11 VCC12

VCC13

VCC_AXG_NCTF24

VCC_AXG_NCTF23

VCC6

VCC5 VCC4

VCC GFX

VCC SM

VCC SM LF

(6 OF 10)

VCC CORE

POWER

VCC GFX NCTF

VCC_NCTF49

VCC_NCTF15

VCC_NCTF2

VCC_NCTF10

VCC_AXM7

VCC_AXM5

VCC_AXM4

VCC_AXM3

VCC_AXM2

VCC_AXM1

VSS_SCB6

VSS_SCB5

VSS_SCB4

VSS_SCB3

VSS_SCB2

VSS_SCB1

VCC_NCTF11 VCC_NCTF12 VCC_NCTF13 VCC_NCTF14

VSS_NCTF21

VSS_NCTF20

VSS_NCTF19

VSS_NCTF18

VSS_NCTF17

VSS_NCTF16

VSS_NCTF15

VSS_NCTF14

VSS_NCTF12

VSS_NCTF11

VSS_NCTF13

VSS_NCTF10

VSS_NCTF9

VSS_NCTF8

VSS_NCTF7

VSS_NCTF6

VSS_NCTF5

VSS_NCTF4

VSS_NCTF3

VSS_NCTF2

VSS_NCTF1

VCC_NCTF22

VCC_NCTF27

VCC_NCTF50

VCC_NCTF47 VCC_NCTF48

VCC_NCTF44

VCC_NCTF43

VCC_NCTF39 VCC_NCTF40

VCC_NCTF38

VCC_NCTF37

VCC_NCTF34 VCC_NCTF35

VCC_NCTF33

VCC_NCTF32

VCC_NCTF31

VCC_NCTF29

VCC_NCTF28

VCC_NCTF26

VCC_NCTF24 VCC_NCTF25

VCC_NCTF23

VCC_NCTF21

VCC_NCTF18 VCC_NCTF19

VCC_NCTF16 VCC_NCTF17

VCC_NCTF3 VCC_NCTF4

VCC_NCTF41 VCC_NCTF42

VCC_NCTF45 VCC_NCTF46

VCC_AXM6

VCC_AXM_NCTF1 VCC_AXM_NCTF2 VCC_AXM_NCTF3 VCC_AXM_NCTF4 VCC_AXM_NCTF5 VCC_AXM_NCTF6 VCC_AXM_NCTF7 VCC_AXM_NCTF8 VCC_AXM_NCTF9 VCC_AXM_NCTF10 VCC_AXM_NCTF11 VCC_AXM_NCTF12 VCC_AXM_NCTF13 VCC_AXM_NCTF14 VCC_AXM_NCTF15 VCC_AXM_NCTF16 VCC_AXM_NCTF17 VCC_AXM_NCTF18 VCC_AXM_NCTF19

VCC_NCTF8

VCC_NCTF20

VCC_NCTF1

VCC_NCTF5 VCC_NCTF6 VCC_NCTF7

VCC_NCTF36

VCC_NCTF30

VCC_NCTF9

VCC AXM NCTF

VCC NCTF

VSS SCBVCC AXM

VSS NCTF

(7 OF 10)

POWER

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

1395 mA (1 ch, 533MHz)

1700 mA (1 ch, 667MHz)

2700 mA (2 ch, 533MHz)

3300 mA (2 ch, 667MHz)

540 mA

1573 mA (Int Graphics)

1310 mA (Ext Graphics)

7700 mA (Int Graphics)

5 mA (standby)

impacting part performance.

These connections can break without

NCTF balls are Not Critical To Function

Current numbers from Crestline EDS, doc #21749.

FCBGA

CRESTLINE

OMIT

U1400

AT35

AH31 AH29 AF32

R30

AT34 AH28

AC31

AC32

AK32 AJ31 AJ28 AH32

R20

AB21 AB24 AB29 AC20 AC21 AC23 AC24 AC26 AC28 AC29

T14

AD20 AD23 AD24 AD28 AF21 AF26 AA31 AH20 AH21 AH23

W13

AH24 AH26 AD31 AJ20 AN14

W14

Y12 AA20 AA23 AA26 AA28

T17

U17 U19 U20 U21 U23 U26 V16 V17 V19 V20

T18

V21 V23 V24 Y15 Y16 Y17 Y19 Y20 Y21 Y23

T19

Y24 Y26 Y28 Y29 AA16 AA17 AB16 AB19 AC16 AC17

T21

AC19 AD15 AD16 AD17 AF16 AF19 AH15 AH16 AH17 AH19

T22

AJ16 AJ17 AJ19 AK16 AK19 AL16 AL17 AL19 AL20 AL21

T23

AL23 AM15 AM16 AM19 AM20 AM21 AM23 AP15 AP16 AP17

T25

AP19 AP20 AP21 AP23 AP24 AR20 AR21 AR23 AR24 AR26

U15

V26 V28 V29 Y31

U16

AU32

BA35 BB33 BC32 BC33 BC35 BD32 BD35 BE32 BE33 BE35

AU33

BF33 BF34 BG32 BG33 BG35 BH32 BH34 BH35 BJ32 BJ33

AU35

BJ34 BK32 BK33 BK34 BK35 BL33 AU30

AV33 AW33 AW35 AY35 BA32 BA33

AW45 BC39 BE39 BD17 BD4 AW8 AT6

FCBGA

CRESTLINE

OMIT

U1400

AT33 AT31 AK29 AK24 AK23 AJ26 AJ23

AL24

AP29 AP31 AP32 AP33 AL29 AL31 AL32 AR31 AR32 AR33

AL26 AL28 AM26 AM28 AM29 AM31 AM32 AM33

AB33

AF36 AH33 AH35 AH36 AH37 AJ33 AJ35 AK33 AK35 AK36

AB36

AK37 AD33 AJ36 AM35 AL33 AL35 AA33 AA35 AA36 AP35

AB37

AP36 AR35 AR36

Y32 Y33 Y35 Y36 Y37 T30 T34

AC33

T35 U29 U31 U32 U33 U35 U36 V32 V33 V36

AC35

V37

AC36 AD35 AD36 AF33

T27

AD19 AD37 AF17 AF35 AK17 AM17 AM24 AP26 AP28 AR15

T37

AR19 AR28

U24 U28 V31 V35 AA19 AB17 AB35

A3 B2 C1 BL1 BL51 A51

20%

CERM

10V

0.1uF

402

C1806

1

2

20%

CERM

10V

0.1uF

402

C1807

1

2

20%

6.3V

0.22UF

X5R 402

C1804

1

2

20%

6.3V

0.22UF

X5R 402

C1805

1

2

6.3V

1uF

CERM

10%

402

C1802

1

2

CERM-X5R

6.3V

0.47UF

10%

402

C1803

1

2

6.3V

1uF

CERM

10%

402

C1801

1

2

SYNC_MASTER=T9_NOME

SYNC_DATE=01/25/2007

NB Power 1

051-7261

10.0.0

9218

PP1V05_S0

NB_VCCSM_LF5

NB_VCCSM_LF7

PPVCORE_S0_NB_R

PP1V05_S0

NB_VCCSM_LF1 NB_VCCSM_LF2 NB_VCCSM_LF3 NB_VCCSM_LF4

NB_VCCSM_LF6

PPVCORE_S0_NB_GFX

PPVCORE_S0_NB_R

PPVCORE_S0_NB_GFX

PP1V8_S3_ISNS

62

50

46

30

27

26

23

21

19

18

14

50

14

50

13

22

13

60

22 60

58

12

21

12

22

21 22

50

11

18

11

18

18 18

21

10

16

10

8

16

8

16

8

7

8 7

8

http://24hcongnghe.org

VCCA_CRT_DAC1

VTT7 VTT8

VCC_AXD_NCTF

VCCD_CRT

VCC_RXR_DMI1 VCC_RXR_DMI2

VTT1

VCCA_SM_CK2 VCC_TX_LVDS

VCC_HV2

VCC_PEG1 VCC_PEG2 VCC_PEG3

VCC_AXF2

VCC_AXD1 VCC_AXD2

VSSA_LVDS

VCCA_SM5

VCCA_PEG_PLL

VCCA_MPLL

VCCA_HPLL VTT16

VTT17

VTT15

VCCD_LVDS2

VCCD_LVDS1

VCCD_PEG_PLL

VCCD_HPLL

VCCD_QDAC

VCCD_TVDAC

VCCA_TVC_DAC1 VCCA_TVC_DAC2

VCCA_TVB_DAC2

VCCA_TVB_DAC1

VCCA_TVA_DAC2

VCCA_TVA_DAC1

VCCA_SM_CK1

VCCA_SM2

VCCA_SM1

VCCA_SM_NCTF2

VCCA_SM_NCTF1

VCCA_SM11

VCCA_SM10

VCCA_SM9

VCCA_SM8

VCCA_SM7

VCCA_SM4

VCCA_SM3

VSSA_PEG_BG

VCCA_PEG_BG

VCCA_LVDS

VCCA_DPLLB

VCCA_DPLLA

VSSA_DAC_BG

VCCA_DAC_BG

VCC_AXF3

VCC_HV1

VCC_PEG5

VTTLF1

VTTLF3

VTTLF2

VCC_PEG4

VCC_SM_CK3

VCC_SM_CK2

VCC_SM_CK1

VCC_SM_CK4

VCC_DMI

VCC_AXF1

VTT22

VCC_AXD6

VCC_AXD5

VCC_AXD4

VCC_AXD3

VTT19

VTT2

VTT6

VTT5

VTT11

VTT10

VTT9

VTT13

VTT12

VTT14

VTT18

VTT21

VTT20

VTT3 VTT4

VCCA_CRT_DAC2

VCC_SYNC

CRT

AXD

PEG

HV

AXF

VTTLF

VTT

SM CK

DMI

TV/CRT

D

LVDS

A SMA CK

CRT A LVDS

A PEG

PLL

(8 OF 10)

POWER

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

550 mA (533MHz DDR)

640 mA (667MHz DDR)

Current numbers from Crestline EDS, doc #21749.

515 mA

495 mA

850 mA @ 800MHz FSB (1.05V)

35 mA

100 mA

60 mA

30 mA

80 mA

0.4 mA

260 mA

1260 mA

770 mA @ 667MHz FSB (1.05V)

150 mA

TBD mA @ 1067MHz FSB (1.25V)

S0 or S3M is acceptable

5 mA

150 mA

250 mA

60 mA

40 mA

10 mA

100 mA

50 mA

5 mA

200 mA

100 mA

6.3V 402

CERM-X5R

10%

0.47UF

C1911

1

2

402

CERM-X5R

6.3V

10%

0.47UF

C1913

1

2

402

CERM-X5R

6.3V

10%

0.47UF

C1912

1

2

CRESTLINE

FCBGA

OMIT

U1400

AT23 AU28 AU24 AT29 AT25 AT30

AR29

B23 B21 A21

AJ50

C40 B40

AD51 W50 W51 V49 V50

AH50 AH51

BK24 BK23 BJ24 BJ23

J32

A43

A33 B33

A30

B49

H49

AL2

A41

AM2

K50

U51

AW18

AT18 AT17

AV19 AU19 AU18 AU17

AT22 AT21 AT19

BC29 BB29

AR17 AR16

C25 B25 C27 B27 B28 A28

M32

AN2

J41 H42

U48

N28

L29

B32

B41

K49

U13

U1 T13 T11 T10 T9 T7 T6 T5 T3 T2

U12

R3 R2 R1

U11 U9 U8 U7 U5 U3 U2

A7 F2 AH1

SYNC_MASTER=T9_NOME

SYNC_DATE=01/25/2007

NB Power 2

19 92

10.0.0

051-7261

NB_VTTLF_CAP2

PP1V8_S0

PP1V25_S0_NB_VCCA_DPLLA

PP1V25_S0M_NB_VCCA_HPLL

GND

PP1V5_S0 PP1V5_S0_NB_VCCD_TVDAC

GND

PP1V25_S0

GND

PP1V25_S0M_NB_VCCA_MPLL

NB_VTTLF_CAP1

NB_VTTLF_CAP3

PP1V25_S0

GND

PP1V8_S0_NB_VCCTXLVDS

PP1V05_S0_NB_VCCPEG

PP3V3_S0

PP1V05_S0_NB_VCCPEG

PP1V25_S0_NB_VCCAXF

PP1V25_S0M_NB_VCCAXD

GND

PP1V25_S0_NB_VCCA_DPLLB

GND

PP1V05_S0

PP1V8_S0_NB_VCCTXLVDS

GND

PP1V25_S0M_NB_VCCA_SM_CK

PP1V25_S0_NB_PEGPLL

PP1V8_S3M_NB_VCCSMCK

PP1V25_S0M_NB_VCCA_SM

PP3V3_S0

91

81

79

77

76

66

60

59

58

53

52

51

50

48

47

46

42

32

62

32

31

50

31

30

46

30

29

30

29

28

27

28

27

26

27

91

26

23

26

64

25

21

25

34

66

24

18

24

27

58

23

14

23

26

27

21

13

21

66

22

26

19

12

19

58

12

21

16

21

11

16

22

11

19

22

19

13

19

21

10

22

13

8

22

21

8

22

8

21

8

19

15

8

15

21

16

22

8

19

21

8

http://24hcongnghe.org

VSS198VSS99

VSS197VSS98

VSS196VSS97

VSS195VSS96

VSS194VSS95

VSS193VSS94

VSS192VSS93

VSS191VSS92

VSS190VSS91

VSS189VSS90

VSS188VSS89

VSS187VSS88

VSS186VSS87

VSS185VSS86

VSS184VSS85

VSS183VSS84

VSS182VSS83

VSS181VSS82

VSS180VSS81

VSS179VSS80

VSS178VSS79

VSS177VSS78

VSS176VSS77

VSS175VSS76

VSS174VSS75

VSS173VSS74

VSS172VSS73

VSS171VSS72

VSS170VSS71

VSS169VSS70

VSS168VSS69

VSS167VSS68

VSS166VSS67

VSS165VSS66

VSS164VSS65

VSS163VSS64

VSS162VSS63

VSS161VSS62

VSS160VSS61

VSS159VSS60

VSS158VSS59

VSS157VSS58

VSS156VSS57

VSS155VSS56

VSS154VSS55

VSS153VSS54

VSS152VSS53

VSS151VSS52

VSS150VSS51

VSS149VSS50

VSS148VSS49

VSS147VSS48

VSS146VSS47

VSS145VSS46

VSS144VSS45

VSS143VSS44

VSS142VSS43

VSS141VSS42

VSS140VSS41

VSS139VSS40

VSS138VSS39

VSS137VSS38

VSS136VSS37

VSS135VSS36

VSS134VSS35

VSS133VSS34

VSS132VSS33

VSS131VSS32

VSS130VSS31

VSS129VSS30

VSS128VSS29

VSS127VSS28

VSS126VSS27

VSS125VSS26

VSS124VSS25

VSS123VSS24

VSS122VSS23

VSS121VSS22

VSS120VSS21

VSS119VSS20

VSS118VSS19

VSS117

VSS116VSS17

VSS115VSS16

VSS114VSS15

VSS113VSS14

VSS112VSS13

VSS111VSS12

VSS110VSS11

VSS109VSS10

VSS108

VSS9

VSS107VSS8

VSS106VSS7

VSS105VSS6

VSS104VSS5

VSS103VSS4

VSS102

VSS101

VSS100

VSS1

VSS18

VSS2 VSS3

VSS

(9 OF 10)

VSS202

VSS289 VSS290 VSS291 VSS292

VSS295

VSS199 VSS287 VSS200 VSS288 VSS201

VSS203 VSS204

VSS293 VSS294

VSS208 VSS296 VSS209 VSS297 VSS210 VSS298 VSS211 VSS299 VSS212 VSS300 VSS213 VSS301 VSS214 VSS215 VSS216 VSS302 VSS217 VSS218 VSS219 VSS303 VSS220 VSS221 VSS222 VSS304 VSS223 VSS224 VSS225 VSS305 VSS226 VSS227 VSS228 VSS229 VSS306 VSS230 VSS307 VSS231 VSS308 VSS232 VSS309 VSS233 VSS310 VSS234 VSS311 VSS235 VSS312 VSS236 VSS313 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243

VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 VSS286

VSS207

VSS206

VSS205

(10 OF 10)

VSS

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NOTE: TDE = _P

Crestline Thermal Diode Pins

TDB_SENSE

NOTE: TDB = _N

Mainly for investigation. If not used, alias these nets directly to GND.

TDB_FORCE

TDE_FORCE

TDE_SENSE

CRESTLINE

OMIT

FCBGA

U1400

A13

AB26

AW24 AW29 AW32 AW5 AW7 AY10 AY24 AY37 AY42 AY43

AB28 AY45

AY47 AY50 B10 B20 B24 B29 B30 B35 B38

AB31

B43 B46 B5 B8 BA1 BA17 BA18 BA2 BA24 BB12

AC10

BB25 BB40 BB44 BB49 BB8 BC16 BC24 BC25 BC36 BC40

AC13

BC51 BD13 BD2 BD28 BD45 BD48 BD5 BE1 BE19 BE23

AC3

BE30 BE42 BE51 BE8 BF12 BF16 BF36 BG19 BG2 BG24

AC39

BG29 BG39 BG48 BG5 BG51 BH17 BH30 BH44 BH46 BH8

AC43

BJ11 BJ13 BJ38 BJ4 BJ42 BJ46 BK15 BK17 BK25 BK29

AC47

BK36 BK40 BK44 BK6 BK8 BL11 BL13 BL19 BL22 BL37

AD1

BL47 C12 C16 C19 C28 C29 C33 C36 C41

A15

AD21 AD26 AD29

AD3 AD41 AD45 AD49

AD5 AD50

AD8

A17

AE10 AE14

AE6 AF20 AF23 AF24 AF31

AG2 AG38 AG43

A24

AG47 AG50

AH3 AH40 AH41

AH7

AH9 AJ11 AJ13 AJ21

AA21

AJ24 AJ29 AJ32 AJ43 AJ45 AJ49 AK20 AK21 AK26 AK28

AA24

AK31 AK51

AL1 AM11 AM13

AM3

AM4 AM41 AM45

AN1

AA29

AN38 AN39 AN43

AN5

AN7

AP4 AP48 AP50 AR11

AR2

AB20

AR39 AR44 AR47

AR7 AT10 AT14 AT41 AT49

AU1 AU23

AB23

AU29

AU3 AU36 AU49 AU51 AV39 AV48

AW1 AW12 AW16

CRESTLINE

OMIT

FCBGA

U1400

C46 C50

C7 D13 D24

D3 D32 D39 D45 D49 E10 E16 E24 E28 E32 E47 F19 F36

F4 F40 F50

G1 G13 G16 G19 G24 G28 G29 G33 G42 G45 G48

G8 H24 H28

H4 H45 J11 J16

J2 J24 J28 J33 J35 J39

K12 K47

K8

L1 L17 L20 L24 L28

L3 L33 L49 M28 M42 M46 M49

M5 M50

M9 N11 N14 N17 N29 N32 N36 N39 N44 N49

N7 P19

P2 P23

P3 P50 R49 T39 T43 T47 U41 U45 U50

V2

V3

W11 W39 W43 W47 W5 W7 Y13 Y2 Y41 Y45 Y49 Y5 Y50 Y11 P29

T29

T31

T33

R28

AA32 AB32 AD32 AF28 AF29 AT27 AV25 H50

SYNC_DATE=01/25/2007

SYNC_MASTER=T9_NOME

NB Grounds

20 92

10.0.0

051-7261

GND

http://24hcongnghe.org

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Placeholder for 5.6nH, 0.9A, 45mOhm max

10uF caps should

Layout Note:

WF: "Place where LVDS

close to MCH

Place L and C

Layout Note:

Placeholder for 2.2nH, 1.4A, 17mOhm

10uF caps should

100 mA

250 mA

50 mA

150 mA

450 mA

be close to MCH on opposite side.

Layout Note:

be close to MCH on opposite side.

200 mA200 mA

100 mA

NOTE: This follower is redundant if VCORE is always 1.05V.

Layout Note: Route to caps, then GND

5 mA (standby)

1395 mA (1ch 533MHz)

1700 mA (1ch 667MHz)

2700 mA (2ch 533MHz)

3300 mA (2ch 667MHz)

675 mA (667MHz DDR2) 585 mA (533MHz DDR2)

515 mA 515 mA

0.4 mA

35 mA

640 mA (667MHz DDR2) 550 mA (533MHz DDR2)

495 mA 495 mA

1260 mA1520 mA

260 mA

Current numbers from Crestline EDS, doc #21749.

GMCH FSB I/O Rail

1310mA (Ext Graphics)

1573mA (Int Graphics)

Placeholder for 3.9nH, 1A, 32mOhm

and DDR2 taps." (C2135)

770 mA (667MHz FSB)

GMCH Memory I/O Rail

850 mA (800MHz FSB)

540 mA

WF: Matanzas has 2-pin 270uF bulk cap

GMCH ME Core Power

GMCH Core Power

0.47UF

CERM-X5R

10% 402

6.3V

PLACEMENT_NOTE=Place close to U1400

C2124

1

2

6.3V

20%

PLACEMENT_NOTE=Place close to U1400

2.2uF

603

CERM1

C2123

1

2

4.7uF

603

PLACEMENT_NOTE=Place close to U1400

CERM

20%

6.3V

C2121

1

2

10V

0.1uF

402

CERM

20%

C2161

1

2

10V

0.1uF

402

CERM

20%

C2165

1

2

20%

CRITICAL

470UF

2.5V TANT

D2T

C2100

1

2 3

10V

PLACEMENT_NOTE=Place in GMCH cavity

0.1uF

402

CERM

20%

C2113

1

2

0.22uF

402

20%

6.3V X5R

C2112

1

2

402

20%

6.3V X5R

0.22uF

C2111

1

2

20%

6.3V

CERM-X5R

805-3

22UF

C2110

1

2

CERM

PLACEMENT_NOTE=Place in GMCH cavity

10V

0.1uF

402

20%

C2114

1

2

PLACEMENT_NOTE=Place in GMCH cavity

10V

0.1uF

402

CERM

20%

C2115

1

2

4.7uF

603

PLACEMENT_NOTE=Place close to U1400

CERM

20%

6.3V

C2122

1

2

6.3V

20%

PLACEMENT_NOTE=Place close to U1400

CERM-X5R 805-3

22UF

C2131

1

2

6.3V

20%

PLACEMENT_NOTE=Place close to U1400

CERM-X5R 805-3

22UF

C2132

1

2

0.1uF

20% CERM

402

10V

C2135

1

2

0.51

MF-LF

1/16W

1%

402

R2183

1

2

10V

0.1uF

402

CERM

20%

C2191

1

2

402

1.1

1% 1/16W MF-LF

R2190

1

2

0805

FERR-220-OHM

L2190

1 2

10uF

20%

6.3V X5R 603

C2190

1

2

10V

0.1uF

402

CERM

20%

C2192

1

2

PLACEMENT_NOTE=Place C2180 by U1400.AN2

10V

0.1uF

402

CERM

20%

C2180

1

2

D3L

POLY

6.3V

20%

330uF

CRITICAL

C2130

1

2

CRITICAL

D3L

POLY

6.3V

20%

330uF

C2120

1

2

20%

603

10uF

6.3V X5R

C2174

1

2

CRITICAL

CASE-B2

2.5V

220UF

20%

POLY

C2173

1

2

91NH

1210

L2173

1 2

10V 402

CERM

20%

0.1uF

C2197

1

2

402

MF-LF

1%

1/16W

1.1

R2195

1

2

0805

1.0UH-220MA-0.12-OHM

L2195

1 2

603

10uF

20%

6.3V X5R

C2195

1

2

6.3V

20%

CERM-X5R

805-3

22UF

C2196

1

2

10V

0.1uF

402

CERM

20%

C2160

1

2

X5R

10V

10%

402

1uF

C2171

1

2

603

X5R

6.3V

20%

10uF

C2170

1

2

603

5%

MF-LF

1/10W

0

R2170

1 2

X5R

10V

10%

1uF

402

C2151

1

2

5% 1/10W MF-LF

0

603

R2150

1 2

NO STUFF

0603

FERR-120-OHM-0.2A

L2150

1 2

6.3V

20%

CERM-X5R

805-3

22UF

C2142

1

2

6.3V

20%

NO STUFF

CERM-X5R

805-3

22UF

C2141

1

2

4.7UF

6.3V

20% CERM

603

C2143

1

2

CRITICAL

D3L

POLY

6.3V

20%

330uF

C2140

1

2

X5R

1uF

402

10% 10V

C2144

1

2

0

5% 1/10W MF-LF

603

R2141

1 2

20%

6.3V

CERM-X5R

805-3

22UF

C2145

1

2

0

603

MF-LF

1/10W

5%

R2145

1 2

CERM

20%

402

0.1uF

10V

C2148

1

2

1/16W

1%

MF-LF

10

402

R2186

1 2

BAT54E3

SOT23

D2186

1 3

10

MF-LF

1%

1/16W

402

R2185

1 2

BAT54E3

SOT23

D2185

1 3

NO STUFF

6.3V

20%

CERM-X5R

805-3

22UF

C2150

1

2

NO STUFF

6.3V

20%

2.2uF

603

CERM1

C2146

1

2

0603

FERR-120-OHM-0.2A

L2181

1 2

PLACEMENT_NOTE=Place in GMCH cavity

10V

0.1uF

402

CERM

20%

C2104

1

2

603

10uF

20%

6.3V X5R

C2177

1

2

0.22uF

PLACEMENT_NOTE=Place in GMCH cavity

402

20%

6.3V X5R

C2103

1

2

0.22uF

PLACEMENT_NOTE=Place in GMCH cavity

402

20%

6.3V X5R

C2102

1

2

10V

PLACEMENT_NOTE=Place C2184 by U1400.AM2

0.1uF

402

CERM

20%

C2184

1

2

PLACEMENT_NOTE=Place C2182 by U1400.AL2

10V

0.1uF

402

CERM

20%

C2182

1

2

6.3V

20%

22UF

CERM-X5R

805-3

C2181

1

2

0603

FERR-120-OHM-0.2A

L2183

1 2

6.3V

20%

22UF

CERM-X5R

805-3

C2183

1

2

6.3V

20%

PLACEMENT_NOTE=Place in GMCH cavity

CERM-X5R 805-3

22UF

C2101

1

2

NB Standard Decoupling

SYNC_MASTER=T9_NOME

92

051-7261

10.0.0

21

SYNC_DATE=12/21/2006

PP1V25_S0M_NB_VCCA_SM

MIN_LINE_WIDTH=0.4 MM VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 MM

PP1V05_S0

PPVCORE_S0_NB_R

PP1V8_S3_ISNS

MAKE_BASE=TRUE

PP1V05_S0_NB_VCCPEG

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

MIN_LINE_WIDTH=0.5 MM

PP1V25_S0

PP1V05_S0

PP1V25_S0M_NB_VCCA_SM_CK

MIN_LINE_WIDTH=0.4 MM VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

PP1V05_S0_NB_VCCPEG

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

PP1V25_S0M_NB_VCCA_HPLL

MIN_LINE_WIDTH=0.25 MM VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 MM

GND

PP3V3_S0

MIN_LINE_WIDTH=0.3 MM VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 MM

PP1V25_S0M_NB_VCCA_MPLL

PP1V25_S0

MIN_LINE_WIDTH=0.3 MM VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 MM

PP1V25_S0M_NB_MPLL_RC

PP1V25_S0

PP3V3_S0

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM VOLTAGE=3.3V

PP3V3_S0_NB1V05_FOLLOW_R

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP3V3_S0_NBCORE_FOLLOW_R

VOLTAGE=3.3V

PP1V05_S0

PP3V3_S0

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

PP1V8_S3M_NB_VCCSMCK_RC

VOLTAGE=1.8V

PP1V05_S0

PP1V25_S0

PP1V25_S0_NB_VCCAXF

MIN_LINE_WIDTH=0.4 MM VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 MM

PP1V05_S0

VOLTAGE=1.25V

PP1V25_S0M_NB_VCCAXD

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP1V25_S0

PP1V25_S0_NB_PEGPLL

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 MM

PP1V25_S0_NB_PEGPLL_RC

MIN_LINE_WIDTH=0.25 MM VOLTAGE=1.25V

PP1V25_S0

PP1V8_S3_ISNS

PP1V8_S3M_NB_VCCSMCK

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.8V

91

81

79

77

76

66

60

59

58

53

52

51

50

48

47

46

62

42

62

42

62

62 50

50

32

50

32

50

50 46

46

31

46

31

46

46 30

30

30 27

27

29

27

29

27

27 26

26

28

26

28

26

23

27

23

27

23

23 21

21

26

21

26

21

21 19

19

25

19

25

19

19 18

66

18

24

66

24

18

24

18

66

18

66

14

58

14

23

58

23

14

23

14

58

14

58

13

50

27

13

21

27

21

13

21

13

27

13

27

50

12

22

21

26

12

19

26

19

12

19

12

26

12

26

21

11

18

21

11 21

16

21

16

11

16

11

21

11

21

18

10

16

19

10 19

13

19

13

10

13

10

19

10

19

16

19

8

15

8

19

15

19

8

19

8

16

8

19

8

19

http://24hcongnghe.org

IN

IN IN

OUT

EN

NR/FB

IN

GND

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

100 mA

(1.7V - 5.5V)

100 mA

These 2 caps should be within 6.35 mm of NB edge

Layout Note:

60 mA

Current numbers from Crestline EDS Addendum, doc #20127.

150 mA

110 mA260 mA

65 mA

Layout Note: Route to cap, then GND

Vout = 1.25V (Factory Programmed)

7700 mA

GMCH Graphics Core Power

VCCD_TVDAC also powers internal thermal sensors.

NOTE: This filter is required even if using only external graphics.

Crestline LVDS Support

402

MF-LF

1/16W

1%

2.37K

R2299

1

2

15 84

1UF

10%

402

CERM

6.3V

C2265

1

2

CRITICAL

SOT23-5

TPS731125

U2265

3

2

1

4

5

10% 16V

402

CERM

0.01UF

C2266

1

2

NO STUFF

402

5%

4.7

MF-LF

1/16W

R2261

1 2

NO STUFF

20% CERM

402

0.1uF

10V

C2261

1

2

1/16W

402

5%

MF-LF

4.7

R2262

1 2

0.1uF

20% CERM

402

10V

C2262

1

2

X5R

6.3V

20%

10UF

603

C2260

1

2

CERM

50V

10% 402

0.001UF

C2223

1

2

0.001UF

CERM

50V

10% 402

C2221

1

2

22000pF-1000mA

16V

NFM18

C2201

2

1 3

20% CERM

402

10V

0.1uF

C2200

1

2

1210

1.0UH-0.5A

L2220

1 2

CASE-D3L

CRITICAL

POLY

6.3V

20%

220UF

C2220

1

2

0.1uF

20% CERM

402

10V

PLACEMENT_NOTE=Place in GMCH cavity

C2217

1

2

20%

0.1uF

10V

PLACEMENT_NOTE=Place in GMCH cavity

402

CERM

C2216

1

2

402

10%

PLACEMENT_NOTE=Place in GMCH cavity

6.3V CERM-X5R

0.47UF

C2215

1

2

20%

6.3V X5R

PLACEMENT_NOTE=Place in GMCH cavity

10uF

603

C2213

1

2

CRITICAL

6.3V

20%

PLACEMENT_NOTE=Place in GMCH cavity

22UF

CERM-X5R 805-3

C2212

1

2

2.5V D2T

470UF

20%

TANT

CRITICAL

C2211

1

2 3

20%

2.5V D2T

470UF

CRITICAL

TANT

C2210

1

2 3

1UF

10% 402

CERM

6.3V

C2226

1

2

6.3V CERM

10%

1UF

PLACEMENT_NOTE=Place in GMCH cavity

402

C2214

1

2

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

NB Graphics Decoupling

22 92

10.0.0

051-7261

NB_CLK100M_DPLLSS_P

GND

PPVCORE_S0_NB_R

NB_CLK100M_DPLLSS_N NB_CLK100M_DPLLSS_N

NB_CLK100M_DPLLSS_P

PP1V5_S0

PPVCORE_S0_NB_GFX

PP1V8_S0

GND

PP1V8_S0_NB_VCCTXLVDS

MIN_LINE_WIDTH=0.2 MM VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 MM

PPVCORE_S0_NB_R

LVDS_IBG

PP1V8_S0

PP1V25_S0_NB_VCCA_DPLLA

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.25V

VOLTAGE=1.5V

PP1V5_S0_NB_VCCD_TVDAC

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.3 MM

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.25V

MIN_LINE_WIDTH=0.3 MM

PP1V25_S0_NB_VCCA_DPLLB

PP1V25_S0_NB_DPLL

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.25V

MIN_LINE_WIDTH=0.4 MM

PP1V8_S0

P1V25S0NBDPLL_NR

GND

GND GND

GND

91

64 34

88

50

88 88

88

27

50

30

22

30 30

30

26

66

22

66

29

21

29 29

29

19

60

58

21

58

22

18

22 22

22

12

18

22

18

22

16

16 16

16

11

8

19

16

19

7

8

7 7

7

8

7

8

19

8

19

8

http://24hcongnghe.org

SATA0RXP

SATA0RXN

SATALED*

RTCRST*

HDA_BIT_CLK

DDREQ

RTCX1 RTCX2

DCS1* DCS3*

IDEIRQ

DDACK*

IORDY

DIOR* DIOW*

DD11 DD12

DD4

DD2

DD14

DD0

DD15

DD1

DD13

DD5

DD10

DD8

DD3

DD9

LDRQ0*

FWH2/LAD2 FWH3/LAD3

FWH1/LAD1

LDRQ1*/GPIO23

FWH0/LAD0

FWH4/LFRAME*

HDA_SDIN0

HDA_SYNC

SATA1TXN SATA1TXP

HDA_SDIN1 HDA_SDIN2

RCIN*

SATA0TXP

SATA0TXN

CPUPWRGD/GPIO49

SMI*

A20M*

SATA1RXP

SATA1RXN

SATARBIAS

SATARBIAS*

IGNNE*

DPRSTP*

INTVRMEN

A20GATE

SATA2RXN SATA2RXP

THRMTRIP*

DPSLP*

INIT*

HDA_RST*

HDA_SDOUT

HDA_DOCK_EN*/GPIO33

SATA2TXN SATA2TXP

FERR*

NMI

HDA_SDIN3

INTR

SATA_CLKP

SATA_CLKN

DA2

DD6

STPCLK*

TP8

DA0 DA1

HDA_DOCK_RST*/GPIO34

INTRUDER*

LAN_TXD0

LAN100_SLP

LAN_RSTSYNC

LAN_RXD0 LAN_RXD1 LAN_RXD2

DD7

LAN_TXD2

LAN_TXD1

GLAN_DOCK*/GPIO13

GLAN_COMPI GLAN_COMPO

GLAN_CLK

LAN/GLANIHDA

CPU

RTC

LPC

(1 OF 6)

SATA

IDE

OUT

IN

BI

BI BI

BI

OUT

IN

OUT

IN

IN OUT OUT

IN

OUT

IN

OUT OUT

IN

OUT

OUT OUT OUT

IN IN IN

BI

OUT OUT OUT

OUT

OUT OUT

OUT

OUT OUT

IN

OUT OUT

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

INT PU

INT PD

HDA

24.000MHZ CLOCK W/INTERNAL WEAK PD

HDA_BIT_CLK HDA_RST# HDA_SDIN[0-2] HDA_SDOUT ACZ_SYNC

INTEGRATED PDs INTEGRATED PD INTEGRATED PD

INT PDINT PU

INT PD

INT PU

NOTE: ALL IDE PINS HAVE INTERNAL 33-OHM SERIES R’S

ICH8M

BGA

OMIT

U2300

AF13 AG26

AG29

AA4 AA1 AB3

Y6 Y5

V1 U2

T4 V6 V5 U1 V2 U6

V3 T1 V4 T5 AB2 T6 T3 R2

Y2

W5

W4 W3

AF26 AE26

AD24

E5 F5 G8 F6

C4

B24

D25 C25

AH21

AJ16

AE10 AG14

AE14

AJ17 AH17 AH15 AD13

AE13

AJ15

Y3

AF27

AE24 AC20

AD22

AF25

Y1

AD21

D22

C21 B21 C22

D21 E20 C20

G9 E6

AD23

AH14

AF23

AG25 AF24

AF6 AF5 AH5 AH6

AG3 AG4 AJ4 AJ3

AF2 AF1 AE4 AE3

AB7 AC6

AF10

AG2

AG1

AG28

AA24

AE27

AA23

28

7

28

7

45 47

7

45 47

7

45 47

7

45 47

28 58 66

7

45 47

10 83

NO STUFF

2.2K

5% 1/16W MF-LF

402

R2304

1

2

1/16W MF-LF

24.9

1%

402

R2302

1

2

1/16W 402

MF-LF

332K

1%

R2301

1

2

80 86

42 86

29 30 88

23 42 86

7

10 16 59 83

7

10 83

7

10 13 83

42 86

7

10 83

10 47 83

10 83

1/16W

5%

402

MF-LF

10K

R2306

1

2

10 16 46 83

402

24.9

1/16W MF-LF

1%

PLACEMENT_NOTE=Place R2308 within 50mm of U2300

R2308

1 2

34 86

MF-LF

402

332K

1%

1/16W

R2300

1

2

402

MF-LF

1/16W

5%

8.2K

R2303

1

2

34 86

8.2K

5% 1/16W MF-LF

402

R2310

1

2

54.9

402

MF-LF

1/16W

1%

R2305

1

2

PLACEMENT_NOTE=Place R2309 within 50mm of R2308 (NO STUB)

54.9

402

MF-LF

1/16W

1%

R2309

1

2

5%

1/16W MF-LF33402

R2313

1 2

402

33

MF-LF1/16W

5%

R2314

1 2

4025%

MF-LF

33

1/16W

R2315

1 2

33

402

MF-LF1/16W

5%

R2316

1 2

5%

10K

MF-LF 402

1/16W

R2311

1

2

42 86

SB Enet, Disk, FSB, LPC

SYNC_DATE=01/25/2007

SYNC_MASTER=T9_NOME

051-7261

9223

10.0.0

TP_HDA_SDIN2 TP_HDA_SDIN3

HDA_SDIN0

TP_LAN_D2R<1>

TP_ENET_GLAN_CLK

TP_HDA_SDIN1

SATA_A_D2R_N

HDA_SDOUT

HDA_RST_L

HDA_BIT_CLK HDA_SYNC

HDA_SDOUT_R

HDA_RST_L_R

HDA_SYNC_R

HDA_BIT_CLK_R

SATA_RBIAS SATA_RBIAS

SB_CLK100M_SATA_N SB_CLK100M_SATA_P

TP_SATA_C_R2DP

TP_SATA_C_R2DN

TP_SATA_C_D2RN TP_SATA_C_D2RP

TP_SATA_B_R2DP

TP_SATA_B_R2DN

TP_LAN_R2D<1>

TP_LAN_D2R<0>

TP_LAN_RSTSYNC

TP_LAN_R2D<0>

TP_HDA_DOCK_RST_L

TP_SATA_B_D2RN TP_SATA_B_D2RP

SATA_A_R2D_C_N SATA_A_R2D_C_P

TP_SB_SATALED_L

SATA_A_D2R_P

TP_LAN_D2R<2>

TP_SB_TP8

SB_RCIN_L

TP_LPC_DRQ0_L

SB_A20GATE

CPU_FERR_L

PP3V3_S0

PP1V05_S0

IDE_PDDREQ

IDE_PDIORDY

IDE_IRQ14

IDE_PDDACK_L

IDE_PDIOR_L IDE_PDIOW_L

IDE_PDCS1_L IDE_PDCS3_L

IDE_PDA<2>

IDE_PDA<1>

IDE_PDA<0>

IDE_PDD<14> IDE_PDD<15>

IDE_PDD<13>

IDE_PDD<11> IDE_PDD<12>

IDE_PDD<9> IDE_PDD<10>

IDE_PDD<8>

IDE_PDD<6> IDE_PDD<7>

IDE_PDD<5>

IDE_PDD<4>

IDE_PDD<3>

IDE_PDD<1> IDE_PDD<2>

IDE_PDD<0>

CPU_STPCLK_L

CPU_SMI_L

CPU_NMI

CPU_INTR

CPU_INIT_L

CPU_IGNNE_L

CPU_PWRGD

CPU_DPRSTP_L CPU_DPSLP_L

CPU_A20M_L

CPU_THERMTRIP_R

PM_THRMTRIP_L

EXTGPU_PWR_EN

LPC_FRAME_L

LPC_AD<3>

LPC_AD<1>

LPC_AD<0>

LPC_AD<2>

TP_LAN_R2D<2>

SB_RTC_X1 SB_RTC_X2

SB_RTC_RST_L SB_SM_INTRUDER_L

SB_LAN100_SLP

SB_INTVRMEN

HDA_DOCK_EN_L

PP3V3_G3_SB_RTC

GLAN_COMP

PP1V5_S0_SB_VCC1_5_B

PP3V3_S0

LAN_ENERGY_DET

91

81

79

77

76

66

60

59

58

53

52

51

50

48

47

46

42

32

62

32

31

50

31

30

46

30

29

30

29

28

27

28

27

26

27

26

21

26

25

19

25

24

18

24

23

14

23

21

13

21

19

12

19

16

11

28

27

16

13

10

27

26

13

86

8

7

26

87

24

8

http://24hcongnghe.org

SPI_CS1*

PETN1

PERP1

OC4*/GPIO43 OC5*/GPIO29 OC6*/GPIO30 OC7*/GPIO31 OC8* OC9*

SPI_MOSI

OC0* OC1*/GPIO40 OC2*/GPIO41 OC3*/GPIO42

PERN5

DMI1RXN DMI1RXP DMI1TXN DMI1TXP

DMI0RXN DMI0RXP DMI0TXN DMI0TXP

DMI_CLKN DMI_CLKP

PETP1

USBP9N USBP9P

PERN2

USBP7N USBP7P USBP8N USBP8P

PETN2

USBP6N USBP6P

PERP3

USBP4N USBP4P USBP5N USBP5P

PETN3 PETP3

USBP3N USBP3P

PERN4 PERP4

USBP1N USBP1P USBP2N USBP2P

PETN4 PETP4

USBP0N USBP0P

PERP5

SPI_MISO

USBRBIAS

USBRBIAS*

PETP5

PERN6/GLAN_RXN PERP6/GLAN_RXP PETN6/GLAN_TXN PETP6/GLAN_TXP

SPI_CLK SPI_CS0*

DMI3RXN DMI3RXP DMI3TXN DMI3TXP

DMI2RXN DMI2RXP DMI2TXN DMI2TXP

DMI_IRCOMP

DMI_ZCOMP

PERN1

PERP2

PETP2

PERN3

PETN5

PCI_EXPRESS

DIRECT MEDIA INTERFACE

SPI

USB

(2 OF 6)

IN

IN OUT OUT

IN

IN OUT OUT

IN

IN OUT OUT

IN

IN OUT OUT

IN

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

IN IN OUT OUT

BI BI

BI

AD4 AD5

AD9

PIRQF*/GPIO3

PIRQE*/GPIO2

AD13

PME*

PCIRST*

GNT2*/GPIO53

C/BE2*

PIRQG*/GPIO4

SERR*

PIRQA*

AD1

REQ1*/GPIO50

C/BE3*

AD11

C/BE1*

AD25 AD26

AD0

AD2

DEVSEL*

AD18

AD21

PAR

GNT0*

AD7

GNT1*/GPIO51

C/BE0*

STOP*

AD20

AD16

GNT3*/GPIO55

TRDY*

IRDY*

AD22

PIRQC*

REQ2*/GPIO52

AD19

PCICLK

PLOCK*

AD15

PIRQB*

PIRQH*/GPIO5

PLTRST*

AD3

AD6

AD8

FRAME*

AD14

AD12

AD10

REQ3*/GPIO54

PIRQD*

AD17

PERR*

REQ0*

AD31

AD27 AD28

AD30

AD29

AD24

AD23

(3 OF 6)

INTERRUPT I/F

PCI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

IN

BI

BI BI

OUT

BI BI BI

BI

OUT

IN

BI BI

IN

IN IN IN

OUT

IN

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NOTE: GNT[0-3]# have internal 20K pull-ups enabled only when PCIRST# = 0 and PWROK = 1

If used, ensure GNT2# is not low when PWROK rises, or PCIe ports 5 & 6 will be disabled.

FireWire INT*

INT PU

Provide a pull-down on this GPIO if not used.

R2415 pull-down on GNT0# selects SPI ROM by default.

SB BOOT BIOS SELECT

I/F LPC

Nineveh-GLCI

Yukon-PCIE

PCIe Mini Card

SPI

NOTE:

0

GNT0#

1

GNT0# HAS INT PU; ENABLED ONLY WHEN PCIRST#=0 AND PWROK=H SPI_CS1# HAS INT PU (NOMINAL=20K, SIMULATION=15K-35K)

high for x2)

pull HDA_SYNC

(x2-capable,

Ethernet

(AirPort)

FireWire

ExpressCard

Spares

INT PD

INT PD INT PD

EHCI1

INT PU INT PU

INT PU

INT PD

INT PD INT PD

INT PD

EHCI0

INT PD

INT PD INT PD INT PD INT PD

INT PD

External C

Camera

AirPort (PCIe Mini-Card)

ExpressCard

External B

Geyser Trackpad/Keyboard

External A

External D / WWAN

Bluetooth

IR

NOTE: USBP[0-9]P/N have internal 15K pull-downs.

MF-LF

5%

10K

402

1/16W

R2408

1

2

1/16W MF-LF 402

10K

5%

R2407

1

2

10K

402

5% 1/16W MF-LF

R2400

1

2

10K

1/16W 402

MF-LF

5%

R2409

1

2

MF-LF 402

5%

10K

1/16W

R2401

1

2

402

5% 1/16W MF-LF

10K

R2402

1

2

402

1/16W

10K

MF-LF

5%

R2404

1

2

10K

MF-LF 402

1/16W

5%

R2403

1

2

BGA

ICH8M

OMIT

U2300

V27 V26 U29 U28

Y27 Y26 W29 W28

AB26 AB25 AA29 AA28

AD27 AD26 AC29 AC28

T26 T25

Y24

Y23

AJ19 AG16 AG15 AE15 AF15 AG17 AD12 AJ18 AD14 AH18

P27

M27

K27

H27

F27

D27

P26

M26

K26

H26

F26

D26

N29

L29

J29

G29

E29

C29

N28

L28

J28

G28

E28

C28

C23 B23 E22

F21

D23

G3 G2 H5 H4 H2 H1 J3 J2 K5 K4 K2 K1 L3 L2 M5 M4 M2 M1 N3 N2

F3

F2

16 84

29 30 88

1% 402

MF-LF1/16W

24.9

R2413

1 2

43 86

34 86

44 86

7

80 86

7

80 86

34 86

22.6

MF-LF

402

1%

1/16W

R2414

1 2

34 87

35 87

56 86

ICH8M

BGA

OMIT

U2300

D20 E19

A12 E16 A14 G16 A15

B6

C11

A9 D11 B12

D19

C12 D10

C7 F13 E11 E13 E12

D8

A6

E8

A20

D6

A3

D17 A21 A19 C19 A18 B16 C17

E15 F16 E17

D16

A17

D7

C18

F18

C10

C8 D9

B10

G6

A7

F9

B5

C5 A10

F8 G11 F12 B3

B7

AG24

G7

A4

E18

B19

A11

F10 C16 C9

38 87

24 87

24 38 87

24 87

24 38 87

24 87

38 87

24 38 87

38 87

7

28

24 38 87

24 87

24 38 87

7 9

28 79 81

30 88

24 87

5%

402

MF-LF

1/16W

10K

R2405

1

2

402

1/16W

5%

MF-LF

10K

R2406

2

1

402

5% 1/16W MF-LF

1K

R2415

1

2

8.2K

R2423

1 2

8.2K

R2424

1 2

8.2K

R2425

1 2

8.2K

R2426

1 2

8.2K

R2427

1 2

8.2K

R2428

1 2

8.2K

R2430

1 2

8.2K

R2429

1 2

8.2K

R2432

1 2

8.2K

R2431

1 2

8.2K

R2433

1 2

8.2K

R2437

1 2

8.2K

R2439

1 2

8.2K

R2438

1 2

8.2K

R2436

1 2

8.2K

R2440

1 2

24 87

8.2K

R2441

1 2

13 43

13

13 34

34 46

34

24 42

78

7

24 38 47 87

42 86

13

7

24 38 47 87

13 79

8.2K

R2442

1 2

13

13 36

13

SYNC_DATE=01/25/2007

051-7261

9224

10.0.0

SYNC_MASTER=T9_NOME

SB PCI, PCIe, DMI, USB

DMI_N2S_N<0> DMI_N2S_P<0> DMI_S2N_N<0> DMI_S2N_P<0>

DMI_N2S_N<1> DMI_N2S_P<1> DMI_S2N_N<1> DMI_S2N_P<1>

DMI_N2S_N<2> DMI_N2S_P<2> DMI_S2N_N<2> DMI_S2N_P<2>

DMI_N2S_N<3> DMI_N2S_P<3> DMI_S2N_N<3> DMI_S2N_P<3>

SB_CLK100M_DMI_N SB_CLK100M_DMI_P

USB_EXTA_N USB_EXTA_P USB_MINI_N USB_MINI_P USB_WWAN_N USB_WWAN_P

USB_CAMERA_P

USB_CAMERA_N

USB_IR_N USB_IR_P USB_TPAD_N

USB_BT_N

USB_TPAD_P

USB_BT_P USB_EXTB_N USB_EXTB_P USB_EXCARD_N

USB_EXTC_N

USB_EXCARD_P

USB_EXTC_P

PCIE_MINI_R2D_C_N

PCIE_EXCARD_D2R_N

TP_PCIE_B_R2D_C_P

TP_PCIE_B_D2R_P

TP_PCIE_A_D2R_N

SPI_CE_R_L<0>

SPI_SCLK_R

PCIE_ENET_R2D_C_P

PCIE_ENET_R2D_C_N

PCIE_ENET_D2R_P

PCIE_ENET_D2R_N

PCIE_MINI_R2D_C_P

SPI_SO

PCIE_MINI_D2R_P

TP_PCIE_FW_R2D_C_P

TP_PCIE_FW_R2D_C_N

TP_PCIE_FW_D2R_P

TP_PCIE_FW_D2R_N

PCIE_EXCARD_R2D_C_P

PCIE_EXCARD_R2D_C_N

PCIE_EXCARD_D2R_P

TP_PCIE_B_R2D_C_N

TP_PCIE_B_D2R_N

PCIE_MINI_D2R_N

USB_EXTD_OC_L

SPI_SI_R

EXCARD_OC_L

USB_EXTB_OC_L

PM_LATRIGGER_L

TP_PCIE_A_D2R_P TP_PCIE_A_R2D_C_N

TP_SPI_CE_R_L<1>

DMI_IRCOMP_R

USB_RBIAS

PP1V5_S0_SB_VCC1_5_B

PP3V3_S0

PCI_PERR_L

PCI_DEVSEL_L

PCI_SERR_L

ODD_PWR_EN_L

INT_PIRQC_L

INT_PIRQF_L

PCI_LOCK_L PCI_FW_REQ_L

PCI_FRAME_L PCI_IRDY_L

PCI_STOP_L

PCI_REQ2_L INT_PIRQA_L

INT_PIRQB_L

INT_PIRQD_L INT_PIRQE_L

PCI_TRDY_L

PCI_REQ1_L

TP_PCIE_A_R2D_C_P

SB_GPIO30

USB_EXTC_OC_L

EXTGPU_LVDS_EN

USB_EXTA_OC_L SB_GPIO40

PP3V3_S5

PCI_FW_GNT_L

MAKE_BASE=TRUE

PCI_FW_GNT_L

TP_PCI_PME_L

TP_SB_GPIO53

PCI_REQ1_L TP_SB_GPIO51

TP_SB_GPIO55

PCI_FW_REQ_L

PCI_REQ2_L

ODD_RST_5VTOL_L

PCI_C_BE_L<2>

PCI_C_BE_L<0> PCI_C_BE_L<1>

PCI_C_BE_L<3>

PCI_IRDY_L PCI_PAR PCI_RST_L

PCI_PERR_L

PCI_DEVSEL_L

PCI_LOCK_L PCI_SERR_L PCI_STOP_L

PCI_FRAME_L

PCI_TRDY_L

PCI_CLK33M_SB

PLT_RST_L

INT_PIRQF_L

INT_PIRQE_L

DVI_HOTPLUG_DET ODD_PWR_EN_L

PCI_AD<0>

PCI_AD<2>

PCI_AD<1>

PCI_AD<3> PCI_AD<4> PCI_AD<5> PCI_AD<6>

PCI_AD<8>

PCI_AD<7>

PCI_AD<9> PCI_AD<10> PCI_AD<11>

PCI_AD<13>

PCI_AD<12>

PCI_AD<14> PCI_AD<15> PCI_AD<16>

PCI_AD<18>

PCI_AD<17>

PCI_AD<19> PCI_AD<20> PCI_AD<21> PCI_AD<22>

PCI_AD<24>

PCI_AD<23>

PCI_AD<25> PCI_AD<26> PCI_AD<27> PCI_AD<28> PCI_AD<29> PCI_AD<30> PCI_AD<31>

INT_PIRQB_L

INT_PIRQA_L

INT_PIRQC_L INT_PIRQD_L

WOW_EN

91

81 79 77 76 66 60 59 58 53 52 51 50 48 47 46 42 32 31

91

30

77

29

66

28

61

27

58

26

56

25

48

23

46

21

28

19

27

16

87

26

87

26

13

38

42

87

38

87

38

87

38

87

25

34

86

23

8

24

8

http://24hcongnghe.org

OUT OUT

BI

IN

BI

IN IN

SMBALERT*/GPIO11

STP_PCI*/GPIO15

BMBUSY*/GPIO0

SYS_RESET*

SUS_STAT*/LPCPD*

QRT_STATE0/GPIO27

THRM*

SMLINK0

GPIO12

SPKR

SDATAOUT1/GPIO48

QRT_STATE1/GPIO28

SLP_S5*

GPIO20

GPIO8

WAKE*

CL_CLK1

BATLOW*

PWROK

SLOAD/GPIO38

SATA2GP/GPIO36

SERIRQ

RI*

CL_DATA1

SLP_S4*

EC_ME_ALERT/GPIO14

TACH0/GPIO17

CLK14

SCLOCK/GPIO22

SATA3GP/GPIO37

SATACLKREQ*/GPIO35

STP_CPU*/GPIO25

WOL_EN/GPIO9

LINKALERT*

SLP_S3*

RSMRST*

TACH3/GPIO7

CLKRUN*/GPIO32

GPIO18

LAN_RST*

CL_VREF1

S4_STATE*/GPIO26

TACH1/GPIO1 TACH2/GPIO6

SATA1GP/GPIO19

SDATAOUT0/GPIO39

SATA0GP/GPIO21

MCH_SYNC*

DPRSLPVR/GPIO16

VRMPWRGD

TP3

TP7

CL_RST*

ME_EC_ALERT/GPIO10

SLP_M*

MEM_LED/GPIO24

PWRBTN*

SUSCLK

CL_VREF0

CK_PWRGD

CLPWROK

CL_DATA0

CL_CLK0

CLK48

SMBCLK SMBDATA

SMLINK1

MISC

SYS GPIO

SMB

CLOCKS

POWER MGT

CONTROLLER LINK

GPIO

SATA

GPIO

(4 OF 6)

IN IN

OUT

IN

BI BI

OUT

IN

OUT

IN

BI

OUT

BI

IN

OUT OUT

OUT

IN

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

See note below

have been up for at least 1ms.

PM_LAN_ENABLE must remain deasseted until VccCL3_3, VccLAN3_3 and VccLAN1_05

INT PU

NOTE: ICH CLPWROK input must be PWRGD signal for PP3V3_S0M, PP3V3_S0MWOL, PP1V8_S3M, PP1V25_S0M, PP1V05_S0M, PP0V9_S3M and PP0V9_S0M. If ME/AMT is not used, short CLPWROK to PWROK.

PLACE R2511-16 WHERE PHYSICALLY ACCESSIBLE

LAYOUT NOTE:

INT PU INT PU INT PU

INT PD

INT PU

for XOR chain testing.

Test access required

INT PU

AT BOOT/RESET FOR STRAPPING FUNCTION

NOTE: DPRSLPVR HAS INT 20K PD ENABLED

INT PU

7

29 30

7

29 30

7

45 47

34 35

7

45 47

45

13 45

402

100K

5% 1/16W MF-LF

R2514

1

2

402

MF-LF

1/16W

5%

10K

R2515

1

2

402

0

5% 1/16W MF-LF

ARB_ONLY

R2516

1

2

402

10K

5% 1/16W MF-LF

R2511

1

2

402

NOSTUFF

0

5% 1/16W MF-LF

R2512

1

2

402

MF-LF

10K

5%

1/16W

R2502

1

2

1/16W MF-LF

5%

10K

402

R2504

1

2

402

MF-LF

1/16W

5%

1K

R2500

1

2

MF-LF

1/16W

5%

8.2K

402

R2507

1

2

MF-LF

1/16W

10K

5%

402

R2506

1

2

MF-LF

5%

8.2K

1/16W

402

R2505

1

2

ICH8M

BGA

OMIT

U2300

AE21

AG12

E1

F23 AE18

F22 AF19

AJ23

D24 AH23

AG9 G5

AH11

E3

AJ14

AF22

AC19

AH12 AE11

AE16

AH20

AG21

AJ13 AJ24

AJ27

C2

AE23

AH25 AD16

AF17

AG27

AH27

AJ12 AJ10 AF11 AG11

AG13

AG10

AJ11 AD10

AF12

AF9

AJ25

AG23 AF21 AD18

AG22

AJ26 AD19

AC17 AE19

AD9

AG18

AE20

F4 D3

AD15

AG8

AJ8 AJ9 AH9

AC13

AJ21

AJ22

AJ20

AE17

AG19

30 88

45 46

7

35 36 40 45 49 58 63 66

MF-LF

NO_REBOOT_MODE

1K

5% 1/16W

402

R2510

1

2

7

45 46

7

16 59 83

7 9

25 28

25 45

7

45

29 31 32 34 48 86

7

45 46 47

7

28 45

7

16

7

28

25 38

7

16

7

34 43 45 58 66

29

7 9

25 28

16 87

MF-LF

1/16W

1%

3.24K

402

R2526

1

2

MF-LF

1/16W

1%

453

402

R2527

1

2

X5R

0.1uF

10% 16V

402

C2500

1

2

453

MF-LF

1% 1/16W

402

R2529

1

2

MF-LF

1/16W

1%

3.24K

402

R2528

1

2

0.1uF

X5R

10% 16V

402

C2501

1

2

16 87

25

100K

5% 1/16W MF-LF

402

R2523

1

2

48 86

25

402

1%

MF-LF

10K

1/16W

R2536

1 2

402

8.2K

1/16W MF-LF

5%

R2544

1 2

402

1%

1/16W

10K

MF-LF

R2545

1 2

402

1%

MF-LF

1/16W

10K

R2531

1 2

402

1%

MF-LF

1/16W

10K

R2530

1 2

402

5% 1/16W MF-LF

10K

R2525

1

2

7

25 47

25

28

29

402

10K

5% 1/16W MF-LF

R2534

2

1

5%

10K

1/16W MF-LF

402

R2552

1

2

402

1/16W

5%

MF-LF

10K

R2550

1

2

8.2K

5% 1/16W MF-LF 402

R2553

1

2

402

MF-LF

5%

8.2K

1/16W

R2551

1

2

7

45

402

10K

1/16W MF-LF

1%

R2598

1 2

402

10K

1/16W MF-LF

1%

R2546

1 2

1/16W

5%

402

MF-LF

10K

R2532

2

1

10K

MF-LF

5%

1/16W

402

R2533

2

1

5%

402

10K

MF-LF

1/16W

R2535

2

1

79

402

10K

MF-LF

1/16W

5%

R2547

2

1

MF-LF

1/16W

5%

402

100K

R2524

1

2

SB Pwr Mgt, GPIO, Clink

SYNC_DATE=01/25/2007

SYNC_MASTER=T9_NOME

051-7261

9225

10.0.0

SATA_B_DET_L

TP_CLINK_WLAN_DATA

SB_CLINK_VREF0

ARB_DETECT_L SB_GPIO10_CL1 SB_GPIO14_CL2 WOL_EN

PM_SLP_S3_L

SB_CLK14P3M_TIMER

SB_CLINK_VREF1

PCI_PME_FW_L

SATA_B_PWR_EN_L

INT_SERIRQ

SMC_WAKE_SCI_L

PP3V3_S5

SB_SCLOCK

SB_SLOAD

PM_THRM_L VR_PWRGD_CLKEN

PM_SUS_STAT_L

NB_SB_SYNC_L

SB_SATA_CLKREQ_L

LINDACARD_GPIO

PM_BMBUSY_L

CLINK_NB_DATA

TP_CLINK_WLAN_CLK

PM_BATLOW_L

PM_S4_STATE_L PM_SB_PWROK

PM_SLP_S5_L

TP_PM_SLP_S4_L

PM_SYSRST_L

SMBUS_SB_ME_SDA

SMBUS_SB_SDA

TP_SB_TP7

TP_SB_TP3

FWH_MFG_MODE

SATA_B_PWR_EN_L

PP3V3_S0

SB_GPIO14_CL2

LAN_PHYPC

SB_GPIO10_CL1

PM_BATLOW_L

PM_RI_L LINDACARD_GPIO ARB_DETECT_L

FWH_MFG_MODE

PP3V3_S5

PM_STPCPU_L PM_CLKRUN_L

TP_SB_GPIO6

CLK_PWRGD

PM_DPRSLPVR

SB_SDATAOUT<0> SB_SDATAOUT<1>

TP_SB_GPIO20

SB_GPIO18

EXTGPU_RST_L

LAN_PHYPC

PCI_PME_FW_L

SB_SPKR

SMBUS_SB_SCL

SMBUS_SB_ME_SCL

SMC_RUNTIME_SCI_L

PM_PWRBTN_L

TP_CLINK_WLAN_RESET_L

SUS_CLK_SB

SB_CLK48M_USBCTLR

PP3V3_S5

CLINK_NB_RESET_L

PCIE_WAKE_L

PM_RI_L

CLINK_NB_CLK

TP_PM_SLP_M_L

PM_SB_PWROK

PM_RSMRST_L

PM_LAN_ENABLE

PP3V3_S5

PM_STPPCI_L

RSVD_EXTGPU_LVDS_EN

SB_CRT_TVOUT_MUX_L

PP3V3_S0

SB_GPIO36

PP3V3_S0

91

81

79

77

76

66

60

59

58

53

52

51

50

48

47

46

42

32

91

31

91

31

77

30

77

30

66

29

66

29

61

28

61

28

58

27

58

27

56

26

56

26

48

25

48

25

46

24

46

24

28

23

28

23

27

21

27

21

26

19

26

19

25

16

47

25

16

87

38

24

87

13

45

25

24

87

24

13

34

87

25

36

87

25

8

34

25

8

25

7

25

8

34

8

http://24hcongnghe.org

VSS

VSS_NCTF

VSS

(5 OF 6)

VCC1_5_B

V5REF_SUS

VCCDMIPLL

VCC_DMI

VCC3_3

VCC1_05

V5REF

VCCCL1_5

VCCGLANPLL

VCC3_3

VCC1_5_A

VCC3_3

VCCHDA

VCCSUS1_5

VCCSUS3_3

V_CPU_IO

VCC3_3

VCCSUSHDA

VCC1_5_A

VCC3_3

VCCSATAPLL

VCCGLAN3_3

VCCSUS3_3

VCCLAN3_3

VCCCL1_05

VCCSUS1_05

VCCSUS1_5

VCCSUS3_3

VCCA3GP

VCCGLAN1_5

VCCCL3_3

VCCLAN1_05

VCC1_5_A24

VCC1_5_A

VCCRTC

VCC1_5_A

VCCUSBPLL

VCC1_5_A

GLAN POWER

USB CORE

ATX ARX

(6 OF 6)

VCCPSUS

IDE

COREVCCP CORE

PCI

VCCPUSB

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

19 mA S0, 51 mA M1 & WOL

1 mA

80 mA

23 mA

10 mA

19 mA S0, 63 mA M1 & WOL

(VCC1_5_A total)

47 mA

1080 mA

32 mA

(VCCSUS3_3 total)

1 mA S3-S5

44 mA S3-S5

11 mA S0,

117 mA S0,

442 mA

(VCC3_3 total)

1 mA

50 mA

23 mA

1130 mA

NOTE: VccHDA and VccSusHDA can be 1.5V or 3.3V depending on VIO of HD Audio interface.

Current figures provided assume 1.5V.

Current numbers from ICH8M Max Power Estimates Rev 2.0, doc #610194.

657 mA

1 mA S0-S5

1 mA

6 uA S0-G3

1uF

6.3V CERM

10%

402

C2600

1

2

402

CERM

10V

20%

0.1uF

C2601

1

2

ICH8M

BGA

OMIT

U2300

A23

A5

AC26

L13 L15 L26 L27 L4 L5 M12 M13 M14 M15

AC27

M16 M17 M23 M28 M29 M3 N1 N11 N12 N13

AD17

N14 N15 N16 N17 N18 N26 N27 N4 N5 N6

AD20

P12 P13 P14 P15 P16 P17 P23 P28 P29 R11

AD28

R12 R13 R14 R15 R16 R17 R18 R28 R4 T12

AD29

T13 T14 T15 T16 T17 T2 U12 U13 U14 U15

AD3

U16 U17 U23 U26 U27 U3 U5 V13 V15 V28

AD4

V29 W2 W26 W27 Y28 Y29 Y4 AB4 AB23 AB5

AD6

AB6 AD5 U4 W24

AE1

AA2

AE12

AE2

AE22

AD1

AE25

AE5 AE6

AE9 AF14 AF16

AA7

AF18

AF3

AF4

AG5

AG6 AH10 AH13 AH16 AH19

AH2

A25

AF28 AH22 AH24 AH26

AH3

AH4

AH8

AJ5

B11

B14

AB1

B17

B2 B20 B22

B8 C24 C26 C27

C6 D12

AB24

D15 D18

D2

D4 E21 E24

E4

E9 F15 E23

AC11

F28 F29

F7

G1

E2 G10 G13 G19 G23 G25

AC14

G26 G27 H25 H28 H29

H3

H6

J1 J25 J26

AC25

J27

J4

J5 K23 K28 K29

K3

K6

K7 L1

A1 A2

B1 B29

A28 A29 AH1 AH29 AJ1 AJ2 AJ28 AJ29

BGA

ICH8M

OMIT

U2300

A16

T7

G4

AC23 AC24

A13 B13

L14 L16 L17 L18 M11 M18 P11 P18 T11 T18

C13

U18 V17 V14 V11 U11 V18 V16 V12

C14 D14 E14 F14 G14 L11 L12

AE7 AF7

AC10

AC9

AA5 AA6

G12 G17

H7

AC7 AD7

F1

AG7

L6 L7 M6 M7

W23

AH7 AJ7

AC1 AC2 AC3 AC4 AC5

AA25 AA26

E27 F24 F25 G24 H23 H24 J23 J24 K24 K25

AA27

L23 L24 L25 M24 M25 N23 N24 N25 P24 P25

AB27

R24 R25 R26 R27 T23 T24 T27 T28 T29 U24

AB28

W25 V24 U25 Y25 V25 V23

AB29

D28 D29 E25 E26

AF29

AD2

W6 W7 Y7

A8 B15 B18 B4 B9 C15 D13

AC8

D5 E10 E7 F11

AD8 AE8 AF8

AA3 U7 V7 W1

AE28 AE29

G22

A22

F20 G21

R29

B27 A27 B28 B26 A26

B25

A24

AC12

F17 G18

F19 G20

AD25

AJ6

J6 AF20

AC16

J7

C3

AC18

P1 P2 P3 P4 P5 R1 R3 R5 R6

AC21 AC22 AG20 AH28

P6 P7 C1 N7

AD11

D1

SYNC_MASTER=T9_NOME

051-7261

9226

10.0.0

SYNC_DATE=01/25/2007

SB Power & Ground

PP1V05_S0

PP3V3_S0

PP1V5_S0_SB_VCC1_5_B

PP5V_S0_SB_V5REF

VCCCL1_5V

PP1V05_S0

PP1V25_S0

PP1V5_S0

PP3V3_S5

PP3V3_S0

PP1V5_S0

PP3V3_S0

PP1V5_S0_SB_VCC1_5_B

PP5V_S5_SB_V5REF_SUS

PP1V5_S0_SB_VCCDMIPLL

PP1V5_S0

PP3V3_S0

TP_VCCSUS1_5_INTERNAL_REG1

PP3V3_S0

PP3V3_S5

PP3V3_S0

PP1V5_S0_SB_VCCSATAPLL

PP3V3_S0

TP_VCCCL1_05_INTERNAL_REG

TP_VCCSUS1_05_INTERNAL_REG1

TP_VCCSUS1_5_INTERNAL_REG2

TP_VCCSUS1_05_INTERNAL_REG2

TP_VCCLAN1_05_INTERNAL_REG2

TP_VCCLAN1_05_INTERNAL_REG1

PP3V3_G3_SB_RTC

PP1V5_S0

PP3V3_S0

91

81

79

77

76

66

60

59

58

53

52

51

50

48

47

46

62

42

62

42

50

32

50

32

46

31

46

91

31

91

31

30

77

30

77

30

27

29

27

66

29

66

29

26

28

26

61

28

61

28

23

27

23

91

58

27

91

27

91

27

58

27

91

27

21

26

21

64

56

26

64

26

64

26

56

26

64

26

19

25

19

34

48

25

34

25

34

25

48

25

34

25

18

24

18

27

46

24

27

24

27

24

46

24

27

24

14

23

14

66

26

28

23

26

23

26

23

28

23

26

23

13

21

13

58

22

27

21

22

21

22

21

27

21

22

21

12

19

27

12

27

19

26

19

27

19

26

19

11

16

26

11

21

12

25

16

12

16

26

12

16

25

16

28

12

16

10

13

24

10

19

11

24

13

11

13

24

11

13

24

13

27

11

13

8

23

27

8

23

27

8

27

8

23

8

http://24hcongnghe.org

NCNC

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(ICH Reference for 5V Tolerance on Resume Well Inputs)

PLACEMENT NOTE:

ON SECONDARY SIDE OR 3.56MM ON PRIMARY

(ICH Reference for 5V Tolerance on Core Well Inputs)

PLACE C2704 < 2.54MM OF PIN G4 OF SB

PLACEMENT NOTE:

ICH V5REF_SUS Filter & Follower

ICH VCC1_5_A/ARX BYPASS (ICH LOGIC&IO[ARX] 1.5V PWR)

(ICH LOGIC&IO[ATX] 1.5V PWR)

ICH VCC1_5_A/ATX BYPASS

PLACE < 2.54MM OF SB ON SECONDARY OR

3.56MM ON PRIMARY NEAR PINS AE7..AJ7

PLACEMENT NOTE:

PLACE < 2.54MM OF SB ON SECONDARY OR

PLACEMENT NOTE:

(ICH USB CORE 1.5V PWR)

PLACE < 2.54MM OF SB ON SECONDARY OR

ICH USB CORE/VCC1_5_A BYPASS

3.56MM ON PRIMARY NEAR PINS F1..M7

PLACE C2715 NEAR PIN D1 OF SB

ICH VCCUSBPLL BYPASS (ICH USB PLL 1.5V PWR)

PLACEMENT NOTE:

PLACE < 2.54MM OF SB ON SECONDARY OR 3.56MM ON PRIMARY NEAR PIN AE29

PLACE NEAR PINS AC23,AC24 OF SB

PLACEMENT NOTE:

3.56MM ON PRIMARY NEAR PIN AC1..AC5

10 mA

(ICH CORE 1.05V PWR)

ICH CORE/VCC1_05 BYPASS

1130 mA

1 mA

50 mA

(ICH CPU I/O 1.05V PWR)

ICH V_CPU_IO BYPASS

PLACE CAPS AT EDGE OF SB

PLACEMENT NOTE:

F19 AND G20

PLACE CAP UNDER SB NEAR PINS

ICH VCC_PAUX/VCCLAN3_3 BYPASS (ICH LAN I/F BUFFER 3.3V PWR)

ICH IDE/VCC3_3 BYPASS (ICH IDE I/O 3.3V PWR)

(ICH PCI I/O 3.3V PWR)

ICH PCI/VCC3_3 BYPASS

(ICH INTEL HDA CORE 3.3V/1.5V PWR)

ICH VCCHDA BYPASS

PLACEMENT NOTE:

PLACE CAP < 2.54MM OF SB ON SECONDARY OR 3.56MM ON PRIMARY NEAR PIN AF29

DISTRIBUTE IN PCI SECTION OF SB NEAR PINS A8 ... F11

PLACEMENT NOTE:

OR 3.56MM ON PRIMARY NEAR PIN AC12

PLACE < 2.54MM OF SB ON SECONDARY

OR 3.56MM ON PRIMARY NEAR PIN AD11

PLACE < 2.54MM OF SB ON SECONDARY

PLACEMENT NOTE:

OR 3.56MM ON PRIMARY NEAR PIN AD2

PLACE < 2.54MM OF SB ON SECONDARY

PLACEMENT NOTE:

PLACE < 2.54MM OF SB ON SECONDARY OR

3.56MM ON PRIMARY NEAR PINS AA3...Y7

(VCC3_3 Total)

1 mA S0-S5

ON SECONDARY SIDE OR 3.56MM ON PRIMARY

PLACE C2703 < 2.54MM OF PIN A16..T7 OF SB

1 mA

ICH V5REF Filter & Follower

1 mA

PLACEMENT NOTE:

837 mA

PLACEMENT NOTE:

SECONDARY SIDE OR 3.56MM ON PRIMARY

PLACE CAPS < 2.54MM OF SB ON

PLACEMENT NOTE:

23 mA

47 mA

ICH VCCDMIPLL Filter (ICH DMI PLL PWR)

23 mA

ICH VCCSATAPLL Filter (ICH SATA PLL PWR)

33 mA

47 mA

ICH VCC1_5_B BYPASS

80 mA

657 mA

(VCC1_5_A Total)

1080 mA

(ICH RTC 3.3V PWR)

ICH VCCRTC BYPASS

(ICH SUSPEND USB 3.3V PWR)

PLACEMENT NOTE: PLACE CAP NEAR PINS

PLACE CAPS NEAR PINS AC18..AH28

(ICH SUSPEND 3.3V PWR)

PLACE CAPS NEAR PIN AD25 OF SB

PLACEMENT NOTE:

P6..R6

PLACEMENT NOTE:

(VCCSUS3_3 Total)

442 mA

44 mA S3-S5

117 mA S0 /

ICH VCCSUS3_3 BYPASS

(ICH IO,LOGIC 1.5V PWR)

Current numbers from ICH8M Max Power Estimates Rev 2.0, doc #610194.

0.6 uA G3

ICH USB/VCCSUS3_3 BYPASS

(@ 1.5V)

32 mA

11 mA S0 / 1 mA S3-S5

ICH VCCSUSHDA BYPASS (ICH INTEL HDA SUSPEND 3.3V/1.5V PWR)

114 mA M1 & WOL

38 mA S0 /

OR 3.56MM ON PRIMARY NEAR PIN AJ6

PLACE CAPS < 2.54MM OF SB ON SECONDARY

DISTRIBUTED BETWEEN AA25..V23

ON SECONDARY SIDE OR 3.56MM ON PRIMARY

PLACE C2700 & C2705-07 < 2.54MM OF SB

PLACE C2736 NEAR PIN B27..A26

PLACE C2732 NEAR PIN A24

PLACEMENT NOTE:

(ICH GLAN PLL PWR)

ICH VCCGLANPLL Filter

CRITICAL

CASE-B2

20%

POLY

2.5V

220UF

C2700

1

2

0.1UF

10% 16V

402

X5R

C2712

1

2

603

5%

MF-LF

1/10W

1

R2700

1 2

603

CERM

20%

6.3V

4.7UF

C2724

1

2

X5R 402

16V

10%

0.1UF

C2722

1

2

BAT54DW

SOT-363

D2702

1

6

5

BAT54DW

SOT-363

D2702

4

3

2

1.0UH-0.5A

1210

L2703

1 2

603

10UF

20%

6.3V X5R

C2735

1

2

0.1UF

10% 16V

402

X5R

C2703

1

2

6.3V CERM 402

10%

1UF

C2711

1

2

6.3V

20% CERM1

603

2.2uF

C2732

1

2

4.7uF

603

CERM

20%

6.3V

C2736

1

2

6.3V

20%

603

CERM

4.7uF

C2733

1

2

0.1UF

10% 16V

402

X5R

C2741

1

2

X5R 402

16V

10%

0.1UF

C2738

1

2

0805

10UH-100MA

L2702

1 2

X5R 402

16V

10%

0.1UF

C2737

1

2

CERM

20%

805

22UF

6.3V

C2739

1

2

0.1UF

10% 16V

402

X5R

C2702

1

2

0

1/16W MF-LF

5%

402

R2735

1 2

402

5% 1/16W MF-LF

100

R2702

2

1

402

5% 1/16W MF-LF

10

R2701

2

1

X5R 402

16V

10%

0.1UF

C2704

1

2

FERR-330-OHM

SM

L2700

1 2

CERM

22UF

20%

6.3V 805

C2705

20%

6.3V CERM 805

22UF

C2706

CERM1 603

2.2UF

20%

6.3V

C2707

10%

0.01UF

16V CERM 402

C2701

1

2

X5R

6.3V

20%

10UF

603

C2708

1

2

10%

1UF

402

CERM

6.3V

C2717

1UF

10% 402

CERM

6.3V

C2714

1

2

0.1UF

10% 16V

402

X5R

C2715

1

2

0.1UF

10% 16V

402

X5R

C2718

1

2

X5R 402

16V

10%

0.1UF

C2719

1

2

0.1UF

10% 16V

402

X5R

C2721

1

2

X5R 402

16V

10%

0.1UF

C2723

1

2

0.1UF

10% 16V

402

X5R

C2725

1

2

0.1UF

10% 16V

402

X5R

C2726

1

2

0.1UF

10% 16V

402

X5R

C2727

1

2

0.1UF

10% 16V

402

X5R

C2728

1

2

X5R 402

16V

10%

0.1UF

C2729

1

2

X5R 402

16V

10%

0.1UF

C2730

1

2

X5R 402

16V

10%

0.1UF

C2734

1

2

0.1UF

10% 16V

402

X5R

C2731

1

2

051-7261

10.0.0

9227

SB Decoupling

SYNC_MASTER=T9_NOME

SYNC_DATE=01/25/2007

PP1V5_S0

PP3V3_S5

PP3V3_G3_SB_RTC

PP3V3_S5

PP1V5_S0_SB_VCC1_5_B

VOLTAGE=1.5V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

PP1V5_S0_SB_VCC1_5_B

PP1V5_S0_SB_VCCSATAPLL

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM VOLTAGE=1.5V

PP1V5_S0_SB_VCCDMIPLL

MIN_NECK_WIDTH=0.25MM VOLTAGE=1.5V

MIN_LINE_WIDTH=0.5MM

PP1V5_S0_SB_VCCSATAPLL_F

PP1V5_S0_SB_VCCDMIPLL_F

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM

PP5V_S0_SB_V5REF

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.25MM VOLTAGE=5V

PP3V3_S0 PP5V_S0

VOLTAGE=5V

MIN_NECK_WIDTH=0.25MM

PP5V_S5_SB_V5REF_SUS

MIN_LINE_WIDTH=0.3MM

PP5V_S5

PP3V3_S5

PP3V3_S0

PP3V3_S5

PP3V3_S0

PP1V05_S0

PP1V25_S0

PP1V5_S0

91

81

79

77

76

66

60

59

58

53

52

51

50

48

47

46

42

62

32

50

91

31

81

91

31

91

31

46

77

30

80

77

30

77

30

66

29

78

66

29

66

29

27

61

28

66

61

28

61

28

26

91

58

27

60

76

58

27

58

27

23

91

64

56

26

59

66

56

26

56

26

21

64

34

48

25

58

64

48

25

48

25

19

34

27

46

24

54

63

46

24

46

24

18

27

26

28

23

52

62

28

23

28

23

14

66

26

22

27

21

49

61

27

21

27

21

13

58

22

19

26

27

19

47

58

26

19

26

19

12

26

19

12

25

28

25

26

16

42

43

25

16

25

16

11

21

12

11

24

26

24

13

8

42

24

13

24

13

10

19

11

8

23

8

23

26

8

7

26

8

http://24hcongnghe.org

OUT

IN

OUT

IN

NCNC

IN

OUT

IN

OUT OUT

OUT

IN

OUT

IN

A

B

Y

132

A

B

Y

132

IN

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

into isolated signals due to sharp reset edge and isolating FET Cgs.

that would otherwise be injected

of the system. RC prevents glitch

certain GPU signals from the rest

This ensures that GPU is put into reset while chip is still powered

PCI Reset Connections

ON POWER DOWN:

ON POWER UP: This delay ensures that GPU clocks

and clocks are still running.

run before GPU is released from reset

PWROK Circuit

Coin-Cell Connector

518S0487

fault protection for RTC battery.

CPU VCore ForcePSI

SB RTC Crystal

NC

NOTE: R2800 and D2805 form the double-

This part is never stuffed, it provides a set of pads on the board to short or

RTC Power Sources

System Reset "Button"

(RC should reach schmitt trigger threshold at approx 1.65ms nominal w/ 1K pullup on PM_ALL_GPU_PGOOD)

GPU_IOENABLE_RC is used to isolate

NC

Unbuffered

NC

to solder a reset button.

Platform Reset Connections

NC

Muxed GFX GPU Reset Support

VRMPWRGD Inverter

402

20K

MF-LF

5%

1/16W

R2806

1 2

23

402

0.1UF

10V

20% CERM

C2830

1

2

402

10%

1UF

CERM

6.3V

C2806

1

2

10 13

5%

402

1M

1/16W MF-LF

R2805

1

2

7

25 45

1/16W 402

5% MF-LF

10K

R2825

1

2

1/16W

402

MF-LF

1K

5%

R2800

2 1

12pF

402

50V

5%

CERM

C2810

1 2

CERM

402

12pF

50V

5%

C2811

1 2

CRITICAL

SM-2

32.768K

Y2810

2 4

1 3

402

1/16W

5%

MF-LF

0

R2810

1 2

402

5%

10M

MF-LF

1/16W

R2811

1

2

7 9

24 28 79 81

402

ITP&XDP

MF-LF

5%

1/16W

1K

R2826

1 2

BAT54DW

SOT-363

D2805

1

4

6

3

5

2

5%

100

MF-LF

1/16W

402

R2862

1 2

402

MF-LF

0

5%

1/16W

R2863

1 2

100

1/16W

5%

402

MF-LF

R2864

1 2

402

1/16W

5%

MF-LF

100

R2860

1 2

402

0.1UF

CERM

20% 10V

C2840

1

2

7 9

16 59

45 46 66

7 9

25

402

0.1UF

CERM

20% 10V

C2880

1

2

0

5%

1/16W

402

MF-LF

R2881

1 2

7

16

7

47

7

45

34

7

68

MC74VHC1G08

SC70

U2880

3

2

1

4

5

MC74VHC1G08

SC70

U2840

3

2

1

4

5

MC74VHC1G00

SC70-5

U2830

3

2

1

4

5

SILK_PART=SYS RST

603

1/10W

0

5%

OMIT

MF-LF

R2820

1

2

38

MF-LF

1/16W

5%

0

402

R2861

1 2

38

100

MF-LF

5%

1/16W

402

R2890

1 2

7

24

28 78 79

7 9

24 28 79 81

10 28 59 10 28 59

59

7

25

10K

MF-LF

5% 1/16W

402

R2840

1

2

MF-LF

1/16W

402

5%

10K

R2841

1

2

M-RT-SM

BM02B-ACHKS-GAN-TF-LF-SN-M

CRITICAL

J2800

3

4

1 2

402

5% 1/16W MF-LF

1K

R2882

1 2

0.001UF

50V

10% CERM

402

C2882

1

2

1/16W

0

MF-LF

402

5%

R2865

1 2

35

30 79

20% 10V

CERM

402

0.1UF

C2883

12

MF-LF

10K

1/16W

5%

402

R2885

1 2

10V CERM

0.1UF

20%

402

C2885

1

2

24.3K

1%

402

MF-LF

1/16W

R2886

1

2

US8

74LVC2G132

CRITICAL

U2883

5

6

4

8

3

74LVC2G132

US8

CRITICAL

U2883

1

2

4

8

7

25

23 58 66

0

5%

1/16W

402

MF-LF

EXTGPU_RST_HW

R2887

1 2

0

402

5%

MF-LF

1/16W

EXTGPU_RST_SW

R2880

1 2

7

23

CERM

402

6.3V

1UF

10%

C2805

1

2

SB Misc

SYNC_MASTER=M75_MLB

92

10.0.0

051-7261

28

SYNC_DATE=01/30/2007

EXTGPU_PWR_EN

EXTGPU_RST_L

EXTGPU_RST_QUAL_L

PP3V3_S0

RST_L_AND_GPU_PGOOD

PM_SB_PWROK

ENET_RESET_L

PLT_RST_L

MAKE_BASE=TRUE

DEBUG_RESET_L

PP3V3_S5

PCI_RST_L

PCI_FW_RST_L

GPU_IOENABLE_RC

GPU_RESET_L

PP3V3_S0

SB_RTC_X2

VR_PWRGOOD_DELAY

PP3V3_S0

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

PPVBATT_G3_RTC

PP3V42_G3H

MIN_NECK_WIDTH=0.2 mm

PPVBATT_G3_RTC_R

MIN_LINE_WIDTH=0.3 mm VOLTAGE=3.3V

PM_SYSRST_L

XDP_DBRESET_L

SB_RTC_X1

LIO_PLT_RST_L

NB_RESET_L

FW_PLT_RST_L

PP3V3_G3_SB_RTC

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

SB_RTC_RST_L

SB_SM_INTRUDER_L

SMC_LRESET_L

PM_ALL_GPU_PGOOD

VR_PWRGD_CLKEN_L

GPU_PGOOD_RC

RST_L_AND_GPU_PGOOD_L

PP3V3_S0

ALL_SYS_PWRGD

VR_PWRGD_CLKEN

SB_RTC_X1_R

CPU_PSI_LCPU_PSI_L

MAKE_BASE=TRUE

GPU_IOENABLE_RC

GPU_RESET_R_L

91

91 91

91

81

81 81

81

79

79 79

79

77

77 77

77

76

76 76

76

66

66 66

66

60

60 60

60

59

59 59

59

58

58 58

58

53

53 53

53

52

52 52

52

51

51 51

51

50

50 50

50

48

48 48

48

47

47 47

47

46

46 46

46

42

42 42

42

32

32 32

32

31

31 31

31

30

91

30 30

30

29

77

29 29

29

28

66

28 28

80

28

27

61

27 27

67

27

26

58

26 26

66

26

25

56

25 25

57

25

24

48

24 24

48

24

23

46

23 23

47

23

21

27

21 21

46

21

19

26

19 19

45

19

16

25

16 16

43

27

16

79

13

24

13 13

8

26

13

78

8

23

8

7

23

8

28

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Apple macbook pro a1129 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual