How it Works
Apple
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LINK Q51
Schematic
66 pgs1.37 Mb0

Apple LINK Q51 Schematic

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
D
Module
Page
(.csa)
1 2 3 4 5 6 7 8
9 10 11
C
TOP
12 13 14 15 16 17 18 19 20 21 22 23 24
B
25 26 27
Processor Interface
28 29 30 31 32
Main
Memory
A
DRAWING
TITLE=LINK ABBREV=DRAWING
LAST_MODIFIED=Mon Feb 23 18:35:53 2004
8
33 34 35
QTY
337S2835
343S0283
338S0154 CRITICAL
343S0288
341S1340
341S1394
78
(1)
Table of Contents
(2)
System Block Diagram
(3)
Power Block Diagram
(4)
Revision Notes
(5)
Power & Signal Aliases
(6)
Functional Test Properties
(7)
System Power Connectors
(8)
Battery Charger
(9)
1.8V / 1.5V/ 1.2V Regulators
(10)
3.3V / 5V Regulators
(11)
2.5V / NB Vcore / PMU Regulators
(12)
Vesta Power / Misc
(13)
System Management Unit (SMU)
(14)
Power Sequencing Connections
(15)
Thermal Sensor / Fans
(16)
Misc Internal Connectors
(18)
Q51 Specific design/Connectors
(20)
I2C Connections
(21)
LMU Support
(22)
U3Lite Core
(23)
Shasta Core
(24)
U3Lite Misc
(25)
Shasta Misc
(26)
Pulsar Core
(27)
Pulsar Clocks
(28)
U3Lite Processor Interface
(29)
PPC970 Processor Interface
(30)
PPC970 Pull-ups / Pull-downs
(31)
PPC970 Core
(32)
PPC970 Bypassing
(33)
CPU VCore Regulator
(36)
CPU Temperature Monitoring
(37)
U3Lite Memory Interface
(38)
Memory Series Termination
(40)
SO-DIMM Connectors
Contents
Module Components
DESCRIPTION
IC,PPC970,1.8GHz,1.1V,80C,25W,576CBGA1U2900
IC,U3LITE,V1.1,300MM,PBGA
1
IC,ASIC,SHASTA,V1.1,484BALL,PBGA
1
1
IC,ATI,M11-CSP64,NO HEATSPREADER
1
IC,ATI,M11-CSP128,NO HEATSPREADER
1
IC,ASIC,VESTA,V1.1
BOOTROM,PROTO,Q51
1
SMU,PROTO,Q51
1
REFERENCE DESIGNATOR(S)
CRITICAL BOM OPTION
CRITICAL
CRITICALU3343S0284
CRITICAL
CRITICAL338S0158
CRITICAL
CRITICAL
CRITICAL
6
67
M11CSP64
M11CSP128
Date
Sync
N/A N/A N/A N/A
N/A
N/A
Gila
Gila Gila U3Lite Gila Gila Gila Gila
U3Lite
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
09/25/03
08/01/03
09/11/03
09/15/03
09/11/03
09/11/03
07/28/03
09/01/03
10/01/03
09/26/03
08/01/03
07/28/03
08/01/03
09/01/03
07/28/03
09/18/03
07/28/03
09/18/03
09/18/03
09/18/03
09/18/03
09/18/03
09/18/03
09/18/03
09/11/03
09/25/03
09/18/03
08/01/03
08/01/03
(Link)
(Nimitz) (Link) (Link) (Link) (Link) (Fizzy) (smu_real)
(Link)
(Link) (Nimitz)
(Gila) (Nimitz) (Gila) (Fizzy)
(Fizzy)
(Link) (Gila)
(Nimitz) (Nimitz)
5
LINK
02/23/2004
(.csa)
Module
Graphics
Hyper­Transport
PCI
Disk
Ethernet
FireWire
USB
Modem Audio
CRef
Alternates Components
PART NUMBER
343S0282 U3
Schematic / PCB #’s
051-6532 SCH1
820-1573
ALTERNATE FOR PART NUMBER
343S0284
QTY
DESCRIPTION
SCHEM,LINK,Q51
1
PCBF,LINK,Q51
1
5
BOM OPTION
Page
36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66
REF DES
REFERENCE DESIGNATOR(S)
(100)
(101)
(102)
(103)
COMMENTS:
U3L,V1.1,200MM,PBGA
PCB1
(48)
(49)
(50)
(51)
(52)
(57)
(59)
(60)
(62)
(74)
(75)
(76)
(77)
(78)
(80)
(81)
(83)
(84)
(86)
(87)
(88)
(89)
(90)
(91)
(94)
(95)
(99)
4
3
Contents
U3Lite AGP Interface M10-CSP64 AGP Interface GPU VCore Regulator M10-CSP64 Core M10-CSP64 Misc Power TMDS Terminations Video Connectors U3Lite HyperTransport Interface Shasta HyperTransport Interface South Bridge PCI Interface BootROM AirPort Extreme Connector USB2 Controller PCI Interface CardBus Controller & Connector South Bridge Disk Interfaces Serial ATA to Parallel ATA Bridge UATA/PATA Connectors South Bridge Ethernet Vesta Ethernet Ethernet Magnetics & Connector South Bridge Firewire Vesta FireWire FireWire Ports USB Interfaces Modem Interface Audio Interface End of Modules Placeholder Signal Cross Reference (1 of 2) Signal Cross Reference (2 of 2) Component Cross Reference (1 of 2) Component Cross Reference (2 of 2)
DIMENSIONS ARE IN MILLIMETERS
XX
X.XX
ANGLES
DO NOT SCALE DRAWING
THIRD ANGLE PROJECTION
3
4
TABLE_ALT_HEAD
TABLE_ALT_ITEM
BOM OPTION
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
Date
Sync
(Nimitz) (Link) (Nimitz) (Nimitz) (Nimitz) (Nimitz)
(Fizzy)
(Fizzy/Nimitz)
(Fizzy) (Fizzy) (Fizzy) (Fizzy) (Fizzy)
(Fizzy/Nimitz)
(Fizzy) (Fizzy)
(Fizzy/Nimitz)
(Fizzy) (Fizzy) (Fizzy)
Gila
U3Lite Fizzy
Fizzy
Fizzy Fizzy
Fizzy
N/A N/A N/A N/A
09/18/03
07/01/03
09/11/03
07/01/03
07/01/03
08/01/03
07/01/03
09/18/03
09/30/03
09/13/03
09/30/03
08/01/03
09/30/03
09/30/03
07/28/03
07/28/03
07/28/03
07/28/03
07/28/03
08/01/03
07/28/03
07/28/03
08/06/03
09/30/03
08/06/03
08/06/03
09/25/03
METRIC
DRAFTER
ENG APPD
QA APPD
RELEASE
MATERIAL/FINISH
NOTED AS
APPLICABLE
REV
ECN
ZONE
31600803
DESCRIPTION OF CHANGE
ENGINEERING RELEASED
EVT1
BOM Option Table
BOM Options
DEVELOPMENT GPU_SS MPIC_NB MPIC_SB PATA_3V3_LOGIC PATA_5V_LOGIC PCI_64BIT SMU_CPU_I2C SMU_CPU_JTAG THERM_1 THERM_1B THERM_2 THERM_2B THERM_3 THERM_3B VESTA1V2_BURST VESTA1V2_PULSE VESTA_DS_ONLY_EN0 VESTA_PWR_CLASS_0 AGP_BUSYSTOP NO_SMU_I2C_D EI_3TO1 CPU_PLL_MEDIUM CPU_AVDD_2V8 SB_HT_200M M11CSP64 M11CSP128 INT_TMDS EXT_TMDS
Apple Computer Inc.
DESIGN CK
MFG APPD
DESIGNER
NONE
SIZE
D
2
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SCHEM,LINK,Q51
DRAWING NUMBER
051-6532
12
CK APPD
DATE
02/23/04
630-4843 630-4902
PCBA,LINK,Q51
SHT
NO STUFF
REV.
1 103
STUFF
630-4843
630-4902
1
ENG APPD
?
03
OF
DATE
D
C
B
A
78
6
5
4
3
12
J700
Nicky (PWR)
Connector
P.7
D
Power Supply
& Charger
P.7-12
U1300
J750
SMU
P.13
U2900
CPU
NEO 10S
P.26-29
Level shifting
I2C
Battery
Connector
P.7
C
J1600
RTC
P.13
U2600
LEFT USB Bluetooth
Connector
P.16
I2C buses
Pulsar
Clock Gen
P.23-24
Max1668
Thermal
P.15
EI Clocks VSP Clock HT Clocks AGP Clocks PCI Clocks SATA Clock
SYSTEM BLOCK DIAGRAM
AGP
PAGE 35
U3
P.17
ELASTIC INTERFACE 44-BIT/Directional APPLE PI
1.2V/600MHz
APPLE PI
MISC
PAGE 21
J4010/J4020
DDR SDRAM DIMM 0
DDR SDRAM DIMM 1
SODIMM Connector
P.34
U3LITE
PAGE 25
CORE
PAGE 19
MAIN MEMORY
PAGE 32
PAGE 42
HYPERTRANSPORT
MEMORY BUS
2.5V
333MHz 128BITS
AGP BUS
4X/8X
1.5V/0.8V 32BITS 267/533MHZ
HYPERTRANSPORT 8-BIT/Direction
1.2V/400MHZ
CONTROL = 2.5V
U4900
ATI M11
64/128MB
P.36,38-40
J5980
Inverter
Connector
MEMORY CH. A
(INTERNAL MEM)
(INTERNAL MEM)
MEMORY CH. B
(INTERNAL MEM)
(INTERNAL MEM)
LVDS
J5970
LCD Panel
Connector
P.41P.41
MEMORY
CH. C
MEMORY CH. D
TMDS
RGB
DDC
S-Video/Comp
ENET Pairs
4 Datapairs @125MHz
J5900
DVI-I
Connector
P.41
J5960
S-Video
Connector
P.41
J8700
Gigabit Ethernet
Connector
P.54
D
C
U8600
ETHERNET
FIREWIRE
SMU/JR
Debug
P.16
Modem
VESTA
Core
PAGE 12
PAGE 53
PAGE 56
FW-A Pairs
2 Datapairs @200MHz
FW-B pairs
2 Datapairs @400MHz
SYSTEM BLOCK DIAGRAM
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
APPLE COMPUTER INC.
J9010
Firewire A
Connector
P.57
J9020
Firewire B
Connector
P.57
J790
Backup Battery
Right USB
Connector
P.7
NOTICE OF PROPRIETARY PROPERTY
SIZE
DRAWING NUMBER
D
051-6532
NONE
SHT
B
A
REV.
03
OF
1032
J8350
Hard DRIVE
133MHz/3.3V/16 Bit
Connector
P.51
B
U8150
Serial ATA
Bridge
P.50
J8300
OPTICAL DRIVE
Connector
P.51
J7800
Cardbus
1.5Gbps/1.2V/1 Bit/Directonal
Not Used
133MHz/3.3V/16 Bit
SATA1
PAGE 49 PAGE 49
SATA2
UATASATA
PCI
PAGE 44
HYPERTRANSPORT
U2300
SHASTA
CORE
PAGE 20
GPIO/PCI64
PAGE 22
PAGE 43
I2S0
I2S
PAGE 22
SCCA I2S1 I2S2
ETHERNETFIREWIRE
PAGE 55 PAGE 52
SCCB
8-bit TX & 8-bit RX
GMII (3.3V/125MHz)
1394 OHCI (3.3V/98MHz)
J1699
Connector
Connector
P.48
PCI BUS
33MHZ 16/32 BITS
3.3V/5V
J7600
Airport
Extreme
Connector
PAGE 46
A
PORT = USB 2.0 (Low/Full/High Speed) Bluetooth = USB 1.1 (Low/Full Speed)
32BITS 33MHZ
3.3V
U7800
U7700
Cardbus
PCI1510
PAGE 48 PAGE 47
J2130
USB Trackpad
USB 2.0
uPD720101
USB 1.1
Connector
P.18
U7500
BOOTROM
PAGE 45
KB
LED
P.18
J9500
Sound (Kazoo)
Connector
P.60 P.18 P.59
USB 1.1 (Low/Full Speed)
USB 2.0 (Low/Full/High Speed)
Sleep
J9400
ConnectorLED
8
67
5
4
3
2
1
78
6
5
4
3
12
LEGEND
(overcurrent shutoff)
AC Adapter
D
(pg 7)
PP18V5_ALL_DCIN
In-Rush Limiter
(pg 7)
PP18V5_ALL_INRUSH
Backfeed
Protection
(pg 8)
(MAX1544 Built-in Current Sense)
PP18V5_ALL_SENSE
Current
Sense
(pg 8)
PPBUS_ALL_B
PBUS Isolation
SMU
4.6V/3.3V
Power Supplies
(pg 11)
PPBUS_ALL_A
Circuit
(pg 8)
MAX1544
CPU Vcore Switcher
Voltage Toggled by SMU
(pg 29)
PPVCORE_RUN_CPU
TPS5120
5V/3.3V DC Switcher
(pg 10)
Backup
C
Battery
Connector
(pg 7)
MAX1993
GPU Vcore Switcher
Selectable 1.2V/1.0V
(pg 35)
PP1V2_RUN_GPU
Max1535
Battery Charger
Stops charging when system draws more than xxW
(pg 8)
Inverter Connector
(pg 39)
PPBUS_INVERTER
TPS5120
NBVCORE/2.5V DC Switcher
(pg 11)
PP=Power Positive PN=Power Negative
_ALL=ON during Shutdown/Run/Sleep _PWRON=ON during Run/Sleep _RUN=ON during Run
LTC3412
1.2V DC Switcher
(pg 9)
SLEEP
PP5V_PWRON
PP3V3_PWRON
FET
SLEEP
FET
SLEEP
FET
TP62050
1.5V DC Switcher
(pg 9)
LP3982
1.8V LDO
(pg 9)
PP2V5_PWRON
SLEEP
FET
PPVCORE_NB_PWRON
PP1V2_PWRON
SLEEP
FET
PP5V_RUN_HD
PP5V_RUN
PP3V3_RUN
PP1V5_PWRON
SLEEP
FET
PP1V8_RUN
PP2V5_RUN
D
PP1V2_RUN
C
PP1V5_RUN
B
A
DRAWING
TITLE=LINK ABBREV=DRAWING
LAST_MODIFIED=Mon Feb 23 18:35:54 2004
Charge Enable
Circuit
(pg 8)
5A Fuse (pg 8)
5A Fuse (pg 8)
Battery
Connector
(pg 11)
Cell 1 Cell 2 Cell 3
Cell 5 Cell 8 Cell 9Cell 7
3S3P Prismatic Battery Pack
Cell 6Cell 4
Battery Out
Enable Circuit A
(pg 8)
Battery Out
Enable Circuit B
(pg 8)
Power Budget
PPBUS_ALL_A
CPU_Core => 28W GPU_Core => 6W Inverter => 7W 1V8_RUN => 5W Charger => ??W
TOTAL => 46W+?
1.5A Fuse (pg 12)
5VPWRON => 20W/25W 3V3PWRON => 10W/6.6W 2V5PWRON => 10W 1V2PWRON => 10W Firewire => 8W/15W
TOTAL => 58W/67W
Port PWR
Enable Circuit
(pg 56)
Power Budget
PPBUS_ALL_B
Firewire B Conn
1.5A Fuse (pg 56)
Firewire A Conn
Power Block Diagram
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
APPLE COMPUTER INC.
(pg 56)
(pg 56)
NOTICE OF PROPRIETARY PROPERTY
SIZE
DRAWING NUMBER
D
051-6532
NONE
SHT
3
B
A
REV.
03
OF
103
8
67
5
4
3
2
1
78
6
5
4
3
12
Revision Notes
1/14/04
1) moved Q3001-Q3004,D3001,D3002,R3044,R3046,R3048,R3070,R3050,R3052,R3054 from Page 27 to page 16 to allow sync with Gila
2) moved AGP Vref (R4802,R4803,C4818) circuit to M11 specific page (49)
3) changed R2191 to pulldown on SYS_LED *** sync with Gila *** 1/20/04
4) added 10 mil MIN_LINE_WIDTH and MIN_NECK_WIDTH to BKFD_PROT_EN_L
5) changed MIN_LINE_WIDTH of PP5V4_CHGR_LDO to 10 mils
6) moved J790 (backup battery/R USB connector) to page 18 for syncing with Logic
7) moved J1600 (BT/USB connector) to page 18 for syncing with Logic
8) moved C860-C865 (PBus hold-up caps) to page 18 for syncing with Logic
9) moved ZT9900-ZT9903 (EMI vias) to page 18 for syncing with Logic
10) moved SP500-SP505 and SP9900 to (speaker wire clips) to page 18 for syncing with Logic
11) moved ZT500-ZT505, ZT510, and ZT511 (plated screw holes) to page 18 for syncing with Logic
12) moved BS510 to page 18 for syncing with Logic
D
C
13) moved J2130 (trackpad connector) to page 18 for syncing with Logic
14) changed C2150 to 20%
15) added 10 mil MIN_LINE_WIDTH and MIN_NECK_WIDTH to KBDLED_ANODE and KDBLED_RETURN
16) changed C2115 to R2116 (3.32K 1% 402) to divide ALS output to 2.5V *** sync with Logic *** 2/2/04
17) changed PCI from shasta to PCI_SB to allow desktops to insert series R’s
18) added pg 73 to alias PCI_SB nets back to PCI to reconnect
19) changed R2150 to 8.25 to reduce LED drive current to 20mA
20) changed Q2113 to second FET in Q5909
21) changed SMU_ADAPTER_ID to SMU_ONEWIRE
22) added R1620 and R1621 to divide ALS output down to 2.5V
23) added alias from TP_SATA_CLK25M to SATA_CLK25M 2/3/04
24) changed PPVCORE_RUN_CPU connection to XW592 to _PP1V5_RUN_FET 2/6/04
25) changed C720 to 0.22uF
26) changed R800 and R810 to 1/2W 1206 10mohm
27) changed C1068 to NO STUFF
28) removed Q1117 and C1114
29) changed L1115 to 2.2uH IHLP5050CE (152S0152)
30) changed C1121 to 680pF 402
31) changed R1102 to 20K 1% 402
32) added MIN_LINE_WIDTH and MIN_NECK_WIDTH properties to CPUVCORE_CM_N and CPUVCORE_CS_N
33) added MIN_LINE_WIDTH and MIN_NECK_WIDTH properties to ALS1_PHOTODIODE and ALS1_OP_IN 2/7/04
34) changed R5019 to 26.7K 1% to increase GPU Vcore current limit (rdar://3510721)
35) sync with Gila (Q45) to fix several power disconnects
36) added aliases on page 5 to set unused CKE, CS, and MUX controls back to TP
37) sync with Logic (Q43) to get DVO contraints 2/10/04
38) changed R3671 to 100K 0.1% to adjust the Tdiode range
39) changed C3671 to 10uF 20% 6.3V to adjust the Tdiode range
40) changed R3672 to 40.2K 0.1% to adjust the Tdiode range
41) changed R3676 to 100K 0.1% to adjust the Tdiode range
42) changed C3676 to 10uF 20% 6.3V to adjust the Tdiode range
43) changed R3677 to 40.2K 0.1% to adjust the Tdiode range
44) mirrored FL9020 and FL9021 to fix layout 2/11/04
45) changed L970 to 152S0154 (10uH) to reduce size 2/12/04
46) removed 197S0703 as alternate for 197S0037 (25MHz Vesta crystal)
47) changed all references to SMU_MANUAL_RESET_L to SMU_RESET_L 2/19/04
48) removed DC current limit circuit (U870 and associated discretes)
49) added BOMOPTION for 2.8V CPU Avdd LDO
50) changed R4800 to 2.2 ohm 603, C4811 to 1uF 402, and C4816 to 0.1uF 402 in U3Lite AGP Avdd filter.
51) changed R1610 (series R on SMU_ONEWIRE output) to 0 ohm
52) added R1611 (1k pullup to PP3V3_ALL) on ADAPTER_ID to power SMU_ONEWIRE interface 2/23/04
53) changed C8160-C8160 (SATA AC coupling caps) to 0.01uF per Marvell recommendation
54) added NO_TEST properties to CPUVCORE_GNDSENSE and CPUVCORE_SENSE
D
C
B
A
APPLE COMPUTER INC.
8
67
5
4
3
2
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
051-6532
NONE
SHT
4 103
1
REV.
03
OF
B
A
_PP1V8_SATABR
SHT
5
12
7
17
13
13
18
16
13
D
19
52
12
16
29
52
61
51
52
48
49
23
45
31
15
41
49
48
47
46
45
C
49
29
51
36
37
24
43
22
24
B
26
18
29
28
27
18
A
REV.
03
OF
103
78
Page Notes
Power aliases required by this page: N/A (Most aliases are on this page)
Signal aliases required by this page: N/A (Most aliases are on this page)
BOM options provided by this page: (NONE)
AGP Signal Aliasing
PCI_RESET_L
48
47
46
45 41
48
47
46
5
MAKE_BASE=TRUE
PCI_RESET_L
45
5
MAKE_BASE=TRUE
PCI_CLK33M_AIRPORT
6
MAKE_BASE=TRUE
PCI_CLK33M_CBUS
MAKE_BASE=TRUE
PCI_CLK33M_USB2
MAKE_BASE=TRUE
SATA_CLK25M
MAKE_BASE=TRUE
PCI_CLK33M_SB_EXT
45
MAKE_BASE=TRUE
D
GPU is D3cold
PCI Signal Aliasing
CardBus is D3cold
_GPU_RESET_L
ALIAS
_PCI_CBUS_RESET_L
ALIAS
PCI_CLK_P3
ALIAS
_PCI_CLK33M_AIRPORT
PCI_CLK_GP1
ALIAS
_PCI_CLK33M_CBUS PCI_CLK_GP0
ALIAS
_PCI_CLK33M_USB2 PCI_CLK_P4
ALIAS
_SATA_CLK25M
PCI_CLK_P1
ALIAS
37
49
25
47
25
49
25
48
25
51
25 25
PPBUS_ALL_A
6
PPBUS_ALL_B
6
_PPVCORE_CPU_REG
32
31
PBUS PWR
VOLTAGE=18.5V MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
ALIAS ALIAS ALIAS ALIAS
ALIAS
VOLTAGE=18.5V MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
ALIAS ALIAS ALIAS ALIAS ALIAS
CPU/GPU Core PWR
6
_PPBUS_ALL_A _PPVIN_CPUVCORE _PPVIN_GPUVCORE _PPBUS_INV
_PPBUSA_BBATT
_PPBUS_ALL_B _PPVIN_5V3VPWRON _PPVIN_2V5_NBVCORE_PWRON _PPBUS_FW _PPBUSB_BBATT
PPVCORE_RUN_CPU
MAKE_BASE=TRUE VOLTAGE=1.1V MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
ALIAS
ALIAS
5
_PWRON PWR
_PP5V_PWRON_REG
10
42
8
17
31
38
42
17
8
17
10
11
12
17
6
PPVCORE_CPU
32
31
30
29
27
PP5V_PWRON_REG
MAKE_BASE=TRUE VOLTAGE=5V MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
_PP3V3_PWRON_REG
10
PP3V3_PWRON_REG
MAKE_BASE=TRUE VOLTAGE=3.3V MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
ALIAS
ALIAS
USB Signal Aliasing
USB "0": Left USB Port
USB2_N<0>
6
59
USB2_P<0>
6
59
USB2_PWREN<0>
59
C
6
59
6
USB2_OC<0>
USB "1": Right USB Port
USB2_N<1>
59
6
USB2_P<1>
6
59
USB2_PWREN<1>
59
6
USB2_OC<1>
59
6
USB "2": BlueTooth
USB2_N<2>
6
59
USB2_P<2>
6
59
USB2_PWREN<2>
59
USB2_OC<2>
59
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
USB2_LT_N
MAKE_BASE=TRUE
USB2_LT_P
MAKE_BASE=TRUE
LTUSB_PWREN
MAKE_BASE=TRUE
LTUSB_OVERCURRENT
MAKE_BASE=TRUE
USB2_RT_N
MAKE_BASE=TRUE
USB2_RT_P
MAKE_BASE=TRUE
RTUSB_PWREN
MAKE_BASE=TRUE
RTUSB_OVERCURRENT
MAKE_BASE=TRUE
USB_BT_N
MAKE_BASE=TRUE
USB_BT_P
MAKE_BASE=TRUE
TP_USB2_PWREN2
MAKE_BASE=TRUE
USB2_OC2_PU
MAKE_BASE=TRUE
17
17
17
17
17
17
17
17
17
17
_PPVCORE_GPU_REG
38
PPVCORE_GPU_REG
MAKE_BASE=TRUE VOLTAGE=1.2V MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
PP2V5_RUN
5
ALIAS
Graphic PWR
1
R505
0
5%
FF
805
2
_PP2V5_GPU
PP2V5_GPU
ALIAS
MAKE_BASE=TRUE VOLTAGE=2.5V MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
XW510
JUMPER
40
USB "3": MicroDash Modem
USB2_N<3>
6
59
USB2_P<3>
6
59
USB2_PWREN<3>
59
USB2_OC<3>
59
B
USB2_N<4>
6
59
USB2_P<4>
6
59
USB2_PWREN<4>
59
USB2_OC<4>
59
USB "4": Trackpad/Keyboard
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
USB_MODEM_N
MAKE_BASE=TRUE
USB_MODEM_P
MAKE_BASE=TRUE
TP_USB2_PWREN3
MAKE_BASE=TRUE
USB2_OC3_PU
MAKE_BASE=TRUE
USB_TPAD_N
MAKE_BASE=TRUE
USB_TPAD_P
MAKE_BASE=TRUE
TP_USB2_PWREN4
MAKE_BASE=TRUE
USB2_OC4_PU
MAKE_BASE=TRUE
60
60
17
17
PP3V3_PWRON
SMU Signal Aliasing
SMU_SLEEP SYS_SLEEP
13 10
SMU_WARM_RESET_L
22
13
ALIAS
MAKE_BASE=TRUE
25
11
PP2V5_RUN
5
PP1V8_RUN
6
5
ATI_MEMIO_1V8
R503
1/4W 1210
1
R599
100K
5% 1/16W MF 402
2
SYS_WARM_RESET_L
MAKE_BASE=TRUE
0
5% FF
1
2
ALIAS
22
ATI_MEMIO_2V5
1
R501
0
5% 1/4W FF 1210
2
_PPVCORE_GPUFB
PPVCORE_GPUFB
45
23
MAKE_BASE=TRUE VOLTAGE=1.8V MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
48
Test Point Aliasing
EXT_LED_L
FAN_RPM2
13
FAN_TACH2
13
FAN_TACH3
13
FAN_TACH4
13
FAN_TACH5
13
I2C_SMU_D_SCL
A
13
NB_PMR_OBSV
22
NB_THMI
22
NB_THMO
22
SATA_RXD_P2_C
50
SATA_RXD_N2_C
50
SATA_TXD_P2
50
SATA_TXD_N2
50
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
TP_EXT_LED_L
MAKE_BASE=TRUE
TP_FAN_RPM2
MAKE_BASE=TRUE
TP_FAN_TACH2
MAKE_BASE=TRUE
TP_FAN_TACH3
MAKE_BASE=TRUE
TP_FAN_TACH4
MAKE_BASE=TRUE
TP_FAN_TACH5
MAKE_BASE=TRUE
TP_I2C_SMU_D_SCL
MAKE_BASE=TRUE
TP_NB_PMR_OBSV
MAKE_BASE=TRUE
TP_NB_THMI
MAKE_BASE=TRUE
TP_NB_THMO
MAKE_BASE=TRUE
TP_SATA_RXD_P2
MAKE_BASE=TRUE
TP_SATA_RXD_N2
MAKE_BASE=TRUE
TP_SATA_TXD_P2
MAKE_BASE=TRUE
TP_SATA_TXD_N2
MAKE_BASE=TRUE
More Test Point Aliasing
EI_CPU1_CLK_N_R
25
EI_CPU1_CLK_P_R
25
CPU1_HTBEN_R
25
EI_CPU1_SYNC_R
25
RAM_CKE_R<2>
33
RAM_CKE_R<3>
33
RAM_CKE_R<6>
33
RAM_CKE_R<7>
33
RAM_CS_L_R<2>
33
RAM_CS_L_R<3>
33
RAM_CS_L_R<10>
33
RAM_CS_L_R<11>
33
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
TP_EI_CPU1_CLK_N
MAKE_BASE=TRUE
TP_EI_CPU1_CLK_P
MAKE_BASE=TRUE
TP_CPU1_HTBEN_R
MAKE_BASE=TRUE
TP_EI_CPU1_SYNC_R
MAKE_BASE=TRUE
TP_RAM_CKE_R<2>
TP_RAM_CKE_R<3>
TP_RAM_CKE_R<6>
TP_RAM_CKE_R<7>
TP_RAM_CS_L_R<2>
TP_RAM_CS_L_R<3>
TP_RAM_CS_L_R<10>
TP_RAM_CS_L_R<11>
OPEN
PP1V2_RUN_GPU
MAKE_BASE=TRUE VOLTAGE=1.2V MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
21
ALIAS
PP3V3_RUN
6
R502
ALIAS
ALIAS
6
5
37
40
PP1V5_RUN
6
1
0
5% FF
805
2
_PP3V3_GPU
PP3V3_GPU
MAKE_BASE=TRUE VOLTAGE=3.3V MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
PP3V3_AGP
VOLTAGE=3.3V MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
PP1V8_RUN
1
R504
0
5%
FF
805
2
_PP1V8_GPU
PP1V8_GPU
ALIAS
MAKE_BASE=TRUE VOLTAGE=1.8V MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
1
R500
0
5%
FF
805
2
PP1V5_GPU
ALIAS
RAM_MUXEN0
33
RAM_MUXEN4
33
PPVCORE_GPU
37
36
_PP1V5_GPU_AGP
MAKE_BASE=TRUE VOLTAGE=1.5V MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
37
40
39
41
40
39
37
39
37
ALIAS
ALIAS
39
_PP2V5_PWRON_REG
11
_PP1V5_PWRON_REG
9
PP1V5_PWRON_REG MAKE_BASE=TRUE VOLTAGE=1.5V MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
_PP1V2_PWRON_REG
9
_PPVCORE_NB_REG
11
PPVCORE_NB_REG MAKE_BASE=TRUE VOLTAGE=1.3V MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
PP2V5_PWRON_REG
MAKE_BASE=TRUE VOLTAGE=2.5V MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
PP1V2_PWRON_REG MAKE_BASE=TRUE VOLTAGE=1.2V MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
ALIAS
ALIAS
ALIAS
ALIAS
XW552 Always close
GND
40
TP_RAM_MUXEN0
TP_RAM_MUXEN4
GND_CHASSIS_DVI
17 42
VOLTAGE=0V MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
GND_CHASSIS_INVERTER
17 42
VOLTAGE=0V MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
GND_CHASSIS_LVDS
6
VOLTAGE=0V MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
GND_CHASSIS_IO
6 17
VOLTAGE=0V MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
4
PP5V_PWRON
VOLTAGE=5V MIN_LINE_WIDTH=25 mil
OPEN
OPEN
21
21
21
PP3V3_PWRON
21
PP2V5_PWRON
21
ALIAS
ALIAS
ALIAS
ALIAS ALIAS ALIAS ALIAS ALIAS
MIN_NECK_WIDTH=10 mil
PP1V5_PWRON
_PP5V_PWRON_AUDIO
ALIAS
_PP5V_PWRON_MODEM
ALIAS
_PP5V_PWRON_LTUSB
ALIAS
_PP5V_PWRON_RTUSB
ALIAS
_PP5V_PWRON_SLEEPLED
ALIAS
_PP5V_PWRON_TPAD
ALIAS
_PP5V_PWRON_3V3ALL
ALIAS
_PP5V_PWRON_FAN
ALIAS
_PP5V_PWRON_GPUVCORE
ALIAS
_PP5V_PWRON_SERIAL
ALIAS
_PPVIN_1V2PWRON
ALIAS
_PP5V_PWRON_5VRUN
ALIAS
_PP5V_CBUS
ALIAS
_PP5V_CPUVCORE_VDD
ALIAS
_PP5V_CPUTHERM
ALIAS
VOLTAGE=3.3V MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
VOLTAGE=2.5V MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
PP1V2_PWRON
_PP3V3_PWRON_AUDIO
ALIAS
_PP3V3_PWRON_MODEM
ALIAS
_PP3V3_PWRON_SB
ALIAS
_PPPCI64_PWRON_SB
ALIAS
_PPPCI32_PWRON_SB
ALIAS ALIAS
_PP3V3_PWRON_USB
ALIAS
_PP3V3_PWRON_BT _PP3V3_PWRON_ALS1
ALIAS
_PPVIN_1V5PWRON
ALIAS
_PP3V3_PWRON_THERM
ALIAS
_PP3V3_PWRON_3V3RUN
ALIAS
_PP3V3_CBUS
ALIAS
_PP3V3_CPUTHERM
ALIAS
_PP3V3_PWRON_1V8RUN
ALIAS
_PP2V5_PWRON_SB
ALIAS
_PP2V5_PWRON_HT
ALIAS
_PP2V5_PWRON_DIMM
ALIAS
_PP2V5_ENET
ALIAS
PP2V5_HT
ALIAS
_PPSPD_DIMM
ALIAS
_PP2V5_PWRON_2V5RUN
ALIAS
_PP2V5_PWRON_1V8RUN
ALIAS
PP2V5_PWRON_RAM
ALIAS
VOLTAGE=1.5V MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
ALIAS ALIAS ALIAS
VOLTAGE=1.2V MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
ALIAS ALIAS ALIAS ALIAS ALIAS
ONLY ONE CAN BE CLOSED Between XW560/XW561!!!
ONLY ONE CAN BE CLOSED Between XW550/XW551!!!
ALIAS
PPVCORE_PWRON_NB
MAKE_BASE=TRUE VOLTAGE=1.3V MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
VOLTAGE=0V MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
_GND_CHASSIS_DVI_TOP
_GND_CHASSIS_INV
_GND_CHASSIS_LVDS
_GND_CHASSIS_ENET _GND_CHASSIS_FW_PORT1 _GND_CHASSIS_FW_PORT2 _GND_CHASSIS_DVI_BOTTOM _GND_CHASSIS_SVIDEO
XW520
JUMPER
OPEN
XW530
JUMPER
XW540
JUMPER
XW560
JUMPER
OPEN
XW561
JUMPER
OPEN
XW552
JUMPER
OPEN
Chassis Grounds
PPVCORE_PWRON_PULSAR _PP1V5_PWRON_1V5RUN PP1V5_PWRON_NB_AVDD
_PP1V2_PWRON_DISK_SB _PP1V2_PWRON_HT _PP1V2_PWRON_SB _PPVCORE_PWRON_SB _PP1V2_PWRON_1V2RUN
_PPVCORE_PWRON_NB
55
58
58
42
3
_RUN PWR
PP3V3_ALL
_PP3V3_ALL_LDO
61
60
17
17
19
17
11
15
38
16
9
10
49
31
32
61
60
45
23
21
18
21
21
59
17
19
9
15
10
49
32
9
56
45
23
21
44
35
55
43
35
11
9
33
24
24
9
43
36
33
26
50
44
23
21
9
20
42
42
11
2.5V SMU VRef PP2V5_SMU_VREF
32
MAKE_BASE=TRUE
_PP5V_RUN_FET
10
_PP5V_RUN_HD_FET
10
_PP3V3_RUN_FET
10
_PP2V5_RUN_FET
11
_PP1V8_RUN_LDO
9
_PP1V5_RUN_FET
9
5
_PP1V2_RUN_FET
9
_PP1V5_RUN_FET
9
5
PP1V8_RUN_LDO
MAKE_BASE=TRUE VOLTAGE=1.8V MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
XW592
JUMPER
OPEN
ALIAS
ALIAS
ALIAS
21
APPLE COMPUTER INC.
VOLTAGE=3.3V MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
PP5V_RUN
VOLTAGE=5V MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
PP3V3_RUN
ALIAS
PP2V5_RUN
ALIAS
XW518
JUMPER
PP1V5_RUN
ALIAS
PP1V2_RUN
OPEN
_PP3V3_ALL_ACIN
ALIAS
_PP3V3_ALL_DCILIM
ALIAS
_PP3V3_ALL_HALLEFFECT
ALIAS
_PP3V3_ALL_RTC
ALIAS
_PP3V3_ALL_SMU
ALIAS
_PPVREF_SMU
ALIAS
_PP5V_RUN_KBDLED
ALIAS
_PP5V_UATA
ALIAS
_PPBU_RUN_FW
ALIAS
PP5V_RUN_CPU
ALIAS
PP5V_RUN_HD
VOLTAGE=5V MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
ALIASALIAS ALIAS
VOLTAGE=3.3V MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
VOLTAGE=2.5V MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
PP1V8_RUN
VOLTAGE=1.5V MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
VOLTAGE=1.2V MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
6
_PP5V_PATA _PP5V_RUN_AUDIO
_PP3V3_SATABR _PP3V3_PATA
ALIAS
_PPVIO_PCI_USB2
ALIASALIAS
_PPVIO_PCI_CBUS
ALIAS
_PP3V3_PCI
ALIAS
_PP3V3_SB_PCI
ALIAS
_PP3V3_CPUVCORE
ALIAS
_PP3V3_RUN_FAN
ALIAS
_PP3V3_RUN_SI
ALIAS
_PP2V5_PCI
ALIAS
PP2V5_RUN_CPU
ALIAS
VOLTAGE=1.8V MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
21
ALIAS
PP1V5_AGP
ALIAS
PPVCORE_PULSAR
ALIAS
PP1V2_HT
ALIASALIAS
PP1V2_PULSAR
ALIAS
ONLY ONE CAN BE CLOSED Between XW590/XW591!!!
XW590
JUMPER
OPEN
XW591
JUMPER
OPEN
21
21
PP1V2_EI_NB VOLTAGE=1.2V MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
PP1V2_EI_CPU VOLTAGE=1.2V MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
Power Connections
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
051-6532
NONE
8
67
5
4
3
2
1
78
Wireless
FUNC_TEST=TRUE
PCI_AD<0>
FUNC_TEST=TRUE
PCI_AD<1>
FUNC_TEST=TRUE
PCI_AD<2>
FUNC_TEST=TRUE
PCI_AD<3>
FUNC_TEST=TRUE
PCI_AD<4>
FUNC_TEST=TRUE
D
C
B
A
PCI_AD<5>
FUNC_TEST=TRUE
PCI_AD<6>
FUNC_TEST=TRUE
PCI_AD<7>
FUNC_TEST=TRUE
PCI_AD<8>
FUNC_TEST=TRUE
PCI_AD<9>
FUNC_TEST=TRUE
PCI_AD<10>
FUNC_TEST=TRUE
PCI_AD<11>
FUNC_TEST=TRUE
PCI_AD<12>
FUNC_TEST=TRUE
PCI_AD<13>
FUNC_TEST=TRUE
PCI_AD<14>
FUNC_TEST=TRUE
PCI_AD<15>
FUNC_TEST=TRUE
PCI_AD<16>
FUNC_TEST=TRUE
PCI_AD<17>
FUNC_TEST=TRUE
PCI_AD<18>
FUNC_TEST=TRUE
PCI_AD<19>
FUNC_TEST=TRUE
PCI_AD<20>
FUNC_TEST=TRUE
PCI_AD<21>
FUNC_TEST=TRUE
PCI_AD<22>
FUNC_TEST=TRUE
PCI_AD<23>
FUNC_TEST=TRUE
PCI_AD<24>
FUNC_TEST=TRUE
PCI_AD<25>
FUNC_TEST=TRUE
PCI_AD<26>
FUNC_TEST=TRUE
PCI_AD<27>
FUNC_TEST=TRUE
PCI_AD<28>
FUNC_TEST=TRUE
PCI_AD<29>
FUNC_TEST=TRUE
PCI_AD<30>
FUNC_TEST=TRUE
PCI_AD<31>
FUNC_TEST=YES
PCI_FRAME_L
FUNC_TEST=YES
PCI_TRDY_L
FUNC_TEST=YES
PCI_IRDY_L
FUNC_TEST=YES
PCI_DEVSEL_L
FUNC_TEST=YES
PCI_STOP_L
FUNC_TEST=YES
PCI_PAR
FUNC_TEST=TRUE
PCI_CBE_L<0>
FUNC_TEST=TRUE
PCI_CBE_L<1>
FUNC_TEST=TRUE
PCI_CBE_L<2>
FUNC_TEST=TRUE
PCI_CBE_L<3>
FUNC_TEST=YES
PCI_SLOTA_REQ_L
FUNC_TEST=YES
PCI_SLOTA_GNT_L
FUNC_TEST=YES
PCI_SLOTA_INT_L
FUNC_TEST=YES
PCI_SLOTA_IDSEL
FUNC_TEST=YES
PCI_CLK33M_AIRPORT
FUNC_TEST=YES
TP_AIRPORT_PME_L
FUNC_TEST=YES
TP_AIRPORT_RF_DISABLE
FUNC_TEST=YES
AIRPORT_CLKRUN_L_PD
FUNC_TEST=YES PP3V3_RUN
GND x 4
Within 1" of connector
62
49
48
47
46
45
62
49
48
47
46
45
62
49
48
47
46
45
62
49
48
47
46
45
62
49
48
47
46
45
62
49
48
47
46
45
49
62
48
47
46
45
49
62
48
47
46
45
49
62
48
47
46
45
49
48
47
46
45
45
45
45
45
5
62
49
48
47
62
46
45
49
48
62
47
46
45
49
62
48
47
46
45
49
62
48
47
46
45
49
62
48
47
46
45
49
62
48
47
46
45
49
62
48
47
46
45
49
62
48
47
46
45
49
62
48
47
46
45
49
62
48
47
46
45
49
62
48
47
46
45
62
49
48
47
45
62
49
48
47
45
62
49
48
47
45
49
48
47
46
62
45
49
48
47
46
62
45
49
48
47
46
62
45
49
48
47
46
62
45
49
48
47
46
62
45
49
48
47
46
62
45
49
48
47
46
62
45
49
48
47
46
62
45
62
49
48
47
62
49
48
47
62
49
48
47
62
49
48
47
45
62
49
48
47
62
49
45 51
48
47 52
62
49
48
47
45
62
49
48
47
45
62
49
48
47
45
62
49
48
47
45
47
45
47
45
47
23
47
5
47
47
47
X 4
6
Within 1" of connector
Within 1" of connector
DVI/VGA
Within 1" of connector
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=YES
TMDS_CONN_CLKN
FUNC_TEST=YES
TMDS_CONN_CLKP
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
DVI_DDC_CLK_UF
FUNC_TEST=YES DVI_DDC_DATA_UF
FUNC_TEST=YES
FUNC_TEST=YES
PP5V_RUN_DDC
FUNC_TEST=YES GND_CHASSIS_IO
GND x 1
LVDS
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
CLKLVDS_LN
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
CLKLVDS_UN
FUNC_TEST=YES
CLKLVDS_UP
FUNC_TEST=YES
LVDS_DDC_CLK
FUNC_TEST=YES
LVDS_DDC_DATA
FUNC_TEST=YES
PP3V3_LCD
FUNC_TEST=YES
GND_CHASSIS_LVDS
2 x GND
INVERTER
FUNC_TEST=YES
PPBUS_ALL_A
FUNC_TEST=YES
PP5V_INVERTER
FUNC_TEST=YES
BRIGHT_PWM
1 x GND
FUNCTIONAL TEST POINTS
TMDS_DN<0>
TMDS_DP<0>
TMDS_DN<1>
TMDS_DP<1>
TMDS_DN<2>
TMDS_DP<2>
VGA_R
VGA_G
VGA_B
VGA_VSYNC
VGA_HSYNC
DVI_HPD_UF
LVDS_L0N
LVDS_L0P
LVDS_L1N
LVDS_L1P
LVDS_L2N
LVDS_L2P
CLKLVDS_LP
LVDS_U0N
LVDS_U0P
LVDS_U1N
LVDS_U1P
LVDS_U2N
LVDS_U2P
42
62
41
62
42
41
62
42
41
62
42
41
62
42
41
62
42
41
62
42
62
42
42
42
42
42
42
42
42
42
42
17
5
42
39
42
39
42
39
42
39
42
39
42
39
42
39
42
39
42
39
42
39
42
39
42
39
42
39
42
39
42
39
42
39
42
39
42
39
42
P
5
6
5
42
42
8
6
S-Video
Within 1 of connector
FUNC_TEST=YES
TV_GND1
FUNC_TEST=YES
TV_GND2
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
TV_COMP
TV_C
TV_Y
42
42
42
42
42
PATA (SATA Bridge)
Within 1" of connector
FUNC_TEST=TRUE
PATA_DD<0>
FUNC_TEST=TRUE
PATA_DD<1>
FUNC_TEST=TRUE
PATA_DD<2>
FUNC_TEST=TRUE
PATA_DD<3>
FUNC_TEST=TRUE
PATA_DD<4>
FUNC_TEST=TRUE
PATA_DD<5>
FUNC_TEST=TRUE
PATA_DD<6>
FUNC_TEST=TRUE
PATA_DD<7>
FUNC_TEST=TRUE
PATA_DD<8>
FUNC_TEST=TRUE
PATA_DD<9>
FUNC_TEST=TRUE
PATA_DD<10>
FUNC_TEST=TRUE
PATA_DD<11>
FUNC_TEST=TRUE
PATA_DD<12>
FUNC_TEST=TRUE
PATA_DD<13>
FUNC_TEST=TRUE
PATA_DD<14>
FUNC_TEST=TRUE
PATA_DD<15>
FUNC_TEST=TRUE
PATA_DMARQ_R
FUNC_TEST=TRUE
PATA_DMACK_L
FUNC_TEST=TRUE
PATA_DA<0>
FUNC_TEST=TRUE
PATA_DA<1>
FUNC_TEST=TRUE
PATA_DA<2>
FUNC_TEST=TRUE
PATA_CS0_L
FUNC_TEST=TRUE
PATA_CS1_L
FUNC_TEST=TRUE
PATA_RESET_L
FUNC_TEST=TRUE
PATA_DSTROBE_R
FUNC_TEST=TRUE
PATA_HSTROBE
FUNC_TEST=TRUE
PATA_STOP
FUNC_TEST=TRUE
PATA_INTRQ_R
FUNC_TEST=TRUE
PP5V_RUN_HD
re
Within 1" of connector
FUNC_TEST=TRUE
PPLOGIC_PATA
GND x 5
Battery Conn
FUNC_TEST=YES PPBATT_ALL_F
FUNC_TEST=YES I2C_SMU_E_SCL
FUNC_TEST=YES I2C_SMU_E_SDA
FUNC_TEST=YES BATT_DET_L
FUNC_TEST=YES GND_BATT
52
51
52
51
52
51
52
51
52
51
52
51
52
51
52
51
52
51
51
52
52
51
52
51
52
51
52
51
52
51
52
51
52
52
51
52
51
52
51
52
51
52
51
52
51
52
51
52
52
51
52
x4
5
x3
52
x2
7
(I2C_BATT_SCL)
18
13
(I2C_BATT_SDA)
18
13
7
x2
7
DC-in Connectors
Within 1" of connector
FUNC_TEST=YES
PP18V5_ALL_DCIN
GND x 3
x 3
11
7
67
5
l
5
UATA (Optical)
Within 2" of connector
FUNC_TEST=TRUE
UATA_DD<0>
FUNC_TEST=TRUE
UATA_DD<1>
FUNC_TEST=TRUE
UATA_DD<2>
FUNC_TEST=TRUE
UATA_DD<3>
FUNC_TEST=TRUE
UATA_DD<4>
FUNC_TEST=TRUE
UATA_DD<5>
FUNC_TEST=TRUE
UATA_DD<6>
FUNC_TEST=TRUE
UATA_DD<7>
FUNC_TEST=TRUE
UATA_DD<8>
FUNC_TEST=TRUE
UATA_DD<9>
FUNC_TEST=TRUE
UATA_DD<10>
FUNC_TEST=TRUE
UATA_DD<11>
FUNC_TEST=TRUE
UATA_DD<12>
FUNC_TEST=TRUE
UATA_DD<13>
FUNC_TEST=TRUE
UATA_DD<14>
FUNC_TEST=TRUE
UATA_DD<15>
FUNC_TEST=TRUE
UATA_DMARQ_R
FUNC_TEST=TRUE
UATA_DMACK_L
FUNC_TEST=TRUE
UATA_DA<0>
FUNC_TEST=TRUE
UATA_DA<1>
FUNC_TEST=TRUE
UATA_DA<2>
FUNC_TEST=TRUE
UATA_CS0_L
FUNC_TEST=TRUE
UATA_CS1_L
FUNC_TEST=TRUE
UATA_RESET_L
FUNC_TEST=TRUE
UATA_DSTROBE_R
FUNC_TEST=TRUE
UATA_HSTROBE
m
FUNC_TEST=TRUE
UATA_STOP
FUNC_TEST=TRUE
i
UATA_INTRQ_R
FUNC_TEST=TRUE
PP5V_RUN
GND x 5
Trackpad
Within 3" of connector
FUNC_TEST=YES
I2C_SMU_B_SCL
FUNC_TEST=YES
I2C_SMU_B_SDA
FUNC_TEST=YES
SYS_OVERTEMP_L
FUNC_TEST=YES
USB2_N<4>
FUNC_TEST=YES
USB2_P<4>
FUNC_TEST=YES
KBDLED_ANODE
FUNC_TEST=YES
KBDLED_RETURN
FUNC_TEST=YES
SYS_DOOR_AJAR
FUNC_TEST=YES
SYS_POWER_BUTTON_L
FUNC_TEST=YES PP3V3_PWRON
FUNC_TEST=YES PP5V_PWRON
FUNC_TEST=YES PP3V3_ALL
FUNC_TEST=YES PP3V3_RUN
4
52
50
52
50
52
50
52
50
52
50
52
50
52
50
52
50
52
50
52
50
52
50
50
52
52
50
52
50
52
50
52
50
52
52
50
52
50
52
50
52
50
52
50
52
50
52
50
52
52
50
52
50
52
x4
(I2C_DS1775_SCL)
18
13
(I2C_DS1775_SDA)
18
13
25
23
17
15
13
59
5
59
5
19
17
19
17
(SYS_LID_OPEN)
42
17
16
13
6
25
17
11
6
6
6
5
4
i
Firewire B
Within 1" of connector
FUNC_TEST=YES
FW_PORT1_TPA_P_FL
FUNC_TEST=YES
FW_PORT1_TPA_N_FL
FUNC_TEST=YES
FW_PORT1_TPB_P_FL
FUNC_TEST=YES
FW_PORT1_TPB_N_FL
FUNC_TEST=YES
FW_PORT1_AREF
FUNC_TEST=YES
GND_FW_PORT1_VG
FUNC_TEST=YES
PPFW_PORT1_VP
Firewire A
Within 1" of connector
FUNC_TEST=YES
FW_PORT2_TPA_P_FL
FUNC_TEST=YES
FW_PORT2_TPA_N_FL
FUNC_TEST=YES
FW_PORT2_TPB_P_FL
FUNC_TEST=YES
FW_PORT2_TPB_N_FL
FUNC_TEST=YES
PPFW_PORT2_VP
FUNC_TEST=YES
GND_FW_PORT2_VG
Fan Connectors
Within 2" of connector
FUNC_TEST=YES FAN_RPM0
n
FUNC_TEST=YES FAN_TACH0
FUNC_TEST=YES FAN_RPM1
FUNC_TEST=YES FAN_TACH1
FUNC_TEST=YES PP5V_PWRON
GND x 2 - one by each fan
BT/USB Flex
Within 2" of connector
FUNC_TEST=YES USB2_N<2>
FUNC_TEST=YES USB2_P<2>
FUNC_TEST=YES USB2_N<0>
FUNC_TEST=YES USB2_P<0>
FUNC_TEST=YES USB2_PWREN<0>
FUNC_TEST=YES ALS0_OUT
FUNC_TEST=YES USB2_OC<0>
FUNC_TEST=YES ALS_GAIN_BOOST
FUNC_TEST=YES ADAPTER_ID
PP3V3_PWRON x 1 PP5V_PWRON x 1 GND x 1
Backup Battery/USB Flex
Within 2" of connector
FUNC_TEST=YES
PPBUS_ALL_B
FUNC_TEST=YES
PPBUS_ALL_A
FUNC_TEST=YES
SYS_POWERUP
FUNC_TEST=YES
USB2_N<1>
FUNC_TEST=YES
USB2_P<1>
FUNC_TEST=YES
USB2_PWREN<1>
FUNC_TEST=YES
USB2_OC<1>
PP5V_PWRON x 1 GND x 1
3
58
58
58
58
58
58
58
58
58
58
58
58
58
ry
a
15
13
15
13
15
13
15
13
x 2 one by each fan
11
6
(USB_BT_N)
59
5
(USB_BT_P)
59
5
(USB2_LT_N)
59
5
(USB2_LT_P)
59
5
(LTUSB_PWREN)
59
5
17
13
(LTUSB_OVERCURRENT)
59
5
17
19
13
17
6
5
6
5
14
(USB2_RT_N)
59
5
(USB2_RT_P)
59
5
(RTUSB_PWREN)
59
5
(RTUSB_OVERCURRENT)
59
5
3
Sound Connector
Within 2" of connector
FUNC_TEST=YES
I2S0_DEV_TO_SB_DTI_F
FUNC_TEST=YES
I2S0_BITCLK_F
FUNC_TEST=YES
I2S0_MCLK_F
FUNC_TEST=YES
I2S0_SYNC_F
FUNC_TEST=YES
I2S0_SB_TO_DEV_DTO_F
FUNC_TEST=YES
I2S2_DEV_TO_SB_DTI_F
FUNC_TEST=YES
I2S2_BITCLK_F
FUNC_TEST=YES
I2S2_SYNC_F
FUNC_TEST=YES
AUDIO_GPIO_11
FUNC_TEST=YES
AUDIO_EXT_MCLK_SEL
FUNC_TEST=YES
AUDIO_LO_MUTE_L
FUNC_TEST=YES
AUDIO_SPKR_MUTE_L
FUNC_TEST=YES
AUDIO_LO_DET_L
FUNC_TEST=YES
AUDIO_LO_OPTICAL_PLUG_L
FUNC_TEST=YES
AUDIO_LI_DET_L
FUNC_TEST=YES
AUDIO_LI_OPTICAL_PLUG_L
FUNC_TEST=YES
I2S0_RESET_L_F
FUNC_TEST=YES
I2S2_RESET_L_F
FUNC_TEST=YES
SLEEPLED_ANODE
FUNC_TEST=YES
GND_AUDIO
FUNC_TEST=YES
PP5V_PWRON_AUDIO
FUNC_TEST=YES
PP3V3_PWRON_AUDIO
GND x 2
Modem Connector
Within 3" of connector
FUNC_TEST=YES
I2S1_SB_TO_DEV_DTO
FUNC_TEST=YES
I2S1_BITCLK
FUNC_TEST=YES
I2S1_SYNC
FUNC_TEST=YES
I2S1_RESET_L
FUNC_TEST=YES
I2S1_MCLK
FUNC_TEST=YES
I2S1_DEV_TO_SB_DTI
FUNC_TEST=YES
USB2_N<3>
FUNC_TEST=YES
USB2_P<3>
FUNC_TEST=YES
MODEM_RING2SYS_L
FUNC_TEST=YES
UDASH_SDOWN
FUNC_TEST=YES
I2C_SB_SCL
FUNC_TEST=YES
I2C_SB_SDA
APPLE COMPUTER INC.
2
ROM Control
Within 2" of U7500
61
61
61
61
61
61
61
61
61
23
61
23
61
23
61
23
61
23
61
23
61
23
61
23
61
61
61
19
x4
61
x3
61
x2
61
60
23
16
23
60
16
60
23
16
23
16
60
60
23
16
23
16
60
(USB_MODEM_N)
59
5
(USB_MODEM_P)
59
5
60
23
60
23
(I2C_MODEM_SCL)
23
18
(I2C_MODEM_SDA)
23
18
(SMU_BOOT_BUSY)
(SMU_BOOT_SCLK)
(SMU_BOOT_CE)
Functional Testpoints
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
051-6532
NONE
12
FUNC_TEST=YES
ROM_ONBOARD_CS_L
FUNC_TEST=YES
ROM_OE_L
FUNC_TEST=YES
ROM_CS_L
FUNC_TEST=YES
ROM_WE_L
MISC
FUNC_TEST=YES JTAG_NB_TMS
FUNC_TEST=YES
JTAG_NB_TDI
FUNC_TEST=YES
JTAG_NB_TDO
FUNC_TEST=YES JTAG_NB_TCK
FUNC_TEST=YES
JTAG_NB_TRST_L
FUNC_TEST=YES JTAG_SB_TMS
FUNC_TEST=YES
JTAG_SB_TDI
FUNC_TEST=YES
JTAG_SB_TDO
FUNC_TEST=YES JTAG_SB_TCK
FUNC_TEST=YES
JTAG_SB_TRST_L
FUNC_TEST=YES
JTAG_VESTA_TMS
FUNC_TEST=YES
JTAG_VESTA_TDI
FUNC_TEST=YES
JTAG_VESTA_TDO
FUNC_TEST=YES
JTAG_VESTA_TCK
FUNC_TEST=YES
JTAG_VESTA_TRST_L
FUNC_TEST=YES
JTAG_CPU_TMS
FUNC_TEST=YES
JTAG_CPU_TDI
FUNC_TEST=YES
JTAG_CPU_TDO
FUNC_TEST=YES
JTAG_CPU_TCK
FUNC_TEST=YES
JTAG_CPU_TRST_L
FUNC_TEST=YES
SMU_RESET_L
FUNC_TEST=YES
SYS_POWER_BUTTON_L
FUNC_TEST=YES
SYS_RESET_BUTTON_L
FUNC_TEST=YES
PP1V8_RUN
FUNC_TEST=YES
PP2V5_PWRON
FUNC_TEST=YES
PPBUS_ALL_B
FUNC_TEST=YES
PP3V3_ALL
FUNC_TEST=YES
PPVCORE_RUN_CPU
FUNC_TEST=YES
PP1V2_RUN_GPU
FUNC_TEST=YES
CPU_VID<4>
FUNC_TEST=YES
CPU_VID<5>
FUNC_TEST=YES
SMU_BOOT_CNVSS
FUNC_TEST=YES
SMU_BOOT_TXD
FUNC_TEST=YES
SMU_BOOT_RXD
FUNC_TEST=YES
SYS_POWERUP_L
SHT
OF
6
1
47
46
47
46
45
46
47
45
46
47
45
22
22
22
22
22
23
18
23
18
23
23
18
23
18
12
12
12
12
12
27
28
18
27
28
18
28
27
18
27
28
18
28
27
16
19
13
16
13
6
16
13
5
6
5
6
5
5
31
13
13
16
13
16
13
16
13
14
13
REV.
03
103
D
C
42
17
B
A
G
D
S
G
D
S
D1
D2
D3
D4S3
S2
GATE
S1
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
NONE
Place L759 as close to J750 as possible
518S0117
Main Battery Connector
<R1a>
DC Power Input
(DC-In jack and associated circuit are on separate baord)
Vref = 3.3V * (R2a / (R1a + R2a))
ACIN Detection
<R2b>
<R1b>
Power Connectors
DC Inrush Limiter
<R2a>
Vth = 13.4V
Vth = Vref / (R2b / (R1b + R2b))
(BATT_IN_PD)
(GND_BATT)
(PPBATT_F)
1K resistor to protect SMU pins
518S0064
2
1
R705
402
MF
5%
10K
2
1
R708
MF
1%
102K
402
2
1
R709
MF
1%
10K
402
2
1
R710
402
MF
1%
102K
2
1
R711
MF
1%
57.6K
402
2
1
C700
50V
0.1uF
10% X7R
NO STUFF
2
5
1
3
4
U710
LMC7211
SM
CRITICAL
2
1
R713
470K
5% 1/16W MF 402
21
R712
MF
5%
402
1M
4
5
3
Q715
SOT-363
2N7002DW
1
2
6
Q715
2N7002DW
SOT-363
2
1
R719
5% MF
470K
402
2
1
R715
MF
402
5%
10K
2
1
C710
0.01uF
20%
402
16V CERM
2
1
R720
402
5%
330K
MF
2
1
C720
0.22uF
25V
20% CERM
805
21
L751
SM
FERR-50-OHM
CRITICAL
21
L755
FERR-EMI-100-OHM
SM
21
L756
FERR-EMI-100-OHM
SM
21
R755
5%
1K
402
MF
2
1
R754
402
470K
5% 1/16W MF
2
1
R706
5%
402
MF
10K
PP3V3_ALL
9
8
7
6
5
4
3
2
10
1
J750
M-RT-SM
CRITICAL
87438-1033
21
L759
SM
FERR-EMI-100-OHM
21
L750
FERR-50-OHM
SM
CRITICAL
3 2 1
4
8 7 6 5
Q720
SI4405DY
SO-8
CRITICAL
4
3
2
1
J700
87438-0433
M-RT-SM
CRITICAL
7 103
051-6532
03
I2C_BATT_SCL
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=25 mil
VOLTAGE=0V
GND_BATT
MIN_NECK_WIDTH=10 mil
PPBATT_ALL_VSNS
VOLTAGE=12.8V MIN_LINE_WIDTH=10 mil
MIN_LINE_WIDTH=25 mil
VOLTAGE=12.8V
PPBATT_ALL
MIN_NECK_WIDTH=10 mil
BATT_DET_L
I2C_BATT_SDA_F
I2C_BATT_SCL_F
ACIN_DIV
ADAPTER_PD
SMU_BATT_DET_L
MIN_LINE_WIDTH=8 mil
ACIN_ENABLE_L MIN_NECK_WIDTH=8 mil
I2C_BATT_SDA
MIN_LINE_WIDTH=8 mil
ACIN_ENABLE_L_DIV MIN_NECK_WIDTH=8 mil
MIN_LINE_WIDTH=25 mil
VOLTAGE=18.5V
PP18V5_ALL_INRUSH
MIN_NECK_WIDTH=10 mil
_PP3V3_ALL_ACIN
PP18V5_ALL_DCIN
VOLTAGE=18.5V MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
ACIN_1V20_REF
MAKE_BASE=TRUE
SMU_ACIN
SMU_ACIN_L
MIN_LINE_WIDTH=25 mil
VOLTAGE=12.8V MIN_NECK_WIDTH=10 mil
PPBATT_ALL_F
13
11
12
18
6
8
8
6
13
18
8
5
6
8
8
6
Preliminary
S2
GATE
S1
S3 D4
D3 D2
D1
S2
GATE
S1
S3D4
D3 D2
D1
S
D
G
S
D
G
G
D
S
G
D
S
G
D
S
G
D
S
CSSP CSSN
ACIN
DCIN
SCL SDA INT*
IMAX VMAX
CCS
CCI
CCV
CSIP CSIN
VDD LDO
SRC
PDL
PDS
REF
DHIV
DHI
DLO
PGND
PAD
THM
GND
DAC
ACOK*
THM
BATT
I.C.
DLOV
G
D4
D2
S3
S2
D1
D3
S1
D1
D2
D3
D4 S3
S2
GATE
S1
G
D
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
NONE
DC-IN Input Current Limiter
Place U800 and U870 near R800
NC
SMBus Battery Charger
Battery Charge Path
Battery charge FET is open when not charging
Keep short and route as pair
RC time is 480K * 10uF @ 3.3V
NC
NC
NC
(PP18V5_ALL)
NC
SMBus Battery Charger
(PP18V5_ALL_SENSE)
FETs are quickly turned off (diode)
When AC is connected, P-channel
When AC is disconnected, P-channel FETs turn on
Battery Switch-over Circuit
2
1
C826
603
CERM
10V
1UF
20%
2
1
R821
169K
1%
MF
402
2
1
R820
100K
1% MF
402
2
1
R801
4.7
5%
402
MF
2
1
R802
5% 1/16W
402
MF
4.7
2
1
C801
50V
0.47UF
1206
20%
CERM
2
1
D810
MBRS140T3
SM
21
R800
0.010
MF
1%
CRITICAL
1/2W 1206
2
1
C802
0.47UF
CERM
50V
20%
1206
2
1
R896
402
MF
5%
100K
3 2 1
4
8 7 6 5
Q890
CRITICAL
SOI
SI4435DY
3 2 1
4
8 7 6 5
Q880
CRITICAL
SI4435DY
SOI
2
1
R881
402
MF
5% 1/16W
330K
2
1
R891
100K
5%
402
MF
2
1
R890
470K
MF
5%
402
3
1
4
Q895
SUD45P03
TO-252
CRITICAL
2
1
R895
470K
MF
5%
402
3
1
4
Q899
SUD45P03
TO-252
CRITICAL
4
5
3
Q800
SOT-363
2N7002DW
2
1
C897
CERM
805
6.3V
20%
10uF
2
1
R897
1%
158K
MF
43
DP800
BAS16TW
SOT-363
2
1
R898
402
MF
5%
100K
2
1
F899
SM-2
5AMP-125V
2
1
F895
5AMP-125V
SM-2
2
1
R899
5% 1/16W
402
470K
MF
2
1
C812
20% 25V CERM 1206
4.7uF
2
1
C813
4.7uF
1206
CERM
25V
20%
2
1
C815
4.7uF
1206
CERM
25V
20%
2
1
C814
4.7uF
1206
CERM
25V
20%
2
1
C817
4.7uF
1206
CERM
25V
20%
2
1
C816
4.7uF
1206
CERM
25V
20%
2
1
C818
CRITICAL
20% 25V ELEC SM1
33uF
2
1
R812
603
MF
5% 1/16W
1
21
R810
1% MF
0.010
CRITICAL
1/2W 1206
21
L810
SM1
10uH
CRITICAL
2
1
R811
1
5%
603
MF
2
1
R825
402
20.5K
1% 1/16W MF
2
1
R824
MF
1%
100K
402
2
1
C825
1uF
CERM
20%
603
10V
2
1
C823
402
16V
0.01uF
CERM
20%
2
1
R805
NO STUFF
100K
1%
402
MF
2
1
R806
NO STUFF
13K
1%
402
MF
3
1
D800
1N914
2
1
C800
805
CERM
25V
20%
1uF
2
1
R850
MF 402
49.9K
1%
2
1
R851
5% MF
68K
2
1
C851
CERM
20%
0.1uF
25V 603
1
2
6
Q800
2N7002DW
SOT-363
2
1
R880
5% MF
402
470K
52
DP800
SOT-363
BAS16TW
2
1
C882
16V
10%
CERM
402
0.01UF
2
1
R882
MF
100K
5%
402
2
1
C811
10% 50V
402
CERM
0.001uF
NO STUFF
1
2
6
Q882
SOT-363
2N7002DW
4
5
3
Q882
SOT-363
2N7002DW
2
1
C805
25V 1206
4.7uF
20% CERM
2
1
C806
25V 1206
20% CERM
4.7uF
2
1
C807
1206
4.7uF
20% 25V CERM
2
1
C808
4.7uF
1206
CERM
20% 25V
2
1
C829
1UF
603
CERM
20% 10V
2
1
C824
20% 16V
CERM
402
0.01UF
2
1
C827
0.1UF
CERM
25V
20%
603
2
1
R826
5%
MF
402
33
2
1
C830
402
10V
0.1UF
CERM
20%
2
1
C831
0.1UF
402
10V
20%
CERM
9
12
33
13
27
14
15
4
22
31 30
2
16
10
17
18
5
24
23
25 26
1
11
29 28
21 20
8
6
7
19
32
3
U800
MAX1535A
CRITICAL
QFN
2
1
R828
5% 1/16W MF
0
402
2
1
C828
0.1UF
20%
603
CERM
25V
2
1
R827
5%
MF
0
402
2
1
R892
100K
5%
402
MF
21
R823
0
MF
5%
402
2
1
C820
0.1UF
402
CERM
10V
20%
321
4
876
5
Q810
SOI
CRITICAL
SI4835BDY
2
1
R829
100K
5%
MF
402
3 2 1
4
8 7 6 5
Q850
CRITICAL
SI4405DY
SO-8
2
1
R830
100K
5% 1/16W MF 402
4
5
3
Q877
2N7002DW
SOT-363
321
4
8765
Q811
SI4336DY
CRITICAL
SO-8
2
1
R822
5%
402
MF
30K
2
1
C822
16V
0.01uF
20%
CERM
402
21
XW800
SM
03
051-6532
1038
PP18V5_ALL_INRUSH
VOLTAGE=18.5V MIN_NECK_WIDTH=10 mil
PP18V5_ALL_SENSE
MIN_LINE_WIDTH=25 mil
_PPBUS_ALL_B
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=10 mil
BKFD_PROT_EN_L_DIV
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=25 mil
VOLTAGE=12.6V
PPBATT_ALL_FUSEA
CHGR_THM
_PPBUS_ALL_A
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=20 mil
CHGR_DLOV_RC
MIN_LINE_WIDTH=10 mil MIN_NECK_WIDTH=10 mil
PP5V4_CHGR_LDO
VOLTAGE=5.4V
CHGR_DAC
CHGR_CSSP CHGR_CSSN
CHGR_VMAX
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=15 mil
VOLTAGE=0V
GND_CHGR
CHGR_CCS
CHGR_IMAX
_PPBUS_ALL_A _PPBUS_ALL_B
CHGR_ACIN_RC
PPBATT_ALL
CHGR_DCIN
MIN_NECK_WIDTH=10 mil
CHGR_DHI MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
CHGR_DHIV MIN_LINE_WIDTH=20 mil
CHGR_DLOV
PPBATT_ALL_VSNS
I2C_CHGR_SCL I2C_CHGR_SDA
MIN_NECK_WIDTH=10 mil
BATT_PBUSA_EN_L MIN_LINE_WIDTH=10 mil
MIN_LINE_WIDTH=10 mil MIN_NECK_WIDTH=10 mil
BATT_PBUSB_EN_L
CHGR_CHARGE_EN_L
SMU_ACIN_L
_PPBUS_ALL_A
MIN_NECK_WIDTH=10 mil
PPBATT_ALL_FUSEB
VOLTAGE=12.6V MIN_LINE_WIDTH=25 mil
CHGR_PBUS_EN_L
MIN_LINE_WIDTH=10 mil
CHGR_PBUS_EN_L_DIV MIN_NECK_WIDTH=10 mil
SMU_ACIN
CHGR_CCV
PPBATT_CHGR_RSNS
MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
CHGR_CCS_RC CHGR_CCI_RC
CHGR_CCV_RC
CHGR_CHARGE_EN_L_DIV
PPBATT_CHGR_OUT
BATT_ACIN_L_RC
BATT_PBUS_EN_L
SMU_ACIN
CHGR_CCI
SMU_CHARGE_BATT
CHGR_ACIN
CHGR_REF
SMU_CHARGE_BATT
CHGR_CSIP
SMU_CHARGE_BATT_L
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=10 mil
BKFD_PROT_EN_L
CHGR_CSIN
MIN_LINE_WIDTH=25 mil
PPBATT_CHGR_OUT
VOLTAGE=12.6V MIN_NECK_WIDTH=10 mil
CHGR_REF
MIN_LINE_WIDTH=25 mil
CHGR_DLO MIN_NECK_WIDTH=10 mil
MIN_NECK_WIDTH=10 mil
PPBATT_CHGR_SW MIN_LINE_WIDTH=25 mil
42
42
42
13
13
17
17
17 17
17
12
12
8
8
8 8
8
8
8
13
13
7
5
11
5
5 5
7
7
18
18
7
5
7
8
7
8
8
8
8
8
Preliminary
SW
SGND PGND
PAD
THERM
SVIN PVIN
PGOOD
VFB
ITH SYNC/MODE
RUN/SS
RT
GND
SET
SHDN*
OUT1
FAULT*
OUT2
CC
IN
VIN
LBO
PG
SW
FB
SYNC
GND
PGND
LBI
EN
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
NONE
1.8V/1.5V/1.2V MAIN SUPPLIES
1.8V/1.5V Supplies
NC
for fix voltage part
Burst
Continuous
powers up with PP5V_PWRON
SET internally disconnected
300mA output
LB - low battery - NOT USED
2
1
C981
CERM
50V
0.0022uF
10%
402
4
36
5
2
1
Q980
SI3446DV
TSOP
CRITICAL
2
1
C980
CERM
805
6.3V
20%
10UF
2
1
C956
20%
22uF
6.3V CERM 1206
2
1
C955
22uF
20%
6.3V CERM 1206
2
1
C952
CERM
6.3V 1206
20%
22uF
2
1
C951
CERM
6.3V
20%
1206
22uF
2
1
R958
5%
100K
2
1
C950
22pF
402
5% CERM
50V
2
1
R950
470K
1%
MF
402
21
L950
1.0uH-3.5A
SM
CRITICAL
21
XW950
SM
4
17
6
15
14
11
10
1
8
7
5
16
9
2
13
12
3
U950
CRITICAL
LTC3412
TSSOP
2
1
R954
309K
1% 1/16W MF 402
2
1
R951
402
1%
MF
511K
2
1
R952
1%
MF
402
422K
2
1
R955
NO STUFF
5% 1/16W
0
402
MF
2
1
R956
5% 1/16W MF 402
0
2
1
C957
10% 50V
CERM
402
470pF
2
1
R953
402
MF
15K
1%
2
1
C954
402
50V
5% CERM
100pF
2
1
C953
10% 50V
CERM
402
0.001uF
2
1
R957
5% MF
402
5.1M
2
1
C961
402
50V CERM
10%
0.0022uF
4
36
5
2
1
Q960
TSOP
SI3446DV
CRITICAL
2
1
C960
805
6.3V CERM
20%
10UF
7
5
4
12
3
8
6
U940
LP3982
MSOP
21
R940
MF
603
0
5%
NO STUFF
21
R941
0
5%
603
MF
2
1
C940
2.2uF
20%
6.3V CERM1 603
2
1
C941
402
10V X7R
20%
0.033uF
2
1
C942
10UF
20%
6.3V CERM 805
21
L970
10uH
CRITICAL
CDRH4D28C-SM
2
1
R970
1%
100K
MF
402
2
1
R971
49.9K
402
MF
1%
2
1
C970
50V CERM
6.8pF
0.5pF%
402
2
1
C972
22uF
6.3V CERM
20%
1206
2
1
C971
CERM
10UF
20%
6.3V 805
1
7
9
10
4
2
6
3
5
8
U970
TPS62050
MSOP
CRITICAL
1039
051-6532
03
_PP1V5_PWRON_REG
_PPVIN_1V5PWRON
MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
1V5PWRON_SW
1V2PWRON_VFB_DIV
_PP1V8_RUN_LDO
1V8RUN_SHDN_L
MIN_NECK_WIDTH=8 mil
1V8RUN_CC MIN_LINE_WIDTH=8 mil
1V8RUN_PGOOD
1V2PWRON_RUNSS
1V2PWRON_SGND
VOLTAGE=0V MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=10 mil
_PP3V3_PWRON_1V8RUN
1V2PWRON_RT
1V2PWRON_ITH 1V2PWRON_MODE
_PP1V5_PWRON_1V5RUN
1V5RUN_EN
_PP1V5_RUN_FET
1V2PWRON_ITH_RC
1V2PWRON_VFB
1V2PWRON_PGOOD
_PP1V2_PWRON_1V2RUN
1V2RUN_EN
_PP1V2_RUN_FET
_PP1V2_PWRON_REG
1V2PWRON_SW
MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
_PP2V5_PWRON_1V8RUN
PPVIN_1V8RUN
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=20 mil
_PPVIN_1V2PWRON
1V5PWRON_VFB_DIV
5 5
5
14 14
5
5
14
5
5
14
5
5
5
5
Preliminary
GND
FLT
POWERGOOD CT
REF
REG5V_IN
STBY2
STBY1
TRIP1
TRIP2
LH2 LH1
OUT1_UOUT2_U
LL1LL2
OUT2_D OUT1_D
OUTGND1OUTGND2
FB2 FB1
INV1INV2
SOFTSTART1SOFTSTART2
PWM/SKIP
VCC
VREF55V_STBY
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
NONE
DIODE WILL ENSURE DCDC_EN_L IS QUICKLY DISCHARGED DURING SHUT-DOWN
(GND)
5V START TO TURN ON ~12.5MS AFTER DCDC_EN_L
3V START TO TURN ON ~25MS AFTER DCDC_EN_L
(PP5V_PWRON)
is 10% necessary?
another 0.1uF needed?
POWERDOWN DELAY IS AROUND 4MS-15.6MS
3.3V/5V REGULATOR
(GND)
>2V = SKIP
3.3V/5V MAIN SUPPLY
<0.5V = PWM
4
3 6
5 2 1
Q1007
CRITICAL
TSOP
SI3443DV
21
C1009
402
10%
0.0022uF
50V
CERM
22 24
23 25
10
9
13
3
21
84
12
20 26
17
19
29
27
18 28
16 30
15
1
7
11
14
2
5
6
U1000
CRITICAL
TSOP
TPS5120
2
1
C1050
0.1uF
CERM
20% 25V
603
2 1
R1050
402
MF
5%
10
2
1
C1051
10V
20%
4.7UF
CERM 1206
3
1
D1030
30V-200MA
3
1
D1035
30V-200MA
2
1
D1031
SM
MBR0540
2
1
D1036
MBR0540
SM
21
R1031
3.3
5% MF
402
2
1
C1031
20%
0.1uF
10V CERM 402
21
R1035
5%
MF
402
3.3
2
1
C1035
402
20%
CERM
10V
0.1uF
2
1
C1052
CERM
0.01uF
402
20% 16V
2
1
R1053
402
MF
1%
15K
2
1
C1053
16V
0.01uF
20% CERM
402
2
1
C1065
CERM 1206
25V
20%
4.7uF
2
1
C1066
1206
CERM
25V
20%
4.7uF
2
1
C1067
1206
CERM
25V
20%
4.7uF
2
1
C1062
4.7uF
CERM
20% 25V
1206
2
1
C1061
4.7uF
20%
25V CERM 1206
2
1
C1060
1206
CERM
25V
20%
4.7uF
2
1
C1063
CERM 402
50V
0.001uF
10%
NO STUFF
2
1
C1068
50V 402
CERM
10%
0.001uF
NO STUFF
21
L1060
CRITICAL
4.7UH
IHLP-5050
2
1
C1077
22uF
6.3V CERM 1206
20%
2
1
C1076
1206
6.3V
20%
CERM
22uF
2
1
C1075
6.3V
20%
330uF
POLY CASE-D
CRITICAL
2
1
C1054
10% 25V
CERM
402
0.0047uF
2
1
R1073
20.5K
402
MF
1%
21
L1065
SM1
10uH
CRITICAL
2
1
R1081
10K
1%
402
MF
2
1
C1081
CERM
50V
0.001uF
402
10%
2
1
C1087
20%
6.3V
330uF
POLY CASE-D
CRITICAL
2 1
XW1003
SM
2
1
C1086
CERM
20%
22uF
6.3V 1206
2
1
C1085
1206
CERM
20%
22uF
6.3V
2
1
R1083
34.8K
1%
402
MF
2
1
R1080
100K
1% MF
402
2
1
C1058
10% 25V CERM 402
0.0047uF
2
1
C1057
402
10V
20%
0.1uF
CERM
2
1
C1056
5%
47pF
402
CERM
50V
2
1
C1055
0.1uF
CERM
402
10V
20%
2
1
C1059
CERM
25V
5%
402
220pF
2
1
D1060
SM
MBRS140T3
1
2
R1036
MF
0
5% 1/16W
402
12
C1080
5%
100pF
402
CERM
50V
12
R1082
5%
MF
10K
402
12
C1082
10% 16V
CERM
0.01uF
402
21
R1033
5%
402
MF
100K
3
2
4
1
7
6
5
8
Q1065
CRITICAL
SI4816DY
SOI
2
1
R1032
0
MF
5%
402
2
1
C1071
50V
10%
402
0.001uF
CERM
2
1
R1071
17.4K
MF
402
1%
2
1
R1070
MF
1%
402
100K
21
C1070
47pF
CERM
50V 402
5%
21
C1072
CERM
0.01uF
16V
10%
402
21
R1072
402
5% MF
10K
2
1
C1074
100uF
6.3V
20% TANT
CASE-B2
CRITICAL
NO STUFF
2
1
C1013
CRITICAL
CASE-B2
6.3V TANT
100uF
20%
2
1
C1012
CERM
20%
6.3V 805
10UF
2
1
C1003
20%
402
16V
CERM
0.01uF
2
1
C1001
CRITICAL
CASE-B-3528
POLY
20%
100uF
6.3V
2
1
C1004
CRITICAL
CASE-B-3528
POLY
6.3V
20%
100uF
4
3 6
5 2 1
Q1003
CRITICAL
TSOP
SI3443DV
2
1
C1011
CERM
20%
6.3V 805
10uF
2
1
C1005
0.1uF
10V 402
CERM
20%
4
3 6
5 2 1
Q1004
CRITICAL
SI3443DV
TSOP
2
1
C1006
CERM
20%
6.3V 805
10UF
3 2 1
4
8 7 6 5
Q1060
SO-8
CRITICAL
IRF7821
3 2 1
4
8 7 6 5
Q1061
SO-8
CRITICAL
SI4336DY
2
1
R1052
11K
MF 402
1%
03
051-6532
10310
_PP5V_PWRON_REG
5VPWRON_INV
5V3VPWRON_CT
3V3PWRON_SS
MIN_LINE_WIDTH=15 mil
GND_5V3V VOLTAGE=0V
MIN_NECK_WIDTH=10 mil
5V3VPWRON_PGOOD
3V3RUN_EN_L
_PP3V3_PWRON_3V3RUN
_PP3V3_RUN_FET
5VRUN_EN_L
_PP5V_PWRON_5VRUN
5VRUNHD_EN_L
_PP5V_RUN_FET
_PP5V_RUN_HD_FET
5VPWRON_FB
VOLTAGE=5V
PP5V_5V3V_VREF5
MIN_LINE_WIDTH=20 mil MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=15 mil MIN_NECK_WIDTH=10 mil
PPVCC_ALL_3V5V
VOLTAGE=18.5V
5VPWRON_TRIP
3V3PWRON_LH
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=25 mil
3V3PWRON_TRIP
5VPWRON_SS
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=25 mil
5VPWRON_OUT_U
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=25 mil
3V3PWRON_OUT_D
SYS_SLEEP
3V3PWRON_LL
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=25 mil
5VPWRON_FB_RC
3V3PWRON_FB_RC
3V3PWRON_INV_RC
5VPWRON_LH
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=25 mil
5V3VPWRON_SKIP
5V3VPWRON_FLT
5VPWRON_LL
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=25 mil
MIN_LINE_WIDTH=20 mil MIN_NECK_WIDTH=10 mil
5VPWRON_BOOST_ESR
_PP3V3_PWRON_REG
3V3PWRON_FB
3V3PWRON_INV
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=25 mil
3V3PWRON_SW
MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
3V3PWRON_OUT_U
5V3VPWRON_REF
5VPWRON_INV_RC
MIN_LINE_WIDTH=20 mil
3V3PWRON_BOOST_ESR
MIN_NECK_WIDTH=10 mil
_PPVIN_5V3VPWRON
3V3_STBY_L
5V_STBY_L
MIN_NECK_WIDTH=10 mil
5VPWRON_OUT_D
MIN_LINE_WIDTH=25 mil
5VPWRON_SW
MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
25 11
5
14
14
5
5
14
5
14
5
5
5
5
5
14 14
Preliminary
GND
FLT
POWERGOOD CT
REF
REG5V_IN
STBY2
STBY1
TRIP1
TRIP2
LH2
LH1
OUT1_U
OUT2_U
LL1
LL2
OUT2_D
OUT1_D
OUTGND1OUTGND2
FB2 FB1
INV1INV2
SOFTSTART1SOFTSTART2
PWM/SKIP
VCC
VREF55V_STBY
VTAP
IN OUT SENSE
GND
FDBK
ERR
LP2951
SHUT
SHUT
PLUS5VTAP
LP2951
ERR
FDBK
GND
SENSE
OUTIN
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
NONE
1.328V
Bootstrap system from adapter or battery
PP3V3_ALL LDO
PP4V6_ALL Generation
NC
NC
NC NC
> 2V = SKIP
(GND)(GND)
< 0.5V = PWM
2.5V/NBVCORE/PMU SUPPLIES
2.5V/NBVCORE MAIN SUPPLIES
2
1
C1117
1206
CERM
25V
20%
4.7uF
2
1
C1116
4.7uF
20% 25V CERM 1206
2
1
C1115
20% 25V CERM 1206
4.7uF
2
1
C1148
20%
6.3V POLY CASE-D
330uF
CRITICAL
2
1
C1125
330uF
POLY
CASE-D
20%
6.3V
CRITICAL
2
1
C1126
1206
6.3V
22uF
20% CERM
2
1
C1127
CERM
20%
22uF
6.3V 1206
2
1
C1141
0.001uF
50V 402
CERM
10%
2
1
R1141
17.4K
1%
402
MF
2 1
XW1104
SM
21
L1110
CRITICAL
4.7UH
IHLP-5050
2
1
R1140
100K
402
MF
1%
2
1
R1143
51.1K
MF 402
1% 1/16W
2
1
R1142
10K
402
MF
1%
2
1
C1142
16V
0.01uF
402
10%
CERM
2
1
C1140
47pF
CERM
402
50V
5%
3
1
D1135
30V-200MA
2
1
C1103
16V
0.01uF
CERM
20%
402
21
R1136
402
0
5% MF
2
1
R1103
402
MF
1% 1/16W
11K
2
1
C1100
0.1uF
20% 25V CERM 603
2 1
R1100
402
MF
5%
10
2
1
C1101
20%
4.7UF
1206
10V
CERM
2
1
R1102
402
MF
1%
20K
2
1
C1102
0.01uF
16V 402
CERM
20%
21
R1132
402
MF
5%
0
2
1
D1130
MBR0540
SM
2
1
C1112
4.7uF
1206
CERM
25V
20%
2
1
C1118
0.001uF
10% 50V
CERM
402
NO STUFF
2
1
C1135
0.1uF
10V 402
CERM
20%
21
R1135
1.8
5% MF
402
2
1
C1108
0.0047uF
10% 25V CERM 402
2
1
C1107
0.1uF
20% 10V CERM 402
2
1
C1106
68pF
5% 50V CERM
2
1
D1136
MBR0540
SM
2
1
C1105
0.1uF
20% 10V
402
CERM
22 24
23 25
10
9
13
3
21
84
12
20 26
17
19
29
27
18 28
16 30
15
1
7
11
14
2
5
6
U1100
TSOP
TPS5120
CRITICAL
2
1
D1131
SM
MBR0540
2
1
C1104
402
CERM
25V
10%
0.0047uF
2
1
C1131
402
0.1uF
20% 10V
CERM
21
R1131
1.8
MF
5%
402
2
1
C1113
0.001uF
10% 50V CERM 402
NO STUFF
3 2 1
4
5
Q1115
SO-8-PWRPK
SI7392DP
CRITICAL
2
1
C1120
402
150pF
5% 50V CERM
2
1
R1122
5.36K
402
MF
1%
2
1
C1122
0.01uF
10% 16V CERM 402
2
1
C1111
CERM 1206
4.7uF
25V
20%
2
1
C1110
25V CERM 1206
20%
4.7uF
21
L1115
IHLP
CRITICAL
2.2uH-16A
2
1
R1120
51.1K
1%
402
MF
2
1
R1121
402
MF
1% 1/16W
17.4K
2
1
C1121
402
CERM
50V
10%
680pF
2
1
C1145
1206
6.3V
20%
CERM
22uF
2
1
R1123
1%
402
MF
90.9K
2
1
C1146
1206
6.3V
22uF
CERM
20%
2
1
C1147
CASE-D
POLY
330uF
6.3V
20%
CRITICAL
2
1
C1109
402
CERM
25V
220pF
5%
2
1
D1110
SM
MBRS140T3
2
1
D1115
B340LB
SMB
21
R1133
402
MF
100K
5%
7 6 3 2
4
8 5 1
Q1190
SI6467BDQ
CRITICAL
2
1
C1190
10UF
20%
CERM
6.3V 805
21
C1192
0.0022uF
402
10% 50V
CERM
2
1
R1171
MF
5% 1/16W
603
1
6
3
2
18
4
7
5
U1170
CRITICAL
SOI-3.3V
2
1
C1171
805
CERM
20%
10uF
6.3V
21
D1164
SM
MBR0520LT
NO STUFF
21
D1163
NO STUFF
SM
MBR0520LT
2
1
C1170
0.1uF
402
CERM
10V
20%
2
1
R1164
1
603
MF
5%
2
1
R1162
402
MF
1%
294K
2
1
C1162
402
CERM
50V
10%
470pF
2
1
C1164
805
CERM
10V
20%
2.2uF
2
1
R1163
402
MF
1%
100K
2
1
C1161
402
CERM
10V
20%
0.1uF
3
2
6
18
4
7
5
U1160
CRITICAL
SOI
2
1
C1160
603
25V
0.1uF
20% CERM
21
R1166
1210
137
1%
1/4W
FF
2
1
D1162
SM
MBR0540
3
1
D1161
1N914
21
D1160
SM
MBR0540
3
1
D1165
1N5228B
21
R1161
0
5%
FF
805
321
4
8765
Q1110
SO-8
CRITICAL
IRF7821
2
1
C1193
100uF
20%
6.3V POLY CASE-B-3528
321
4
8765
Q1111
SO-8
CRITICAL
SI4336DY
3 2 1
4
8 7 6 5
Q1116
SO-8
CRITICAL
SI4336DY
10311
03
051-6532
2V5_ITRIP
2V5PWRON_SW MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=25 mil
2V5_LO_GATE
NBVCORE_LO_GATE
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=25 mil
SYS_SLEEP
2V5_NBVCORE_PWM
MIN_LINE_WIDTH=25 mil
NBVCORE_HI_GATE
MIN_NECK_WIDTH=10 mil
_PPVIN_2V5_NBVCORE_PWRON
MIN_NECK_WIDTH=10 mil
2V5_NBVCORE_VCC MIN_LINE_WIDTH=10 mil
VOLTAGE=18.5V
2V5NBVCORE_STBY_L
2V5_NBVCORE_FLT
2V5_NBVCORE_CT
2V5_NBVCORE_REF
2V5_SS
2V5_INV
2V5_FB
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=25 mil
2V5_BST_HI
NBVCORE_ITRIP
MIN_LINE_WIDTH=25 mil
NBVCORE_BST_HI
MIN_NECK_WIDTH=10 mil
2V5_NBVCORE_VREF5
MIN_NECK_WIDTH=10 mil
VOLTAGE=5V MIN_LINE_WIDTH=20 mil
VOLTAGE=18.5V MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=10 mil
PP18V5_ALL_4V85ALL
PPBATT_ALL_FUSEA_ZENER
VOLTAGE=16.3V MIN_LINE_WIDTH=10 mil MIN_NECK_WIDTH=10 mil
MIN_NECK_WIDTH=10 mil
VOLTAGE=18.5V MIN_LINE_WIDTH=10 mil
PP18V5_ALL_DCIN_R
MIN_LINE_WIDTH=15 mil
4V85ALL_ESR MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
2V5_BST_LO
NBVCORE_BOOST_ESR
MIN_LINE_WIDTH=20 mil MIN_NECK_WIDTH=10 mil
2V5_FB_RC
2V5_INV_RC
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=15 mil
3V3ALL_ESR4V85ALL_FB
MIN_NECK_WIDTH=8 mil
MIN_LINE_WIDTH=8 mil
MIN_LINE_WIDTH=8 mil MIN_NECK_WIDTH=8 mil
3V3ALL_FB
PP4V85_ALL_LDO
MIN_LINE_WIDTH=15 mil
VOLTAGE=4.85V MIN_NECK_WIDTH=10 mil
PP18V5_ALL_DCIN
_PP5V_PWRON_3V3ALL
PP4V6_ALL
VOLTAGE=4.6V MIN_LINE_WIDTH=15 mil MIN_NECK_WIDTH=10 mil
_PP3V3_ALL_LDO
PPBBATT_BOOST_OUT
PPBATT_ALL_FUSEA
_PP2V5_PWRON_REG
MIN_LINE_WIDTH=20 mil
2V5_BOOST_ESR
MIN_NECK_WIDTH=10 mil
2V5RUN_EN_L
_PP2V5_RUN_FET
_PP2V5_PWRON_2V5RUN
NBVCORE_BST_LO MIN_LINE_WIDTH=25 mil MIN_NECK_WIDTH=10 mil
2V5_HI_GATE MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=25 mil
NBVCORE_FB_RC
NBVCORE_SS
NBVCORE_FB
PP5V_PWRON
2V5_NBVCORE_PGOOD
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=15 mil
VOLTAGE=0V
GND_2V5_NBVCORE
MIN_LINE_WIDTH=25 mil
NBVCORE_SW
MIN_NECK_WIDTH=10 mil
_PPVCORE_NB_REG
NBVCORE_INV_RC
NBVCORE_INV2
25 10 7 5
5
14
6
5
5
17
8
5
14
5
5
6
14
5
Preliminary
S
D
G
VESTA MISC
1 OF 3
PVDDDVDD
AVDDL
AVDD
GND
AGND
OVDD
REGSUP1 REGSEN1 REGCTL1
REGSUP2 REGSEN2 REGCTL2
2.5V_EN
NC
DNC
DNC
DNC
NC
TDO TCK TMS TRST*
TDI
RESET*
PVINSVIN
SHDN/RT SYNC/MODE
SW VFB ITH
PGOOD
PGND SGND
G
D
S
G
D
S
GND
VOUT
VIN
NOISE
CONT
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS ALIAS ALIAS
ALIAS
ON/OFF
GND
VOUT
FB
VIN
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
NONE
DRAWING
N9/N10
Ethernet LowPwr
Signal aliases required by this page:
(Repeater mode on portables)
whenever port power is disabled.
Pulse Mode
Vout = 2.5V @ 150 mA
Port Power Switch
regulator will be in continuous mode.
3.3V Regulator
- VESTA1V2_BURST / VESTA1V2_PULSE
regulator. If both options are off the
Vout = 0.8V * (1 + (R2 / R1))
Controls operating mode of Vesta 1.2V
1.2V Regulator
<R1>
<R2>
Vout = 1.199V @ 1.2 A
Page Notes
Power aliases required by this page:
machine is running or when asleep on AC.
Ethernet portion in low power mode
- _PP12V_RUN_FW (backup PHY power)
2.5V LDO
NC NC
N5/N6
Schmitt trigger
L6/M6
Reset RC values per
To keep Vesta from being held
Broadcom recommendation
NOTE: Reset GPIO is active HIGH
in reset when system is off
(NONE)
Continuous Mode
Vout = 3.3V @ 500mA
L9/M9
Burst Mode
- _PPBUS_FW (system supply for bus power)
BOM options provided by this page:
Vesta Core / Misc
Master: Link
Enables port power when
2
1
C1210
20% 10V CERM 402
0.1uF
2
1
C1211
0.1uF
402
CERM
10V
20%
2
1
C1212
402
CERM
10V
20%
0.1uF
2
1
C1213
20% 10V CERM 402
0.1uF
2
1
C1203
0.1uF
CERM 402
10V
20%
2
1
C1202
0.1uF
402
CERM
10V
20%
2
1
C1201
0.1uF
402
CERM
20% 10V
2
1
C1200
20% 10V CERM 402
0.1uF
2
1
C1222
20% 10V
CERM
402
0.1uF
2
1
C1225
10V
20%
CERM
402
0.1uF
2
1
C1221
20% 10V
CERM
402
0.1uF
2
1
C1224
0.1uF
20% 10V
CERM
402
2
1
C1231
0.1uF
402
CERM
10V
20%
2
1
C1230
20% 10V
CERM
402
0.1uF
2
1
C1220
20% 10V
CERM
402
0.1uF
2
1
C1223
0.1uF
20% 10V
CERM
402
2
1
C1243
0.1uF
402
CERM
10V
20%
2
1
C1242
20% 10V
CERM
402
0.1uF
2
1
C1241
10V
0.1uF
402
CERM
20%
2
1
C1240
0.1uF
402
CERM
10V
20%
2
1
C1250
CERM
10V
1uF
20%
603
2
1
3
Q1250
2N7002
SM
2
1
R1250
5%
MF
402
10K
D8
E8
E10
D7
E7
H4
E2
E1
F2
F1
G4
G5
N4
A15
K1
F15
A7
A1
M13
C3
K2
J2
F14
C14
B7B2A2
J1
C15
B15
B1
E9
C9
B9
N10
N9N6N5M9M6L9L6
R12
R3
P11
P10
P5
P4
N8N7M8M7L8
L7
J12
J11
P9P8P7
P6
H12
H11
M3
U8600
OMIT
BCM5462
FBGA-200
2
1
R1251
82K
5%
MF
402
2
1
C1208
20% CERM
10uF
6.3V 805
21
L1200
FERR-EMI-600-OHM
SM
9
2
4
7
1
3
6
8
5
10
U1290
LTC3411
MSOP
CRITICAL
2
1
C1293
100pF
402
CERM
50V
5%
2
1
R1296
402
MF
4.99K
1%
2
1
C1294
402
0.0033uF
10% 50V
CERM
21
L1290
2.2uH
SM1
CRITICAL
2
1
C1292
5%
22pF
402
50V
CERM
2
1
R1297
1% MF
4.99K
2
1
R1298
1% 1/16W MF 402
10K
2
1
C1295
CERM
22uF
20%
1206
6.3V
2
1
C1291
CERM
1uF
10V 603
20%
21
R1290
10
5% MF
402
2
1
C1290
6.3V CERM
20%
10uF
805
2
1
R1295
324K
1%
2
1
R1294
5%
1M
402
MF
2
1
R1291
5%
1M
402
MF
2
1
R1293
VESTA1V2_PULSE
10K
5%
402
MF
2
1
R1292
VESTA1V2_BURST
5%
10K
402
MF
21
XW1290
SM
2
1
C1281
20%
0.01uF
402
CERM
16V
2
1
C1280
1uF
603
10V
20%
CERM
2
1
C1282
20%
10uF
805
CERM
6.3V
2
1
R1266
402
MF
330K
5%
2
1
C1265
402
CERM
16V
20%
0.01uF
2
1
R1265
5% MF
402
470K
43
DP1260
SOT-363
BAS16TW
5 2
DP1260
SOT-363
BAS16TW
61
DP1260
BAS16TW
SOT-363
21
R1261
402
MF
5%
10K
PP3V3_RUN
2
1
R1260
100K
402
5%
MF
4
5
3
Q1260
SOT-363
2N7002DW
1
2
6
Q1260
2N7002DW
SOT-363
2
1
R1262
5% MF
402
100K
2
1
R1263
402
MF
5% 1/16W
470K
51
4
2
3
U1280
CRITICAL
SOT-25A
MM1572FN
21
D1265
B340B
CRITICAL
SMB
3 2 1
4
8 7 6 5
Q1265
NDS9407
SOI
CRITICAL
21
F1265
1.5A-24V
SM
3
2
1
D1270
SDM20E40C
8
7
56
4
U1270
LM2594
SM
CRITICAL
2
1
C1270
10uF
50V
2320
N20P20%
CERM
2
1
C1271
CRITICAL
CASE-B-3528
POLY
20%
100uF
6.3V
21
L1270
CRITICAL
PLFC
100uH-1A
2
1
D1271
MBRS140T3
SM
10312
03
051-6532
TITLE=FIZZY ABBREV=DRAWING
MIN_LINE_WIDTH=20 mil
PP3V3_VESTA
VOLTAGE=3.3V MIN_NECK_WIDTH=10 mil
FWPWR_RUN
VESTA_RESET_L
PP3V3_VESTA
PP2V5_VESTA
_PPBUS_FW
FWPWR_EN_L MIN_LINE_WIDTH=8 mil MIN_NECK_WIDTH=8 mil
MIN_LINE_WIDTH=15 mil MIN_NECK_WIDTH=10 mil
VOLTAGE=33V
PPVIN_FWLM2594
VESTA1V2_ITH_RC
_PPFW_PHY
_PP1V2_ENETFW
_PP3V3_FW
MIN_LINE_WIDTH=20 mil
PPVOUT_VESTA1V2
VOLTAGE=3.3V MIN_NECK_WIDTH=10 mil
ENETFW_RESET
TP_VESTA_REGSEN2
TP_VESTA_REGSUP2
TP_VESTA_REGSEN1
TP_VESTA_REGSUP1
TP_VESTA_REGCTL1
TP_VESTA_2_5V_EN
TP_VESTA_DNC_B9
TP_VESTA_DNC_E9
PP1V2_VESTA
JTAG_VESTA_TRST_L
PP3V3_VESTA
_PP2V5_ENETFW
_PPBU_RUN_FW
PPFW_COMBINED
SMU_ACIN
_PPFW_PORT1
VESTA1V2_SW
MIN_LINE_WIDTH=20 mil MIN_NECK_WIDTH=10 mil
_PP3V3_ENET
FWPWR_ACIN
PP3V3_VESTA
MIN_NECK_WIDTH=10 mil
VOLTAGE=0V
VESTA1V2_SGND MIN_LINE_WIDTH=15 mil
_PP3V3_ENETFW
VESTA1V2_ITH
VESTA1V2_VFB
MIN_LINE_WIDTH=20 mil
FWLM2594_VOUT
MIN_NECK_WIDTH=10 mil
VOLTAGE=1.2V
PP1V2_VESTA
MIN_LINE_WIDTH=20 mil MIN_NECK_WIDTH=10 mil
_PPFW_PORT2
MIN_LINE_WIDTH=25 mil
PPFW_COMBINED
VOLTAGE=33V MIN_NECK_WIDTH=10 mil
PP3V3_VESTA
VESTA_ENET_LOWPWR
FWPWR_EN_L_DIV MIN_LINE_WIDTH=8 mil MIN_NECK_WIDTH=8 mil
PP3V3_VESTA
VOLTAGE=2.5V
PP2V5_VESTA
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=20 mil
VESTA2V5_NOISE
MIN_NECK_WIDTH=8 mil
MIN_LINE_WIDTH=8 mil
FWPWR_PWRON
VESTA1V2_MODE
VESTA1V2_RT
PP1V2_VESTA_AVDDL
MIN_LINE_WIDTH=20 mil
VOLTAGE=1.2V MIN_NECK_WIDTH=10 mil
TP_VESTA_DNC_C9
JTAG_VESTA_TMS
JTAG_VESTA_TCK
JTAG_VESTA_TDO
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=25 mil
VOLTAGE=19V
PPBUS_FW_FUSE
FWPWR_EN
PPFW_SWITCH
MIN_NECK_WIDTH=10 mil
VOLTAGE=19V MIN_LINE_WIDTH=25 mil
TP_VESTA_REGCTL2
JTAG_VESTA_TDI
LAST_MODIFIED=Mon Feb 23 19:03:46 2004
13
57
58
57
8
12
12
12
5
57
54
57
23
12
6
12
54
5
12
7
58
54
12
57
12
58
12
12
54
12
12
14
6
6
6
6
Preliminary
P9[7]
P9[6]
P9[5]
P8[7]
P8[6]
P8[5]
P3[7]
P3[6]
P3[5]
P3[4]
P2[6] P2[7]
P2[4] P2[5]
P1[4]
P1[3]
P1[2]
P1[1]
P1[0]
P0[4]
P0[0]
P0[2] P0[3]
P0[1]
P0[7]
P0[6]
P0[5]
P3[3]
P3[2]
P3[1]
P3[0]
P2[3]
P2[2]
P2[1]
P2[0]
P1[5] P1[6] P1[7]
PCNVSS RESET* XOUT
VREF
XIN
P7[7]
P7[6]
P7[5]
P7[4]
P7[3]
P7[2]
P7[1]
P7[0]
P6[7]
P6[6]
P6[5]
P6[4]
P6[3]
P6[2]
P6[1]
P6[0]
P10[0] P10[1]
P9[3]
P9[2]
P9[1]
P9[0]
P8[4]
P8[3]
P8[2]
P8[1]
P8[0]
P10[6] P10[7]
P10[2] P10[3] P10[4] P10[5]
VCC
AVSS
VSS
AVCC
SQW/ OUT
VBAT
SDA SCL
X1 X2
GND
VCC
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
NONE
Y
KI1*
NOTE: Pinout matches SMU pinout v1.51.
NOTE: All analog inputs to SMU should have a 100pF capacitor to the SMU AVSS signal (GND_SMU_AVSS). None of
Signal aliases required by this page:
- _PPVREF_SMU (SMU AVCC or 2.5V reference)
Page Notes
S = Spare
Y = Primary function N = Alternate function
CLK3
TA2out
AN00
AN02 AN03
AN01
TXD0
KI3*
S
Keep crystal subcircuit close to SMU.
Y1300’s load capacitance is 12pF
S
S
Y
Y
SDAmm
INT5*
INT4*
Y
AN20
AN06
CTS0*
IOC7
TA2in
AN04
INT2*
CE*
Y
AN27
AN23
AN21
TA3in
AN0
(BUSY)
TB0in
Sin3
Master: Link
System Management Unit
provided on another page.
reference used by monitoring
(NONE)
(NONE)
- _PP3V3_PWRON_SMU
- _PP3V3_ALL_RTC
- _PP3V3_ALL_SMU
ELECTRICAL_CONSTRAINT_SET
BOM options provided by this page:
NOTE: CPU current/voltage monitoring
Real Time Clock
NC
provided on this page. Please.
reuire pull-ups that are not.
RTS0*/
TXD1
CLK1
RTS1*
RXD0
CLK0
RXD1
AN07
AN05
SDA
TA4out
TA1in
AN24
TB1in
NMI*
INT1*
AN25
SCLmm
Y
Y
Y
Y
Y
Y
Y
Y
Sout3
AN1 AN2 AN3
KI0*
KI2*
Y
Y
IOC4
Y
SCL
this page.
TB2in
to ensure missing pull-ups are
review the latest SMU specification
Power aliases required by this page:
IOC6
TA4in
TA3out
(CPU_SENSE_I/CPU_SENSE_V) requires
Caps should connect to GND_SMU_AVSS.
those capacitors are provided on
affect other analog inputs such as AC adapter ID.
NOTE: Some primary and alternate functions
S S
TA1out
DIFFERENTIAL_PAIR
System Management Unit
NET_SPACING_TYPE
SMU Pull-ups / pull-down
Server
Y
Desktop
Portable
Y
Y
Y
Y Y Y
N N
Y Y
S
Y Y
Y Y
Y
Y Y
Y
Y
Y
N
N
Y
Y
Y
Y
Y
S
Y
S
S
Y
Consumer
S
S
S S
SS
Y Y Y YY
Y
YN
S YY
Y
Y
Y
Y
Y YSY
Y
Y Y Y
Y
Y Y Y SSN
S
Y
Y
Y
Y
Y Y
Y
Y
Y
Y
Y YYY
Y
Y
Y Y
Y Y
Y
S
Y Y Y Y S
YYYY
Y
Y
Y
Y
S
Server
N
N N
Consumer
N N N
SS
N Y
Y
S
S
Y
Y
Y
S S Y Y
N Y
Y
YY
Y
Y
Y
Y
S
Y
Y
Y
Y
Y
Y S
Y
Y
Y
Y
Y
S
Y
Y S
Y S
Y
Y
Y
Y
Y
S Y
Y
Y S
Y
Y
Y
S Y Y
Y Y Y
YY Y Y Y
Portable
Y
Y
Y
Y
Y
Y
Y
Y
Y Y
Y
Y
Y
Y
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y Y
S Y Y Y
Y
Y Y
Y
Y
S
Desktop
Entry Desktop
Entry Desktop
Y Y
Y
Y
Y
Y
Y
Y Y
Y
Y
Y Y
Y
Y
Y Y
Y
Y
Y
Y
Y
S S
N N
Y Y
Y
Y
Y Y S Y Y
Y Y
Y
Y
Y
Y
Y Y
S
INT0*
S
Y Y Y Y
Y
Y Y
Y
Y
YYY
Y
AN26
SSYY Y
S Y Y
Y
Y
Y Y
Y
Y
S Y Y
S
Y Y
Y
Y Y
S S
(see aliases below)
N N N
Y Y YYY
YYY
Y
Y
Y Y YYY
YYY
AN22
INT3*
IOC5
Y
Y
Y Y Y Y
Y
Y
S S
IOC3
IOC2
Y
Y
Tower & Server
7.4
7.2
6.0
6.2
6.1
Port
Consumer
2.5
Port
2.6
2.7
Alternate Functions
Portable
0.4
Port
0.5
0.6
1.7
1.6
1.5
7.6
circuit, but be aware that this will
SMU_VREF should be same signal or
100K/10uF RC filter at SMU pins.
21
Y1300
8X4.5MM-SM
10.0000M
CRITICAL
10 12
11
77
13
9
79
80
1
2
3
4
5
7
8
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
40
41
42
43
32
33
34
35
36
37
38
39
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
68
69
70
71
72
73
74
76
59
60
61
62
63
64
65
66
67
6
75
78
U1300
QFP-80
M30280F8
OMIT
2
1
8
3
7
5
6
4
U1301
MSOP
DS1338
PP3V3_PWRON
PP3V3_RUN
PP2V5_PWRON
21
R1399
5%
MF
402
NO_SMU_I2C_D
0
3
1
D1310
1N914
2
1
C1325
1uF
CERM
6.3V
10%
402
2
1
R1325
10K
5% MF
402
2
1
R1322
100K
5% 1/16W MF 402
2
1
C1310
20%
0.22uF
402
6.3V CERM
2
1
C1304
50V
5%
12pF
402
CERM
2
1
C1305
50V
5%
12pF
402
CERM
2
1
R1317
402
MF
5%
0
21
R1316
10M
5% MF
402
NO STUFF
2
1
R1327
402
5%
10K
21
R1312
100K
5%
MF
402
21
R1311
402
MF
5%
100K
21
R1313
402
MF
5%
100K
21
R1310
100K
5%
MF
402
21
R1302
402
MF
5%
10K
21
R1300
5%
MF
402
10K
12
R1304
5%
MF
10K
402
2
1
C1309
10V
20% CERM
0.1uF
402
2
1
C1308
10V
20%
0.1uF
CERM
402
2
1
C1302
10V
20%
0.1uF
CERM
402
2
1
C1301
10V
20%
0.1uF
CERM
402
2
1
C1300
6.3V
10uF
20%
CERM
805
2
1
C1303
402
CERM
1uF
10%
6.3V
21
R1315
402
MF
5%
4.7
21
XW1300
SM
4
1
Y1301
32.768K
SM-1
CRITICAL
051-6532
10313
03
FAN_PWM8
SYS_KBDLED
SYS_DOOR_AJAR_L
SYS_LID_OPEN
SYS_DRIVE_BAY_INT_L
SMU_BATT_DET_L
SYS_POWERFAIL_L
SMU_ACIN
FAN_RPM5
ALS_GAIN_BOOST
FAN_RPM4 ALS1_OUT
FAN_RPM3 ALS0_OUT
FAN_TACH5
SYS_LED_BLUE
FAN_TACH4
SYS_LED_GREEN
FAN_TACH3
SYS_LED_RED
I2C_SMU_CPU_SDA_IN
FAN_PWM6
I2C_SMU_CPU_SCL_IN
FAN_PWM7
CPU_VID<1>
FAN_TACH7
CPU_VID<2>
FAN_TACH8
CPU_VID<0>
FAN_TACH6
SYS_SLOT_PWR
TP_SMU_SPARE_P10_0
SYS_RESET_BUTTON_L
SB_SUSPENDACK_L
NB_SUSPENDACK_L
SMU_WARM_RESET_L
SMU_PWRSEQ_P9_6
SB_STOPXTALS_L
I2C_SMU_CPU_SDA_OUT
FAN_PWM8
I2C_SMU_B_SCL
CPU_VID<3>
CPU_VID<1>
CPU_VID<0>
CPU_VID<2>
I2C_SMU_A_SDA_IN I2C_SMU_A_SDA_OUT
FAN_TACH4
FAN_RPM3
15 MIL SPACING
SMU_CLK10M_XOUT_R
SMU_PWRSEQ_P9_5
CPU_TEMP
SYS_COLD_RESET_L
SYS_POWER_BUTTON_L
SMU_SUSPENDREQ_L
SB_TO_SMU_INT_L
CLOCK_RESET_L
SMU_SLEEP
SYS_SLEWING_L
I2C_SMU_CPU_SCL_OUT
CPU_HRESET_L
FAN_RPM1
SYS_LED
I2C_SMU_CPU_SDA_IN
FAN_RPM2
SYS_PME_L TP_SMU_SPARE_P8_3
I2C_SMU_CPU_SCL_IN
FAN_RPM0
I2C_SMU_B_SDA
SMU_BOOT_TXD
SMU_TO_SB_INT_L
FAN_TACH5
FAN_TACH3
FAN_TACH2
SYS_DOOR_AJAR_L
FAN_TACH0
I2C_SMU_E_SCL
I2C_SMU_E_SDA
SMU_PWRSEQ_P1_3 SMU_PWRSEQ_P1_4
SMU_ONEWIRE
FAN_RPM5
I2C_SMU_D_SDA
CPU_SENSE_I CPU_SENSE_V
SYS_DRIVE_BAY_INT_L
SMU_PWRSEQ_P1_0 SMU_PWRSEQ_P1_1
CPU_BYPASS_L
FAN_RPM4
SMU_PWRSEQ_P1_2
SMU_CHARGE_BATT
I2C_SMU_D_SCL
I2C_SMU_A_SCL_IN I2C_SMU_A_SCL_OUT
15 MIL SPACING
SMU_CLK10M_XTAL
SMU_CLK10M_XIN
RTC_CLK32K_X2
15 MIL SPACING
I2C_RTC_SDA
I2C_RTC_SCL
15 MIL SPACING
RTC_CLK32K_XTAL
RTC_CLK32K_X1
SMU_CLK10M_XOUT
15 MIL SPACING
FAN_TACH1
SYS_OVERTEMP_L
SYS_POWERFAIL_L
_PPVREF_SMU
SMU_BOOT_CNVSS
_PP3V3_ALL_SMU
SMU_RESET_L
SMU_CLK10M_XOUT
SMU_CLK10M_XOUT_R SMU_CLK10M_XIN
SMU_BOOT_RXD
SYS_SLEWING_L
SMU_SUSPENDREQ_L
SYS_COLD_RESET_L
SMU_SLEEP
SYS_POWERUP_L
_PP3V3_ALL_SMU
SYS_POWER_BUTTON_L
SYS_PME_L
GND_SMU_AVSS
SMU_BOOT_CE
MAKE_BASE=TRUE
SYS_POWERUP_L
CPU_VID<5>
SMU_BOOT_SCLK
SMU_BOOT_BUSY
CPU_VID<4>
_PP3V3_ALL_SMU
VOLTAGE=3.3V MIN_LINE_WIDTH=15 mil MIN_NECK_WIDTH=10 mil
PP3V3_ALL_SMU_AVCC
VOLTAGE=0V MIN_LINE_WIDTH=15 mil MIN_NECK_WIDTH=10 mil
GND_SMU_AVSS
_PP3V3_ALL_SMU
_PP3V3_ALL_RTC
RTC_CLK32K_X1
RTC_CLK32K_X2
42
25
42
17
31
23
18
31
18
17
32
18
32
18
12
19
51
16
23
25
48
17
16
19
25
23
51
14
16
16
48
19
14
16
19
16
8
17
17
13
13
13
18
18
31
31
31
16
22
18
31
31
31
13
22
13
22
13
23
28
15
18
23
18
15
18
16
13
13
15
18
18
28
15
15
16
13
16
16
23
22
22
13
13
13
13
23
17
13
31
13
17
13
13 19
13 17
13
7
13
7
13
6
13 19
13
6
5
5
5
13
13
13
13
13
6
23
22
5
14
23
18
13
6
31
13
13
13
18
18
5
13
13
14
32
13
6
13
23
25
5
13
18
27
6
19
13
5
13
13
6
6
6
23
5
5
5
13
6
6
6
14
14
17
13
32
32
13
14
14
27
13
14
8
5
18
18
13
13
18
18
13
13
6
6
13
5
6
5
6
13
13
13
6
13
13
13
5
6
5
6
13
13
16
6
6
16
16
6
5
13
5
5
13
13
Preliminary
ALIAS
G
D
S
ALIAS
G
D
S
ALIAS
ALIAS ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
G
D
S
G
D
S
ALIAS
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
NONE
TPS5120 needs a pull-up stronger than 82.5K
ACTIVE-HIGH, OUTPUT, PUSH-PULL
ACTIVE-HIGH, OUTPUT, PUSH-PULL
ACTIVE-LOW, OUTPUT, PUSH-PULL
ACTIVE-HIGH, OUTPUT/INPUT, OPEN-COLLECTOR
100K pull-up to 3.3V_ALL on pg 13
ACTIVE-LOW, OUTPUT, PUSH-PULL
ACTIVE-LOW, OUTPUT, PUSH-PULL
POWER-UP
ACTIVE-HIGH, OUTPUT/INPUT, OPEN-COLLECTOR
SHUT-DOWN
SLEEP
WAKE
Power Sequencing
Used to see if last rail is up
ANALOG INPUT, SENSE > 1.7V
21
R1411
0
402
MF
5%
21
R1420
402
MF
5%
100K
21
R1421
100K
402
MF
5%
21
R1422
5%
MF
402
100K
21
R1430
5% MF
402
0
2
1
R1435
5%
MF
100K
402
4
5
3
Q1435
2N7002DW
SOT-363
PP5V_RUN
21
R1436
5%
MF
402
100K
21
R1437
402
MF
100K
5%
21
R1440
5% MF
100K
402
21
R1441
5% MF
402
100K
21
R1450
0
MF
402
5%
21
R1451
0
5% MF
402
PP5V_RUN
2
1
R1465
5% 1/16W MF 402
100K
1
2
6
Q1435
2N7002DW
SOT-363
21
R1466
5%
MF
402
100K
21
R1467
5%
MF
402
0
2
1
R1449
MF
0
5%
402
2
1
R1459
5%
0
402
MF
21
XW1470
SM
21
R1469
402
MF
5%
0
2
1
R1458
5% MF
100K
2
1
R1448
100K
5% 1/16W MF 402
PP3V3_RUN
PP3V3_RUN
1
2
R1412
100K
5% MF
402
2
1
R1401
5% MF
402
68K
PP3V3_ALL
1
2
6
Q1400
SOT-363
2N7002DW
4
5
3
Q1400
SOT-363
2N7002DW
2
1
R1429
MF
100K
5%
402
PP5V_PWRON
21
R1402
5%
0
MF
402
21
R1403
0
5% MF
402
21
R1400
402
MF
5%
0
21
R1410
5% MF
402
0
14 103
03
051-6532
SYS_POWERUP_L_R
5VRUNHD_EN_L
SYS_POWERUP_L
GPUVCORE_SHDN_L
CPU_AVDD_EN
GPUVDD15_EN
3V3RUN_EN_L
1V5RUN_EN
SMU_PWRSEQ_P1_3
SMU_PWRSEQ_P9_6
MAKE_BASE=TRUE
SYS_PWRSEQ_7
PP1V8_GPU_PVDD
GPUVCORE_PGOOD
CPUVCORE_SHDN_L
1V8RUN_SHDN_L
GPUPVDD_EN
VCORE_SWITCHING
1V2RUN_EN
1V8RUN_PGOOD
2V5RUN_EN_L
3V3_STBY_L
2V5NBVCORE_STBY_L
SMU_PWRSEQ_P1_4
2V5_NBVCORE_PGOOD
SMU_PWRSEQ_P9_5
SYS_PWRSEQ_6_L
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SYS_PWRSEQ_6_LS5
MAKE_BASE=TRUE
SYS_PWRSEQ_5
5V3VPWRON_PGOOD
5VRUN_EN_L
MAKE_BASE=TRUE
SYS_PWRSEQ_1
SMU_PWRSEQ_P1_2
MAKE_BASE=TRUE
SYS_PWRSEQ_4
PWRON_REGS_PGOOD
MAKE_BASE=TRUE
SYS_PWRSEQ_3_LS5
SYS_PWRSEQ_3_L
MAKE_BASE=TRUE
SMU_PWRSEQ_P1_0
SYS_PWRSEQ_2_L
SYS_PWRSEQ_2
MAKE_BASE=TRUE
SMU_PWRSEQ_P1_1
SYS_POWERUP
FWPWR_PWRON
5V_STBY_L
13
10
6
38
29
39
10
9
13
13 40
38
31
9
40
31
9
9
11
10
11
13
11
13
10
10
13
13
13
6
12
10
Preliminary
GND
DXN3
DXN4
DXP4
DXP3
DXP1 DXN1
DXP2 DXN2
ADD0 ADD1
ALERT*
STBY*
SMBDATA
SMBCLK
VCC
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
NONE
ELECTRICAL_CONSTRAINT_SET
Fan 1
Fan 2
Thermal Sensor / Fans
(NONE)
- _PP5V_PWRON_FAN
thermal sensors for each of the available remote sensor locations.
- THERM_x / THERM_xB
BOM options provided by this page:
Signal aliases required by this page:
- _PP3V3_PWRON_THERM
Page Notes
Power aliases required by this page:
DIFFERENTIAL_PAIR
(PWM)
Remote 3
Remote 3 (Backup)
Remote 2 (Backup)
(GND)
(TACH)
(PWR)
GPU Thermal Diode
Remote 4
Addr=0x30(Wr)/0x31(Rd)
(GND)
(PWM)
Remote 1 (Backup)
minimizing stubs.
to two different sensors. These
Sensor Selection
Remote 1
Place each cap close to associated transistor
Remote Temperature Sensors
Selects between primary and backup
NET_SPACING_TYPE
resistors should be close to MAX1668,
First 3 MAX1668 inputs can connect
MAX1989 Thermal Sensor
(TACH)
(PWR)
Remote 2
Place close to CPU_VCORE
Place close to 5V/3.3V
Place close to U3Lite
Place close to Shasta/GPU_Vcore
Place close to bottom RAM
Place close to CPU
2
3
1
Q1510
THERM_1
2N3904
SM
2
1
C1510
20% 50V CERM 402
THERM_1
0.001uF
2
1
C1520
402
0.001uF
CERM
50V
20%
THERM_2
2
3
1
Q1520
SM
2N3904
THERM_2
2
1
C1515
CERM
50V
20%
402
0.001uF
THERM_1B
2
3
1
Q1515
SM
2N3904
THERM_1B
2
1
C1525
402
0.001uF
CERM
50V
20%
THERM_2B
2
3
1
Q1525
SM
2N3904
THERM_2B
21
R1510
THERM_1
0
402
MF
5%
21
R1515
THERM_1B
5%
MF
402
0
21
R1511
5% MF
402
0
THERM_1
21
R1516
402
5%
0
MF
THERM_1B
21
R1520
5%
MF
402
0
THERM_2
21
R1525
0
402
MF
5%
THERM_2B
21
R1526
5%
MF
402
0
THERM_2B
21
R1521
THERM_2
0
402
MF
5%
2
1
R1592
10K
402
MF
5%
2
1
C1592
20%
10V CERM 1206
4.7uF
9
15
13
14
16
7
5
3
1
8
6
4
2
12
10
11
U1500
MAX1668
QSOP
CRITICAL
2
1
C1505
NO STUFF
20% 50V CERM 402
0.001uF
2
1
C1507
0.001uF
402
CERM
50V
20%
NO STUFF
2
1
C1506
0.001uF
402
CERM
50V
20%
NO STUFF
2
1
C1508
NO STUFF
20% 50V
CERM
402
0.001uF
2
1
C1500
402
0.1uF
CERM
10V
20%
21
R1500
402
MF
5%
200
2
1
C1501
50V
20% CERM
402
0.001uF
NO STUFF
2
1
C1502
0.001uF
402
CERM
50V
20%
NO STUFF
2
1
C1503
NO STUFF
0.001uF
402
CERM
50V
20%
2
1
C1504
0.001uF
402
CERM
50V
20%
NO STUFF
21
R1535
THERM_3B
5%
MF
402
0
21
R1536
THERM_3B
0
402
MF
5%
21
R1530
THERM_3
0
402
MF
5%
21
R1531
THERM_3
5%
MF
402
0
2
1
C1535
THERM_3B
20% 50V CERM
0.001uF
402
2
3
1
Q1535
SM
THERM_3B
2N3904
2
1
C1530
402
0.001uF
CERM
50V
20%
THERM_3
2
3
1
Q1530
SM
2N3904
THERM_3
2
1
C1540
20% 50V CERM
0.001uF
402
4
3
2
1
6
5
J1592
SM-2MT
CRITICAL
4
3
2
1
6
5
J1591
SM-2MT
CRITICAL
2
1
R1591
5%
MF
10K
402
2
1
C1591
20%
10V CERM 1206
4.7uF
03
051-6532
15 103
THERM_1_N
THERM_2_N
_PP3V3_RUN_FAN
_PP3V3_RUN_FAN
_PP5V_PWRON_FAN
_PP5V_PWRON_FAN
PP3V3_PWRON_MAX1989
MIN_LINE_WIDTH=10 mil MIN_NECK_WIDTH=10 mil
VOLTAGE=3.3V
MAX1989_D4
MAX1989_D4_N
THERM
MAX1989_D1
MAX1989_D1_P
THERM
MAX1989_D1
MAX1989_D1_N
THERM
MAX1989_D2
MAX1989_D2_P
THERM
THERM
THERM_3_P
THERM_3
THERM
THERM_1
THERM_1_N
THERM
THERM_1_P
THERM_1
MAX1989_D4
MAX1989_D4_P
THERM
MAX1989_D3
MAX1989_D3_N
THERM
THERM_1_P
THERM
THERM_2_N
THERM_2
FAN_TACH0
I2C_MAX1989_SDA
MAX1989_D4_N
MAKE_BASE=TRUE
GPU_THMDIODE_P
MAKE_BASE=TRUE
GPU_THMDIODE_N
MAX1989_D4_N
MAX1989_D4_P
FAN_TACH1
FAN_RPM0
FAN_RPM1
THERM_1B_P
THERM_1B_N
THERM_2B_N
THERM_3B_P
THERM_3B_N
THERM_2_P
THERM_3_P
THERM_3_N
THERM_2B_P
MAX1989_D1_P
MAX1989_D1_N
MAX1989_D2_P
MAX1989_D2_N
MAX1989_D3_P
MAX1989_D3_N
THERM_1B_P
THERM_1_P
THERM_1_N
THERM_2_P
THERM_2B_P
THERM_2_N
THERM_3B_P
THERM_3_P
THERM_3_N
THERM_3B_N
MAX1989_D2
MAX1989_D2_N
THERM
THERM
THERM_2_P
THERM_2
THERM
THERM_3B_P
THERM_3B
THERM
THERM_2B
THERM_2B_N
THERM
THERM_2B_P
THERM_2B
THERM
THERM_1B_N
THERM_1B
THERM
THERM_3_N
THERM_3
_PP3V3_PWRON_THERM
MAX1989_D2_P
MAX1989_D3_P
SYS_OVERTEMP_L
MAX1989_D4_P
MAX1989_D1_P
I2C_MAX1989_SCL
THERM_2B_N
THERM_1B_N
MAX1989_D3_N
MAX1989_D2_N
MAX1989_D1_N
THERM
THERM_1B_P
THERM_1B
THERM
THERM_3B_N
THERM_3B
MAX1989_D3
MAX1989_D3_P
THERM
25 23 17
15
15
15
15
13
13
13
13
13
15
15
5
5
5
5
15
15
15
15
15
15
15
15
15
15
15
6
18
15
37
37 15
15
6
6
6
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
5
15
15
6
15
15
18
15
15
15
15
15
15
15
15
Preliminary
S
D
G
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
NONE
Debug LEDs
Debug "Buttons"
"RESET"
Add silkscreen:
"POWER"
(GPIO#)
(TRXC)
516S0143
(RXD)
(SCCA)
(DTR#)
(RTS#)
(TXD#)
allow serial debug flex to use either connector
SCC same pins have pinout as modem connector to
SMU Download / Serial Debug Connector
INTERNAL I/O CONNECTORS
21
R1690
NO STUFF
5%
MF
0
603
21
R1691
603
5% MF
0
NO STUFF
9
8 7
6 5
4 3
2
16 15
14 13
12 11
10
1
J1699
DEVELOPMENT
QT510166-L010
F-ST-SM1
CRITICAL
2
1
R3054
DEVELOPMENT
5%
180
2
1
D3002
SM
RED
DEVELOPMENT
2
1
3
Q3004
DEVELOPMENT
Q3004_D
SM
2N7002
2
1
R3052
DEVELOPMENT
5%
402
MF
180
2
3
1
Q3003
DEVELOPMENT
SM
Q3003_B
2N3904
2
3
1
Q3002
SM
DEVELOPMENT
2N3906
2
1
R3048
DEVELOPMENT
5%
180
21
R3050
5%
DEVELOPMENT
402
MF
180
2
1
D3001
GREEN
SM
DEVELOPMENT
2
1
R3070
DEVELOPMENT
5%
402
MF
180
2
1
R3046
DEVELOPMENT
5%
1K
2
3
1
Q3001
DEVELOPMENT
SM
2N3904
21
R3044
5%
DEVELOPMENT
402
MF
180
03
051-6532
10316
_PP5V_PWRON_SERIAL
_PP3V3_ALL_SMU
I2S1_SB_TO_DEV_DTO I2S1_MCLK
I2S1_RESET_L SMU_BOOT_TXD SMU_BOOT_RXD SMU_BOOT_BUSY
I2S1_SYNC I2S1_DEV_TO_SB_DTI I2S1_BITCLK SMU_RESET_L SMU_BOOT_CE SMU_BOOT_SCLK SMU_BOOT_CNVSS
SYS_POWER_BUTTON_L
SYS_RESET_BUTTON_L
D3002_1
PP5V_RUN_CPU
Q3004_G
Q3002_E
CHKSTOP_L
D3001_1
PP5V_RUN_CPU
Q3002_B
Q3001_C
Q3001_BPLLLOCK
42
18
60
60
60
60
60
60
19
17
29
29
13
23
23
23
13
13
23
23
23
13
13
13
13
16
16
5 5
6
6
6
6
6
13
6
6
6
6
13
13
6
6
6
5
27
5
27
Preliminary
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
NONE
series resistors to protect SMU pins
overtemp may need pull-up resistor
USB Trackpad Connector
For EMI around ENET magnetic
Speaker Clips
for EMI testing only
Graphic Heat Sink
CPU Heat Sink
Right I/O area
PPBUS Hold-Up Caps
BlueTooth / Left USB Flex Connector
Place cap close to SMU
battery circuit. _PPBUSA_BBATT is an output only.
NC
NC
Backup Battery / Right USB Flex Connector
_PPBUSB_BBATT is both an input and an output for backup
Q51 Specific connectors
Place cap close to SMU
21
D790
SM
MBR0530
9
8
7
6
5
4
3
2
14
13
12
11
10
1
16
15
J1600
CRITICAL
F-RT-SM
54550-1490
2
1
C862
CRITICAL
ELEC
25V
20%
33uF
SM1
2
1
C861
CRITICAL
SM1
33uF
20% 25V ELEC
2
1
C865
CRITICAL
ELEC
25V
20%
33uF
SM1
2
1
C864
CRITICAL
ELEC
25V
20%
33uF
SM1
2
1
C860
CRITICAL
ELEC
25V
20%
33uF
SM1
2
1
C863
CRITICAL
ELEC
25V
20%
33uF
SM1
1
ZT511
146R126
1
ZT510
146R126
1
BS510
STDOFF-217ODX150IDX35H-TH
1
ZT503
255R158
1
ZT504
255R158
1
ZT502
255R158
1
ZT500
255R158
1
ZT501
255R158
1
ZT505
255R158
9
8
7
6
5
4
3
2
14
13
12
11
10
1
16
15
J790
54550-1490
CRITICAL
F-RT-SM
1
SP9900
OMIT
SPKR_CLIP_P84
1
SP503
SPKR_CLIP_P84
1
SP504
SPKR_CLIP_P84
1
SP505
SPKR_CLIP_P84
1
SP500
SPKR_CLIP_P84
1
SP501
SPKR_CLIP_P84
1
SP502
SPKR_CLIP_P84
1
ZT9901
HOLE-VIA-20R10
OMIT
2
1
C1610
CERM 402
5% 50V
100pF
1
ZT9903
HOLE-VIA-20R10
OMIT
1
ZT9900
HOLE-VIA-20R10
OMIT
1
ZT9902
OMIT
HOLE-VIA-20R10
2
1
R2132
100K
402
5% MF
9
8
7
6
5
4
3
2
14
13
12
11
10
1
16
15
J2130
CRITICAL
F-RT-SM
54550-1490
2
1
R2131
5% 1/16W MF 402
15K
2
1
R2130
5% MF
402
15K
21
R1620
1K
MF
5%
402
21
R1610
MF
5%
402
0
2
1
R1621
3.32K
1% 1/16W MF 402
2
1
R1611
1K
5% 1/16W MF 402
PP3V3_ALL
2
1
C1605
CERM
50V
5%
402
100pF
2
1
R1601
5% 1/16W
15K
MF 402
2
1
R1600
5%
MF
402
15K
18
103
03051-6532
ALS0_OUT
GND_SMU_AVSS
ALS0_OUT_R
SMU_ONEWIRE
MAKE_BASE=TRUE
GND_SMU_AVSS
_PPBUSA_BBATT
PPBBATT_BOOST_OUT
MIN_LINE_WIDTH=20 mil MIN_NECK_WIDTH=10 mil
VOLTAGE=6.3V
RTUSB_PWREN
USB2_RT_N
RTUSB_OVERCURRENT
USB2_RT_P
_PP5V_PWRON_RTUSB _PPBUSB_BBATT
USB_BT_N
USB_BT_P
_PP5V_PWRON_LTUSB
ALS_GAIN_BOOST
MAKE_BASE=TRUE
LTUSB_OVERCURRENT
USB2_LT_P
LTUSB_PWREN
USB2_LT_N
_PP3V3_PWRON_BT
_PPBUS_ALL_A
_PPBUS_ALL_B
GND_CHASSIS_DVI
GND_CHASSIS_IO
GND_CHASSIS_INVERTER
_PP3V3_ALL_HALLEFFECT
USB_TPAD_N
SYS_LID_OPEN
MAKE_BASE=TRUE
_PP5V_PWRON_TPAD
PP3V3_PWRON
USB_TPAD_P
KBDLED_RETURN KBDLED_ANODE
SYS_OVERTEMP_L
SYS_POWER_BUTTON_L
I2C_DS1775_SDA
I2C_DS1775_SCL
ADAPTER_ID
25
32
32
23
42
19
19
19
42
15
16
13
17
17
13
8
8
6
25
19
19
13
13
6
13
13
13
5
11
5
5
5
5
5
5
5
5
5
6
5
5
5
5
5
5
5
5
5 5
5
5
13
5
6
5
6
6
6
6
18
18
6
Preliminary
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIASALIAS
ALIAS
ALIAS
ALIAS
LM339A
V+
GND
LM339A
V+
GND
LM339A
V+
GND
LM339A
V+
GND
G
D
S
G
D
S
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
NONE
(MASTER)
U1300
SMU
U3
(MASTER)
NorthBridge I2C "B" Bus
I2C CONNECTIONS
I2C "A" Bus
U3Lite
U3
(MASTER)
U1300
SMU
(Write: 0x?? Read: 0x??)
U2900
CPU
Power aliases required by this page: (NONE)
(NONE)
(NONE)
BOM options provided by this page:
(I2C_CPU_A_SDA)
(I2C_CPU_A_SCL)
(Write: 0x?? Read: 0x??)
ELECTRICAL_CONSTRAINT_SET
DIFFERENTIAL_PAIR
NET_SPACING_TYPE
(Write: 0xAC Read: 0xAD)
(Address set on modem flex)
MicroDash
Audio Board
(Write: 0x?? Read: 0x??)
J9500
J9400
SouthBridge I2C Bus
(MASTER)
U2300
Shasta
RTC
U1301
J790
U800
(Write: 0x?? Read: 0x??)
(Write: 0x?? Read: 0x??)
(Write: 0x?? Read: 0x??)
Battery Charger
Battery Conn
I2C "E" Bus
SMU
U1300
(MASTER)
Pulsar
U2600
On Trackpad Flex
DS1775
(Write: 0x?? Read: 0x??)
(Write: 0x30 Read: 0x31)
(Write: 0x?? Read: 0x??)
I2C "B" Bus
SMU
(MASTER)
U1300
U3Lite
(Write: 0xA0 / 0xA2,
J4010 / J4020
DIMMs
Read: 0xA1 / 0xA3)
NorthBridge I2C "C" Bus
U3
(MASTER)
U3Lite
MAX1989
U1500
Signal aliases required by this page:
Page Notes
U3 Lite I2C inversion
2
1
R2029
5% 1/16W MF 402
2K
PP2V5_PWRON
2
1
R2028
402
MF
5%
2K
2
1
R2051
7.15K
1% MF
402
2
1
R2050
1%
7.15K
MF
402
2
1
R2019
5% 1/16W MF 402
200
2
1
R2018
MF
402
5%
200
2
1
R2015
5%
MF
402
4.7K
PP5V_PWRON
2
1
C2015
20% 10V
CERM
402
0.1uF
3
13
11
10
12
U2015
SOI
CRITICAL
PP3V3_PWRON
2
1
R2011
402
MF
5%
2K
2
1
R2010
5%
MF
402
2K
2
1
C2016
CERM
10V
20%
402
0.1uF
2
1
R2016
MF
1%
576
402
3
14
9
8
12
U2015
SOI
CRITICAL
PP3V3_PWRON
2
1
R2081
MF
5%
2K
2
1
R2080
MF
402
5%
2K
3
1
7
6
12
U2015
SOI
CRITICAL
2
1
R2083
MF
5%
1K
402
2
1
R2082
MF
1K
5%
402
3
2
5
4
12
U2015
SOI
CRITICAL
5
6
7
8
4
3
2
1
RP2085
0K
5%
SM1
SMU_CPU_JTAG
5
6
7
8
4
3
2
1
RP2080
SM1
5%
0K
SMU_CPU_I2C
4
5
3
Q2000
SOT-363
2N7002DW
1
2
6
Q2000
2N7002DW
SOT-363
PP3V3_RUN
2
1
R2041
1K
402
MF
5%
2
1
R2040
5%
1K
MF
402
72
RP2060
4.7K
SM1
5%
81
RP2060
5%
SM1
4.7K
54
RP2060
5%
4.7K
SM1
63
RP2060
4.7K
SM1
5%
PP2V5_PWRON
2
1
R2030
2K
5%
MF
402
2
1
R2031
2K
402
5% MF
PP3V3_PWRON
2
1
R2021
5% 1/16W MF 402
1K
2
1
R2020
1K
402
MF
5%
03
20 103
051-6532
I2C_0V546_REF
MAKE_BASE=TRUE
I2C_SMU_A_SDA_IN
SMU_CPU_JTAG_OR_I2C
MAKE_BASE=TRUE
I2C_SMU_CPU_SDA_OUT
I2C_SMU_A_SDA_OUT MAKE_BASE=TRUE
I2C_SMU_A_SCL_OUT MAKE_BASE=TRUE
I2C_SMU_A_SDA_OUT_L
I2C_SMU_A_SCL_OUT_L
I2C_NB_C
I2C
I2C_NB_C
I2C_NB_C_SDA
I2C_SB
I2C
I2C_SB
I2C_SB_SCL
I2C
I2C_SMU_A_OUTI2C_SMU_A_OUT
I2C_SMU_A_SDA_OUT
I2C
I2C_NB_CI2C_NB_C
I2C_NB_C_SCL
I2C_DIMM_SDA
I2C_DIMM_SCL
MAKE_BASE=TRUE
I2C_NB_C_SDA
MAKE_BASE=TRUE
I2C_NB_C_SCL
I2C_DS1775_SDA
I2C_DS1775_SCL
I2C_MAX1989_SDA
I2C_MAX1989_SCL
I2C_CLOCK_SDA
I2C_CLOCK_SCL
I2C_CHGR_SCL
I2C_CHGR_SDA
I2C_BATT_SDA
I2C_BATT_SCL
I2C_RTC_SDA
I2C_RTC_SCL
MAKE_BASE=TRUE
I2C_SMU_B_SDA
MAKE_BASE=TRUE
I2C_SMU_B_SCL
MAKE_BASE=TRUE
I2C_SMU_E_SCL
MAKE_BASE=TRUE
I2C_SMU_E_SDA
_PP3V3_ALL_SMU
I2C_AUDIO_SDA
I2C_AUDIO_SCL
I2C_MODEM_SDA
I2C_MODEM_SCL
MAKE_BASE=TRUE
I2C_SB_SDA
MAKE_BASE=TRUE
I2C_SB_SCL
I2C
I2C_SMU_CPU_OUTI2C_SMU_CPU_OUT
I2C_SMU_CPU_SCL_OUT
I2C
SMU_CPU_JTAG_OR_I2C
I2C
I2C_CPU_A_SDA
I2C
I2C_SMU_BI2C_SMU_B
I2C_SMU_B_SDA
I2C
I2C_SMU_BI2C_SMU_B
I2C_SMU_B_SCL
I2C
I2C_CPU_A_SDA_TO_SMU
I2C
I2C_CPU_A_SCL
I2C
I2C_SMU_A_INI2C_SMU_A_IN
I2C_SMU_A_SDA_IN
I2C
I2C_SMU_A_INI2C_SMU_A_IN
I2C_SMU_A_SCL_IN
I2C
I2C_SMU_A_OUTI2C_SMU_A_OUT
I2C_SMU_A_SCL_OUT
I2C
I2C_SMU_CPU_OUTI2C_SMU_CPU_OUT
I2C_SMU_CPU_SDA_OUT
I2C
I2C_NB_BI2C_NB_B
I2C_NB_B_SDA
I2C
I2C_SMU_CPU_INI2C_SMU_CPU_IN
I2C_SMU_CPU_SCL_IN
I2C
I2C_SMU_CPU_INI2C_SMU_CPU_IN
I2C_SMU_CPU_SDA_IN
I2C
I2C_NB_BI2C_NB_B
I2C_NB_B_SCL
MAKE_BASE=TRUE
I2C_SMU_A_SCL_IN
I2C_SMU_A_SCL_OUT_L
PP1V2_EI_NB
I2C_CPU_A_SDA
JTAG_CPU_TDO
PP1V2_EI_CPU
I2C_NB_A_SCL
I2C_NB_A_SDA
JTAG_SB_TCK
JTAG_SB_TDI
JTAG_SB_TRST_L
JTAG_SB_TMS
_PP3V3_PWRON_SB
MAKE_BASE=TRUE
I2C_NB_B_SCL
MAKE_BASE=TRUE
I2C_NB_B_SDA
I2C_SMU_A_SDA_OUT_L
JTAG_CPU_TDI
JTAG_CPU_TMS
JTAG_CPU_TCK
I2C_SMU_CPU_SCL_IN
MAKE_BASE=TRUE
I2C
I2C_SBI2C_SB
I2C_SB_SDA
I2C_CPU_A_SCL
I2C_CPU_A_SDA_TO_SMU
MAKE_BASE=TRUE
I2C_SMU_CPU_SCL_OUT
MAKE_BASE=TRUE
I2C_SMU_CPU_SDA_IN
29
45
23
18
18
16
23
23
18
18
28
28
23
28
28
28
23
18
18
18
18
22
18
18
22
22
22
13
13 13
13
13
18
18
18
27
13
13
27
18
18
18
18
22
18
18
22
18
26
27
27
27
23
23
23
23
21
22
22
27
27
27
18
18
27
18
18
13
18
13
13
13
18
18
18
6
13
18
35
35
18
18
17
17
15
15
25
25
8
8
7
7
13
13
6
6 6
6
5
61
61
60
60
6
6
13
18
18
6
6
18
18
13
13
13
13
18
13
13
18
13
18
5
18
6
5
22
22
6
6
6
6
5
18
18
18
6
6
6
13
6
18
18
13
13
Preliminary
V+
V-
G
D
S
PGND
EP
GND
COMP
CTRL
CS
OUT
LX
IN
G
D
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
NONE
Ambient Light Sensor #1
SMU ALS/LEDs
Keyboard LED Driver
Sleep LED Circuit
SMU / System Reset Button
Keep inductor close to cap
Place R2115,R2116 and C2115 close to SMU
2
6
5
1
4
3
U2110
CRITICAL
SOT23-6
MAX4236EUTT
2
1
C2110
20% CERM
402
0.1uF
10V
2
1
R2110
1K
402
1% MF
2
1
R2111
5% 1/16W MF 402
5.1M
2
1
C2111
CERM
402
16V
20%
0.01uF
2
1
RD2111
CRITICAL
TH
BS520
2
1
R2112
120K
402
MF
5%
2
1
C2112
0.22uF
20%
6.3V 402
X5R
2
1
R2113
1K
402
1% MF
2
1
R2114
15K
402
1% MF
21
R2115
1K
402
1% MF
2
1
R2199
100
402
MF
5%
2
1
L2199
SM-1
400-OHM-EMI
2
1
C2199
402
CERM
50V
10%
470pF
2
3
1
Q2199
SM
2N3906
2
1
R2193
2.2K
402
MF
5%
2
1
R2192
402
5% MF
4.7K
4
5
3
Q2191
SOT-363
2N7002DW
2
1
R2191
5%
MF
402
100K
7
1
82
69
3
4
5
U2150
CRITICAL
QFN
MAX1561
21
L2150
CRITICAL
22uH
2
1
C2151
20% 10V
CERM
402
0.1uF
2
1
C2152
0.22uF
10% CERM
50V 1210
2
1
C2150
6.3V 603
2.2uF
20%
2
1
D2150
SM
MBR0540
2
1
R2150
8.25
1% 1/10W FF 805
43
21
SW2100
SM
2
1
R2116
3.32K
1% 1/16W MF 402
2
1
C2115
402
CERM
50V
5%
100pF
1
2
6
Q5909
SOT-363
2N7002DW
21 103
051-6532
03
GND_SMU_AVSS
ALS1_OUT
SYS_LED
ALS1_OUT_DIV
ALS1_OUT_R
SLEEPLED_EN_L_DIV
SLEEPLED_ANODE
SLEEPLED_ANODE_F
SLEEPLED_ANODE_F_Q
SLEEPLED_EN_L
ALS1_PHOTODIODE
MIN_LINE_WIDTH=10 mil
MIN_NECK_WIDTH=10 mil
SMU_RESET_L
KBDLED_COMP
MAKE_BASE=TRUE
SYS_KBDLED
KBDLED_LX
_PP5V_RUN_KBDLED
_PP3V3_PWRON_ALS1
_PP5V_PWRON_SLEEPLED
KBDLED_RETURN MIN_LINE_WIDTH=10 mil MIN_NECK_WIDTH=10 mil
KBDLED_ANODE MIN_LINE_WIDTH=10 mil MIN_NECK_WIDTH=10 mil
ALS_GAIN_BOOST
ALS1_GAIN_BOOST_L
MIN_NECK_WIDTH=10 mil MIN_LINE_WIDTH=10 mil
ALS1_OP_IN
32
16
17
17
61
13
17
17
13
13
13
13
6
6
13
5
5
5
6
6
6
Preliminary
GND
GND
VDD
(SYM 6 OF 7)
DRAWING
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
NONE
U3Lite Core Power
Page Notes
Power aliases required by this page:
- _PPVCORE_PWRON_NB
BOM options provided by this page: (NONE)
(NONE)
Signal aliases required by this page:
Master: Link
R14
T16
T11
U18
U13
U10
V15
K15
V12
K12
L17
L14
M16
M11
N18
N13
P15
P12
R17
W17
W14
AC13
B22
B16
B13
B4
AC7
D25
D19
D10
D7
D2
F22
F16
F13
G27
G23
AE25
G4
H19
H10
J14
J9
K25
K21
K16
K11
K6
AE19
K2
L18
L13
L10
M20
M15
M12
N27
N23
N17
AE10
N14
N9
N8
N4
P19
P16
P11
R18
R13
R10
AE4
T27
T23
T20
T15
T12
T6
T2
U17
U14
U9
AG22
V19
V16
V11
W25
W21
W18
W13
W8
W4
Y20
AG16
Y15
Y12
AA19
AA10
AB27
AB23
AB6
AB2
AC22
AC16
AG13
AG7
U3
PBGA
OMIT
U3LITE
V1.0-300MM
2
1
C2222
402
0.1UF
20% 10V CERM
2
1
C2223
CERM
10V
20%
0.1UF
402
2
1
C2224
402
0.1UF
20% 10V CERM
2
1
C2226
CERM
10V
20%
402
0.1UF
2
1
C2225
402
0.1UF
20% 10V CERM
2
1
C2228
CERM
10V
20%
0.1UF
402
2
1
C2227
402
0.1UF
20% 10V CERM
2
1
C2230
CERM
10V
20%
0.1UF
402
2
1
C2229
402
0.1UF
20% 10V CERM
2
1
C2232
402
0.1UF
20% CERM
10V
2
1
C2231
20%
402
0.1UF
10V CERM
2
1
C2234
402
0.1UF
20% 10V CERM
2
1
C2233
CERM
10V
20%
0.1UF
402
2
1
C2236
402
0.1UF
20% 10V CERM
2
1
C2235
402
0.1UF
20% 10V CERM
2
1
C2238
402
0.1UF
20% 10V CERM
2
1
C2237
CERM
10V
20%
402
0.1UF
2
1
C2240
402
0.1UF
20% 10V CERM
2
1
C2239
10V
20%
0.1UF
402
CERM
2
1
C2242
CERM
10V
20%
0.1UF
402
2
1
C2241
CERM
10V
20%
0.1UF
402
2
1
C2243
CERM
10V
20%
0.1UF
402
2
1
C2244
402
0.1UF
20% 10V CERM
2
1
C2245
402
0.1UF
20% 10V CERM
2
1
C2246
402
0.1UF
20% 10V CERM
2
1
C2247
402
0.1UF
20% 10V CERM
ABBREV=DRAWING
TITLE=FIZZY
10322
03
051-6532
_PPVCORE_PWRON_NB
LAST_MODIFIED=Mon Feb 23 19:04:04 2004
5
Preliminary
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