Page 1
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
D
Module
Page
(.csa)
1
2
3
4
5
6
7
8
9
10
11
C
TOP
12
13
14
15
16
17
18
19
20
21
22
23
24
B
25
26
27
Processor
Interface
28
29
30
31
32
Main
Memory
A
DRAWING
TITLE=LINK
ABBREV=DRAWING
LAST_MODIFIED=Mon Feb 23 18:35:53 2004
8
33
34
35
PART#
QTY
337S2835
343S0283
338S0154 CRITICAL
343S0288
341S1340
341S1394
78
(1)
Table of Contents
(2)
System Block Diagram
(3)
Power Block Diagram
(4)
Revision Notes
(5)
Power & Signal Aliases
(6)
Functional Test Properties
(7)
System Power Connectors
(8)
Battery Charger
(9)
1.8V / 1.5V/ 1.2V Regulators
(10)
3.3V / 5V Regulators
(11)
2.5V / NB Vcore / PMU Regulators
(12)
Vesta Power / Misc
(13)
System Management Unit (SMU)
(14)
Power Sequencing Connections
(15)
Thermal Sensor / Fans
(16)
Misc Internal Connectors
(18)
Q51 Specific design/Connectors
(20)
I2C Connections
(21)
LMU Support
(22)
U3Lite Core
(23)
Shasta Core
(24)
U3Lite Misc
(25)
Shasta Misc
(26)
Pulsar Core
(27)
Pulsar Clocks
(28)
U3Lite Processor Interface
(29)
PPC970 Processor Interface
(30)
PPC970 Pull-ups / Pull-downs
(31)
PPC970 Core
(32)
PPC970 Bypassing
(33)
CPU VCore Regulator
(36)
CPU Temperature Monitoring
(37)
U3Lite Memory Interface
(38)
Memory Series Termination
(40)
SO-DIMM Connectors
Contents
Module Components
DESCRIPTION
IC,PPC970,1.8GHz,1.1V,80C,25W,576CBGA1U2900
IC,U3LITE,V1.1,300MM,PBGA
1
IC,ASIC,SHASTA,V1.1,484BALL,PBGA
1
1
IC,ATI,M11-CSP64,NO HEATSPREADER
1
IC,ATI,M11-CSP128,NO HEATSPREADER
1
IC,ASIC,VESTA,V1.1
BOOTROM,PROTO,Q51
1
SMU,PROTO,Q51
1
REFERENCE DESIGNATOR(S)
U2300
U4900
U4900
U8600
U7500
U1300
CRITICAL BOM OPTION
CRITICAL
CRITICALU3343S0284
CRITICAL
CRITICAL338S0158
CRITICAL
CRITICAL
CRITICAL
6
67
M11CSP64
M11CSP128
Date
Sync
N/A
N/A
N/A
N/A
N/A
N/A
Gila
Gila
Gila
U3Lite
Gila
Gila
Gila
Gila
U3Lite
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
09/25/03
08/01/03
09/11/03
09/15/03
09/11/03
09/11/03
07/28/03
09/01/03
10/01/03
09/26/03
08/01/03
07/28/03
08/01/03
09/01/03
07/28/03
09/18/03
07/28/03
09/18/03
09/18/03
09/18/03
09/18/03
09/18/03
09/18/03
09/18/03
09/11/03
09/25/03
09/18/03
08/01/03
08/01/03
(Link)
(Nimitz)
(Link)
(Link)
(Link)
(Link)
(Fizzy)
(smu_real)
(Link)
(Link)
(Nimitz)
(Gila)
(Nimitz)
(Gila)
(Fizzy)
(Fizzy)
(Link)
(Gila)
(Nimitz)
(Nimitz)
5
LINK
02/23/2004
(.csa)
Module
Graphics
HyperÂTransport
PCI
Disk
Ethernet
FireWire
USB
Modem
Audio
CRef
Alternates Components
PART NUMBER
343S0282 U3
Schematic / PCB #’s
PART#
051-6532 SCH1
820-1573
ALTERNATE FOR
PART NUMBER
343S0284
QTY
DESCRIPTION
SCHEM,LINK,Q51
1
PCBF,LINK,Q51
1
5
BOM OPTION
Page
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
REF DES
REFERENCE DESIGNATOR(S)
(100)
(101)
(102)
(103)
COMMENTS:
U3L,V1.1,200MM,PBGA
PCB1
(48)
(49)
(50)
(51)
(52)
(57)
(59)
(60)
(62)
(74)
(75)
(76)
(77)
(78)
(80)
(81)
(83)
(84)
(86)
(87)
(88)
(89)
(90)
(91)
(94)
(95)
(99)
4
3
Contents
U3Lite AGP Interface
M10-CSP64 AGP Interface
GPU VCore Regulator
M10-CSP64 Core
M10-CSP64 Misc Power
TMDS Terminations
Video Connectors
U3Lite HyperTransport Interface
Shasta HyperTransport Interface
South Bridge PCI Interface
BootROM
AirPort Extreme Connector
USB2 Controller PCI Interface
CardBus Controller & Connector
South Bridge Disk Interfaces
Serial ATA to Parallel ATA Bridge
UATA/PATA Connectors
South Bridge Ethernet
Vesta Ethernet
Ethernet Magnetics & Connector
South Bridge Firewire
Vesta FireWire
FireWire Ports
USB Interfaces
Modem Interface
Audio Interface
End of Modules Placeholder
Signal Cross Reference (1 of 2)
Signal Cross Reference (2 of 2)
Component Cross Reference (1 of 2)
Component Cross Reference (2 of 2)
DIMENSIONS ARE IN MILLIMETERS
XX
X.XX
X.XXX
ANGLES
DO NOT SCALE DRAWING
THIRD ANGLE PROJECTION
3
4
TABLE_ALT_HEAD
TABLE_ALT_ITEM
BOM OPTION
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
Date
Sync
(Nimitz)
(Link)
(Nimitz)
(Nimitz)
(Nimitz)
(Nimitz)
(Fizzy)
(Fizzy/Nimitz)
(Fizzy)
(Fizzy)
(Fizzy)
(Fizzy)
(Fizzy)
(Fizzy/Nimitz)
(Fizzy)
(Fizzy)
(Fizzy/Nimitz)
(Fizzy)
(Fizzy)
(Fizzy)
Gila
U3Lite
Fizzy
Fizzy
Fizzy
Fizzy
Fizzy
N/A
N/A
N/A
N/A
09/18/03
07/01/03
09/11/03
07/01/03
07/01/03
08/01/03
07/01/03
09/18/03
09/30/03
09/13/03
09/30/03
08/01/03
09/30/03
09/30/03
07/28/03
07/28/03
07/28/03
07/28/03
07/28/03
08/01/03
07/28/03
07/28/03
08/06/03
09/30/03
08/06/03
08/06/03
09/25/03
METRIC
DRAFTER
ENG APPD
QA APPD
RELEASE
MATERIAL/FINISH
NOTED AS
APPLICABLE
REV
ECN
ZONE
31600803
DESCRIPTION OF CHANGE
ENGINEERING RELEASED
EVT1
BOM Option Table
BOM Options
DEVELOPMENT
GPU_SS
MPIC_NB
MPIC_SB
PATA_3V3_LOGIC
PATA_5V_LOGIC
PCI_64BIT
SMU_CPU_I2C
SMU_CPU_JTAG
THERM_1
THERM_1B
THERM_2
THERM_2B
THERM_3
THERM_3B
VESTA1V2_BURST
VESTA1V2_PULSE
VESTA_DS_ONLY_EN0
VESTA_PWR_CLASS_0
AGP_BUSYSTOP
NO_SMU_I2C_D
EI_3TO1
CPU_PLL_MEDIUM
CPU_AVDD_2V8
SB_HT_200M
M11CSP64
M11CSP128
INT_TMDS
EXT_TMDS
Apple Computer Inc.
DESIGN CK
MFG APPD
DESIGNER
SCALE
NONE
SIZE
D
2
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
TITLE
SCHEM,LINK,Q51
DRAWING NUMBER
051-6532
12
CK
APPD
DATE
02/23/04
630-4843
630-4902
PCBA,LINK,Q51
SHT
NO STUFF
REV.
1 103
STUFF
630-4843
630-4902
1
ENG
APPD
?
03
OF
DATE
D
C
B
A
Page 2
78
6
5
4
3
12
J700
Nicky (PWR)
Connector
P.7
D
Power Supply
& Charger
P.7-12
U1300
J750
SMU
P.13
U2900
CPU
NEO 10S
P.26-29
Level shifting
I2C
Battery
Connector
P.7
C
J1600
RTC
P.13
U2600
LEFT USB
Bluetooth
Connector
P.16
I2C buses
Pulsar
Clock Gen
P.23-24
Max1668
Thermal
P.15
EI Clocks
VSP Clock
HT Clocks
AGP Clocks
PCI Clocks
SATA Clock
SYSTEM BLOCK DIAGRAM
AGP
PAGE 35
U3
P.17
ELASTIC INTERFACE
44-BIT/Directional
APPLE PI
1.2V/600MHz
APPLE PI
MISC
PAGE 21
J4010/J4020
DDR SDRAM DIMM 0
DDR SDRAM DIMM 1
SODIMM Connector
P.34
U3LITE
PAGE 25
CORE
PAGE 19
MAIN MEMORY
PAGE 32
PAGE 42
HYPERTRANSPORT
MEMORY BUS
2.5V
333MHz
128BITS
AGP BUS
4X/8X
1.5V/0.8V
32BITS
267/533MHZ
HYPERTRANSPORT
8-BIT/Direction
1.2V/400MHZ
CONTROL = 2.5V
U4900
ATI
M11
64/128MB
P.36,38-40
J5980
Inverter
Connector
MEMORY
CH. A
(INTERNAL MEM)
(INTERNAL MEM)
MEMORY
CH. B
(INTERNAL MEM)
(INTERNAL MEM)
LVDS
J5970
LCD Panel
Connector
P.41P.41
MEMORY
CH. C
MEMORY
CH. D
TMDS
RGB
DDC
S-Video/Comp
ENET Pairs
4 Datapairs @125MHz
J5900
DVI-I
Connector
P.41
J5960
S-Video
Connector
P.41
J8700
Gigabit
Ethernet
Connector
P.54
D
C
U8600
ETHERNET
FIREWIRE
SMU/JR
Debug
P.16
Modem
VESTA
Core
PAGE 12
PAGE 53
PAGE 56
FW-A Pairs
2 Datapairs @200MHz
FW-B pairs
2 Datapairs @400MHz
SYSTEM BLOCK DIAGRAM
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
APPLE COMPUTER INC.
J9010
Firewire A
Connector
P.57
J9020
Firewire B
Connector
P.57
J790
Backup Battery
Right USB
Connector
P.7
NOTICE OF PROPRIETARY PROPERTY
SIZE
DRAWING NUMBER
D
051-6532
NONE
SHT
SCALE
B
A
REV.
03
OF
1032
J8350
Hard DRIVE
133MHz/3.3V/16 Bit
Connector
P.51
B
U8150
Serial ATA
Bridge
P.50
J8300
OPTICAL DRIVE
Connector
P.51
J7800
Cardbus
1.5Gbps/1.2V/1 Bit/Directonal
Not Used
133MHz/3.3V/16 Bit
SATA1
PAGE 49 PAGE 49
SATA2
UATASATA
PCI
PAGE 44
HYPERTRANSPORT
U2300
SHASTA
CORE
PAGE 20
GPIO/PCI64
PAGE 22
PAGE 43
I2S0
I2S
PAGE 22
SCCA
I2S1 I2S2
ETHERNETFIREWIRE
PAGE 55 PAGE 52
SCCB
8-bit TX & 8-bit RX
GMII (3.3V/125MHz)
1394 OHCI (3.3V/98MHz)
J1699
Connector
Connector
P.48
PCI BUS
33MHZ
16/32 BITS
3.3V/5V
J7600
Airport
Extreme
Connector
PAGE 46
A
PORT = USB 2.0 (Low/Full/High Speed)
Bluetooth = USB 1.1 (Low/Full Speed)
32BITS
33MHZ
3.3V
U7800
U7700
Cardbus
PCI1510
PAGE 48 PAGE 47
J2130
USB Trackpad
USB 2.0
uPD720101
USB 1.1
Connector
P.18
U7500
BOOTROM
PAGE 45
KB
LED
P.18
J9500
Sound (Kazoo)
Connector
P.60 P.18 P.59
USB 1.1 (Low/Full Speed)
USB 2.0 (Low/Full/High Speed)
Sleep
J9400
ConnectorLED
8
67
5
4
3
2
1
Page 3
78
6
5
4
3
12
LEGEND
(overcurrent shutoff)
AC Adapter
D
(pg 7)
PP18V5_ALL_DCIN
In-Rush
Limiter
(pg 7)
PP18V5_ALL_INRUSH
Backfeed
Protection
(pg 8)
(MAX1544 Built-in Current Sense)
PP18V5_ALL_SENSE
Current
Sense
(pg 8)
PPBUS_ALL_B
PBUS Isolation
SMU
4.6V/3.3V
Power Supplies
(pg 11)
PPBUS_ALL_A
Circuit
(pg 8)
MAX1544
CPU Vcore Switcher
Voltage Toggled by SMU
(pg 29)
PPVCORE_RUN_CPU
TPS5120
5V/3.3V DC Switcher
(pg 10)
Backup
C
Battery
Connector
(pg 7)
MAX1993
GPU Vcore Switcher
Selectable 1.2V/1.0V
(pg 35)
PP1V2_RUN_GPU
Max1535
Battery Charger
Stops charging when
system draws more
than xxW
(pg 8)
Inverter Connector
(pg 39)
PPBUS_INVERTER
TPS5120
NBVCORE/2.5V DC Switcher
(pg 11)
PP=Power Positive
PN=Power Negative
_ALL=ON during Shutdown/Run/Sleep
_PWRON=ON during Run/Sleep
_RUN=ON during Run
LTC3412
1.2V DC Switcher
(pg 9)
SLEEP
PP5V_PWRON
PP3V3_PWRON
FET
SLEEP
FET
SLEEP
FET
TP62050
1.5V DC Switcher
(pg 9)
LP3982
1.8V LDO
(pg 9)
PP2V5_PWRON
SLEEP
FET
PPVCORE_NB_PWRON
PP1V2_PWRON
SLEEP
FET
PP5V_RUN_HD
PP5V_RUN
PP3V3_RUN
PP1V5_PWRON
SLEEP
FET
PP1V8_RUN
PP2V5_RUN
D
PP1V2_RUN
C
PP1V5_RUN
B
A
DRAWING
TITLE=LINK
ABBREV=DRAWING
LAST_MODIFIED=Mon Feb 23 18:35:54 2004
Charge Enable
Circuit
(pg 8)
5A Fuse (pg 8)
5A Fuse (pg 8)
Battery
Connector
(pg 11)
Cell 1 Cell 2 Cell 3
Cell 5
Cell 8 Cell 9Cell 7
3S3P Prismatic Battery Pack
Cell 6Cell 4
Battery Out
Enable Circuit A
(pg 8)
Battery Out
Enable Circuit B
(pg 8)
Power Budget
PPBUS_ALL_A
CPU_Core => 28W
GPU_Core => 6W
Inverter => 7W
1V8_RUN => 5W
Charger => ??W
TOTAL => 46W+?
1.5A Fuse (pg 12)
5VPWRON => 20W/25W
3V3PWRON => 10W/6.6W
2V5PWRON => 10W
1V2PWRON => 10W
Firewire => 8W/15W
TOTAL => 58W/67W
Port PWR
Enable Circuit
(pg 56)
Power Budget
PPBUS_ALL_B
Firewire B Conn
1.5A Fuse (pg 56)
Firewire A Conn
Power Block Diagram
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
APPLE COMPUTER INC.
(pg 56)
(pg 56)
NOTICE OF PROPRIETARY PROPERTY
SIZE
DRAWING NUMBER
D
051-6532
NONE
SHT
3
SCALE
B
A
REV.
03
OF
103
8
67
5
4
3
2
1
Page 4
78
6
5
4
3
12
Revision Notes
1/14/04
1) moved Q3001-Q3004,D3001,D3002,R3044,R3046,R3048,R3070,R3050,R3052,R3054 from Page 27 to page 16 to allow sync with Gila
2) moved AGP Vref (R4802,R4803,C4818) circuit to M11 specific page (49)
3) changed R2191 to pulldown on SYS_LED
*** sync with Gila ***
1/20/04
4) added 10 mil MIN_LINE_WIDTH and MIN_NECK_WIDTH to BKFD_PROT_EN_L
5) changed MIN_LINE_WIDTH of PP5V4_CHGR_LDO to 10 mils
6) moved J790 (backup battery/R USB connector) to page 18 for syncing with Logic
7) moved J1600 (BT/USB connector) to page 18 for syncing with Logic
8) moved C860-C865 (PBus hold-up caps) to page 18 for syncing with Logic
9) moved ZT9900-ZT9903 (EMI vias) to page 18 for syncing with Logic
10) moved SP500-SP505 and SP9900 to (speaker wire clips) to page 18 for syncing with Logic
11) moved ZT500-ZT505, ZT510, and ZT511 (plated screw holes) to page 18 for syncing with Logic
12) moved BS510 to page 18 for syncing with Logic
D
C
13) moved J2130 (trackpad connector) to page 18 for syncing with Logic
14) changed C2150 to 20%
15) added 10 mil MIN_LINE_WIDTH and MIN_NECK_WIDTH to KBDLED_ANODE and KDBLED_RETURN
16) changed C2115 to R2116 (3.32K 1% 402) to divide ALS output to 2.5V
*** sync with Logic ***
2/2/04
17) changed PCI from shasta to PCI_SB to allow desktops to insert series R’s
18) added pg 73 to alias PCI_SB nets back to PCI to reconnect
19) changed R2150 to 8.25 to reduce LED drive current to 20mA
20) changed Q2113 to second FET in Q5909
21) changed SMU_ADAPTER_ID to SMU_ONEWIRE
22) added R1620 and R1621 to divide ALS output down to 2.5V
23) added alias from TP_SATA_CLK25M to SATA_CLK25M
2/3/04
24) changed PPVCORE_RUN_CPU connection to XW592 to _PP1V5_RUN_FET
2/6/04
25) changed C720 to 0.22uF
26) changed R800 and R810 to 1/2W 1206 10mohm
27) changed C1068 to NO STUFF
28) removed Q1117 and C1114
29) changed L1115 to 2.2uH IHLP5050CE (152S0152)
30) changed C1121 to 680pF 402
31) changed R1102 to 20K 1% 402
32) added MIN_LINE_WIDTH and MIN_NECK_WIDTH properties to CPUVCORE_CM_N and CPUVCORE_CS_N
33) added MIN_LINE_WIDTH and MIN_NECK_WIDTH properties to ALS1_PHOTODIODE and ALS1_OP_IN
2/7/04
34) changed R5019 to 26.7K 1% to increase GPU Vcore current limit (rdar://3510721)
35) sync with Gila (Q45) to fix several power disconnects
36) added aliases on page 5 to set unused CKE, CS, and MUX controls back to TP
37) sync with Logic (Q43) to get DVO contraints
2/10/04
38) changed R3671 to 100K 0.1% to adjust the Tdiode range
39) changed C3671 to 10uF 20% 6.3V to adjust the Tdiode range
40) changed R3672 to 40.2K 0.1% to adjust the Tdiode range
41) changed R3676 to 100K 0.1% to adjust the Tdiode range
42) changed C3676 to 10uF 20% 6.3V to adjust the Tdiode range
43) changed R3677 to 40.2K 0.1% to adjust the Tdiode range
44) mirrored FL9020 and FL9021 to fix layout
2/11/04
45) changed L970 to 152S0154 (10uH) to reduce size
2/12/04
46) removed 197S0703 as alternate for 197S0037 (25MHz Vesta crystal)
47) changed all references to SMU_MANUAL_RESET_L to SMU_RESET_L
2/19/04
48) removed DC current limit circuit (U870 and associated discretes)
49) added BOMOPTION for 2.8V CPU Avdd LDO
50) changed R4800 to 2.2 ohm 603, C4811 to 1uF 402, and C4816 to 0.1uF 402 in U3Lite AGP Avdd filter.
51) changed R1610 (series R on SMU_ONEWIRE output) to 0 ohm
52) added R1611 (1k pullup to PP3V3_ALL) on ADAPTER_ID to power SMU_ONEWIRE interface
2/23/04
53) changed C8160-C8160 (SATA AC coupling caps) to 0.01uF per Marvell recommendation
54) added NO_TEST properties to CPUVCORE_GNDSENSE and CPUVCORE_SENSE
D
C
B
A
APPLE COMPUTER INC.
8
67
5
4
3
2
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
051-6532
NONE
SHT
4 103
SCALE
1
REV.
03
OF
B
A
Page 5
_PP1V8_SATABR
SHT
5
12
7
17
13
13
18
16
13
D
19
52
12
16
29
52
61
51
52
48
49
23
45
31
15
41
49
48
47
46
45
C
49
29
51
36
37
24
43
22
24
B
26
18
29
28
27
18
A
REV.
03
OF
103
78
Page Notes
Power aliases required by this page:
N/A (Most aliases are on this page)
Signal aliases required by this page:
N/A (Most aliases are on this page)
BOM options provided by this page:
(NONE)
AGP Signal Aliasing
PCI_RESET_L
48
47
46
45 41
48
47
46
5
MAKE_BASE=TRUE
PCI_RESET_L
45
5
MAKE_BASE=TRUE
PCI_CLK33M_AIRPORT
6
MAKE_BASE=TRUE
PCI_CLK33M_CBUS
MAKE_BASE=TRUE
PCI_CLK33M_USB2
MAKE_BASE=TRUE
SATA_CLK25M
MAKE_BASE=TRUE
PCI_CLK33M_SB_EXT
45
MAKE_BASE=TRUE
D
GPU is D3cold
PCI Signal Aliasing
CardBus is D3cold
_GPU_RESET_L
ALIAS
_PCI_CBUS_RESET_L
ALIAS
PCI_CLK_P3
ALIAS
_PCI_CLK33M_AIRPORT
PCI_CLK_GP1
ALIAS
_PCI_CLK33M_CBUS
PCI_CLK_GP0
ALIAS
_PCI_CLK33M_USB2
PCI_CLK_P4
ALIAS
_SATA_CLK25M
PCI_CLK_P1
ALIAS
37
49
25
47
25
49
25
48
25
51
25 25
PPBUS_ALL_A
6
PPBUS_ALL_B
6
_PPVCORE_CPU_REG
32
31
PBUS PWR
VOLTAGE=18.5V
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
VOLTAGE=18.5V
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
CPU/GPU Core PWR
6
_PPBUS_ALL_A
_PPVIN_CPUVCORE
_PPVIN_GPUVCORE
_PPBUS_INV
_PPBUSA_BBATT
_PPBUS_ALL_B
_PPVIN_5V3VPWRON
_PPVIN_2V5_NBVCORE_PWRON
_PPBUS_FW
_PPBUSB_BBATT
PPVCORE_RUN_CPU
MAKE_BASE=TRUE
VOLTAGE=1.1V
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
ALIAS
ALIAS
5
_PWRON PWR
_PP5V_PWRON_REG
10
42
8
17
31
38
42
17
8
17
10
11
12
17
6
PPVCORE_CPU
32
31
30
29
27
PP5V_PWRON_REG
MAKE_BASE=TRUE
VOLTAGE=5V
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
_PP3V3_PWRON_REG
10
PP3V3_PWRON_REG
MAKE_BASE=TRUE
VOLTAGE=3.3V
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
ALIAS
ALIAS
USB Signal Aliasing
USB "0": Left USB Port
USB2_N<0>
6
59
USB2_P<0>
6
59
USB2_PWREN<0>
59
C
6
59
6
USB2_OC<0>
USB "1": Right USB Port
USB2_N<1>
59
6
USB2_P<1>
6
59
USB2_PWREN<1>
59
6
USB2_OC<1>
59
6
USB "2": BlueTooth
USB2_N<2>
6
59
USB2_P<2>
6
59
USB2_PWREN<2>
59
USB2_OC<2>
59
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
USB2_LT_N
MAKE_BASE=TRUE
USB2_LT_P
MAKE_BASE=TRUE
LTUSB_PWREN
MAKE_BASE=TRUE
LTUSB_OVERCURRENT
MAKE_BASE=TRUE
USB2_RT_N
MAKE_BASE=TRUE
USB2_RT_P
MAKE_BASE=TRUE
RTUSB_PWREN
MAKE_BASE=TRUE
RTUSB_OVERCURRENT
MAKE_BASE=TRUE
USB_BT_N
MAKE_BASE=TRUE
USB_BT_P
MAKE_BASE=TRUE
TP_USB2_PWREN2
MAKE_BASE=TRUE
USB2_OC2_PU
MAKE_BASE=TRUE
17
17
17
17
17
17
17
17
17
17
_PPVCORE_GPU_REG
38
PPVCORE_GPU_REG
MAKE_BASE=TRUE
VOLTAGE=1.2V
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
PP2V5_RUN
5
ALIAS
Graphic PWR
1
R505
0
5%
1/10W
FF
805
2
_PP2V5_GPU
PP2V5_GPU
ALIAS
MAKE_BASE=TRUE
VOLTAGE=2.5V
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
XW510
JUMPER
40
USB "3": MicroDash Modem
USB2_N<3>
6
59
USB2_P<3>
6
59
USB2_PWREN<3>
59
USB2_OC<3>
59
B
USB2_N<4>
6
59
USB2_P<4>
6
59
USB2_PWREN<4>
59
USB2_OC<4>
59
USB "4": Trackpad/Keyboard
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
USB_MODEM_N
MAKE_BASE=TRUE
USB_MODEM_P
MAKE_BASE=TRUE
TP_USB2_PWREN3
MAKE_BASE=TRUE
USB2_OC3_PU
MAKE_BASE=TRUE
USB_TPAD_N
MAKE_BASE=TRUE
USB_TPAD_P
MAKE_BASE=TRUE
TP_USB2_PWREN4
MAKE_BASE=TRUE
USB2_OC4_PU
MAKE_BASE=TRUE
60
60
17
17
PP3V3_PWRON
SMU Signal Aliasing
SMU_SLEEP SYS_SLEEP
13 10
SMU_WARM_RESET_L
22
13
ALIAS
MAKE_BASE=TRUE
25
11
PP2V5_RUN
5
PP1V8_RUN
6
5
ATI_MEMIO_1V8
R503
1/4W
1210
1
R599
100K
5%
1/16W
MF
402
2
SYS_WARM_RESET_L
MAKE_BASE=TRUE
0
5%
FF
1
2
ALIAS
22
ATI_MEMIO_2V5
1
R501
0
5%
1/4W
FF
1210
2
_PPVCORE_GPUFB
PPVCORE_GPUFB
45
23
MAKE_BASE=TRUE
VOLTAGE=1.8V
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
48
Test Point Aliasing
EXT_LED_L
FAN_RPM2
13
FAN_TACH2
13
FAN_TACH3
13
FAN_TACH4
13
FAN_TACH5
13
I2C_SMU_D_SCL
A
13
NB_PMR_OBSV
22
NB_THMI
22
NB_THMO
22
SATA_RXD_P2_C
50
SATA_RXD_N2_C
50
SATA_TXD_P2
50
SATA_TXD_N2
50
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
TP_EXT_LED_L
MAKE_BASE=TRUE
TP_FAN_RPM2
MAKE_BASE=TRUE
TP_FAN_TACH2
MAKE_BASE=TRUE
TP_FAN_TACH3
MAKE_BASE=TRUE
TP_FAN_TACH4
MAKE_BASE=TRUE
TP_FAN_TACH5
MAKE_BASE=TRUE
TP_I2C_SMU_D_SCL
MAKE_BASE=TRUE
TP_NB_PMR_OBSV
MAKE_BASE=TRUE
TP_NB_THMI
MAKE_BASE=TRUE
TP_NB_THMO
MAKE_BASE=TRUE
TP_SATA_RXD_P2
MAKE_BASE=TRUE
TP_SATA_RXD_N2
MAKE_BASE=TRUE
TP_SATA_TXD_P2
MAKE_BASE=TRUE
TP_SATA_TXD_N2
MAKE_BASE=TRUE
More Test Point Aliasing
EI_CPU1_CLK_N_R
25
EI_CPU1_CLK_P_R
25
CPU1_HTBEN_R
25
EI_CPU1_SYNC_R
25
RAM_CKE_R<2>
33
RAM_CKE_R<3>
33
RAM_CKE_R<6>
33
RAM_CKE_R<7>
33
RAM_CS_L_R<2>
33
RAM_CS_L_R<3>
33
RAM_CS_L_R<10>
33
RAM_CS_L_R<11>
33
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
TP_EI_CPU1_CLK_N
MAKE_BASE=TRUE
TP_EI_CPU1_CLK_P
MAKE_BASE=TRUE
TP_CPU1_HTBEN_R
MAKE_BASE=TRUE
TP_EI_CPU1_SYNC_R
MAKE_BASE=TRUE
TP_RAM_CKE_R<2>
TP_RAM_CKE_R<3>
TP_RAM_CKE_R<6>
TP_RAM_CKE_R<7>
TP_RAM_CS_L_R<2>
TP_RAM_CS_L_R<3>
TP_RAM_CS_L_R<10>
TP_RAM_CS_L_R<11>
OPEN
PP1V2_RUN_GPU
MAKE_BASE=TRUE
VOLTAGE=1.2V
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
21
ALIAS
PP3V3_RUN
6
R502
1/10W
ALIAS
ALIAS
6
5
37
40
PP1V5_RUN
6
1
0
5%
FF
805
2
_PP3V3_GPU
PP3V3_GPU
MAKE_BASE=TRUE
VOLTAGE=3.3V
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
PP3V3_AGP
VOLTAGE=3.3V
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
PP1V8_RUN
1
R504
0
5%
1/10W
FF
805
2
_PP1V8_GPU
PP1V8_GPU
ALIAS
MAKE_BASE=TRUE
VOLTAGE=1.8V
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
1
R500
0
5%
1/10W
FF
805
2
PP1V5_GPU
ALIAS
RAM_MUXEN0
33
RAM_MUXEN4
33
PPVCORE_GPU
37
36
_PP1V5_GPU_AGP
MAKE_BASE=TRUE
VOLTAGE=1.5V
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
37
40
39
41
40
39
37
39
37
ALIAS
ALIAS
39
_PP2V5_PWRON_REG
11
_PP1V5_PWRON_REG
9
PP1V5_PWRON_REG
MAKE_BASE=TRUE
VOLTAGE=1.5V
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
_PP1V2_PWRON_REG
9
_PPVCORE_NB_REG
11
PPVCORE_NB_REG
MAKE_BASE=TRUE
VOLTAGE=1.3V
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
PP2V5_PWRON_REG
MAKE_BASE=TRUE
VOLTAGE=2.5V
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
PP1V2_PWRON_REG
MAKE_BASE=TRUE
VOLTAGE=1.2V
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
ALIAS
ALIAS
ALIAS
ALIAS
XW552 Always close
GND
40
TP_RAM_MUXEN0
TP_RAM_MUXEN4
GND_CHASSIS_DVI
17 42
VOLTAGE=0V
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
GND_CHASSIS_INVERTER
17 42
VOLTAGE=0V
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
GND_CHASSIS_LVDS
6
VOLTAGE=0V
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
GND_CHASSIS_IO
6
17
VOLTAGE=0V
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
4
PP5V_PWRON
VOLTAGE=5V
MIN_LINE_WIDTH=25 mil
OPEN
OPEN
21
21
21
PP3V3_PWRON
21
PP2V5_PWRON
21
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
MIN_NECK_WIDTH=10 mil
PP1V5_PWRON
_PP5V_PWRON_AUDIO
ALIAS
_PP5V_PWRON_MODEM
ALIAS
_PP5V_PWRON_LTUSB
ALIAS
_PP5V_PWRON_RTUSB
ALIAS
_PP5V_PWRON_SLEEPLED
ALIAS
_PP5V_PWRON_TPAD
ALIAS
_PP5V_PWRON_3V3ALL
ALIAS
_PP5V_PWRON_FAN
ALIAS
_PP5V_PWRON_GPUVCORE
ALIAS
_PP5V_PWRON_SERIAL
ALIAS
_PPVIN_1V2PWRON
ALIAS
_PP5V_PWRON_5VRUN
ALIAS
_PP5V_CBUS
ALIAS
_PP5V_CPUVCORE_VDD
ALIAS
_PP5V_CPUTHERM
ALIAS
VOLTAGE=3.3V
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
VOLTAGE=2.5V
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
PP1V2_PWRON
_PP3V3_PWRON_AUDIO
ALIAS
_PP3V3_PWRON_MODEM
ALIAS
_PP3V3_PWRON_SB
ALIAS
_PPPCI64_PWRON_SB
ALIAS
_PPPCI32_PWRON_SB
ALIAS ALIAS
_PP3V3_PWRON_USB
ALIAS
_PP3V3_PWRON_BT
_PP3V3_PWRON_ALS1
ALIAS
_PPVIN_1V5PWRON
ALIAS
_PP3V3_PWRON_THERM
ALIAS
_PP3V3_PWRON_3V3RUN
ALIAS
_PP3V3_CBUS
ALIAS
_PP3V3_CPUTHERM
ALIAS
_PP3V3_PWRON_1V8RUN
ALIAS
_PP2V5_PWRON_SB
ALIAS
_PP2V5_PWRON_HT
ALIAS
_PP2V5_PWRON_DIMM
ALIAS
_PP2V5_ENET
ALIAS
PP2V5_HT
ALIAS
_PPSPD_DIMM
ALIAS
_PP2V5_PWRON_2V5RUN
ALIAS
_PP2V5_PWRON_1V8RUN
ALIAS
PP2V5_PWRON_RAM
ALIAS
VOLTAGE=1.5V
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
ALIAS
ALIAS
ALIAS
VOLTAGE=1.2V
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ONLY ONE CAN BE CLOSED Between XW560/XW561!!!
ONLY ONE CAN BE CLOSED Between XW550/XW551!!!
ALIAS
PPVCORE_PWRON_NB
MAKE_BASE=TRUE
VOLTAGE=1.3V
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
VOLTAGE=0V
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
_GND_CHASSIS_DVI_TOP
_GND_CHASSIS_INV
_GND_CHASSIS_LVDS
_GND_CHASSIS_ENET
_GND_CHASSIS_FW_PORT1
_GND_CHASSIS_FW_PORT2
_GND_CHASSIS_DVI_BOTTOM
_GND_CHASSIS_SVIDEO
XW520
JUMPER
OPEN
XW530
JUMPER
XW540
JUMPER
XW560
JUMPER
OPEN
XW561
JUMPER
OPEN
XW552
JUMPER
OPEN
Chassis Grounds
PPVCORE_PWRON_PULSAR
_PP1V5_PWRON_1V5RUN
PP1V5_PWRON_NB_AVDD
_PP1V2_PWRON_DISK_SB
_PP1V2_PWRON_HT
_PP1V2_PWRON_SB
_PPVCORE_PWRON_SB
_PP1V2_PWRON_1V2RUN
_PPVCORE_PWRON_NB
55
58
58
42
3
_RUN PWR
PP3V3_ALL
_PP3V3_ALL_LDO
61
60
17
17
19
17
11
15
38
16
9
10
49
31
32
61
60
45
23
21
18
21
21
59
17
19
9
15
10
49
32
9
56
45
23
21
44
35
55
43
35
11
9
33
24
24
9
43
36
33
26
50
44
23
21
9
20
42
42
11
2.5V SMU VRef
PP2V5_SMU_VREF
32
MAKE_BASE=TRUE
_PP5V_RUN_FET
10
_PP5V_RUN_HD_FET
10
_PP3V3_RUN_FET
10
_PP2V5_RUN_FET
11
_PP1V8_RUN_LDO
9
_PP1V5_RUN_FET
9
5
_PP1V2_RUN_FET
9
_PP1V5_RUN_FET
9
5
PP1V8_RUN_LDO
MAKE_BASE=TRUE
VOLTAGE=1.8V
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
XW592
JUMPER
OPEN
ALIAS
ALIAS
ALIAS
21
APPLE COMPUTER INC.
VOLTAGE=3.3V
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
PP5V_RUN
VOLTAGE=5V
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
PP3V3_RUN
ALIAS
PP2V5_RUN
ALIAS
XW518
JUMPER
PP1V5_RUN
ALIAS
PP1V2_RUN
OPEN
_PP3V3_ALL_ACIN
ALIAS
_PP3V3_ALL_DCILIM
ALIAS
_PP3V3_ALL_HALLEFFECT
ALIAS
_PP3V3_ALL_RTC
ALIAS
_PP3V3_ALL_SMU
ALIAS
_PPVREF_SMU
ALIAS
_PP5V_RUN_KBDLED
ALIAS
_PP5V_UATA
ALIAS
_PPBU_RUN_FW
ALIAS
PP5V_RUN_CPU
ALIAS
PP5V_RUN_HD
VOLTAGE=5V
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
ALIASALIAS
ALIAS
VOLTAGE=3.3V
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
VOLTAGE=2.5V
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
PP1V8_RUN
VOLTAGE=1.5V
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
VOLTAGE=1.2V
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
6
_PP5V_PATA
_PP5V_RUN_AUDIO
_PP3V3_SATABR
_PP3V3_PATA
ALIAS
_PPVIO_PCI_USB2
ALIASALIAS
_PPVIO_PCI_CBUS
ALIAS
_PP3V3_PCI
ALIAS
_PP3V3_SB_PCI
ALIAS
_PP3V3_CPUVCORE
ALIAS
_PP3V3_RUN_FAN
ALIAS
_PP3V3_RUN_SI
ALIAS
_PP2V5_PCI
ALIAS
PP2V5_RUN_CPU
ALIAS
VOLTAGE=1.8V
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
21
ALIAS
PP1V5_AGP
ALIAS
PPVCORE_PULSAR
ALIAS
PP1V2_HT
ALIASALIAS
PP1V2_PULSAR
ALIAS
ONLY ONE CAN BE CLOSED Between XW590/XW591!!!
XW590
JUMPER
OPEN
XW591
JUMPER
OPEN
21
21
PP1V2_EI_NB
VOLTAGE=1.2V
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
PP1V2_EI_CPU
VOLTAGE=1.2V
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
Power Connections
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
051-6532
SCALE
NONE
8
67
5
4
3
2
1
Page 6
78
Wireless
FUNC_TEST=TRUE
PCI_AD<0>
FUNC_TEST=TRUE
PCI_AD<1>
FUNC_TEST=TRUE
PCI_AD<2>
FUNC_TEST=TRUE
PCI_AD<3>
FUNC_TEST=TRUE
PCI_AD<4>
FUNC_TEST=TRUE
D
C
B
A
PCI_AD<5>
FUNC_TEST=TRUE
PCI_AD<6>
FUNC_TEST=TRUE
PCI_AD<7>
FUNC_TEST=TRUE
PCI_AD<8>
FUNC_TEST=TRUE
PCI_AD<9>
FUNC_TEST=TRUE
PCI_AD<10>
FUNC_TEST=TRUE
PCI_AD<11>
FUNC_TEST=TRUE
PCI_AD<12>
FUNC_TEST=TRUE
PCI_AD<13>
FUNC_TEST=TRUE
PCI_AD<14>
FUNC_TEST=TRUE
PCI_AD<15>
FUNC_TEST=TRUE
PCI_AD<16>
FUNC_TEST=TRUE
PCI_AD<17>
FUNC_TEST=TRUE
PCI_AD<18>
FUNC_TEST=TRUE
PCI_AD<19>
FUNC_TEST=TRUE
PCI_AD<20>
FUNC_TEST=TRUE
PCI_AD<21>
FUNC_TEST=TRUE
PCI_AD<22>
FUNC_TEST=TRUE
PCI_AD<23>
FUNC_TEST=TRUE
PCI_AD<24>
FUNC_TEST=TRUE
PCI_AD<25>
FUNC_TEST=TRUE
PCI_AD<26>
FUNC_TEST=TRUE
PCI_AD<27>
FUNC_TEST=TRUE
PCI_AD<28>
FUNC_TEST=TRUE
PCI_AD<29>
FUNC_TEST=TRUE
PCI_AD<30>
FUNC_TEST=TRUE
PCI_AD<31>
FUNC_TEST=YES
PCI_FRAME_L
FUNC_TEST=YES
PCI_TRDY_L
FUNC_TEST=YES
PCI_IRDY_L
FUNC_TEST=YES
PCI_DEVSEL_L
FUNC_TEST=YES
PCI_STOP_L
FUNC_TEST=YES
PCI_PAR
FUNC_TEST=TRUE
PCI_CBE_L<0>
FUNC_TEST=TRUE
PCI_CBE_L<1>
FUNC_TEST=TRUE
PCI_CBE_L<2>
FUNC_TEST=TRUE
PCI_CBE_L<3>
FUNC_TEST=YES
PCI_SLOTA_REQ_L
FUNC_TEST=YES
PCI_SLOTA_GNT_L
FUNC_TEST=YES
PCI_SLOTA_INT_L
FUNC_TEST=YES
PCI_SLOTA_IDSEL
FUNC_TEST=YES
PCI_CLK33M_AIRPORT
FUNC_TEST=YES
TP_AIRPORT_PME_L
FUNC_TEST=YES
TP_AIRPORT_RF_DISABLE
FUNC_TEST=YES
AIRPORT_CLKRUN_L_PD
FUNC_TEST=YES
PP3V3_RUN
GND x 4
Within 1" of connector
62
49
48
47
46
45
62
49
48
47
46
45
62
49
48
47
46
45
62
49
48
47
46
45
62
49
48
47
46
45
62
49
48
47
46
45
49
62
48
47
46
45
49
62
48
47
46
45
49
62
48
47
46
45
49
48
47
46
45
45
45
45
45
5
62
49
48
47
62
46
45
49
48
62
47
46
45
49
62
48
47
46
45
49
62
48
47
46
45
49
62
48
47
46
45
49
62
48
47
46
45
49
62
48
47
46
45
49
62
48
47
46
45
49
62
48
47
46
45
49
62
48
47
46
45
49
62
48
47
46
45
62
49
48
47
45
62
49
48
47
45
62
49
48
47
45
49
48
47
46
62
45
49
48
47
46
62
45
49
48
47
46
62
45
49
48
47
46
62
45
49
48
47
46
62
45
49
48
47
46
62
45
49
48
47
46
62
45
49
48
47
46
62
45
62
49
48
47
62
49
48
47
62
49
48
47
62
49
48
47
45
62
49
48
47
62
49
45 51
48
47 52
62
49
48
47
45
62
49
48
47
45
62
49
48
47
45
62
49
48
47
45
47
45
47
45
47
23
47
5
47
47
47
X 4
6
Within 1" of connector
Within 1" of connector
DVI/VGA
Within 1" of connector
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=YES
TMDS_CONN_CLKN
FUNC_TEST=YES
TMDS_CONN_CLKP
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
DVI_DDC_CLK_UF
FUNC_TEST=YES
DVI_DDC_DATA_UF
FUNC_TEST=YES
FUNC_TEST=YES
PP5V_RUN_DDC
FUNC_TEST=YES
GND_CHASSIS_IO
GND x 1
LVDS
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
CLKLVDS_LN
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
CLKLVDS_UN
FUNC_TEST=YES
CLKLVDS_UP
FUNC_TEST=YES
LVDS_DDC_CLK
FUNC_TEST=YES
LVDS_DDC_DATA
FUNC_TEST=YES
PP3V3_LCD
FUNC_TEST=YES
GND_CHASSIS_LVDS
2 x GND
INVERTER
FUNC_TEST=YES
PPBUS_ALL_A
FUNC_TEST=YES
PP5V_INVERTER
FUNC_TEST=YES
BRIGHT_PWM
1 x GND
FUNCTIONAL TEST POINTS
TMDS_DN<0>
TMDS_DP<0>
TMDS_DN<1>
TMDS_DP<1>
TMDS_DN<2>
TMDS_DP<2>
VGA_R
VGA_G
VGA_B
VGA_VSYNC
VGA_HSYNC
DVI_HPD_UF
LVDS_L0N
LVDS_L0P
LVDS_L1N
LVDS_L1P
LVDS_L2N
LVDS_L2P
CLKLVDS_LP
LVDS_U0N
LVDS_U0P
LVDS_U1N
LVDS_U1P
LVDS_U2N
LVDS_U2P
42
62
41
62
42
41
62
42
41
62
42
41
62
42
41
62
42
41
62
42
62
42
42
42
42
42
42
42
42
42
42
17
5
42
39
42
39
42
39
42
39
42
39
42
39
42
39
42
39
42
39
42
39
42
39
42
39
42
39
42
39
42
39
42
39
42
39
42
39
42
P
5
6
5
42
42
8
6
S-Video
Within 1 of connector
FUNC_TEST=YES
TV_GND1
FUNC_TEST=YES
TV_GND2
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
TV_COMP
TV_C
TV_Y
42
42
42
42
42
PATA (SATA Bridge)
Within 1" of connector
FUNC_TEST=TRUE
PATA_DD<0>
FUNC_TEST=TRUE
PATA_DD<1>
FUNC_TEST=TRUE
PATA_DD<2>
FUNC_TEST=TRUE
PATA_DD<3>
FUNC_TEST=TRUE
PATA_DD<4>
FUNC_TEST=TRUE
PATA_DD<5>
FUNC_TEST=TRUE
PATA_DD<6>
FUNC_TEST=TRUE
PATA_DD<7>
FUNC_TEST=TRUE
PATA_DD<8>
FUNC_TEST=TRUE
PATA_DD<9>
FUNC_TEST=TRUE
PATA_DD<10>
FUNC_TEST=TRUE
PATA_DD<11>
FUNC_TEST=TRUE
PATA_DD<12>
FUNC_TEST=TRUE
PATA_DD<13>
FUNC_TEST=TRUE
PATA_DD<14>
FUNC_TEST=TRUE
PATA_DD<15>
FUNC_TEST=TRUE
PATA_DMARQ_R
FUNC_TEST=TRUE
PATA_DMACK_L
FUNC_TEST=TRUE
PATA_DA<0>
FUNC_TEST=TRUE
PATA_DA<1>
FUNC_TEST=TRUE
PATA_DA<2>
FUNC_TEST=TRUE
PATA_CS0_L
FUNC_TEST=TRUE
PATA_CS1_L
FUNC_TEST=TRUE
PATA_RESET_L
FUNC_TEST=TRUE
PATA_DSTROBE_R
FUNC_TEST=TRUE
PATA_HSTROBE
FUNC_TEST=TRUE
PATA_STOP
FUNC_TEST=TRUE
PATA_INTRQ_R
FUNC_TEST=TRUE
PP5V_RUN_HD
re
Within 1" of connector
FUNC_TEST=TRUE
PPLOGIC_PATA
GND x 5
Battery Conn
FUNC_TEST=YES
PPBATT_ALL_F
FUNC_TEST=YES
I2C_SMU_E_SCL
FUNC_TEST=YES
I2C_SMU_E_SDA
FUNC_TEST=YES
BATT_DET_L
FUNC_TEST=YES
GND_BATT
52
51
52
51
52
51
52
51
52
51
52
51
52
51
52
51
52
51
51
52
52
51
52
51
52
51
52
51
52
51
52
51
52
52
51
52
51
52
51
52
51
52
51
52
51
52
51
52
52
51
52
x4
5
x3
52
x2
7
(I2C_BATT_SCL)
18
13
(I2C_BATT_SDA)
18
13
7
x2
7
DC-in Connectors
Within 1" of connector
FUNC_TEST=YES
PP18V5_ALL_DCIN
GND x 3
x 3
11
7
67
5
l
5
UATA (Optical)
Within 2" of connector
FUNC_TEST=TRUE
UATA_DD<0>
FUNC_TEST=TRUE
UATA_DD<1>
FUNC_TEST=TRUE
UATA_DD<2>
FUNC_TEST=TRUE
UATA_DD<3>
FUNC_TEST=TRUE
UATA_DD<4>
FUNC_TEST=TRUE
UATA_DD<5>
FUNC_TEST=TRUE
UATA_DD<6>
FUNC_TEST=TRUE
UATA_DD<7>
FUNC_TEST=TRUE
UATA_DD<8>
FUNC_TEST=TRUE
UATA_DD<9>
FUNC_TEST=TRUE
UATA_DD<10>
FUNC_TEST=TRUE
UATA_DD<11>
FUNC_TEST=TRUE
UATA_DD<12>
FUNC_TEST=TRUE
UATA_DD<13>
FUNC_TEST=TRUE
UATA_DD<14>
FUNC_TEST=TRUE
UATA_DD<15>
FUNC_TEST=TRUE
UATA_DMARQ_R
FUNC_TEST=TRUE
UATA_DMACK_L
FUNC_TEST=TRUE
UATA_DA<0>
FUNC_TEST=TRUE
UATA_DA<1>
FUNC_TEST=TRUE
UATA_DA<2>
FUNC_TEST=TRUE
UATA_CS0_L
FUNC_TEST=TRUE
UATA_CS1_L
FUNC_TEST=TRUE
UATA_RESET_L
FUNC_TEST=TRUE
UATA_DSTROBE_R
FUNC_TEST=TRUE
UATA_HSTROBE
m
FUNC_TEST=TRUE
UATA_STOP
FUNC_TEST=TRUE
i
UATA_INTRQ_R
FUNC_TEST=TRUE
PP5V_RUN
GND x 5
Trackpad
Within 3" of connector
FUNC_TEST=YES
I2C_SMU_B_SCL
FUNC_TEST=YES
I2C_SMU_B_SDA
FUNC_TEST=YES
SYS_OVERTEMP_L
FUNC_TEST=YES
USB2_N<4>
FUNC_TEST=YES
USB2_P<4>
FUNC_TEST=YES
KBDLED_ANODE
FUNC_TEST=YES
KBDLED_RETURN
FUNC_TEST=YES
SYS_DOOR_AJAR
FUNC_TEST=YES
SYS_POWER_BUTTON_L
FUNC_TEST=YES
PP3V3_PWRON
FUNC_TEST=YES
PP5V_PWRON
FUNC_TEST=YES
PP3V3_ALL
FUNC_TEST=YES
PP3V3_RUN
4
52
50
52
50
52
50
52
50
52
50
52
50
52
50
52
50
52
50
52
50
52
50
50
52
52
50
52
50
52
50
52
50
52
52
50
52
50
52
50
52
50
52
50
52
50
52
50
52
52
50
52
50
52
x4
(I2C_DS1775_SCL)
18
13
(I2C_DS1775_SDA)
18
13
25
23
17
15
13
59
5
59
5
19
17
19
17
(SYS_LID_OPEN)
42
17
16
13
6
25
17
11
6
6
6
5
4
i
Firewire B
Within 1" of connector
FUNC_TEST=YES
FW_PORT1_TPA_P_FL
FUNC_TEST=YES
FW_PORT1_TPA_N_FL
FUNC_TEST=YES
FW_PORT1_TPB_P_FL
FUNC_TEST=YES
FW_PORT1_TPB_N_FL
FUNC_TEST=YES
FW_PORT1_AREF
FUNC_TEST=YES
GND_FW_PORT1_VG
FUNC_TEST=YES
PPFW_PORT1_VP
Firewire A
Within 1" of connector
FUNC_TEST=YES
FW_PORT2_TPA_P_FL
FUNC_TEST=YES
FW_PORT2_TPA_N_FL
FUNC_TEST=YES
FW_PORT2_TPB_P_FL
FUNC_TEST=YES
FW_PORT2_TPB_N_FL
FUNC_TEST=YES
PPFW_PORT2_VP
FUNC_TEST=YES
GND_FW_PORT2_VG
Fan Connectors
Within 2" of connector
FUNC_TEST=YES
FAN_RPM0
n
FUNC_TEST=YES
FAN_TACH0
FUNC_TEST=YES
FAN_RPM1
FUNC_TEST=YES
FAN_TACH1
FUNC_TEST=YES
PP5V_PWRON
GND x 2 - one by each fan
BT/USB Flex
Within 2" of connector
FUNC_TEST=YES
USB2_N<2>
FUNC_TEST=YES
USB2_P<2>
FUNC_TEST=YES
USB2_N<0>
FUNC_TEST=YES
USB2_P<0>
FUNC_TEST=YES
USB2_PWREN<0>
FUNC_TEST=YES
ALS0_OUT
FUNC_TEST=YES
USB2_OC<0>
FUNC_TEST=YES
ALS_GAIN_BOOST
FUNC_TEST=YES
ADAPTER_ID
PP3V3_PWRON x 1
PP5V_PWRON x 1
GND x 1
Backup Battery/USB Flex
Within 2" of connector
FUNC_TEST=YES
PPBUS_ALL_B
FUNC_TEST=YES
PPBUS_ALL_A
FUNC_TEST=YES
SYS_POWERUP
FUNC_TEST=YES
USB2_N<1>
FUNC_TEST=YES
USB2_P<1>
FUNC_TEST=YES
USB2_PWREN<1>
FUNC_TEST=YES
USB2_OC<1>
PP5V_PWRON x 1
GND x 1
3
58
58
58
58
58
58
58
58
58
58
58
58
58
ry
a
15
13
15
13
15
13
15
13
x 2
one by each fan
11
6
(USB_BT_N)
59
5
(USB_BT_P)
59
5
(USB2_LT_N)
59
5
(USB2_LT_P)
59
5
(LTUSB_PWREN)
59
5
17
13
(LTUSB_OVERCURRENT)
59
5
17
19
13
17
6
5
6
5
14
(USB2_RT_N)
59
5
(USB2_RT_P)
59
5
(RTUSB_PWREN)
59
5
(RTUSB_OVERCURRENT)
59
5
3
Sound Connector
Within 2" of connector
FUNC_TEST=YES
I2S0_DEV_TO_SB_DTI_F
FUNC_TEST=YES
I2S0_BITCLK_F
FUNC_TEST=YES
I2S0_MCLK_F
FUNC_TEST=YES
I2S0_SYNC_F
FUNC_TEST=YES
I2S0_SB_TO_DEV_DTO_F
FUNC_TEST=YES
I2S2_DEV_TO_SB_DTI_F
FUNC_TEST=YES
I2S2_BITCLK_F
FUNC_TEST=YES
I2S2_SYNC_F
FUNC_TEST=YES
AUDIO_GPIO_11
FUNC_TEST=YES
AUDIO_EXT_MCLK_SEL
FUNC_TEST=YES
AUDIO_LO_MUTE_L
FUNC_TEST=YES
AUDIO_SPKR_MUTE_L
FUNC_TEST=YES
AUDIO_LO_DET_L
FUNC_TEST=YES
AUDIO_LO_OPTICAL_PLUG_L
FUNC_TEST=YES
AUDIO_LI_DET_L
FUNC_TEST=YES
AUDIO_LI_OPTICAL_PLUG_L
FUNC_TEST=YES
I2S0_RESET_L_F
FUNC_TEST=YES
I2S2_RESET_L_F
FUNC_TEST=YES
SLEEPLED_ANODE
FUNC_TEST=YES
GND_AUDIO
FUNC_TEST=YES
PP5V_PWRON_AUDIO
FUNC_TEST=YES
PP3V3_PWRON_AUDIO
GND x 2
Modem Connector
Within 3" of connector
FUNC_TEST=YES
I2S1_SB_TO_DEV_DTO
FUNC_TEST=YES
I2S1_BITCLK
FUNC_TEST=YES
I2S1_SYNC
FUNC_TEST=YES
I2S1_RESET_L
FUNC_TEST=YES
I2S1_MCLK
FUNC_TEST=YES
I2S1_DEV_TO_SB_DTI
FUNC_TEST=YES
USB2_N<3>
FUNC_TEST=YES
USB2_P<3>
FUNC_TEST=YES
MODEM_RING2SYS_L
FUNC_TEST=YES
UDASH_SDOWN
FUNC_TEST=YES
I2C_SB_SCL
FUNC_TEST=YES
I2C_SB_SDA
APPLE COMPUTER INC.
2
ROM Control
Within 2" of U7500
61
61
61
61
61
61
61
61
61
23
61
23
61
23
61
23
61
23
61
23
61
23
61
23
61
61
61
19
x4
61
x3
61
x2
61
60
23
16
23
60
16
60
23
16
23
16
60
60
23
16
23
16
60
(USB_MODEM_N)
59
5
(USB_MODEM_P)
59
5
60
23
60
23
(I2C_MODEM_SCL)
23
18
(I2C_MODEM_SDA)
23
18
(SMU_BOOT_BUSY)
(SMU_BOOT_SCLK)
(SMU_BOOT_CE)
Functional Testpoints
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
051-6532
SCALE
NONE
12
FUNC_TEST=YES
ROM_ONBOARD_CS_L
FUNC_TEST=YES
ROM_OE_L
FUNC_TEST=YES
ROM_CS_L
FUNC_TEST=YES
ROM_WE_L
MISC
FUNC_TEST=YES
JTAG_NB_TMS
FUNC_TEST=YES
JTAG_NB_TDI
FUNC_TEST=YES
JTAG_NB_TDO
FUNC_TEST=YES
JTAG_NB_TCK
FUNC_TEST=YES
JTAG_NB_TRST_L
FUNC_TEST=YES
JTAG_SB_TMS
FUNC_TEST=YES
JTAG_SB_TDI
FUNC_TEST=YES
JTAG_SB_TDO
FUNC_TEST=YES
JTAG_SB_TCK
FUNC_TEST=YES
JTAG_SB_TRST_L
FUNC_TEST=YES
JTAG_VESTA_TMS
FUNC_TEST=YES
JTAG_VESTA_TDI
FUNC_TEST=YES
JTAG_VESTA_TDO
FUNC_TEST=YES
JTAG_VESTA_TCK
FUNC_TEST=YES
JTAG_VESTA_TRST_L
FUNC_TEST=YES
JTAG_CPU_TMS
FUNC_TEST=YES
JTAG_CPU_TDI
FUNC_TEST=YES
JTAG_CPU_TDO
FUNC_TEST=YES
JTAG_CPU_TCK
FUNC_TEST=YES
JTAG_CPU_TRST_L
FUNC_TEST=YES
SMU_RESET_L
FUNC_TEST=YES
SYS_POWER_BUTTON_L
FUNC_TEST=YES
SYS_RESET_BUTTON_L
FUNC_TEST=YES
PP1V8_RUN
FUNC_TEST=YES
PP2V5_PWRON
FUNC_TEST=YES
PPBUS_ALL_B
FUNC_TEST=YES
PP3V3_ALL
FUNC_TEST=YES
PPVCORE_RUN_CPU
FUNC_TEST=YES
PP1V2_RUN_GPU
FUNC_TEST=YES
CPU_VID<4>
FUNC_TEST=YES
CPU_VID<5>
FUNC_TEST=YES
SMU_BOOT_CNVSS
FUNC_TEST=YES
SMU_BOOT_TXD
FUNC_TEST=YES
SMU_BOOT_RXD
FUNC_TEST=YES
SYS_POWERUP_L
SHT
OF
6
1
47
46
47
46
45
46
47
45
46
47
45
22
22
22
22
22
23
18
23
18
23
23
18
23
18
12
12
12
12
12
27
28
18
27
28
18
28
27
18
27
28
18
28
27
16
19
13
16
13
6
16
13
5
6
5
6
5
5
31
13
13
16
13
16
13
16
13
14
13
REV.
03
103
D
C
42
17
B
A
Page 7
G
D
S
G
D
S
D1
D2
D3
D4S3
S2
GATE
S1
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Place L759 as close to J750 as possible
518S0117
Main Battery Connector
<R1a>
DC Power Input
(DC-In jack and associated circuit are on separate baord)
Vref = 3.3V * (R2a / (R1a + R2a))
ACIN Detection
<R2b>
<R1b>
Power Connectors
DC Inrush Limiter
<R2a>
Vth = 13.4V
Vth = Vref / (R2b / (R1b + R2b))
(BATT_IN_PD)
(GND_BATT)
(PPBATT_F)
1K resistor to protect SMU pins
518S0064
2
1
R705
402
MF
1/16W
5%
10K
2
1
R708
MF
1/16W
1%
102K
402
2
1
R709
MF
1/16W
1%
10K
402
2
1
R710
1/16W
402
MF
1%
102K
2
1
R711
MF
1%
57.6K
402
1/16W
2
1
C700
50V
0.1uF
10%
X7R
603-1
NO STUFF
2
5
1
3
4
U710
LMC7211
SM
CRITICAL
2
1
R713
470K
5%
1/16W
MF
402
21
R712
MF
1/16W
5%
402
1M
4
5
3
Q715
SOT-363
2N7002DW
1
2
6
Q715
2N7002DW
SOT-363
2
1
R719
1/16W
5%
MF
470K
402
2
1
R715
MF
402
1/16W
5%
10K
2
1
C710
0.01uF
20%
402
16V
CERM
2
1
R720
402
5%
330K
1/16W
MF
2
1
C720
0.22uF
25V
20%
CERM
805
21
L751
SM
FERR-50-OHM
CRITICAL
21
L755
FERR-EMI-100-OHM
SM
21
L756
FERR-EMI-100-OHM
SM
21
R755
5%
1K
402
1/16W
MF
2
1
R754
402
470K
5%
1/16W
MF
2
1
R706
5%
402
MF
1/16W
10K
PP3V3_ALL
9
8
7
6
5
4
3
2
10
1
J750
M-RT-SM
CRITICAL
87438-1033
21
L759
SM
FERR-EMI-100-OHM
21
L750
FERR-50-OHM
SM
CRITICAL
3
2
1
4
8
7
6
5
Q720
SI4405DY
SO-8
CRITICAL
4
3
2
1
J700
87438-0433
M-RT-SM
CRITICAL
7 103
051-6532
03
I2C_BATT_SCL
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=25 mil
VOLTAGE=0V
GND_BATT
MIN_NECK_WIDTH=10 mil
PPBATT_ALL_VSNS
VOLTAGE=12.8V
MIN_LINE_WIDTH=10 mil
MIN_LINE_WIDTH=25 mil
VOLTAGE=12.8V
PPBATT_ALL
MIN_NECK_WIDTH=10 mil
BATT_DET_L
I2C_BATT_SDA_F
I2C_BATT_SCL_F
ACIN_DIV
ADAPTER_PD
SMU_BATT_DET_L
MIN_LINE_WIDTH=8 mil
ACIN_ENABLE_L
MIN_NECK_WIDTH=8 mil
I2C_BATT_SDA
MIN_LINE_WIDTH=8 mil
ACIN_ENABLE_L_DIV
MIN_NECK_WIDTH=8 mil
MIN_LINE_WIDTH=25 mil
VOLTAGE=18.5V
PP18V5_ALL_INRUSH
MIN_NECK_WIDTH=10 mil
_PP3V3_ALL_ACIN
PP18V5_ALL_DCIN
VOLTAGE=18.5V
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
ACIN_1V20_REF
MAKE_BASE=TRUE
SMU_ACIN
SMU_ACIN_L
MIN_LINE_WIDTH=25 mil
VOLTAGE=12.8V
MIN_NECK_WIDTH=10 mil
PPBATT_ALL_F
13
11
12
18
6
8
8
6
13
18
8
5
6
8
8
6
Preliminary
Page 8
S2
GATE
S1
S3 D4
D3
D2
D1
S2
GATE
S1
S3D4
D3
D2
D1
S
D
G
S
D
G
G
D
S
G
D
S
G
D
S
G
D
S
CSSP
CSSN
ACIN
DCIN
SCL
SDA
INT*
IMAX
VMAX
CCS
CCI
CCV
CSIP
CSIN
VDD LDO
SRC
PDL
PDS
REF
DHIV
DHI
DLO
PGND
PAD
THM
GND
DAC
ACOK*
THM
BATT
I.C.
DLOV
G
D4
D2
S3
S2
D1
D3
S1
D1
D2
D3
D4 S3
S2
GATE
S1
G
D
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
DC-IN Input Current Limiter
Place U800 and U870 near R800
NC
SMBus Battery Charger
Battery Charge Path
Battery charge FET is open when not charging
Keep short and route as pair
RC time is 480K * 10uF @ 3.3V
NC
NC
NC
(PP18V5_ALL)
NC
SMBus Battery Charger
(PP18V5_ALL_SENSE)
FETs are quickly turned off (diode)
When AC is connected, P-channel
When AC is disconnected, P-channel FETs turn on
Battery Switch-over Circuit
2
1
C826
603
CERM
10V
1UF
20%
2
1
R821
169K
1%
1/16W
MF
402
2
1
R820
1/16W
100K
1%
MF
402
2
1
R801
4.7
5%
1/16W
402
MF
2
1
R802
5%
1/16W
402
MF
4.7
2
1
C801
50V
0.47UF
1206
20%
CERM
2
1
D810
MBRS140T3
SM
21
R800
0.010
MF
1%
CRITICAL
1/2W
1206
2
1
C802
0.47UF
CERM
50V
20%
1206
2
1
R896
402
MF
1/16W
5%
100K
3
2
1
4
8
7
6
5
Q890
CRITICAL
SOI
SI4435DY
3
2
1
4
8
7
6
5
Q880
CRITICAL
SI4435DY
SOI
2
1
R881
402
MF
5%
1/16W
330K
2
1
R891
100K
5%
402
1/16W
MF
2
1
R890
470K
MF
5%
402
1/16W
3
1
4
Q895
SUD45P03
TO-252
CRITICAL
2
1
R895
470K
MF
1/16W
5%
402
3
1
4
Q899
SUD45P03
TO-252
CRITICAL
4
5
3
Q800
SOT-363
2N7002DW
2
1
C897
CERM
805
6.3V
20%
10uF
2
1
R897
1/16W
402
1%
158K
MF
43
DP800
BAS16TW
SOT-363
2
1
R898
402
MF
1/16W
5%
100K
2
1
F899
SM-2
5AMP-125V
2
1
F895
5AMP-125V
SM-2
2
1
R899
5%
1/16W
402
470K
MF
2
1
C812
20%
25V
CERM
1206
4.7uF
2
1
C813
4.7uF
1206
CERM
25V
20%
2
1
C815
4.7uF
1206
CERM
25V
20%
2
1
C814
4.7uF
1206
CERM
25V
20%
2
1
C817
4.7uF
1206
CERM
25V
20%
2
1
C816
4.7uF
1206
CERM
25V
20%
2
1
C818
CRITICAL
20%
25V
ELEC
SM1
33uF
2
1
R812
603
MF
5%
1/16W
1
21
R810
1%
MF
0.010
CRITICAL
1/2W
1206
21
L810
SM1
10uH
CRITICAL
2
1
R811
1
1/16W
5%
603
MF
2
1
R825
402
20.5K
1%
1/16W
MF
2
1
R824
MF
1%
100K
402
1/16W
2
1
C825
1uF
CERM
20%
603
10V
2
1
C823
402
16V
0.01uF
CERM
20%
2
1
R805
NO STUFF
100K
1%
402
MF
1/16W
2
1
R806
NO STUFF
13K
1%
402
MF
1/16W
3
1
D800
SOT23
1N914
2
1
C800
805
CERM
25V
20%
1uF
2
1
R850
MF
402
1/16W
49.9K
1%
2
1
R851
1/16W
402
5%
MF
68K
2
1
C851
CERM
20%
0.1uF
25V
603
1
2
6
Q800
2N7002DW
SOT-363
2
1
R880
1/16W
5%
MF
402
470K
52
DP800
SOT-363
BAS16TW
2
1
C882
16V
10%
CERM
402
0.01UF
2
1
R882
MF
100K
5%
402
1/16W
2
1
C811
10%
50V
402
CERM
0.001uF
NO STUFF
1
2
6
Q882
SOT-363
2N7002DW
4
5
3
Q882
SOT-363
2N7002DW
2
1
C805
25V
1206
4.7uF
20%
CERM
2
1
C806
25V
1206
20%
CERM
4.7uF
2
1
C807
1206
4.7uF
20%
25V
CERM
2
1
C808
4.7uF
1206
CERM
20%
25V
2
1
C829
1UF
603
CERM
20%
10V
2
1
C824
20%
16V
CERM
402
0.01UF
2
1
C827
0.1UF
CERM
25V
20%
603
2
1
R826
5%
1/16W
MF
402
33
2
1
C830
402
10V
0.1UF
CERM
20%
2
1
C831
0.1UF
402
10V
20%
CERM
9
12
33
13
27
14
15
4
22
31
30
2
16
10
17
18
5
24
23
25
26
1
11
29
28
21
20
8
6
7
19
32
3
U800
MAX1535A
CRITICAL
QFN
2
1
R828
5%
1/16W
MF
0
402
2
1
C828
0.1UF
20%
603
CERM
25V
2
1
R827
5%
1/16W
MF
0
402
2
1
R892
1/16W
100K
5%
402
MF
21
R823
0
1/16W
MF
5%
402
2
1
C820
0.1UF
402
CERM
10V
20%
321
4
876
5
Q810
SOI
CRITICAL
SI4835BDY
2
1
R829
100K
5%
1/16W
MF
402
3
2
1
4
8
7
6
5
Q850
CRITICAL
SI4405DY
SO-8
2
1
R830
100K
5%
1/16W
MF
402
4
5
3
Q877
2N7002DW
SOT-363
321
4
8765
Q811
SI4336DY
CRITICAL
SO-8
2
1
R822
5%
402
MF
1/16W
30K
2
1
C822
16V
0.01uF
20%
CERM
402
21
XW800
SM
03
051-6532
1038
PP18V5_ALL_INRUSH
VOLTAGE=18.5V
MIN_NECK_WIDTH=10 mil
PP18V5_ALL_SENSE
MIN_LINE_WIDTH=25 mil
_PPBUS_ALL_B
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=10 mil
BKFD_PROT_EN_L_DIV
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=25 mil
VOLTAGE=12.6V
PPBATT_ALL_FUSEA
CHGR_THM
_PPBUS_ALL_A
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=20 mil
CHGR_DLOV_RC
MIN_LINE_WIDTH=10 mil
MIN_NECK_WIDTH=10 mil
PP5V4_CHGR_LDO
VOLTAGE=5.4V
CHGR_DAC
CHGR_CSSP
CHGR_CSSN
CHGR_VMAX
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=15 mil
VOLTAGE=0V
GND_CHGR
CHGR_CCS
CHGR_IMAX
_PPBUS_ALL_A _PPBUS_ALL_B
CHGR_ACIN_RC
PPBATT_ALL
CHGR_DCIN
MIN_NECK_WIDTH=10 mil
CHGR_DHI
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
CHGR_DHIV
MIN_LINE_WIDTH=20 mil
CHGR_DLOV
PPBATT_ALL_VSNS
I2C_CHGR_SCL
I2C_CHGR_SDA
MIN_NECK_WIDTH=10 mil
BATT_PBUSA_EN_L
MIN_LINE_WIDTH=10 mil
MIN_LINE_WIDTH=10 mil
MIN_NECK_WIDTH=10 mil
BATT_PBUSB_EN_L
CHGR_CHARGE_EN_L
SMU_ACIN_L
_PPBUS_ALL_A
MIN_NECK_WIDTH=10 mil
PPBATT_ALL_FUSEB
VOLTAGE=12.6V
MIN_LINE_WIDTH=25 mil
CHGR_PBUS_EN_L
MIN_LINE_WIDTH=10 mil
CHGR_PBUS_EN_L_DIV
MIN_NECK_WIDTH=10 mil
SMU_ACIN
CHGR_CCV
PPBATT_CHGR_RSNS
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
CHGR_CCS_RC
CHGR_CCI_RC
CHGR_CCV_RC
CHGR_CHARGE_EN_L_DIV
PPBATT_CHGR_OUT
BATT_ACIN_L_RC
BATT_PBUS_EN_L
SMU_ACIN
CHGR_CCI
SMU_CHARGE_BATT
CHGR_ACIN
CHGR_REF
SMU_CHARGE_BATT
CHGR_CSIP
SMU_CHARGE_BATT_L
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=10 mil
BKFD_PROT_EN_L
CHGR_CSIN
MIN_LINE_WIDTH=25 mil
PPBATT_CHGR_OUT
VOLTAGE=12.6V
MIN_NECK_WIDTH=10 mil
CHGR_REF
MIN_LINE_WIDTH=25 mil
CHGR_DLO
MIN_NECK_WIDTH=10 mil
MIN_NECK_WIDTH=10 mil
PPBATT_CHGR_SW
MIN_LINE_WIDTH=25 mil
42
42
42
13
13
17
17
17 17
17
12
12
8
8
8 8
8
8
8
13
13
7
5
11
5
5 5
7
7
18
18
7
5
7
8
7
8
8
8
8
8
Preliminary
Page 9
SW
SGND PGND
PAD
THERM
SVIN PVIN
PGOOD
VFB
ITH
SYNC/MODE
RUN/SS
RT
GND
SET
SHDN*
OUT1
FAULT*
OUT2
CC
IN
VIN
LBO
PG
SW
FB
SYNC
GND
PGND
LBI
EN
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
1.8V/1.5V/1.2V MAIN SUPPLIES
1.8V/1.5V Supplies
NC
for fix voltage part
Burst
Continuous
powers up with PP5V_PWRON
SET internally disconnected
300mA output
LB - low battery - NOT USED
2
1
C981
CERM
50V
0.0022uF
10%
402
4
36
5
2
1
Q980
SI3446DV
TSOP
CRITICAL
2
1
C980
CERM
805
6.3V
20%
10UF
2
1
C956
20%
22uF
6.3V
CERM
1206
2
1
C955
22uF
20%
6.3V
CERM
1206
2
1
C952
CERM
6.3V
1206
20%
22uF
2
1
C951
CERM
6.3V
20%
1206
22uF
2
1
R958
1/16W
MF
402
5%
100K
2
1
C950
22pF
402
5%
CERM
50V
2
1
R950
470K
1%
1/16W
MF
402
21
L950
1.0uH-3.5A
SM
CRITICAL
21
XW950
SM
4
17
6
15
14
11
10
1
8
7
5
16
9
2
13
12
3
U950
CRITICAL
LTC3412
TSSOP
2
1
R954
309K
1%
1/16W
MF
402
2
1
R951
402
1%
1/16W
MF
511K
2
1
R952
1%
1/16W
MF
402
422K
2
1
R955
NO STUFF
5%
1/16W
0
402
MF
2
1
R956
5%
1/16W
MF
402
0
2
1
C957
10%
50V
CERM
402
470pF
2
1
R953
402
1/16W
MF
15K
1%
2
1
C954
402
50V
5%
CERM
100pF
2
1
C953
10%
50V
CERM
402
0.001uF
2
1
R957
5%
MF
402
1/16W
5.1M
2
1
C961
402
50V
CERM
10%
0.0022uF
4
36
5
2
1
Q960
TSOP
SI3446DV
CRITICAL
2
1
C960
805
6.3V
CERM
20%
10UF
7
5
4
12
3
8
6
U940
LP3982
MSOP
21
R940
MF
603
0
1/16W
5%
NO STUFF
21
R941
1/16W
0
5%
603
MF
2
1
C940
2.2uF
20%
6.3V
CERM1
603
2
1
C941
402
10V
X7R
20%
0.033uF
2
1
C942
10UF
20%
6.3V
CERM
805
21
L970
10uH
CRITICAL
CDRH4D28C-SM
2
1
R970
1%
100K
1/16W
MF
402
2
1
R971
49.9K
402
MF
1/16W
1%
2
1
C970
50V
CERM
6.8pF
0.5pF%
402
2
1
C972
22uF
6.3V
CERM
20%
1206
2
1
C971
CERM
10UF
20%
6.3V
805
1
7
9
10
4
2
6
3
5
8
U970
TPS62050
MSOP
CRITICAL
1039
051-6532
03
_PP1V5_PWRON_REG
_PPVIN_1V5PWRON
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
1V5PWRON_SW
1V2PWRON_VFB_DIV
_PP1V8_RUN_LDO
1V8RUN_SHDN_L
MIN_NECK_WIDTH=8 mil
1V8RUN_CC
MIN_LINE_WIDTH=8 mil
1V8RUN_PGOOD
1V2PWRON_RUNSS
1V2PWRON_SGND
VOLTAGE=0V
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=10 mil
_PP3V3_PWRON_1V8RUN
1V2PWRON_RT
1V2PWRON_ITH
1V2PWRON_MODE
_PP1V5_PWRON_1V5RUN
1V5RUN_EN
_PP1V5_RUN_FET
1V2PWRON_ITH_RC
1V2PWRON_VFB
1V2PWRON_PGOOD
_PP1V2_PWRON_1V2RUN
1V2RUN_EN
_PP1V2_RUN_FET
_PP1V2_PWRON_REG
1V2PWRON_SW
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
_PP2V5_PWRON_1V8RUN
PPVIN_1V8RUN
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=20 mil
_PPVIN_1V2PWRON
1V5PWRON_VFB_DIV
5 5
5
14 14
5
5
14
5
5
14
5
5
5
5
Preliminary
Page 10
GND
FLT
POWERGOOD CT
REF
REG5V_IN
STBY2
STBY1
TRIP1
TRIP2
LH2 LH1
OUT1_UOUT2_U
LL1LL2
OUT2_D OUT1_D
OUTGND1OUTGND2
FB2 FB1
INV1INV2
SOFTSTART1SOFTSTART2
PWM/SKIP
VCC
VREF55V_STBY
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
DIODE WILL ENSURE DCDC_EN_L IS QUICKLY DISCHARGED DURING SHUT-DOWN
(GND)
5V START TO TURN ON ~12.5MS AFTER DCDC_EN_L
3V START TO TURN ON ~25MS AFTER DCDC_EN_L
(PP5V_PWRON)
is 10% necessary?
another 0.1uF needed?
POWERDOWN DELAY IS AROUND 4MS-15.6MS
3.3V/5V REGULATOR
(GND)
>2V = SKIP
3.3V/5V MAIN SUPPLY
<0.5V = PWM
4
3 6
5
2
1
Q1007
CRITICAL
TSOP
SI3443DV
21
C1009
402
10%
0.0022uF
50V
CERM
22 24
23 25
10
9
13
3
21
84
12
20 26
17
19
29
27
18 28
16 30
15
1
7
11
14
2
5
6
U1000
CRITICAL
TSOP
TPS5120
2
1
C1050
0.1uF
CERM
20%
25V
603
2 1
R1050
402
MF
1/16W
5%
10
2
1
C1051
10V
20%
4.7UF
CERM
1206
3
1
D1030
SOT23
30V-200MA
3
1
D1035
30V-200MA
SOT23
2
1
D1031
SM
MBR0540
2
1
D1036
MBR0540
SM
21
R1031
3.3
5%
MF
402
1/16W
2
1
C1031
20%
0.1uF
10V
CERM
402
21
R1035
5%
1/16W
MF
402
3.3
2
1
C1035
402
20%
CERM
10V
0.1uF
2
1
C1052
CERM
0.01uF
402
20%
16V
2
1
R1053
1/16W
402
MF
1%
15K
2
1
C1053
16V
0.01uF
20%
CERM
402
2
1
C1065
CERM
1206
25V
20%
4.7uF
2
1
C1066
1206
CERM
25V
20%
4.7uF
2
1
C1067
1206
CERM
25V
20%
4.7uF
2
1
C1062
4.7uF
CERM
20%
25V
1206
2
1
C1061
4.7uF
20%
25V
CERM
1206
2
1
C1060
1206
CERM
25V
20%
4.7uF
2
1
C1063
CERM
402
50V
0.001uF
10%
NO STUFF
2
1
C1068
50V
402
CERM
10%
0.001uF
NO STUFF
21
L1060
CRITICAL
4.7UH
IHLP-5050
2
1
C1077
22uF
6.3V
CERM
1206
20%
2
1
C1076
1206
6.3V
20%
CERM
22uF
2
1
C1075
6.3V
20%
330uF
POLY
CASE-D
CRITICAL
2
1
C1054
10%
25V
CERM
402
0.0047uF
2
1
R1073
20.5K
402
MF
1/16W
1%
21
L1065
SM1
10uH
CRITICAL
2
1
R1081
10K
1%
402
MF
1/16W
2
1
C1081
CERM
50V
0.001uF
402
10%
2
1
C1087
20%
6.3V
330uF
POLY
CASE-D
CRITICAL
2 1
XW1003
SM
2
1
C1086
CERM
20%
22uF
6.3V
1206
2
1
C1085
1206
CERM
20%
22uF
6.3V
2
1
R1083
34.8K
1%
402
MF
1/16W
2
1
R1080
100K
1%
MF
402
1/16W
2
1
C1058
10%
25V
CERM
402
0.0047uF
2
1
C1057
402
10V
20%
0.1uF
CERM
2
1
C1056
5%
47pF
402
CERM
50V
2
1
C1055
0.1uF
CERM
402
10V
20%
2
1
C1059
CERM
25V
5%
402
220pF
2
1
D1060
SM
MBRS140T3
1
2
R1036
MF
0
5%
1/16W
402
12
C1080
5%
100pF
402
CERM
50V
12
R1082
5%
1/16W
MF
10K
402
12
C1082
10%
16V
CERM
0.01uF
402
21
R1033
5%
1/16W
402
MF
100K
3
2
4
1
7
6
5
8
Q1065
CRITICAL
SI4816DY
SOI
2
1
R1032
0
MF
5%
402
1/16W
2
1
C1071
50V
10%
402
0.001uF
CERM
2
1
R1071
17.4K
MF
402
1%
1/16W
2
1
R1070
MF
1%
402
1/16W
100K
21
C1070
47pF
CERM
50V
402
5%
21
C1072
CERM
0.01uF
16V
10%
402
21
R1072
402
5%
MF
10K
1/16W
2
1
C1074
100uF
6.3V
20%
TANT
CASE-B2
CRITICAL
NO STUFF
2
1
C1013
CRITICAL
CASE-B2
6.3V
TANT
100uF
20%
2
1
C1012
CERM
20%
6.3V
805
10UF
2
1
C1003
20%
402
16V
CERM
0.01uF
2
1
C1001
CRITICAL
CASE-B-3528
POLY
20%
100uF
6.3V
2
1
C1004
CRITICAL
CASE-B-3528
POLY
6.3V
20%
100uF
4
3 6
5
2
1
Q1003
CRITICAL
TSOP
SI3443DV
2
1
C1011
CERM
20%
6.3V
805
10uF
2
1
C1005
0.1uF
10V
402
CERM
20%
4
3 6
5
2
1
Q1004
CRITICAL
SI3443DV
TSOP
2
1
C1006
CERM
20%
6.3V
805
10UF
3 2 1
4
8 7 6 5
Q1060
SO-8
CRITICAL
IRF7821
3 2 1
4
8 7 6 5
Q1061
SO-8
CRITICAL
SI4336DY
2
1
R1052
11K
MF
402
1/16W
1%
03
051-6532
10310
_PP5V_PWRON_REG
5VPWRON_INV
5V3VPWRON_CT
3V3PWRON_SS
MIN_LINE_WIDTH=15 mil
GND_5V3V
VOLTAGE=0V
MIN_NECK_WIDTH=10 mil
5V3VPWRON_PGOOD
3V3RUN_EN_L
_PP3V3_PWRON_3V3RUN
_PP3V3_RUN_FET
5VRUN_EN_L
_PP5V_PWRON_5VRUN
5VRUNHD_EN_L
_PP5V_RUN_FET
_PP5V_RUN_HD_FET
5VPWRON_FB
VOLTAGE=5V
PP5V_5V3V_VREF5
MIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=15 mil
MIN_NECK_WIDTH=10 mil
PPVCC_ALL_3V5V
VOLTAGE=18.5V
5VPWRON_TRIP
3V3PWRON_LH
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=25 mil
3V3PWRON_TRIP
5VPWRON_SS
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=25 mil
5VPWRON_OUT_U
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=25 mil
3V3PWRON_OUT_D
SYS_SLEEP
3V3PWRON_LL
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=25 mil
5VPWRON_FB_RC
3V3PWRON_FB_RC
3V3PWRON_INV_RC
5VPWRON_LH
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=25 mil
5V3VPWRON_SKIP
5V3VPWRON_FLT
5VPWRON_LL
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=25 mil
MIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=10 mil
5VPWRON_BOOST_ESR
_PP3V3_PWRON_REG
3V3PWRON_FB
3V3PWRON_INV
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=25 mil
3V3PWRON_SW
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
3V3PWRON_OUT_U
5V3VPWRON_REF
5VPWRON_INV_RC
MIN_LINE_WIDTH=20 mil
3V3PWRON_BOOST_ESR
MIN_NECK_WIDTH=10 mil
_PPVIN_5V3VPWRON
3V3_STBY_L
5V_STBY_L
MIN_NECK_WIDTH=10 mil
5VPWRON_OUT_D
MIN_LINE_WIDTH=25 mil
5VPWRON_SW
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
25 11
5
14
14
5
5
14
5
14
5
5
5
5
5
14 14
Preliminary
Page 11
GND
FLT
POWERGOOD CT
REF
REG5V_IN
STBY2
STBY1
TRIP1
TRIP2
LH2
LH1
OUT1_U
OUT2_U
LL1
LL2
OUT2_D
OUT1_D
OUTGND1OUTGND2
FB2 FB1
INV1INV2
SOFTSTART1SOFTSTART2
PWM/SKIP
VCC
VREF55V_STBY
VTAP
IN OUT
SENSE
GND
FDBK
ERR
LP2951
SHUT
SHUT
PLUS5VTAP
LP2951
ERR
FDBK
GND
SENSE
OUTIN
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
1.328V
Bootstrap system from adapter or battery
PP3V3_ALL LDO
PP4V6_ALL Generation
NC
NC
NC NC
> 2V = SKIP
(GND)(GND)
< 0.5V = PWM
2.5V/NBVCORE/PMU SUPPLIES
2.5V/NBVCORE MAIN SUPPLIES
2
1
C1117
1206
CERM
25V
20%
4.7uF
2
1
C1116
4.7uF
20%
25V
CERM
1206
2
1
C1115
20%
25V
CERM
1206
4.7uF
2
1
C1148
20%
6.3V
POLY
CASE-D
330uF
CRITICAL
2
1
C1125
330uF
POLY
CASE-D
20%
6.3V
CRITICAL
2
1
C1126
1206
6.3V
22uF
20%
CERM
2
1
C1127
CERM
20%
22uF
6.3V
1206
2
1
C1141
0.001uF
50V
402
CERM
10%
2
1
R1141
17.4K
1%
402
MF
1/16W
2 1
XW1104
SM
21
L1110
CRITICAL
4.7UH
IHLP-5050
2
1
R1140
100K
402
MF
1/16W
1%
2
1
R1143
51.1K
MF
402
1%
1/16W
2
1
R1142
10K
402
MF
1/16W
1%
2
1
C1142
16V
0.01uF
402
10%
CERM
2
1
C1140
47pF
CERM
402
50V
5%
3
1
D1135
30V-200MA
SOT23
2
1
C1103
16V
0.01uF
CERM
20%
402
21
R1136
402
0
5%
MF
1/16W
2
1
R1103
402
MF
1%
1/16W
11K
2
1
C1100
0.1uF
20%
25V
CERM
603
2 1
R1100
402
1/16W
MF
5%
10
2
1
C1101
20%
4.7UF
1206
10V
CERM
2
1
R1102
402
1/16W
MF
1%
20K
2
1
C1102
0.01uF
16V
402
CERM
20%
21
R1132
1/16W
402
MF
5%
0
2
1
D1130
MBR0540
SM
2
1
C1112
4.7uF
1206
CERM
25V
20%
2
1
C1118
0.001uF
10%
50V
CERM
402
NO STUFF
2
1
C1135
0.1uF
10V
402
CERM
20%
21
R1135
1.8
1/16W
5%
MF
402
2
1
C1108
0.0047uF
10%
25V
CERM
402
2
1
C1107
0.1uF
20%
10V
CERM
402
2
1
C1106
402-1
68pF
5%
50V
CERM
2
1
D1136
MBR0540
SM
2
1
C1105
0.1uF
20%
10V
402
CERM
22 24
23 25
10
9
13
3
21
84
12
20 26
17
19
29
27
18 28
16 30
15
1
7
11
14
2
5
6
U1100
TSOP
TPS5120
CRITICAL
2
1
D1131
SM
MBR0540
2
1
C1104
402
CERM
25V
10%
0.0047uF
2
1
C1131
402
0.1uF
20%
10V
CERM
21
R1131
1.8
1/16W
MF
5%
402
2
1
C1113
0.001uF
10%
50V
CERM
402
NO STUFF
3 2 1
4
5
Q1115
SO-8-PWRPK
SI7392DP
CRITICAL
2
1
C1120
402
150pF
5%
50V
CERM
2
1
R1122
5.36K
402
MF
1/16W
1%
2
1
C1122
0.01uF
10%
16V
CERM
402
2
1
C1111
CERM
1206
4.7uF
25V
20%
2
1
C1110
25V
CERM
1206
20%
4.7uF
21
L1115
IHLP
CRITICAL
2.2uH-16A
2
1
R1120
51.1K
1%
402
MF
1/16W
2
1
R1121
402
MF
1%
1/16W
17.4K
2
1
C1121
402
CERM
50V
10%
680pF
2
1
C1145
1206
6.3V
20%
CERM
22uF
2
1
R1123
1%
402
MF
1/16W
90.9K
2
1
C1146
1206
6.3V
22uF
CERM
20%
2
1
C1147
CASE-D
POLY
330uF
6.3V
20%
CRITICAL
2
1
C1109
402
CERM
25V
220pF
5%
2
1
D1110
SM
MBRS140T3
2
1
D1115
B340LB
SMB
21
R1133
402
MF
1/16W
100K
5%
7
6
3
2
4
8
5
1
Q1190
SI6467BDQ
TSSOP
CRITICAL
2
1
C1190
10UF
20%
CERM
6.3V
805
21
C1192
0.0022uF
402
10%
50V
CERM
2
1
R1171
MF
5%
1/16W
603
1
6
3
2
18
4
7
5
U1170
CRITICAL
SOI-3.3V
2
1
C1171
805
CERM
20%
10uF
6.3V
21
D1164
SM
MBR0520LT
NO STUFF
21
D1163
NO STUFF
SM
MBR0520LT
2
1
C1170
0.1uF
402
CERM
10V
20%
2
1
R1164
1
603
MF
1/16W
5%
2
1
R1162
402
MF
1/16W
1%
294K
2
1
C1162
402
CERM
50V
10%
470pF
2
1
C1164
805
CERM
10V
20%
2.2uF
2
1
R1163
402
MF
1/16W
1%
100K
2
1
C1161
402
CERM
10V
20%
0.1uF
3
2
6
18
4
7
5
U1160
CRITICAL
SOI
2
1
C1160
603
25V
0.1uF
20%
CERM
21
R1166
1210
137
1%
1/4W
FF
2
1
D1162
SM
MBR0540
3
1
D1161
1N914
SOT23
21
D1160
SM
MBR0540
3
1
D1165
SOT23
1N5228B
21
R1161
0
5%
1/10W
FF
805
321
4
8765
Q1110
SO-8
CRITICAL
IRF7821
2
1
C1193
100uF
20%
6.3V
POLY
CASE-B-3528
321
4
8765
Q1111
SO-8
CRITICAL
SI4336DY
3 2 1
4
8 7 6 5
Q1116
SO-8
CRITICAL
SI4336DY
10311
03
051-6532
2V5_ITRIP
2V5PWRON_SW
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=25 mil
2V5_LO_GATE
NBVCORE_LO_GATE
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=25 mil
SYS_SLEEP
2V5_NBVCORE_PWM
MIN_LINE_WIDTH=25 mil
NBVCORE_HI_GATE
MIN_NECK_WIDTH=10 mil
_PPVIN_2V5_NBVCORE_PWRON
MIN_NECK_WIDTH=10 mil
2V5_NBVCORE_VCC
MIN_LINE_WIDTH=10 mil
VOLTAGE=18.5V
2V5NBVCORE_STBY_L
2V5_NBVCORE_FLT
2V5_NBVCORE_CT
2V5_NBVCORE_REF
2V5_SS
2V5_INV
2V5_FB
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=25 mil
2V5_BST_HI
NBVCORE_ITRIP
MIN_LINE_WIDTH=25 mil
NBVCORE_BST_HI
MIN_NECK_WIDTH=10 mil
2V5_NBVCORE_VREF5
MIN_NECK_WIDTH=10 mil
VOLTAGE=5V
MIN_LINE_WIDTH=20 mil
VOLTAGE=18.5V
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=10 mil
PP18V5_ALL_4V85ALL
PPBATT_ALL_FUSEA_ZENER
VOLTAGE=16.3V
MIN_LINE_WIDTH=10 mil
MIN_NECK_WIDTH=10 mil
MIN_NECK_WIDTH=10 mil
VOLTAGE=18.5V
MIN_LINE_WIDTH=10 mil
PP18V5_ALL_DCIN_R
MIN_LINE_WIDTH=15 mil
4V85ALL_ESR
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
2V5_BST_LO
NBVCORE_BOOST_ESR
MIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=10 mil
2V5_FB_RC
2V5_INV_RC
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=15 mil
3V3ALL_ESR4V85ALL_FB
MIN_NECK_WIDTH=8 mil
MIN_LINE_WIDTH=8 mil
MIN_LINE_WIDTH=8 mil
MIN_NECK_WIDTH=8 mil
3V3ALL_FB
PP4V85_ALL_LDO
MIN_LINE_WIDTH=15 mil
VOLTAGE=4.85V
MIN_NECK_WIDTH=10 mil
PP18V5_ALL_DCIN
_PP5V_PWRON_3V3ALL
PP4V6_ALL
VOLTAGE=4.6V
MIN_LINE_WIDTH=15 mil
MIN_NECK_WIDTH=10 mil
_PP3V3_ALL_LDO
PPBBATT_BOOST_OUT
PPBATT_ALL_FUSEA
_PP2V5_PWRON_REG
MIN_LINE_WIDTH=20 mil
2V5_BOOST_ESR
MIN_NECK_WIDTH=10 mil
2V5RUN_EN_L
_PP2V5_RUN_FET
_PP2V5_PWRON_2V5RUN
NBVCORE_BST_LO
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
2V5_HI_GATE
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=25 mil
NBVCORE_FB_RC
NBVCORE_SS
NBVCORE_FB
PP5V_PWRON
2V5_NBVCORE_PGOOD
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=15 mil
VOLTAGE=0V
GND_2V5_NBVCORE
MIN_LINE_WIDTH=25 mil
NBVCORE_SW
MIN_NECK_WIDTH=10 mil
_PPVCORE_NB_REG
NBVCORE_INV_RC
NBVCORE_INV2
25 10 7 5
5
14
6
5
5
17
8
5
14
5
5
6
14
5
Preliminary
Page 12
S
D
G
VESTA MISC
1 OF 3
PVDDDVDD
AVDDL
AVDD
GND
AGND
OVDD
REGSUP1
REGSEN1
REGCTL1
REGSUP2
REGSEN2
REGCTL2
2.5V_EN
NC
DNC
DNC
DNC
NC
TDO
TCK
TMS
TRST*
TDI
RESET*
PVINSVIN
SHDN/RT
SYNC/MODE
SW
VFB
ITH
PGOOD
PGND SGND
G
D
S
G
D
S
GND
VOUT
VIN
NOISE
CONT
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ON/OFF
GND
VOUT
FB
VIN
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
DRAWING
N9/N10
Ethernet LowPwr
Signal aliases required by this page:
(Repeater mode on portables)
whenever port power is disabled.
Pulse Mode
Vout = 2.5V @ 150 mA
Port Power Switch
regulator will be in continuous mode.
3.3V Regulator
- VESTA1V2_BURST / VESTA1V2_PULSE
regulator. If both options are off the
Vout = 0.8V * (1 + (R2 / R1))
Controls operating mode of Vesta 1.2V
1.2V Regulator
<R1>
<R2>
Vout = 1.199V @ 1.2 A
Page Notes
Power aliases required by this page:
machine is running or
when asleep on AC.
Ethernet portion in low power mode
- _PP12V_RUN_FW (backup PHY power)
2.5V LDO
NC
NC
N5/N6
Schmitt trigger
L6/M6
Reset RC values per
To keep Vesta from being held
Broadcom recommendation
NOTE: Reset GPIO is active HIGH
in reset when system is off
(NONE)
Continuous
Mode
Vout = 3.3V @ 500mA
L9/M9
Burst Mode
- _PPBUS_FW (system supply for bus power)
BOM options provided by this page:
Vesta Core / Misc
Master: Link
Enables port power when
2
1
C1210
20%
10V
CERM
402
0.1uF
2
1
C1211
0.1uF
402
CERM
10V
20%
2
1
C1212
402
CERM
10V
20%
0.1uF
2
1
C1213
20%
10V
CERM
402
0.1uF
2
1
C1203
0.1uF
CERM
402
10V
20%
2
1
C1202
0.1uF
402
CERM
10V
20%
2
1
C1201
0.1uF
402
CERM
20%
10V
2
1
C1200
20%
10V
CERM
402
0.1uF
2
1
C1222
20%
10V
CERM
402
0.1uF
2
1
C1225
10V
20%
CERM
402
0.1uF
2
1
C1221
20%
10V
CERM
402
0.1uF
2
1
C1224
0.1uF
20%
10V
CERM
402
2
1
C1231
0.1uF
402
CERM
10V
20%
2
1
C1230
20%
10V
CERM
402
0.1uF
2
1
C1220
20%
10V
CERM
402
0.1uF
2
1
C1223
0.1uF
20%
10V
CERM
402
2
1
C1243
0.1uF
402
CERM
10V
20%
2
1
C1242
20%
10V
CERM
402
0.1uF
2
1
C1241
10V
0.1uF
402
CERM
20%
2
1
C1240
0.1uF
402
CERM
10V
20%
2
1
C1250
CERM
10V
1uF
20%
603
2
1
3
Q1250
2N7002
SM
2
1
R1250
5%
1/16W
MF
402
10K
D8
E8
E10
D7
E7
H4
E2
E1
F2
F1
G4
G5
N4
A15
K1
F15
A7
A1
M13
C3
K2
J2
F14
C14
B7B2A2
J1
C15
B15
B1
E9
C9
B9
N10
N9N6N5M9M6L9L6
R12
R3
P11
P10
P5
P4
N8N7M8M7L8
L7
J12
J11
P9P8P7
P6
H12
H11
M3
U8600
OMIT
BCM5462
FBGA-200
2
1
R1251
82K
5%
1/16W
MF
402
2
1
C1208
20%
CERM
10uF
6.3V
805
21
L1200
FERR-EMI-600-OHM
SM
9
2
4
7
1
3
6
8
5
10
U1290
LTC3411
MSOP
CRITICAL
2
1
C1293
100pF
402
CERM
50V
5%
2
1
R1296
402
MF
1/16W
4.99K
1%
2
1
C1294
402
0.0033uF
10%
50V
CERM
21
L1290
2.2uH
SM1
CRITICAL
2
1
C1292
5%
22pF
402
50V
CERM
2
1
R1297
1%
MF
4.99K
1/16W
402
2
1
R1298
1%
1/16W
MF
402
10K
2
1
C1295
CERM
22uF
20%
1206
6.3V
2
1
C1291
CERM
1uF
10V
603
20%
21
R1290
10
1/16W
5%
MF
402
2
1
C1290
6.3V
CERM
20%
10uF
805
2
1
R1295
1/16W
MF
402
324K
1%
2
1
R1294
5%
1M
402
MF
1/16W
2
1
R1291
1/16W
5%
1M
402
MF
2
1
R1293
VESTA1V2_PULSE
10K
1/16W
5%
402
MF
2
1
R1292
VESTA1V2_BURST
5%
10K
402
MF
1/16W
21
XW1290
SM
2
1
C1281
20%
0.01uF
402
CERM
16V
2
1
C1280
1uF
603
10V
20%
CERM
2
1
C1282
20%
10uF
805
CERM
6.3V
2
1
R1266
402
1/16W
MF
330K
5%
2
1
C1265
402
CERM
16V
20%
0.01uF
2
1
R1265
5%
MF
402
1/16W
470K
43
DP1260
SOT-363
BAS16TW
5 2
DP1260
SOT-363
BAS16TW
61
DP1260
BAS16TW
SOT-363
21
R1261
402
MF
1/16W
5%
10K
PP3V3_RUN
2
1
R1260
100K
402
5%
1/16W
MF
4
5
3
Q1260
SOT-363
2N7002DW
1
2
6
Q1260
2N7002DW
SOT-363
2
1
R1262
5%
MF
402
1/16W
100K
2
1
R1263
402
MF
5%
1/16W
470K
51
4
2
3
U1280
CRITICAL
SOT-25A
MM1572FN
21
D1265
B340B
CRITICAL
SMB
3
2
1
4
8
7
6
5
Q1265
NDS9407
SOI
CRITICAL
21
F1265
1.5A-24V
SM
3
2
1
D1270
SC-59
SDM20E40C
8
7
56
4
U1270
LM2594
SM
CRITICAL
2
1
C1270
10uF
50V
2320
N20P20%
CERM
2
1
C1271
CRITICAL
CASE-B-3528
POLY
20%
100uF
6.3V
21
L1270
CRITICAL
PLFC
100uH-1A
2
1
D1271
MBRS140T3
SM
10312
03
051-6532
TITLE=FIZZY
ABBREV=DRAWING
MIN_LINE_WIDTH=20 mil
PP3V3_VESTA
VOLTAGE=3.3V
MIN_NECK_WIDTH=10 mil
FWPWR_RUN
VESTA_RESET_L
PP3V3_VESTA
PP2V5_VESTA
_PPBUS_FW
FWPWR_EN_L
MIN_LINE_WIDTH=8 mil
MIN_NECK_WIDTH=8 mil
MIN_LINE_WIDTH=15 mil
MIN_NECK_WIDTH=10 mil
VOLTAGE=33V
PPVIN_FWLM2594
VESTA1V2_ITH_RC
_PPFW_PHY
_PP1V2_ENETFW
_PP3V3_FW
MIN_LINE_WIDTH=20 mil
PPVOUT_VESTA1V2
VOLTAGE=3.3V
MIN_NECK_WIDTH=10 mil
ENETFW_RESET
TP_VESTA_REGSEN2
TP_VESTA_REGSUP2
TP_VESTA_REGSEN1
TP_VESTA_REGSUP1
TP_VESTA_REGCTL1
TP_VESTA_2_5V_EN
TP_VESTA_DNC_B9
TP_VESTA_DNC_E9
PP1V2_VESTA
JTAG_VESTA_TRST_L
PP3V3_VESTA
_PP2V5_ENETFW
_PPBU_RUN_FW
PPFW_COMBINED
SMU_ACIN
_PPFW_PORT1
VESTA1V2_SW
MIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=10 mil
_PP3V3_ENET
FWPWR_ACIN
PP3V3_VESTA
MIN_NECK_WIDTH=10 mil
VOLTAGE=0V
VESTA1V2_SGND
MIN_LINE_WIDTH=15 mil
_PP3V3_ENETFW
VESTA1V2_ITH
VESTA1V2_VFB
MIN_LINE_WIDTH=20 mil
FWLM2594_VOUT
MIN_NECK_WIDTH=10 mil
VOLTAGE=1.2V
PP1V2_VESTA
MIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=10 mil
_PPFW_PORT2
MIN_LINE_WIDTH=25 mil
PPFW_COMBINED
VOLTAGE=33V
MIN_NECK_WIDTH=10 mil
PP3V3_VESTA
VESTA_ENET_LOWPWR
FWPWR_EN_L_DIV
MIN_LINE_WIDTH=8 mil
MIN_NECK_WIDTH=8 mil
PP3V3_VESTA
VOLTAGE=2.5V
PP2V5_VESTA
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=20 mil
VESTA2V5_NOISE
MIN_NECK_WIDTH=8 mil
MIN_LINE_WIDTH=8 mil
FWPWR_PWRON
VESTA1V2_MODE
VESTA1V2_RT
PP1V2_VESTA_AVDDL
MIN_LINE_WIDTH=20 mil
VOLTAGE=1.2V
MIN_NECK_WIDTH=10 mil
TP_VESTA_DNC_C9
JTAG_VESTA_TMS
JTAG_VESTA_TCK
JTAG_VESTA_TDO
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=25 mil
VOLTAGE=19V
PPBUS_FW_FUSE
FWPWR_EN
PPFW_SWITCH
MIN_NECK_WIDTH=10 mil
VOLTAGE=19V
MIN_LINE_WIDTH=25 mil
TP_VESTA_REGCTL2
JTAG_VESTA_TDI
LAST_MODIFIED=Mon Feb 23 19:03:46 2004
13
57
58
57
8
12
12
12
5
57
54
57
23
12
6
12
54
5
12
7
58
54
12
57
12
58
12
12
54
12
12
14
6
6
6
6
Preliminary
Page 13
P9[7]
P9[6]
P9[5]
P8[7]
P8[6]
P8[5]
P3[7]
P3[6]
P3[5]
P3[4]
P2[6]
P2[7]
P2[4]
P2[5]
P1[4]
P1[3]
P1[2]
P1[1]
P1[0]
P0[4]
P0[0]
P0[2]
P0[3]
P0[1]
P0[7]
P0[6]
P0[5]
P3[3]
P3[2]
P3[1]
P3[0]
P2[3]
P2[2]
P2[1]
P2[0]
P1[5]
P1[6]
P1[7]
PCNVSS
RESET*
XOUT
VREF
XIN
P7[7]
P7[6]
P7[5]
P7[4]
P7[3]
P7[2]
P7[1]
P7[0]
P6[7]
P6[6]
P6[5]
P6[4]
P6[3]
P6[2]
P6[1]
P6[0]
P10[0]
P10[1]
P9[3]
P9[2]
P9[1]
P9[0]
P8[4]
P8[3]
P8[2]
P8[1]
P8[0]
P10[6]
P10[7]
P10[2]
P10[3]
P10[4]
P10[5]
VCC
AVSS
VSS
AVCC
SQW/
OUT
VBAT
SDA
SCL
X1
X2
GND
VCC
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Y
KI1*
NOTE: Pinout matches SMU pinout v1.51.
NOTE: All analog inputs to SMU should have
a 100pF capacitor to the SMU AVSS
signal (GND_SMU_AVSS). None of
Signal aliases required by this page:
- _PPVREF_SMU (SMU AVCC or 2.5V reference)
Page Notes
S = Spare
Y = Primary function
N = Alternate function
CLK3
TA2out
AN00
AN02
AN03
AN01
TXD0
KI3*
S
Keep crystal subcircuit close to SMU.
Y1300’s load capacitance is 12pF
S
S
Y
Y
SDAmm
INT5*
INT4*
Y
AN20
AN06
CTS0*
IOC7
TA2in
AN04
INT2*
CE*
Y
AN27
AN23
AN21
TA3in
AN0
(BUSY)
TB0in
Sin3
Master: Link
System Management Unit
provided on another page.
reference used by monitoring
(NONE)
(NONE)
- _PP3V3_PWRON_SMU
- _PP3V3_ALL_RTC
- _PP3V3_ALL_SMU
ELECTRICAL_CONSTRAINT_SET
BOM options provided by this page:
NOTE: CPU current/voltage monitoring
Real Time Clock
NC
provided on this page. Please.
reuire pull-ups that are not.
RTS0*/
TXD1
CLK1
RTS1*
RXD0
CLK0
RXD1
AN07
AN05
SDA
TA4out
TA1in
AN24
TB1in
NMI*
INT1*
AN25
SCLmm
Y
Y
Y
Y
Y
Y
Y
Y
Sout3
AN1
AN2
AN3
KI0*
KI2*
Y
Y
IOC4
Y
SCL
this page.
TB2in
to ensure missing pull-ups are
review the latest SMU specification
Power aliases required by this page:
IOC6
TA4in
TA3out
(CPU_SENSE_I/CPU_SENSE_V) requires
Caps should connect to GND_SMU_AVSS.
those capacitors are provided on
affect other analog inputs such as
AC adapter ID.
NOTE: Some primary and alternate functions
S
S
TA1out
DIFFERENTIAL_PAIR
System Management Unit
NET_SPACING_TYPE
SMU Pull-ups / pull-down
Server
Y
Desktop
Portable
Y
Y
Y
Y
Y
Y
N
N
Y
Y
S
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
Y
Y
Y
Y
Y
S
Y
S
S
Y
Consumer
S
S
S S
SS
Y Y Y YY
Y
YN
S
YY
Y
Y
Y
Y
Y
YSY
Y
Y
Y
Y
Y
Y
Y
Y
SSN
S
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
YYY
Y
Y
Y
Y
Y
Y
Y
S
Y
Y
Y
Y
S
YYYY
Y
Y
Y
Y
S
Server
N
N
N
Consumer
N
N
N
SS
N
Y
Y
S
S
Y
Y
Y
S
S
Y
Y
N
Y
Y
YY
Y
Y
Y
Y
S
Y
Y
Y
Y
Y
Y
S
Y
Y
Y
Y
Y
S
Y
Y
S
Y
S
Y
Y
Y
Y
Y
S
Y
Y
Y
S
Y
Y
Y
S
Y
Y
Y
Y
Y
YY
Y
Y
Y
Portable
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
S
Y
Y
Y
Y
Y
Y
Y
Y
S
Desktop
Entry Desktop
Entry Desktop
Y
Y
Y
Y
Y
Y
Y
Y Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
S S
N N
Y Y
Y
Y
Y
Y
S
Y
Y
Y Y
Y
Y
Y
Y
Y
Y
S
INT0*
S
Y
Y
Y
Y
Y
Y Y
Y
Y
YYY
Y
AN26
SSYY Y
S
Y
Y
Y
Y
Y
Y
Y
Y
S
Y Y
S
Y
Y
Y
Y
Y
S S
(see aliases below)
N
N
N
Y
Y
YYY
YYY
Y
Y
Y
Y
YYY
YYY
AN22
INT3*
IOC5
Y
Y
Y
Y
Y
Y
Y
Y
S S
IOC3
IOC2
Y
Y
Tower & Server
7.4
7.2
6.0
6.2
6.1
Port
Consumer
2.5
Port
2.6
2.7
Alternate Functions
Portable
0.4
Port
0.5
0.6
1.7
1.6
1.5
7.6
circuit, but be aware that this will
SMU_VREF should be same signal or
100K/10uF RC filter at SMU pins.
21
Y1300
8X4.5MM-SM
10.0000M
CRITICAL
10
12
11
77
13
9
79
80
1
2
3
4
5
7
8
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
40
41
42
43
32
33
34
35
36
37
38
39
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
68
69
70
71
72
73
74
76
59
60
61
62
63
64
65
66
67
6
75
78
U1300
QFP-80
M30280F8
OMIT
2
1
8
3
7
5
6
4
U1301
MSOP
DS1338
PP3V3_PWRON
PP3V3_RUN
PP2V5_PWRON
21
R1399
5%
1/16W
MF
402
NO_SMU_I2C_D
0
3
1
D1310
SOT23
1N914
2
1
C1325
1uF
CERM
6.3V
10%
402
2
1
R1325
10K
5%
MF
1/16W
402
2
1
R1322
100K
5%
1/16W
MF
402
2
1
C1310
20%
0.22uF
402
6.3V
CERM
2
1
C1304
50V
5%
12pF
402
CERM
2
1
C1305
50V
5%
12pF
402
CERM
2
1
R1317
402
1/16W
MF
5%
0
21
R1316
10M
5%
MF
1/16W
402
NO STUFF
2
1
R1327
402
1/16W
MF
5%
10K
21
R1312
100K
5%
1/16W
MF
402
21
R1311
402
MF
1/16W
5%
100K
21
R1313
402
MF
1/16W
5%
100K
21
R1310
100K
5%
1/16W
MF
402
21
R1302
402
MF
1/16W
5%
10K
21
R1300
5%
1/16W
MF
402
10K
12
R1304
5%
1/16W
MF
10K
402
2
1
C1309
10V
20%
CERM
0.1uF
402
2
1
C1308
10V
20%
0.1uF
CERM
402
2
1
C1302
10V
20%
0.1uF
CERM
402
2
1
C1301
10V
20%
0.1uF
CERM
402
2
1
C1300
6.3V
10uF
20%
CERM
805
2
1
C1303
402
CERM
1uF
10%
6.3V
21
R1315
402
MF
1/16W
5%
4.7
21
XW1300
SM
4
1
Y1301
32.768K
SM-1
CRITICAL
051-6532
10313
03
FAN_PWM8
SYS_KBDLED
SYS_DOOR_AJAR_L
SYS_LID_OPEN
SYS_DRIVE_BAY_INT_L
SMU_BATT_DET_L
SYS_POWERFAIL_L
SMU_ACIN
FAN_RPM5
ALS_GAIN_BOOST
FAN_RPM4 ALS1_OUT
FAN_RPM3 ALS0_OUT
FAN_TACH5
SYS_LED_BLUE
FAN_TACH4
SYS_LED_GREEN
FAN_TACH3
SYS_LED_RED
I2C_SMU_CPU_SDA_IN
FAN_PWM6
I2C_SMU_CPU_SCL_IN
FAN_PWM7
CPU_VID<1>
FAN_TACH7
CPU_VID<2>
FAN_TACH8
CPU_VID<0>
FAN_TACH6
SYS_SLOT_PWR
TP_SMU_SPARE_P10_0
SYS_RESET_BUTTON_L
SB_SUSPENDACK_L
NB_SUSPENDACK_L
SMU_WARM_RESET_L
SMU_PWRSEQ_P9_6
SB_STOPXTALS_L
I2C_SMU_CPU_SDA_OUT
FAN_PWM8
I2C_SMU_B_SCL
CPU_VID<3>
CPU_VID<1>
CPU_VID<0>
CPU_VID<2>
I2C_SMU_A_SDA_IN
I2C_SMU_A_SDA_OUT
FAN_TACH4
FAN_RPM3
15 MIL SPACING
SMU_CLK10M_XOUT_R
SMU_PWRSEQ_P9_5
CPU_TEMP
SYS_COLD_RESET_L
SYS_POWER_BUTTON_L
SMU_SUSPENDREQ_L
SB_TO_SMU_INT_L
CLOCK_RESET_L
SMU_SLEEP
SYS_SLEWING_L
I2C_SMU_CPU_SCL_OUT
CPU_HRESET_L
FAN_RPM1
SYS_LED
I2C_SMU_CPU_SDA_IN
FAN_RPM2
SYS_PME_L
TP_SMU_SPARE_P8_3
I2C_SMU_CPU_SCL_IN
FAN_RPM0
I2C_SMU_B_SDA
SMU_BOOT_TXD
SMU_TO_SB_INT_L
FAN_TACH5
FAN_TACH3
FAN_TACH2
SYS_DOOR_AJAR_L
FAN_TACH0
I2C_SMU_E_SCL
I2C_SMU_E_SDA
SMU_PWRSEQ_P1_3
SMU_PWRSEQ_P1_4
SMU_ONEWIRE
FAN_RPM5
I2C_SMU_D_SDA
CPU_SENSE_I
CPU_SENSE_V
SYS_DRIVE_BAY_INT_L
SMU_PWRSEQ_P1_0
SMU_PWRSEQ_P1_1
CPU_BYPASS_L
FAN_RPM4
SMU_PWRSEQ_P1_2
SMU_CHARGE_BATT
I2C_SMU_D_SCL
I2C_SMU_A_SCL_IN
I2C_SMU_A_SCL_OUT
15 MIL SPACING
SMU_CLK10M_XTAL
SMU_CLK10M_XIN
RTC_CLK32K_X2
15 MIL SPACING
I2C_RTC_SDA
I2C_RTC_SCL
15 MIL SPACING
RTC_CLK32K_XTAL
RTC_CLK32K_X1
SMU_CLK10M_XOUT
15 MIL SPACING
FAN_TACH1
SYS_OVERTEMP_L
SYS_POWERFAIL_L
_PPVREF_SMU
SMU_BOOT_CNVSS
_PP3V3_ALL_SMU
SMU_RESET_L
SMU_CLK10M_XOUT
SMU_CLK10M_XOUT_R
SMU_CLK10M_XIN
SMU_BOOT_RXD
SYS_SLEWING_L
SMU_SUSPENDREQ_L
SYS_COLD_RESET_L
SMU_SLEEP
SYS_POWERUP_L
_PP3V3_ALL_SMU
SYS_POWER_BUTTON_L
SYS_PME_L
GND_SMU_AVSS
SMU_BOOT_CE
MAKE_BASE=TRUE
SYS_POWERUP_L
CPU_VID<5>
SMU_BOOT_SCLK
SMU_BOOT_BUSY
CPU_VID<4>
_PP3V3_ALL_SMU
VOLTAGE=3.3V
MIN_LINE_WIDTH=15 mil
MIN_NECK_WIDTH=10 mil
PP3V3_ALL_SMU_AVCC
VOLTAGE=0V
MIN_LINE_WIDTH=15 mil
MIN_NECK_WIDTH=10 mil
GND_SMU_AVSS
_PP3V3_ALL_SMU
_PP3V3_ALL_RTC
RTC_CLK32K_X1
RTC_CLK32K_X2
42
25
42
17
31
23
18
31
18
17
32
18
32
18
12
19
51
16
23
25
48
17
16
19
25
23
51
14
16
16
48
19
14
16
19
16
8
17
17
13
13
13
18
18
31
31
31
16
22
18
31
31
31
13
22
13
22
13
23
28
15
18
23
18
15
18
16
13
13
15
18
18
28
15
15
16
13
16
16
23
22
22
13
13
13
13
23
17
13
31
13
17
13
13 19
13 17
13
7
13
7
13
6
13 19
13
6
5
5
5
13
13
13
13
13
6
23
22
5
14
23
18
13
6
31
13
13
13
18
18
5
13
13
14
32
13
6
13
23
25
5
13
18
27
6
19
13
5
13
13
6
6
6
23
5
5
5
13
6
6
6
14
14
17
13
32
32
13
14
14
27
13
14
8
5
18
18
13
13
18
18
13
13
6
6
13
5
6
5
6
13
13
13
6
13
13
13
5
6
5
6
13
13
16
6
6
16
16
6
5
13
5
5
13
13
Preliminary
Page 14
ALIAS
G
D
S
ALIAS
G
D
S
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
G
D
S
G
D
S
ALIAS
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
TPS5120 needs a pull-up stronger than 82.5K
ACTIVE-HIGH, OUTPUT, PUSH-PULL
ACTIVE-HIGH, OUTPUT, PUSH-PULL
ACTIVE-LOW, OUTPUT, PUSH-PULL
ACTIVE-HIGH, OUTPUT/INPUT, OPEN-COLLECTOR
100K pull-up to 3.3V_ALL on pg 13
ACTIVE-LOW, OUTPUT, PUSH-PULL
ACTIVE-LOW, OUTPUT, PUSH-PULL
POWER-UP
ACTIVE-HIGH, OUTPUT/INPUT, OPEN-COLLECTOR
SHUT-DOWN
SLEEP
WAKE
Power Sequencing
Used to see if last rail is up
ANALOG INPUT, SENSE > 1.7V
21
R1411
1/16W
0
402
MF
5%
21
R1420
402
1/16W
MF
5%
100K
21
R1421
100K
402
MF
1/16W
5%
21
R1422
5%
1/16W
MF
402
100K
21
R1430
5%
MF
402
0
1/16W
2
1
R1435
5%
1/16W
MF
100K
402
4
5
3
Q1435
2N7002DW
SOT-363
PP5V_RUN
21
R1436
5%
1/16W
MF
402
100K
21
R1437
402
MF
1/16W
100K
5%
21
R1440
5%
MF
100K
1/16W
402
21
R1441
5%
MF
402
100K
1/16W
21
R1450
0
1/16W
MF
402
5%
21
R1451
0
5%
MF
402
1/16W
PP5V_RUN
2
1
R1465
5%
1/16W
MF
402
100K
1
2
6
Q1435
2N7002DW
SOT-363
21
R1466
5%
1/16W
MF
402
100K
21
R1467
5%
1/16W
MF
402
0
2
1
R1449
MF
1/16W
0
5%
402
2
1
R1459
5%
0
1/16W
402
MF
21
XW1470
SM
21
R1469
402
MF
1/16W
5%
0
2
1
R1458
1/16W
402
5%
MF
100K
2
1
R1448
100K
5%
1/16W
MF
402
PP3V3_RUN
PP3V3_RUN
1
2
R1412
100K
1/16W
5%
MF
402
2
1
R1401
5%
MF
402
68K
1/16W
PP3V3_ALL
1
2
6
Q1400
SOT-363
2N7002DW
4
5
3
Q1400
SOT-363
2N7002DW
2
1
R1429
MF
100K
1/16W
5%
402
PP5V_PWRON
21
R1402
5%
0
1/16W
MF
402
21
R1403
0
1/16W
5%
MF
402
21
R1400
402
MF
5%
1/16W
0
21
R1410
5%
MF
402
0
1/16W
14 103
03
051-6532
SYS_POWERUP_L_R
5VRUNHD_EN_L
SYS_POWERUP_L
GPUVCORE_SHDN_L
CPU_AVDD_EN
GPUVDD15_EN
3V3RUN_EN_L
1V5RUN_EN
SMU_PWRSEQ_P1_3
SMU_PWRSEQ_P9_6
MAKE_BASE=TRUE
SYS_PWRSEQ_7
PP1V8_GPU_PVDD
GPUVCORE_PGOOD
CPUVCORE_SHDN_L
1V8RUN_SHDN_L
GPUPVDD_EN
VCORE_SWITCHING
1V2RUN_EN
1V8RUN_PGOOD
2V5RUN_EN_L
3V3_STBY_L
2V5NBVCORE_STBY_L
SMU_PWRSEQ_P1_4
2V5_NBVCORE_PGOOD
SMU_PWRSEQ_P9_5
SYS_PWRSEQ_6_L
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SYS_PWRSEQ_6_LS5
MAKE_BASE=TRUE
SYS_PWRSEQ_5
5V3VPWRON_PGOOD
5VRUN_EN_L
MAKE_BASE=TRUE
SYS_PWRSEQ_1
SMU_PWRSEQ_P1_2
MAKE_BASE=TRUE
SYS_PWRSEQ_4
PWRON_REGS_PGOOD
MAKE_BASE=TRUE
SYS_PWRSEQ_3_LS5
SYS_PWRSEQ_3_L
MAKE_BASE=TRUE
SMU_PWRSEQ_P1_0
SYS_PWRSEQ_2_L
SYS_PWRSEQ_2
MAKE_BASE=TRUE
SMU_PWRSEQ_P1_1
SYS_POWERUP
FWPWR_PWRON
5V_STBY_L
13
10
6
38
29
39
10
9
13
13 40
38
31
9
40
31
9
9
11
10
11
13
11
13
10
10
13
13
13
6
12
10
Preliminary
Page 15
GND
DXN3
DXN4
DXP4
DXP3
DXP1
DXN1
DXP2
DXN2
ADD0
ADD1
ALERT*
STBY*
SMBDATA
SMBCLK
VCC
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
ELECTRICAL_CONSTRAINT_SET
Fan 1
Fan 2
Thermal Sensor / Fans
(NONE)
- _PP5V_PWRON_FAN
thermal sensors for each of the
available remote sensor locations.
- THERM_x / THERM_xB
BOM options provided by this page:
Signal aliases required by this page:
- _PP3V3_PWRON_THERM
Page Notes
Power aliases required by this page:
DIFFERENTIAL_PAIR
(PWM)
Remote 3
Remote 3 (Backup)
Remote 2 (Backup)
(GND)
(TACH)
(PWR)
GPU Thermal Diode
Remote 4
Addr=0x30(Wr)/0x31(Rd)
(GND)
(PWM)
Remote 1 (Backup)
minimizing stubs.
to two different sensors. These
Sensor Selection
Remote 1
Place each cap close to associated transistor
Remote Temperature Sensors
Selects between primary and backup
NET_SPACING_TYPE
resistors should be close to MAX1668,
First 3 MAX1668 inputs can connect
MAX1989 Thermal Sensor
(TACH)
(PWR)
Remote 2
Place close to CPU_VCORE
Place close to 5V/3.3V
Place close to U3Lite
Place close to Shasta/GPU_Vcore
Place close to bottom RAM
Place close to CPU
2
3
1
Q1510
THERM_1
2N3904
SM
2
1
C1510
20%
50V
CERM
402
THERM_1
0.001uF
2
1
C1520
402
0.001uF
CERM
50V
20%
THERM_2
2
3
1
Q1520
SM
2N3904
THERM_2
2
1
C1515
CERM
50V
20%
402
0.001uF
THERM_1B
2
3
1
Q1515
SM
2N3904
THERM_1B
2
1
C1525
402
0.001uF
CERM
50V
20%
THERM_2B
2
3
1
Q1525
SM
2N3904
THERM_2B
21
R1510
THERM_1
0
402
MF
1/16W
5%
21
R1515
THERM_1B
5%
1/16W
MF
402
0
21
R1511
5%
MF
402
0
THERM_1
1/16W
21
R1516
402
1/16W
5%
0
MF
THERM_1B
21
R1520
5%
1/16W
MF
402
0
THERM_2
21
R1525
0
402
MF
1/16W
5%
THERM_2B
21
R1526
5%
1/16W
MF
402
0
THERM_2B
21
R1521
THERM_2
0
402
MF
1/16W
5%
2
1
R1592
10K
402
MF
1/16W
5%
2
1
C1592
20%
10V
CERM
1206
4.7uF
9
15
13
14
16
7
5
3
1
8
6
4
2
12
10
11
U1500
MAX1668
QSOP
CRITICAL
2
1
C1505
NO STUFF
20%
50V
CERM
402
0.001uF
2
1
C1507
0.001uF
402
CERM
50V
20%
NO STUFF
2
1
C1506
0.001uF
402
CERM
50V
20%
NO STUFF
2
1
C1508
NO STUFF
20%
50V
CERM
402
0.001uF
2
1
C1500
402
0.1uF
CERM
10V
20%
21
R1500
402
MF
1/16W
5%
200
2
1
C1501
50V
20%
CERM
402
0.001uF
NO STUFF
2
1
C1502
0.001uF
402
CERM
50V
20%
NO STUFF
2
1
C1503
NO STUFF
0.001uF
402
CERM
50V
20%
2
1
C1504
0.001uF
402
CERM
50V
20%
NO STUFF
21
R1535
THERM_3B
5%
1/16W
MF
402
0
21
R1536
THERM_3B
0
402
MF
1/16W
5%
21
R1530
THERM_3
0
402
MF
1/16W
5%
21
R1531
THERM_3
5%
1/16W
MF
402
0
2
1
C1535
THERM_3B
20%
50V
CERM
0.001uF
402
2
3
1
Q1535
SM
THERM_3B
2N3904
2
1
C1530
402
0.001uF
CERM
50V
20%
THERM_3
2
3
1
Q1530
SM
2N3904
THERM_3
2
1
C1540
20%
50V
CERM
0.001uF
402
4
3
2
1
6
5
J1592
SM-2MT
CRITICAL
4
3
2
1
6
5
J1591
SM-2MT
CRITICAL
2
1
R1591
5%
1/16W
MF
10K
402
2
1
C1591
20%
10V
CERM
1206
4.7uF
03
051-6532
15 103
THERM_1_N
THERM_2_N
_PP3V3_RUN_FAN
_PP3V3_RUN_FAN
_PP5V_PWRON_FAN
_PP5V_PWRON_FAN
PP3V3_PWRON_MAX1989
MIN_LINE_WIDTH=10 mil
MIN_NECK_WIDTH=10 mil
VOLTAGE=3.3V
MAX1989_D4
MAX1989_D4_N
THERM
MAX1989_D1
MAX1989_D1_P
THERM
MAX1989_D1
MAX1989_D1_N
THERM
MAX1989_D2
MAX1989_D2_P
THERM
THERM
THERM_3_P
THERM_3
THERM
THERM_1
THERM_1_N
THERM
THERM_1_P
THERM_1
MAX1989_D4
MAX1989_D4_P
THERM
MAX1989_D3
MAX1989_D3_N
THERM
THERM_1_P
THERM
THERM_2_N
THERM_2
FAN_TACH0
I2C_MAX1989_SDA
MAX1989_D4_N
MAKE_BASE=TRUE
GPU_THMDIODE_P
MAKE_BASE=TRUE
GPU_THMDIODE_N
MAX1989_D4_N
MAX1989_D4_P
FAN_TACH1
FAN_RPM0
FAN_RPM1
THERM_1B_P
THERM_1B_N
THERM_2B_N
THERM_3B_P
THERM_3B_N
THERM_2_P
THERM_3_P
THERM_3_N
THERM_2B_P
MAX1989_D1_P
MAX1989_D1_N
MAX1989_D2_P
MAX1989_D2_N
MAX1989_D3_P
MAX1989_D3_N
THERM_1B_P
THERM_1_P
THERM_1_N
THERM_2_P
THERM_2B_P
THERM_2_N
THERM_3B_P
THERM_3_P
THERM_3_N
THERM_3B_N
MAX1989_D2
MAX1989_D2_N
THERM
THERM
THERM_2_P
THERM_2
THERM
THERM_3B_P
THERM_3B
THERM
THERM_2B
THERM_2B_N
THERM
THERM_2B_P
THERM_2B
THERM
THERM_1B_N
THERM_1B
THERM
THERM_3_N
THERM_3
_PP3V3_PWRON_THERM
MAX1989_D2_P
MAX1989_D3_P
SYS_OVERTEMP_L
MAX1989_D4_P
MAX1989_D1_P
I2C_MAX1989_SCL
THERM_2B_N
THERM_1B_N
MAX1989_D3_N
MAX1989_D2_N
MAX1989_D1_N
THERM
THERM_1B_P
THERM_1B
THERM
THERM_3B_N
THERM_3B
MAX1989_D3
MAX1989_D3_P
THERM
25 23 17
15
15
15
15
13
13
13
13
13
15
15
5
5
5
5
15
15
15
15
15
15
15
15
15
15
15
6
18
15
37
37 15
15
6
6
6
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
5
15
15
6
15
15
18
15
15
15
15
15
15
15
15
Preliminary
Page 16
S
D
G
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Debug LEDs
Debug "Buttons"
"RESET"
Add silkscreen:
"POWER"
(GPIO#)
(TRXC)
516S0143
(RXD)
(SCCA)
(DTR#)
(RTS#)
(TXD#)
allow serial debug flex to use either connector
SCC same pins have pinout as modem connector to
SMU Download / Serial Debug Connector
INTERNAL I/O CONNECTORS
21
R1690
NO STUFF
5%
1/16W
MF
0
603
21
R1691
1/16W
603
5%
MF
0
NO STUFF
9
8 7
6 5
4 3
2
16 15
14 13
12 11
10
1
J1699
DEVELOPMENT
QT510166-L010
F-ST-SM1
CRITICAL
2
1
R3054
DEVELOPMENT
5%
180
1/16W
MF
402
2
1
D3002
SM
RED
DEVELOPMENT
2
1
3
Q3004
DEVELOPMENT
Q3004_D
SM
2N7002
2
1
R3052
DEVELOPMENT
5%
402
MF
1/16W
180
2
3
1
Q3003
DEVELOPMENT
SM
Q3003_B
2N3904
2
3
1
Q3002
SM
DEVELOPMENT
2N3906
2
1
R3048
DEVELOPMENT
5%
180
1/16W
MF
402
21
R3050
5%
DEVELOPMENT
402
MF
1/16W
180
2
1
D3001
GREEN
SM
DEVELOPMENT
2
1
R3070
DEVELOPMENT
1/16W
5%
402
MF
180
2
1
R3046
DEVELOPMENT
5%
1K
1/16W
MF
402
2
3
1
Q3001
DEVELOPMENT
SM
2N3904
21
R3044
5%
DEVELOPMENT
402
MF
1/16W
180
03
051-6532
10316
_PP5V_PWRON_SERIAL
_PP3V3_ALL_SMU
I2S1_SB_TO_DEV_DTO
I2S1_MCLK
I2S1_RESET_L
SMU_BOOT_TXD
SMU_BOOT_RXD
SMU_BOOT_BUSY
I2S1_SYNC
I2S1_DEV_TO_SB_DTI
I2S1_BITCLK
SMU_RESET_L
SMU_BOOT_CE
SMU_BOOT_SCLK
SMU_BOOT_CNVSS
SYS_POWER_BUTTON_L
SYS_RESET_BUTTON_L
D3002_1
PP5V_RUN_CPU
Q3004_G
Q3002_E
CHKSTOP_L
D3001_1
PP5V_RUN_CPU
Q3002_B
Q3001_C
Q3001_BPLLLOCK
42
18
60
60
60
60
60
60
19
17
29
29
13
23
23
23
13
13
23
23
23
13
13
13
13
16
16
5 5
6
6
6
6
6
13
6
6
6
6
13
13
6
6
6
5
27
5
27
Preliminary
Page 17
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
series resistors to protect SMU pins
overtemp may need pull-up resistor
USB Trackpad Connector
For EMI around ENET magnetic
Speaker Clips
for EMI testing only
Graphic Heat Sink
CPU Heat Sink
Right I/O area
PPBUS Hold-Up Caps
BlueTooth / Left USB Flex Connector
Place cap close to SMU
battery circuit. _PPBUSA_BBATT is an output only.
NC
NC
Backup Battery / Right USB Flex Connector
_PPBUSB_BBATT is both an input and an output for backup
Q51 Specific connectors
Place cap close to SMU
21
D790
SM
MBR0530
9
8
7
6
5
4
3
2
14
13
12
11
10
1
16
15
J1600
CRITICAL
F-RT-SM
54550-1490
2
1
C862
CRITICAL
ELEC
25V
20%
33uF
SM1
2
1
C861
CRITICAL
SM1
33uF
20%
25V
ELEC
2
1
C865
CRITICAL
ELEC
25V
20%
33uF
SM1
2
1
C864
CRITICAL
ELEC
25V
20%
33uF
SM1
2
1
C860
CRITICAL
ELEC
25V
20%
33uF
SM1
2
1
C863
CRITICAL
ELEC
25V
20%
33uF
SM1
1
ZT511
146R126
1
ZT510
146R126
1
BS510
STDOFF-217ODX150IDX35H-TH
1
ZT503
255R158
1
ZT504
255R158
1
ZT502
255R158
1
ZT500
255R158
1
ZT501
255R158
1
ZT505
255R158
9
8
7
6
5
4
3
2
14
13
12
11
10
1
16
15
J790
54550-1490
CRITICAL
F-RT-SM
1
SP9900
OMIT
SPKR_CLIP_P84
1
SP503
SPKR_CLIP_P84
1
SP504
SPKR_CLIP_P84
1
SP505
SPKR_CLIP_P84
1
SP500
SPKR_CLIP_P84
1
SP501
SPKR_CLIP_P84
1
SP502
SPKR_CLIP_P84
1
ZT9901
HOLE-VIA-20R10
OMIT
2
1
C1610
CERM
402
5%
50V
100pF
1
ZT9903
HOLE-VIA-20R10
OMIT
1
ZT9900
HOLE-VIA-20R10
OMIT
1
ZT9902
OMIT
HOLE-VIA-20R10
2
1
R2132
100K
402
5%
MF
1/16W
9
8
7
6
5
4
3
2
14
13
12
11
10
1
16
15
J2130
CRITICAL
F-RT-SM
54550-1490
2
1
R2131
5%
1/16W
MF
402
15K
2
1
R2130
5%
MF
402
15K
1/16W
21
R1620
1K
MF
5%
1/16W
402
21
R1610
MF
5%
1/16W
402
0
2
1
R1621
3.32K
1%
1/16W
MF
402
2
1
R1611
1K
5%
1/16W
MF
402
PP3V3_ALL
2
1
C1605
CERM
50V
5%
402
100pF
2
1
R1601
5%
1/16W
15K
MF
402
2
1
R1600
5%
1/16W
MF
402
15K
18
103
03051-6532
ALS0_OUT
GND_SMU_AVSS
ALS0_OUT_R
SMU_ONEWIRE
MAKE_BASE=TRUE
GND_SMU_AVSS
_PPBUSA_BBATT
PPBBATT_BOOST_OUT
MIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=10 mil
VOLTAGE=6.3V
RTUSB_PWREN
USB2_RT_N
RTUSB_OVERCURRENT
USB2_RT_P
_PP5V_PWRON_RTUSB
_PPBUSB_BBATT
USB_BT_N
USB_BT_P
_PP5V_PWRON_LTUSB
ALS_GAIN_BOOST
MAKE_BASE=TRUE
LTUSB_OVERCURRENT
USB2_LT_P
LTUSB_PWREN
USB2_LT_N
_PP3V3_PWRON_BT
_PPBUS_ALL_A
_PPBUS_ALL_B
GND_CHASSIS_DVI
GND_CHASSIS_IO
GND_CHASSIS_INVERTER
_PP3V3_ALL_HALLEFFECT
USB_TPAD_N
SYS_LID_OPEN
MAKE_BASE=TRUE
_PP5V_PWRON_TPAD
PP3V3_PWRON
USB_TPAD_P
KBDLED_RETURN
KBDLED_ANODE
SYS_OVERTEMP_L
SYS_POWER_BUTTON_L
I2C_DS1775_SDA
I2C_DS1775_SCL
ADAPTER_ID
25
32
32
23
42
19
19
19
42
15
16
13
17
17
13
8
8
6
25
19
19
13
13
6
13
13
13
5
11
5
5
5
5
5
5
5
5
5
6
5
5
5
5
5
5
5
5
5 5
5
5
13
5
6
5
6
6
6
6
18
18
6
Preliminary
Page 18
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIASALIAS
ALIAS
ALIAS
ALIAS
LM339A
V+
GND
LM339A
V+
GND
LM339A
V+
GND
LM339A
V+
GND
G
D
S
G
D
S
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
(MASTER)
U1300
SMU
U3
(MASTER)
NorthBridge I2C "B" Bus
I2C CONNECTIONS
I2C "A" Bus
U3Lite
U3
(MASTER)
U1300
SMU
(Write: 0x?? Read: 0x??)
U2900
CPU
Power aliases required by this page:
(NONE)
(NONE)
(NONE)
BOM options provided by this page:
(I2C_CPU_A_SDA)
(I2C_CPU_A_SCL)
(Write: 0x?? Read: 0x??)
ELECTRICAL_CONSTRAINT_SET
DIFFERENTIAL_PAIR
NET_SPACING_TYPE
(Write: 0xAC Read: 0xAD)
(Address set on modem flex)
MicroDash
Audio Board
(Write: 0x?? Read: 0x??)
J9500
J9400
SouthBridge I2C Bus
(MASTER)
U2300
Shasta
RTC
U1301
J790
U800
(Write: 0x?? Read: 0x??)
(Write: 0x?? Read: 0x??)
(Write: 0x?? Read: 0x??)
Battery Charger
Battery Conn
I2C "E" Bus
SMU
U1300
(MASTER)
Pulsar
U2600
On Trackpad Flex
DS1775
(Write: 0x?? Read: 0x??)
(Write: 0x30 Read: 0x31)
(Write: 0x?? Read: 0x??)
I2C "B" Bus
SMU
(MASTER)
U1300
U3Lite
(Write: 0xA0 / 0xA2,
J4010 / J4020
DIMMs
Read: 0xA1 / 0xA3)
NorthBridge I2C "C" Bus
U3
(MASTER)
U3Lite
MAX1989
U1500
Signal aliases required by this page:
Page Notes
U3 Lite I2C inversion
2
1
R2029
5%
1/16W
MF
402
2K
PP2V5_PWRON
2
1
R2028
402
MF
1/16W
5%
2K
2
1
R2051
7.15K
1/16W
1%
MF
402
2
1
R2050
1%
7.15K
1/16W
MF
402
2
1
R2019
5%
1/16W
MF
402
200
2
1
R2018
MF
402
5%
200
1/16W
2
1
R2015
5%
1/16W
MF
402
4.7K
PP5V_PWRON
2
1
C2015
20%
10V
CERM
402
0.1uF
3
13
11
10
12
U2015
SOI
CRITICAL
PP3V3_PWRON
2
1
R2011
402
MF
1/16W
5%
2K
2
1
R2010
5%
1/16W
MF
402
2K
2
1
C2016
CERM
10V
20%
402
0.1uF
2
1
R2016
MF
1/16W
1%
576
402
3
14
9
8
12
U2015
SOI
CRITICAL
PP3V3_PWRON
2
1
R2081
1/16W
402
MF
5%
2K
2
1
R2080
1/16W
MF
402
5%
2K
3
1
7
6
12
U2015
SOI
CRITICAL
2
1
R2083
MF
1/16W
5%
1K
402
2
1
R2082
MF
1K
1/16W
5%
402
3
2
5
4
12
U2015
SOI
CRITICAL
5
6
7
8
4
3
2
1
RP2085
0K
5%
1/16W
SM1
SMU_CPU_JTAG
5
6
7
8
4
3
2
1
RP2080
SM1
1/16W
5%
0K
SMU_CPU_I2C
4
5
3
Q2000
SOT-363
2N7002DW
1
2
6
Q2000
2N7002DW
SOT-363
PP3V3_RUN
2
1
R2041
1K
402
MF
1/16W
5%
2
1
R2040
5%
1K
1/16W
MF
402
72
RP2060
4.7K
SM1
1/16W
5%
81
RP2060
5%
1/16W
SM1
4.7K
54
RP2060
5%
1/16W
4.7K
SM1
63
RP2060
4.7K
SM1
1/16W
5%
PP2V5_PWRON
2
1
R2030
2K
5%
1/16W
MF
402
2
1
R2031
2K
402
1/16W
5%
MF
PP3V3_PWRON
2
1
R2021
5%
1/16W
MF
402
1K
2
1
R2020
1K
402
MF
1/16W
5%
03
20 103
051-6532
I2C_0V546_REF
MAKE_BASE=TRUE
I2C_SMU_A_SDA_IN
SMU_CPU_JTAG_OR_I2C
MAKE_BASE=TRUE
I2C_SMU_CPU_SDA_OUT
I2C_SMU_A_SDA_OUT
MAKE_BASE=TRUE
I2C_SMU_A_SCL_OUT
MAKE_BASE=TRUE
I2C_SMU_A_SDA_OUT_L
I2C_SMU_A_SCL_OUT_L
I2C_NB_C
I2C
I2C_NB_C
I2C_NB_C_SDA
I2C_SB
I2C
I2C_SB
I2C_SB_SCL
I2C
I2C_SMU_A_OUTI2C_SMU_A_OUT
I2C_SMU_A_SDA_OUT
I2C
I2C_NB_CI2C_NB_C
I2C_NB_C_SCL
I2C_DIMM_SDA
I2C_DIMM_SCL
MAKE_BASE=TRUE
I2C_NB_C_SDA
MAKE_BASE=TRUE
I2C_NB_C_SCL
I2C_DS1775_SDA
I2C_DS1775_SCL
I2C_MAX1989_SDA
I2C_MAX1989_SCL
I2C_CLOCK_SDA
I2C_CLOCK_SCL
I2C_CHGR_SCL
I2C_CHGR_SDA
I2C_BATT_SDA
I2C_BATT_SCL
I2C_RTC_SDA
I2C_RTC_SCL
MAKE_BASE=TRUE
I2C_SMU_B_SDA
MAKE_BASE=TRUE
I2C_SMU_B_SCL
MAKE_BASE=TRUE
I2C_SMU_E_SCL
MAKE_BASE=TRUE
I2C_SMU_E_SDA
_PP3V3_ALL_SMU
I2C_AUDIO_SDA
I2C_AUDIO_SCL
I2C_MODEM_SDA
I2C_MODEM_SCL
MAKE_BASE=TRUE
I2C_SB_SDA
MAKE_BASE=TRUE
I2C_SB_SCL
I2C
I2C_SMU_CPU_OUTI2C_SMU_CPU_OUT
I2C_SMU_CPU_SCL_OUT
I2C
SMU_CPU_JTAG_OR_I2C
I2C
I2C_CPU_A_SDA
I2C
I2C_SMU_BI2C_SMU_B
I2C_SMU_B_SDA
I2C
I2C_SMU_BI2C_SMU_B
I2C_SMU_B_SCL
I2C
I2C_CPU_A_SDA_TO_SMU
I2C
I2C_CPU_A_SCL
I2C
I2C_SMU_A_INI2C_SMU_A_IN
I2C_SMU_A_SDA_IN
I2C
I2C_SMU_A_INI2C_SMU_A_IN
I2C_SMU_A_SCL_IN
I2C
I2C_SMU_A_OUTI2C_SMU_A_OUT
I2C_SMU_A_SCL_OUT
I2C
I2C_SMU_CPU_OUTI2C_SMU_CPU_OUT
I2C_SMU_CPU_SDA_OUT
I2C
I2C_NB_BI2C_NB_B
I2C_NB_B_SDA
I2C
I2C_SMU_CPU_INI2C_SMU_CPU_IN
I2C_SMU_CPU_SCL_IN
I2C
I2C_SMU_CPU_INI2C_SMU_CPU_IN
I2C_SMU_CPU_SDA_IN
I2C
I2C_NB_BI2C_NB_B
I2C_NB_B_SCL
MAKE_BASE=TRUE
I2C_SMU_A_SCL_IN
I2C_SMU_A_SCL_OUT_L
PP1V2_EI_NB
I2C_CPU_A_SDA
JTAG_CPU_TDO
PP1V2_EI_CPU
I2C_NB_A_SCL
I2C_NB_A_SDA
JTAG_SB_TCK
JTAG_SB_TDI
JTAG_SB_TRST_L
JTAG_SB_TMS
_PP3V3_PWRON_SB
MAKE_BASE=TRUE
I2C_NB_B_SCL
MAKE_BASE=TRUE
I2C_NB_B_SDA
I2C_SMU_A_SDA_OUT_L
JTAG_CPU_TDI
JTAG_CPU_TMS
JTAG_CPU_TCK
I2C_SMU_CPU_SCL_IN
MAKE_BASE=TRUE
I2C
I2C_SBI2C_SB
I2C_SB_SDA
I2C_CPU_A_SCL
I2C_CPU_A_SDA_TO_SMU
MAKE_BASE=TRUE
I2C_SMU_CPU_SCL_OUT
MAKE_BASE=TRUE
I2C_SMU_CPU_SDA_IN
29
45
23
18
18
16
23
23
18
18
28
28
23
28
28
28
23
18
18
18
18
22
18
18
22
22
22
13
13 13
13
13
18
18
18
27
13
13
27
18
18
18
18
22
18
18
22
18
26
27
27
27
23
23
23
23
21
22
22
27
27
27
18
18
27
18
18
13
18
13
13
13
18
18
18
6
13
18
35
35
18
18
17
17
15
15
25
25
8
8
7
7
13
13
6
6 6
6
5
61
61
60
60
6
6
13
18
18
6
6
18
18
13
13
13
13
18
13
13
18
13
18
5
18
6
5
22
22
6
6
6
6
5
18
18
18
6
6
6
13
6
18
18
13
13
Preliminary
Page 19
V+
V-
G
D
S
PGND
EP
GND
COMP
CTRL
CS
OUT
LX
IN
G
D
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Ambient Light Sensor #1
SMU ALS/LEDs
Keyboard LED Driver
Sleep LED Circuit
SMU / System Reset Button
Keep inductor close to cap
Place R2115,R2116 and C2115 close to SMU
2
6
5
1
4
3
U2110
CRITICAL
SOT23-6
MAX4236EUTT
2
1
C2110
20%
CERM
402
0.1uF
10V
2
1
R2110
1K
402
1%
MF
1/16W
2
1
R2111
5%
1/16W
MF
402
5.1M
2
1
C2111
CERM
402
16V
20%
0.01uF
2
1
RD2111
CRITICAL
TH
BS520
2
1
R2112
120K
402
MF
1/16W
5%
2
1
C2112
0.22uF
20%
6.3V
402
X5R
2
1
R2113
1K
402
1%
MF
1/16W
2
1
R2114
15K
402
1%
MF
1/16W
21
R2115
1K
402
1%
MF
1/16W
2
1
R2199
100
402
MF
1/16W
5%
2
1
L2199
SM-1
400-OHM-EMI
2
1
C2199
402
CERM
50V
10%
470pF
2
3
1
Q2199
SM
2N3906
2
1
R2193
1/16W
2.2K
402
MF
5%
2
1
R2192
402
1/16W
5%
MF
4.7K
4
5
3
Q2191
SOT-363
2N7002DW
2
1
R2191
5%
1/16W
MF
402
100K
7
1
82
69
3
4
5
U2150
CRITICAL
QFN
MAX1561
21
L2150
CRITICAL
22uH
SMA-2
2
1
C2151
20%
10V
CERM
402
0.1uF
2
1
C2152
0.22uF
10%
CERM
50V
1210
2
1
C2150
CERM1
6.3V
603
2.2uF
20%
2
1
D2150
SM
MBR0540
2
1
R2150
8.25
1%
1/10W
FF
805
43
21
SW2100
SM
2
1
R2116
3.32K
1%
1/16W
MF
402
2
1
C2115
402
CERM
50V
5%
100pF
1
2
6
Q5909
SOT-363
2N7002DW
21 103
051-6532
03
GND_SMU_AVSS
ALS1_OUT
SYS_LED
ALS1_OUT_DIV
ALS1_OUT_R
SLEEPLED_EN_L_DIV
SLEEPLED_ANODE
SLEEPLED_ANODE_F
SLEEPLED_ANODE_F_Q
SLEEPLED_EN_L
ALS1_PHOTODIODE
MIN_LINE_WIDTH=10 mil
MIN_NECK_WIDTH=10 mil
SMU_RESET_L
KBDLED_COMP
MAKE_BASE=TRUE
SYS_KBDLED
KBDLED_LX
_PP5V_RUN_KBDLED
_PP3V3_PWRON_ALS1
_PP5V_PWRON_SLEEPLED
KBDLED_RETURN
MIN_LINE_WIDTH=10 mil
MIN_NECK_WIDTH=10 mil
KBDLED_ANODE
MIN_LINE_WIDTH=10 mil
MIN_NECK_WIDTH=10 mil
ALS_GAIN_BOOST
ALS1_GAIN_BOOST_L
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=10 mil
ALS1_OP_IN
32
16
17
17
61
13
17
17
13
13
13
13
6
6
13
5
5
5
6
6
6
Preliminary
Page 20
GND
GND
VDD
(SYM 6 OF 7)
DRAWING
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
U3Lite Core Power
Page Notes
Power aliases required by this page:
- _PPVCORE_PWRON_NB
BOM options provided by this page:
(NONE)
(NONE)
Signal aliases required by this page:
Master: Link
R14
T16
T11
U18
U13
U10
V15
K15
V12
K12
L17
L14
M16
M11
N18
N13
P15
P12
R17
W17
W14
AC13
B22
B16
B13
B4
AC7
D25
D19
D10
D7
D2
F22
F16
F13
G27
G23
AE25
G4
H19
H10
J14
J9
K25
K21
K16
K11
K6
AE19
K2
L18
L13
L10
M20
M15
M12
N27
N23
N17
AE10
N14
N9
N8
N4
P19
P16
P11
R18
R13
R10
AE4
T27
T23
T20
T15
T12
T6
T2
U17
U14
U9
AG22
V19
V16
V11
W25
W21
W18
W13
W8
W4
Y20
AG16
Y15
Y12
AA19
AA10
AB27
AB23
AB6
AB2
AC22
AC16
AG13
AG7
U3
PBGA
OMIT
U3LITE
V1.0-300MM
2
1
C2222
402
0.1UF
20%
10V
CERM
2
1
C2223
CERM
10V
20%
0.1UF
402
2
1
C2224
402
0.1UF
20%
10V
CERM
2
1
C2226
CERM
10V
20%
402
0.1UF
2
1
C2225
402
0.1UF
20%
10V
CERM
2
1
C2228
CERM
10V
20%
0.1UF
402
2
1
C2227
402
0.1UF
20%
10V
CERM
2
1
C2230
CERM
10V
20%
0.1UF
402
2
1
C2229
402
0.1UF
20%
10V
CERM
2
1
C2232
402
0.1UF
20%
CERM
10V
2
1
C2231
20%
402
0.1UF
10V
CERM
2
1
C2234
402
0.1UF
20%
10V
CERM
2
1
C2233
CERM
10V
20%
0.1UF
402
2
1
C2236
402
0.1UF
20%
10V
CERM
2
1
C2235
402
0.1UF
20%
10V
CERM
2
1
C2238
402
0.1UF
20%
10V
CERM
2
1
C2237
CERM
10V
20%
402
0.1UF
2
1
C2240
402
0.1UF
20%
10V
CERM
2
1
C2239
10V
20%
0.1UF
402
CERM
2
1
C2242
CERM
10V
20%
0.1UF
402
2
1
C2241
CERM
10V
20%
0.1UF
402
2
1
C2243
CERM
10V
20%
0.1UF
402
2
1
C2244
402
0.1UF
20%
10V
CERM
2
1
C2245
402
0.1UF
20%
10V
CERM
2
1
C2246
402
0.1UF
20%
10V
CERM
2
1
C2247
402
0.1UF
20%
10V
CERM
ABBREV=DRAWING
TITLE=FIZZY
10322
03
051-6532
_PPVCORE_PWRON_NB
LAST_MODIFIED=Mon Feb 23 19:04:04 2004
5
Preliminary
Page 21
VIO1
POWER
VDDO33
VDDO25
VIO2
VDDP_KL
VDDC
GND
GND
GND
(1 OF 8)
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
DRAWING
Master: Link
other Shasta supplies.
- _PP2V5_PWRON_SB
- _PPPCI32_PWRON_SB (to 5V or 3.3V)
- _PPPCI64_PWRON_SB (to 5V or 3.3V)
- _PP3V3_PWRON_SB
different drive timing
PCI, otherwise 3.3V.
Connect _PPPCI32_PWRON_SB to
spec for 5V vs. 3.3V operation.
appropriate PCI bus voltage and
Signal aliases required by this page:
(NONE)
(NONE)
BOM options provided by this page:
Power Sequencing:
- _PPVCORE_PWRON_SB (1.2V)
NOTE: PCI pads use the VIO supply to meet
characteristics required by the PCI
_PPPCI64_PWRON_SB to same if 64-bit
Must power Shasta VCore rail before any
Page Notes
Power aliases required by this page:
Shasta Core Power
Shasta max (est 06/30/03) current:
VDDPs - 2.5V - 100 mA ( 250 mW)
I/O 2.5 - 2.5V - 20 mA ( 60 mW)
Total: 3015 mW
I/O 3.3 - 3.3V - 220 mA ( 770 mW)
ANALOG12 - 1.2V - 600 mA ( 760 mW)
DIGITAL - 1.2V - 950 mA (1175 mW)
For PCI_AD<31..0>
For PCI_AD<63..32>
2
1
C2304
20%
10V
CERM
402
0.1uF
2
1
C2305
10V
CERM
402
0.1uF
20%
2
1
C2306
0.1uF
402
CERM
10V
20%
2
1
C2307
20%
10V
CERM
402
0.1uF
2
1
C2308
0.1uF
402
20%
CERM
10V
2
1
C2309
20%
10V
402
CERM
0.1uF
2
1
C2302
0.1uF
402
CERM
10V
20%
2
1
C2301
0.1uF
402
CERM
10V
20%
2
1
C2300
20%
10V
CERM
402
0.1uF
2
1
C2314
0.1uF
402
CERM
10V
20%
2
1
C2313
0.1uF
402
CERM
10V
20%
2
1
C2312
402
20%
10V
CERM
0.1uF
2
1
C2311
20%
10V
CERM
402
0.1uF
2
1
C2310
402
CERM
20%
10V
0.1uF
2
1
C2334
20%
10V
CERM
402
0.1uF
2
1
C2333
0.1uF
402
CERM
10V
20%
2
1
C2339
0.1uF
402
CERM
10V
20%
2
1
C2338
20%
10V
CERM
402
0.1uF
2
1
C2332
20%
10V
CERM
402
0.1uF
2
1
C2331
0.1uF
402
CERM
10V
20%
2
1
C2337
0.1uF
402
CERM
10V
20%
2
1
C2336
20%
10V
CERM
402
0.1uF
2
1
C2330
20%
10V
CERM
402
0.1uF
2
1
C2335
0.1uF
402
CERM
10V
20%
2
1
C2324
0.1uF
402
CERM
10V
20%
2
1
C2323
0.1uF
402
CERM
10V
20%
2
1
C2329
20%
10V
CERM
402
0.1uF
2
1
C2328
20%
10V
CERM
402
0.1uF
2
1
C2322
20%
10V
CERM
402
0.1uF
2
1
C2321
CERM
20%
10V
402
0.1uF
2
1
C2327
0.1uF
402
CERM
10V
20%
2
1
C2326
0.1uF
402
CERM
10V
20%
2
1
C2320
0.1uF
402
CERM
10V
20%
2
1
C2325
20%
10V
CERM
402
0.1uF
2
1
C2351
20%
10V
CERM
0.1uF
402
2
1
C2350
0.1uF
402
10V
20%
CERM
2
1
C2357
0.1uF
402
20%
10V
CERM
2
1
C2356
20%
10V
CERM
402
0.1uF
2
1
C2355
0.1uF
402
CERM
10V
20%
2
1
C2362
CERM
402
0.1uF
10V
20%
2
1
C2361
20%
CERM
402
0.1uF
10V
2
1
C2360
0.1uF
10V
402
CERM
20%
2
1
C2365
0.1uF
402
CERM
10V
20%
Y19
W22
L21
K21
H17
H18
V8
D1
B5
B2
B1
AB6
AB2
AB10
AA3
W4
V7
U9
U12
R2
M1
L7
H1
F8
F4
AA2
AA1
G15
D19
P15
N8
M15
L8
L15
K8
J15
J12
T15
T10
R9
R12
R10
H8
H15
D2
C19
AB22
AB1
W5
W19
U22
U13
U10
T12
R19
P9
P4
AA6
P14
P13
P12
P10
N9
N22
N13
N12
N11
N10
AA10
M2
M14
M13
M12
M11
M10
L9
L16
L14
L13A5L12
L11
L10
K9
K7
K13
K12
K11
K10
J22
A22
J16
J14
J13
J11
J10
H9
H2
F7
F3
E22
A2
A1
U2300
OMIT
BGA
V1.0
SHASTA
2
1
C2303
20%
10V
CERM
402
0.1uF
23 103
051-6532
03
TITLE=FIZZY
ABBREV=DRAWING
_PP2V5_PWRON_SB
_PPPCI64_PWRON_SB
_PPPCI32_PWRON_SB
_PP3V3_PWRON_SB
_PP2V5_PWRON_SB
_PPVCORE_PWRON_SB
LAST_MODIFIED=Mon Feb 23 19:04:08 2004
56
56
45
45
45
23
23
23
21
18
21
5
5
5
5
5
5
Preliminary
Page 22
G
D
S
G
D
S
S
D
G
G
D
S
G
D
S
G
D
S
G
D
S
SYS_ISCL0
SYS_ISCA0
SYS_ISCA1
SYS_ISCL1
API_ISCA
API0_ISCL
THMO
DUMMY_A
DUMMY_B
PMR_OBSV
IRQ0
THMI
(SYM 7 OF 7)
HRESET*
PURESET*
SUSPENDACK*
SUSPENDREQ*
CE1_B_TDO
CE1_A_TDI
CE1_LT_TCK
VSP_CLKN
VSP_CLKP
CE1_DI1_TMS
CE1_DI2_TRST
CE1_RI
CEO_TEST
PM_SLEEP0
CE0_RE
CE0_MC
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
ELECTRICAL_CONSTRAINT_SET
NET_SPACING_TYPE
DIFFERENTIAL_PAIR
MASTER: GILA
JTAG_NB_TRST_L
JTAG_NB_TDO
JTAG_NB_TMS
U3LITE MISC
JTAG_NB_TDI
JTAG_NB_TCK
U3LITE REQUIRES ALL JTAG SIGNALS
HIGH FOR NORMAL OPERATION
PP3V3_PWRON
PP3V3_PWRON PP3V3_PWRON
PP3V3_PWRON PP2V5_PWRON
PP2V5_PWRONPP2V5_PWRON
PP2V5_PWRON
I109
I110
2
1
R2435
MF
1/16W
5%
4.7K
402
2
1
C2400
0.1UF
402
CERM
10V
20%
2
1
R2418
100
MF
1/16W
5%
402
2
1
R2419
402
MF
1/16W
5%
100
NOSTUFF
4
5
3
Q2404
SOT-363
2N7002DW
NOSTUFF
2
1
R2420
1/16W
402
10K
5%
MF
NOSTUFF
2
1
R2400
MF
100
1/16W
402
1%
1
2
6
Q2404
2N7002DW
SOT-363
NOSTUFF
2
1
3
Q2407
2N7002
SM
2
1
R2421
MF
1/16W
5%
10K
402
2
1
R2422
402
4.7K
5%
1/16W
MF
2
1
3
Q2408
SI2302DS
SM
4
5
3
Q2409
SOT-363
2N7002DW
2
1
R2423
1/16W
10K
MF
5%
402
1
2
6
Q2409
2N7002DW
SOT-363
4
5
3
Q2412
NOSTUFF
2N7002DW
SOT-363
2
1
R2438
NOSTUFF
MF
10K
402
5%
1/16W
1
2
6
Q2412
NOSTUFF
SOT-363
2N7002DW
2
1
R2403
402
MF
1/16W
1%
100
2
1
R2424
402
10K
5%
1/16W
MF
2
1
R2426
402
MF
1/16W
5%
10K
2
1
R2429
402
10K
5%
1/16W
MF
2
1
R2431
MF
1/16W
5%
10K
402
2
1
R2433
402
10K
5%
1/16W
MF
2
1
R2436
MF
1/16W
402
10K
5%
2
1
R2442
10K
MF
1/16W
5%
402
2
1
R2443
MF
1/16W
5%
10K
402
2
1
R2444
402
10K
5%
1/16W
MF
2
1
R2405
NOSTUFF
5%
1/16W
MF
402
4.7K
21
R2406
402
MF
1/16W
5%
0
21
R2407
NOSTUFF
0
5%
1/16W
MF
402
21
R2408
402
MF
1/16W
5%
0
P4
R4
J18
J17
C21
C20
E21
B21
D21
D20
E20
D15
Y9
E9
A21
AB28
AC28
AH3
AC2
R25
F20
M26
AA25
V25
AD3
AD5
B20
A20
U3
V1.0-300MM
U3LITE
OMIT
PBGA
2
1
R2402
402
121
1%
1/16W
MF
2
1
R2401
MF
1/16W
1%
121
402
21
R2409
NOSTUFF
0
5%
1/16W
MF
402
2
1
C2401
CERM
NOSTUFF
1000PF
5%
25V
603
051-6532
10324
03
NB_RST_L
PP1V2_HT
SYS_COLD_RESET_L
NB_RESET
NB_PU_RST_L
NB_MC_PD
NB_TEST_PD
JTAG_NB_TCK
JTAG_NB_TDI
JTAG_NB_TRST_L
JTAG_NB_TMS
NB_RI_PU
VSP_NB_CLK_P
VSP_NB_CLK_N
I2C_NB_B_SCL
JTAG_NB_TDO
TP_NB_PM_SLEEP0
NB_RE_PD
PMU_SUSPEND_REQ
SMU_SUSPENDREQ_L
NB_SUSPEND_REQ_L
VOLTAGE=0.6V
NB_VSP_CLK_VREF
MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=25MIL
NB_SUSPEND_ACK_L
I2C_NB_A_SDA
I2C_NB_B_SDA
I2C_NB_A_SCL
NB_SUSPEND_REQ_L
NB_PU_RST_L
NB_RST_L
I2C_NB_C_SDA
I2C_NB_C_SCL
TP_DUMMY_A
TP_DUMMY_B
NB_INT_L
NB_PMR_OBSV
NB_THMI
NB_THMO
NB_PU_RESET
NB_SUSPENDACK_L
NB_SUSPEND_ACK
NB_SUSPEND_ACK_L
SMU_WARM_RESET_L
SMU_RESET
SYS_COLD_RESET_L
10 MIL SPACING
10 MIL SPACING
SMU_RESET
SYS_WARM_RESET_L
48
51
51
45
43
22
23
13
22
23
22
5
13
22
6
6
6
6
25
25
18
6
13
22
22
18
18
18
22
22
22
18
18
23
5
5
5
13
22
5
13
5
Preliminary
Page 23
GND
PLL_49
GND
XTAL_18 PLL_45
GND
VIO
PME
PLL_49
VDD
PLL_45
VDD
XGI
XTALS
TEST
PWR_MGT
PCI
GPIO
I2C
I2S2 I2S1 I2S0
(2 OF 8)
PCI1C_BE_4_L
PCI1C_BE_5_L
PCI1C_BE_6_L
PCI1C_BE_7_L
PCI1PAR64_H
XGI_DTI_H
XGI_DTO1_H
XGI_CLK_H
XGI_DTO0_H
PCI1ACK64_L
PCI1REQ64_L
PCI1AD_60_H
PCI1AD_63_H
PCI1AD_62_H
PCI1AD_61_H
PCI1AD_50_H
PCI1AD_52_H
PCI1AD_53_H
PCI1AD_51_H
PCI1AD_59_H
PCI1AD_58_H
PCI1AD_57_H
PCI1AD_56_H
PCI1AD_55_H
PCI1AD_54_H
PCI1AD_40_H
PCI1AD_41_H
PCI1AD_42_H
PCI1AD_43_H
PCI1AD_44_H
PCI1AD_49_H
PCI1AD_48_H
PCI1AD_47_H
PCI1AD_46_H
PCI1AD_45_H
PCI1AD_39_H
PCI1REQ_5_L
PCI1AD_32_H
PCI1AD_34_H
PCI1AD_38_H
PCI1AD_37_H
PCI1AD_36_H
PCI1AD_33_H
PCI1AD_35_H
PCI1GNT_5_L
PCI1GNT_4_L
PCI1REQ_4_L
PCI1GNT_3_L
PCI1REQ_3_L
XTAL_18XTAL
VDD VDD
FSTEST
XTAL_18_I
XTAL_18_O
XTALI
XTALO
PLLTEST
TEST_MODE_H
TDI
TCK
TMS
TDO
INTRWD_H
I2CDATA_H
I2CCLK_H
PCI_SEL32BIT_H
GPIO_H_3
GPIO_H_2
GPIO_H_1
I2S2SYNC_H
I2S2BITCLK_H
I2S2MCLK_H
I2S2DTO_H
I2S2DTI_H
GPIO_H_0
I2S1DTO_H
I2S1MCLK_H
I2S1BITCLK_H
I2S1SYNC_H
I2S1DTI_H
I2S0BITCLK_H
I2S0SYNC_H
I2S0DTI_H
I2S0DTO_H
I2S0MCLK_H
RESET_L
STOPXTALS_L
SUSPENDREQ_L
SUSPENDACK_L
PCI1PME_L
TRST_L
DRAWING
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
NOTE: It is the responsibility of
AUDIO GPIOS
necessary pull-ups & pull-downs.
the audio circuit to provide the
<- To CPU
-> From NorthBridge
NorthBridge / SouthBridge MPIC Routing
From SouthBridge <-
To SouthBridge ->
interrupt controller.
SouthBridge MPIC will be used for
Selects whether NorthBridge or
- MPIC_NB/MPIC_SB
Configures Shasta for 64-bit PCI
- PCI_64BIT
AUDIO GPIO - see note on right
Shasta Serial / Misc
- _PP3V3_PWRON_SB
- _PP1V2_PWRON_SB
Signal aliases required by this page:
35
32
21
DO NOT swap between RPAKs
"Slot F" - AD22
"Slot E" - AD21
6
NOTE: XGC required for Shasta GPIOs
(NONE)
- _PP2V5_PWRON_SB
- _PP3V3_PCI
29
(I2S2_RESET_L)
48
49
52
51
50
54
53
40
39
46
47
45
44
41
43
38
37
36
34
28
30
33
31
(SCCB) (SCCA)
25
24
20
18
19
27
23
22
12
9
16
15
14
13
17
8
11
7
10
(I2S0_DEV_TO_SB_DTI)
26
Power aliases required by this page:
BOM options provided by this page:
NC
GPIO
Page Notes
ELECTRICAL_CONSTRAINT_SET
NET_SPACING_TYPE
DIFFERENTIAL_PAIR
I2S1: Soft Modem
I2S0: Audio DAC
Master: Link
REDUNDANT - NEED TO ADDRESS THIS
REDUNDANT - NEED TO ADDRESS THIS
(I2S2_DEV_TO_SB_DTI)
1 = 32-bit PCI & GPIOs
Re-pin within each RPAK as necessary
(I2S1_RESET_L)
(I2S1_DEV_TO_SB_DTI)
0 = 64-bit PCI & XGC
PCI 32-bit select
I2S2: S/P-DIF
42
2
1
C2500
10uF
20%
6.3V
1206
CERM
2
1
C2501
402
CERM
1uF
10%
6.3V
2
1
C2511
402
10%
CERM
1uF
6.3V
2
1
C2510
20%
6.3V
CERM
1206
10uF
2
1
C2520
20%
6.3V
CERM
1206
10uF
2
1
C2521
402
10%
CERM
1uF
6.3V
2
1
C2530
10uF
CERM
1206
20%
6.3V
2
1
C2531
CERM
402
10%
1uF
6.3V
2
1
R2500
402
MF
1/16W
5%
10K
2
1
R2501
1/16W
MF
402
PCI_64BIT
5%
1K
21
Y2590
8X4.5MM-SM
18.432M
CRITICAL
2
1
R2590
1%
1/16W
MF
402
200
2
1
C2591
402
CERM
50V
5%
22pF
2
1
C2590
22pF
402
CERM
50V
5%
2
1
R2580
MF
402
5%
1/16W
4.7K
Y13
V13
W13
AB12
W14
V15
U15
T9
U7
W2
Y4
W17
W12
Y11
A3
W11
AA11
AB11
U11
V11
W10
E9
Y12
AA12
AA13AB13
U14
W6
U16
AB21
U17
K17
W18
E18
Y20
AA20
AA19
K20
K22
H22
J20
H21
G22
F22
J19
H20
G21
F21
J17
H19
K18
D22
G20
D21
C22
G19
F20
C21
E20
D20
F19
E19
G18
G17
C20
B21
A21
F16
G16
F17
F18
A20
D18
L17
V12
W9
Y7
Y8
AA5
AB4
AA7
V9
AB5
V10
AA8
Y6
U8
Y5
W7
AA4
AB7
Y9
W8
AB3
Y2
V5
V14
U2300
V1.0
BGA
SHASTA
OMIT
2
1
C2540
0.1uF
402
CERM
10V
20%
63
RP2551
SM1
10K
5%
1/16W
81
RP2550
SM1
5%
1/16W
10K
54
RP2550
1/16W
SM1
5%
10K
72
RP2550
SM1
10K
5%
1/16W
81
RP2551
SM1
1/16W
10K
5%
72
RP2551
SM1
1/16W
5%
10K
54
RP2551
SM1
10K
1/16W
5%
81
RP2552
10K
SM1
5%
1/16W
63
RP2550
SM1
1/16W
5%
10K
72
RP2552
5%
1/16W
SM1
10K
54
RP2552
SM1
1/16W
5%
10K
63
RP2552
5%
SM1
10K
1/16W
72
RP2553
SM1
5%
1/16W
10K
54
RP2553
10K
5%
SM1
1/16W
81
RP2553
5%
1/16W
SM1
10K
63
RP2553
SM1
10K
5%
1/16W
21
R2550
10K
MF
1/16W
5%
402
21
R2551
10K
MF
1/16W
5%
402
21
R2552
402
1/16W
5%
10K
MF
21
R2553
5%
1/16W
MF
10K
402
21
R2556
5%
1/16W
MF
10K
402
21
R2557
5%
1/16W
MF
10K
402
21
R2558
10K
MF
1/16W
5%
402
21
R2559
10K
MF
1/16W
5%
402
21
R2564
10K
402
MF
1/16W
5%
21
R2563
10K
402
MF
1/16W
5%
21
R2560
402
MF
1/16W
5%
1K
21
R2561
5%
MF
402
10K
1/16W
21
R2566
10K
402
5%
MF
1/16W
21
R2565
NO STUFF
5%
1/16W
MF
402
10K
21
R2567
5%
1/16W
MF
402
10K
21
R2568
5%
MF
402
10K
1/16W
21
R2562
NO STUFF
402
MF
1/16W
5%
1K
21
R2555
10K
MF
1/16W
5%
NO STUFF
402
21
R2554
1K
5%
1/16W
MF
402
PP3V3_RUN
2
1
R2576
402
1/16W
5%
10K
MF
2
3
1
Q2576
SM
2N3904
MPIC_SB
21
R2575
5%
1/16W
MF
402
10K
MPIC_SB
2
1
R2579
MPIC_NB
5%
1/16W
MF
402
0
21
R2578
5%
1/16W
MF
402
0
MPIC_SB
7
8
6
5
2
1
3
4
RP2510
5%
33
SM1
1/16W
8
7
6
5
1
2
3
4
RP2530
SM1
33
5%
1/16W
6
5
8
7
3
4
1
2
RP2520
1/16W
5%
33
SM1
21
R2505
3.3
805
FF
1/10W
5%
21
R2510
5%
1/10W
FF
805
3.3
21
R2520
3.3
805
FF
1/10W
5%
21
R2530
5%
1/10W
FF
805
3.3
TITLE=FIZZY
ABBREV=DRAWING
25 103
03
051-6532
I2S1_RESET_L
_PP3V3_PWRON_SB
I2S2_SYNC
SB_CLK18M_XTALI
TP_SB_FSTEST
SB_PCI_SEL32BIT
JTAG_SB_TRST_L
I2S2_BIDIR
I2S2_SYNC
I2S1_BITCLK
I2S1_BIDIR
I2S0_BITCLK
JTAG_SB_TMS
I2S2_MCLK
SB_GPIO52
SB_GPIO50
SMU_TO_SB_INT_L
SB_GPIO51
SB_GPIO47
SB_GPIO45
SB_GPIO49
SB_GPIO46
SB_GPIO25
SB_GPIO23
SB_GPIO30
SB_GPIO24
SB_GPIO12
PCI_SLOTC_INT_L
PCI_SLOTF_INT_L
PCI_SLOTB_INT_L
ENET_ENERGYDET
ENETFW_RESET
FW_LOWPWR
SB_SATABR_RESET_L
SYS_SLEWING_L
MODEM_RING2SYS_L
UDASH_RESET_L
SB_TO_SMU_INT_L
SYS_OVERTEMP_L
CPU_SRESET_L
_PP3V3_PWRON_SB
I2S0_BIDIR
I2S0_BITCLK
I2S1_TO_DEV
I2S1_SB_TO_DEV_DTO
SB_TEST_MODE_PD
15 MIL SPACING
SB_CLK18M_XTALO
_PP3V3_PWRON_SB
I2S1_RESET_L
I2S1_DEV_TO_SB_DTI
I2S2_RESET_L
I2S0_DEV_TO_SB_DTI
I2S0_SYNC
I2S0_MCLK
I2S0_SB_TO_DEV_DTO
I2S1_SYNC
I2S1_BITCLK
I2S1_MCLK
I2S1_SB_TO_DEV_DTO
I2S2_SB_TO_DEV_DTO
I2S2_SYNC_R
I2S2_BITCLK_R
I2S2_SB_TO_DEV_DTO_R
I2S1_SYNC_R
I2S1_BITCLK_R
I2S1_MCLK_R
I2S1_SB_TO_DEV_DTO_R
I2S0_SYNC_R
I2S0_BITCLK_R
I2S0_MCLK_R
I2S0_SB_TO_DEV_DTO_R
I2S2_SB_TO_DEV_DTO
I2S2_TO_DEV
I2S1_TO_SB
I2S1_DEV_TO_SB_DTI
I2S1_SYNC
I2S1_BIDIR
SB_CLK18M_XTALI
SB_CLK18M_XTAL 15 MIL SPACING
I2S2_TO_SB
I2S2_DEV_TO_SB_DTI
I2S0_BIDIR
I2S0_SYNC
I2S2_BITCLK
I2S2_BIDIR
I2S0_SB_TO_DEV_DTO
I2S0_TO_DEV
I2S2_MCLK
I2S2_TO_DEV
10 MIL SPACING
15 MIL SPACING
SB_CLK18M_XTALO_R
SYS_PME_L
I2C_SB_SCL
SB_SUSPENDACK_L
SMU_SUSPENDREQ_L
SB_STOPXTALS_L
SB_INT_L
MODEM_RING2SYS_L
I2C_SB_SDA
TP_SB_WATCHDOG
JTAG_SB_TCK
JTAG_SB_TDI
TP_SB_PLLTEST
SB_CLK25M_ATA
_PP3V3_PWRON_SB
_PP3V3_PCI
PCI_SLOTE_REQ_L
PCI_SLOTF_REQ_L
PCI_SLOTE_GNT_L
PCI_SLOTF_GNT_L
PCI_SLOTA_INT_L
PCI_SLOTE_INT_L
PCI_SLOTD_INT_L
PCI_SLOTG_INT_L
JTAG_SB_TDO
SYS_WARM_RESET_L
SB_CLK18M_XTALO_R
I2S2_BITCLK
SB_CLK18M_XTALO
15 MIL SPACING
SB_CLK25M_ATA
SB_CLK25M_ATA
I2S2_DEV_TO_SB_DTI
I2S2_MCLK_R
MIN_NECK_WIDTH=15 mil
MIN_LINE_WIDTH=20 mil
VOLTAGE=2.5V
PP2V5_PWRON_SB_XTAL18VDD
MIN_NECK_WIDTH=15 mil
VOLTAGE=2.5V
PP2V5_PWRON_SB_XTALVDD
MIN_LINE_WIDTH=20 mil
_PP2V5_PWRON_SB
MIN_NECK_WIDTH=15 mil
MIN_LINE_WIDTH=20 mil
VOLTAGE=1.2V
PP1V2_PWRON_SB_PLL49VDD
MIN_NECK_WIDTH=15 mil
MIN_LINE_WIDTH=20 mil
VOLTAGE=1.2V
PP1V2_PWRON_SB_PLL45VDD
_PP1V2_PWRON_SB
NB_TO_SB_INT
NB_INT_L
CPU_INT_L
NB_INT_L_R
SB_INT_L
I2S0_TO_DEV
I2S0_MCLK
10 MIL SPACING
I2S0_DEV_TO_SB_DTI
I2S0_TO_SB
I2S1_MCLK
I2S1_TO_DEV
10 MIL SPACING
SB_GPIO47
SYS_SLEWING_L
SB_GPIO50
SB_GPIO49
SB_GPIO51
SB_GPIO52
NB_TO_SB_INT
SMU_TO_SB_INT_L
AUDIO_SPKR_DET_L
AUDIO_LO_MUTE_L
AUDIO_SPKR_MUTE_L
AUDIO_GPIO_12
AUDIO_LO_OPTICAL_PLUG_L
AUDIO_LO_DET_L
AUDIO_LI_DET_L
AUDIO_LI_OPTICAL_PLUG_L
AUDIO_HP_DET_L
AUDIO_HP_MUTE_L
AUDIO_EXT_MCLK_SEL
AUDIO_GPIO_11
PCI_SLOTG_INT_L
FW_LOWPWR
ENETFW_RESET
SB_GPIO30
SB_GPIO45
SB_GPIO46
ENET_ENERGYDET
I2S0_RESET_L
SYS_OVERTEMP_L
PCI_SLOTF_REQ_L
CPU_SRESET_L
PCI_SLOTF_GNT_L
UDASH_SDOWN
UDASH_RESET_L
AGP_INT_L
PCI_SLOTA_INT_L
PCI_SLOTB_INT_L
PCI_SLOTC_INT_L
PCI_SLOTD_INT_L
PCI_SLOTE_INT_L
PCI_SLOTF_INT_L
SB_GPIO23
SB_GPIO24
SB_GPIO25
SB_SATABR_RESET_L
SB_TO_SMU_INT_L
SB_GPIO12
PCI_SLOTE_GNT_L
PCI_SLOTE_REQ_L
LAST_MODIFIED=Mon Feb 23 19:04:13 2004
25
49
25
45
23
45
45
45
48
23
60
23
60
31
17
23
60
23
60
60
60
60
60
60
60
60
23
47
48
56
60
31
17
23
21
23
25
60
15
28
21
23
21
23
23
23
23
23
23
23
23
60
21
46
47
45
45
23
25
15
28
47
16
18
61
18
61
16
61
18
23
54
23
57
51
23
23
23
13
27
18
61
16
18
16
16
61
61
61
61
16
16
16
16
16
16
61
61
61
61
48
18
22
23
18
18
18
25
18
45
49
49
23
49
48
22
61
25
61
21
28
61
61
16
23
23
61
61
61
61
61
61
61
61
48
57
23
54
13
27
60
23
49
51
23
49
49
6
5
23
23
6
23
6
23
6
23
23
23
13
23
23
23
23
23
23
23
23
23
23
23
23
23
23
12
23
23
13
6
23
13
6
23
5
23
6
23
5
6
6
61
23
23
23
23
6
6
6
6
23
23
6
6
23
23
23
23
23
23
23
13
6
13
13
13
23
6
6
6
6
23
5
5
23
23
23
23
6
23
23
23
6
5
23
23
23
23
23
5
5
23
22
27 23
23
23
6
23
13
23
23
23
23
23
13
61
6
6
61
6
6
6
6
61
61
6
6
23
23
12
23
23
23
23
61
6
23
23
23
6
23
37
6
23
23
23
23
23
23
23
23
23
13
23
23
23
Preliminary
Page 24
SYM 2 OF 2
VDD33
VDD25
VDD25
VDD_PLL3
VDD_PLL2
VDD_PLL1
C4_VDD
C3_VDD
C2_VDD
VDD_PLL4
VDD_I2C
VDD_NBSYNC
VDD_PCLK
VDD33_BC
VDD33_BC1
VDD_HCLK0
VDD_HSYNC
VDD_HCLK2
VDD_HCLK0
VDD_HCLK1
VDD_HCLK2
VDD_HSYNC
VDD15_HSYNC
VDD15_PCLK
VDD_XTAL
VDD_VCLK
VSS_XTAL
VSS_VCLK
VSS_HSYNC
VSS_HCLK2
VSS_HCLK0
VSS_HCLK1
VSS_HCLK2
VSS_HSYNC
VSS_HCLK0
VSS33_BC1
VSS33_BC
VSS33
VSS_PCLK
VSS_NBSYNC
VSS25
VSS25
VSS_I2C
VSS_CML
VSS_PLL4
VSS_PLL3
VSS_PLL2
C2_VSS
C3_VSS
C4_VSS
VSS_PLL1
C1_VSSC1_VDD
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)
BOM OPTION
TABLE_5_HEAD
QTY
DESCRIPTION
PART#
MASTER: GILA
IF 603 CAN BE PLACED CLOSE TO PULSAR
402 CAPS NOT NEEDED
PLACE NEAR PIN L8 K8
PLACE NEAR PIN M3 M2
PLACE NEAR PIN D2 D1
PULSAR POWER
CAN BE TURNED OFF IN SLEEP
PINS G12, M12, H3, K1, L5, M9, A11, A9
A8, C5, B4, K10, H12 J11, M11, A1
PLACE NEAR PIN D10 D12
21
R2601
4.7
MF
1/16W
5%
402
PP3V3_RUN
PP3V3_PWRON
2
1
C2601
CERM
20%
10V
402
0.1UF
21
R2603
402
4.7
5%
1/16W
MF
21
R2605
402
4.7
5%
1/16W
MF
2
1
C2605
0.1UF
402
10V
20%
CERM
21
L2601
0603
180-OHM-1.5A
2
1
C2609
CERM
402
10V
0.1UF
20%
2
1
C2611
402
10V
20%
CERM
0.1UF
21
L2603
0603
180-OHM-1.5A
2
1
C2613
0.1UF
CERM
20%
10V
402
21
L2605
0603
180-OHM-1.5A
2
1
C2615
0.1UF
CERM
20%
10V
402
21
L2607
0603
180-OHM-1.5A
2
1
C2617
402
CERM
20%
10V
0.1UF
2
1
C2619
0.1UF
CERM
20%
10V
402
2
1
C2622
0.1UF
402
10V
20%
CERM
21
R2607
MF
1/16W
5%
4.7
402
21
L2609
180-OHM-1.5A
0603
2
1
C2620
10V
20%
CERM
0.1UF
402
2
1
C2627
CERM
20%
10V
402
0.1UF
2
1
C2628
0.1UF
402
10V
20%
CERM
2
1
C2629
CERM
20%
10V
402
0.1UF
2
1
C2630
CERM
20%
10V
402
0.1UF
2
1
C2651
CERM
20%
10V
402
0.1UF
2
1
C2623
0.1UF
402
10V
20%
CERM
2
1
C2624
0.1UF
402
10V
20%
CERM
2
1
C2625
0.1UF
402
10V
20%
CERM
2
1
C2626
0.1UF
402
10V
20%
CERM
2
1
C2631
0.1UF
402
10V
20%
CERM
2
1
C2632
0.1UF
402
10V
20%
CERM
2
1
C2633
0.1UF
402
10V
20%
CERM
2
1
C2634
0.1UF
402
10V
20%
CERM
2
1
C2635
0.1UF
402
10V
20%
CERM
2
1
C2636
0.1UF
402
10V
20%
CERM
2
1
C2637
0.1UF
402
10V
20%
CERM
2
1
C2638
0.1UF
402
10V
20%
CERM
2
1
C2665
10V
402
20%
0.1UF
CERM
2
1
C2667
CERM
20%
10V
402
0.1UF
2
1
C2671
CERM
20%
10V
402
0.1UF
2
1
C2640
402
0.1UF
10V
20%
CERM
2
1
C2639
402
CERM
0.1UF
20%
10V
21
R2609
402
4.7
5%
1/16W
MF
2
1
C2645
603
20%
CERM1
6.3V
2.2UF
2
1
C2669
603
20%
2.2UF
6.3V
CERM1
2
1
C2603
603
20%
CERM1
6.3V
2.2UF
2
1
C2607
603
20%
2.2UF
6.3V
CERM1
2
1
C2621
603
20%
CERM1
6.3V
2.2UF
C12
A3
M2
K8
D1
D12
L12
F11
C2
K12
H10
A7
A4
B7
B11
C10
A6
M5
L7
E2
H2
L2
A12
A1
M3
L8
D2
D10
M12
G12
B2
H12
K10
B4
C5
A8
A9
A11
M9
L5
E1
K1
H3
M11
J11
C9B9
E10E12
M4L3
G1F1
U2600
PULSAR
OMIT
FSBGA
PP3V3_PWRON
PP3V3_PWRON
PP3V3_PWRON
PP3V3_RUN
103
26
03
051-6532
PULSAR, PBGA
U2600
1
359S0076
PPVCORE_PWRON_PULSAR
MIN_NECK_WIDTH=10MIL
PP3V3_PSL_XTAL
MIN_LINE_WIDTH=25MIL
VOLTAGE=3.3V
MIN_NECK_WIDTH=10MIL
PP1V5_PSL_PLL1
VOLTAGE=1.5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
PP1V5_PSL_PLL3
VOLTAGE=1.5V
MIN_LINE_WIDTH=25MIL
PP2V5_PWRON_RAM
PP2V5_PWRON_RAM
PP1V2_PULSAR
MIN_NECK_WIDTH=10MIL
PP1V5_PSL_PLL2
VOLTAGE=1.5V
MIN_LINE_WIDTH=25MIL
PPVCORE_PULSAR
PP1V2_PULSAR
PPVCORE_PWRON_PULSAR
PPVCORE_PWRON_PULSAR
PPVCORE_PULSAR
PPVCORE_PULSAR
PP1V2_PULSAR
MIN_NECK_WIDTH=10MIL
PP1V5_PSL_PLL4
VOLTAGE=1.5V
MIN_LINE_WIDTH=25MIL
33
33
24
24
24
24
24
24
24
24
24
24
24
5
5
5
5
5
5
5
5
5
5
5
Preliminary
Page 25
REFCLK_1
SYM 1 OF 2
SCLK
SDATA
RESET*
XIN
XOUT
REF25
REF15
TEST3
TEST2
TEST1
ADDRSEL
REF33
REF_CML
PRES_CML
FORCESPO*
PD
VCLKN
VCLKP
HCLKN_0
HCLKN_1
HCLKN_2
GPCLK33_1
GPCLK33_0
HCLKP_0
HCLKP_2
HCLKP_1
PCLK33_1
PCLK33_0
PCLK25_1
PCLK25_0
GPCLK25_0
GPCLK25_1
PCLK33_2
PCLK33_3
PCLK33_4
HTBEN_0
HTBEN_1
NBSYNC
HSYNC_0
HSYNC_1
REFCLK_0
ERROR*
SLEWING*
PCLK12
PCLK15
SCAN_MODE
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
1.2V
MASTER: GILA
ELECTRICAL_CONSTRAINT_SET
NET_PHYSICAL_TYPE DIFFERENTIAL_PAIR
33MHZ
33MHZ
1=IIC ADDR D4/D5
PULSAR CLOCKS
66MHZ
66MHZ
33MHZ
66MHZ
66MHZ
66MHZ
3.3V
1.2V
1.2V
1.2V
1.5V
66MHZ
66MHZ
NET
TYPE
SPACING
(SLEEP)
66MHZ
NET_SPACING_TYPE
3.3V
3.3V
2.5V
2.5V
2.5V
25MHZ
25MHZ
EI_NB_SYNC IS PART OF EI_CPU_SYNC TOPOLOGY
DIFFERENTIAL SIGNALS SHOULD HAVE 5 MIL SPACING TO EACH OTHER
ALL SPACING GROUPS SHOULD HAVE 15 MIL SPACING TO SIGNALS NOT IN THEIR GROUP
3.3V
3.3V
2.5V
2.5V
2.5V
3.3V
33MHZ
0=IIC ADDR D2/D3
33MHZ
21
R2701
5%
0
I100
I101
I102
I103
21
R2704
4025%
0
21
R2706
1%
402
249
B12
C11
B3
A2
D11
E11
K3
K9
B1
C1
M1
D3
H1
G2
A5
M6
J2
G11
B6
C3
M10
L9
M7
L6
K5
L1
K2
L10
L11
F12
J12
K11
H11
J10
B5
B8
A10
C4
C8
B10
K4
L4
J1
J3
F2
M8
E3
U2600
PULSAR
OMIT
FSBGA
1
2
3
J2700
F-ST-SM
NOSTUFF
U.FL-R_SMT
21
Y2701
25.0000M
8X4.5MM-SM
CRITICAL
2
1
R2722
MF
1/16W
5%
1K
402
21
R2748
MF
1/16W
5%
0
NOSTUFF
402
I116
I117
I118
I119
21
R2703
5% 402
20
21
R2705
5%0402
21
R2707
5% 402
0
21
R2709
5% 402
20
21
R2711
5%0402
21
R2715
0
4025%
21
R2717
5% 402
0
21
R2719
5%0402
21
R2720
40205%
21
R2724
1K
402 5%
NOSTUFF
21
R2738
NOSTUFF
1K
5% 402
21
R2740
1K
1%
402
21
R2742
402
806
1%
21
R2744
1%402
681
21
R2746
1%1K402
21
R2750
0
5%
402
21
R2752
NO STUFF
402
MF
5%
0
1/16W
21
R2754
MF
1/16W
0
5%
402
21
R2756
MF
1/16W
5%
0
402
21
R2758
MF
1/16W
5%
330K
NO STUFF
402
21
R2761
40205%
2
1
R2762
24
MF
5%
402
NOSTUFF
1/16W
2
1
R2764
5%
24
1/16W
402
MF
NOSTUFF
2
1
C2705
402
33PF
CERM
50V
5%
2
1
C2707
402
33PF
5%
50V
CERM
21
R2768
5% 402
0
21
R2770
4025%
20
21
R2772
5% 402
0
21
C2708
0.001UF
50V
CERM
40210%
21
C2710
10% 402
CERM
50V
0.001UF
21
C2713
10% 402
CERM
50V
0.001UF
21
C2715
0.001UF
50V
CERM
40210%
21
C2700
10% 402
CERM
50V
0.001UF
21
C2702
40210%
CERM
50V
0.001UF
21
R2775
0
5%
402
21
R2776
5%0402
21
R2702
5%0402
21
R2779
40205%
21
R2700
5%22402
NOSTUFF
I86
I87
I90
I91
I94
I95
I96
I97
I98
I99
103
27
03
051-6532
EI_CPU_CLK_N
CLOCKS
EI_CPU_CLKEI_CPU_CLK
EI_CPU_CLK_N
EI_CPU_CLK_P
EI_CPU_CLK_P
CLOCKS
EI_CPU_CLKEI_CPU_CLK
EI_CPU_SYNC
EI_CPU_SYNC
EI_SYNC
CLOCKS
EI_CPU_CLK_N_C
CLOCKS
EI_CPU_CLK_P_C
CLOCKS
SYS_SLEEP
CLOCKS
EI_NB_SYNC_R
SB_CLK25M_ATA
PCI_CLK66M_SB_INT_R
CLOCKS
PCI_CLK_P3_R
CLOCKS
SB_CLK25M_ATA_R
CLOCKS
HT_CLK66M_SB
AGP_CLK66M_GPU_R
CLOCKS
CLOCKS
PCI_CLK_P1_R
PLS_X_OUT_B
PLS_X_IN_B
PLS_FORCE_P0_L_R
PLS_X_IN
EI_NB_SYNC
CLOCKS
HT_SB_CLK
HT_CLK66M_SB
CLOCKS
HT_NB_CLK
HT_CLK66M_NB
CLOCKS
AGP_CLK66M_GPU
TP_PLS_CLK_66M_0
EI_NB_CLK_N
PCI_CLK_P3
PCI_CLK_P1
TP_PLS_CLK_66M_1
CLOCKS
PLS_CLK_66M_1_R
EI_NB_CLK_P
PLS_XTAL
CLOCKS
PLS_EXTCLK
PCI_CLK33M_SB_EXT
CLOCKS
CLOCKS_PCI
CLOCKS_PCI
CLOCKS
PCI_CLK66M_SB_INT
EI_NB_CLK_N
EI_NB_CLK
CLOCKS
EI_NB_CLK
VSP_NB_CLKVSP_NB_CLK
VSP_NB_CLK_N
CLOCKS
TP_SATA_CLK25M
RAM_CLK66M_NB
CLOCKS
HT_CLK66M_NB_R
PCI_CLK66M_SB_INT
CPU_HTBEN
CLOCKS
PCI_CLK_GP0_R
CLOCKS
EI_CPU1_CLK_P_R
CLOCKS
EI_CPU1_CLK_N_R
CLOCKS
PCI_CLK_GP1_R
CLOCKS
EI_CPU1_SYNC_R
HT_CLK66M_NB
CPU1_HTBEN_R
CLOCKS
PLS_POWER_DOWN
VSP_NB_CLK_N
PCI_CLK_GP1
EI_NB_SYNC
PLS_RESET_L
I2C_CLOCK_SDA
PLS_X_ADDRSEL
I2C_CLOCK_SCL
SYS_SLEWING_L
CLOCKS
AGP_CLK66M_NB_R
PLS_PRES_CML
PLS_REF33
PLS_REF25
PLS_REF15
PLS_SCAN_MODE
CLOCKS
SLEWING_L_R
CLOCKS
SATA_CLK25M_R
CLOCK_ERROR_L
TP_PLS_REF_CML
TP_PLS_TEST1
TP_PLS_TEST2
TP_PLS_TEST3
AGP_CLK66M_NB
PLS_INTERM
CLOCK_RESET_L
PP3V3_PWRON
VSP_NB_CLK_P
PCI_CLK_GP0
VSP_NB_CLK_N_C
CLOCKS
AGP_NB_CLK
AGP_CLK66M_NB
CLOCKS
EI_NB_CLK_P
EI_NB_CLK
CLOCKS
EI_NB_CLK
VSP_NB_CLK VSP_NB_CLK
CLOCKS
VSP_NB_CLK_P
AGP_CLK66M_GPU
AGP_GPU_CLK
CLOCKS
CLOCKS
EI_CPU_SYNC_R
CLOCKS
CPU_HTBEN_R
PCI_CLK_P4_R
CLOCKS
CLOCKS
RAM_CLK66M_NB_R
EI_NB_CLK_P_C
CLOCKS
CLOCKS
HT_CLK66M_SB_R
PCI_CLK_P4
CLOCKS
VSP_NB_CLK_P_C
CLOCKS
PLS_CLK_66M_0_R
EI_NB_CLK_N_C
CLOCKS
PLS_X_OUT
SYS_OVERTEMP_L
PLS_EXTCLK
CLOCKS
EI_CPU1_SYNC
EI_CPU1_SYNC
CLOCKS
EI_CPU1_CLK_P
EI_CPU1_CLK EI_CPU1_CLK
CLOCKS
EI_CPU1_CLK_N
EI_CPU1_CLK EI_CPU1_CLK
23 17
11
31
15
27
27
27
27
27
27
10
44
26
44
43
37
26
26
45
45
26
25
45
28
43
25
26
23
36
17
25
36
26
25
37
13
25
25
25
25
25
25
5
23
25
25
25
25
25
25
5
5
25
25
5
25
25
22
33
25
27
5
5
5
25
5
22
5
25
18
18
13
25
13
6
22
5
25
25
22
25
5
6
25
Preliminary
Page 26
API_APCLKP
API_APCLKN
API0_SRIP1
API0_SRIN0
API0_SROP1
API0_SRON0
API0_BCLKIN
API0_BCLKIP
INTERFACE
APPLE PI
API_APCLK_AVSS
(SYM 1 OF 7)
API0_ADO35
API0_ADO36
API0_ADO37
API0_ADO38
API0_ADO39
API0_ADO40
API0_ADO41
API0_ADO43
API0_ADO42
API0_SROP0
API0_SRON1
API_QREQ0
API_CSTP
API0_ADO34
API0_ADO0
API0_ADO1
API0_ADO2
API0_ADO3
API0_ADO4
API0_ADO5
API0_ADO8
API0_ADO7
API0_ADO6
API0_ADO10
API0_ADO9
API0_ADO12
API0_ADO11
API0_ADO13
API0_BCLKON
API0_BCLKOP
API0_ADO14
API0_ADO15
API0_ADO18
API0_ADO17
API0_ADO16
API0_ADO19
API0_ADO20
API0_ADO21
API0_ADO22
API0_ADO23
API0_ADO24
API0_ADO25
API0_ADO26
API0_ADO28
API0_ADO27
API0_ADO29
API0_ADO30
API0_ADO31
API0_ADO33
API0_ADO32
VDD_API
APCLK_AVDD
API
API0_ADI3
API0_ADI2
API0_ADI1
API0_ADI0
API0_ADI5
API0_ADI4
API0_ADI13
API0_ADI12
API0_ADI11
API0_ADI10
API0_ADI9
API0_ADI8
API0_ADI7
API0_ADI6
API0_ADI15
API0_ADI14
API0_ADI17
API0_ADI18
API0_ADI19
API0_ADI20
API0_ADI21
API0_ADI22
API0_ADI23
API0_ADI16
API0_ADI24
API0_ADI33
API0_ADI32
API0_ADI31
API0_ADI25
API0_ADI26
API0_ADI30
API0_ADI29
API0_ADI28
API0_ADI27
API0_ADI34
API0_SE
API0_APSYNC
API0_ADI42
API0_ADI43
API0_ADI37
API0_ADI38
API0_ADI39
API0_ADI40
API0_ADI41
API0_SRIP0
API0_SRIN1
API_QACK0
API0_ADI36
API0_ADI35
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
U3LITE APPLE PI
NEAR U3LITE
PLACE R2805 AND R2806
DIFFERENTIAL_PAIR
NET_SPACING_TYPE
ELECTRICAL_CONSTRAINT_SET
EI_NB_CLK_N
EI_NB_CLK_P
C2820, R2803, R2804 CHANGED TO 603 FOR FMAX
MASTER: GILA
1
ZT2800
OMIT
HOLE-VIA-20R10
1
ZT2801
OMIT
HOLE-VIA-20R10
1
ZT2802
OMIT
HOLE-VIA-20R10
1
ZT2803
OMIT
HOLE-VIA-20R10
1
ZT2804
OMIT
HOLE-VIA-20R10
2
1
C2813
CERM
10V
20%
0.1UF
402
1
ZT2805
OMIT
HOLE-VIA-20R10
1
ZT2806
OMIT
HOLE-VIA-20R10
1
ZT2807
OMIT
HOLE-VIA-20R10
1
ZT2808
OMIT
HOLE-VIA-20R10
1
ZT2809
HOLE-VIA-20R10
OMIT
2
1
C2812
402
0.1UF
20%
10V
CERM
1
ZT2810
OMIT
HOLE-VIA-20R10
1
ZT2811
OMIT
HOLE-VIA-20R10
1
ZT2812
OMIT
HOLE-VIA-20R10
1
ZT2813
OMIT
HOLE-VIA-20R10
1
ZT2814
OMIT
HOLE-VIA-20R10
2
1
C2811
CERM
10V
20%
0.1UF
402
1
ZT2815
OMIT
HOLE-VIA-20R10
1
ZT2816
OMIT
HOLE-VIA-20R10
1
ZT2817
OMIT
HOLE-VIA-20R10
1
ZT2818
OMIT
HOLE-VIA-20R10
1
ZT2819
OMIT
HOLE-VIA-20R10
2
1
C2810
402
0.1UF
20%
10V
CERM
1
ZT2820
OMIT
HOLE-VIA-20R10
1
ZT2821
OMIT
HOLE-VIA-20R10
1
ZT2822
OMIT
HOLE-VIA-20R10
1
ZT2823
OMIT
HOLE-VIA-20R10
1
ZT2824
OMIT
HOLE-VIA-20R10
2
1
C2809
CERM
10V
20%
0.1UF
402
1
ZT2825
OMIT
HOLE-VIA-20R10
1
ZT2826
OMIT
HOLE-VIA-20R10
1
ZT2827
OMIT
HOLE-VIA-20R10
1
ZT2828
OMIT
HOLE-VIA-20R10
1
ZT2829
HOLE-VIA-20R10
OMIT
2
1
C2808
402
0.1UF
20%
10V
CERM
1
ZT2830
OMIT
HOLE-VIA-20R10
1
ZT2831
OMIT
HOLE-VIA-20R10
1
ZT2832
OMIT
HOLE-VIA-20R10
1
ZT2833
OMIT
HOLE-VIA-20R10
1
ZT2834
OMIT
HOLE-VIA-20R10
2
1
C2807
CERM
10V
20%
0.1UF
402
1
ZT2835
OMIT
HOLE-VIA-20R10
1
ZT2836
OMIT
HOLE-VIA-20R10
1
ZT2837
OMIT
HOLE-VIA-20R10
1
ZT2838
OMIT
HOLE-VIA-20R10
1
ZT2839
OMIT
HOLE-VIA-20R10
2
1
C2806
402
0.1UF
20%
10V
CERM
1
ZT2840
OMIT
HOLE-VIA-20R10
1
ZT2841
OMIT
HOLE-VIA-20R10
1
ZT2842
OMIT
HOLE-VIA-20R10
1
ZT2843
OMIT
HOLE-VIA-20R10
1
ZT2844
OMIT
HOLE-VIA-20R10
2
1
C2805
CERM
10V
20%
0.1UF
402
1
ZT2845
OMIT
HOLE-VIA-20R10
21
R2805
402
0
21
R2806
NOSTUFF
402
0
2
1
C2804
402
0.1UF
20%
10V
CERM
D13
D4
F10
F7G2H16
H13
J13
B19
B10
B7
D16
K8
K4
E14D14
F14
G20
F21
D18
C18
B5
A3
B6
A4
E17
D17
B18
A19
H17
D6
E6
F15
E15
E8
H2
G1
H4
J4
F2
B8
A7
B3
A2
E1
C8
A6
C1
B1
D1
B2
C6
C5
C3
C2
K1
A5
D8
E4
D5
E5
F6
J8
F3
J7
H6
J1
F5
E2
F4
E3
J6
J5
J3
H3
H5
F1
H1
J2
C9
D9
G14
H14
H12
C17
B17
A18
A17
G12
E18
F18
H18
G18
G17
F17
G15
H15
C15
B15
H11
A15
A16
C14
B14
A14
A13
E12
D12
C12
B12
G11
A12
A11
B11
C11
B9
A8
A9
A10
E11
D11
F12
F11
U3
U3LITE
PBGA
OMIT
V1.0-300MM
2
1
R2803
MF
NOSTUFF
121
1/16W
1%
402
2
1
R2804
1%
121
1/16W
MF
NOSTUFF
402
2
1
C2821
402
0.001UF
50V
CERM
NOSTUFF
10%
2
1
C2803
CERM
10V
20%
0.1UF
402
I212
I213
I214
I215
I216
I217
I218
I219
2
1
C2802
402
0.1UF
20%
10V
CERM
I220
I221
I222
I223
I224
I225
2
1
C2801
CERM
10V
20%
0.1UF
402
2
1
C2800
0.1UF
CERM
402
20%
10V
2
1
C2814
402
0.1UF
20%
10V
CERM
2
1
C2815
CERM
10V
20%
0.1UF
402
2
1
C2816
CERM
10V
20%
0.1UF
402
2
1
C2817
CERM
10V
20%
0.1UF
402
2
1
R2801
100
1%
1/16W
MF
402
NOSTUFF
2
1
C2820
NOSTUFF
0.1UF
20%
CERM
10V
402
2
1
R2802
NOSTUFF
100
1%
1/16W
MF
402
2
1
C2819
0.1UF
20%
CERM
402
10V
2
1
C2818
CERM
6.3V
10%
1UF
402
21
R2800
2.2
1/16W
5%
MF
603
1
ZT2846
HOLE-VIA-20R10
OMIT
1
ZT2847
HOLE-VIA-20R10
OMIT
1
ZT2848
HOLE-VIA-20R10
OMIT
1
ZT2849
HOLE-VIA-20R10
OMIT
1
ZT2850
HOLE-VIA-20R10
OMIT
1
ZT2851
HOLE-VIA-20R10
OMIT
1
ZT2852
HOLE-VIA-20R10
OMIT
1
ZT2853
HOLE-VIA-20R10
OMIT
1
ZT2854
HOLE-VIA-20R10
OMIT
1
ZT2855
OMIT
HOLE-VIA-20R10
1
ZT2856
OMIT
HOLE-VIA-20R10
1
ZT2857
OMIT
HOLE-VIA-20R10
1
ZT2858
OMIT
HOLE-VIA-20R10
1
ZT2859
OMIT
HOLE-VIA-20R10
1
ZT2860
OMIT
HOLE-VIA-20R10
1
ZT2861
OMIT
HOLE-VIA-20R10
1
ZT2862
OMIT
HOLE-VIA-20R10
1
ZT2863
OMIT
HOLE-VIA-20R10
1
ZT2864
OMIT
HOLE-VIA-20R10
1
ZT2865
OMIT
HOLE-VIA-20R10
1
ZT2866
HOLE-VIA-20R10
OMIT
1
ZT2867
OMIT
HOLE-VIA-20R10
1
ZT2868
OMIT
HOLE-VIA-20R10
1
ZT2869
OMIT
HOLE-VIA-20R10
051-6532
03
28
103
EI_CPU_TO_NB_CAD EI_CPU_TO_NB_CLK EI_CPU_TO_NB_SR1
EI_CPU_TO_NB_SR_N<1>
EI_CPU_TO_NB_SR_N<1>
EI_CPU_TO_NB_CAD EI_CPU_TO_NB_CLK EI_CPU_TO_NB_SR0
EI_CPU_TO_NB_SR_N<0>
EI_CPU_TO_NB_SR_N<0>
EI_CPU_TO_NB_CAD EI_CPU_TO_NB_CLK EI_CPU_TO_NB_SR1
EI_CPU_TO_NB_SR_P<1>
EI_CPU_TO_NB_SR_P<1>
EI_CPU_TO_NB_CAD EI_CPU_TO_NB_CLK EI_CPU_TO_NB_SR0
EI_CPU_TO_NB_SR_P<0>
EI_CPU_TO_NB_SR_P<0>
EI_NB_TO_CPU_CAD EI_NB_TO_CPU_CLK EI_NB_TO_CPU_SR1
EI_NB_TO_CPU_SR_N<1>
EI_NB_TO_CPU_SR_N<1>
EI_NB_TO_CPU_CAD EI_NB_TO_CPU_CLK EI_NB_TO_CPU_SR0
EI_NB_TO_CPU_SR_N<0>
EI_NB_TO_CPU_SR_N<0>
EI_NB_TO_CPU_CAD EI_NB_TO_CPU_CLK EI_NB_TO_CPU_SR1
EI_NB_TO_CPU_SR_P<1>
EI_NB_TO_CPU_SR_P<1>
EI_NB_TO_CPU_CAD EI_NB_TO_CPU_CLK EI_NB_TO_CPU_SR0
EI_NB_TO_CPU_SR_P<0>
EI_NB_TO_CPU_SR_P<0>
EI_SYNC_FROM_NB
EI_NB_CLK_P
PP1V2_EI_NB
PP1V5_PWRON_NB_AVDD
EI_NB_CLK_N
PP1V5_PWRON_EI_NB_AVDD
VOLTAGE=1.5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
EI_NB_TO_CPU_CAD
EI_NB_TO_CPU_AD
EI_NB_TO_CPU_AD<0..43>
EI_CPU_TO_NB_CAD
EI_CPU_TO_NB_AD
EI_CPU_TO_NB_AD<0..43>
PP1V2_EI_NB
EI_QACK_L
NB_APSYNC
EI_SE
EI_QREQ_L
CPU_CHKSTOP_L
EI_NB_SYNC
PP1V2_EI_NB
VOLTAGE=0.6V
EI_APCLK_VREF
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
EI_NB_TO_CPU_CLK EI_NB_TO_CPU_CLK EI_NB_TO_CPU_CLK
EI_NB_TO_CPU_CLK_P
EI_NB_TO_CPU_CLK_P
EI_NB_TO_CPU_CLK EI_NB_TO_CPU_CLK EI_NB_TO_CPU_CLK
EI_NB_TO_CPU_CLK_N
EI_NB_TO_CPU_CLK_N
EI_CPU_TO_NB_CLK_P
EI_CPU_TO_NB_CLK EI_CPU_TO_NB_CLK EI_CPU_TO_NB_CLK
EI_CPU_TO_NB_CLK_P
EI_CPU_TO_NB_CLK EI_CPU_TO_NB_CLK EI_CPU_TO_NB_CLK
EI_CPU_TO_NB_CLK_N
EI_CPU_TO_NB_CLK_N
EI_NB_TO_CPU_AD<43>
EI_NB_TO_CPU_AD<42>
EI_NB_TO_CPU_AD<41>
EI_NB_TO_CPU_AD<40>
EI_NB_TO_CPU_AD<39>
EI_NB_TO_CPU_AD<38>
EI_NB_TO_CPU_AD<37>
EI_NB_TO_CPU_AD<36>
EI_NB_TO_CPU_AD<35>
EI_NB_TO_CPU_AD<34>
EI_NB_TO_CPU_AD<33>
EI_NB_TO_CPU_AD<32>
EI_NB_TO_CPU_AD<31>
EI_NB_TO_CPU_AD<30>
EI_NB_TO_CPU_AD<29>
EI_NB_TO_CPU_AD<28>
EI_NB_TO_CPU_AD<27>
EI_NB_TO_CPU_AD<26>
EI_NB_TO_CPU_AD<25>
EI_NB_TO_CPU_AD<24>
EI_NB_TO_CPU_AD<23>
EI_NB_TO_CPU_AD<22>
EI_NB_TO_CPU_AD<21>
EI_NB_TO_CPU_AD<20>
EI_NB_TO_CPU_AD<19>
EI_NB_TO_CPU_AD<18>
EI_NB_TO_CPU_AD<17>
EI_NB_TO_CPU_AD<16>
EI_NB_TO_CPU_AD<15>
EI_NB_TO_CPU_AD<14>
EI_NB_TO_CPU_AD<13>
EI_NB_TO_CPU_AD<12>
EI_NB_TO_CPU_AD<11>
EI_NB_TO_CPU_AD<10>
EI_NB_TO_CPU_AD<9>
EI_NB_TO_CPU_AD<8>
EI_NB_TO_CPU_AD<7>
EI_NB_TO_CPU_AD<6>
EI_NB_TO_CPU_AD<5>
EI_NB_TO_CPU_AD<4>
EI_NB_TO_CPU_AD<3>
EI_NB_TO_CPU_AD<2>
EI_NB_TO_CPU_AD<1>
EI_NB_TO_CPU_AD<0>
EI_CPU_TO_NB_AD<43>
EI_CPU_TO_NB_AD<42>
EI_CPU_TO_NB_AD<41>
EI_CPU_TO_NB_AD<40>
EI_CPU_TO_NB_AD<39>
EI_CPU_TO_NB_AD<38>
EI_CPU_TO_NB_AD<37>
EI_CPU_TO_NB_AD<36>
EI_CPU_TO_NB_AD<35>
EI_CPU_TO_NB_AD<34>
EI_CPU_TO_NB_AD<33>
EI_CPU_TO_NB_AD<32>
EI_CPU_TO_NB_AD<31>
EI_CPU_TO_NB_AD<30>
EI_CPU_TO_NB_AD<29>
EI_CPU_TO_NB_AD<28>
EI_CPU_TO_NB_AD<27>
EI_CPU_TO_NB_AD<26>
EI_CPU_TO_NB_AD<25>
EI_CPU_TO_NB_AD<24>
EI_CPU_TO_NB_AD<23>
EI_CPU_TO_NB_AD<22>
EI_CPU_TO_NB_AD<21>
EI_CPU_TO_NB_AD<20>
EI_CPU_TO_NB_AD<19>
EI_CPU_TO_NB_AD<18>
EI_CPU_TO_NB_AD<17>
EI_CPU_TO_NB_AD<16>
EI_CPU_TO_NB_AD<15>
EI_CPU_TO_NB_AD<14>
EI_CPU_TO_NB_AD<13>
EI_CPU_TO_NB_AD<12>
EI_CPU_TO_NB_AD<11>
EI_CPU_TO_NB_AD<10>
EI_CPU_TO_NB_AD<9>
EI_CPU_TO_NB_AD<8>
EI_CPU_TO_NB_AD<7>
EI_CPU_TO_NB_AD<6>
EI_CPU_TO_NB_AD<5>
EI_CPU_TO_NB_AD<4>
EI_CPU_TO_NB_AD<3>
EI_CPU_TO_NB_AD<2>
EI_CPU_TO_NB_AD<1>
EI_CPU_TO_NB_AD<0>
43
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
26
36
62
62
26
26
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18
33
27
27
18
28
28
18
27
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26
26
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26
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26
26
26
26
26
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25
5
5
25
26
26
5
27
27
27
27
25
5
26
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26
26
26
26
26
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26
26
26
26
26
26
26
26
26
26
26
26
Preliminary
Page 27
(1 OF 3)
EI_ADI3
EI_ADI2
EI_ADI0
EI_CLKI
EI_ADI1
EI_CLKI*
EI_ADI11
EI_ADI10
EI_ADI8
EI_ADI4
EI_ADI9
EI_ADI7
EI_ADI6
EI_ADI5
EI_ADI12
EI_ADI21
EI_ADI18
EI_ADI20
EI_ADI19
EI_ADI16
EI_ADI17
EI_ADI15
EI_ADI14
EI_ADI13
EI_ADI22
EI_ADI23
EI_ADI24
EI_ADI28
EI_ADI29
EI_ADI31
EI_ADI30
EI_ADI25
EI_ADI26
EI_ADI27
EI_ADI32
EI_ADI42
EI_ADI38
EI_ADI35
EI_ADI39
EI_ADI41
EI_ADI40
EI_ADI34
EI_ADI37
EI_ADI36
EI_ADI33
EI_ADI43
EI_SRI0*
EI_SRI1*
CHKSTOP*
EI_SRI1
EI_SRI0
SRESET*
HRESET*
THERM_INT*
APSYNCOUT
TBEN
QACK*
PROCID0
TRIGGER_OUT
TRIGGER_IN
PROCID2
PROCID1
AVPRESET*
C1UNDGLOBAL
C2UNDGLOBAL
LSSDMODE
LSSDSCANENABLE
LSSDSTOPC2ENABLE
LSSDSTOPC2STARENABLE
LSSDSTOPENABLE
BIMODE*
AFN
MCP*
DI2*
SYNCENABLE*
RAMSTOPENABLE
PULSESEL2
PULSESEL1
PULSESEL0
PSRO1
PSRO2
RI*
INT*
QREQ*
I2CGO
APSYNCIN
CKTERMDIS
IIC_SDA
IIC_SCL
TMS
TRST*
TCK
TDO
TDI
ATTENTION
BUSCFG0
BUSCFG1
BUSCFG2
EI_DISABLE
GPUL_DBG
JTAGMODE
PLLMULT
BYPASS*
PLLLOCK
PLLRANGE0
SPARE
PLLTESTOUT
PLLRANGE1
PLLTEST
EI_SRO1*
EI_SRO1
EI_SRO0*
EI_SRO0
EI_ADO11
EI_ADO10
EI_ADO12
EI_ADO13
EI_ADO14
EI_ADO15
EI_ADO17
EI_ADO16
EI_ADO18
EI_ADO19
EI_ADO20
EI_ADO21
EI_ADO23
EI_ADO22
EI_ADO24
EI_ADO25
EI_ADO28
EI_ADO29
EI_ADO30
EI_ADO31
EI_ADO27
EI_ADO26
EI_ADO32
EI_ADO43
EI_ADO38
EI_ADO37
EI_ADO36
EI_ADO35
EI_ADO42
EI_ADO41
EI_ADO40
EI_ADO39
EI_ADO34
EI_ADO33
EI_ADO3
EI_ADO2
EI_ADO1
EI_ADO0
EI_ADO9
EI_ADO8
EI_ADO7
EI_ADO4
EI_ADO6
EI_ADO5
EI_CLKO*
EI_CLKO
SYSCLK
SYSCLK*
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
PLACE AT PROCESSOR PINS.
PROCESSOR IIC ADDRESS:
ON PAGES 31 & 32
MORE PROCESSOR DECOUPLING
PROCESSOR LOGIC I/O
PLACE BY PROCESSOR PIN.
(SEE TABLE)
80,84
NEO APPLE PI
MATCH TO SYSCLK
PLACE NEAR PROCESSOR.
MASTER: GILA
2
1
C2900
1UF
10%
6.3V
CERM
402
2
1
C2902
402
CERM
6.3V
10%
1UF
2
1
C2903
402
CERM
6.3V
10%
1UF
2
1
C2904
402
CERM
6.3V
10%
1UF
2
1
C2905
402
CERM
6.3V
10%
1UF
2
1
C2906
6.3V
402
CERM
10%
1UF
2
1
C2907
402
CERM
6.3V
10%
1UF
2
1
C2908
10%
CERM
402
6.3V
1UF
2
1
C2909
CERM
6.3V
10%
1UF
402
2
1
C2910
402
6.3V
10%
1UF
CERM
2
1
C2911
402
CERM
6.3V
10%
1UF
2
1
R2909
402
MF
1/16W
1%
100
NOSTUFF
2
1
C2901
20%
0.22UF
NOSTUFF
X5R
6.3V
402
2
1
R2907
402
100
1%
1/16W
MF
NOSTUFF
21
R2910
402
MF
0
1/16W
5%
W20
N19
N21
AD22
V22
AD13
AB21
AD21
AD17
T22
R22
AB24
AB4
AA13
AA5
AB6
AB12
V21
AC10
AB11
AC9
V5
V23
M18
M19
L19
T19
W22
AA9
AB7
AA8
T20
AD18
AD11
AD7
AD8
U19
AB5
W4
AB19
Y21
AA20
N22
V20
AA22
F1
G1
L2
L3
L22
L21
K24
L24
P20
E3
D3
D24
E24
G4
H1
H3
K2
K4
A6
A8
C10
A10
M3
C9
A9
A4
C6
C8
A7
C7
C4
B4
B6
L1
A12
C12
D8
D2
A2
A5
D6
B2
C5
C1
K3
C11
B10
A11
E12
D11
B8
G3
E2
F4
F2
H2
N3
G20
J24
H23
K22
A13
A19
C16
A17
A15
C13
A18
A20
A23
A21
C18
C19
A22
D20
B21
D18
J22
C17
C14
B19
B17
F21
B24
B23
E21
E20
C22
H22
A16
D15
C15
A14
B15
G19
G24
D22
G21
F23
J21
H21
U24
AA14
R20
AC15
AC16
V24
AB16
AC19
AA19
AC24
W23
AD12
AD14 AA10
AA12
U2900
CBGA
GPUL
CRITICAL
OMIT
21
R2901
NOSTUFF
46.4
1%
MF
402
1/16W
21
R2903
1/16W
46.4
NOSTUFF
402
MF
1%
21
R2905
NOSTUFF
1/16W
49.9
1%
402
MF
21
R2902
5%
0
1/16W
402
MF
21
R2904
NOSTUFF
1/16W
5%
402
MF
0
2
1
R2906
402
1/16W
1K
MF
5%
2
1
R2908
402
1/16W
5%
1K
MF
21
R2911
402
MF
0
NOSTUFF
1/16W
5%
2
1
C2912
402
CERM
1UF
10%
6.3V
2
1
C2913
1UF
10%
6.3V
CERM
402
2
1
C2914
1UF
10%
6.3V
CERM
402
2
1
C2915
1UF
10%
6.3V
CERM
402
2
1
C2916
1UF
10%
6.3V
CERM
402
2
1
C2917
1UF
10%
6.3V
CERM
402
2
1
C2918
1UF
10%
6.3V
CERM
402
2
1
C2919
1UF
10%
6.3V
CERM
402
2
1
C2920
1UF
10%
6.3V
CERM
402
2
1
C2921
1UF
10%
6.3V
CERM
402
2
1
C2922
1UF
10%
6.3V
CERM
402
2
1
C2923
1UF
10%
6.3V
CERM
402
2
1
C2924
1UF
10%
6.3V
CERM
402
2
1
C2925
1UF
10%
6.3V
CERM
402
2
1
C2926
1UF
10%
6.3V
CERM
402
2
1
C2927
1UF
10%
6.3V
CERM
402
2
1
C2928
1UF
10%
6.3V
CERM
402
2
1
C2929
1UF
10%
6.3V
CERM
402
2
1
C2930
1UF
10%
6.3V
CERM
402
2
1
C2931
1UF
10%
6.3V
CERM
402
2
1
C2932
1UF
10%
6.3V
CERM
402
2
1
C2933
1UF
10%
6.3V
CERM
402
2
1
C2934
1UF
10%
6.3V
CERM
402
2
1
C2935
1UF
10%
6.3V
CERM
402
2
1
C2936
1UF
10%
6.3V
CERM
402
2
1
C2937
1UF
10%
6.3V
CERM
402
2
1
C2938
1UF
10%
6.3V
CERM
402
2
1
C2939
1UF
10%
6.3V
CERM
402
2
1
C2940
1UF
10%
6.3V
CERM
402
2
1
C2941
1UF
10%
6.3V
CERM
402
2
1
C2942
1UF
10%
6.3V
CERM
402
2
1
C2943
1UF
10%
6.3V
CERM
402
2
1
C2944
1UF
10%
6.3V
CERM
402
2
1
C2945
1UF
10%
6.3V
CERM
402
2
1
C2946
1UF
10%
6.3V
CERM
402
2
1
C2947
1UF
10%
6.3V
CERM
402
2
1
C2948
1UF
10%
6.3V
CERM
402
2
1
C2949
1UF
10%
6.3V
CERM
402
2
1
C2950
10%
1UF
6.3V
CERM
402
2
1
C2951
1UF
10%
6.3V
CERM
402
2
1
C2952
CERM
6.3V
10%
1UF
402
2
1
C2953
1UF
10%
6.3V
CERM
402
2
1
C2954
1UF
10%
6.3V
CERM
402
2
1
C2955
1UF
10%
6.3V
CERM
402
2
1
C2956
1UF
10%
6.3V
CERM
402
2
1
C2957
1UF
10%
6.3V
CERM
402
2
1
C2958
1UF
6.3V
402
CERM
10%
2
1
C2959
402
1UF
10%
6.3V
CERM
2
1
C2960
CERM
1UF
10%
6.3V
402
03
051-6532
29
103
EI_CPU_TO_NB_AD<9>
EI_CPU_SYNC
CPU_APSYNC
EI_SYNC_FROM_NB
EI_CPU_TO_NB_AD<5>
EI_CPU_TO_NB_AD<7>
EI_CPU_TO_NB_AD<2>
PLLRANGE0
PLLRANGE1
PLLTEST
PLLTESTOUT
MCP_L
LSSDSTOPENABLE
LSSDSCANENABLE
LSSDMODE
DI2_L
C2UNDGLOBAL
C1UNDGLOBAL
AVPRESET_L
PROCID2
PROCID1
PROC_THERM_INT_L
CPU_SRESET_L
EI_CPU_TO_NB_SR_N<1>
EI_CPU_TO_NB_SR_N<0>
EI_CPU_TO_NB_AD<42>
EI_CPU_TO_NB_AD<37>
EI_CPU_TO_NB_AD<35>
EI_CPU_TO_NB_AD<33>
EI_CPU_TO_NB_AD<31>
EI_CPU_TO_NB_AD<10>
EI_CPU_TO_NB_AD<4>
PP1V2_EI_CPU
CPU_INT_L
EI_CPU_TO_NB_AD<39>
EI_CPU_TO_NB_AD<41>
EI_CPU_TO_NB_AD<43>
EI_CPU_TO_NB_AD<30>
EI_CPU_TO_NB_AD<38>
EI_CPU_TO_NB_AD<24>
EI_CPU_TO_NB_AD<12>
EI_CPU_TO_NB_AD<8>
EI_CPU_TO_NB_AD<6>
EI_CPU_TO_NB_AD<34>
EI_CPU_TO_NB_AD<29>
EI_CPU_TO_NB_AD<11>
PPVCORE_CPU
JTAGMODE_SPARE2
CPU_HTBEN
EI_NB_TO_CPU_AD<42>
EI_NB_TO_CPU_SR_P<0>
CHKSTOP_L
EI_NB_TO_CPU_AD<43>
EI_NB_TO_CPU_SR_P<1>
PROCID0
PP1V2_EI_CPU
EI_CPU_CLK_P
EI_CPU_CLK_N
CPU_CHKSTOP_L
CPU_SPARE
CPU_BYPASS_L
PLLLOCK
PLLMULT
JTAG_CPU_TRST_L
JTAG_CPU_TDO
JTAG_CPU_TMS
JTAG_CPU_TDI
JTAG_CPU_TCK
BUSCFG2
TP_ATTENTION
GPUL_DBG
BUSCFG1
EI_DISABLE
CKTERMDIS_L
EI_CPU_TO_NB_SR_P<1>
EI_CPU_TO_NB_AD<40>
EI_CPU_TO_NB_AD<36>
EI_CPU_TO_NB_AD<32>
EI_CPU_TO_NB_AD<26>
EI_CPU_TO_NB_AD<27>
EI_CPU_TO_NB_AD<25>
EI_CPU_TO_NB_AD<21>
EI_CPU_TO_NB_AD<23>
EI_CPU_TO_NB_AD<22>
EI_CPU_TO_NB_AD<20>
EI_CPU_TO_NB_AD<19>
EI_CPU_TO_NB_AD<15>
EI_CPU_TO_NB_AD<16>
EI_CPU_TO_NB_AD<17>
EI_CPU_TO_NB_AD<18>
EI_CPU_TO_NB_AD<14>
EI_CPU_TO_NB_AD<13>
EI_CPU_TO_NB_AD<3>
EI_CPU_TO_NB_AD<0>
EI_CPU_TO_NB_CLK_P
RAMSTOPENABLE
SYNCENABLE
RI_L
PULSESEL1
PULSESEL2
TP_PSRO1
TP_PSRO2
PULSESEL0
LSSDSTOPC2ENABLE
LSSDSTOPC2STARENABLE
BIMODE_L
TP_AFN
EI_SE
TP_PROC_TRIGGER_OUT
CPU_HRESET_L
TP_PSYNCOUT
CPU_HTBEN
EI_NB_TO_CPU_SR_N<1>
EI_QACK_L
EI_NB_TO_CPU_SR_N<0>
EI_NB_TO_CPU_AD<41>
EI_NB_TO_CPU_AD<40>
EI_NB_TO_CPU_AD<39>
EI_NB_TO_CPU_AD<38>
EI_NB_TO_CPU_AD<37>
EI_NB_TO_CPU_AD<36>
EI_NB_TO_CPU_AD<35>
EI_NB_TO_CPU_AD<34>
EI_NB_TO_CPU_AD<32>
EI_NB_TO_CPU_AD<33>
EI_NB_TO_CPU_AD<31>
EI_NB_TO_CPU_AD<30>
EI_NB_TO_CPU_AD<29>
EI_NB_TO_CPU_AD<27>
EI_NB_TO_CPU_AD<28>
EI_NB_TO_CPU_AD<26>
EI_NB_TO_CPU_AD<25>
EI_NB_TO_CPU_AD<24>
EI_NB_TO_CPU_AD<22>
EI_NB_TO_CPU_AD<23>
EI_NB_TO_CPU_AD<21>
EI_NB_TO_CPU_AD<20>
EI_NB_TO_CPU_AD<19>
EI_NB_TO_CPU_AD<18>
EI_NB_TO_CPU_AD<17>
EI_NB_TO_CPU_AD<16>
EI_NB_TO_CPU_AD<15>
EI_NB_TO_CPU_AD<14>
EI_NB_TO_CPU_AD<13>
EI_NB_TO_CPU_AD<12>
EI_NB_TO_CPU_AD<11>
EI_NB_TO_CPU_AD<10>
EI_NB_TO_CPU_AD<9>
EI_NB_TO_CPU_AD<8>
EI_NB_TO_CPU_AD<6>
EI_NB_TO_CPU_AD<5>
EI_NB_TO_CPU_AD<2>
EI_NB_TO_CPU_AD<3>
EI_NB_TO_CPU_CLK_N
EI_NB_TO_CPU_AD<1>
EI_CPU_TO_NB_AD<28>
EI_CPU_TO_NB_SR_P<0>
EI_QREQ_L
I2C_CPU_A_SCL
I2C_CPU_A_SDA
BUSCFG0
CHKSTOP_L
EI_CPU_TO_NB_CLK_N
EI_NB_TO_CPU_AD<7>
EI_NB_TO_CPU_AD<4>
EI_NB_TO_CPU_AD<0>
EI_NB_TO_CPU_CLK_P
MCP_L
I2CGO
EI_CPU_TO_NB_AD<1>
VOLTAGE=0.6V
SYSCLK_TERM
29
32
29
28
31
28
27
30
28
27
28
28
28
28
28
62
62
62
62
28
62
62
62
62
62
62
62
62
62
18
28
62
62
62
62
62
62
62
62
62
62
62
62
29
27
62
62
27
62
62
18
28
28
18
18
18
18
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
28
28
27
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
28
27
62
62
62
62
62
62
26
25
26
26
26
26
28
28
28
28
27
28
28
28
28
28
28
28
28
28
28
23
26
26
26
26
26
26
26
26
26
5
23
26
26
26
26
26
26
26
26
26
26
26
26
5
28
25
26
26
16
26
26
28
5
25
25
26
28
13
16
28
6
6
6
6
6
28
28
28
28
28
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
28
28
28
28
28
28
28
28
28
26
13
25
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
18
18
28
16
26
26
26
26
26
27
28
26
Preliminary
Page 28
TABLE_5_ITEM
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)
BOM OPTION
TABLE_5_HEAD
QTY
DESCRIPTION
PART#
REFERENCE DESIGNATOR(S)
BOM OPTION
TABLE_5_HEAD
QTY
DESCRIPTION
PART#
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)
BOM OPTION
TABLE_5_HEAD
QTY
DESCRIPTION
PART#
TABLE_5_ITEM
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)
BOM OPTION
TABLE_5_HEAD
QTY
DESCRIPTION
PART#
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)
BOM OPTION
TABLE_5_HEAD
QTY
DESCRIPTION
PART#
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
SYSTEM CONFIGURATION
SYSCLK * 8
SYSCLK * 12
PROC / 3
PROC / 8
PROC / 16
SELECT PROCESSOR CLOCK MULTIPLIER. PROCESSOR CLOCK(MHZ)= SYSTCLOCK * PLLMULT.
AVPRESET ON
SELECT ELASTIC MODE OR BYPASS.
* STUFF THESE ON Q45.
*
BYPASS MODE
PROC / 4
PROC / 6
PROC / 12
PROC / 2
CPU STRAPS
RESERVED
AVPRESET OFF
MASTER: GILA
SELECT EI BUS DIVIDER. BUS DATA RATE(BPS)= (PROCESSOR CLOCK) / BUSCFG.
*
*
SELECT PLL FREQUENCY RANGE.
*
21
R3001
402
MF
1/16W
0
5%
21
R3003
1K
5%
1/16W
MF
402
21
R3005
402
1K
5%
1/16W
MF
21
R3007
402
MF
1/16W
5%
1K
2 1
R3009
1K
5%
1/16W
MF
402
21
R3002
1K
5%
1/16W
MF
402
21
R3004
1K
5%
1/16W
MF
402
21
R3006
402
MF
1/16W
5%
1K
2
1
R3008
OMIT
402
MF
1/16W
5%
1K
2
1
R3024
OMIT
402
MF
1/16W
5%
1K
2
1
R3026
OMIT
402
MF
1/16W
5%
1K
2
1
R3028
OMIT
402
MF
1/16W
5%
1K
2
1
R3030
OMIT
MF
1/16W
5%
1K
402
2
1
R3032
OMIT
1K
5%
1/16W
MF
402
2
1
R3034
402
OMIT
MF
1/16W
5%
1K
2
1
R3012
OMIT
1K
5%
1/16W
MF
402
2
1
R3018
OMIT
1K
5%
1/16W
MF
402
2
1
R3016
OMIT
402
MF
1/16W
5%
1K
2
1
R3014
OMIT
1K
5%
MF
402
1/16W
2
1
R3010
OMIT
1K
5%
1/16W
MF
402
2
1
R3020
OMIT
402
MF
1/16W
5%
1K
2
1
R3022
OMIT
402
1K
5%
1/16W
MF
21
R3040
402
1K
5%
MF
1/16W
21
R3042
MF
5%
1K
402
1/16W
NOSTUFF
2
1
R3036
OMIT
402
1K
5%
1/16W
MF
2
1
R3038
OMIT
402
MF
1/16W
5%
1K
2
1
R3068
10K
5%
1/16W
MF
402
21
R3031
402
MF
1/16W
5%
1K
21
R3033
1K
5%
1/16W
MF
402
21
R3035
1K
5%
1/16W
MF
402
21
R3037
402
MF
1/16W
5%
1K
21
R3039
0
5%
1/16W
MF
402
21
R3041
402
MF
1/16W
5%
1K
21
R3043
402
MF
5%
1K
1/16W
21
R3045
402
MF
1/16W
5%
1K
21
R3047
1/16W
402
MF
5%
1K
21
R3049
402
MF
1/16W
5%
1K
21
R3051
402
5%
MF
1/16W
1K
21
R3053
NOSTUFF
402
MF
1/16W
5%
10K
21
R3055
1K
402
MF
1/16W
5%
21
R3057
402
1K
5%
1/16W
MF
NOSTUFF
21
R3059
1/16W
402
1K
5%
MF
21
R3061
402
1K
5%
1/16W
MF
21
R3063
402
1K
5%
1/16W
MF
NOSTUFF
21
R3065
1K
5%
1/16W
MF
402
21
R3067
NOSTUFF
1K
5%
MF
402
1/16W
21
R3069
MF
402
1/16W
5%
1K
21
R3071
NOSTUFF
MF
5%
1K
402
1/16W
21
R3073
402
1K
5%
1/16W
MF
21
R3075
402
1K
5%
1/16W
MF
NOSTUFF
21
R3077
402
NOSTUFF
MF
1/16W
5%
1K
21
R3079
1/16W
NOSTUFF
402
MF
5%
1K
21
R3081
1K
402
MF
1/16W
5%
21
R3083
402
1K
5%
1/16W
MF
21
R3085
402
1K
5%
1/16W
MF
21
R3087
402
MF
1K
5%
1/16W
21
R3089
402
MF
1/16W
5%
1K
21
R3091
402
1K
5%
1/16W
MF
21
R3093
5%
1K
1/16W
MF
402
21
R3095
10K
402
MF
1/16W
5%
21
R3097
402
5%
1/16W
MF
10K
21
R3099
402
MF
1/16W
5%
10K
21
R3000
0
5%
MF
402
1/16W
NOSTUFF
CPU_PLL_HIGH
114S1103
2
R3030,R3016
RES,1K OHM,1/16W,5%,0402
RES,1K OHM,1/16W,5%,0402
R3034
1
114S1103
EI_3TO1
CPU_PLL_MEDIUM
114S1103
2
R3014,R3032
RES,1K OHM,1/16W,5%,0402
114S1103
2
R3014,R3016
RES,1K OHM,1/16W,5%,0402
NOSTUFF
CPU_PLL_LOW
RES,1K OHM,1/16W,5%,0402
R3030,R3032
114S1103
2
03
051-6532
103
30
R3008,R3010,R3012
114S1103
3
RES,1K OHM,1/16W,5%,0402
NOSTUFF
1
114S1103
RES,1K OHM,1/16W,5%,0402
R3036
1
RES,1K OHM,1/16W,5%,0402
114S1103
R3020
NOSTUFF
114S1103
RES,1K OHM,1/16W,5%,0402
1
R3022
R3024,R3010,R3012
3
RES,1K OHM,1/16W,5%,0402
114S1103
NOSTUFF
R3008,R3026,R3012
RES,1K OHM,1/16W,5%,0402
3
114S1103
NOSTUFF
114S1103
RES,1K OHM,1/16W,5%,0402
R3008,R3026,R3028
3
NOSTUFF
RES,1K OHM,1/16W,5%,0402
R3008,R3010,R3028
114S1103
3
NOSTUFF
R3024,R3026,R3012
114S1103
3
RES,1K OHM,1/16W,5%,0402
EI_3TO1
114S1103
RES,1K OHM,1/16W,5%,0402
1
R3038
NOSTUFF
R3024,R3010,R3028
3
RES,1K OHM,1/16W,5%,0402
114S1103
NOSTUFF
RES,1K OHM,1/16W,5%,0402
1
114S1103
R3018
EI_2TO1
R3024,R3026,R3028
3
RES,1K OHM,1/16W,5%,0402
114S1103
EI_2TO1
LSSDSTOPENABLE
PLLRANGE0
BUSCFG0
PLLRANGE1
PLLMULT
EI_DISABLE
BUSCFG1
AVPRESET_L
PP1V2_EI_CPU
PP1V2_EI_CPU
PP1V2_EI_CPU
CPU_SPARE
LSSDSTOPC2STARENABLE
EI_QREQ_L
RI_L
LSSDMODE
JTAG_CPU_TCK
JTAG_CPU_TDI
JTAG_CPU_TMS
PULSESEL1
PULSESEL0
C1UNDGLOBAL
C2UNDGLOBAL
CPU_BYPASS_L
PLLTEST
JTAGMODE_SPARE2
LSSDSCANENABLE
LSSDSTOPC2ENABLE
SYNCENABLE
RAMSTOPENABLE
PULSESEL2
PROCID0
PROCID1
PROCID2
JTAG_CPU_TDO
BIMODE_L
DI2_L
CPU_INT_L
PROC_THERM_INT_L
CPU_HRESET_L
CPU_SRESET_L
I2CGO
CPU_HTBEN
CKTERMDIS_L
BUSCFG2
PLLTESTOUT
JTAG_CPU_TRST_L
JTAG_SEL
GPUL_DBG
EI_SE
PP1V2_EI_CPU
29
29
29
29
28
28
28
28
27
27
27
27
27
27
27
27
18
18
18
27
18
18
18
27
18
27
27
27
27
27
27
18
27
27
27
27
27
27
27
27
5
5
5
27
27
26
27
27
6
6
6
27
27
27
27
13
27
27
27
27
27
27
27
27
27
27
6
27
27
23
27
13
23
27
25
27
27
27
6
27
26
5
Preliminary
Page 29
X100
X99
GND
VCORE
(3 OF 3)
GND
VOUT
VIN
NOISE
CONT
KPGND2
KPVDD2KPVDD1
AVDD
X105 X105
VCORE
GND
(2 OF 3)
AGND KPGND1
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)
BOM OPTION
TABLE_5_HEAD
QTY
DESCRIPTION
PART#
TABLE_5_ITEM
PLACE ALL THESE PARTS VERY CLOSE TO U2900
0805
MASTER: GILA
CPU POWER AND BYPASS
21
R3101
1/16W
MF
5%
603
2.2
2
1
C3100
0.22UF
6.3V
20%
402
X5R
2
1
C3101
NOSTUFF
20%
0.22UF
402
6.3V
X5R
21
R3103
5%
MF
402
0
NOSTUFF
1/16W
21
R3105
NOSTUFF
0
5%
1/16W
MF
402
2
1
C3102
20%
6.3V
CERM
805
10UF
21
L3101
60-OHM-EMI
SM
21
R3127
5%
MF
1/16W
402
0
21
R3129
5%
0
1/16W
MF
402
21
R3131
MF
0
402
5%
1/16W
2
1
C3103
10%
1UF
402
6.3V
CERM
2
1
C3104
CERM
6.3V
10%
402
1UF
2
1
C3105
402
CERM
6.3V
10%
1UF
2
1
C3106
402
CERM
6.3V
10%
1UF
2
1
C3107
402
CERM
6.3V
10%
1UF
2
1
C3108
CERM
6.3V
10%
402
1UF
2
1
C3109
402
CERM
10%
1UF
6.3V
2
1
C3110
402
CERM
6.3V
10%
1UF
2
1
C3111
402
CERM
6.3V
10%
1UF
2
1
C3112
402
CERM
6.3V
1UF
10%
2
1
C3113
402
CERM
6.3V
10%
1UF
2
1
C3114
805
20%
6.3V
CERM
10UF
2
1
C3115
10UF
6.3V
20%
805
CERM
2
1
C3116
CERM
6.3V
20%
805
10UF
2
1
C3117
805
CERM
6.3V
20%
10UF
NO STUFF
2
1
C3118
402
CERM
6.3V
10%
1UF
2
1
C3119
402
CERM
6.3V
10%
1UF
2
1
C3120
402
CERM
6.3V
10%
1UF
2
1
C3121
CERM
6.3V
10%
1UF
402
2
1
C3122
402
CERM
6.3V
10%
1UF
2
1
C3123
402
CERM
6.3V
10%
1UF
2
1
C3124
402
6.3V
10%
1UF
CERM
2
1
C3125
402
CERM
6.3V
10%
1UF
2
1
C3126
402
CERM
6.3V
10%
1UF
2
1
C3127
402
CERM
6.3V
10%
1UF
2
1
C3128
6.3V
10%
1UF
CERM
402
2
1
C3129
402
CERM
6.3V
10%
1UF
2
1
C3130
402
CERM
6.3V
10%
1UF
2
1
C3131
402
CERM
10%
1UF
6.3V
2
1
C3132
402
CERM
6.3V
10%
1UF
2
1
C3133
402
CERM
10%
1UF
6.3V
2
1
C3134
402
CERM
6.3V
10%
1UF
2
1
C3135
402
6.3V
10%
1UF
CERM
2
1
C3136
CERM
6.3V
1UF
10%
402
2
1
C3137
402
CERM
6.3V
10%
1UF
2
1
C3138
402
CERM
6.3V
10%
1UF
2
1
C3139
6.3V
10%
1UF
CERM
402
2
1
C3140
402
CERM
6.3V
1UF
10%
2
1
C3141
402
CERM
6.3V
10%
1UF
2
1
C3142
402
10%
1UF
CERM
6.3V
2
1
C3143
402
CERM
10%
1UF
6.3V
2
1
C3144
1UF
402
CERM
10%
6.3V
2
1
C3145
402
CERM
6.3V
10%
1UF
2
1
C3146
6.3V
10%
1UF
CERM
402
2
1
C3147
6.3V
10%
1UF
402
CERM
AD9
AD5
AD3
AD23
AD19
AD15
AD1
AC8
AC6
AC4
AC22
AC20
AC2
AC18
AC14
AC12
AB9
AB3
AB23
AB17
AB15
AB13
AB1
AA6
AA4
AA24
AA2
AA18
AA16
Y9
Y7
Y5
Y3
Y23
Y22
Y19
Y17
Y15
Y13
Y11
W8
W6
W24
W2
W18
W16
W14
W12
W10
V9
V7
V3
V19
V17
V15
V13
V11
V1
U8
U6
U4
U22
U20
U2
U18
U16
U14
U12
U10
T9
T7
T5
T3
T23
T21
T17
T15
T13
T11
T1
R8
R6
R4
R18
R16
R14
R12
R10
P9
P7
P5
P3
P23
P21
P19
P17
P15
P13
P11
P1
AD6
AD4
AD24
AD20
AD2
AD16
AD10
AC7
AC5
AC3
AC23
AC21
AC17
AC13
AC11
AC1
AB8
AB22
AB20
AB2
AB18
AB14
AB10
AA7
AA3
AA23
AA21
AA17
AA15
AA11
Y8
Y6
Y4
Y24
Y20
Y2
Y18
Y16
Y14
Y12
Y10
W9
W7
W5
W3
W21
W19
W17
W15
W13
W11
W1
V8
V6
V4
V2
V18
V16
V14
V12
V10
U9
U7
U5
U3
U23
U21
U17
U15
U13
U11
U1
T8
T6
T4
T24
T18
T16
T14
T12
T10
R9
R7
R5
R3
R23
R21
R19
R17
R15
R13
R11
R1
P8
P6
P4
P22
P2
P18
U2900
CBGA
GPUL
21
R3132
1/16W
603
5%
MF
2.2
NOSTUFF
51
4
2
3
VR3100
OMIT
MM1572FN
SOT-25A
2
1
C3150
20%
6.3V
CERM
805
10UF
2
1
C3149
1UF
10V
CERM
603
20%
2
1
C3148
16V
CERM
20%
0.01UF
402
2
1
C3199
1UF
10%
CERM
402
6.3V
2
1
XW3100
SM
OMIT
N18
N16
N14
N12
N10
M9
M7
M5
M23
M21
C2
M17
M15
M13
M11
M1
L8
L6
L4
L20
L18
B7
L16
L14
L12
L10
K9
K7
K5
K23
K21
K19
B3
K17
K15
K13
K11
J8
J6
J4
J20
J2
J18
B20
J16
J14
J12
J10
J1
H9
H7
H5
H24
H19
B16
H17
H15
H13
H11
G8
G6
G22
G18
G16
G14
B13
G12
G10
F9
F7
F5
F3
F19
F17
F15
F13
B11
F11
E8
E6
E4
E22
E18
E16
E14
E10
E1
A24
D9
D7
D5
D23
D21
D19
D17
D13
C24
N8
N6
N4
N24
N20
N2
C20
A1
R2
Y1
T2
AA1
N5
N23
N17
N15
N13
N11
N1
M8
M6
M4
C21
M24
M22
M20
M2
M16
M14
M12
M10
L9
L7
B9
L5
L23
L17
L15
L13
L11
K8
K6
K20
K18
B5
K16
K14
K12
K10
K1
J9
J7
J5
J3
J23
B22
J19
J17
J15
J13
J11
H8
H6
H4
H20
H18
B18
H16
H14
H12
H10
G9
G7
G5
G23
G2
G17
B14
G15
G13
G11
F8
F6
F24
F22
F20
F18
F16
B12
F14
F12
F10
E9
E7
E5
E23
E19
E17
E15
B1
E13
E11
D4
D16
D14
D12
D10
D1
C3
P16
P14
P12
P10
N9
N7
C23
A3
P24
R24
U2900
GPUL
CBGA
051-6532
03
103
31
CRITICAL
CPU_AVDD_2V8
VREG MM1572FN 2.8V
353S0807
1
VR3100
CRITICAL
CPU_AVDD_2V6
VR3100
VREG MM1572FN 2.6V
1
353S0806
PP5V_RUN_CPU
VOLTAGE=2.5V
PP2V5_RUN_CPU_AVDD
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
MIN_NECK_WIDTH=8MIL
NET_SPACING_TYPE=PROC_DIFF
KPGND2
DIFFERENTIAL_PAIR=P_KP2
MIN_LINE_WIDTH=10MIL
NET_SPACING_TYPE=PROC_DIFF
MIN_NECK_WIDTH=8MIL
KPVDD2
DIFFERENTIAL_PAIR=P_KP2
MIN_LINE_WIDTH=10MIL
PPVCORE_CPU
PP1V2_EI_CPU
GND_CPU_AVDD
PP2V5_RUN_CPU_AVDD_R_L
VOLTAGE=2.5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
PP2V5_RUN_CPU
CPU_AVDD_EN
CPU_AVDD_NOISE
VOLTAGE=2.5V
MIN_NECK_WIDTH=10MIL
PP2V5_RUN_CPU_AVDD_R
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=8MIL
MIN_LINE_WIDTH=10MIL
DIFFERENTIAL_PAIR=P_TDD
NET_SPACING_TYPE=PROC_DIFF
TDIODE_POS
GND_SPARE_GND
GND_Z_OUT
GND_Z_SENSE
GND_Z_OUT
GND_Z_SENSE
PPVCORE_CPU
GND_SPARE_GND
TDIODE_NEG
DIFFERENTIAL_PAIR=P_TDD
MIN_LINE_WIDTH=10MIL
MIN_NECK_WIDTH=8MIL
NET_SPACING_TYPE=PROC_DIFF
32
32
31
31
30
28
30
29
27
29
16
27
18
27
5
5
5
5
14
32
29
29
29
29
29
5
29
32
Preliminary
Page 30
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
MASTER: GILA
PROC DECOUPLING
2
1
C3200
1UF
10%
CERM
402
6.3V
2
1
C3201
1UF
10%
CERM
402
6.3V
2
1
C3202
1UF
10%
CERM
402
6.3V
2
1
C3203
402
1UF
10%
CERM
6.3V
2
1
C3204
1UF
10%
CERM
402
6.3V
2
1
C3205
1UF
10%
CERM
402
6.3V
2
1
C3206
1UF
10%
CERM
402
6.3V
2
1
C3207
1UF
10%
CERM
402
6.3V
2
1
C3208
1UF
10%
CERM
402
6.3V
2
1
C3209
1UF
10%
CERM
402
6.3V
2
1
C3210
1UF
10%
CERM
402
6.3V
2
1
C3211
1UF
10%
CERM
402
6.3V
2
1
C3212
1UF
10%
CERM
402
6.3V
2
1
C3213
402
1UF
10%
CERM
6.3V
2
1
C3214
402
1UF
10%
CERM
6.3V
2
1
C3215
1UF
10%
CERM
402
6.3V
2
1
C3216
1UF
10%
CERM
402
6.3V
2
1
C3217
1UF
10%
CERM
402
6.3V
2
1
C3218
1UF
10%
CERM
402
6.3V
2
1
C3219
1UF
10%
CERM
402
6.3V
2
1
C3220
1UF
10%
CERM
402
6.3V
2
1
C3221
1UF
10%
CERM
402
6.3V
2
1
C3222
1UF
10%
CERM
402
6.3V
2
1
C3223
1UF
10%
CERM
402
6.3V
2
1
C3224
1UF
10%
CERM
402
6.3V
2
1
C3225
1UF
10%
CERM
402
6.3V
2
1
C3226
1UF
10%
CERM
402
6.3V
2
1
C3227
1UF
10%
CERM
402
6.3V
2
1
C3228
1UF
10%
CERM
402
6.3V
2
1
C3229
1UF
10%
CERM
402
6.3V
2
1
C3230
1UF
10%
CERM
402
6.3V
2
1
C3231
1UF
10%
CERM
402
6.3V
2
1
C3232
1UF
10%
CERM
402
6.3V
2
1
C3233
1UF
10%
CERM
402
6.3V
2
1
C3234
1UF
10%
CERM
402
6.3V
2
1
C3235
1UF
10%
CERM
402
6.3V
2
1
C3236
1UF
10%
CERM
402
6.3V
2
1
C3237
1UF
10%
CERM
402
6.3V
2
1
C3238
1UF
10%
CERM
402
6.3V
2
1
C3239
1UF
10%
CERM
402
6.3V
2
1
C3240
1UF
10%
CERM
402
6.3V
2
1
C3241
1UF
10%
CERM
402
6.3V
2
1
C3242
1UF
10%
CERM
402
6.3V
2
1
C3243
1UF
10%
CERM
402
6.3V
2
1
C3244
1UF
10%
CERM
402
6.3V
2
1
C3245
1UF
10%
CERM
402
6.3V
2
1
C3246
1UF
10%
CERM
402
6.3V
2
1
C3247
1UF
10%
CERM
402
6.3V
2
1
C3248
1UF
10%
CERM
402
6.3V
2
1
C3249
1UF
10%
CERM
402
6.3V
2
1
C3250
1UF
10%
CERM
402
6.3V
2
1
C3251
1UF
10%
CERM
402
6.3V
2
1
C3252
1UF
10%
CERM
402
6.3V
2
1
C3253
1UF
10%
CERM
402
6.3V
2
1
C3254
1UF
10%
CERM
402
6.3V
2
1
C3255
1UF
10%
CERM
402
6.3V
2
1
C3256
1UF
10%
CERM
402
6.3V
2
1
C3257
1UF
10%
CERM
402
6.3V
2
1
C3258
1UF
10%
CERM
402
6.3V
2
1
C3259
1UF
10%
CERM
402
6.3V
2
1
C3260
1UF
10%
CERM
402
6.3V
2
1
C3261
1UF
10%
CERM
402
6.3V
2
1
C3262
1UF
10%
CERM
402
6.3V
2
1
C3263
1UF
10%
CERM
402
6.3V
2
1
C3264
1UF
10%
CERM
402
6.3V
2
1
C3265
1UF
10%
CERM
402
6.3V
2
1
C3266
1UF
10%
CERM
402
6.3V
2
1
C3267
1UF
10%
CERM
402
6.3V
2
1
C3268
1UF
10%
CERM
402
6.3V
2
1
C3269
1UF
10%
CERM
402
6.3V
2
1
C3270
1UF
10%
CERM
402
6.3V
2
1
C3271
1UF
10%
CERM
402
6.3V
2
1
C3272
1UF
10%
CERM
402
6.3V
2
1
C3273
1UF
10%
CERM
402
6.3V
2
1
C3274
1UF
10%
CERM
402
6.3V
2
1
C3275
1UF
10%
CERM
402
6.3V
2
1
C3276
1UF
10%
CERM
402
6.3V
2
1
C3277
1UF
10%
CERM
402
6.3V
2
1
C3278
1UF
10%
CERM
402
6.3V
2
1
C3279
1UF
10%
CERM
402
6.3V
2
1
C3280
1UF
10%
CERM
402
6.3V
2
1
C3281
1UF
10%
CERM
402
6.3V
2
1
C3282
1UF
10%
CERM
402
6.3V
2
1
C3283
1UF
10%
CERM
402
6.3V
2
1
C3284
1UF
10%
CERM
402
6.3V
2
1
C3285
402
1UF
10%
CERM
6.3V
2
1
C3286
402
1UF
10%
CERM
6.3V
2
1
C3287
402
1UF
10%
CERM
6.3V
2
1
C3288
402
1UF
10%
CERM
6.3V
2
1
C3289
1UF
10%
CERM
402
6.3V
2
1
C3290
402
1UF
10%
CERM
6.3V
2
1
C3291
402
1UF
10%
CERM
6.3V
2
1
C3292
402
1UF
10%
CERM
6.3V
2
1
C3293
1UF
10%
CERM
402
6.3V
2
1
C3294
1UF
10%
CERM
402
6.3V
2
1
C3295
1UF
10%
CERM
402
6.3V
2
1
C3296
1UF
10%
CERM
402
6.3V
2
1
C3297
1UF
10%
CERM
402
6.3V
2
1
C3298
1UF
10%
CERM
402
6.3V
2
1
C3299
1UF
10%
CERM
402
6.3V
051-6532
103
32
03
PPVCORE_CPU
32 31 29 27
5
Preliminary
Page 31
PGND
GND
THM
PAD
VDDVCC
VROK
V+
ILIM
TIME
BSTS
BSTM
LXM
LXS
CCI
CCV
DHS
DLM
DLS
REF
DHM
D2
D3
S1
S0
D4
D1
D0
SUS
CMN
OFS
TON
SKIP*
SHDN*
CMP
OVP
CSN
OAINÂOAIN+
CSP
FB
GNDS
S
D
G
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
VID4 = 0, VID3 = 1
0.850V
(CPUVCORE_CM_P)
NC
NC
(_PPVIN_CPUVCORE)
Output
1
1.350V
0
VID0
VID4 = 1, VID3 = 0
VID2VID1 VID0VID2VID1
0
NET_SPACING_TYPE
DIFFERENTIAL_PAIR
CPU VCore Regulator
1.100V
(CPUVCORE_DLM)
(CPUVCORE_OAIN_N)
Output
0.875V
0.900V
0.925V
0.950V
1.050V
1.025V
1.000V
0.975V
REF
GND
S0
OPEN
S1
OPEN
OPEN
OPEN
VCC
OPEN
OPEN
GND
REF
VCCVCC
VCC
VCC
VCC
SUS > 2.7V
0.850V
0.825V
0.800V
0.775V
0.750V
0.725V
0.700V
0.675V
Output
S0
GND
REF
GND
S1
GND VCC
VCC
OPEN
REF
GNDREF
REF
REF
REF
Output
0.950V
0.925V
0.900V
VID0
1
0
0
1
0.875V
SHDN
0
0
1
1
0.800V
0.825V
VID1
0
0
1
1
0
0
1
1
1.150V
1.125V
0
0
0
1.075V
0
1
1
1
1
1.050V
1.025V
1.000V
0.975V
0
0
0
1
0
0
0
110
0
0
1
1
1
1
1
1
0
0
1
1
SUS = GND
1.325V
1.300V
Output
VID0
0
1
1.275V
1
1.175V
1.200V
1.225V
1.250V
0
0
1
1
VID2
0 1
0
00
0
10
0
0
1
1
1
1
1
1
1.450V
1.425V
1.400V
1.500V
Output
1.475V
1.375V
0
0
1
VID1
0
0
1
11
0
0
1
1 1
1
0
0
VID2
0
0
0
0
1
1
1
1
(CPUVCORE_LXM)
(CPUVCORE_LXS)
(CPUVCORE_BSTM)
(CPUVCORE_DLS)
(CPUVCORE_VREF)
1.525V
1.550V
(CPUVCORE_DHS)
(CPUVCORE_CS_P)
ELECTRICAL_CONSTRAINT_SET
GND
OPEN
GND
VID4 = 1, VID3 = 1
(GND_CPUVCORE)
VID4 = 0, VID3 = 0
(CPUVCORE_FB)
(CPUVCORE_DHM)
(CPUVCORE_SUS)
2
1
C3350
4.7uF
20%
25V
CERM
1206
2
1
C3351
4.7uF
1206
CERM
25V
20%
2
1
C3352
NO STUFF
20%
1206
25V
CERM
4.7uF
2
1
C3353
4.7uF
1206
CERM
25V
20%
2
1
C3354
1206
25V
20%
CERM
4.7uF
2
1
C3355
25V
1206
CERM
20%
4.7uF
2
1
C3356
NO STUFF
4.7uF
20%
25V
CERM
1206
2
1
C3357
25V
4.7uF
1206
CERM
20%
25
30
10
36
2
1
41
3
18
6
5
4
8
31
19
7
16
17
34
27
9
13
11
15
32
29
33
28
20
21
22
23
24
40
39
37
38
12
14
35
26
U3300
MAX1544
QFN
CRITICAL
21
R3300
1/16W
402
MF
5%
10
2
1
C3302
402
X5R
0.22uF
20%
6.3V
2
1
C3300
CERM
805
2.2uF
20%
10V
2
1
C3301
CERM
603
10V
20%
1uF
2
1
R3340
402
MF
1/16W
5%
0
2
1
R3307
100K
5%
MF
402
1/16W
NO STUFF
2
1
C3333
5%
100pF
402
CERM
50V
2
1
R3302
402
5%
1/16W
MF
0
NO STUFF
2
1
R3301
402
1/16W
0
5%
MF
2
1
R3303
402
1%
MF
1/16W
100K
2
1
R3304
402
1%
MF
1/16W
51.1K
2
1
C3312
402
10%
0.001uF
50V
CERM
NO STUFF
2
1
C3313
402
10%
0.001uF
CERM
50V
NO STUFF
21
L3310
0.36uH
SM-FDH1040
CRITICAL
21
L3320
SM-FDH1040
0.36uH
CRITICAL
2
1
C3323
10%
402
0.001uF
50V
CERM
NO STUFF
2
1
C3322
0.001uF
402
10%
50V
CERM
NO STUFF
2
1
C3310
25V
1uF
805
CERM
20%
2
1
C3311
CERM
805
20%
25V
1uF
2
1
C3321
20%
25V
CERM
1uF
805
2
1
C3320
20%
25V
805
1uF
CERM
21
R3316
5%
1/16W
MF
10
402
2
1
C3315
CERM
10V
20%
1uF
603
2
1
D3315
SM
MBR0540
2
1
C3316
CERM
20%
805
0.22uF
25V
2
1
C3325
20%
10V
CERM
1uF
603
2
1
D3325
MBR0540
SM
2
1
C3326
20%
25V
CERM
805
0.22uF
21
R3326
402
5%
1/16W
MF
10
2
1
C3304
100pF
50V
5%
402
CERM
2
1
C3303
50V
402
10%
CERM
470pF
2
1
R3310
2512
1W
MF
1%
0.001
CRITICAL
1
2
R3320
2512
1%
MF
1W
0.001
CRITICAL
2
1
R3305
1%
1/16W
MF
402
20K
2
1
R3306
5%
1/16W
MF
402
220K
2
1
C3306
470pF
CERM
50V
10%
402
2
1
C3370
10uF
CERM
20%
805
6.3V
2
1
C3371
805
6.3V
20%
10uF
CERM
2
1
C3372
20%
10uF
6.3V
805
CERM
2
1
C3373
805
6.3V
10uF
20%
CERM
2
1
C3374
NO STUFF
20%
10uF
6.3V
805
CERM
2
1
C3375
805
6.3V
10uF
20%
CERM
2
1
C3376
20%
CERM
10uF
6.3V
805
2
1
C3377
805
6.3V
10uF
CERM
20%
2
1
C3378
20%
CERM
10uF
6.3V
805
2
1
C3379
20%
10uF
6.3V
CERM
805
2
1
C3389
NO STUFF
805
6.3V
10uF
CERM
20%
2
1
C3388
NO STUFF
805
10uF
CERM
20%
6.3V
2
1
C3387
20%
CERM
6.3V
805
10uF
2
1
C3386
NO STUFF
6.3V
CERM
20%
805
10uF
2
1
C3385
20%
10uF
6.3V
805
CERM
2
1
C3384
10uF
20%
CERM
6.3V
805
2
1
C3383
NO STUFF
6.3V
20%
805
10uF
CERM
2
1
C3382
20%
CERM
10uF
805
6.3V
2
1
C3381
805
6.3V
10uF
CERM
20%
2
1
C3380
805
6.3V
10uF
CERM
20%
2
1
C3394
805
NO STUFF
10uF
20%
6.3V
CERM
2
1
C3393
NO STUFF
CERM
6.3V
805
10uF
20%
2
1
C3392
6.3V
CERM
10uF
20%
805
2
1
C3391
CERM
805
6.3V
20%
10uF
2
1
C3359
805
6.3V
10uF
CERM
20%
2
1
C3363
330uF
2.5V-ESR9V
20%
POLY
CASE-D2E
CRITICAL
2
1
C3362
2.5V-ESR9V
330uF
20%
POLY
CASE-D2E
CRITICAL
2
1
C3361
2.5V-ESR9V
330uF
20%
POLY
CASE-D2E
CRITICAL
2
1
C3360
2.5V-ESR9V
330uF
20%
POLY
CASE-D2E
CRITICAL
2
1
C3365
2.5V-ESR9V
330uF
20%
POLY
CASE-D2E
CRITICAL
2
1
C3367
2.5V-ESR9V
20%
330uF
POLY
CASE-D2E
CRITICAL
2
1
C3364
330uF
20%
2.5V-ESR9V
POLY
CASE-D2E
CRITICAL
2
1
C3366
20%
330uF
POLY
CRITICAL
CASE-D2E
2.5V-ESR9V
2
1
XW3360
SM
2
1
XW3361
SM
21
R3360
5%
1/16W
MF
402
10
21
R3361
5%
1/16W
MF
402
10
21
R3318
5%
1/16W
MF
0
402
21
R3319
5%
1/16W
MF
0
402
2
1
C3319
10%
NO STUFF
402
0.001uF
50V
CERM
21
R3329
402
0
MF
1/16W
5%
21
R3328
402
MF
1/16W
5%
0
2
1
C3329
10%
NO STUFF
402
0.001uF
50V
CERM
2
1
R3321
1/16W
MF
1K
402
1%
2
1
R3311
1/16W
MF
1K
1%
402
2
1
R3366
1%
402
2K
MF
1/16W
2
1
R3333
5%
1/16W
MF
402
100
2
1
C3330
10%
50V
CERM
470pF
402
2
1
R3330
5%
1/16W
MF
402
0
2
1
R3331
1/16W
5%
MF
1M
402
2
1
C3332
470pF
10%
50V
CERM
NO STUFF
402
2
1
R3332
1%
1/16W
MF
2K
402
2
1
R3312
MF
1K
1%
402
1/16W
2
1
R3322
1/16W
MF
1K
402
1%
2
1
3
Q3309
SM
2N7002
21
XW3300
SM
2
1
R3309
1/16W
402
30.1K
MF
1%
21
XW3320
SM
21
XW3310
SM
3
2
1
D3320
SBM540
PWRMITE
3
2
1
D3310
PWRMITE
SBM540
2
1
C3399
CERM
6.3V
805
NO STUFF
10uF
20%
2
1
C3398
805
CERM
6.3V
10uF
20%
2
1
C3397
NO STUFF
6.3V
805
CERM
20%
10uF
2
1
C3396
805
6.3V
CERM
20%
10uF
2
1
C3395
6.3V
10uF
CERM
20%
805
NO STUFF
21
R3399
1/16W
10K
MF
402
5%
1
2
3
4
8
7
6
5
RP3300
SM1
5%
1/16W
10K
321
4
5
Q3320
SI7392DP
SO-8-PWRPK
CRITICAL
321
4
5
Q3310
CRITICAL
SO-8-PWRPK
SI7392DP
21
R3398
MF
402
5%
1/16W
0
21
R3397
0
1/16W
5%
402
MF
2 1
R3341
1%
30.1K
1/16W
MF
402
2
1
R3370
5%
402
MF
0
1/16W
2
1
R3371
402
1/16W
5%
MF
0
NO STUFF
321
4
8765
Q3323
SI4336DY
CRITICAL
SO-8
321
4
8765
Q3312
CRITICAL
SO-8
SI4336DY
321
4
8765
Q3313
CRITICAL
SO-8
SI4336DY
321
4
8765
Q3322
CRITICAL
SO-8
SI4336DY
051-6532
03
10333
CPUVCORE_TON
CPUVCORE_OVP
CPUVCORE_FB
CPUVCORE_OFS
CPUVCORE_VREF
CPUVCORE_SKIP_L
GND_CPUVCORE
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=20 mil
VOLTAGE=0V
CPUVCORE_CM_P_R
CPUVCORE_OAIN_N
CPUVCORE_OAIN_P
CPUVCORE_CS_N_R
CPUVCORE_CS_P_R
CPU_VID<1>
MAKE_BASE=TRUE
CPUVCORE_DLM
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=25 mil
CPUVCORE_CM_P
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=25 mil
CPUVCORE_LXM
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
CPUVCORE_LXS
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=25 mil
CPUVCORE_DLS
_PPVIN_CPUVCORE
CPUVCORE_GNDS
CPUVCORE_GNDS_RC
CPUVCORE_SNS
CPUVCORE_CM_N_R
CPUVCORE_SHDN_L
MIN_LINE_WIDTH=15 mil
PP5V_CPUVCORE_VCC
VOLTAGE=5V
MIN_NECK_WIDTH=10 mil
CPUVCORE_VID<4>
CPUVCORE_TIME
CPUVCORE_SW_TIME
CPUVCORE_SNS
CPUVCORE_GNDS
THERM
CPUVCORE_CS_P
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
CPUVCORE_CS_P
CPUVCORE_CS
THERM
CPUVCORE_CS_N
CPUVCORE_CS
THERM
CPUVCORE_CM_N
CPUVCORE_CM
THERM
CPUVCORE_CM_P
CPUVCORE_CM
THERM
CPUVCORE_GNDS
CPUVCORE_GNDS
THERM
CPUVCORE_CCI
MIN_LINE_WIDTH=20 mil
CPUVCORE_BSTM_R
MIN_NECK_WIDTH=10 mil
CPU_VID<2>
CPU_VID<1>
CPU_VID<0>
SYS_SLEWING_L
CPUVCORE_BSTS_R
MIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=10 mil
CPUVCORE_CCI_C
CPU_VID<4>
MAKE_BASE=TRUE
CPUVCORE_VID<4>
MAKE_BASE=TRUE
CPU_VID<3>
CPUVCORE_VID<3>
CPUVCORE_DHM
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
_PP3V3_CPUVCORE
CPUVCORE_VID<3>
CPUVCORE_VID<4>
CPUVCORE_CCV
CPUVCORE_VID<3>
CPU_VID<2>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
CPU_VID<0>
VCORE_SWITCHING
_PP5V_CPUVCORE_VDD
MIN_LINE_WIDTH=25 mil
CPUVCORE_DHS
MIN_NECK_WIDTH=10 mil
PPVCORE_CPU
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=20 mil
CPUVCORE_BSTS
MIN_LINE_WIDTH=20 mil
CPUVCORE_BSTM
MIN_NECK_WIDTH=10 mil
CPUVCORE_ILIM
CPUVCORE_CS_N
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=25 mil
_PPVCORE_CPU_REG
CPUVCORE_GNDSENSE
NO_TEST=TRUE
CPUVCORE_SENSE
NO_TEST=TRUE
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
CPUVCORE_CM_N
32 30
25
29
31
32
32
32
32
31
31
31
23
13
31
31
27
32
13
31
5
31
31
14
31
31 31
31
31
31
31
31
13
13
13
13
6
31
13 31
5
31
31
31
13
13
14
5
5
31
5
31
Preliminary
Page 32
ALIAS
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Place close to SMU
For U3670For U3669For U3660
Place close to CPU
Place close to SMU
BUFFER
100UA CURRENT SOURCE
Place close to R3320
Place close to R3310
CPU Temp Monitoring
CPU Thermal Diode Circuit
For U3630
Place close to SMU
Place close to SMU
Place close to R3320
SMU Voltage Reference
DC GAIN = 80
CPU Current Monitoring
Place near center of CPU
CPU Voltage Monitoring
Place close to CPU Power Supply
Place XW3600 close to SMU
Place close to R3310
2
1
C3670
2.2UF
805
20%
CERM
10V
21
C3671
20%
805
CERM
10uF
6.3V
21
R3671
603
MF
1/16W
100K
0.1%
21
R3670
1/16W
0.1%
10K
FF
603
CRITICAL
2
5
1
4
3
U3669
SOT23-5
LMV2011
CRITICAL
2
5
1
4
3
U3670
LMV2011
SOT23-5
CRITICAL
21
C3676
6.3V
805
CERM
20%
10uF
21
R3676
MF
603
1/16W
100K
0.1%
21
R3672
CRITICAL
603
1/16W
FF
40.2K
0.1%
21
R3675
FF
10K
603
1/16W
0.1%
CRITICAL
21
R3677
CRITICAL
603
1/16W
FF
TD4
40.2K
0.1%
2
1
C3669
10V
CERM
20%
805
2.2UF
2
1
C3660
2.2UF
10V
CERM
20%
805
21
R3662
10K
FF
603
1/16W
0.1%
2
1
C3630
2.2UF
20%
805
10V
CERM
21
R3600
5%
1/16W
603
MF
2.2
21
XW3600
SM
21
R3661
1/16W
10K
FF
603
0.1%
CRITICAL
2
1
R3669
12.7K
1/16W
1%
603
MF
2
5
1
4
3
U3660
LMV2011
SOT23-5
CRITICAL
21
R3666
10K
603
1/16W
0.1%
FF
CRITICAL
21
R3660
20K
1/16W
0.1%
603
FF
CRITICAL
21
R3665
20K
FF
603
0.1%
1/16W
CRITICAL
2
1
R3655
NOSTUFF
1/16W
1%
MF
402
1K
2
1
R3656
0
5%
MF
1/16W
402
2
1
C3651
402
10%
50V
CERM
0.0022UF
2
1
C3650
402
10%
50V
CERM
0.0022UF
21
XW3630
SM
21
C3631
20%
0.22UF
402
6.3V
X5R
21
R3631
1%
MF
1/16W
806K
603
2
5
1
4
3
U3630
SOT23-5
LMV2011
CRITICAL
21
C3636
6.3V
0.22UF
X5R
20%
402
21
R3636
1/16W
806K
MF
603
1%
21
R3630
CRITICAL
1/16W
0.1%
603
FF
10K
21
R3635
10K
FF
603
0.1%
1/16W
CRITICAL
21
R3679
1/16W
5%
MF
402
1K
2
1
C3679
5%
50V
CERM
402
100pF
21
XW3640
SM
21
R3640
1K
402
MF
1/16W
5%
2
1
C3640
100pF
402
CERM
50V
5%
21
R3610
1%
1/16W
MF
402
10
21
R3620
10
1%
1/16W
402
MF
21
R3621
1/16W
10
1%
MF
402
21
R3611
1/16W
1%
10
402
MF
2
1
C3639
100pF
402
CERM
50V
5%
21
R3639
5%
MF
402
1K
1/16W
21
XW3621
SM
21
XW3611
SM
21
XW3620
SM
21
XW3610
SM
2
1
C3698
2.2UF
20%
10V
CERM
805
2
1
C3699
2.2UF
20%
10V
CERM
805
2
1
R3699
200
1/16W
MF
603
1%
3
12
D3699
2.5V
SSOT-23
CRITICAL
21
XW3650
SM
21
XW3651
SM
36
03
051-6532
103
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=10 mil
CORE_ISNS_N
MIN_NECK_WIDTH=10 mil
ISNS0
MIN_LINE_WIDTH=10
MIN_NECK_WIDTH=10 mil
CPU_SENSE_I_R
MIN_LINE_WIDTH=10
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=10 mil
ADC_REF
PP2V5_SMU_VREF
DAGND
_PP3V3_CPUTHERM
TD_CURRENT
DAVDD
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=10
TD_BUFFERED
DAGND
ADC_REF
DAGND
MIN_LINE_WIDTH=15
MIN_NECK_WIDTH=10 mil
DAGND
MIN_NECK_WIDTH=10 mil
CPU_SENSE_V
MIN_LINE_WIDTH=10 mil
MIN_LINE_WIDTH=10
TP_PROC_SENSE_COMMON
MIN_NECK_WIDTH=10 mil
_PP5V_CPUTHERM
GND_SMU_AVSS
DAVDD
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=10
ISNS1
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=10 mil
CORE_ISNS_P
DAGND
CPUVCORE_CM_P
CPUIMON_PHASE1_P
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=10 mil
_PPVCORE_CPU_REG
_PPVCORE_CPU_REG
MIN_LINE_WIDTH=10 mil
MIN_NECK_WIDTH=10 mil
CPUIMON_PHASE1_N
CPUVCORE_CS_P
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=10 mil
CPUIMON_PHASE2_P
GND_SMU_AVSS
CPU_SENSE_V_R
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=10 mil
GND_SMU_AVSS
DAVDD
DAVDD
MIN_LINE_WIDTH=10 mil
MIN_NECK_WIDTH=10 mil
CPU_TEMP
MIN_NECK_WIDTH=10 mil
TD1
10
MIN_NECK_WIDTH=10 mil
10
CPU_TEMP_R
ADC_REF
TD3
10
MIN_NECK_WIDTH=10 mil
MIN_NECK_WIDTH=10 mil
10
10
MIN_NECK_WIDTH=10 mil
TD2
DAGND
DAGND
DAGND
ADC_REF
DAGND
DAGND
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=15
DAVDD
PPVCORE_CPU
PPVCORE_CPU
CPUIMON_PHASE2_N
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=10 mil
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=10 mil
CPU_SENSE_I
TDIODE_POS
MIN_NECK_WIDTH=8 mil
MIN_LINE_WIDTH=10 mil
CPU_TDIODE_POS
TDIODE_NEG
CPU_TDIODE_NEG
MIN_LINE_WIDTH=10 mil
MIN_NECK_WIDTH=8 mil
32
32
31
31
32
32
32
30
30
19
32
32
19
19
29
29
17
31
31
17
17
27
27
32
5
32
5
32
32
32
32
32
13
5
13
32
32
31
5
5
31
13
13
32
32
13
32
32
32
32
32
32
32
32
5
5
13
29
29
Preliminary
Page 33
INTERFACE
DATA
MEMORY
DDR_DQ5
DDR_DQ0
DDR_DQ1
DDR_DQ2
DDR_DQ3
DDR_DQ4
DDR_DQ6
DDR_DQ7
DDR_DQ8
DDR_DQ9
DDR_DQ10
DDR_DQ11
DDR_DQ12
DDR_DQ13
DDR_DQ14
DDR_DQ15
DDR_DQ16
DDR_DQ26
DDR_DQ25
DDR_DQ24
DDR_DQ23
DDR_DQ22
DDR_DQ21
DDR_DQ20
DDR_DQ19
DDR_DQ18
DDR_DQ17
DDR_DQ36
DDR_DQ35
DDR_DQ34
DDR_DQ33
DDR_DQ32
DDR_DQ31
DDR_DQ30
DDR_DQ29
DDR_DQ28
DDR_DQ27
DDR_DQ46
DDR_DQ45
DDR_DQ44
DDR_DQ43
DDR_DQ42
DDR_DQ41
DDR_DQ40
DDR_DQ39
DDR_DQ38
DDR_DQ37
DDR_DQ47
DDR_DQ48
DDR_DQ49
DDR_DQ50
DDR_DQ51
DDR_DQ52
DDR_DQ53
DDR_DQ54
DDR_DQ55
DDR_DQ56
DDR_DQ57
DDR_DQ58
DDR_DQ59
DDR_DQ60
DDR_DQ61
DDR_DQ62
DDR_DQ63
VDD_DDR
(SYM 2 OF 7)
DDR_DQ64
DDR_DQ65
DDR_DQ69
DDR_DQ68
DDR_DQ67
DDR_DQ66
DDR_DQ70
DDR_DQ74
DDR_DQ73
DDR_DQ72
DDR_DQ71
DDR_DQ75
DDR_DQ79
DDR_DQ78
DDR_DQ77
DDR_DQ76
DDR_DQ80
DDR_DQ81
DDR_DQ82
DDR_DQ83
DDR_DQ85
DDR_DQ84
DDR_DQ90
DDR_DQ89
DDR_DQ88
DDR_DQ87
DDR_DQ86
DDR_DQ95
DDR_DQ94
DDR_DQ93
DDR_DQ92
DDR_DQ91
DDR_DQ99
DDR_DQ98
DDR_DQ97
DDR_DQ96
DDR_DQ100
DDR_DQ104
DDR_DQ105
DDR_DQ106
DDR_DQ107
DDR_DQ108
DDR_DQ109
DDR_DQ110
DDR_DQ103
DDR_DQ102
DDR_DQ101
DDR_DQ111
DDR_DQ112
DDR_DQ113
DDR_DQ114
DDR_DQ115
DDR_DQ116
DDR_DQ117
DDR_DQ118
DDR_DQ119
DDR_DQ120
DDR_DQ121
DDR_DQ127
DDR_DQ126
DDR_DQ125
DDR_DQ124
DDR_DQ123
DDR_DQ122
DDR_VREF7
DDR_VREF6
DDR_VREF5
DDR_VREF4
DDR_VREF3
INTERFACE
CONTROL
MEMORY
DDR
CLK_AVDD
VDD_DDR
(SYM 3 OF 7)
DDR_CK_D
DDR_CK_CN
DDR_CK_C
DDR_CK_BN
DDR_CK_B
DDR_CK_AN
DDR_CK_A
DDR_CK_DN
DDR_CK_EN
DDR_CK_FN
DDR_CK_F
DDR_CK_E
DDR_CLKP
DDR_CKE7
DDR_CKE6
DDR_CKE5
DDR_CKE4
DDR_CKE3
DDR_CKE1
DDR_CKE2
DDR_CKE0
DDR_VREF1
DDR_RAS
DDR_CAS
DDR_WE
DDR_BA1
DDR_BA0
DDR_MUXEN0
DDR_MAD5
DDR_MAD4
DDR_MAD3
DDR_MAD2
DDR_MAD1
DDR_MAD0
DDR_MUXEN4
DDR_MAD9
DDR_MAD8
DDR_MAD6
DDR_MAD7
DDR_MAD13
DDR_MAD12
DDR_MAD11
DDR_MAD10
DDR_CS1
DDR_CS0
DDR_CS2
DDR_CS8
DDR_CS3
DDR_CS11
DDR_CS10
DDR_CS9
DDR_DQSP1
DDR_DQSP0
DDR_DQSP2
DDR_DQSP3
DDR_DQSP8
DDR_DQSP7
DDR_DQSP6
DDR_DQSP9
DDR_DQSP10
DDR_DQSP11
DDR_DQSP12
DDR_DQSP4
DDR_DQSP5
DDR_DQSP13
DDR_DQSP15
DDR_DQSP14
DDR_CLK_AVSS
DDR_VREF2
DDR_VREF0
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
MASTER: GILA
U3LITE MEMORY
U3TWINS DO NOT HAVE MASKS
2
1
C3713
402
0.1UF
20%
10V
CERM
2
1
C3712
CERM
10V
20%
0.1UF
402
2
1
C3711
402
0.1UF
20%
10V
CERM
2
1
C3710
CERM
10V
20%
0.1UF
402
2
1
C3709
402
0.1UF
20%
10V
CERM
2
1
C3708
CERM
10V
20%
0.1UF
402
2
1
C3707
402
0.1UF
20%
10V
CERM
2
1
C3706
CERM
10V
20%
0.1UF
402
2
1
C3705
402
0.1UF
20%
10V
CERM
2
1
C3704
CERM
10V
20%
0.1UF
402
2
1
C3703
402
0.1UF
20%
10V
CERM
2
1
C3702
CERM
10V
20%
0.1UF
402
2
1
C3701
402
0.1UF
20%
10V
CERM
2
1
C3700
10V
20%
402
CERM
0.1UF
2
1
C3714
CERM
10V
20%
0.1UF
402
2
1
C3729
CERM
10V
20%
0.1UF
402
2
1
C3728
402
0.1UF
20%
10V
CERM
2
1
C3727
CERM
10V
20%
0.1UF
402
2
1
C3726
402
0.1UF
20%
10V
CERM
2
1
C3725
CERM
10V
20%
0.1UF
402
2
1
C3724
402
0.1UF
20%
10V
CERM
2
1
C3722
402
0.1UF
20%
10V
CERM
2
1
C3721
CERM
10V
20%
0.1UF
402
2
1
C3720
402
0.1UF
20%
10V
CERM
2
1
C3719
CERM
10V
20%
0.1UF
402
2
1
C3718
402
0.1UF
20%
10V
CERM
2
1
C3717
CERM
10V
20%
0.1UF
402
2
1
C3716
402
0.1UF
20%
10V
CERM
2
1
C3715
10V
20%
402
CERM
0.1UF
2
1
C3731
402
0.1UF
20%
10V
CERM
2
1
C3732
CERM
10V
20%
0.1UF
402
2
1
C3733
CERM
10V
20%
0.1UF
402
2
1
C3734
CERM
10V
20%
0.1UF
402
2
1
C3735
CERM
10V
20%
0.1UF
402
2
1
C3730
CERM
10V
20%
0.1UF
402
2
1
C3736
CERM
10V
20%
0.1UF
402
2
1
C3737
CERM
10V
20%
0.1UF
402
2
1
C3738
402
0.1UF
20%
10V
CERM
2
1
C3739
402
0.1UF
20%
10V
CERM
2
1
C3740
402
0.1UF
20%
10V
CERM
2
1
C3742
402
0.1UF
20%
10V
CERM
2
1
C3743
402
0.1UF
20%
10V
CERM
21
R3702
5%
603
MF
1/16W
2.2
2
1
C3744
0.1UF
20%
10V
CERM
402
2
1
R3700
402
MF
1%
1K
1/16W
2
1
C3745
CERM
6.3V
10%
1UF
402
2
1
C3746
402
20%
10V
CERM
0.1UF
2
1
C3747
402
0.1UF
20%
10V
CERM
2
1
C3748
402
0.1UF
20%
10V
CERM
2
1
R3701
MF
1/16W
1%
1K
402
AA16
AA13
AB25
AC19
AE27
AE22
AE16
AE13
V20
W27
W23
Y19
Y16
AG25
AG19
P27
R28
R26
R27
U26
T28
V28
U27
W28
V24
AH25
V27
V26
Y24
Y28
Y25
Y26
AA28
AA24
AA26
AA27
AH26
AD27
AC27
AC25
AC26
AF27
AD26
AE28
AF28
AG28
AD25
AD21
AD24
AF26
AG26
AE24
AF24
AG27
H22
G21
H21
J21
AD23
H23
E23
J22
F24
A26
B28
A28
A27
A24
A23
AC21
B23
B24
C23
C24
A25
A22
C27
C26
D24
D23
AB20
J23
L23
L22
M24
P22
P21
M23
M25
P23
P24
AG21
R24
P26
U23
R21
R22
P25
U22
V22
V23
U24
AH21
AA22
Y22
AA23
U25
AH28
AF23
AG24
E24
E25
C28
D28
E26
F26
E27
E28
AH27
H26
F27
H24
H25
G28
J26
J24
J25
L24
J27
AH23
H28
H27
K28
L27
L26
L25
P28
L28
N28
M28
AH24
AH22
AF20
U3
PBGA
OMIT
V1.0-300MM
U3LITE
B25
D27
D22
F19
G25
K27
K23
K19
M19
N25
N21
P20
T25
T21
T19
AC23
J20
V21
M21
AA21
H20
L21
U21
Y21
AE21
AH18
AH16
AF15
AG15
AC12
AD12
AE12
AF12
AH15
AH14
AG17
AH17
AG14
AF14
AH13
AG12
AD28
AE23
F23
B27
B26
M22
R23
Y23
F25
F28
J28
M27
U28
Y27
AG23
AC24
AD18
AC18
AH20
AG20
AH19
AG18
AE18
AF18
AA20
AB21
AC20
AB15
AA15
AC15
AD15
AD14
AC14
AE14
AE15
AA14
AB14
AB12
AA12
AA18
AB18
AA17
AB17
AF17
AE17
AD17
AC17
AD20
AE20
AF21
U3
OMIT
V1.0-300MM
U3LITE
PBGA
03
37
103
051-6532
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=1.25V
PP1V25_PWRON_RAM_VREF_NB
RAM_CLK_E_N_R
PP1V5_PWRON_RAM_NB_AVDD
VOLTAGE=1.5V
MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=25MIL
RAM_DQ_R<64>
RAM_DQ_R<71>
RAM_DQ_R<75>
RAM_DQS_R<15>
RAM_DQS_R<14>
RAM_DQS_R<12>
RAM_DQS_R<13>
RAM_DQS_R<11>
RAM_DQS_R<9>
RAM_DQS_R<10>
RAM_DQS_R<8>
RAM_DQS_R<7>
RAM_DQS_R<6>
RAM_DQS_R<5>
RAM_DQS_R<4>
RAM_DQS_R<3>
RAM_DQS_R<2>
RAM_DQS_R<1>
RAM_DQS_R<0>
RAM_CS_L_R<9>
RAM_CS_L_R<8>
RAM_CS_L_R<1>
RAM_CS_L_R<0>
RAM_A_R<13>
RAM_A_R<12>
RAM_A_R<11>
RAM_A_R<10>
RAM_A_R<9>
RAM_A_R<8>
RAM_A_R<7>
RAM_A_R<3>
RAM_A_R<4>
RAM_A_R<2>
RAM_A_R<1>
RAM_A_R<0>
RAM_BA_R<0>
RAM_WE_L_R
RAM_CAS_L_R
RAM_RAS_L_R
RAM_DQ_R<127>
RAM_DQ_R<126>
RAM_DQ_R<124>
RAM_DQ_R<125>
RAM_DQ_R<121>
RAM_DQ_R<123>
RAM_DQ_R<122>
RAM_DQ_R<119>
RAM_DQ_R<120>
RAM_DQ_R<117>
RAM_DQ_R<118>
RAM_DQ_R<116>
RAM_DQ_R<114>
RAM_DQ_R<115>
RAM_DQ_R<111>
RAM_DQ_R<113>
RAM_DQ_R<112>
RAM_DQ_R<110>
RAM_DQ_R<109>
RAM_DQ_R<108>
RAM_DQ_R<107>
RAM_DQ_R<106>
RAM_DQ_R<104>
RAM_DQ_R<105>
RAM_DQ_R<103>
RAM_DQ_R<101>
RAM_DQ_R<102>
RAM_DQ_R<99>
RAM_DQ_R<98>
RAM_DQ_R<100>
RAM_DQ_R<96>
RAM_DQ_R<97>
RAM_DQ_R<94>
RAM_DQ_R<95>
RAM_DQ_R<93>
RAM_DQ_R<91>
RAM_DQ_R<92>
RAM_DQ_R<89>
RAM_DQ_R<90>
RAM_DQ_R<88>
RAM_DQ_R<86>
RAM_DQ_R<87>
RAM_DQ_R<85>
RAM_DQ_R<84>
RAM_DQ_R<83>
RAM_DQ_R<81>
RAM_DQ_R<80>
RAM_DQ_R<82>
RAM_DQ_R<79>
RAM_DQ_R<76>
RAM_DQ_R<77>
RAM_DQ_R<74>
RAM_DQ_R<73>
RAM_DQ_R<70>
RAM_DQ_R<72>
RAM_DQ_R<69>
RAM_DQ_R<68>
RAM_DQ_R<65>
RAM_DQ_R<67>
RAM_DQ_R<59>
RAM_DQ_R<0>
RAM_DQ_R<5>
RAM_DQ_R<3>
RAM_DQ_R<2>
RAM_DQ_R<4>
RAM_DQ_R<10>
RAM_DQ_R<6>
RAM_DQ_R<7>
RAM_DQ_R<8>
RAM_DQ_R<9>
RAM_DQ_R<11>
RAM_DQ_R<15>
RAM_DQ_R<12>
RAM_DQ_R<13>
RAM_DQ_R<14>
RAM_DQ_R<16>
RAM_DQ_R<21>
RAM_DQ_R<20>
RAM_DQ_R<19>
RAM_DQ_R<17>
RAM_DQ_R<18>
RAM_DQ_R<26>
RAM_DQ_R<22>
RAM_DQ_R<23>
RAM_DQ_R<24>
RAM_DQ_R<25>
RAM_DQ_R<31>
RAM_DQ_R<27>
RAM_DQ_R<28>
RAM_DQ_R<29>
RAM_DQ_R<30>
RAM_DQ_R<36>
RAM_DQ_R<32>
RAM_DQ_R<33>
RAM_DQ_R<34>
RAM_DQ_R<35>
RAM_DQ_R<41>
RAM_DQ_R<37>
RAM_DQ_R<38>
RAM_DQ_R<39>
RAM_DQ_R<40>
RAM_DQ_R<46>
RAM_DQ_R<45>
RAM_DQ_R<44>
RAM_DQ_R<43>
RAM_DQ_R<42>
RAM_DQ_R<51>
RAM_DQ_R<47>
RAM_DQ_R<48>
RAM_DQ_R<49>
RAM_DQ_R<50>
RAM_DQ_R<52>
RAM_DQ_R<56>
RAM_DQ_R<55>
RAM_DQ_R<54>
RAM_DQ_R<53>
RAM_DQ_R<57>
RAM_DQ_R<60>
RAM_DQ_R<58>
RAM_DQ_R<61>
RAM_DQ_R<62>
RAM_DQ_R<63>
RAM_DQ_R<1>
RAM_DQ_R<66>
RAM_CKE_R<7>
RAM_BA_R<1>
RAM_MUXEN4
RAM_MUXEN0
RAM_CS_L_R<3>
RAM_CS_L_R<2>
RAM_CS_L_R<11>
RAM_CS_L_R<10>
RAM_CKE_R<5>
RAM_CKE_R<1>
RAM_CLK_F_P_R
RAM_CLK_E_P_R
RAM_CKE_R<0>
RAM_CKE_R<4>
RAM_CKE_R<6>
RAM_CKE_R<3>
RAM_CLK_D_N_R
RAM_CLK_C_N_R
RAM_CLK_D_P_R
RAM_CLK_C_P_R
RAM_CLK_A_N_R
RAM_CLK_B_N_R
RAM_CLK_B_P_R
PP1V5_PWRON_NB_AVDD
RAM_CKE_R<2>
RAM_CLK_F_N_R
RAM_DQ_R<78>
RAM_A_R<5>
RAM_CLK_A_P_R
RAM_CLK66M_NB
RAM_A_R<6>
PP2V5_PWRON_RAM
PP2V5_PWRON_RAM
PP2V5_PWRON_RAM
PP2V5_PWRON_RAM
43 36
33
33
33
33
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
26
62
62
62
62
24
24
24
24
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
5
34
5
5
5
5
5
5
34
34
34
34
34
34
5
5
34
34
34
34
34
34
34
5
5
34
34
34
34
25
34
5
5
5
5
Preliminary
Page 34
ALIAS
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ALIAS
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ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
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ALIAS
ALIAS
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ALIAS
ALIAS
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ALIAS
ALIAS
ALIAS
ALIAS
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ALIAS
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ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
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D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
into self refresh during sleep
CKE pulldowns to put RAM
Series Termination for Clock/Control Signals
RPAKs can be swapped if the 3rd number in reference designator (RP38x0) is the same.
BA
CNTL
CS
CKE
ADDR
CLOCKS
DIMM "B"
No series termination on data signals
DIMM "A"
No series termination on strobe signals
NOTE: SO-DIMMs only use 2 of the 3 clocks
(NONE)
Signal aliases required by this page:
(NONE)
Page Notes
Power aliases required by this page:
Memory Series Term
(NONE)
Unused clocks renamed below.
provided for each DIMM module.
BOM options provided by this page:
63
RP3801
SM1
22
1/16W
5%
54
RP3801
5%
1/16W
SM1
22
81
RP3801
1/16W
22
SM1
5%
72
RP3801
22
SM1
5%
1/16W
72
RP3810
1/16W
22
SM1
5%
81
RP3810
22
SM1
1/16W
5%
63
RP3810
SM1
5%
1/16W
22
54
RP3810
SM1
5%
1/16W
22
54
RP3820
SM1
5%
1/16W
22
63
RP3820
SM1
5%
1/16W
22
81
RP3820
5%
1/16W
SM1
22
72
RP3820
SM1
22
1/16W
5%
72
RP3830
22
SM1
1/16W
5%
54
RP3830
5%
1/16W
SM1
22
81
RP3830
1/16W
5%
SM1
22
63
RP3830
22
SM1
1/16W
5%
72
RP3831
5%
1/16W
SM1
22
81
RP3831
22
SM1
1/16W
5%
63
RP3831
SM1
22
1/16W
5%
54
RP3831
SM1
5%
1/16W
22
63
RP3832
SM1
5%
1/16W
22
54
RP3832
SM1
22
1/16W
5%
81
RP3832
SM1
22
1/16W
5%
72
RP3832
SM1
22
1/16W
5%
54
RP3833
SM1
1/16W
5%
22
72
RP3833
SM1
5%
1/16W
22
81
RP3833
SM1
22
5%
1/16W
21
R3841
5%
1/16W
MF
402
22
21
R3842
402
22
MF
1/16W
5%
63
RP3833
22
SM1
1/16W
5%
21
R3840
5%
1/16W
MF
402
22
72
RP3850
SM1
1/16W
5%
10K
54
RP3850
10K
5%
1/16W
SM1
81
RP3850
1/16W
SM1
5%
10K
63
RP3850
10K
5%
1/16W
SM1
81
RP3800
SM1
5%
1/16W
22
72
RP3800
SM1
22
1/16W
5%
54
RP3800
SM1
22
1/16W
5%
63
RP3800
5%
1/16W
SM1
22
38 103
051-6532
03
RAM_CKE<5>
RAM_CKE<4>
RAM_CLK_E_N_R
RAM_CLK_A_N
RAM_CLK_A_P_R
RAM_CLK_B_P_R
RAM_CS_L_R<9>
RAM_CLK_C_N_R
MAKE_BASE=TRUE
TP_RAM_CLK_C_N
RAM_CLK_F_P_R
MAKE_BASE=TRUE
TP_RAM_CLK_F_P
RAM_CLK_F_N_R
MAKE_BASE=TRUE
TP_RAM_CLK_F_N
RAM_CLK_C_P_R
MAKE_BASE=TRUE
TP_RAM_CLK_C_P
RAM_DQS<1>
MAKE_BASE=TRUE
RAM_DQS_R<1>
RAM_DQS<0>
MAKE_BASE=TRUE
RAM_DQS_R<0>
MAKE_BASE=TRUE
RAM_DQS<2>
RAM_DQS_R<2>
MAKE_BASE=TRUE
RAM_DQS<3>
RAM_DQS_R<3>
RAM_DQS<4>
MAKE_BASE=TRUE
RAM_DQS_R<4>
RAM_DQS<5>
MAKE_BASE=TRUE
RAM_DQS_R<5>
RAM_DQS<6>
MAKE_BASE=TRUE
RAM_DQS_R<6>
RAM_DQS<8>
MAKE_BASE=TRUE
RAM_DQS_R<8>
RAM_DQS<7>
MAKE_BASE=TRUE
RAM_DQS_R<7>
RAM_DQS<9>
MAKE_BASE=TRUE
RAM_DQS_R<9>
RAM_DQS<10>
MAKE_BASE=TRUE
RAM_DQS_R<10>
RAM_DQS<11>
MAKE_BASE=TRUE
RAM_DQS_R<11>
RAM_DQS<12>
MAKE_BASE=TRUE
RAM_DQS_R<12>
RAM_DQS<13>
MAKE_BASE=TRUE
RAM_DQS_R<13>
RAM_DQS<14>
MAKE_BASE=TRUE
RAM_DQS_R<14>
RAM_DQS<15>
MAKE_BASE=TRUE
RAM_DQS_R<15>
MAKE_BASE=TRUE
RAM_DQ<62>
RAM_DQ_R<62>
MAKE_BASE=TRUE
RAM_DQ<63>
RAM_DQ_R<63>
MAKE_BASE=TRUE
RAM_DQ<61>
RAM_DQ_R<61>
MAKE_BASE=TRUE
RAM_DQ<60>
RAM_DQ_R<60>
MAKE_BASE=TRUE
RAM_DQ<59>
RAM_DQ_R<59>
MAKE_BASE=TRUE
RAM_DQ<58>
RAM_DQ_R<58>
MAKE_BASE=TRUE
RAM_DQ<55>
RAM_DQ_R<55>
MAKE_BASE=TRUE
RAM_DQ<57>
RAM_DQ_R<57>
MAKE_BASE=TRUE
RAM_DQ<56>
RAM_DQ_R<56>
MAKE_BASE=TRUE
RAM_DQ<53>
RAM_DQ_R<53>
MAKE_BASE=TRUE
RAM_DQ<54>
RAM_DQ_R<54>
MAKE_BASE=TRUE
RAM_DQ<52>
RAM_DQ_R<52>
MAKE_BASE=TRUE
RAM_DQ<51>
RAM_DQ_R<51>
MAKE_BASE=TRUE
RAM_DQ<49>
RAM_DQ_R<49>
MAKE_BASE=TRUE
RAM_DQ<48>
RAM_DQ_R<48>
MAKE_BASE=TRUE
RAM_DQ<50>
RAM_DQ_R<50>
MAKE_BASE=TRUE
RAM_DQ<45>
RAM_DQ_R<45>
MAKE_BASE=TRUE
RAM_DQ<47>
RAM_DQ_R<47>
MAKE_BASE=TRUE
RAM_DQ<46>
RAM_DQ_R<46>
MAKE_BASE=TRUE
RAM_DQ<44>
RAM_DQ_R<44>
MAKE_BASE=TRUE
RAM_DQ<43>
RAM_DQ_R<43>
MAKE_BASE=TRUE
RAM_DQ<42>
RAM_DQ_R<42>
MAKE_BASE=TRUE
RAM_DQ<41>
RAM_DQ_R<41>
MAKE_BASE=TRUE
RAM_DQ<39>
RAM_DQ_R<39>
MAKE_BASE=TRUE
RAM_DQ<38>
RAM_DQ_R<38>
MAKE_BASE=TRUE
RAM_DQ<40>
RAM_DQ_R<40>
MAKE_BASE=TRUE
RAM_DQ<37>
RAM_DQ_R<37>
MAKE_BASE=TRUE
RAM_DQ<36>
RAM_DQ_R<36>
MAKE_BASE=TRUE
RAM_DQ<35>
RAM_DQ_R<35>
MAKE_BASE=TRUE
RAM_DQ<34>
RAM_DQ_R<34>
MAKE_BASE=TRUE
RAM_DQ<31>
RAM_DQ_R<31>
MAKE_BASE=TRUE
RAM_DQ<32>
RAM_DQ_R<32>
MAKE_BASE=TRUE
RAM_DQ<33>
RAM_DQ_R<33>
MAKE_BASE=TRUE
RAM_DQ<29>
RAM_DQ_R<29>
MAKE_BASE=TRUE
RAM_DQ<30>
MAKE_BASE=TRUE
RAM_DQ<27>
RAM_DQ_R<27>
RAM_DQ_R<28>
MAKE_BASE=TRUE
RAM_DQ<25>
RAM_DQ_R<25>
MAKE_BASE=TRUE
RAM_DQ<24>
RAM_DQ_R<24>
MAKE_BASE=TRUE
RAM_DQ<26>
RAM_DQ_R<26>
MAKE_BASE=TRUE
RAM_DQ<21>
RAM_DQ_R<21>
MAKE_BASE=TRUE
RAM_DQ<23>
RAM_DQ_R<23>
MAKE_BASE=TRUE
RAM_DQ<22>
RAM_DQ_R<22>
MAKE_BASE=TRUE
RAM_DQ<20>
RAM_DQ_R<20>
MAKE_BASE=TRUE
RAM_DQ<19>
RAM_DQ_R<19>
MAKE_BASE=TRUE
RAM_DQ<18>
RAM_DQ_R<18>
RAM_DQ_R<17>
RAM_DQ<14>
MAKE_BASE=TRUE
RAM_DQ_R<14>
RAM_DQ_R<16>
MAKE_BASE=TRUE
RAM_DQ<15>
RAM_DQ_R<15>
MAKE_BASE=TRUE
RAM_DQ<13>
RAM_DQ_R<13>
MAKE_BASE=TRUE
RAM_DQ<12>
RAM_DQ_R<12>
MAKE_BASE=TRUE
RAM_DQ<11>
RAM_DQ_R<11>
MAKE_BASE=TRUE
RAM_DQ<10>
RAM_DQ_R<10>
MAKE_BASE=TRUE
RAM_DQ<7>
RAM_DQ_R<7>
MAKE_BASE=TRUE
RAM_DQ<8>
RAM_DQ_R<8>
MAKE_BASE=TRUE
RAM_DQ<9>
RAM_DQ_R<9>
MAKE_BASE=TRUE
RAM_DQ<4>
RAM_DQ_R<4>
MAKE_BASE=TRUE
RAM_DQ<6>
RAM_DQ_R<6>
MAKE_BASE=TRUE
RAM_DQ<5>
RAM_DQ_R<5>
MAKE_BASE=TRUE
RAM_DQ<3>
RAM_DQ_R<3>
MAKE_BASE=TRUE
RAM_DQ<2>
RAM_DQ_R<2>
MAKE_BASE=TRUE
RAM_DQ<0>
RAM_DQ_R<0>
MAKE_BASE=TRUE
RAM_DQ<1>
RAM_DQ_R<1>
MAKE_BASE=TRUE
RAM_DQ<127>
RAM_DQ_R<127>
MAKE_BASE=TRUE
RAM_DQ<126>
RAM_DQ_R<126>
MAKE_BASE=TRUE
RAM_DQ<125>
RAM_DQ_R<125>
MAKE_BASE=TRUE
RAM_DQ<124>
RAM_DQ_R<124>
MAKE_BASE=TRUE
RAM_DQ<123>
RAM_DQ_R<123>
MAKE_BASE=TRUE
RAM_DQ<122>
RAM_DQ_R<122>
MAKE_BASE=TRUE
RAM_DQ<119>
RAM_DQ_R<119>
MAKE_BASE=TRUE
RAM_DQ<121>
RAM_DQ_R<121>
MAKE_BASE=TRUE
RAM_DQ<120>
RAM_DQ_R<120>
MAKE_BASE=TRUE
RAM_DQ<116>
RAM_DQ_R<116>
MAKE_BASE=TRUE
RAM_DQ<117>
RAM_DQ_R<117>
MAKE_BASE=TRUE
RAM_DQ<118>
RAM_DQ_R<118>
MAKE_BASE=TRUE
RAM_DQ<115>
RAM_DQ_R<115>
MAKE_BASE=TRUE
RAM_DQ<112>
RAM_DQ_R<112>
MAKE_BASE=TRUE
RAM_DQ<113>
RAM_DQ_R<113>
MAKE_BASE=TRUE
RAM_DQ<114>
RAM_DQ_R<114>
MAKE_BASE=TRUE
RAM_DQ<111>
RAM_DQ_R<111>
MAKE_BASE=TRUE
RAM_DQ<110>
RAM_DQ_R<110>
MAKE_BASE=TRUE
RAM_DQ<109>
RAM_DQ_R<109>
MAKE_BASE=TRUE
RAM_DQ<108>
RAM_DQ_R<108>
MAKE_BASE=TRUE
RAM_DQ<105>
RAM_DQ_R<105>
MAKE_BASE=TRUE
RAM_DQ<106>
RAM_DQ_R<106>
MAKE_BASE=TRUE
RAM_DQ<107>
RAM_DQ_R<107>
MAKE_BASE=TRUE
RAM_DQ<104>
RAM_DQ_R<104>
MAKE_BASE=TRUE
RAM_DQ<103>
RAM_DQ_R<103>
MAKE_BASE=TRUE
RAM_DQ<102>
RAM_DQ_R<102>
MAKE_BASE=TRUE
RAM_DQ<98>
RAM_DQ_R<98>
MAKE_BASE=TRUE
RAM_DQ<100>
RAM_DQ_R<100>
MAKE_BASE=TRUE
RAM_DQ<101>
RAM_DQ_R<101>
MAKE_BASE=TRUE
RAM_DQ<99>
RAM_DQ_R<99>
MAKE_BASE=TRUE
RAM_DQ<97>
RAM_DQ_R<97>
MAKE_BASE=TRUE
RAM_DQ<96>
RAM_DQ_R<96>
MAKE_BASE=TRUE
RAM_DQ<95>
RAM_DQ_R<95>
MAKE_BASE=TRUE
RAM_DQ<92>
RAM_DQ_R<92>
MAKE_BASE=TRUE
RAM_DQ<91>
RAM_DQ_R<91>
MAKE_BASE=TRUE
RAM_DQ<94>
RAM_DQ_R<94>
MAKE_BASE=TRUE
RAM_DQ<93>
RAM_DQ_R<93>
MAKE_BASE=TRUE
RAM_DQ<90>
RAM_DQ_R<90>
MAKE_BASE=TRUE
RAM_DQ<88>
RAM_DQ_R<88>
MAKE_BASE=TRUE
RAM_DQ<89>
RAM_DQ_R<89>
MAKE_BASE=TRUE
RAM_DQ<85>
MAKE_BASE=TRUE
RAM_DQ<87>
RAM_DQ_R<87>
MAKE_BASE=TRUE
RAM_DQ<86>
RAM_DQ_R<86>
MAKE_BASE=TRUE
RAM_DQ<84>
RAM_DQ_R<84>
MAKE_BASE=TRUE
RAM_DQ<83>
RAM_DQ_R<83>
MAKE_BASE=TRUE
RAM_DQ<81>
RAM_DQ_R<81>
MAKE_BASE=TRUE
RAM_DQ<82>
RAM_DQ_R<82>
MAKE_BASE=TRUE
RAM_DQ<79>
RAM_DQ_R<79>
MAKE_BASE=TRUE
RAM_DQ<80>
RAM_DQ_R<80>
MAKE_BASE=TRUE
RAM_DQ<78>
RAM_DQ_R<78>
MAKE_BASE=TRUE
RAM_DQ<75>
RAM_DQ_R<75>
MAKE_BASE=TRUE
RAM_DQ<77>
RAM_DQ_R<77>
MAKE_BASE=TRUE
RAM_DQ<76>
RAM_DQ_R<76>
MAKE_BASE=TRUE
RAM_DQ<74>
RAM_DQ_R<74>
MAKE_BASE=TRUE
RAM_DQ<71>
RAM_DQ_R<71>
MAKE_BASE=TRUE
RAM_DQ<72>
RAM_DQ_R<72>
MAKE_BASE=TRUE
RAM_DQ<73>
RAM_DQ_R<73>
MAKE_BASE=TRUE
RAM_DQ<70>
RAM_DQ_R<70>
MAKE_BASE=TRUE
RAM_DQ<69>
RAM_DQ_R<69>
MAKE_BASE=TRUE
RAM_DQ<68>
RAM_DQ_R<68>
RAM_DQ<67>
MAKE_BASE=TRUE
RAM_DQ_R<67>
MAKE_BASE=TRUE
RAM_DQ<65>
RAM_DQ_R<65>
RAM_DQ<64>
MAKE_BASE=TRUE
RAM_DQ_R<64>
MAKE_BASE=TRUE
RAM_DQ<66>
RAM_DQ_R<66>
RAM_CLK_E_N
RAM_CLK_E_P_R
RAM_CLK_E_P
RAM_CLK_D_N_R
RAM_CLK_D_N
RAM_CLK_B_N_R
RAM_CLK_B_N
RAM_CLK_A_N_R
RAM_CLK_D_P_R
RAM_CLK_D_P
RAM_CLK_A_P
RAM_A_R<9>
RAM_A<9>
RAM_A<12>
RAM_A_R<10>
RAM_A<10>
RAM_A_R<8>
RAM_A<8>
RAM_A_R<7>
RAM_A<7>
RAM_A_R<5>
RAM_A<5>
RAM_A_R<1>
RAM_A<1>
RAM_A_R<6>
RAM_A<6>
RAM_A_R<4>
RAM_A<4>
RAM_A<2>
RAM_CS_L<9>
RAM_A_R<0>
RAM_A<0>
RAM_CS_L_R<8>
RAM_CS_L<8>
RAM_CS_L_R<1>
RAM_CS_L<1>
RAM_CS_L_R<0>
RAM_CS_L<0>
RAM_A_R<12>
RAM_A_R<11>
RAM_A<11>
RAM_A_R<13>
RAM_BA_R<0>
RAM_BA<0>
RAM_BA_R<1>
RAM_BA<1>
RAM_WE_L_R
RAM_WE_L
RAM_CAS_L_R
RAM_RAS_L
RAM_RAS_L_R
RAM_A<3>
RAM_A_R<2>
RAM_CLK_B_P
MAKE_BASE=TRUE
RAM_DQ<16>
MAKE_BASE=TRUE
RAM_DQ<17>
RAM_DQ_R<85>
MAKE_BASE=TRUE
RAM_DQ<28>
RAM_DQ_R<30>
RAM_CAS_L
RAM_A<13>
RAM_CKE_R<5>
RAM_CKE_R<1>
RAM_CKE_R<4>
RAM_CKE_R<0>
RAM_A_R<3>
RAM_CKE<5>
RAM_CKE<1>
RAM_CKE<4>
RAM_CKE<0>
RAM_CKE<1>
RAM_CKE<0>
62
62
62
62
62
62
62
62
35
35
62
62
62
62
62
62 62
62 62
62 62
62 62
62 62
62 62
62 62
62 62
62 62
62 62
62 62
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62 62
62 62
62 62
62 62
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62 62
62 62
62 62
62 62
62 62
62 62
62 62
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62 62
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62
62 62
62
62 62
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62
62 62
62
62 62
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62
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62
62 62
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62
62 62
62
62 62
62
62 62
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62 62
62
62
62 62
62 62
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62
62 62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
35
35
35
35
35
35
34
34
33
35
33
33
33
33
33
33
33
35 33
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35
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33
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33
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33
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35
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35
33 35
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33
33 35
33
33 35
33 35
33 35
33
35 33
35
33
35
35
35
33
35
33
35
35
33
33
33
33
33
34
34
34
34
34
34
Preliminary
Page 35
DQ58
RFU18
KEY
VDD6
VSS6
VSS8
VDD5
DQ15
DQ13
DQ14
VSS5
DM1
VDD3
VSS3
DQ7
DQ12
DQ6
DM0
DQ4
DQ5
VSS1
VREF1
VDD1
SA1
SA2
RFU19
SA0
VDD32
DQ63
DQ62
VSS32
DQ61
VDD30
DQ60
DQ55
DM7
VSS30
DQ54
DM6
VDD28
DQ53
DQ52
VDD25
CK1*
CK1
VSS28
DQ47
DQ46
VDD23
VSS25
DM5
DQ45
DQ44
DM4
DQ39
VSS23
DQ38
DQ37
RFU17
DQ36
VSS21
VDD21
VDD19
RAS*
BA1
CAS*
S1*
A6
A4
A2
A0
VSS19
A8
A11
VDD17
RFU15
CKE0
VDD15
VSS17
RFU11
VSS16
RFU9
VDD14
RFU3
VSS14
RFU5
RFU7
RFU1
VDD12
VSS12
DM3
DQ31
DQ30
DQ29
VSS10
VDD10
DQ28
DQ23
DM2
DQ20
VDD8
DQ21
DQ22
VDDSPD
SCL
SDA
VDD31
VSS31
DQ59
DQS7
DQ51
VDD29
DQ56
VSS29
DQ57
DQ48
DQS6
VDD27
DQ49
DQ50
DQ43
VSS26
VDD26
VDD24
VSS27
DQ41
DQS5
VSS24
VDD22
DQ42
DQ34
VSS22
DQ35
DQS4
DQ40
VDD20
RFU16
DQ32
VSS20
DQ33
S0*
VDD18
BA0
A10_AP
WE*
A1
A5
A3
A9
A7
VSS18
CKE1
RFU14
RFU13
VDD16
VDD13
VSS15
RFU10
RFU8
RFU12
RFU0
RFU4
VSS13
RFU2
RFU6
VSS11
DQ26
DQ27
DQS3
VDD11
DQ19
DQ24
VDD9
VSS9
DQ25
DQ18
DQ16
VDD7
DQ17
DQS2
DQ11
VDD4
VSS7
CK0*
CK0
DQS1
VSS4
DQ10
VDD2
DQ9
DQ2
DQS0
DQ8
DQ3
VSS2
VDD0
DQ0
DQ1
VSS0
VREF0
A12
DQ58
RFU18
KEY
VREF0
VDD0
DQ0
DQ1
VSS0
DQS0
VSS2
DQ3
DQ8
DQ2
VDD2
VSS4
DQS1
DQ10
DQ9
DQ11
CK0
CK0*
VSS7
VDD4
DQ16
DQ18
VDD7
DQ17
DQS2
VSS9
DQ25
VDD9
DQ24
DQ19
DQS3
VDD11
DQ27
DQ26
VSS11
RFU0
VDD13
RFU4
VSS13
RFU2
RFU6
RFU13
RFU12
RFU8
RFU10
VSS15
A9
CKE1
RFU14
VDD16
A1
A5
A7
VSS18
A3
BA0
VDD18
S0*
WE*
A10_AP
DQ33
VSS20
DQ32
VDD20
RFU16
DQS4
DQ34
VSS22
DQ35
DQ40
VDD22
DQ41
DQS5
VSS24
DQ42
DQ43
DQ48
VSS26
VDD26
VDD24
VSS27
VSS29
DQ50
DQ49
DQS6
VDD27
DQS7
DQ51
VDD29
DQ56
DQ57
SDA
VDD31
VSS31
DQ59
VDDSPD
SCL
RFU19
VDD32
VSS28
CK1
DQ52
VDD28
DM6
DQ54
VSS30
DM7
DQ55
DQ60
VDD30
DQ61
DQ53
SA1
SA2
SA0
DQ63
DQ62
VSS32
VSS25
DM5
DQ45
VDD23
VDD21
VSS21
DQ36
RFU17
DQ44
DM4
DQ39
VSS23
DQ38
DQ37
RAS*
CAS*
S1*
DQ46
DQ47
CK1*
VDD25
RFU7
RFU5
VDD14
VSS17
VDD15
CKE0
RFU15
VDD17
A11
A8
RFU11
VSS16
RFU9
VSS19
A0
A2
A4
A6
BA1
VDD19
VDD12
VSS12
DQ31
DQ30
DM3
DQ22
DQ21
VDD8
DQ20
DQ29
VSS10
VDD10
DQ28
DQ23
DM2
VSS6
VSS8
RFU1
VSS14
RFU3
VREF1
DQ5
DQ4
DM0
DQ6
DQ12
DQ7
VSS3
VSS1
VDD1
VDD3
DM1
VSS5
DQ14
DQ13
DQ15
VDD5
VDD6
A12
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
NC
Customer Slot
Slot "A"
Standard
NC
NC
DDR SODIMM CONNS
DDR VRef
One 0.1uF per connector
NC
NC
NC
NC
NC
NC
NC
NC
NC
NCNC
NC
NC
NC
NC
NC
NC
NC
516S0029
NC
Addr=0xA2(Wr)/0xA3(Rd)
NC
Slot "B"
Reversed
NC
NC
NC
NC
NC
NC
NC
NC
Addr=0xA0(Wr)/0xA1(Rd)
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Factory Slot
NC
516S0028
Power aliases required by this page:
- _PP2V5_PWRON_DIMM
(NONE)
Signal aliases required by this page:
(NONE)
BOM options provided by this page:
- _PPSPD_DIMM (2.5V - 3.3V)
Page Notes
Slot "A"
(For return current)
DDR Bypass Caps
Slot "B"
2
1
C4031
20%
CERM
10uF
6.3V
805
2
1
C4014
20%
10V
CERM
402
0.1uF
2
1
C4013
20%
10V
CERM
402
0.1uF
2
1
C4012
402
CERM
10V
20%
0.1uF
2
1
C4009
805
6.3V
10uF
CERM
20%
2
1
C4011
402
CERM
10V
20%
0.1uF
2
1
C4008
20%
CERM
10uF
6.3V
805
2
1
C4010
402
CERM
10V
20%
0.1uF
2
1
C4019
402
CERM
10V
20%
0.1uF
2
1
C4018
402
CERM
10V
20%
0.1uF
2
1
C4017
20%
10V
CERM
402
0.1uF
2
1
C4016
20%
10V
CERM
402
0.1uF
2
1
C4015
20%
10V
CERM
402
0.1uF
119
51
4039
38
2827
186185
174
16
173
162161
159
150149
138137
126125
15
104103
90
8887
7675
6463
52
43
21
197
57
4645
36
3433
192191
180
22
179
168167
157
156155
144143
132131
21
114113
9493
92
8281
7069
58
10
9
193
195
198
196
194
122121
8483
8079
7877
7473
200199
124123
9897
91
89
8685
7271
118
202
201
183
169
147
133
61
47
25
11
23
19
18
190
188
182
178
14
189
187
181
177
176
172
166
164
175
171
8
165
163
154
152
146
142
153
151
145
141
6
140
136
130
128
139
135
129
127
68
66
17
60
56
67
65
59
55
54
50
44
42
13
53
49
43
41
32
30
24
20
31
29
7
5
184
170
148
134
62
48
26
12
95 96
158
160
37
35
120
116
117
101 102
105 106
107 108
109 110
99
100
115
111 112
J4010
F-RT-SM
AS0A42-D2S
CRITICAL
119
51
40 39
38
28 27
186 185
174
16
173
162 161
159
150 149
138 137
126 125
15
104 103
90
88 87
76 75
64 63
52
4 3
2 1
197
57
46 45
36
34 33
192 191
180
22
179
168 167
157
156 155
144 143
132 131
21
114 113
94 93
92
82 81
70 69
58
10
9
193
195
198
196
194
122 121
84 83
80 79
78 77
74 73
200 199
124 123
98 97
91
89
86 85
72 71
118
202
201
183
169
147
133
61
47
25
11
23
19
18
190
188
182
178
14
189
187
181
177
176
172
166
164
175
171
8
165
163
154
152
146
142
153
151
145
141
6
140
136
130
128
139
135
129
127
68
66
17
60
56
67
65
59
55
54
50
44
42
13
53
49
43
41
32
30
24
20
31
29
7
5
184
170
148
134
62
48
26
12
9596
158
160
37
35
120
116
117
101102
105106
107108
109110
99
100
115
111112
J4020
F-RT-SM
AS0A42-D2R
CRITICAL
2
1
R4000
1K
1%
1/16W
MF
402
2
1
R4001
402
MF
1/16W
1%
1K
2
1
C4001
0.1uF
402
CERM
10V
20%
2
1
C4002
0.1uF
402
CERM
10V
20%
2
1
C4029
0.1uF
20%
10V
CERM
402
2
1
C4028
0.1uF
20%
10V
CERM
402
2
1
C4024
0.1uF
402
CERM
10V
20%
2
1
C4023
0.1uF
402
CERM
10V
20%
2
1
C4022
0.1uF
20%
10V
CERM
402
2
1
C4021
0.1uF
20%
10V
CERM
402
2
1
C4027
0.1uF
402
CERM
10V
20%
2
1
C4026
0.1uF
402
CERM
10V
20%
2
1
C4020
0.1uF
20%
10V
CERM
402
2
1
C4030
805
6.3V
10uF
CERM
20%
2
1
C4025
0.1uF
402
CERM
10V
20%
03
051-6532
40 103
_PP2V5_PWRON_DIMM
_PP2V5_PWRON_DIMM
RAM_DQ<63>
RAM_DQ<62>
RAM_DQ<61>
RAM_DQ<60>
RAM_DQ<55>
RAM_DQ<52>
RAM_DQ<53>
RAM_DQ<54>
RAM_CLK_B_P
RAM_CLK_B_N
RAM_DQ<44>
RAM_DQ<46>
RAM_DQ<45>
RAM_DQ<39>
RAM_DQ<47>
RAM_DQ<38>
RAM_DQ<36>
RAM_DQ<37>
RAM_CS_L<1>
RAM_RAS_L
RAM_CAS_L
RAM_BA<1>
RAM_A<0>
RAM_A<4>
RAM_A<2>
RAM_A<6>
RAM_A<8>
RAM_A<11>
RAM_CKE<0>
RAM_DQ<31>
RAM_DQ<30>
RAM_DQ<29>
RAM_DQ<28>
RAM_DQ<23>
RAM_DQ<22>
RAM_DQ<21>
RAM_DQ<20>
RAM_DQ<15>
RAM_DQ<14>
RAM_DQ<13>
RAM_DQ<7>
RAM_DQ<12>
RAM_DQ<6>
RAM_DQ<5>
RAM_DQ<4>
RAM_VREF_DIMM
_PPSPD_DIMM
I2C_DIMM_SCL
I2C_DIMM_SDA
RAM_DQ<59>
RAM_DQ<58>
RAM_DQS<7>
RAM_DQ<57>
RAM_DQ<56>
RAM_DQ<51>
RAM_DQS<6>
RAM_DQ<50>
RAM_DQ<49>
RAM_DQ<48>
RAM_DQ<43>
RAM_DQS<5>
RAM_DQ<42>
RAM_DQ<40>
RAM_DQS<4>
RAM_DQ<33>
RAM_DQ<32>
RAM_CS_L<0>
RAM_BA<0>
RAM_WE_L
RAM_A<10>
RAM_A<1>
RAM_A<5>
RAM_A<3>
RAM_A<7>
RAM_A<9>
RAM_CKE<1>
RAM_DQ<27>
RAM_DQS<3>
RAM_DQ<24>
RAM_DQ<25>
RAM_DQ<19>
RAM_DQ<18>
RAM_DQS<2>
RAM_DQ<17>
RAM_DQ<16>
RAM_CLK_A_P
RAM_CLK_A_N
RAM_DQ<11>
RAM_DQS<1>
RAM_DQ<10>
RAM_DQ<3>
RAM_DQ<8>
RAM_DQ<2>
RAM_DQS<0>
RAM_DQ<1>
RAM_VREF_DIMM RAM_VREF_DIMM
RAM_DQ<64>
RAM_DQ<65>
RAM_DQS<8>
RAM_DQ<66>
RAM_DQ<67>
RAM_DQ<72>
RAM_DQ<73>
RAM_DQS<9>
RAM_DQ<74>
RAM_DQ<75>
RAM_CLK_D_P
RAM_CLK_D_N
RAM_DQ<80>
RAM_DQ<81>
RAM_DQS<10>
RAM_DQ<82>
RAM_DQ<88>
RAM_DQ<83>
RAM_DQ<89>
RAM_DQS<11>
RAM_DQ<90>
RAM_DQ<91>
RAM_CKE<5>
RAM_A<9>
RAM_A<7>
RAM_A<5>
RAM_A<3>
RAM_A<1>
RAM_A<10>
RAM_BA<0>
RAM_CS_L<8>
RAM_WE_L
RAM_DQ<96>
RAM_DQ<97>
RAM_DQS<12>
RAM_DQ<98>
RAM_DQ<99>
RAM_DQ<104>
RAM_DQ<105>
RAM_DQS<13>
RAM_DQ<106>
RAM_DQ<107>
RAM_DQ<112>
RAM_DQ<113>
RAM_DQ<114>
RAM_DQS<14>
RAM_DQ<120>
RAM_DQ<115>
RAM_DQS<15>
RAM_DQ<121>
RAM_DQ<122>
RAM_DQ<123>
I2C_DIMM_SDA
I2C_DIMM_SCL
_PPSPD_DIMM
_PPSPD_DIMM
RAM_DQ<124>
RAM_DQ<127>
RAM_DQ<125>
RAM_DQ<126>
RAM_DQ<119>
RAM_DQ<118>
RAM_DQ<116>
RAM_CLK_E_P
RAM_CLK_E_N
RAM_DQ<109>
RAM_DQ<108>
RAM_DQ<103>
RAM_DQ<110>
RAM_DQ<111>
RAM_DQ<102>
RAM_DQ<101>
RAM_DQ<100>
RAM_CAS_L
RAM_RAS_L
RAM_CS_L<9>
RAM_A<4>
RAM_A<0>
RAM_A<6>
RAM_A<8>
RAM_A<11>
RAM_A<2>
RAM_BA<1>
RAM_CKE<4>
RAM_DQ<95>
RAM_DQ<94>
RAM_DQ<93>
RAM_DQ<92>
RAM_DQ<87>
RAM_DQ<86>
RAM_DQ<85>
RAM_DQ<84>
RAM_DQ<79>
RAM_DQ<78>
RAM_DQ<77>
RAM_DQ<76>
RAM_DQ<71>
RAM_DQ<70>
RAM_DQ<69>
RAM_DQ<68>
RAM_VREF_DIMM
_PP2V5_PWRON_DIMM _PP2V5_PWRON_DIMM _PP2V5_PWRON_DIMM
RAM_VREF_DIMM
_PP2V5_PWRON_DIMM
RAM_A<12>
RAM_A<13>
RAM_A<12>
RAM_A<13>
RAM_DQ<0>
RAM_DQ<9>
RAM_DQ<26>
RAM_DQ<41>
RAM_DQ<34>
RAM_DQ<35>
RAM_DQ<117>
_PP2V5_PWRON_DIMM
62
62
62
62
62
62
62
62
62
62
62
62 62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
35
35
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
35
35
35
35
35
35
35
35
35
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
35
35
35
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
35
35
35
35
35
35
35
35
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
35
35
35
35
35
35
35
62
35
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
35
35
35
35
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
35
35
62
35
35
35
35
35
35
35
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
35 35 35
35
35
35
35
35
62
62
62
62
62
62
62
35
5
5
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
35
5
18
18
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
35 35
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
18
18
5
5
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
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34
34
34
34
35
5 5 5
35
5
34
34
34
34
34
34
34
34
34
34
34
5
Preliminary
Page 36
S
D
G
AGP
REFCLK_AVDD
VDD_AGP
AGP_CBE2
AGP_AD_STBS0
AGP_AD_STBF0
AGP_DBI_LO
AGP_CBE1
AGP_CBE0
AGP_SB_STBS
AGP_SB_STBF
AGP_AD_STBS1
AGP_AD_STBF1
AGP_DBI_HI
AGP_CBE3
AGP_STOP
AGP_REQ
AGP_DEVSEL
AGP_FRAME
AGP_GNT
AGP_IRDY
AGP_TRDY
AGP_PAR
AGP_ST0
AGP_ST1
AGP_ST2
AGP_RBF
AGP_WBF
AGP_GC_AGP8X_DET
AGP_TYPEDET
AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD9
AGP_AD8
AGP_AD15
AGP_AD16
AGP_AD12
AGP_AD11
AGP_AD10
AGP_AD13
AGP_AD14
AGP_AD21
AGP_AD20
AGP_AD19
AGP_AD18
AGP_AD17
AGP_AD26
AGP_AD25
AGP_AD24
AGP_AD23
AGP_AD22
AGP_AD27
AGP_SBA2
AGP_SBA3
AGP_AD31
AGP_AD30
AGP_AD29
AGP_AD28
AGP_SBA1
AGP_SBA0
AGP_SBA4
AGP_STP_AGP*
AGP_BUSY*
AGP_REFCLK
AGP_SBA5
AGP_SBA6
AGP_SBA7
AGP_VREFCG
AGP_PVTREF2
AGP_PVTREF1
AGP_VREFGC
AGP_MB_AGP8X_DET
AGP_REFCLK_AVSS
(SYM 4 OF 7)
AGP
INTERFACE
G
D
S
G
D
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
AGP BUSY AND STOP ARE NOT USED IN ALL DESIGNS
LEVEL SHIFTER FOR U3LITE
FOR CONSTRAINTS
GROUPS WITH STROBE1
DBIHI AND DBILO
U3LITE AGP
DIFFERENTIAL_PAIR
ELECTRICAL_CONSTRAINT_SET
NET_SPACING_TYPE
NET_PHYSICAL_TYPE
MASTER: GILA
PVTREF RESISTOR
DBI_HI IS NOT A STROBE BUT SHARES THE SAME TOPOLOGY AS A STROBE
2
1
C4808
CERM
10V
20%
0.1UF
402
2
1
R4811
402
MF
1/16W
5%
10K
AGP_BUSYSTOP
2
1
R4812
1/16W
402
10K
5%
MF
2
1
R4808
5%
10K
1/16W
MF
402
AGP_BUSYSTOP
2
1
R4810
MF
402
10K
5%
1/16W
2
3
1
Q4802
2N3904
SM
AGP_BUSYSTOP
2
1
3
Q4803
2N7002
SM
AGP_BUSYSTOP
2
1
R4809
MF
10K
5%
1/16W
402
2
1
C4807
402
0.1UF
20%
10V
CERM
21
R4813
5%
402
MF
1/16W
1K
AGP_BUSYSTOP
2
1
R4807
402
MF
1/16W
5%
10K
2
1
C4806
CERM
10V
20%
0.1UF
402
2
1
C4805
402
0.1UF
20%
10V
CERM
2
1
C4804
CERM
10V
20%
0.1UF
402
2
1
C4803
402
0.1UF
20%
10V
CERM
2
1
C4802
CERM
10V
20%
0.1UF
402
2
1
C4801
402
0.1UF
20%
10V
CERM
2
1
C4800
10V
20%
402
CERM
0.1UF
21
R4800
603
5%
2.2
1/16W
MF
2
1
C4811
402
6.3V
10%
1UF
CERM
2
1
C4816
402
10V
0.1UF
CERM
20%
21
R4801
1/16W
MF
182
1%
402
2
1
C4812
10V
402
0.1UF
20%
CERM
2
1
C4813
CERM
20%
0.1UF
402
10V
2
1
C4814
CERM
20%
0.1UF
402
10V
2
1
C4815
CERM
20%
0.1UF
402
10V
2
1
C4817
0.01UF
402
20%
16V
CERM
I46
I48
I49
I50
I51
I52
I53
I54
I55
I56
I57
I58
I59
W10
W6
W2
Y11
AB4
AC10
AE7
AE2V9AG10
AG4
AD6
AA9
AC5
AC9
AH5
AD4
AH4
AB1
AC1
AC4
AE1
AD1
AF1
AG1
AF2
AD2
AG3
AH1
AF3
AG2
AB9
AE5
AE6
AH2
AC6
AF5
AG5
AH7
AA8
AG6
AC3
AB8
AH6
AF6
AA6
AA4
AA5
Y8
AF8
AG8
AC8
AA2
AD8
AA3
AE8
AH9
AH8
AF11
AE11
AD11
AC11
AA7
W1
AH12
V7
V8
V3
V4
V6
V5
Y7
Y1
Y2
AA1
AG11
Y5
Y6
Y3
Y4
AD9
AE9
AF9
AG9
AH11
AH10
AA11
AB11
U3
V1.0-300MM
PBGA
U3LITE
OMIT
2
1
C4810
CERM
20%
0.1UF
402
10V
4
5
3
Q4801
SOT-363
2N7002DW
AGP_BUSYSTOP
1
2
6
Q4801
SOT-363
2N7002DW
AGP_BUSYSTOP
03
48
103
051-6532
VOLTAGE=1.5V
PP1V5_PWRON_AGP_NB_AVDD
MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=25MIL
AGP_SBA_L<5>
AGP_SBA_L<7>
AGP_IRDY
TP_VREF_CG
AGP_AD_STBF<1>
PP1V5_PWRON_NB_AVDD
AGP_SBA_L<0>
AGP_PVTREF2
AGP_PVTREF1
PP1V5_AGP
AGP_CBE<0>
AGP_CBE<1>
AGP_DBI_HI
AGP_VREF_GC
TP_AGP_MB_AGP8X_DET_L
AGP_AD<24>
AGP_AD<23>
AGP_AD<21>
AGP_AD<2>
AGP_AD<3>
AGP_SBA
AGP_DATA
AGP_SBA_L<7..0>
AGP_AD<7>
AGP_AD<29>
AGP_AD<31>
AGP_SBA_L<3>
AGP_AD<0>
AGP_AD<19>
AGP_AD<18>
AGP_AD<16>
AGP_AD_STB_0
AGP_STROBE
AGP_AD_STB0
AGP_AD_STBF<0>
AGP_AD_1 AGP_DATA
AGP_CBE<3..2>
AGP_SB_STBS
AGP_STROBE AGP_SB_STB
AGP_SB_STBF
AGP_AD_0 AGP_DATA
AGP_CBE<1..0>
AGP_AD_1
AGP_AD<31..16>
AGP_DATA
AGP_AD<11>
AGP_AD_STB_1
AGP_DBI_HI
AGP_DATA
AGP_AD_STB_1
AGP_AD_STB1
AGP_AD_STBS<1>
AGP_STROBE
AGP_SB_STBS
AGP_STROBE AGP_SB_STB
AGP_SB_STBS
AGP_AD_STB_1
AGP_AD_STBF<1>
AGP_STROBE
AGP_AD_STB1
AGP_AD_0 AGP_DATA
AGP_DBI_LO
AGP_SBA_L<1>
NB_AGP_BUSY_L
AGP_SBA_L<2>
AGP_AD_STBS<1>
AGP_CBE<3>
AGP_CBE<2>
AGP_AD_STBS<0>
AGP_AD_STBF<0>
AGP_DBI_LO
AGP_AD<28>
AGP_AD<27>
AGP_SB_STBF
AGP_SB_STBS
AGP_AD<17>
AGP_WBF
AGP_AD<1>
AGP_ST<2>
AGP_RBF
AGP_DEVSEL
AGP_TRDY
AGP_AD<13>
AGP_REQ
AGP_PAR
AGP_SBA_L<4>
AGP_SBA_L<6>
AGP_CLK66M_NB
NB_STOP_AGP_L
AGP_AD<30>
AGP_AD<25>
AGP_AD_STB_0
AGP_STROBE
AGP_AD_STBS<0>
AGP_AD_STB0
AGP_AD_0
AGP_AD<15..0>
AGP_DATA
AGP_AD<5>
AGP_AD<6>
AGP_AD<8>
AGP_AD<9>
AGP_AD<10>
AGP_AD<12>
AGP_AD<14>
AGP_AD<15>
AGP_AD<20>
AGP_AD<22>
AGP_AD<26>
AGP_ST<1>
AGP_ST<0>
AGP_STOP
AGP_GNT
NB_AGP_GCDET_L
AGP_TYPEDET_L
AGP_FRAME
PP1V5_AGP
AGP_AD<4>
PP1V5_AGP
NB_AGP_BUSY_L
PP3V3_AGP
AGP_BUSY_L_F
AGP_BUSY_L
PP3V3_AGP
PP3V3_AGP
PP1V5_AGP
STOP_AGP_L
STOP_AGP_L_F
NB_STOP_AGP_L
STOP_AGP_L_R
43 33
37
37
37
37
37
37
37
26
37
36
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
36
37
36
36
36
36
36
36
36
37
36
5
36
5
36
36
36
37
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
37
36
37
37
37
37
36
37
37
36
36
25
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
37
37
37
37
37
37
37
5
36
5
36
5
37
5
5
5
37
36
Preliminary
Page 37
OE
GND
OUT
VCC
OSC
XIN/CLKIN
SSCLK
VSS
S0
S1
FRSEL
XOUT
VDD
VSS VSS
VSSVSS
RAGE_MOBILITY
(2 OF 6)
VDDCI
VSS
(6 OF 6)
RAGE_MOBILITY
VSS
VSS
(1 OF 6)
RAGE_MOBILITY
AGP_BUSYB
AD_STBB1
AD_STBB0
AD_STB0
AGPREF
AD_STB1
AD30
AD31
AD29
AD28
AD27
AD26
AD25
AD24
AD17
AD14
AD15
AD23
AD22
AD19
AD20
AD21
AD16
AD18
AD6
AD5
AD4
AD13
AD11
AD12
AD10
AD9
AD8
AD7
AD3
CBEB1
CBEB2
CBEB3
AD0
AD1
AD2
CBEB0
PCICLK
FRAMEB
PAR
IRDYB
TRDYB
RSTB
INTAB
GNTB
REQB
DEVSELB
STOPB
MEMVMODE1
MEMVMODE0
TEST_YCLK
TEST_MLCK
D+
D-
VREF
VREFG
MEMTEST
PLLTEST
WBF
ST0
ST1
ST2
SBA5
SBA6
SBA3
SBA4
SBA7
SBA2
STP_AGPB
RBFB
SB_STB
SBA1
SBA0
SUS_STAT
AGPTEST
AGP8X_DETB
RSTB_MSK
DBI_LO
DBI_HI
SB_STBS
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
AGP 4X
S0=1;S1=M => -1.5% DOWN-SPREAD
NC
(PULL-UP to GPU_MEM_IO)
NC
NC
27MHz OSC
CLOSE TO GPU PIN AJ29)
(PLACE THE OSCILLATOR AND R4981 AND RR4982
(PLACE R4985 CLOSE TO OSC)
FOR 2.5 VDDR1
MEMVMODE0=1.8V
MEMVMODE1=GND
FOR 1.8 VDDR1
MEMVMODE0=GND
MEMVMODE1=1.8V
CLOSE TO ATI M10 VREF PIN
PLACE VREF VOLTAGE DIVIDER
SPREAD SPECTRUM SUPPORT
M11 AGP INTERFACE
AGP 8X
U3LITE SIGNAL
U3LITE AGP I/O REFERENCE
(PLACE CLOSE TO GPU AGP BALL)
(PLACE C4913 CLOSE TO AGPREF PIN)
21
R4900
1/16W
47
5%
MF
402
2
1
R4901
402
1/16W
5%
MF
10K
21
L4900
60-OHM-EMI
SM
2
1
C4900
0.01uF
20%
CERM
402
16V
2
1
C4901
402
CERM
20%
16V
0.01uF
2
1
C4902
CERM
20%
6.3V
805
10uF
2
1
C4903
16V
CERM
20%
402
0.01uF
2
1
C4904
16V
402
CERM
20%
0.01uF
2
1
R4902
MF
1/16W
5%
10K
402
2
1
R4904
45.3
402
MF
1/16W
1%
21
R4905
5%
0
1/16W
MF
402
2
1
R4906
NO STUFF
402
5%
1/16W
MF
10K
2
1
R4907
5%
1/16W
MF
402
4.7K
2
1
R4908
4.7K
5%
1/16W
MF
402
2
1
R4909
1/16W
MF
402
1%
1K
2
1
R4910
1/16W
MF
1K
1%
402
2
1
R4911
MF
402
1K
1%
1/16W
2
1
R4912
1K
1/16W
MF
402
1%
2
1
C4906
CERM
20%
0.1uF
10V
402
2
1
C4907
20%
6.3V
805
CERM
10uF
14
81
7
G4980
SM-1
CRITICAL
27.0000M
2
1
R4980
NO STUFF
100K
5%
402
MF
1/16W
2
1
C4980
4.7uF
805
CERM
20%
6.3V
2
1
C4981
CERM
402
20%
10V
0.1uF
21
L4980
SM
FERR-EMI-100-OHM
2
1
R4990
1/16W
MF
5%
402
NO STUFF
0
21
L4990
GPU_SS
SM
FERR-EMI-100-OHM
8
1
2
7
5
3
4
6
U4990
GPU_SS CRITICAL
SOI
CY25811
2
1
C4991
0.1uF
CERM
10V
402
20%
GPU_SS
2
1
C4990
805
CERM
20%
6.3V
GPU_SS
10uF
2
1
R4991
GPU_SS
MF
0
1/16W
5%
402
2
1
R4993
0
NO STUFF
1/16W
MF
5%
402
2
1
R4992
0
402
5%
MF
1/16W
NO STUFF
2
1
R4981
MF
402
1%
1/16W
287
2
1
R4982
162
1/16W
402
MF
1%
2
1
R4920
47
5%
MF
1/16W
402
2
1
C4912
20%
10V
402
CERM
0.1uF
2
1
R4923
NO STUFF
1/16W
4.7K
402
MF
5%
2
1
R4924
NO STUFF
4.7K
402
MF
5%
1/16W
21
R4985
GPU_SS
402
MF
1/16W
5%
0
2
1
R4995
GPU_SS
MF
1/16W
33
5%
402
2
1
C4913
20%
16V
402
CERM
0.01uF
G30
N3
N4
N1
N2
M4
L3
M3
L4
K3
K4
J1
J2
H1
H2
B27
A27
D23
C23
D22
C20
D20
C21
D21
C22
A25
B25
A26
B26
AE4
AE3
AD4
AD3
AB4
AB3
AA4
AA3
AD2
AD1
AC2
AC1
AA2
AA1
Y2
Y1
Y4
Y3
W4
W3
U4
U3
T4
T3
W2
W1
V2
V1
T2
T1
R2
R1
G2
G1
F2
F1
D2
D1
C2
C1
J4
J3
H4
H3
F4
F3
E3
E4
B1
A1
B2
A2
B4
A4
B5
A5
D3
C3
D4
C4
D6
C6
D7
C7
A8
B8
A9
B9
A11
B11
A12
B12
C9
D9
C10
D10
C12
D12
C13
D13
A13
B13
A14
B14
A16
B16
A17
B17
C14
D14
C15
D15
C17
D17
C18
D18
C24
D24
C25
D25
C27
D27
C28
D28
B28
A28
A29
A30
C29
C30
D29
D30
E27
E28
F27
F28
H27
H28
J27
J28
E29
E30
F29
F30
H29
H30
J29
J30
AC3
AB1
V3
U1
E1
G3
B3
D5
B10
D11
B15
D16
D26
B30
G28
U4900
M10-CSP64
64MB
BGA
OMIT
R19
R18
R17
R16
T16
U16
V16
W16
T14
T13
T12
T15
R15
P15
N15
M15
B19
A21
P3
M2
P25
F18
AE15
U6
U4900
64MB
BGA
OMIT
M10-CSP64
AE27
L1
A22
L2
B22
K1
A23
K2
B23
AC4
AB2
V4
U2
E2
G4
A3
C5
A10
C11
A15
C16
C26
B29
G27
G29
P1
D19
R4
A18
R3
A19
P4
B18
P2
C19
AK3
D8
T28
E8
J6
AJ28
AG29
T27
AE29
AF28
AF30
AD28
AC29
AC28
AB29
AC27
AC30
AD27
AD30
AE28
AD29
AD24
AH30
AF29
AE30
AC22
AG30
R28
B6
B7 C8
T30
AH29
AF27
U27
T29
Y25
Y27
AC11
AC10
W28
U29
R30
N27
AG28
K29
K30
U25
Y29
W29
M28
N29
N28
N30
M30
M27
M29
L28
AB30
AB27
L30
AA29
AB28
AA30
AA27
Y30
AA28
W30
W27
V30
V28
L27
V29
V27
U30
U28
R27
R29
P28
P30
P27
P29
L29
K28
U4900
M10-CSP64
CRITICAL
OMIT
BGA
64MB
2
1
R4913
10K
402
MF
1/16W
5%
2
1
R4914
5%
1/16W
0
402
MF
2
1
R4802
1/16W
3.32K
1%
402
MF
2
1
C4818
402
16V
CERM
20%
0.01UF
2
1
R4803
1.02K
1%
1/16W
MF
402
051-6532
10349
03
AGP_VREF_GC
MIN_LINE_WIDTH=8 mil
MIN_NECK_WIDTH=8 mil
AGP_AD_STBS<1>
AGP_AD<2>
AGP_ATI_VREFG
MIN_NECK_WIDTH=8 mil
MIN_LINE_WIDTH=8 mil
GPU_RESET_L_R
AGP_WBF
AGP_TRDY
AGP_DBI_HI
_PP3V3_GPU
AGP_SUS_STAT_L_PU
AGP_VREF_GC
GPU_AGP_TEST
_PP1V5_GPU_AGP
NB_AGP_GCDET_L
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=10 mil
AGP_ATI_MVREF
_PP3V3_GPU
_GPU_RESET_L
_PP3V3_GPU
AGP_AD<30>
AGP_AD<31>
PP1V5_AGP
AGP_AD<13>
STOP_AGP_L
AGP_SBA_L<5>
GPU_MEMVMODE1
AGP_ST<0>
_PP1V8_GPU
GPU_MEMVMODE0
AGP_DBI_LO
AGP_AD<20>
AGP_BUSY_L
AGP_INT_L
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=10 mil
VOLTAGE=3.3V
PP3V3_GPU_OSC
GPUSS_S1
GPUSS_S0
GPUSS_CLK27M
_PPVCORE_GPUFB
_PP3V3_GPU
_PP3V3_GPU
GPU_OSC_OE
GPUSS_CLK27M
GPU_SSCLK_UF
GPU_CLK27M_OSC
AGP_AD<28>
AGP_AD<27>
AGP_AD<25>
AGP_AD<22>
AGP_AD<23>
AGP_AD<21>
AGP_AD<19>
AGP_AD<18>
AGP_AD<17>
AGP_AD<16>
AGP_AD<15>
AGP_AD<12>
AGP_AD<11>
AGP_AD<10>
AGP_AD<7>
AGP_AD<6>
AGP_AD<5>
AGP_AD<4>
AGP_AD<3>
AGP_AD<1>
AGP_AD<0>
AGP_CBE<1>
AGP_CBE<2>
AGP_CLK66M_GPU
AGP_CBE<0>
AGP_FRAME
AGP_IRDY
AGP_DEVSEL
AGP_STOP
AGP_PAR
AGP_REQ
GPU_THMDIODE_P
GPU_MEMTEST
AGP_ST<2>
AGP_AD_STBF<1>
AGP_CBE<3>
GPU_CLK27M_DIV
_PPVCORE_GPUFB
MIN_NECK_WIDTH=10 mil
PP3V3_GPUSS_VDD
VOLTAGE=3.3V
MIN_LINE_WIDTH=10 mil
GPU_SSCLK_IN
AGP_AD_STBF<0>
AGP_ST<1>
AGP_SBA_L<7>
AGP_SB_STBF
AGP_AD<8>
AGP_AD<14>
AGP_SBA_L<2>
AGP_SBA_L<0>
AGP_SBA_L<4>
AGP_AD<29>
AGP_SBA_L<6>
AGP_SBA_L<3>
AGP_SBA_L<1>
ATI_RSTB_MSK
AGP_SB_STBS
AGP_RBF
AGP_AD<9>
AGP_GNT
AGP_AD<26>
AGP_AD<24>
AGP_TYPEDET_L
AGP_AD_STBS<0>
PPVCORE_GPU
GPU_THMDIODE_N
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=20 mil
PPVCORE_GPU_VDDCI
VOLTAGE=1.2V
40
40
40
41
40
40
39
40
39
39
40
40
39
39
40
37
37
37
39
37
41
37
36
39
37
37
37
37
39
36
36
36
36
36
36
5
36
5
36
5
5
5
36
36
5
36
36
36
36
5
36
36
36
23
37
5
5
5
37
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
25
36
36
36
36
36
36
36
15
36
36
36
39
5
39
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36 36
36
36
36
36
36
5
15
Preliminary
Page 38
PAD
THM
GND
V+
TON
DL
LSAT
ILIM
LX
BST
DH
REF
REFIN
FB
OUT
SHDN*
SKIP*
OVP/UVP
CSP
CSN
OD
GATE
PGOOD
FBLANK
VCC VDD
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
2V output reference
<R3a>
<R3b>
<R1>
OD is open drain output controlled by gate
Changed R5050 from 30.1K to 37.4K
to get 1.2V at the high input
REFIN is FB voltage
FAT
GPU VCore Regulator
open LSAT=1.75*Ilim
SHORT
FAT
SHORT
FAT
SHORT
Req = R3a + R3b
Vout = 2V * (R2 / (R1+R2)) = 1.0V
FAT
SHORT
When GPUVCORE_CNTL_L = 1, Vout = 1.0V
When GPUVCORE_CNTL_L = 0, Vout = 1.2V
Vout = 2V * (Req / (R1+Req)) = 1.2V
2
1
C5038
1206
20%
CERM
22uF
6.3V
2
1
C5037
2.5V-ESR9V
POLY
CASE-D2E
330uF
20%
CRITICAL
NO STUFF
2
1
C5036
20%
330uF
CRITICAL
2.5V-ESR9V
POLY
CASE-D2E
2
1
C5033
20%
1206
4.7uF
25V
CERM
2
1
C5032
25V
20%
CERM
1206
4.7uF
2
1
C5031
4.7uF
1206
CERM
25V
20%
2
1
D5011
MBR0540
SM
2
1
C5011
0.1UF
402
20%
CERM
10V
21
R5011
0
5%
MF
402
1/16W
2
1
R5009
MF
5%
100K
1/16W
NO STUFF
402
2
1
R5008
MF
5%
20
1/16W
402
2
1
C5008
6.3V
10%
402
CERM
1uF
2
1
R5007
NO STUFF
MF
5%
0
402
1/16W
2
1
C5035
CRITICAL
20%
330uF
2.5V-ESR9V
POLY
CASE-D2E
3
1 2
L5030
1.53uH
SM
CRITICAL
2
1
R5034
2.2
5%
1/10W
FF
805
NO STUFF
2
1
C5034
CERM
603
50V
0.0022UF
NO STUFF
10%
2
1
R5018
90.9K
MF
402
1%
1/16W
2
1
C5019
470PF
402
50V
10%
CERM
2
1
R5019
26.7K
1/16W
1%
402
MF
2
1
C5030
CERM
10%
402
0.001uF
50V
NO STUFF
2
1
C5000
6.3V
20%
805
CERM
10UF
2
1
R5014
100
1%
MF
402
1/16W
1922
14
1
25
13
23
7
6
4
24
10
8
16
3
5
20
21
2
9
18
15
11
12
17
U5000
CRITICAL
QFN
MAX1993
21
C5012
402
6.3V
20%
X5R
0.22uF
2
1
C5001
CERM
10%
50V
402
0.0018UF
2
1
R5013
5%
MF
402
0
1/16W
2
1
R5012
MF
1/16W
1%
1.1K
402
2
1
R5005
NO STUFF
402
MF
1/16W
5%
0
2
1
R5003
NO STUFF
402
0
5%
1/16W
MF
2
1
R5006
NO STUFF
402
1/16W
MF
5%
0
2
1
R5004
1/16W
0
402
5%
MF
2
1
R5001
402
MF
5%
0
1/16W
2
1
R5002
NO STUFF
402
MF
1/16W
5%
0
2
1
C5002
402
20%
6.3V
0.22uF
X5R
2
1
R5015
1/16W
MF
402
1%
75K
2
1
R5016
402
MF
1/16W
1%
75K
2
1
C5015
0.001uF
50V
10%
CERM
402
2
1
R5017
MF
1%
37.4K
1/16W
402
2
1
D5030
SMB
B340LB
21
XW5001
SM
321
4
5
Q5030
SO-8-PWRPK
SI7392DP
CRITICAL
321
4
8765
Q5031
SI4336DY
CRITICAL
SO-8
2
1
R5010
NO STUFF
1/16W
MF
5%
0
402
50 103
03
051-6532
GPUVCORE_LX
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=25 mil
_PPVCORE_GPU_REG
_PPVIN_GPUVCORE
PP5V_GPUVCORE_VCC
VOLTAGE=5V
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=15 mil
MIN_NECK_WIDTH=10 mil
GPUVCORE_BST
MIN_LINE_WIDTH=20 mil
GPUVCORE_BST_RC
MIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=10 mil
GPUVCORE_FBLANK
GPUVCORE_CNTL_L
GPUVCORE_TON
GND_GPUVCORE
_PPVIN_GPUVCORE
MIN_LINE_WIDTH=25 mil
GPUVCORE_DH
MIN_NECK_WIDTH=10 mil
_PP5V_PWRON_GPUVCORE
GPUVCORE_DL
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
GPUVCORE_SKIP_L
GPOVCORE_LX_RC
GPUVCORE_OVP_UVP
GND_GPUVCORE
GPUVCORE_PGOOD
GPUVCORE_CSP
GPUVCORE_CSN
GPUVCORE_FB
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=15 mil
GND_GPUVCORE
VOLTAGE=0V
GPUVCORE_SHDN_L
GPUVCORE_LSAT
GPUVCORE_REF
GPUVCORE_REFIN
GPUVCORE_ILIM
GPUVCORE_OD
38
38
5
5
39
38
5
5
38
14
38
14
Preliminary
Page 39
HPD1
DDC3CLK
DDC3DATA
DDC1CLK
DDC1DATA
DDC2CLK
DDC2DATA
BLON
GPIO16
GPIO15
G
R
B
Y_G
R2SET
RSET
H2SYNC
HSYNC
V2SYNC
VSYNC
ZV_LCDDATA5
ZV_LCDDATA4
ZV_LCDDATA3
ZV_LCDDATA2
ZV_LCDDATA6
ZV_LCDDATA15
ZV_LCDDATA14
ZV_LCDDATA13
ZV_LCDDATA12
ZV_LCDDATA7
ZV_LCDDATA8
ZV_LCDDATA9
ZV_LCDDATA10
ZV_LCDDATA11
ZV_LCDDATA16
C_R
DIGON
COMP_B
AUXWIN
ZV_LCDDATA21
ZV_LCDDATA20
ZV_LCDCNTL0
ZV_LCDCNTL1
ZV_LCDDATA22
ZV_LCDDATA23
ZV_LCDDATA17
ZV_LCDDATA18
ZV_LCDDATA19
ZV_LCDCNTL2
ZV_LCDCNTL3
GPIO0
GPIO1
GPIO5
GPIO7
GPIO6
GPIO2
GPIO3
GPIO4
TXOUT_L3N
TXOUT_L2P
TXOUT_L2N
TXOUT_U3P
TXCLK_UN
TXOUT_U2P
TXOUT_L0N
TXOUT_L0P
TXOUT_L1N
TXOUT_L1P
TXOUT_U3N
TXCLK_UP
TXOUT_U2N
TXOUT_U1P
TXOUT_U0P
TXOUT_U0N
TXOUT_U1N
GPIO8
GPIO12
GPIO10
GPIO11
GPIO9
GPIO14
GPIO13
TX0M
TX2P
TX1P
TX2M
TXCM
TX1M
TX0P
TXCP
XTALIN
TXOUT_L3P
TXCLK_LN
TXCLK_LP
SSOUT
XTALOUT
TESTEN
SSIN
ROMCSB
ZV_LCDDATA1
ZV_LCDDATA0
RAGE_MOBILITY
(3 OF 6)
VSS
VSS
VSS
VSS
VSS
VDDC
(5 OF 6)
RAGE_MOBILITY
VSS
VDD15
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Length Tolerance: 50 mils
Page Notes
NC
NC
NC
NC
NC
NC
NC
NC
(NO ICT TEST)
(NO ICT TEST)
(NO ICT TEST)
(NO ICT TEST)
NC
NC
NC
M10 Power Shut down Sequencing
(PUT ALL CAPs BELOW ATI ASIC)
Secondary Max Sep: 100 mils
DIFFERENTIAL_PAIR
NOTE: Target differential impedance for
(NONE)
(NONE)
Line To Line: 15 mils
Net Spacing Type: LVDS
Power aliases required by this page:
Signal aliases required by this page:
BOM options provided by this page:
M11 CORE PWR/LVDS/TMDS
(500mA)
GPU VCORE - 1.2V
(GPIO2)
(GPIO0)
(GPIO1)
(GPIO3)
(GPIO4)
(GPIO5)
(GPIO6)
_PP1V5_GPU_AGP, _PP3V3_GPU, PPVCORE_GPU
Primary Max Sep: 10 mils
Secondary Length: 250 mils
LVDS data pairs is 100 ohms.
ELECTRICAL_CONSTRAINT_SET
NET_SPACING_TYPE
2
1
C5120
X5R
6.3V
402
20%
0.22uF
2
1
C5100
6.3V
20%
805
CERM
10uF
2
1
C5101
10uF
20%
6.3V
CERM
805
2
1
C5102
X5R
0.22uF
6.3V
20%
402
2
1
C5103
X5R
0.22uF
6.3V
402
20%
2
1
C5104
X5R
6.3V
20%
0.22uF
402
2
1
C5105
X5R
0.22uF
402
6.3V
20%
2
1
C5106
X5R
402
20%
6.3V
0.22uF
2
1
C5107
X5R
0.22uF
20%
402
6.3V
2
1
C5108
X5R
20%
0.22uF
402
6.3V
2
1
C5109
X5R
6.3V
402
20%
0.22uF
2
1
C5110
X5R
0.22uF
402
20%
6.3V
2
1
C5111
X5R
20%
6.3V
402
0.22uF
2
1
C5112
X5R
20%
402
6.3V
0.22uF
2
1
C5113
X5R
20%
402
6.3V
0.22uF
2
1
C5114
X5R
20%
402
0.22uF
6.3V
2
1
C5115
X5R
6.3V
402
20%
0.22uF
2
1
C5116
X5R
0.22uF
6.3V
20%
402
2
1
C5117
X5R
0.22uF
20%
6.3V
402
2
1
C5118
X5R
6.3V
402
20%
0.22uF
2
1
C5119
X5R
0.22uF
20%
6.3V
402
2
1
C5123
X5R
6.3V
402
20%
0.22uF
2
1
C5121
X5R
6.3V
402
20%
0.22uF
2
1
C5122
X5R
6.3V
20%
402
0.22uF
2
1
R5123
NO STUFF
5%
1/16W
MF
10K
402
2
1
R5100
MF
402
5%
1/16W
10K
2
1
R5101
1/16W
5%
10K
402
MF
2
1
R5102
1/16W
75
1%
MF
402
2
1
R5103
MF
402
1%
1/16W
75
2
1
R5104
1/16W
402
MF
1%
75
2
1
R5105
1/16W
75
1%
MF
402
2
1
R5106
402
MF
1%
75
1/16W
2
1
R5107
MF
1/16W
1%
75
402
2
1
R5108
1%
MF
1/16W
499
402
2
1
R5109
1%
1/16W
715
MF
402
2
1
R5110
5%
10K
MF
1/16W
402
2
1
R5111
NO STUFF
10K
402
5%
MF
1/16W
2
1
R5112
5%
402
MF
10K
NO STUFF
1/16W
2
1
R5113
NO STUFF
5%
MF
10K
1/16W
402
2
1
R5114
1/16W
10K
MF
402
5%
NO STUFF
2
1
R5115
1/16W
NO STUFF
5%
402
MF
10K
2
1
R5116
NO STUFF
5%
402
MF
10K
1/16W
2
1
R5117
10K
MF
5%
402
1/16W
NO STUFF
2
1
R5118
NO STUFF
1/16W
MF
402
5%
10K
2
1
R5119
1/16W
5%
MF
10K
402
2
1
R5120
NO STUFF
5%
1/16W
402
10K
MF
2
1
R5121
402
5%
10K
MF
NO STUFF
1/16W
2
1
R5122
10K
NO STUFF
1/16W
MF
402
5%
2
1
R5125
NO STUFF
402
MF
10K
1/16W
5%
2 1
R5124
1/16W
402
1K
MF
5%
2
1
C5125
10uF
6.3V
20%
CERM
805
2
1
C5124
0.01uF
20%
16V
CERM
402
2
1
C5132
16V
CERM
20%
402
0.01uF
2
1
C5126
16V
20%
CERM
402
0.01uF
2
1
C5127
0.01uF
402
CERM
20%
16V
2
1
C5128
20%
0.01uF
16V
402
CERM
2
1
C5129
402
CERM
16V
20%
0.01uF
2
1
C5130
0.01uF
CERM
16V
20%
402
2
1
C5131
402
CERM
20%
16V
0.01uF
21
L5126
FERR-220-OHM
0805
4
36
5
2
1
Q5100
TSOP
SI3446DV
CRITICAL
2
1
C5133
CERM
50V
10%
0.001uF
402
52
DP5190
BAS16TW
SOT-363
43
DP5190
BAS16TW
SOT-363
61
DP5190
SOT-363
BAS16TW
PP2V5_RUN
21
XW5190
SM
21
XW5191
SM
21
XW5192
SM
21
XW5193
SM
21
XW5194
SM
2
1
R5126
1/16W
MF
5%
1K
402
2
1
R5127
402
MF
5%
10K
1/16W
2
1
R5128
EXT_TMDS
1/16W
10K
402
MF
5%
AK7
AJ7
AH7
AG7
AK6
AJ6
AH6
AH11
AG11
AK10
AJ10
AG6
AH10
AG10
AK9
AJ9
AH9
AG9
AK8
AJ8
AH8
AG8
AK5
AJ5
AG5
AH5
AK4
AJ4
AK23
AJ30
AJ29
AG27
B21
A20
A24
B20
B24
AG25
AG22
AH22
AG20
AH20
AG19
AH19
AG18
AH18
AJ20
AK20
AJ18
AK18
AJ17
AK17
AJ16
AK16
AK12
AJ12
AG21
AH21
AJ19
AK19
AK15
AJ15
AK14
AJ14
AK13
AJ13
AH24
AJ25AJ26
AK25
AE5
AJ24
AK28
AG26
AF11
AG24
AF3
AG3
AH1
AF4
AJ1
AH2
AH3
AK1
M1
AE1
AE2
AF1
AG1
AF2
AG2
AK2
AJ2
AK27
AE13
AH26
AH25
AE12
AF12
AH28
AH27
AK24
AK22
AF13
AK26
AJ27
U4900
64MB
M10-CSP64
BGA
OMIT
G16
G15
AD23
G14
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
G13
AD12
AD11
AD10
AD9
AD8
AD7
AC24
AC23
AC8
AC7
G12
AB24
AB7
AA24
AA7
Y24
Y7
W24
W7
V24
V7
G11
U24
U7
T24
T7
R24
R7
P24
P7
N24
N7
G10
M24
M7
L24
L7
K24
K7
J24
J7
H24
H23
G9
H8
H7
G24
G23
G22
G21
G20
G19
G18
G17
G8
G7
AD26
P6
H6
G6
F6
AF5
V25
W25
N25
M25
F25
AE24
F24
AH4
F23
AE18
AC25
AE17
AF15
W26
AF14
AE14
F14
F13
AG4
AE11
F11
AE10
F10
F7
AE6
AD6
AC6
W6
V6
AF25
AJ3
AB25
R25
G25
F17
AB6
T6
L6
F12
U4900
BGA
64MB
M10-CSP64
OMIT
2
1
R5129
5%
10K
1/16W
MF
402
INT_TMDS
10351
051-6532
03
8 MIL SPACING
GPU_DVOD<0..19>
GPU_DVO_DATA
8 MIL SPACING
GPU_DVO_CLKP
GPU_DVO_CTL
GPU_DVO_DE
8 MIL SPACING
GPU_DVO_CTL
GPU_DVO_VSYNC
8 MIL SPACING
GPU_DVO_CTL
8 MIL SPACING
GPU_DVO_HSYNC
GPU_DVO_DATA
GPU_DVOD<21..23>
8 MIL SPACING
GPU_DVO_DATA
GPU_DVOD<20>
8 MIL SPACING
GPU_DVO_DATA20
SI_DDC_DATA
LVDS_U1
LVDS_U1P
LVDS
LVDS
LVDS_L2
LVDS_L2N
CLKLVDS_UP
LVDS
LVDS_UCLK
CLKLVDS_UN
LVDS
LVDS_UCLK
LVDS
LVDS_U2
LVDS_U2N
LVDS_U0
LVDS_U0N
LVDS
LVDS
LVDS_LCLK
CLKLVDS_LP
LVDS
CLKLVDS_LN
LVDS_LCLK
LVDS
LVDS_L0
LVDS_L0P
LVDS
LVDS_U1
LVDS_U1N
LVDS
LVDS_U2
LVDS_U2P
LVDS_L1N
LVDS_L1
LVDS
LVDS
LVDS_L2P
LVDS_L2
LVDS
LVDS_L1P
LVDS_L1
LVDS_L0N
LVDS_L0
LVDS
LVDS
LVDS_U0
LVDS_U0P
GPU_X1CLK_SKEW<1>
GPU_BUS_CFG<0>
GPU_BUS_CFG<1>
GPU_BUS_CFG<2>
GPU_AGP_FBSKEW<0>
GPU_AGP_FBSKEW<1>
_PP3V3_GPU
GPU_X1CLK_SKEW<0>
PP1V5_GPU_VDD15
MIN_NECK_WIDTH=10mil
MIN_LINE_WIDTH=25mil
VOLTAGE=1.5V
GPUVDD15_EN
_PP1V5_GPU_AGP
VOLTAGE=1.5V
MIN_NECK_WIDTH=10mil
MIN_LINE_WIDTH=25mil
PP1V5_GPU_VDD15_UF
PPVCORE_GPU
MIN_NECK_WIDTH=8mil
MIN_LINE_WIDTH=8mil
PP1V5_AGP_NECK
MIN_LINE_WIDTH=8mil
MIN_NECK_WIDTH=8mil
PP1V8_GPU_PVDD_NECK
MIN_NECK_WIDTH=8mil
MIN_LINE_WIDTH=8mil
PPVCORE_GPU_NECK
_PP1V5_GPU_AGP
MIN_NECK_WIDTH=8mil
MIN_LINE_WIDTH=8mil
PP2V5_RUN_NECK1
PP1V8_GPU_PVDD_LDO
PPVCORE_GPU
PP1V5_GPU_VDD15
PP1V5_GPU_VDD15_NECK
MIN_NECK_WIDTH=8mil
MIN_LINE_WIDTH=8mil
_PP3V3_GPU
FP_PWR_EN
INV_ON_PWM
_PP3V3_GPU
GPU_AUXWIN
GPU_RSET
GPU_R
GPU_R2SET
GPU_Y
GPU_G
GPU_B
GPU_C
GPU_COMP
GPU_DVOD<1>
GPU_DVOD<0>
GPU_CLK27M_DIV
GPU_TMDS_CLKP
GPU_TMDS_CLKN
GPU_TMDS_DP<2>
GPU_TMDS_DN<2>
GPU_TMDS_DP<1>
GPU_TMDS_DN<0>
GPU_TMDS_DN<1>
GPU_TMDS_DP<0>
HPD_PWR_SNS_EN
GPU_GPIO8_PD
SI_RESET_L
GPU_BUS_CFG<2>
GPU_BUS_CFG<1>
GPU_BUS_CFG<0>
GPU_X1CLK_SKEW<1>
GPU_AGP_FBSKEW<1>
GPU_AGP_FBSKEW<0>
GPU_X1CLK_SKEW<0>
GPU_DVO_CLKP
GPU_DVO_DE
GPU_DVOD<23>
GPU_DVOD<22>
GPU_DVO_HSYNC
GPU_DVO_VSYNC
GPU_DVOD<21>
GPU_DVOD<19>
GPU_DVOD<18>
GPU_DVOD<16>
GPU_DVOD<17>
GPU_DVOD<14>
GPU_DVOD<15>
GPU_DVOD<11>
GPU_DVOD<13>
GPU_DVOD<12>
GPU_DVOD<10>
GPU_DVOD<9>
GPU_DVOD<8>
GPU_DVOD<6>
GPU_DVOD<7>
GPU_DVOD<5>
GPU_DVOD<4>
GPU_DVOD<3>
GPU_DVOD<2>
CLKLVDS_LN
TP_LVDS_L3P
CLKLVDS_LP
TP_LVDS_L3N
LVDS_L2P
LVDS_L1P
LVDS_L2N
LVDS_L1N
LVDS_L0P
LVDS_L0N
CLKLVDS_UN
CLKLVDS_UP
TP_LVDS_U3P
LVDS_U2P
TP_LVDS_U3N
LVDS_U1P
LVDS_U1N
LVDS_U2N
LVDS_U0P
LVDS_U0N
GPU_HSYNC
GPU_VSYNC
GPUVCORE_CNTL_L
GPU_SSCLK_IN
LVDS_DDC_DATA
LVDS_DDC_CLK
GPU_DVI_DDC_DATA
GPU_DVI_DDC_CLK
SI_DDC_CLK
GPU_HPD
GPU_TESTEN
GPU_DVOD<20>
_PP3V3_GPU
_PP1V8_GPU
40
40
40
40
40
40
41
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
39
39
39
39
39
39
39
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
39
40
41
41
41
41
41
41
41
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
37
37
37
37
37
37
37
41
41
62
62
62
62
62
62
62
62
41
41
41
41
41
41
41
41
41
41
41
41
41
41
41
41
41
41
41
41
41
41
41
41
41
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
42
42
41
37
37
39
39
39
39
39
39
39
41
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
39
39
39
39
39
39
5
39
39
14
5
5
5
40
5
39
5
42
42
5
42
42
42
42
42
42
39
39
37
41
41
41
41
41
41
41
41
42
41
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
42
42
38
37
6
6
42
42
41
42
39
5
5
Preliminary
Page 40
CONT
NOISE
VIN
VOUT
GND
CONT
NOISE
VIN
VOUT
GND
VDDR1
DVOVMODE
LVDDR_25
LVDDR_25
VSS2DI
VSS1DI
VDD2DI
VDD1DI
(4 OF 6)
RAGE_MOBILITY
PVSS
AVSSQ
AVSSN1
AVSSN0
A2VSSQ
A2VSSN0
A2VSSN1
VSSRH0
VSSRH1
VDDR1
A2VDD0
A2VDD1
PVDD
AVDD1
AVDD0
A2VDDQ
VDDRH0
VDDRH1
VDDP
LPVSS
TPVSS
MPVSS
LVSSR0
LVSSR1
LVSSR2
LVSSR3
VDDM
LVDDR_18
LVDDR_18
LPVDD
TPVDD
MPVDD
TXVDDR3
TXVDDR0
TXVDDR1
TXVDDR2
TXVSSR3
TXVSSR2
TXVSSR1
VDDR3
VDDR4
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
1.8V DVO POWER (EXT. TMDS)
Notice this is FB_VIO as well!
M11 POWER
M10 SHUT DOWN POWER SEQUENCING
MEMORY I/O
AGP 4X I/O - 1.5V
(or 2.5V)
(21mA)
(or 2.5V)
(AVDD+VDDDI=75mA)
(100mA MAX)
(Total PVDD = 66mA)
GPU PLL - 1.8V
(1200mA)
(AVDD+VDDDI=75mA)
(2mA)
(20mA)
(40mA)
(140mA)
(20mA)
(350mA)
(180mA)
LVDS - 2.5V
MEMORY PLL - 1.8V
(1800mA)
LVDS PLL - 1.8V
MEMORY CORE - 1.8V/2.5V
LVDS/TMDS - 1.8V
2
1
C5200
20%
0.1uF
CERM
402
10V
2
1
C5201
0.1uF
402
10V
20%
CERM
2
1
C5202
805
10uF
20%
6.3V
CERM
2
1
C5203
0.1uF
402
CERM
20%
10V
2
1
C5204
20%
402
CERM
10V
0.1uF
2
1
C5205
20%
10V
402
0.1uF
CERM
2
1
C5206
0.1uF
20%
10V
CERM
402
2
1
C5207
10V
402
CERM
0.1uF
20%
2
1
C5208
CERM
402
0.1uF
10V
20%
2
1
C5209
6.3V
20%
10uF
805
CERM
2
1
C5210
20%
10V
402
CERM
0.1uF
2
1
C5211
6.3V
CERM
805
20%
10uF
2
1
C5212
20%
10V
0.1uF
402
CERM
2
1
C5213
16V
402
CERM
20%
0.01uF
2
1
C5214
0.1uF
CERM
402
10V
20%
2
1
C5215
20%
10V
402
CERM
0.1uF
2
1
C5216
402
0.1uF
20%
CERM
10V
2
1
C5217
CERM
10V
402
20%
0.1uF
2
1
C5218
10V
0.1uF
20%
CERM
402
2
1
C5219
20%
402
10V
CERM
0.1uF
2
1
C5220
16V
CERM
20%
402
0.01uF
2
1
C5221
0.01uF
16V
20%
402
CERM
2
1
C5222
10V
CERM
402
0.1uF
20%
2
1
C5223
0.01uF
402
20%
16V
CERM
2
1
C5224
0.1uF
CERM
402
10V
20%
2
1
C5225
20%
402
CERM
0.1uF
10V
2
1
C5226
20%
10V
402
CERM
0.1uF
2
1
C5227
402
CERM
0.01uF
16V
20%
2
1
C5228
20%
6.3V
805
CERM
10uF
2
1
C5229
10V
402
CERM
20%
0.1uF
2
1
C5230
0.01uF
CERM
20%
402
16V
2
1
C5231
CERM
402
0.1uF
20%
10V
2
1
C5232
402
0.01uF
20%
CERM
16V
2
1
C5233
20%
402
0.01uF
CERM
16V
2
1
C5234
20%
10V
CERM
402
0.1uF
2
1
C5235
10V
20%
402
0.1uF
CERM
2
1
C5236
20%
16V
CERM
402
0.01uF
2
1
C5237
0.1uF
CERM
402
20%
10V
2
1
C5238
20%
0.1uF
CERM
10V
402
2
1
C5239
CERM
402
0.01uF
20%
16V
2
1
C5240
0.1uF
CERM
402
10V
20%
2
1
C5241
0.01uF
16V
20%
402
CERM
2
1
C5242
0.01uF
402
CERM
20%
16V
2
1
C5243
0.01uF
16V
CERM
20%
402
2
1
C5244
0.01uF
402
20%
CERM
16V
2
1
C5245
CERM
20%
16V
0.01uF
402
2
1
C5246
402
20%
10V
CERM
0.1uF
2
1
C5247
0.1uF
CERM
402
10V
20%
2
1
C5248
402
20%
CERM
10V
0.1uF
2
1
C5249
0.1uF
20%
10V
402
CERM
2
1
C5250
CERM
10V
20%
0.1uF
402
2
1
C5251
402
0.01uF
20%
CERM
16V
2
1
C5252
20%
0.01uF
16V
CERM
402
2
1
C5253
CERM
0.01uF
20%
16V
402
2
1
C5254
CERM
16V
20%
402
0.01uF
2
1
C5255
0.01uF
CERM
402
20%
16V
2
1
C5256
16V
20%
402
CERM
0.01uF
2
1
C5257
0.01uF
16V
20%
402
CERM
2
1
C5258
0.01uF
20%
402
16V
CERM
2
1
C5259
16V
0.01uF
20%
CERM
402
2
1
C5260
0.01uF
20%
402
CERM
16V
2
1
C5261
0.01uF
CERM
20%
16V
402
2
1
C5262
20%
10uF
805
6.3V
CERM
2
1
C5263
CERM
20%
805
10uF
6.3V
2
1
C5264
0.01uF
CERM
402
16V
20%
2
1
C5265
10uF
20%
CERM
6.3V
805
2
1
C5266
CERM
20%
6.3V
805
10uF
2
1
C5267
CERM
805
10uF
20%
6.3V
2
1
C5268
CERM
20%
805
6.3V
10uF
2
1
C5269
6.3V
10uF
805
20%
CERM
2
1
C5270
CERM
20%
6.3V
805
10uF
2
1
C5271
CERM
10V
0.1uF
402
20%
2
1
C5272
6.3V
10uF
20%
805
CERM
2
1
C5273
10uF
6.3V
CERM
805
20%
2
1
C5274
CERM
0.1uF
402
10V
20%
21
L5200
FERR-220-OHM
0402
21
L5201
0402
FERR-220-OHM
21
L5202
FERR-220-OHM
0402
21
L5203
FERR-220-OHM
0402
21
L5204
FERR-220-OHM
0402
21
L5205
FERR-220-OHM
0402
21
L5206
FERR-220-OHM
0402
21
L5207
FERR-220-OHM
0402
21
L5208
FERR-220-OHM
0402
2
1
C5275
20%
CERM
6.3V
805
10uF
21
L5209
FERR-220-OHM
0805
21
L5210
SM
FERR-10-OHM-500MA
21
L5211
FERR-220-OHM
0805
2 1
L5212
SM
FERR-10-OHM-500MA
21
L5213
SM
FERR-10-OHM-500MA
43
DP5290
SOT-363
BAS16TW
52
DP5290
BAS16TW
SOT-363
61
DP5290
SOT-363
BAS16TW
21
XW5293
SM
21
XW5290
SM
PP2V5_GPU_NECK2
21
XW5291
SM
PP1V8_GPU_NECK
21
XW5292
SM
PP1V5_GPU_NECK
2
1
C5276
20%
0.01uF
16V
CERM
402
2
1
C5277
CERM
20%
805
6.3V
10uF
51
4
2
3
U5290
MM1571J
GPUTPVDD_NOISE
SOT-25A
CRITICAL
2
1
C5278
10%
6.3V
CERM
1uF
402
2
1
C5279
CERM
402
16V
10%
0.01UF
2
1
C5280
10UF
20%
6.3V
CERM
805
21
L5214
FERR-220-OHM
0402
51
4
2
3
U5280
SOT-25A
CRITICAL
MM1571J
2
1
C5281
CERM
10%
1uF
6.3V
402
2
1
C5282
10uF
CERM
6.3V
20%
805
2
1
C5283
20%
CERM
10V
402
0.1uF
2
1
C5284
0.1uF
10V
CERM
20%
402
M6
F20
AF19
AG23
N6
F19
AE8
AF7
AE7
AF6
AE25
AD25
AF10
AF9
AE9
AF8
AF26
AE26
R5
P5
N5
M5
L5
E25
E24
E23
E22
E21
E17
E16
K5
E15
E14
E11
E10
E9
H26
E7
J26
J25
H25
J5
F22
F21
F16
F15
F9
F8
AA6
Y6
R6
K6
H5
G26
AD5
AC5
AB5
AA5
Y5
W5
V5
U5
T5
G5
F5
N26
M26
L26
K26
AA25
K27
Y28
T25
AC26
AB26
AA26
Y26
V26
U26
T26
R26
P26
L25
K25
F26
E26
E20
E19
E18
E13
E12
E6
E5
AF20
AH23
AH15
AH14
AH13
AG15
AG14
AG13
AG12
AJ11AK11
AK30AK29
A6A7
AF18
AH17
AG17
AH16
AF17
AG16
AF16
AE16
AJ21AK21
AH12
AF22
AE23
AE22
AF24
AF23
AJ22
AE20
AE19
AJ23
AF21
AE21
U4900
OMIT
M10-CSP64
64MB
BGA
2
1
C5292
0.1uF
CERM
402
10V
20%
2
1
C5295
10V
402
CERM
0.1uF
20%
2
1
C5298
0.1uF
CERM
402
10V
20%
2
1
C5293
20%
10V
CERM
0.1uF
402
2
1
C5296
0.1uF
CERM
402
10V
20%
2
1
C5299
20%
10V
402
CERM
0.1uF
2
1
C5294
0.1uF
CERM
402
10V
20%
2
1
C5297
20%
10V
402
CERM
0.1uF
2
1
R5201
INT_TMDS
402
MF
1/16W
5%
0
21
R5200
EXT_TMDS
0
5%
1/16W
MF
402
2
1
R5280
INT_TMDS
603
0
5%
1/16W
MF
21
L5280
FERR-10-OHM-500MA
EXT_TMDS
SM
03
051-6532
52 103
MIN_LINE_WIDTH=15 mil
MIN_NECK_WIDTH=10 mil
VOLTAGE=1.8V
PP1V8_GPU_AVDD
MIN_LINE_WIDTH=15 mil
MIN_NECK_WIDTH=10 mil
VOLTAGE=1.8V
PPDVO_GPU_VDDR4
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=25 mil
VOLTAGE=1.8V
PPVIO_GPUFB
VOLTAGE=1.8V
PPVCORE_GPUFB_VDDM
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=25 mil
_PP3V3_GPU
VOLTAGE=3.3V
MIN_LINE_WIDTH=10 mil
MIN_NECK_WIDTH=10 mil
PP3V3_GPU_VDDR3
_PP2V5_GPU
VOLTAGE=1.8V
MIN_NECK_WIDTH=10 mil
PP1V8_GPU_TPVDD_LDO
MIN_LINE_WIDTH=15 mil
PP1V8_GPU_LVDDR
MIN_NECK_WIDTH=10 mil
VOLTAGE=1.8V
MIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=10 mil
PP1V8_GPU_TPVDD
MIN_LINE_WIDTH=15 mil
VOLTAGE=1.8V
PP1V8_GPU_VDDDI
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=15 mil
VOLTAGE=1.8V
PP1V8_GPU_PVDD_LDO
MIN_LINE_WIDTH=15 mil
VOLTAGE=1.8V
MIN_NECK_WIDTH=10 mil
MIN_NECK_WIDTH=10 mil
VOLTAGE=1.8V
PP1V8_GPU_A2VDDQ
MIN_LINE_WIDTH=10 mil
_PPVCORE_GPUFB
GPUPVDD_NOISE
MIN_LINE_WIDTH=10 mil
MIN_NECK_WIDTH=10 mil
GPUPVDD_EN
_PP2V5_GPU
_PP1V8_GPU
_PP1V8_GPU
_PP1V8_GPU
PP1V8_GPU_PVDD_LDO
PP1V8_GPU_PVDD_LDO
GPUPVDD_EN
_PP2V5_GPU
_PP2V5_GPU
MIN_NECK_WIDTH=8 mil
MIN_LINE_WIDTH=8 mil
MIN_NECK_WIDTH=8 mil
MIN_LINE_WIDTH=8 mil
_PP3V3_GPU
MIN_NECK_WIDTH=8 mil
MIN_LINE_WIDTH=8 mil
PP1V8_GPU_MPVDD
VOLTAGE=1.8V
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=15 mil
_PP1V8_GPU
PP1V8_GPU_PVDD
VOLTAGE=1.8V
MIN_LINE_WIDTH=15 mil
MIN_NECK_WIDTH=10 mil
_PP1V5_GPU_AGP
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=20 mil
VOLTAGE=2.5V
PP2V5_GPU_A2VDD
_PP1V5_GPU_AGP
_PPVCORE_GPUFB
_PP2V5_GPU
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=10 mil
_PPVCORE_GPUFB
PP1V5_GPU_VDDP
VOLTAGE=1.5V
MIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=10 mil
_PP1V8_GPU
MIN_NECK_WIDTH=8 mil
MIN_LINE_WIDTH=8 mil
PP3V3_GPU_NECK
PPVIO_GPUFB
PP1V8_GPU_LPVDD
VOLTAGE=1.8V
MIN_LINE_WIDTH=15 mil
MIN_NECK_WIDTH=10 mil
PP2V5_GPU_LVDDR
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=20 mil
VOLTAGE=2.5V
ATI_DVOVMODE
_PP1V8_GPU
_PP1V8_GPU
PPVCORE_GPUFB_VDDRH
VOLTAGE=1.8V
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=20 mil
41
41
41
41
41
41
41
40
40
40
40
40
40
40
40
40
40
40
39
40
39
39
39
39
39
39
39
40
40
39
39
39
37
40
40
37
40
40
37
37
37
40
40
40
40
40 37
37
37
37
37
40
37
37
37
37
40
5
5
39
5
14
5
5
5
5
39
39
14
5
5 5
5
14
5
5
5
5
5
5
40
5
5
Preliminary
Page 41
PGND2
PGND1
PGND1
PGND2
MVREF
SVREF
RSVD
STX2+
STX2-
STX1-
STX1+
STX0+
STX0-
STXC-
STXC+
MTX2+
MTX2-
MTX1-
MTX1+
MTX0+
MTX0-
MTXC+
MTXC-
MMSEN
SMSEN
PVCC1
PVCC1
AVCC
VCC
PGND1
SSDA
SSCL
MSDA
MSCL
SRSET#
MRSET#
MPD
SPD
SEDGE/HTP
MEDGE/HTP
SHSYNC
MHSYNC
MIDCK+
MVSYNC
SVSYNC
SIDCK+
MIDCK-
SIDCK-
SDE
MDE
SDK3
SDK1
MDK3
MDK1
SD14/SYNCO
SD13/MAST
SD12/DUAL
MD14/SYNCO
MD13/MAST
MD12/DUAL
SD11
SD9
SD10
MD11
MD10
MD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
PVCC1
PVCC2
PVCC2
SEXT_SWING
MEXT_SWING
AGND
GND
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Page Notes
TRACE SO THAT IT MAY BE CUT BETWEEN CAPS
EXTERNAL TMDS TERMINATION
strap 1 -> I2C enabled
active-high HTP
NC
ATI TMDS
BOM options provided by this page:
Net Spacing Type: TMDS
NC
NC
Line To Line: 15 mils
NOTE: Target differential impedance for
Power aliases required by this page:
TMDS data pairs is 100 ohms.
Primary Max Sep: 10 mils
Length Tolerance: 50 mils
Secondary Length: 250 mils
Secondary Max Sep: 100 mils
Signal aliases required by this page:
(NONE)
(NONE)
(None)
strap 0 -> reset function
NC
/SYNCI
NC
SILICON IMAGE TMDS
ATI TMDS
TRACE SO THAT IT MAY BE CUT BETWEEN CAPS
CMF LINE SHOULD BE ROUTED AS 4MIL SURFACE
INTERNAL TMDS TERMINATION
TERMINATION NETWORK SHOULD BE CONNECTED AS SHOWN
TERMINATION NETWORK SHOULD BE CONNECTED AS SHOWN
CMF LINE SHOULD BE ROUTED AS 4MIL SURFACE
NC
NC
21
L5720
SM-1
400-OHM-EMI
EXT_TMDS
2
1
C5722
50V
100pF
402
5%
CERM
EXT_TMDS
2
1
C5723
100pF
5%
50V
CERM
402
EXT_TMDS
2
1
C5724
EXT_TMDS
402
CERM
50V
5%
100pF
2
1
C5725
402
CERM
50V
EXT_TMDS
100pF
5%
2
1
C5721
5%
EXT_TMDS
100pF
402
50V
CERM
2
1
C5734
CERM
100pF
EXT_TMDS
402
50V
5%
2
1
C5733
100pF
5%
50V
CERM
402
EXT_TMDS
2
1
C5732
100pF
402
CERM
50V
5%
EXT_TMDS
2
1
C5731
100pF
EXT_TMDS
CERM
5%
50V
402
2
1
C5730
EXT_TMDS
CERM
6.3V
20%
10uF
805
2
1
C5720
EXT_TMDS
6.3V
10uF
805
20%
CERM
21
L5730
400-OHM-EMI
SM-1
EXT_TMDS
2
1
C5738
100pF
5%
50V
CERM
402
EXT_TMDS
2
1
C5737
CERM
402
50V
5%
EXT_TMDS
100pF
2
1
C5736
100pF
5%
50V
CERM
402
EXT_TMDS
21
L5739
400-OHM-EMI
SM-1
EXT_TMDS
2
1
C5726
10uF
805
CERM
6.3V
20%
EXT_TMDS
2
1
C5739
402
CERM
5%
100pF
EXT_TMDS
50V
2
1
C5735
805
CERM
6.3V
20%
10uF
EXT_TMDS
41
RP5707
EXT_TMDS
SM1
10
5%
1/16W
32
RP5707
SM1
1/16W
5%
10
EXT_TMDS
41
RP5708
1/16W
5%
SM1
10
EXT_TMDS
32
RP5709
5%
SM1
1/16W
10
EXT_TMDS
32
RP5708
SM1
1/16W
5%
10
EXT_TMDS
32
RP5710
10
EXT_TMDS
5%
1/16W
SM1
41
RP5709
EXT_TMDS
SM1
1/16W
5%
10
41
RP5710
SM1
EXT_TMDS
10
5%
1/16W
2
1
C5740
20%
10V
CERM
0.1uF
402
EXT_TMDS
2
1
R5740
402
MF
1/16W
1%
1K
EXT_TMDS
2
1
R5741
EXT_TMDS
1K
1%
1/16W
MF
402
2
1
R5745
330
5%
1/16W
MF
402
EXT_TMDS
2
1
R5746
1/16W
402
MF
5%
330
EXT_TMDS
21
R5705
49.9
1%
1/16W
MF
402
EXT_TMDS
21
R5704
1%
MF
402
EXT_TMDS
1/16W
49.9
2
1
C5705
EXT_TMDS
470PF
10%
CERM
402
50V
2
1
C5704
50V
402
10%
CERM
470PF
EXT_TMDS
21
R5703
402
MF
1/16W
1%
49.9
EXT_TMDS
21
R5702
402
MF
1/16W
1%
EXT_TMDS
49.9
2
1
C5703
470PF
10%
50V
CERM
EXT_TMDS
402
2
1
C5702
EXT_TMDS
470PF
10%
50V
CERM
402
21
R5700
EXT_TMDS
402
MF
1/16W
1%
49.9
21
R5701
49.9
1%
1/16W
MF
402
EXT_TMDS
2
1
C5701
EXT_TMDS
CERM
402
50V
10%
470PF
2
1
C5700
470PF
10%
50V
402
CERM
EXT_TMDS
41
RP5711
5%
1/16W
SM1
10
EXT_TMDS
32
RP5712
SM1
1/16W
5%
10
EXT_TMDS
32
RP5711
SM1
1/16W
5%
10
EXT_TMDS
41
RP5712
SM1
1/16W
5%
10
EXT_TMDS
32
RP5713
EXT_TMDS
5%
1/16W
10
SM1
41
RP5713
EXT_TMDS
10
5%
1/16W
SM1
2
1
R5750
10K
EXT_TMDS
402
MF
1/16W
5%
2
1
R5751
EXT_TMDS
1/16W
402
5%
10K
MF
H8H4D8
D4
L5
H3
K11
K10
G11
G10
H11
H10
J11
J10
K8
L8
J8
J7
L7
J1
H1
K5
K9
K6
J5
H6
J4
G2
H2
K4
J2
L4
K3
K2
K1
K7
L6
J6
F2
G1
L2
L3
C8
G3
E3
L10
F10
A10
G4
E4
L9F9A9
B5
D3
E11
E10
B11
B10
C11
C10
D11
D10
B8
A8
C7
B7
A7
C1
D1
A5
F8
A6
C5
D6
C4
B3
B2
B1
A4
D2
B4
E1
E2
F4
B6
C6
A2
A3
C2
F3
C3E8E7E6E5D7F1
L1
H7D5J3H5G8G7G6G5F7F6F5
A1
J9G9D9
B9
F11
L11
H9E9C9
A11
U5700
BGA
SIL1178
EXT_TMDS
2
1
R5754
MF
10K
EXT_TMDS
5%
402
1/16W
2
1
R5753
EXT_TMDS
5%
1/16W
402
10K
MF
2
1
R5752
1/16W
MF
402
10K
5%
EXT_TMDS
2
1
R5755
1/16W
10K
EXT_TMDS
402
MF
5%
21
R5761
EXT_TMDS
49.9
402
1%
1/16W
MF
21
R5760
MF
402
1/16W
1%
49.9
EXT_TMDS
2
1
C5761
470PF
402
50V
10%
CERM
EXT_TMDS
2
1
C5760
470PF
CERM
402
50V
10%
EXT_TMDS
21
R5763
EXT_TMDS
49.9
1%
1/16W
MF
402
2
1
C5763
402
470PF
10%
50V
CERM
EXT_TMDS
2
1
C5762
10%
50V
CERM
402
EXT_TMDS
470PF
21
R5765
EXT_TMDS
49.9
1/16W
402
1%
MF
21
R5762
402
MF
1/16W
1%
49.9
EXT_TMDS
21
R5764
402
MF
1/16W
1%
49.9
EXT_TMDS
2
1
C5765
470PF
10%
50V
CERM
402
EXT_TMDS
2
1
C5764
470PF
10%
50V
CERM
402
EXT_TMDS
21
R5767
49.9
1%
1/16W
MF
402
EXT_TMDS
2
1
C5767
CERM
402
50V
10%
470PF
EXT_TMDS
2
1
C5766
CERM
402
50V
10%
470PF
EXT_TMDS
21
R5766
402
MF
1/16W
1%
49.9
EXT_TMDS
41
RP5714
INT_TMDS
1/16W
5%
SM1
0
32
RP5714
0
5%
1/16W
SM1
INT_TMDS
41
RP5715
INT_TMDS
5%
0
SM1
1/16W
32
RP5716
0
INT_TMDS
SM1
1/16W
5%
32
RP5715
5%
1/16W
INT_TMDS
0
SM1
32
RP5717
0
5%
1/16W
SM1
INT_TMDS
41
RP5716
INT_TMDS
5%
SM1
1/16W
0
41
RP5717
INT_TMDS
SM1
1/16W
5%
0
2
1
R5756
402
5%
1/16W
MF
10K
EXT_TMDS
2
1
R5758
EXT_TMDS
5%
1/16W
MF
402
10K
2
1
R5757
MF
10K
1/16W
402
EXT_TMDS
5%
41
RP5702
SM1
5%
1/16W
INT_TMDS
10
41
RP5703
10
SM1
1/16W
5%
INT_TMDS
32
RP5702
10
5%
1/16W
SM1
INT_TMDS
32
RP5704
INT_TMDS
SM1
1/16W
5%
10
32
RP5703
5%
SM1
INT_TMDS
10
1/16W
41
RP5704
1/16W
SM1
5%
10
INT_TMDS
32
RP5706
1/16W
5%
10
SM1
INT_TMDS
41
RP5706
10
5%
1/16W
SM1
INT_TMDS
2
1
C5710
INT_TMDS
470PF
10%
50V
402
CERM
2
1
C5711
INT_TMDS
470PF
10%
50V
402
CERM
21
R5707
INT_TMDS
402
MF
1/16W
1%
49.9
21
R5708
INT_TMDS
1%
1/16W
MF
402
49.9
21
R5709
49.9
1%
1/16W
MF
402
INT_TMDS
2
1
C5712
402
CERM
50V
10%
470PF
INT_TMDS
2
1
C5713
10%
402
CERM
50V
470PF
INT_TMDS
21
R5710
49.9
1%
MF
402
1/16W
INT_TMDS
21
R5711
INT_TMDS
49.9
1%
1/16W
MF
402
2
1
C5714
INT_TMDS
470PF
10%
50V
CERM
402
2
1
C5715
50V
470PF
10%
CERM
402
INT_TMDS
21
R5712
INT_TMDS
49.9
1%
1/16W
MF
402
21
R5713
INT_TMDS
1%
1/16W
MF
402
49.9
2
1
C5716
INT_TMDS
402
CERM
50V
10%
470PF
2
1
C5717
INT_TMDS
470PF
CERM
402
50V
10%
21
R5714
INT_TMDS
MF
402
1/16W
1%
49.9
03
57 103
051-6532
SI_DDC_DATA
SI_DDC_CLK
SI_I2CSEL
_GPU_RESET_L
SI_RESET_L
GPU_DVO_HSYNC
SI_HTP
GPU_DVOD<22>
GPU_DVOD<7>
GPU_DVOD<4>
GPU_DVO_VSYNC
GPU_DVOD<19>
GPU_DVOD<17>
PP3V3_SI_AVCC
MIN_NECK_WIDTH=10 MIL
MIN_LINE_WIDTH=15 MIL
SI_PRIMARY
SI_DUAL_MODE
GPU_DVOD<11>
GPU_DVOD<10>
GPU_DVOD<9>
GPU_DVOD<8>
GPU_DVOD<5>
GPU_DVO_CLKP
GPU_DVOD<21>
GPU_DVOD<20>
GPU_DVOD<15>
GPU_DVOD<14>
GPU_DVOD<13>
GPU_DVOD<12>
SI_SYNC
SI_MEXTSWING
GPU_TMDS_DN_R<1>
TMDS_CLKN
TMDS_DN<0>
TMDS_DP<1>
TMDS_DP<2>
TMDS_CLKP
TMDS_DP<0>
TMDS_DN<1>
TMDS_DN<2>
GPU_TMDS_DP_R<2>
GPU_TMDS_DN_R<2>
GPU_TMDS_DP_R<0> GPU_TMDS_DN_R<0>
GPU_TMDS_CLKP_R GPU_TMDS_CLKN_R
INT_TMDS_D2_CMF
INT_TMDS_D0_CMF
INT_TMDS_CLK_CMF
GPU_TMDS_DN<2>
GPU_TMDS_DN<1>
GPU_TMDS_DP_R<2>
GPU_TMDS_DP<0>
GPU_TMDS_DP_R<0>
GPU_TMDS_DP<1>
GPU_TMDS_DP_R<1>
GPU_TMDS_DN<0>
GPU_TMDS_DN_R<0>
GPU_TMDS_CLKP
GPU_TMDS_CLKN
SI_TMDS_DN<5>
SI_TMDS_DN<5>
TMDS_DN<5>
SI_TMDS_DP<5>
TMDS_DP<5>
SI_TMDS_DN<4>
TMDS_DN<4>
SI_TMDS_DP<3>
TMDS_DP<3>
SI_TMDS_DP<4>
TMDS_DP<4>
SI_TMDS_DN<2>
SI_TMDS_DN<3>
TMDS_DN<3>
SI_TMDS_DP<2>
SI_TMDS_DN<1>
SI_TMDS_DP<0>
SI_TMDS_DP<1>
SI_TMDS_DN<0>
SI_TMDS_CLKN
_PP1V8_GPU
SI_TMDS_DP<5>
SI_TMDS_DN<4>
SI_TMDS_DP<4>
SI_TMDS_DP<3>
SI_TMDS_DP<2>
SI_TMDS_DN<2>
SI_TMDS_DN<1>
SI_TMDS_DP<1>
SI_TMDS_DP<0>
SI_TMDS_DN<0>
SI_TMDS_CLKP
SI_TMDS_CLKN
SI_SEXTSWING
SI_VREF
MIN_LINE_WIDTH=8 MIL
MIN_NECK_WIDTH=8 MIL
SI_MSEN_OC
SI_TMDS_DN<3>
GPU_TMDS_DP<2>
GPU_TMDS_DP_R<1>
GPU_TMDS_CLKP_R
_PP3V3_RUN_SI
GPU_TMDS_CLKN_R
GPU_TMDS_DN_R<1>
INT_TMDS_D1_CMF
EXT_TMDS_CLK_CMF
EXT_TMDS_D2_CMF
TMDS_CLKP
TMDS_DP<0>
TMDS_DP<1>
TMDS_DP<2>
TMDS_CLKN
EXT_TMDS_D0_CMF
TMDS_DN<0>
TMDS_DN<1>
TMDS_DN<2>
TMDS_D3_CMF
TMDS_D4_CMF
TMDS_D5_CMF
TMDS_DN<3>
TMDS_DN<4>
TMDS_DP<3>
TMDS_DP<4>
TMDS_DN<5>TMDS_DP<5>
TMDS_CLKN
GPU_TMDS_CLKN_R
TMDS_DN<0>
GPU_TMDS_DN_R<0>
TMDS_DP<1>
GPU_TMDS_DP_R<1>
TMDS_CLKP
GPU_TMDS_CLKP_R
TMDS_DP<0>
GPU_TMDS_DP_R<0>
TMDS_DP<2>
GPU_TMDS_DP_R<2>
TMDS_DN<1>
GPU_TMDS_DN_R<1>
TMDS_DN<2>
GPU_TMDS_DN_R<2>
PP3V3_SI_PVCC
MIN_LINE_WIDTH=15 MIL
MIN_NECK_WIDTH=10 MIL
SI_TMDS_CLKP
GPU_TMDS_DN_R<2>
EXT_TMDS_D1_CMF
GPU_DVOD<6>
GPU_DVOD<16>
GPU_DVOD<23>
GPU_DVO_DE
SI_SECONDARY
GPU_DVOD<18>
PP3V3_SI_VCC
MIN_NECK_WIDTH=10 MIL
MIN_LINE_WIDTH=15 MIL
GPU_DVOD<3>
GPU_DVOD<2>
GPU_DVOD<1>
GPU_DVOD<0>
62
62
62
62
62
62
40
62
62
62
62
62
62
62
62
62
62
62
62
62
42
42
42
62
42
42
42
62
62
62
62
62
62
39
62
42
42
42
62
42
42
42
62
62
62
62
62 62
62
42
42
62
42
42
42
42
37
62
42
41
41
41
42
41
41
41
62 62
62 62
62 62
62
62
62
62 62
62 62
62 62
62
62
62
62 42
62 42
62 42
62 42
62 42
62
62 42
62
62
62
62
62
62
37
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
42
41
41
41
42
41
41
41
42
42
42
42
42 42
42 62
41 62
41 62
42 62
41 62
41 62
41 62
41 62
62
62
39
39
5
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
39
41
41
6
6
6
41
6
6
6
41 41
41 41
41 41
39
39
41
39 41
39 41
39 41
39
39
41
41 41
41 41
41 41
41 41
41 41
41
41 41
41
41
41
41
41
41
5
41
41
41
41
41
41
41
41
41
41
41
41
41
39
41
41
5
41
41
41
6
6
6
41
6
6
6
41
41
41
41
41 41
41 41
6
41
6
41
41 41
6
41
6
41
6
41
6
41
41
41
39
39
39
39
39
39
39
39
39
Preliminary
Page 42
G2
D2
S2
G1
S1
D1
G
SD
G
SD
G
SD
G
D
S
G
DS
SYM_VER-1
MINIDIN
S
D
G
G
DS
D
S
G
LCFILTER
LCFILTER
LCFILTER
SYM_VER-1
SYM_VER-1
32
32
32
SYM_VER-1
SYM_VER-1
SYM_VER-1
SYM_VER-1
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
LCD INTERFACE
LCD POWER SWITCH
100K pull-ups are for
Panel has 2K pull-ups
no-panel case (development)
TMDS FILTERING
PLACE CLOSE TO CONNECTOR
S-VIDEO/COMP OUT INTERFACE
EXTERNAL VIDEO (DVI) INTERFACE
(55mA requirement per DVI spec)
GPU DURING SHUTDOWN. WHEN
device path into DDC_CLK.
Isolation will be disabled as well.
will be low, TP0610 will turn
As host rails rise, TP0610
will turn off, as will remote
on, driving SOFT_PWR_ON_L low.
Power key detect path when
is pressed, 5V will be driven
power key on remote device
system is shutdown or asleep..
into DDC_CLK. Since host rails
DDC_CLK is isolated from
pullup.
powered DDC clock
Pulldown prevents
has active, self-
3904 from turning
on when DVI monitor
(LVDS DDC POWER)
PLACE NEAR C5A & C5B
VIDEO CONNECTORS
(+5V_DDC SLEEP)
3V LEVEL SHIFTERS
ANALOG FILTERING
NC
DVI POWER SWITCH
Isolation required for DVI power switch
PLACE CLOSE TO CONNECTOR
graphics controller
Place GND shorts at
graphics controller
Place GND shorts at
VGA VSYNC BUFFERS
NOTE: Pulldown for DVI_HPD provided by DVI power switch interface
DVI DDC CURRENT LIMIT
Q5909 shares with ALS sensor to save space
PLACE NEAR 3, 11 & 19
when system is running.
HPD normally driven to
on remote device pressed,
HPD will be driven to 5V.
COMPARATOR ENABLED BY GPU’s
GPIO.
Power key detect path
3.3V. When power key
NEED PULL-DOWN BECAUSE THIS
SIGNAL IS TRISTATED INITIALLY
INVERTER EXPECTS ACTIVE HIGH SIGNAL
INVERTER INTERFACE
PP5V_PWRON
2
1
R5984
402
MF
1/16W
5%
100K
2
1
C5982
402
50V
CERM
20%
0.001UF
2
1
C5981
0.001UF
402
50V
20%
CERM
2
1
C5980
402
0.001UF
CERM
50V
20%
2
1
C5984
CERM
6.3V
20%
805
10UF
12
L5980
FERR-1K-OHM-EMI
SM
21
L5982
400-OHM-EMI
SM-1
PP3V3_ALL
2
1
C5983
0.1UF
402
CERM
10V
20%
4
3
2
6
Q5984
FDG6324L
SC70-6
1
5
6
Q5984
FDG6324L
SC70-6
2
1
C5910
3.3PF
CERM
50V
402
0.25%
2
1
C5911
0.25%
3.3PF
402
50V
CERM
2
1
C5912
402
0.25%
CERM
50V
3.3PF
2
1
R5908
402
MF
1/16W
5%
10K
2
1
R5907
MF
10K
5%
1/16W
402
1
2
6
Q5907
SOT-363
2N7002DW
PP3V3_RUN
4
5
3
Q5907
2N7002DW
SOT-363
2
1
R5909
100K
MF
1/16W
402
5%
2
1
C5905
CERM
50V
402
5%
100pF
2
1
R5902
402
MF
5%
1/16W
4.7K
2
1
R5903
402
MF
5%
4.7K
1/16W
2
1
C5904
50V
CERM
5%
100pF
402
2
1
C5900
0.01UF
50V
603
CERM
20%
21
L5900
400-OHM-EMI
SM-1
4
5
3
Q5909
SOT-363
2N7002DW
21
F5900
0.5AMP-13.2V
SM
21
D5900
MBR0530
SM
2
1
C5906
100pF
402
5%
50V
CERM
2
3
1
Q5930
SM
2N3904
21
R5930
20K
402
MF
1/16W
5%
2
1
C5920
0.1UF
402
CERM
10V
20%
2
1
R5920
402
MF
1%
1/16W
68.1K
2
5
1
3
4
U5920
CRITICAL
SM
LMC7211
21
R5922
1/16W
10K
1%
MF
402
2
1
R5921
100K
1%
1/16W
MF
402
2
1
R5923
MF
1/16W
1%
10K
402
1
2
6
Q5925
2N7002DW
SOT-363
2
1
R5926
1/16W
100K
MF
402
5%
2
3
1
Q5935
SM
2N3904
21
R5935
1/16W
MF
402
10K
5%
2
1
R5934
330
402
MF
1/16W
5%
2
1
3
Q5933
TP0610
SM
2
1
C5960
0.01UF
CERM
50V
20%
603
21
L5960
FERR-10-OHM-500MA
SM
21
L5962
0603
3.3UH
21
L5963
3.3UH
0603
2
1
C5961
CERM
50V
20%
603
0.01UF
21
L5964
0603
3.3UH
21
L5961
FERR-10-OHM-500MA
SM
PP3V3_RUN
PP5V_RUN
21
XW5960
SM
21
XW5961
SM
2
1
R5900
5%
1/16W
MF
402
0
2
1
R5901
402
0
MF
1/16W
5%
21
R5904
100
MF
402
1/16W
5%
21
R5905
5%
1/16W
MF
402
100
21
R5906
5%
1/16W
MF
100
402
4
3
2
1
6
5
J5980
CRITICAL
SM-2MT
21
L5981
400-OHM-EMI
SM-1
4
32
1
L5915
CRITICAL
165-OHM
SM
5
4 3
2 1
1110
98
J5960
CRITICAL
RT-TH
MH1177
2
1
C5970
CERM
402
20%
0.001uF
50V
2
1
R5973
100K
402
MF
1/16W
5%
2
1
C5973
20%
50V
CERM
402
0.001uF
PP3V3_RUN
2
1
R5972
100K
402
MF
1/16W
5%
9
8
7
6
5
4
30
3
29
28
27
26
25
24
23
22
21
20
2
19
18
17
16
15
14
13
12
11
10
1
34
33
J5970
F-RT-SM
CRITICAL
G-501973
2 1
C5971
20%
50V
CERM
402
0.001uF
2
1
C5975
0.001uF
402
CERM
50V
20%
21
L5975
SM
FERR-250-OHM
PP3V3_PWRON
21
C5976
50V
CERM
10%
402
0.0022uF
4
3 6
5
2
1
Q5975
TSOP
SI3443DV
21
R5976
402
MF
1/16W
100K
5%
2
1
R5977
100K
5%
1/16W
MF
402
2
1
3
Q5977
2N7002
SM
2 1
R5933
402
MF
1/16W
5%
680
21
C5999
0.01uF
603
CERM
50V
20%
9
8
7
6
5
4
3
24
23
22
21
20
2
19
18
17
16
15
14
13
12
11
10
1
36
35
34
33
32
31
C5B C5A
C4
C3
C2
C1
J5900
CRITICAL
QH1112
F-RT-TH
21
R5999
0
5%
1/16W
MF
402
2
1
R5929
68K
5%
1/16W
MF
402
2
1
3
Q5926
SM
TP0610
2
1
R5928
330
402
1/16W
5%
MF
2
1
C5929
6.3V
20%
1210
CERM
47UF
4
5
3
Q5925
SOT-363
2N7002DW
2
1
R5927
5%
1/16W
MF
402
100K
2
1
R5925
100K
5%
1/16W
MF
402
2
1
C5972
NO STUFF
402
CERM
50V
20%
0.001uF
2
1
C5967
402
560PF
10%
50V
CERM
2
1
C5968
402
CERM
50V
10%
560PF
2
1
C5969
402
560PF
10%
50V
CERM
2
1
C5962
560PF
10%
50V
CERM
402
2
1
C5963
402
560PF
10%
50V
CERM
2
1
C5964
560PF
10%
50V
CERM
402
43
21
FL5910
CRITICAL
SM-220MHZ
43
21
FL5911
SM-220MHZ
CRITICAL
43
21
FL5912
CRITICAL
SM-220MHZ
4
32
1
L5916
CRITICAL
2012H
90-OHM-300mA
4
32
1
L5917
CRITICAL
90-OHM-300mA
TMDS_CONN_DN<1>
2012H
5
4
2
1
3
U5914
CRITICAL
74AHC1G32
SM
VGA_VSYNC_BUF
5
4
2
1
3
U5913
74AHC1G32
SM
CRITICAL
VGA_HSYNC_BUF
21
R5913
402
MF
1/16W
5%
33
21
R5914
402
MF
1/16W
5%
33
PP3V3_PWRON
5
4
2
1
3
U5983
CRITICAL
74AHC1G32
SM
4
32
1
L5918
2012H
TMDS_CONN_DN<2>
TMDS_CONN_DP<2>
90-OHM-300mA
CRITICAL
4
32
1
L5919
90-OHM-300mA
2012H
CRITICAL
4
32
1
L5920
2012H
90-OHM-300mA
CRITICAL
TMDS_CONN_DN<4>
4
32
1
L5921
CRITICAL
90-OHM-300mA
2012H
TMDS_CONN_DP<5>
TMDS_CONN_DN<5>
051-6532
5903103
MIN_NECK_WIDTH=10 MIL
MIN_LINE_WIDTH=20 MIL
PPBUS_INVERTER
_PPBUS_INV
BRIGHT_PWM
BRIGHT_PWM_UF
INV_ON_PWM
_PPBUS_ALL_A
GPU_DVI_DDC_DATA
DVI_HPD_UF
DVI_HPD_DIV
SYS_POWER_BUTTON_L
HPD_ON
HPD_PWR_SNS_EN
HPD_4V_REF
COMP_DISABLE
HPD_PWR_SW
COMP_ENABLE
HPD_ON_RC
HPD_BASE
TMDS_CONN_DP<2>
PP3V3_LCD
MIN_NECK_WIDTH=10 MIL
MIN_LINE_WIDTH=20 MIL
_GND_CHASSIS_LVDS
PP5V_RUN_DDC_F
MIN_LINE_WIDTH=10 MIL
MIN_NECK_WIDTH=10 MIL
MIN_LINE_WIDTH=10 MIL
MIN_NECK_WIDTH=10 MIL
DDC_CLK_ISO
DVI_HPD_UF
LVDS_U0P
GPU_HPD
VGA_R
VGA_VSYNC
VGA_HSYNC
GPU_VSYNC
GPU_HSYNC
FP_PWR_EN
GPU_TV_GND2
MIN_LINE_WIDTH=15 MIL
MIN_NECK_WIDTH=10 MIL
GPU_TV_GND1
MIN_LINE_WIDTH=15 MIL
MIN_NECK_WIDTH=10 MIL
GPU_COMP
_GND_CHASSIS_SVIDEO
TV_GND2
TV_COMP
GPU_C
GPU_Y
TV_C
TV_Y
TV_GND1
LCD_DIGON_L
LCD_PWREN_L
MIN_NECK_WIDTH=10 MIL
MIN_LINE_WIDTH=20 MIL
PP3V3_LCD_FET
LVDS_DDC_DATA
LVDS_L1P
LVDS_L1N
DVI_DDC_DATA
LVDS_U1P
LVDS_U2P
LVDS_U0N
LVDS_L0N
LVDS_DDC_CLK
TMDS_CONN_CLKN
VGA_B
CLKLVDS_UP
CLKLVDS_UN
LVDS_U2N
LVDS_U1N
LVDS_L0P
FP_PWR_EN_L
VGA_BGPU_B
GPU_G
GPU_R
VGA_G
PP5V_INVERTER
TMDS_CONN_DN<0> TMDS_CONN_DN<2>
VGA_G
VGA_HSYNC
_GND_CHASSIS_LVDS
VGA_VSYNC
LVDS_L2N
LVDS_L2P
CLKLVDS_LN
CLKLVDS_LP
DVI_DDC_CLK
GPU_DVI_DDC_CLK
_GND_CHASSIS_INV
MIN_NECK_WIDTH=10 MIL
MIN_LINE_WIDTH=10 MIL
PP5V_INVERTER_F
DVI_HPD
DVI_TURN_ON_BASE
DVI_TRUN_ON_ILIM
DVI_TURN_ON
DVI_DDC_CLK_UF
PP5V_RUN_DDC
FP_PWR_EN
_GND_CHASSIS_LVDS
PP5V_RUN_DDC
MIN_LINE_WIDTH=10 MIL
MIN_NECK_WIDTH=10 MIL
DVI_DDC_DATA_UF
DVI_DDC_CLK_UF
VGA_R
TMDS_CONN_DP<0>
_GND_CHASSIS_DVI_TOP
_GND_CHASSIS_DVI_BOTTOM
TMDS_CONN_DN<5>
TMDS_CONN_DP<5>
TMDS_CONN_DP<1>
TMDS_CONN_DP<4>
TMDS_CONN_DP<3>
TMDS_CONN_DN<1>
TMDS_CONN_DN<3>
TMDS_CONN_DN<4>
TMDS_CONN_CLKP
TMDS_CONN_DN<3>
TMDS_CONN_DP<3>
TMDS_DP<3>
TMDS_DN<3>
TMDS_CONN_DP<4>
TMDS_DP<4>
TMDS_DN<4>
TMDS_DP<5>
TMDS_DN<5>
TMDS_CONN_DN<0>
TMDS_CONN_DP<0>
TMDS_DP<0>
TMDS_DN<0>
TMDS_CONN_DP<1>
TMDS_DP<1>
TMDS_DN<1>
TMDS_DP<2>
TMDS_DN<2>
TMDS_CONN_CLKP
TMDS_CONN_CLKN
TMDS_CLKN
TMDS_CLKP
_GND_CHASSIS_INV
17
17
16
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
8
42
13
62
42
42
39
42
42
42
42
39
39
39
39
39
39
39
39
42
42
39
39
39
39
39
42
42
62 62
42 42
42
42
39
39
39
39
42
42
42
42
42
42
42
42
62
62
62
62
62
62
62
62
62
42
62
62 62
62
62 62
62
62
62
62
62 41
41
62 41
41
41
41
42
42 62
62
42
42
42
42
42
42
42
5
6
39
5
39
6
6
39
42
6
5
6
6
39
6
6
6
39
39
39
39
5
6
6
39
39
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
39
39
39
6
6
42 42
6 6
5
6
6
6
6
6
39
5
6
6
39
5
6
6
6
6
42
5
5
42
42
42
42
42
42
42
42
6
42
42 41
41
42 41
41
41
41
42
42
6
6
42
6
6
6
6
6
6
41
41
5
Preliminary
Page 43
HT_CTL_TXN0
HT_CTL_TXP0
HT_CTL_RXN0
HT_CTL_RXP0
HT_CLK_RXN0
HT_CLK_RXP0
HT_CLK_TXN0
HT_CLK_TXP0
(SYM 5 OF 7)
INTERFACE
HT
HT_LDTREQ*
HT_LDTSTOP*
HT_RESET*
HT_PWROK
HT_CAD_RXN7
HT_CAD_RXP7
HT_CAD_RXN6
HT_CAD_RXN1
HT_CAD_RXN5
HT_CAD_RXP5
HT_CAD_RXP6
HT_CAD_RXN4
HT_CAD_RXP4
HT_CAD_RXN3
HT_CAD_RXP3
HT_CAD_RXN2
HT_CAD_RXP2
HT_CLK
HT_CAD_RXP0
HT_CAD_RXN0
HT_CAD_RXP1
HT_PVTREF1
HT_PVTREF0
HT_CAD_TXP7
HT_CAD_TXN7
HT_CAD_TXN6
HT_CAD_TXN1
HT_CAD_TXN5
HT_CAD_TXN4
HT_CAD_TXP2
HT_CAD_TXP3
HT_CAD_TXP4
HT_CAD_TXN2
HT_CAD_TXN3
HT_CAD_TXP5
HT_CAD_TXP6
HT_CAD_TXN0
HT_CAD_TXP1
HT_CAD_TXP0
HT_CLK_AVSS
AVDD
HT_CLK VDD_HT VDD_HT
2_5 1_2
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
MASTER: GILA
U3LITE HT
NET_SPACING_TYPE
DIFFERENTIAL_PAIR
ELECTRICAL_CONSTRAINT_SET
8 MIL SPACING TO ANYTHING ELSE
4 MIL SPACING IN GROUP
HT_2V5
10 MIL SPACING TO ANYTHING ELSE
5 MIL SPACING FOR DIFF PAIR
HT_1V2
LENGTH TOLERENCE DOES NOT NEED TO BE SPECIFIED
MATCHED GROUP CONSTRAINT IS TIGHT ENOUGH
2
1
C6006
402
0.1UF
20%
10V
CERM
2
1
C6005
CERM
10V
20%
0.1UF
402
2
1
C6004
402
0.1UF
20%
10V
CERM
2
1
C6002
402
0.1UF
20%
10V
CERM
2
1
C6001
CERM
10V
20%
0.1UF
402
2
1
C6000
0.1UF
CERM
402
20%
10V
2
1
C6007
CERM
10V
20%
0.1UF
402
2
1
C6008
CERM
10V
20%
0.1UF
402
2
1
C6012
0.1UF
20%
10V
CERM
402
21
R6000
2.2
603
MF
1/16W
5%
2
1
C6013
402
1UF
CERM
10%
6.3V
2
1
C6011
402
0.1UF
20%
10V
CERM
2
1
C6010
10V
20%
402
CERM
0.1UF
2
1
R6001
402
MF
1/16W
1%
200
2
1
R6002
402
MF
1/16W
5%
1K
2
1
R6003
1K
5%
1/16W
MF
402
2
1
R6004
402
MF
1/16W
5%
1K
2
1
R6005
402
MF
1/16W
5%
1K
I46
I47
I48
I49
I50
I51
I52
I53
I54
I55
I56
I57
I58
I59
I60
I61
I62
I63
I64
I65
I66
I67
I68
I69
I70
I71
I72
I73
I74
I75
I76
I77
I78
I79
I80
I81
I82
I83
I84
I85
I86
I87
I88
I89
G6
J10
L9
N10
N6N2R9T8T4
G9
F9
L8
L7H8
H7
L6
L5
V2
V1
R7
R8
N1
P1
G8
F8
H9
M7
M5
P6
P8
R5
U4
U6
U8
M8
M6
P5
P7
R6
U3
U5
U7
U1
R1
R3
P2
M2
M4
L3
L1
U2
T1
R2
P3
M1
M3
L4
L2
U3
OMIT
U3LITE
V1.0-300MM
PBGA
03
60
103
051-6532
HT_NB_TO_SB
HT_NB_TO_SB_CLK
HT_NB_TO_SB_CLK_P
HT_NB_TO_SB
HT_NB_TO_SB_CTL
HT_NB_TO_SB_CTL_N
HT_NB_TO_SB HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB_CAD1
HT_NB_TO_SB_CAD_P<1>
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB_CAD4
HT_NB_TO_SB_CAD_P<4>
HT_NB_TO_SB
HT_SB_TO_NB
HT_SB_TO_NB_CLK
HT_SB_TO_NB_CLK_N
HT_SB_TO_NB
HT_SB_TO_NB_CAD0
HT_SB_TO_NB_CAD_P<0>
HT_SB_TO_NB HT_SB_TO_NB
HT_SB_TO_NB_CAD_N<3>
HT_SB_TO_NB_CAD3
HT_SB_TO_NB HT_SB_TO_NB
HT_NB_TO_SB
HT_NB_TO_SB_CAD0
HT_NB_TO_SB_CAD_N<0>
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB_CLK
HT_NB_TO_SB_CLK_N
HT_NB_TO_SB
HT_NB_TO_SB_CTL
HT_NB_TO_SB_CTL_P
HT_NB_TO_SB HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB_CAD0
HT_NB_TO_SB_CAD_P<0>
HT_NB_TO_SB
HT_CTL
HT_RESET_L
HT_2V5
HT_CTL
HT_LDTREQ_L
HT_2V5
HT_SB_TO_NB_CAD0
HT_SB_TO_NB_CAD_N<0>
HT_SB_TO_NB HT_SB_TO_NB
HT_SB_TO_NB_CTL_N
HT_SB_TO_NB_CTL
HT_SB_TO_NB HT_SB_TO_NB
HT_NB_TO_SB
HT_NB_TO_SB_CAD7
HT_NB_TO_SB_CAD_N<7>
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB_CAD7
HT_NB_TO_SB_CAD_P<7>
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB_CAD6
HT_NB_TO_SB_CAD_N<6>
HT_NB_TO_SB
HT_SB_TO_NB_CAD_P<6>
HT_SB_TO_NB_CAD6
HT_SB_TO_NB HT_SB_TO_NB
HT_NB_TO_SB
HT_NB_TO_SB_CAD5
HT_NB_TO_SB_CAD_N<5>
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB_CAD3
HT_NB_TO_SB_CAD_P<3>
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB_CAD2
HT_NB_TO_SB_CAD_N<2>
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB_CAD2
HT_NB_TO_SB_CAD_P<2>
HT_NB_TO_SB
HT_NB_TO_SB_CAD_N<1>
HT_NB_TO_SB
HT_NB_TO_SB_CAD1
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB_CAD5
HT_NB_TO_SB_CAD_P<5>
HT_NB_TO_SB
HT_SB_TO_NB
HT_SB_TO_NB_CLK
HT_SB_TO_NB_CLK_P
HT_SB_TO_NB
HT_SB_TO_NB_CAD_P<2>
HT_SB_TO_NB_CAD2
HT_SB_TO_NB HT_SB_TO_NB
HT_SB_TO_NB_CAD_P<1>
HT_SB_TO_NB_CAD1
HT_SB_TO_NB HT_SB_TO_NB
HT_PWROK
HT_2V5
HT_PWROK
HT_SB_TO_NB_CAD_P<7>
HT_SB_TO_NB_CAD7
HT_SB_TO_NB HT_SB_TO_NB
HT_SB_TO_NB_CAD_N<7>
HT_SB_TO_NB_CAD7
HT_SB_TO_NB HT_SB_TO_NB
HT_SB_TO_NB_CTL_P
HT_SB_TO_NB_CTL
HT_SB_TO_NB HT_SB_TO_NB
HT_NB_TO_SB
HT_NB_TO_SB_CAD6
HT_NB_TO_SB_CAD_P<6>
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB_CAD3
HT_NB_TO_SB_CAD_N<3>
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB_CAD4
HT_NB_TO_SB_CAD_N<4>
HT_NB_TO_SB
HT_SB_TO_NB
HT_SB_TO_NB_CAD_N<1>
HT_SB_TO_NB_CAD1
HT_SB_TO_NB
HT_SB_TO_NB_CAD_P<4>
HT_SB_TO_NB_CAD4
HT_SB_TO_NB HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB_CAD_P<5>
HT_SB_TO_NB_CAD5
HT_SB_TO_NB
HT_SB_TO_NB_CAD_N<4>
HT_SB_TO_NB_CAD4
HT_SB_TO_NB HT_SB_TO_NB
HT_SB_TO_NB_CAD_N<5>
HT_SB_TO_NB_CAD5
HT_SB_TO_NB HT_SB_TO_NB
HT_SB_TO_NB_CAD_N<6>
HT_SB_TO_NB_CAD6
HT_SB_TO_NB HT_SB_TO_NB
HT_CTL HT_2V5
HT_LDTSTOP_L
PP1V2_HT
HT_SB_TO_NB_CAD_N<1>
HT_SB_TO_NB_CAD_P<4>
PP1V2_HT
PP2V5_HT
HT_LDTREQ_L
HT_RESET_L
HT_LDTSTOP_L
HT_PWROK
HT_SB_TO_NB_CAD_N<7>
HT_SB_TO_NB_CAD_P<7>
HT_SB_TO_NB_CAD_N<6>
HT_SB_TO_NB_CAD_N<4>
HT_SB_TO_NB_CAD_P<5>
HT_SB_TO_NB_CAD_N<5>
HT_SB_TO_NB_CAD_P<6>
HT_SB_TO_NB_CAD_P<2>
HT_SB_TO_NB_CAD_N<2>
HT_SB_TO_NB_CAD_P<3>
HT_SB_TO_NB_CAD_N<3>
HT_SB_TO_NB_CAD_P<0>
HT_SB_TO_NB_CAD_N<0>
HT_SB_TO_NB_CAD_P<1>
HT_CLK66M_NB
HT_NB_PVTREF1
HT_NB_PVTREF0
HT_NB_TO_SB_CAD_N<6>
HT_NB_TO_SB_CAD_N<7>
HT_NB_TO_SB_CAD_P<7>
HT_NB_TO_SB_CAD_P<6>
HT_NB_TO_SB_CAD_N<5>
HT_NB_TO_SB_CAD_P<5>
HT_NB_TO_SB_CAD_N<4>
HT_NB_TO_SB_CAD_P<4>
HT_NB_TO_SB_CAD_N<1>
HT_NB_TO_SB_CAD_P<2>
HT_NB_TO_SB_CAD_N<2>
HT_NB_TO_SB_CAD_N<3>
HT_NB_TO_SB_CAD_P<3>
HT_NB_TO_SB_CAD_P<1>
HT_NB_TO_SB_CAD_N<0>
HT_NB_TO_SB_CAD_P<0>
HT_NB_TO_SB_CLK_P
HT_NB_TO_SB_CLK_N
HT_SB_TO_NB_CLK_P
HT_SB_TO_NB_CLK_N
HT_SB_TO_NB_CTL_P
HT_SB_TO_NB_CTL_N
HT_NB_TO_SB_CTL_P
HT_NB_TO_SB_CTL_N
PP2V5_HT
PP2V5_HT
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
PP1V5_PWRON_HT_NB_AVDD
VOLTAGE=1.5V
PP1V5_PWRON_NB_AVDD
HT_SB_TO_NB_CAD_P<3>
HT_SB_TO_NB_CAD3
HT_SB_TO_NB HT_SB_TO_NB
HT_SB_TO_NB_CAD_N<2>
HT_SB_TO_NB_CAD2
HT_SB_TO_NB HT_SB_TO_NB
36
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44
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22
44
44
22
43
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5
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5
5
43
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25
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5
5
43
43
Preliminary
Page 44
SEL_HT00_H
HT_S100M66M
HT_CTLOUT_N
HT_CTLOUT_P
HT_CTLIN_N
HT_CTLIN_P
HT_LDTSTOP_L
HT_RESET_L
HT_LDTREQ_L
HT_RXVDD
HT
HT_PLL
VDDPDVDDAVDD
HT_CADIN_7_P
HT_CADIN_7_N
HT_PWROK_H
HT_CADIN_6_N
HT_CADIN_3_P
HT_CADIN_3_N
HT_CADIN_4_P
HT_CADIN_4_N
HT_CADIN_5_P
HT_CADIN_5_N
HT_CADIN_6_P
HT_CADIN_2_N
HT_CADIN_2_P
HT_CADIN_1_N
HT_CADIN_1_P
HT_CLKIN_N
HT_CLKIN_P
HT_CADIN_0_P
HT_CADIN_0_N
AGND DGND
HT_PLL
HT_RXGND
HT_CADOUT_7_P
HT_CADOUT_7_N
HT_TXGND
HT_R100N
HT_R100P
HT_CADOUT_6_N
HT_CADOUT_6_P
HT_CADOUT_5_N
HT_CADOUT_5_P
HT_CADOUT_4_N
HT_CADOUT_4_P
HT_CADOUT_3_N
HT_CADOUT_3_P
HT_CADOUT_2_N
HT_CADOUT_2_P
HT_CADOUT_1_N
HT_CADOUT_1_P
HT_CADOUT_0_N
HT_CADOUT_0_P
HT_CLKOUT_N
HT_CLKOUT_P
(3 OF 8)
HT_TXVDD
HT_REFCLK
HYPERTRANSPORT
DRAWING
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
0 = 66MHz
HT RefClk
1 = 100MHz
HT I/F Speed
1 = 100MHz
0 = 200MHz
1.0V pk-pk
Master: Fizzy
Shasta HyperTransport
- _PP1V2_PWRON_HT
Signal aliases required by this page:
AC coupled
(NONE)
- _PP2V5_PWRON_HT
ELECTRICAL_CONSTRAINT_SET
NET_SPACING_TYPE
Page Notes
Power aliases required by this page:
BOM options provided by this page:
DIFFERENTIAL_PAIR
- SB_HT_200M
Stuffs resistor to select 200MHz HT I/F.
2
1
C6231
0.1uF
402
CERM
10V
20%
2
1
C6230
20%
10V
CERM
402
0.1uF
2
1
C6220
20%
10V
CERM
402
0.1uF
2
1
R6251
1K
402
MF
1/16W
5%
SB_HT_200M
B19
V6
G11
B9
B12
G10
A9
A12
D8
G13
B17
B15
G12
A17
A15
C18
C8
E10
F10
E16
B6A6C7C6
E17 A19
C13
D13
F13
E13
B10
A10
D15
C15
A13
B13
E12
F12
C12
D12
A11
B11
D11
C11
E11
F11
B8
A8
D10
C10
B14
A14
E14
F14
D14
C14
B16
A16
D16
C16
F15
E15
B18
A18
D17
C17
U2300
OMIT
SHASTA
BGA
V1.0
21
C6255
20%
10V
CERM
402
0.1uF
2
1
R6255
402
1/16W
MF
1%
332
21
R6200
5%
1/10W
FF
805
3.3
21
R6210
5%
1/10W
FF
805
3.3
2
1
R6254
5%
1/16W
MF
402
10K
2
1
C6200
10uF
CERM
6.3V
20%
1206
2
1
C6201
CERM
402
10%
1uF
6.3V
2
1
C6211
10%
CERM
402
1uF
6.3V
2
1
C6210
20%
6.3V
CERM
1206
10uF
2
1
C6250
5%
50V
CERM
402
47pF
2
1
C6251
5%
50V
CERM
402
47pF
21
R6250
1/16W
MF
402
1%
82.5
2
1
R6252
NO STUFF
4.7K
402
MF
1/16W
5%
2
1
R6253
4.7K
402
5%
1/16W
MF
2
1
C6240
20%
10V
CERM
402
0.1uF
2
1
C6241
10V
402
0.1uF
20%
CERM
2
1
C6242
402
CERM
10V
20%
0.1uF
2
1
C6232
20%
10V
CERM
402
0.1uF
TITLE=FIZZY
ABBREV=DRAWING
62
103
03
051-6532
_PP1V2_PWRON_HT
MIN_NECK_WIDTH=15 mil
PP1V2_PWRON_HT_PLLAVDD
VOLTAGE=1.2V
MIN_LINE_WIDTH=20 mil
PP1V2_PWRON_HT_PLLDVDD
VOLTAGE=1.2V
MIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=15 mil
HT_CLK66M_SB_C
HT_NB_TO_SB_CAD_P<0>
HT_NB_TO_SB_CAD_N<0>
HT_NB_TO_SB_CTL_N
HT_SB_TO_NB_CAD_P<3>
HT_RESET_L
15 MIL SPACING
HT_CLK66M_SB_C
HT_SB_TO_NB_CTL_PHT_NB_TO_SB_CTL_P
HT_SB_TO_NB_CAD_P<6>
HT_SB_TO_NB_CAD_N<5>
HT_SB_TO_NB_CAD_P<7>
HT_SB_TO_NB_CAD_N<6>HT_NB_TO_SB_CAD_N<6>
HT_NB_TO_SB_CAD_N<7>
HT_NB_TO_SB_CAD_P<6>
HT_NB_TO_SB_CAD_N<5>
HT_NB_TO_SB_CAD_P<5>
HT_NB_TO_SB_CAD_N<4>
HT_NB_TO_SB_CAD_P<4>
HT_NB_TO_SB_CAD_P<3>
HT_NB_TO_SB_CAD_N<3>
HT_NB_TO_SB_CAD_N<1>
HT_NB_TO_SB_CAD_N<2>
HT_NB_TO_SB_CAD_P<2>
HT_NB_TO_SB_CLK_N
HT_NB_TO_SB_CAD_P<1>
HT_NB_TO_SB_CLK_P
HT_SB_TO_NB_CAD_P<5>
HT_SB_TO_NB_CAD_P<4>
HT_SB_TO_NB_CAD_N<4>
HT_SB_TO_NB_CAD_N<3>
HT_SB_TO_NB_CAD_N<1>
HT_SB_TO_NB_CAD_P<2>
HT_SB_TO_NB_CAD_N<2>
HT_SB_TO_NB_CAD_P<1>
HT_SB_TO_NB_CAD_N<0>
HT_SB_TO_NB_CLK_N
HT_SB_TO_NB_CAD_P<0>
HT_SB_TO_NB_CLK_P
HT_CLK66M_SB
SB_HT_R100_N
SB_HT_R100_P
_PP1V2_PWRON_HT
_PP2V5_PWRON_HT
HT_NB_TO_SB_CAD_P<7>
_PP1V2_PWRON_HT
HT_LDTREQ_L
HT_SB_TO_NB_CTL_N
HT_SB_TO_NB_CAD_N<7>
HT_LDTSTOP_L
HT_PWROK
SB_SELHT100
_PP1V2_PWRON_HT
SB_HT_S100M66M
LAST_MODIFIED=Mon Feb 23 19:06:27 2004
44
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5
Preliminary
Page 45
PCI
(4 OF 8)
PCI1CLK_H
PCIBR_CLK_H
PCI1PAR_H
PCI1AD_31_H
PCI1AD_30_H
PCI1AD_29_H
PCI1AD_28_H
PCI1AD_27_H
PCI1AD_26_H
PCI1AD_19_H
PCI1AD_18_H
PCI1AD_16_H
PCI1AD_17_H
PCI1AD_24_H
PCI1AD_25_H
PCI1AD_20_H
PCI1AD_21_H
PCI1AD_22_H
PCI1AD_23_H
PCI1AD_15_H
PCI1AD_8_H
PCI1AD_9_H
PCI1AD_10_H
PCI1AD_11_H
PCI1AD_12_H
PCI1AD_13_H
PCI1AD_14_H
PCI1AD_7_H
PCI1AD_6_H
PCI1AD_5_H
PCI1AD_4_H
PCI1AD_0_H
PCI1AD_1_H
PCI1AD_2_H
PCI1AD_3_H
PCIVDDP
VDDOPC
PCI1GNT_0_L
PCI1REQ_0_L
PCI1REQ_1_L
PCI1GNT_1_L
PCI1REQ_2_L
PCI1GNT_2_L
ROMCS_L
ROMOE_L
ROMRW_L
PCI1RST_L
PCI1STOP_L
PCI1TRDY_L
PCI1IRDY_L
PCI1FRAME_L
PCI1DEVSEL_L
PCI1C_BE_3_L
PCI1C_BE_2_L
PCI1C_BE_1_L
PCI1C_BE_0_L
DRAWING
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
"Slot G" - AD27
"Slot A" - AD17
"Slot D" - AD20
- _PP3V3_SB_PCI (can be _PP3V3_PCI)
Shasta PCI Interface
ELECTRICAL_CONSTRAINT_SET
DIFFERENTIAL_PAIR
- _PP3V3_PCI
NET_SPACING_TYPE
Master: Link
Power aliases required by this page:
Page Notes
- _PP2V5_PWRON_SB
AD11 - PCI2 (0x106B/0x0055)
AD11 - PCI1 (0x106B/0x0054)
BOM options provided by this page:
(NONE)
(NONE)
Signal aliases required by this page:
AD23 - KeyLargo (0x106B/0x004F, PCI1)
AD31 - Ethernet (0x106B/0x0051, PCI0)
AD11 - PCI0 (0x106B/0x0053)
PCI Devices implemented on this page:
AD28 - SATA 150 (0x1166/0x0240, PCI0 or 2)
AD29 - UATA 133 (0x106B/0x0050, PCI0 or 2)
AD30 - FireWire (0x106B/0x0052, PCI0 or 2)
- _PP3V3_PWRON_SB
Shasta drives PCI RESET, but its output
it is ANDed with a reset from the SMU.
may not be valid during power-up, so
2
1
C7409
0.1uF
402
CERM
10V
20%
2
1
C7408
20%
10V
CERM
402
0.1uF
2
1
C7407
0.1uF
402
CERM
10V
20%
2
1
C7406
20%
10V
CERM
402
0.1uF
2
1
C7405
CERM
20%
0.1uF
402
10V
2
1
C7404
402
0.1uF
20%
10V
CERM
2
1
C7403
20%
10V
CERM
402
0.1uF
2
1
C7402
0.1uF
402
CERM
10V
20%
2
1
C7401
0.1uF
402
CERM
10V
20%
2
1
C7400
20%
10V
CERM
402
0.1uF
2
1
C7423
0.1uF
CERM
10V
20%
402
2
1
C7422
0.1uF
402
CERM
10V
20%
2
1
C7421
0.1uF
20%
10V
CERM
402
2
1
C7420
20%
0.1uF
CERM
10V
402
63
RP7402
4.7K
1/16W
5%
SM1
54
RP7402
SM1
5%
1/16W
4.7K
72
RP7402
4.7K
1/16W
5%
SM1
81
RP7402
4.7K
5%
1/16W
SM1
72
RP7400
4.7K
5%
1/16W
SM1
81
RP7400
4.7K
1/16W
5%
SM1
54
RP7400
4.7K
1/16W
5%
SM1
63
RP7400
4.7K
1/16W
5%
SM1
54
RP7401
4.7K
5%
1/16W
SM1
63
RP7401
4.7K
5%
1/16W
SM1
27
RP7401
4.7K
1/16W
5%
SM1
V19
U21
R20
N21
M16
J21
H16
E21
B22
AA22
Y10
AA9
AB8
U20
N20
J18
B20
AB9
P19
P17
U18
V17
AB20
AB18
N17
R21
V18
AB19
AA18
T21
T22
V20
V22
P16
L19
U19
P22
M20
N16
M21
L20
M18
M22
T17
AA21
L22
T16
W20
Y21
T18
T19
R18
Y22
W21
R17
R16
K19
T20
P18
V21
P20
R22
P21
N19
M19
N18
M17
L18
U2300
OMIT
SHASTA
V1.0
BGA
2
1
C7410
805
20%
CERM
10uF
6.3V
NO STUFF
2
1
C7411
805
6.3V
10uF
CERM
20%
NO STUFF
5
4
1
2
3
U7450
MC74VHC1G08
SOT23-5
2
1
C7450
402
20%
10V
CERM
0.1uF
2
1
R7450
4.7K
402
MF
1/16W
5%
2
1
R7455
4.7K
402
MF
1/16W
5%
TITLE=LINK
ABBREV=DRAWING
74 103
03
051-6532
PCI_CTL
PCI_DEVSEL_L
PCI_PAR
PCI
PCI
PCI_CBE_L<3..0>
PCI_AD<16..0>
PCI_AD
PCI_AD<20>
PCI_AD20
PCI_AD
PCI_AD<19..18>
SYS_WARM_RESET_L
_PP3V3_SB_PCI
PCI_TRDY_L
PCI_CTL
PCI_CTL
PCI_STOP_L
PCI_AD<17>
PCI_AD17
PCI_AD
PCI_AD<26..24>
PCI_FRAME_L
PCI_CTL
PCI_AD<21>
PCI_AD21
PCI_AD<27>
PCI_AD27
PCI_AD<31..28>
PCI_AD
PCI_AD<23>
PCI_AD23
PCI_CTL
PCI_IRDY_L
PCI_SLOTD_REQ_L
PCI_SLOTD_GNT_L
PCI_SLOTG_REQ_L
PCI_SLOTG_GNT_L
PCI_SLOTA_GNT_L
PCI_SLOTA_REQ_L
PCI_TRDY_L
PCI_FRAME_L
PCI_STOP_L
PCI_IRDY_L
PCI_DEVSEL_L
_PP3V3_PCI
_PP3V3_PCI
PCI_AD<22>
PCI_AD22
PCI_CLK33M_SB_EXT
PCI_CLK66M_SB_INT
PCI_SLOTA_GNT_L
PCI_SLOTA_REQ_L
PCI_SLOTG_REQ_L
PCI_SLOTG_GNT_L
PCI_SLOTD_REQ_L
PCI_SLOTD_GNT_L
ROM_CS_L
ROM_OE_L
ROM_WE_L
_PP2V5_PWRON_SB
PCI_SB_TRDY_L
PCI_SB_STOP_L
PCI_SB_IRDY_L
PCI_SB_PAR
PCI_SB_FRAME_L
PCI_SB_CBE_L<3>
PCI_SB_AD<31>
PCI_SB_CBE_L<0>
PCI_SB_AD<28>
PCI_SB_CBE_L<2>
PCI_SB_AD<29>
PCI_SB_CBE_L<1>
PCI_SB_DEVSEL_L
PCI_SB_AD<30>
PCI_SB_AD<21>
PCI_SB_AD<19>
PCI_SB_AD<18>
PCI_SB_AD<20>
PCI_SB_AD<22>
PCI_SB_AD<23>
PCI_SB_AD<24>
PCI_SB_AD<25>
PCI_SB_AD<26>
PCI_SB_AD<27>
PCI_SB_AD<10>
PCI_SB_AD<7>
PCI_SB_AD<9>
PCI_SB_AD<8>
PCI_SB_AD<11>
PCI_SB_AD<12>
PCI_SB_AD<14>
PCI_SB_AD<17>
PCI_SB_AD<15>
PCI_SB_AD<16>
PCI_SB_AD<13>
PCI_SB_AD<0>
PCI_SB_AD<6>
PCI_SB_AD<1>
PCI_SB_AD<2>
PCI_SB_AD<4>
PCI_SB_AD<3>
PCI_SB_AD<5>
_PP3V3_PWRON_SB
PCI_RESET_L
SB_PCI_RESET_L
LAST_MODIFIED=Mon Feb 23 19:06:40 2004
49
49
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
48
48
49
62
62
49
49
49
49
49
49
49
49
62
49
49
62
49
49
49
49
49
49
47
47
62
48
49
49
48
48
48
48
48
48
48
48
48
49
48
48
49
48
48
48
48
48
48
46
46
49
56
23
48
47
48
48
47
47
47
23
47
47
47
47
47
48
47
47
48
47
47
47
47
47
47
47
47
45
45
48
47
47
47
47
47
23
21
47
45
47
47
46
46
46
22
45
45
46
46
45
47
46
46
47
45
48
48
45
45
45
45
45
45
45
23
23
47
25
45
45
48
48
46
46
46
21
62
18
46
6
6
6
6
6
6
5
5
6
6
6
6
6
6
6
6
6
6
45
45
45
45
6
6
6
6
6
6
6
5
5
6
5
25
6
6
45
45
45
45
6
6
6
5
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
48
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
5
5
Preliminary
Page 46
A0
A1
A6
A2
A3
A4
A5
A9
A8
A7
A10
A11
A12
A13
A14
A15
A16
A20
A17
A18
A19
CE
OE
WE
WP
PWD
GND
DQ0
DQ1
DQ6
DQ5
DQ2
DQ3
DQ4
DQ7
VPP VCC
FEPR-1MX8
DRAWING
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Allows ROM override module
to intercept ROM chip select
BootROM
- _PP3V3_PCI
Power aliases required by this page:
Page Notes
(NONE)
Signal aliases required by this page:
(NONE)
part number. Must use a TABLE_x_ITEM
symbol to declare U7500 part number.
NOTE: This page does not specify a BootROM
BOM options provided by this page:
Master: Fizzy
12
9
11 3130
10
24
3923
35
34
33
32
28
27
26
25
22
7
8
14
15
16
17
18
38
19
37
13
40
1
2
3
4
5
6
36
20
21
U7500
TSOP
OMIT
90.0ns
21
R7502
1/16W
1K
5%
MF
402
2
1
R7501
402
MF
1/16W
5%
10K
2
1
R7500
5%
10K
1/16W
MF
402
2
1
C7500
805
20%
10V
CERM
2.2uF
2
1
C7501
402
CERM
10V
20%
0.1uF
2
1
C7502
0.1uF
20%
10V
CERM
402
ABBREV=DRAWING
TITLE=FIZZY
03
051-6532
103
75
_PP3V3_PCI
_PP3V3_PCI
ROM_CS_L
PCI_RESET_L
ROM_WP_L
ROM_WE_L
ROM_OE_L
PCI_AD<0>
PCI_AD<1>
PCI_AD<10>
PCI_AD<11>
PCI_AD<12>
PCI_AD<13>
PCI_AD<14>
PCI_AD<15>
PCI_AD<16>
PCI_AD<17>
PCI_AD<18>
PCI_AD<19>
PCI_AD<2>
PCI_AD<20>
PCI_AD<3>
PCI_AD<4>
PCI_AD<5>
PCI_AD<6>
PCI_AD<7>
PCI_AD<8>
PCI_AD<9>
PCI_AD<24>
PCI_AD<25>
PCI_AD<26>
PCI_AD<27>
PCI_AD<28>
PCI_AD<29>
PCI_AD<30>
PCI_AD<31>
ROM_ONBOARD_CS_L
LAST_MODIFIED=Mon Feb 23 19:06:47 2004
49
49
48
48
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
62
47
47
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
46
46
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
45
45
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
23
23
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
47
5
5
6
5
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
Preliminary
Page 47
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
DRAWING
- _PCI_CLK33M_AIRPORT (33MHz PCI clock)
- _PP3V3_PCI
(NONE)
NOTE: This AirPort implementation does
AD17 (Slot "A") - AirPort (0x????/0x????)
Page Notes
Power aliases required by this page:
not support PME#.
PCI Devices implemented on this page:
Signal aliases required by this page:
BOM options provided by this page:
ELECTRICAL_CONSTRAINT_SET
NET_SPACING_TYPE
DIFFERENTIAL_PAIR
AirPort Extreme
NC
NC
RESERVED FOR USB_DP AND USB_DN
NC
NC
NC
NC
516S0179
2
1
R7601
402
MF
1/16W
5%
10K
21
R7600
22
1/16W
MF
5%
402
9
82
81
80
8
79
7877
7675
7473
7271
70
7
69
6867
6665
6463
6261
60
6
59
5857
5655
5453
5251
50
5
49
4847
4645
4443
4241
40
4
39
3837
3635
3433
3231
30
3
29
2827
2625
2423
2221
20
2
19
1817
1615
1413
1211
10
1
J7600
M-ST-SM
CPB-7280-1210
CRITICAL
051-6532
03
76 103
TITLE=FIZZY
ABBREV=DRAWING
PCI_SLOTA_REQ_L
PCI_RESET_L
TP_AIRPORT_RF_DISABLE
_PP3V3_PCI
PCI_AD<31>
PCI_AD<29>
PCI_AD<27>
PCI_AD<25>
PCI_CBE_L<3>
PCI_AD<21>
PCI_AD<19>
PCI_AD<17>
PCI_CBE_L<2>
PCI_IRDY_L
AIRPORT_CLKRUN_L_PD
PCI_CBE_L<1>
PCI_AD<14>
PCI_AD<12>
PCI_AD<10>
ROM_WE_L
PCI_AD<8>
PCI_AD<7>
PCI_AD<5>
ROM_ONBOARD_CS_L
PCI_AD<3>
PCI_AD<1>
ROM_CS_L
PCI_AD<23>
PCI_AD<11>
_PCI_CLK33M_AIRPORT
PCI_SLOTA_GNT_L
TP_AIRPORT_PME_L
PCI_SLOTA_INT_L
PCI_AD<30>
PCI_AD<28>
PCI_AD<26>
PCI_AD<24>
PCI_SLOTA_IDSEL
PCI_AD<22>
PCI_AD<20>
PCI_PAR
PCI_AD<18>
PCI_AD<16>
PCI_FRAME_L
PCI_TRDY_L
PCI_AD<15>
PCI_AD<13>
PCI_AD<9>
PCI_CBE_L<0>
ROM_OE_L
PCI_AD<6>
PCI_AD<4>
PCI_AD<2>
PCI_AD<0>
PCI_AD<17>
PCI_CLK_AIRPORT
_PCI_CLK33M_AIRPORT
CLOCKS
PCI_DEVSEL_L
PCI_STOP_L
LAST_MODIFIED=Mon Feb 23 19:06:53 2004
62
62
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48
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62
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49
62
49
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49
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62
49
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62
49
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49
49
48
62
62
48
46
48
48
48
48
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48
48
48
48
48
48
48
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48
48
48
48
48
49
48
49
48
48
49
49
48
48
48
49
48
48
48
48
47
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45
46
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46
48
48
46
46
48
48
48
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46
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48
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46
46
46
48
46
48
46
46
48
48
46
46
46
48
46
46
46
46
46
46
48
48
45
45
23
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
46
45
45
45
45
45
47
45
23
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
47
45
45
6
5
6
5
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
5
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
5
6
6
Preliminary
Page 48
AD1
SRMOD
NANDTEST
NTEST1
SRDTA
SRCLK
TEST
TEB
AMC
SMC
LEGC
PME
PCLK
INTC
INTB
INTA
VBBRST
SMI
CRUN
SERR
REQ
STOP
TRDY
IRDY
FRAME
IDSEL
DEVSEL
GNT
PERR
PAR
CBE3
CBE2
CBE1
CBE0
AD31
AD30
AD29
AD28
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD25
AD26
AD27
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD15
AD16
AD17
AD7
AD6
AD0
AD2
AD5
AD4
VCCRST
AD3
VDD_PCI
DRAWING
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Master: Fizzy
facilitate NAND-tree testing
(PCI_AD<27>)
RP7702 & RP7703 required to
OD
OD
OD
OD
OD
OD
IPD
IPD
IPD
IPD
IPD
IPD
USB 2.0 PCI Interface
(PCI RESET)
(CHIP RESET)
DIFFERENTIAL_PAIR
NET_SPACING_TYPE
Page Notes
BOM options provided by this page:
Power aliases required by this page:
Signal aliases required by this page:
PCI Devices implemented on this page:
AD27 (Slot "G") - USB2 (0x1033/0x0035)
NOTE: This USB2 implementation supports
- _PCI_CLK33M_USB2 (33MHz PCI clock)
- _PPVIO_PCI (to 3.3V or 5V)
(NONE)
D3cold.
ELECTRICAL_CONSTRAINT_SET
2
1
C7703
0.1uF
402
CERM
10V
20%
2
1
R7716
5%
402
MF
1/16W
10K
72
RP7703
5%
1/16W
SM1
47
63
RP7702
47
SM1
1/16W
5%
72
RP7702
5%
1/16W
SM1
47
54
RP7703
47
5%
SM1
1/16W
63
RP7703
1/16W
5%
SM1
47
54
RP7702
47
SM1
1/16W
5%
2
1
R7714
1/16W
402
MF
22
5%
C8M4H3
C9
B8
G1
L8
N7
G3
P9
N9
M9
L6
M7
H1
C6
D9
H2
A8
J4
M8
M10
L7
F4
A7
B7
C7
B3
D6
F3
G2
N6
C3
F1
J3
M2
P7
L1
L2
M1
N3
M3
N4
A6
B6
P4
C5
A5
C4
B5
A4
B4
C1
C2
D2
D1
N5
D3
E1
E3
F2
J1
J2
K3
K1
L3
K2
P5
M5
U7700
FBGA
NEC_uPD720101_USB2
CRITICAL
2
1
R7713
1/16W
MF
402
5%
10K
8
1
RP7703
1/16W
SM1
5%
47
2
1
R7715
4.7K
402
MF
1/16W
5%
TITLE=FIZZY
ABBREV=DRAWING
77
103
03
051-6532
CLOCKS
PCI_CLK_USB2
_PCI_CLK33M_USB2
NEC_PME_L
TP_NEC_SMI_L
NEC_SERR_L_PU
TP_NEC_AMC
PCI_AD<0>
TP_NEC_SMC
TP_NEC_TEB
TP_NEC_SRDATA
PCI_AD<12>
NEC_INTC_L
NEC_INTA_L
NEC_VBBRST_L
NEC_VCCRST_L
_PP3V3_PCI
PCI_SLOTG_IDSEL
PCI_AD<4>
PCI_AD<3>
PCI_AD<10>
PCI_AD<13>
PCI_AD<14>
PCI_AD<17>
PCI_AD<16>
PCI_AD<15>
PCI_AD<18>
PCI_AD<19>
PCI_AD<20>
PCI_AD<22>
PCI_AD<21>
PCI_AD<23>
PCI_AD<24>
PCI_AD<25>
PCI_AD<26>
PCI_AD<29>
PCI_AD<28>
PCI_AD<30>
PCI_AD<31>
PCI_CBE_L<3>
PCI_CBE_L<1>
PCI_CBE_L<2>
PCI_PAR
PCI_FRAME_L
PCI_IRDY_L
PCI_TRDY_L
PCI_STOP_L
PCI_DEVSEL_L
PCI_SLOTG_REQ_L
PCI_SLOTG_GNT_L
_PCI_CLK33M_USB2
NEC_CRUN_L_PD
NEC_LEGC_PD
TP_NEC_NTEST1
TP_NEC_TEST
TP_NEC_SRCLK
TP_NEC_NANDTEST
TP_NEC_SRMOD
NEC_INTB_L
SYS_WARM_RESET_L
PCI_RESET_L
SYS_PME_L
NEC_PERR_L_PU
PCI_AD<11>
PCI_SLOTG_INT_L
PCI_AD<1>
PCI_AD<2>
PCI_AD<9>
PCI_AD<8>
PCI_AD<6>
PCI_AD<5>
PCI_AD<7>
_PPVIO_PCI_USB2
PCI_CBE_L<0>
PCI_AD<27>
PCI_SB_AD<27>
LAST_MODIFIED=Mon Feb 23 19:07:00 2004
62
62
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62
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62
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6
5
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13
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45
Preliminary
Page 49
C/BE3*
C/BE2*
C/BE1*
C/BE0*
VR_EN*
VR_PORT
VCCCB
VCCP
GND
VCC
GRST
MFUNC4
MFUNC5
MFUNC6
MFUNC3
MFUNC0
SUSPEND
MFUNC1
MFUNC2
PCLK
SPKROUT
GNT
TRDY
STOP
FRAME
PRST
REQ
DEVSEL
PERR
IDSEL
SERR
IRDY
AD31
PAR
AD30
AD29
AD28
AD27
AD20
AD21
AD18
AD19
AD26
AD25
AD24
AD23
AD22
AD17
AD10
AD11
AD9
AD8
AD16
AD15
AD14
AD13
AD12
AD7
AD0
AD2
AD3
AD4
AD5
AD6
AD1
D14/RSVD
D13/CAD6
D12/CAD4
D11/CAD2
D10/CAD31
D15/CAD8
D9/CAD30
D8/CAD28
D7/CAD7
D6/CAD5
D5/CAD3
D4/CAD1
D3/CAD0
D2/RSVD
D1/CAD29
D0/CAD27
A22/CTRDY*
A20/CSTOP*
A23/CFRAME*
A21/CDEVSEL*
A19/CBLOCK*
A15/CIRDY*
A14/CPERR*
A12/CC/BE2*
A8/CC/BE1*
A25/CAD19
A24/CAD17
A18/RSVD
A17/CAD16
A16/CCLK
A13/CPAR
A11/CAD12
A10/CAD9
A9/CAD14
A7/CAD18
A6/CAD20
A5/CAD21
CE2/CAD10*
INPACK/CREQ*
WAIT/CSERR*
A4/CAD22
A3/CAD23
A2/CAD24
A1/CAD25
A0/CAD26
VPPD1
VPPD0
VCCD0*
VCCD1*
IORD*/CAD13
IOWR*/CAD15
OE*/CAD11
WE*/CGNT*
CD2*/CCD2*
CD1*/CCD1*
CE1*/CC/BE0*
RDY/IREQ*/CINT*
VS1*/CVS1
VS2*/CVS2
REG*/CC/BE3*
RESET/CRST*
BVD1/CSTSCHG/STSCHG*/RI*
BVD2/SPKR*/CAUDIO
WP/IOIS16*/CCLKRUN*
RI_OUT/PME
CLK_48_RSVD/NC
TPS2211
OC
AVPP
AVCC2
AVCC1
AVCC0
GND
SHTDWN
VCCD0
VCCD1
VPPD0
VPPD1
V_5_2
V_5_1
V_3_2
V_3_1
V_12
DRAWING
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
(or 3.3V)
(or 3.3V)
Allows thinner trace to BGA
This is an internal board short
0.1uF are used to increase ESD of up to 10kV
plane/traces to minimize inductance!
Master: Fizzy
CardBus Interface
TI reference schematic does not
NC
(PCI_AD<21>)
NC
NC
NC
NC
516S0089
Integrated Pullup
Integrated Pullup
Integrated Pullup
Integrated Pullup
Integrated Pullup
Integrated Pullup
Integrated Pullup
Integrated Pullup
Integrated Pullup
Integrated Pullup
Integrated Pullup
Integrated Pullup
Integrated Pullup
Integrated Pullup /
have bulk on PPVCC_CBUS
Integrated Pullup
Clamp for PC Card
DIFFERENTIAL_PAIR
NET_SPACING_TYPE
Power aliases required by this page:
Signal aliases required by this page:
NOTE: All 4 rails MUST implement the same
power state (PWRON or RUN). For
alias to PCI_RESET_L instead.
- _PP3V3_CBUS
- _PP3V3_PCI
- _PP2V5_PCI
Page Notes
- _PP5V_CBUS
to SYS_WARM_RESET_L. For RUN must
PWRON must alias _PCI_CBUS_RESET_L
- _PPVIO_PCI (to _PP5V_PCI or _PP3V3_PCI)
PCI Devices implemented on this page:
(_PPVIO_PCI can be same as _PP3V3_PCI)
NOTE: This CardBus implementation does
AD21 (Slot "E") - CardBus (0x104C/0xAC56)
BOM options provided by this page:
2. _PPVIO_PCI
3. _PP3V3_PCI
Power Down
1. Assert RESET
(NONE)
3. _PPVIO_PCI
Power Up
2. _PP3V3_PCI
1. Assert RESET
Power Sequencing:
not provide PME# or 12V Vpp support.
- _PCI_CLK33M_CBUS (33MHz PCI clock)
- _PCI_CBUS_RESET_L (see note above)
ELECTRICAL_CONSTRAINT_SET
Clamp for PCI
Integrated Pullup
Integrated Pullup
PC Card/CardBus Connector
(or 3.3V)
Make sure Vcc and Vpp are wide
NC
PC Card Power Switch
Disable card power during reset
Pulldown
NC
21
R7803
MF
5%
1/16W
10K
402
21
R7804
5%
402
10K
1/16W
MF
21
R7805
5%
MF
1/16W
10K
402
1
2
8
9
3
7
4
6
10
5
RP7800
10K
5%
1/32W
25V
SM
9
84
83 82
81
80879
78 77
76 75
74 73
72 71
70
7
69
68 67
66 65
64 63
62 61
60
6
59
58 57
56 55
54 53
52 51
50
5
49
48 47
46 45
44 43
42 41
40
4
39
38 37
36 35
34 33
32 31
30329
28 27
26 25
24 23
22 21
20
2
19
18 17
16 15
14 13
12 11
10
1
J7800
QT500806-L111
M-ST-SM
CRITICAL
A5
D13
B6
A9
B2
L8
D4
M11
K9
L3
L12
N13
B11
N11
N7M1E1D5
C13
A7
J3
N10
L1
M9
L2
M8
D8
C2
A8
A6
G3
K3
G1
N1
G10
L10
N12
M10
K10
L9
N9
K7
K1
C11
F12
B8
F2
L11
C1
N2
M13
K8H4
F13
D1
A11
A2
J1
K2
B4
C5
H12
J10
J13
K12
K11
A3
H11
J12
K13
J11
M12
B3
C4
A4
H10
G13
H13
B5
L13
A1
J2
M3
K6
D6
C6
M2
N4
N5
L6
M6
K4
E3
D3
N6
E4
D2
B1
F4
E2
F3
C3
F1
G4
G2
L7
H2
H3
H1
J4
M4
L5
K5
N3
L4
M5
M7
N8
F11
E11
A12
C9
C8
B12
D10
B9
B10
A10
C12
D11
E10
B7
A13
E13
F10
B13
C10
D12
E12
D9
G12
G11
D7
C7
U7800
CRITICAL
PCI1510GGU
BGA
2
1
C7811
2.2uF
20%
10V
CERM
805
2
1
C7810
805
20%
10V
CERM
2.2uF
21
R7802
5%
402
10K
1/16W
MF
2
1
C7807
20%
6.3V
402
0.22uF
X5R
21
R7808
1/16W
5%
MF
402
47
2
1
C7800
10uF
CERM
6.3V
805
20%
2
1
C7801
20%
6.3V
0.22uF
402
X5R
2
1
C7802
20%
6.3V
0.22uF
402
X5R
2
1
C7803
402
6.3V
20%
0.22uF
X5R
2
1
C7804
402
20%
0.22uF
X5R
6.3V
2
1
C7805
402
0.22uF
20%
X5R
6.3V
2
1
C7806
20%
6.3V
0.22uF
402
X5R
2
1
C7809
0.1UF
10V
402
20%
CERM
21
XW7800
SM
6
5
4
3
9
14
15
2
1
16
87
10
13
12
11
U7801
CRITICAL
SSOI
21
R7809
47
5%
1/16W
MF
402
2
1
C7808
0.1UF
CERM
20%
10V
402
2
1
R7806
MF
5%
22
402
1/16W
TITLE=FIZZY
ABBREV=DRAWING
78
051-6532
103
03
VOLTAGE=5V
MIN_LINE_WIDTH=10 mil
MIN_NECK_WIDTH=6 mil
PPVCC_CBUS_XW
CBUS_VPPD1
_PP5V_CBUS
CBUS_VCCD1_L
_PP3V3_CBUS
PCI_AD<9>
PPVCC_CBUS
VOLTAGE=5V
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
PPVPP_CBUS
VOLTAGE=5V
CBUS_DATA<0>
_PPVIO_PCI_CBUS
CBUS_READY
CBUS_BVD1_L
CLOCKS
PCI_CLK_CBUS
_PCI_CLK33M_CBUS
_PCI_CBUS_RESET_L
PCI_TRDY_L
PCI_STOP_L
CBUS_PERR_L_PU
PCI_AD<30>
CBUS_SERR_L_PU
CBUS_SUSPEND_L_PU
CBUS_VR_EN_L_PU
CBUS_PERR_L_PU
_PP3V3_PCI
_PP2V5_PCI
CBUS_WP_L
CBUS_MFUNC3_PD
CBUS_MFUNC2_PD
CBUS_MFUNC1_PD
CBUS_MFUNC4_PD
CBUS_MFUNC5_PD
CBUS_MFUNC6_PD
CBUS_ADDR16_R CBUS_ADDR<16>
CBUS_DET_1_L
CBUS_DET_2_L
CBUS_IORD_L
CBUS_IOWR_L
CBUS_OE_L
CBUS_CE1_L
CBUS_WE_L
CBUS_RESET_L
CBUS_REG_L
CBUS_BVD2_L
CBUS_CE2_L
CBUS_INPACK_L
CBUS_WAIT_L
CBUS_DATA<14>
CBUS_DATA<13>
CBUS_DATA<12>
CBUS_DATA<11>
CBUS_DATA<10>
CBUS_DATA<9>
CBUS_DATA<8>
CBUS_DATA<7>
CBUS_DATA<6>
CBUS_DATA<5>
CBUS_DATA<4>
CBUS_DATA<3>
CBUS_DATA<1>
CBUS_DATA<0>
CBUS_ADDR<25>
CBUS_ADDR<24>
CBUS_ADDR<23>
CBUS_ADDR<22>
CBUS_ADDR<21>
CBUS_ADDR<20>
CBUS_ADDR<19>
CBUS_ADDR<18>
CBUS_ADDR<17>
CBUS_ADDR<15>
CBUS_ADDR<14>
CBUS_ADDR<13>
CBUS_ADDR<12>
CBUS_ADDR<11>
CBUS_ADDR<10>
CBUS_ADDR<9>
CBUS_ADDR<8>
CBUS_ADDR<7>
CBUS_ADDR<6>
CBUS_ADDR<5>
CBUS_ADDR<4>
CBUS_ADDR<3>
CBUS_ADDR<2>
CBUS_ADDR<1>
CBUS_ADDR<0>
CBUS_DATA<15>
PCI_SLOTE_INT_L
PCI_PAR
PCI_AD<8>
PCI_AD<7>
PCI_AD<6>
PCI_AD<5>
PCI_AD<4>
PCI_AD<3>
PCI_AD<29>
PCI_AD<28>
PCI_AD<27>
PCI_AD<26>
PCI_AD<25>
PCI_AD<24>
PCI_AD<23>
PCI_AD<22>
PCI_AD<20>
PCI_AD<2>
PCI_AD<18>
PCI_AD<17>
PCI_AD<14>
PCI_AD<13>
PCI_AD<12>
PCI_AD<11>
PCI_AD<10>
PCI_AD<1>
PCI_AD<0>
_PCI_CLK33M_CBUS
PCI_IRDY_L
CBUS_SERR_L_PU
PCI_FRAME_L
PCI_DEVSEL_L
PCI_SLOTE_REQ_L
PCI_SLOTE_GNT_L
CBUS_SUSPEND_L_PU
CBUS_VS1
CBUS_VS2
CBUS_VR_EN_L_PU
PCI_CBE_L<0>
PCI_AD<21>
PPVCC_CBUS
CBUS_ADDR<0>
CBUS_DATA<1>
CBUS_DATA<2>
CBUS_WP_L
CBUS_ADDR<13>
CBUS_ADDR<14>
CBUS_WE_L
CBUS_READY
PPVCC_CBUS
PPVPP_CBUS
CBUS_ADDR<16>
CBUS_ADDR<15>
CBUS_ADDR<12>
CBUS_ADDR<7>
CBUS_ADDR<6>
CBUS_ADDR<5>
CBUS_ADDR<4>
CBUS_ADDR<3>
CBUS_ADDR<2>
CBUS_ADDR<1>
CBUS_DATA<3>
CBUS_DATA<4>
CBUS_DATA<5>
CBUS_DATA<6>
CBUS_DATA<7>
CBUS_CE1_L
CBUS_ADDR<10>
CBUS_OE_L
CBUS_ADDR<11>
CBUS_ADDR<9>
CBUS_ADDR<8>
CBUS_ADDR<23>
CBUS_ADDR<25>
CBUS_DET_1_L
CBUS_DATA<11>
CBUS_DATA<12>
CBUS_DATA<13>
CBUS_DATA<14>
CBUS_DATA<15>
CBUS_CE2_L
CBUS_VS1
CBUS_IORD_L
CBUS_IOWR_L
CBUS_ADDR<17>
CBUS_ADDR<18>
CBUS_ADDR<19>
CBUS_ADDR<20>
CBUS_ADDR<21>
PPVPP_CBUS
CBUS_ADDR<22>
CBUS_ADDR<24>
CBUS_VS2
CBUS_RESET_L
CBUS_WAIT_L
CBUS_INPACK_L
CBUS_REG_L
CBUS_BVD2_L
CBUS_BVD1_L
CBUS_DATA<10>
CBUS_DET_2_L
PCI_AD<15>
PCI_AD<16>
PCI_AD<19>
PCI_CBE_L<1>
PCI_CBE_L<3>
PCI_CBE_L<2>
PCI_AD<31>
PCI_CBUS_RESET_L_R
PCI_SLOTE_IDSEL
CBUS_DATA<9>
CBUS_DATA<8>
CBUS_DATA<2>
PCI_CBUS_RESET_L_R
CBUS_VCCD0_L
_PP3V3_PCI
CBUS_VPPD0
LAST_MODIFIED=Mon Feb 23 19:07:07 2004
49
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62
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23
45
45
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45
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45
45
45
45
45
45
45
45
45
45
49
45
45
45
45
45
45
45
45
45
45
45
45
23
5
5
6
49
49
49
5
49
49
5
5
6
6
49
6
49
49
49
49
5
5
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
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49
49
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49
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49
49
49
49
23
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
5
6
49
6
6
23
23
49
49
49
49
6
6
49
49
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49
49
49
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49
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49
49
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49
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49
49
49
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49
49
49
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49
49
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6
6
6
6
6
6
6
49
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5
Preliminary
Page 50
UATA
UD_IDECHRDY_H
UD_IDEDMARQ_H
UD_IDEINTRQ_H
UD_IDEDA2_H
UD_IDEDA1_H
UD_IDEDA0_H
UD_IDEDD_15_H
UD_IDEDD_14_H
UD_IDEDD_0_H
UD_IDEDD_1_H
UD_IDEDD_2_H
UD_IDEDD_3_H
UD_IDEDD_4_H
UD_IDEDD_5_H
UD_IDEDD_6_H
UD_IDEDD_7_H
UD_IDEDD_8_H
UD_IDEDD_9_H
UD_IDEDD_10_H
UD_IDEDD_11_H
UD_IDEDD_12_H
UD_IDEDD_13_H
TXDN1
TXDP1
TXDN2
TXDP2
RXDN2
RXDP2
RXDN1
RXDP1
SATA_GND
SATA_VDD
SATA 0
SATA 1
(5 OF 8)
UD_IDECS1FX_L
UD_IDECS3FX_L
UD_IDEDMACK_L
UD_IDERD_L
UD_IDEWR_L
UD_IDERST_L
DRAWING
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
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B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Master: Link
UATA Termination
Shasta Disk
ELECTRICAL_CONSTRAINT_SET
DIFFERENTIAL_PAIR
Page Notes
Power aliases required by this page:
(NONE)
IORDY/HDMARDY*
DSTROBE aka:
HSTROBE aka:
DIOR*
STOP aka:
DIOW*
SATA_VDD x 5
Signal aliases required by this page:
NET_SPACING_TYPE
Recommend 0.1uF cap placed close to Shasta.
AC coupling required for any SATA pair used.
(Caps provided by device page)
(NONE)
BOM options provided by this page:
- _PP1V2_PWRON_DISK
NOTE: Target differential impedance for
Net Spacing Type: SATA
Line To Line: 15 mils
Length Tolerance: 50 mils
SATA data pairs is 100 ohms.
Primary Max Sep: 9 mils inner
Primary Max Sep: 10 mils outer
Secondary Max Sep: 100 mils
Secondary Length: 500 mils
2
1
C8002
0.1uF
402
CERM
20%
10V
2
1
C8001
0.1uF
20%
10V
CERM
402
2
1
C8000
10V
20%
CERM
402
0.1uF
2
1
C8004
0.1uF
402
CERM
10V
20%
2
1
C8003
10V
20%
CERM
402
0.1uF
D3
E7
E4
C5
D7 E8
D4
G5
G6
E3
C2
C1
E2
H6
H7
D5
E5
F5
C3
F6
G7
J6
D6
C4
E6
B4
B3
F9
Y15
AA16
Y14
AB16
Y18
W15
T14
AB17
AB14
W16
T13
AA17
AA14
AB15
Y17
AA15
Y16
U2300
OMIT
BGA
V1.0
SHASTA
54
RP8000
SM1
5%
33
1/16W
63
RP8000
SM1
33
1/16W
5%
72
RP8000
33
5%
1/16W
SM1
54
RP8003
SM1
1/16W
5%
33
81
RP8001
SM1
5%
1/16W
33
72
RP8001
SM1
33
1/16W
5%
63
RP8003
1/16W
33
5%
SM1
81
RP8002
SM1
5%
1/16W
33
72
RP8002
1/16W
33
5%
SM1
81
RP8000
1/16W
33
5%
SM1
54
RP8002
SM1
5%
1/16W
33
72
RP8003
SM1
33
1/16W
5%
63
RP8001
5%
33
1/16W
SM1
81
RP8004
SM1
5%
1/16W
33
81
RP8003
SM1
5%
1/16W
33
63
RP8002
SM1
1/16W
33
5%
72
RP8004
SM1
5%
1/16W
33
54
RP8004
SM1
5%
1/16W
33
54
RP8001
SM1
5%
33
1/16W
63
RP8004
SM1
33
1/16W
5%
2
1
R8005
5%
1/16W
MF
10K
402
21
R8001
33
5%
1/16W
MF
402
21
R8002
22
402
MF
1/16W
5%
21
R8003
5%
1/16W
MF
402
22
21
R8004
5%
1/16W
MF
402
22
21
R8000
402
MF
1/16W
5%
33
ABBREV=DRAWING
TITLE=FIZZY
10380
03
051-6532
SATA
SATA_RXD2
SATA_RXD_N2_C
SATA_RXD2_C
UATA_HOST
UATA_DA<2..0>
UATA_HOST
UATA_CS0_L
UATA_DEV_R
UATA_DMARQ
UATA_HOST
UATA_CS1_L
UATA_DD
UATA_DD<15..8>
SATA
SATA_TXD2
SATA_TXD_N2
SATA_TXD2
SATA_RXD_N2_C
SATA_RXD_P2_C
SATA_RXD_N1_C
SATA_RXD_P1_C
SATA_TXD_P1
SATA_TXD1
SATA
SATA_TXD1
UATA_DEV_R_C
UATA_DSTROBE
UATA_STOP_R
UATA_STOP
UATA_CS1_L_R
UATA_CS1_L
UATA_RESET_L
UATA_RESET_L_R
UATA_DA<1>
UATA_DD<15>
UATA_DD_R<15>
UATA_DD<13>
UATA_DD_R<13>
UATA_DD<11>
UATA_DD_R<11>
UATA_DD<9>
UATA_DD_R<9>
UATA_DD<7>
UATA_DD_R<7>
UATA_DD<5>
UATA_DD_R<5>
UATA_DD<3>
UATA_DD_R<3>
UATA_DD<1>
UATA_DD_R<1>
UATA_DMACK_L_R
UATA_DMACK_L
UATA_HSTROBE_R
UATA_HSTROBE
UATA_CS0_L_R
UATA_CS0_L
UATA_DA<2>
UATA_DA_R<2>
UATA_DA<0>
UATA_DA_R<0>
UATA_DD<14>
UATA_DD_R<14>
UATA_DD<12>
UATA_DD_R<12>
UATA_DD<10>
UATA_DD_R<10>
UATA_DD<8>
UATA_DD_R<8>
UATA_DD<6>
UATA_DD_R<6>
UATA_DD<4>
UATA_DD_R<4>
UATA_DD<2>
UATA_DD_R<2>
UATA_DD<0>
UATA_DD_R<0>
UATA_RESET_L_R
UATA_STOP_R
UATA_HSTROBE_R
UATA_DMACK_L_R
UATA_CS1_L_R
UATA_CS0_L_R
UATA_DA_R<0>
UATA_DD_R<15>
UATA_DD_R<13>
UATA_DD_R<14>
UATA_DD_R<12>
UATA_DD_R<11>
UATA_DD_R<10>
UATA_DD_R<8>
UATA_DD_R<7>
UATA_DD_R<9>
UATA_DD_R<6>
UATA_DD_R<5>
UATA_DD_R<4>
UATA_DD_R<3>
UATA_DD_R<2>
UATA_DD_R<1>
UATA_DD_R<0>
UATA_INTRQ
UATA_DMARQ
UATA_DSTROBE
SATA_TXD_N2
SATA_TXD_P2
SATA_TXD_P1
SATA_TXD_N1
UATA_DA_R<2>
UATA_DA_R<1>
UATA_DEV_R
UATA_INTRQ
UATA_HOST_R
UATA_RESET_L
UATA_HOST_R
UATA_DMACK_L
UATA_HOST
UATA_STOP
UATA_DD7
UATA_DD<7>
UATA_DA_R<1>
_PP1V2_PWRON_DISK_SB
SATA_RXD_N1_C
SATA_RXD1_C
SATA_RXD1
SATA
SATA_RXD1
SATA_RXD1_C
SATA
SATA_RXD_P1_C
SATA_TXD1 SATA_TXD1
SATA
SATA_TXD_N1
SATA
SATA_TXD_P2
SATA_TXD2 SATA_TXD2
UATA_DD<6..0>
UATA_DD
UATA_HOST
UATA_HSTROBE
SATA
SATA_RXD2
SATA_RXD_P2_C
SATA_RXD2_C
LAST_MODIFIED=Mon Feb 23 19:07:21 2004
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Preliminary
Page 51
1414
UAI
UAO
H_STROBE
RX_P
RX_M
TX_P
TX_M
RST*
XTLIN/OSC
XTLOUT
T0
T1
CNFG1
CNFG0
T7
T6
T5
T4
T3
T2
CNFG2
H_INTRQ
H_DMARQ
H_IORDY/
H_DDMARDY*
H_DSTROBE/
H_PDIAG*
H_IOCS16*
ATAIOSEL
H_DD[3]
H_DD[2]
H_DD[1]
H_DD[0]
H_DD[4]
H_DD[9]
H_DD[8]
H_DD[7]
H_DD[6]
H_DD[5]
H_DD[13]
H_DD[12]
H_DD[11]
H_DD[10]
H_DD[14]
H_DA[2]
H_DA[1]
H_DA[0]
H_RESET*
H_DMACK*
H_DMARDY*/
H_DIOR*/
H_CS[1]*
H_CS[0]*
H_DD[15]
H_DIOW*/
H_STOP
ISET
GND
VSS1 VSS2
VDDIO
VDD
VAA1VAA2
SATA
CONFIG/DEBUG
PARALLEL ATA
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
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4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
DRAWING
CONTROLLER
ELECTRICAL_CONSTRAINT_SET
Master: Link
88SA8040 requires SchmittÂTrigger on RST* input
T<4..3> - Reference Clock Configuration
1 - Enable translation of ATA power management
T2 - SSC Enable
1 - Enable SATA Spread Spectrum Clocking
NET_SPACING_TYPE
Place C8162 & C8163
near SATA host device
Signal aliases required by this page:
(Internal Pull-down)
CNFG<2..0> - Mode Configuration
000 Device Mode - 100MB/s
001 Device Mode - 133MB/s
010 Device Mode - 150MB/s (default)
100 Host Mode - 100MB/s
101 Host Mode - 133MB/s
H_IOCS16_N - DMA_EN
1 - Reverse Order mode for Parallel ATA pins
PATA Termination
88SA8040 Config Straps (Device Mode):
00 20 MHz
11 40 MHz
0 - UDMA mode adjustable with Set Features
- _PP1V8_SATABR
BOM options provided by this page:
(NONE)
- _PP3V3_SATABR
SATA port 1.
- SATA_1_BRIDGE (/ SATA_1_CONN)
SATA connector is connected to Shasta
Selects whether 88SA8040 SATA Bridge or
VSS does NOT connect to GND
10mA 50mA 10mA 60mA
0 - Disable SATA Spread Spectrum Clocking
10 1 1 (default)
(Internal Pull-down)
T<1..0> VU Type R/W Long Type
00 1 1
01 1 2
11 2 2
T<1..0> - Vendor Unique (VU) and Read/Write Long
(Internal Pull-up)
T5 - Fixed UDMA
(Internal Pull-downs)
10 30 MHz
01 25 MHz
T<4..3> Clock Frequency
1 - UDMA mode fixed by CNFG<2..0> pins
1 - SATA cable plugged in
0 - SATA cable unplugged
T7 - Plug-in (output)
T6 - Power Mode Enable
0 - Disable translation
(Internal Pull-down)
commands into SATA Partial or Slumber mode
CNFG<2..0> Mode
011 Reserved
111 Reserved
110 Host Mode - 150MB/s
(Internal Pull-up)
H_PDIAG_N - PATA_ORDER
0 - Normal Order mode
ATAIOSEL - ATA I/O Enable
(Internal Pull-up)
0 - Error status on Set Features to set DMA
1 - Good status on Set Features to set DMA
0 - Disable output to ATA bus
1 - Enable output to ATA bus
Power aliases required by this page:
Page Notes
Serial ATA Bridge
Sourced by host or bi-directional
Terminate near bridge
DIFFERENTIAL_PAIR
PROVIDED
SATA
BY
2
1
C8154
CERM
0.1uF
402
10V
20%
2
1
C8153
CERM
402
10V
20%
0.1uF
2
1
C8152
CERM
402
20%
10V
0.1uF
2
1
C8157
0.01uF
16V
20%
402
CERM
2
1
C8158
0.1uF
10V
20%
CERM
402
5
4
2
3
U8199
SC70
74AHC1G14
CRITICAL
5
4
2
3
U8198
CRITICAL
SC70
74AHC1G14
2
1
C8199
10V
20%
0.1uF
402
CERM
2
1
R8198
5%
1/16W
MF
402
330K
2
1
C8198
10V
NO STUFF
402
CERM
20%
0.1uF
54
RP8170
SM1
5%
1/16W
33
72
RP8170
SM1
5%
1/16W
33
54
RP8171
SM1
33
1/16W
5%
72
RP8171
SM1
33
1/16W
5%
54
RP8172
SM1
33
1/16W
5%
72
RP8172
SM1
5%
33
1/16W
54
RP8173
SM1
33
1/16W
5%
72
RP8173
SM1
33
1/16W
5%
54
RP8174
SM1
33
1/16W
5%
81
RP8174
33
SM1
1/16W
5%
21
R8170
33
5%
1/16W
MF
402
21
R8172
22
402
MF
1/16W
5%
21
R8174
22
402
MF
1/16W
5%
63
RP8170
SM1
5%
1/16W
33
81
RP8170
SM1
33
1/16W
5%
63
RP8171
SM1
5%
1/16W
33
21
L8155
FERR-EMI-600-OHM
SM
81
RP8171
SM1
33
1/16W
5%
63
RP8172
SM1
5%
1/16W
33
81
RP8172
SM1
33
1/16W
5%
2
1
R8175
402
10K
MF
1/16W
5%
63
RP8173
SM1
5%
33
1/16W
81
RP8173
SM1
33
1/16W
5%
72
RP8174
SM1
33
1/16W
5%
21
R8171
33
5%
1/16W
MF
402
2
1
C8155
805
6.3V
10uF
20%
CERM
21
R8173
5%
1/16W
MF
402
22
21
R8179
22
402
MF
1/16W
5%
23
22
30
25
44
4
56419
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24
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26
16
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14
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11
7
5
2
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63
1
3
6
10
64
62
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50
47
48
57
42
8
20
19
18
21
U8150
QFP-64
88SA8040
2
1
C8156
10V
402
20%
CERM
0.1uF
21
C8162
402
20%
CERM
0.01uF
16V
21
C8163
20%
CERM
402
0.01uF
16V
2
1
R8160
12.1K
402
MF
1/16W
1%
21
C8160
CERM
20%
402
0.01uF
16V
21
C8161
20%
402
CERM
0.01uF
16V
2
1
C8150
0.1uF
CERM
20%
10V
402
2
1
C8151
10V
0.1uF
402
20%
CERM
2
1
C8159
805
6.3V
CERM
20%
10uF
051-6532
03
10381
ABBREV=DRAWING
TITLE=FIZZY
PATA_DEV_R_C
PATA_DSTROBE
SATA_BR_RXD_N
SATA
SATA_BR_RXD
PATA_HOST
PATA_CS1_L
PATA_HSTROBE
PATA_HOST
TP_SATABR_CLK25M_XTLOUT
SATA_BR_RXD_P
PATA_DSTROBE
SYS_COLD_RESET_L
PATA_DEV_R
PATA_DMARQ
PATA_RESET_L
PATA_RESET_L_R
PATA_DMACK_L_R
PATA_DMACK_L
PATA_STOP_R
PATA_STOP
PATA_HSTROBE_R
PATA_HSTROBE
PATA_CS1_L_R
PATA_CS1_L
PATA_CS0_L_R
PATA_CS0_L
PATA_DD_R<15>
PATA_DD_R<13>
PATA_DD_R<11>
PATA_DD_R<9>
PATA_DD_R<3>
PATA_DD_R<1>
PATA_DD_R<12>
PATA_DD_R<10>
PATA_DD_R<8>
PATA_DD_R<6>
PATA_DD_R<4>
PATA_DD_R<2>
PATA_DD_R<0>
PATA_DA<1>
PATA_DA<2>
PATA_DA<0>
PATA_DD<13>
PATA_DD<11>
PATA_DD<9>
PATA_DD<12>
PATA_DD<10>
PATA_DD<7>
PATA_DD<8>
PATA_DD<6>
PATA_DD<5>
PATA_DD<3>
PATA_DD<4>
PATA_DD<2>
PATA_DD<1>
PATA_DD<0>
PATA_HOST
PATA_DD<15..8>
PATA_DA<3..0>
PATA_HOST
PATA_RESET_L
PATA_HOST_R
PATA_HOST
PATA_CS0_L
_PP3V3_SATABR
MIN_NECK_WIDTH=10 mil
MIN_LINE_WIDTH=20 mil
VOLTAGE=0V
SATABR_VSS
PATA_CS1_L_R
PATA_HSTROBE_R
PATA_STOP_R
SATABR_ISET_PD
PATA_DMACK_L_R
PATA_RESET_L_R
PATA_CS0_L_R
PATA_DA_R<2>
PATA_DA_R<1>
PATA_DD_R<14>
PATA_DD_R<15>
PATA_DA_R<0>
PATA_DD_R<12>
PATA_DD_R<13>
PATA_DD_R<9>
PATA_DD_R<10>
PATA_DD_R<11>
PATA_DD_R<8>
PATA_DD_R<7>
PATA_DD_R<4>
PATA_DD_R<5>
PATA_DD_R<6>
PATA_DD_R<1>
PATA_DD_R<2>
PATA_DD_R<3>
PATA_DD_R<0>
TP_SATABR_T7
TP_SATABR_UAO
SATA_TXD_N1
PATA_DD<6..0>
PATA_HOST
TP_SATABR_UAI
PATA_DA_R<2>
PATA_DA_R<1>
PATA_DD_R<5>
PATA_DD<14>
PATA_DD<15>
PATA_DA_R<0>
PATA_DD_R<14>
PATA_HOST_R
PATA_DMACK_L
SATA_BR_RXD_N
PATA_INTRQ
PATA_DEV_R
_PP1V8_SATABR
SATABR_VSS
_PP3V3_SATABR
SATA_BR_TXD_P
SATA_BR_TXD_N
SATA_TXD_P1
SATA_RXD_P1_C
SATA_RXD_N1_C
PATA_DD_R<7>
VOLTAGE=3.3V
PP3V3_SATABR_VAA
MIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=10 mil
SATA
SATA_BR_RXD_P
SATA_BR_RXD
SATABR_RESET_ST
SB_SATABR_RESET_L
_PP3V3_SATABR
PATA_INTRQ
PATA_DD7
PATA_DD<7>
PATA_HOST
PATA_STOP
SATA
SATA_BR_TXD_P
SATA_BR_TXD
SATA_BR_TXD
SATA_BR_TXD_N
SATA
CLOCKS
_SATA_CLK25M
SATABR_RESET_L
PATA_DMARQ
_SATA_CLK25M
LAST_MODIFIED=Mon Feb 23 19:07:28 2004
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51
51
51
51
51
51
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
5
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51 50
6
51
51
51
6
6
51
51
6
51
51
5
51
5
51
51
50 50
50
51
51
23
5
51
6
6
51
51
5
51
5
Preliminary
Page 52
DRAWING
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
IDE Connectors
(NONE)
(NONE)
NOTE: ATA constraints are expected to be
BOM options provided by this page:
- _PP3V3_UATA
- _PP3V3_PATA
- _PP5V_UATA
- _PP5V_PATA
Power aliases required by this page:
NC
516S0140
NC
NC
516S0140
PATA (SATA Bridge) Connector
defined on another page (ATA host)
and apply to this page via XNets.
Signal aliases required by this page:
Page Notes
UATA (SouthBridge) Connector
21
R8307
5%
1/16W
MF
402
82
2
1
R8351
5%
1/16W
MF
402
4.7K
9
8
7
6
50
5
49
48
47
46
45
44
43
42
41
40
4
39
38
37
36
35
34
33
32
31
30
3
29
28
27
2625
24
23
22
21
20
2
19
18
17
16
15
14
13
12
11
10
1
J8300
CRITICAL
M-ST-SM1
2
1
R8304
20K
402
MF
1/16W
5%
2
1
R8305
10K
402
MF
5%
1/16W
2
1
R8300
NO STUFF
5%
1/16W
MF
402
10K
2
1
R8301
10K
5%
1/16W
MF
402
2
1
R8302
NO STUFF
10K
402
MF
1/16W
5%
21
R8308
82
402
MF
1/16W
5%
21
R8309
1/16W
5%
MF
402
82
2
1
C8308
50V
10pF
402
CERM
5%
9
8
7
6
50
5
49
48
47
46
45
44
43
42
41
40
4
39
38
37
36
35
34
33
32
31
30
3
29
28
27
2625
24
23
22
21
20
2
19
18
17
16
15
14
13
12
11
10
1
J8350
CRITICAL
M-ST-SM1
2
1
R8352
NO STUFF
5%
1/16W
MF
402
10K
2
1
R8350
NO STUFF
10K
402
MF
1/16W
5%
2
1
R8354
5%
1/16W
MF
402
20K
21
R8357
5%
1/16W
MF
402
82
2
1
R8355
10K
402
MF
1/16W
5%
21
R8358
5%
1/16W
MF
402
82
21
R8359
82
402
MF
1/16W
5%
2
1
C8358
5%
50V
CERM
402
10pF
2
1
R8363
PATA_3V3_LOGIC
5%
1/16W
MF
603
0
2
1
R8365
MF
1/16W
5%
603
0
PATA_5V_LOGIC
TITLE=FIZZY
ABBREV=DRAWING
03
051-6532
10383
UATA_INTRQ_R
UATA_DD<9>
PATA_DMARQ
PATA_DD<7>
PATA_DD<6>
PATA_DD<3>
PATA_DD<2>
PATA_DD<1>
PATA_DD<0>
PATA_DMARQ_R
PATA_HSTROBE
PATA_DA<1>
PATA_DA<0>
PATA_CS0_L
PATA_DD<8>
PATA_DD<9>
PATA_DD<10>
PATA_DD<11>
PATA_DD<12>
PATA_DD<13>
PATA_DD<14>
PATA_DD<15>
PATA_STOP
PATA_DA<2>
PATA_CS1_L
PATA_DD<5>
PATA_DD<4>
PATA_INTRQ
MIN_LINE_WIDTH=15 mil
VOLTAGE=5V
PPLOGIC_PATA
MIN_NECK_WIDTH=10 mil
PATA_DMACK_L
PATA_DSTROBE_R
PATA_INTRQ_R
PATA_RESET_L
PATA_DSTROBE
UATA_DMARQ
UATA_DA<0>
UATA_DD<8>
UATA_DD<10>
UATA_DD<13>
UATA_DD<14>
UATA_HSTROBE
UATA_DA<2>
UATA_CS1_L
UATA_DD<4>
UATA_DD<0>
UATA_STOP
UATA_DA<1>
UATA_CS0_L
UATA_DD<11>
UATA_DD<12>
UATA_DD<15>
UATA_INTRQ
UATA_DMACK_L
UATA_DSTROBE
_PP5V_UATA
UATA_RESET_L
UATA_DD<7>
UATA_DD<6>
UATA_DD<5>
UATA_DD<2>
UATA_DD<3>
UATA_DSTROBE_R
UATA_DD<1>
UATA_DMARQ_R
_PP3V3_PATA
_PP5V_PATA
LAST_MODIFIED=Mon Feb 23 19:07:36 2004
50
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
6
6
51
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
51
6
6
6
6
6
51
50
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
50
6
50
5
6
6
6
6
6
6
6
6
6
5
5
Preliminary
Page 53
ETHERNET
(6 OF 8)
ETH_GTX_CLK_H
ETH_TX_ER_H
ETH_TX_EN_H
ETH_TXD_7_H
ETH_TXD_6_H
ETH_TXD_5_H
ETH_TXD_4_H
ETH_TXD_3_H
ETH_TXD_2_H
ETH_TXD_1_H
ETH_TXD_0_H
ETH_MDC_H
ETH_MDIO_H
ETH_TX_CLK_H
ETH_RX_CLK_H
ETH_RXD_0_H
ETH_RXD_1_H
ETH_RXD_2_H
ETH_REFCLK_H
ETH_RXD_3_H
ETH_RXD_4_H
ETH_RXD_5_H
ETH_RXD_6_H
ETH_RXD_7_H
ETH_RX_DV_H
ETH_RX_ER_H
ETH_CRS_H
ETH_COL_H
DRAWING
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
DIFFERENTIAL_PAIR
NET_SPACING_TYPE
NET_PHYSICAL_TYPE
Page Notes
Signal aliases required by this page:
BOM options provided by this page:
(NONE)
(NONE)
Power aliases required by this page:
(NONE)
Shasta Ethernet
ELECTRICAL_CONSTRAINT_SET
Master: Link
F1
H3
H5
K6
J4
F2
G3
J5
H4
E1
G4
G2
K4
J3
G1
J2
K3
L4
J1
K2
L3
K1
M5
M6
M4
K5
L6
L5
U2300
OMIT
BGA
V1.0
SHASTA
72
RP8400
1/16W
0K
5%
SM1
54
RP8400
0K
1/16W
5%
SM1
81
RP8400
0K
5%
1/16W
SM1
63
RP8400
0K
5%
1/16W
SM1
72
RP8401
0K
5%
1/16W
SM1
54
RP8401
0K
SM1
1/16W
5%
81
RP8401
0K
5%
1/16W
SM1
63
RP8401
5%
1/16W
SM1
0K
21
R8400
0
402
MF
1/16W
5%
21
R8401
5%
1/16W
0
MF
402
21
R8402
0
5%
1/16W
MF
402
TITLE=FIZZY
ABBREV=DRAWING
LAST_MODIFIED=Mon Feb 23 18:36:38 2004
10384
03
051-6532
ENET_TXD_R<6>
ENET_TXD_R<3>
ENET_TXD_R<7>
ENET_TXD_R<4>
ENET_TX_EN_R
ENET_CLK125M_GBE_REF
ENET_CLK125M_RX
ENET_CLK25M_TX
ENET_TXD_R<5>
ENET_TX_ER_R
ENET_CLK125M_GTX_R
ENET_TXD_R<1>
ENET_TXD_R<0>
ENET_TXD_R<2>
ENET_COL
ENET_CRS
ENET_RX_ER
ENET_RX_DV
ENET_RXD<7>
ENET_RXD<6>
ENET_RXD<5>
ENET_RXD<4>
ENET_RXD<3>
ENET_RXD<2>
ENET_RXD<1>
ENET_RXD<0>
ENET_MDC
ENET_MDIO
ENET_TXD<7>
ENET_TXD<0>
ENET_TXD<1>
ENET_TXD<2>
ENET_TXD<4>
ENET_TXD<3>
ENET_TXD<6>
ENET_TX_EN
ENET_TXD<5>
ENET_CLK125M_GTX
ENET_TX_ER
ENET_TX
ENET_TXD<7..0>
ENET
ENET_RX_DV
ENET_RX_CTL
ENET
ENET_CLK125M_GTX_R
15 MIL SPACING
ENET
ENET_RX_CLK
ENET_CLK125M_RX
15 MIL SPACING
ENET
ENET_RX
ENET_RXD<7..0>
ENET
ENET_RX_CTL
ENET_RX_ER
ENET
ENET_TX_EN
ENET_TX_CTL
ENET
ENET_COL
ENET_RX_CTL
ENET
ENET_MDC
ENET_MDC ENET
ENET_MDIO
ENET_MDIO
ENET
ENET_TX_CLK
ENET_CLK125M_GTX
15 MIL SPACING
ENET
ENET_GBE_REF
ENET_CLK125M_GBE_REF
15 MIL SPACING
ENET
ENET_TX_CTL
ENET_TX_ER
ENET
ENET_CRS
ENET_RX_CTL
ENET
ENET_RX_CLK
ENET_CLK25M_TX
15 MIL SPACING
ENET
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
Preliminary
Page 54
INTR*/ENERGYDET
GTXCLK
XTALGND BIASGND PLLGND1
CLK125
TXD[4]
TXD[3]
TXD[2]
TXD[1]
TXD[0]
MDIO
MDC
TX_ER
TX_EN
TXD[7]
TXD[6]
TXD[5]
LOWPWR
TXC
RXC
RXD[7]
RX_DV
RX_ER
XTALO
XTALI
ER
HUB
MANMS
SPD0
F1000
FDX
RGMIIEN
EN_10B
PHYA[4]
PHYA[3]
PHYA[2]
PHYA[1]
PHYA[0]
TVCO
TEST[0]
TEST[1]
COL
CRS
RBC0
TRD+[0]
TRD-[0]
TRD+[1]
TRD-[1]
TRD+[2]
TRD-[2]
TRD-[3]
TRD+[3]
RBC1
RXD[2]
RXD[3]
RXD[4]
RXD[5]
RXD[6]
RXD[1]
RXD[0]
SLAVE*/AN_EN
ACTLED*
XMTLED*
FDXLED*
LINK2*
LINK1*
QUALITY*/TXC_RXC_DELAY
RDAC1
PLLVDD1
BIASVDD1XTALVDD1
VESTA ENET
2 OF 3
DRAWING
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
(NONE)
(NONE)
Secondary Max Sep: 100 mils
Secondary Length: 500 mils
Primary Max Sep: 5 mils
Length Tolerance: 50 mils
Line To Line: 15 mils
BOM options provided by this page:
Signal aliases required by this page:
NOTE: Target differential impedance for
ENET data pairs is 100 ohms.
Net Spacing Type: ENET
Page Notes
- _PP2V5_ENETFW
- _PP3V3_ENET
Power aliases required by this page:
DIFFERENTIAL_PAIR
NET_SPACING_TYPE
Vesta Ethernet PHY
ELECTRICAL_CONSTRAINT_SET
PLACE RESISTORS CLOSE TO PHY
ESR < 0.5 ohms
Sets Hub/DTE bit and master/slave configuration value bit
(Internal Pull-up)
0 - Auto-negotiation disabled
1 - Auto-negotiation enabled
AN_EN - Auto-Negotiation Select
0 - Rise time approx. 4 ns
1 - Rise time approx. 5 ns
ER - Edge Rate Select
(Internal Pull-down)
FDX - Full-Duplex Select
Sets manual duplex mode bit
(Internal Pull-up)
0 - GMII/TBI Mode
1 - RGMII/RTBI Mode
RGMIIEN - RGMII Enable
(Internal Pull-down)
0 - GMII/RGMII Mode
(Internal Pull-down)
F1000 - Speed Select
TXC_RXC_DELAY
GTXCLK are delayed by 1.9 ns
(Internal Pull-down)
0 - No clock delay
0 1 X Force 1000BASE-T (test use only)
1 1 0 Auto-negotiate advertise 10/100/1000BASE-T
1 0 1 Auto-negotiate advertise 10/100BASE-TX
1 0 0 Auto-negotiate advertise 10BASE-T
0 0 1 Force 100BASE-TX
SPD0 - Speed Select
(Internal Pull-down)
See table below
(Internal Pull-up)
AN_EN F1000 SPD0 Description
0 0 0 Force 10BASE-T
See table below
- _PP1V2_ENETFW
1 1 1 Auto-negotiate advertise 1000BASE-T
(Internal Pull-down)
Vesta Config Straps:
1 - TBI/RTBI Mode
EN_10B - TBI Interface Select
PHYA<4..0> - PHY Address Select
(Internal Pull-downs)
(Internal Pull-down)
HUB - Repeater Select
Sets manual master/slave configuration enable bit
MANMS - Manual Master/Slave Configuration Select
1 - If RGMII Mode enabled, RXC clock and
CRYSTAL LOAD CAPACITANCE IS 20PF
Put crystal circuit close to PHY
Master: Link
2
1
R8616
49.9
1%
1/16W
MF
402
2
1
R8617
1/16W
402
MF
1%
49.9
2
1
R8614
402
MF
1/16W
1%
49.9
2
1
R8615
402
MF
1/16W
1%
49.9
21
R8602
0
402
5%
1/16W
MF
21
Y8600
CRITICAL
25.0000M
8X4.5MM-SM
2
1
R8620
49.9
1%
MF
402
1/16W
2
1
R8618
MF
1/16W
1%
49.9
402
2
1
R8621
402
MF
1/16W
49.9
1%
2
1
R8619
1%
49.9
1/16W
MF
402
2
1
C8620
20%
0.01UF
16V
CERM
402
2
1
C8622
402
0.01UF
CERM
16V
20%
2
1
C8623
0.01UF
402
CERM
16V
20%
21
R8601
0
402
5%
1/16W
MF
21
R8600
0
MF
1/16W
402
5%
2
1
R8613
402
MF
1/16W
1%
1.24K
2
1
R8609
MF
1/16W
5%
0
402
2
1
C8621
0.01UF
20%
16V
CERM
402
2
1
R8650
1/16W
402
MF
5%
1.5K
2
1
C8604
0.001uF
50V
20%
CERM
402
21
L8602
SM
FERR-EMI-600-OHM
2
1
C8605
1206
6.3V
20%
CERM
10uF
2
1
C8601
402
CERM
20%
0.1uF
10V
21
L8600
SM
FERR-EMI-600-OHM
21
L8601
SM
FERR-EMI-600-OHM
2
1
C8603
402
50V
CERM
0.001uF
20%
2
1
C8602
805
20%
10uF
6.3V
CERM
N1
P2
N2
P3
B12
C4
B4
A5
B5
C5
E6
D6
C7
C6
B6
A6
N3
R10
R11
R9
R8
R6
R7
R5
R4
M5
M4
K5
C10
C2
D2
D3
D4
D5
E3
E4
E5
F5
F4
C1
B8
R1
B3
A3
A8
M1
M2
L1
L2
L3
L4
L5
G2
G1
D9
H5
B11
A10
D10
A9
A4
B10
C8
K4
H3
K3
G3
F3
D1
P1
R2
A11
U8600
OMIT
BCM5462
FBGA-200
2
1
C8618
5%
50V
CERM
402
33pF
2
1
C8619
5%
50V
CERM
402
33pF
TITLE=FIZZY
ABBREV=DRAWING
03
051-6532
10386
VOLTAGE=2.5V
PP2V5_VESTA_BIASVDD1
MIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=15 mil
TP_VESTA_SPD0
TP_VESTA_MANMS
TP_VESTA_HUB
TP_VESTA_TVCO
TP_VESTA_ER
VOLTAGE=1.2V
MIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=15 mil
PP1V2_VESTA_PLLVDD1
ENET_MDI
ENET_MDI3
ENET_MDI_N<3>
ENET
ENET_CLK125M_RX_R
15 MIL SPACING
ENET_MDI
ENET_MDI_P<3>
ENET_MDI3
ENET
VESTA_CLK25M_XTAL
15 MIL SPACING
VESTA_CLK25M_XTALI
_PP2V5_ENETFW
ENET_MDC
TP_VESTA_PHYA<4>
_PP1V2_ENETFW
ENET_CLK25M_TX_R
TP_VESTA_TXC_RXC_DELAY
TP_VESTA_AN_EN
ENET_ENERGYDET
ENET_CLK125M_GTX
ENET_TXD<1>
ENET_TXD<0>
ENET_TXD<4>
ENET_TXD<2>
ENET_TXD<3>
ENET_TXD<5>
ENET_TXD<6>
ENET_TXD<7>
ENET_TX_EN
ENET_TX_ER
ENET_CLK125M_RX_R
ENET_RXD<7>
ENET_RX_DV
ENET_RX_ER
VESTA_CLK25M_XTALO_R
TP_VESTA_PHYA<0>
TP_VESTA_PHYA<1>
TP_VESTA_PHYA<2>
TP_VESTA_PHYA<3>
TP_VESTA_EN_10B
TP_VESTA_FDX
TP_VESTA_RGMIIEN
TP_VESTA_F1000
TP_VESTA_TEST<1>
TP_VESTA_TEST<0>
ENET_COL
ENET_CRS
TP_VESTA_RBC0
ENET_RXD<0>
ENET_RXD<3>
ENET_RXD<1>
ENET_RXD<4>
ENET_RXD<5>
ENET_RXD<6>
TP_VESTA_LINK1_L
TP_VESTA_FDXLED_L
TP_VESTA_XMTLED_L
TP_VESTA_ACTLED_L
VESTA_RDAC1_PD
VESTA_ENET_LOWPWR
ENET_CLK125M_RX
ENET_CLK125M_GBE_REF
ENET_CLK25M_TX
VESTA_CLK25M_XTALI
VESTA_CLK25M_XTALO
ENET_MDIO
ENET_MDI0 ENET_MDI1
ENET_MDI_P<0>
ENET_MDI_N<0>
ENET_MDI_N<1>
ENET_MDI_P<1>
ENET_MDI2 ENET_MDI3
ENET_MDI_N<2>
ENET_MDI_P<2>
ENET_MDI_P<3>
_PP3V3_ENET
ENET_CLK125M_GBE_REF_R
VOLTAGE=2.5V
MIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=15 mil
PP2V5_VESTA_XTALVDD1
ENET_CLK125M_GBE_REF_R
15 MIL SPACING
15 MIL SPACING
VESTA_CLK25M_XTALO
15 MIL SPACING
VESTA_CLK25M_XTALO_R
ENET_MDI
ENET_MDI0
ENET_MDI_P<0>
ENET
ENETENET_MDI
ENET_MDI1
ENET_MDI_N<1>
ENET_MDI
ENET_MDI2
ENET_MDI_P<2>
ENET
ENET_CLK25M_TX_R
15 MIL SPACING
ENET_MDI
ENET_MDI1
ENET_MDI_P<1>
ENET
TP_VESTA_LINK2_L
ENET_MDI_N<3>
TP_VESTA_RBC1
ENET_RXD<2>
ENET_MDI2
ENET_MDI_N<2>
ENET_MDI ENET
ENET_MDI0
ENET_MDI
ENET_MDI_N<0>
ENET
LAST_MODIFIED=Mon Feb 23 19:07:51 2004
55
55
57
57
55
55
55
55
55
55
55
55
55
55
55
55
55
55
54
54
54
54
12
53
12
54
23
53
53
53
53
53
53
53
53
53
53
53
54
53
53
53
54
53
53
53
53
53
53
53
53
12
53
53
53
54
54
53
54
54
54
54
54
54
54
12
54
54
54
54
54
54
54
54
54
54
53
54
54
Preliminary
Page 55
DRAWING
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Place one cap at each pin of transformer
.
Ethernet Connector
DIFFERENTIAL_PAIR
NET_SPACING_TYPE
ELECTRICAL_CONSTRAINT_SET
Page Notes
Signal aliases required by this page:
Power aliases required by this page:
(NONE)
(NONE)
- _GND_CHASSIS_ENET
- _PP2V5_ENET
BOM options provided by this page:
PHY
ETHERNET
BY
PROVIDED
Place close to connector
Short shielded RJ-45
514-0059
24
21
18
15
22
19
16
13
23
20
17
14
3
6
9
12
2
5
8
11
1
4
7
10
T8700
XFR-ENET-1000BT
SM
CRITICAL
2
1
C8700
20%
10V
402
CERM
0.1uF
2
1
C8701
10V
0.1uF
CERM
402
20%
2
1
C8702
20%
10V
402
CERM
0.1uF
2
1
C8703
0.1uF
CERM
402
10V
20%
8
7
6
5
4
3
2
1
12
11
10
9
J8710
CRITICAL
RT-TH
RJ45
2
1
R8705
75
402
MF
1/16W
5%
2
1
R8706
5%
1/16W
MF
402
75
2
1
R8708
402
MF
1/16W
5%
75
2
1
R8707
5%
1/16W
MF
402
75
2
1
C8705
1808
3KV
10%
100pF
CERM
21
R8710
NO STUFF
5%
1/10W
FF
805
0
ABBREV=DRAWING
TITLE=FIZZY
051-6532
03
87 103
ENET_RJ45_P<1>
ENET_RJ45_N<0>
ENET_CTAP_COMMON
_GND_CHASSIS_ENET
ENET_CTAP<3>
ENET_CTAP<2>
ENET_CTAP<1>
ENET_CTAP<0>
ENET_RJ45_N<3>
ENET_RJ45_N<1>
ENET_RJ45_P<2>
ENET_RJ45_P<0>
ENET_RJ45_P<3>
ENET_RJ45_N<2>
_PP2V5_ENET
ENET_MDI_N<3>
ENET_MDI_N<2>
ENET_MDI_P<3>
ENET_MDI_P<2>
ENET_MDI_N<1>
ENET_MDI_N<0>
ENET_MDI_P<1>
ENET_MDI_P<0>
ENET_RJ45_3
ENET_RJ45_N<3>
ENET
ENET_RJ45_3
ENET_RJ45_P<3>
ENET
ENET_RJ45_2
ENET_RJ45_P<2>
ENET
ENET_RJ45_2
ENET_RJ45_N<2>
ENET
ENET_RJ45_1
ENET_RJ45_N<1>
ENET
ENET_RJ45_0
ENET_RJ45_N<0>
ENET
ENET_RJ45_1
ENET_RJ45_P<1>
ENET
ENET_RJ45_0
ENET_RJ45_P<0>
ENET
LAST_MODIFIED=Mon Feb 23 19:07:58 2004
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5
55
55
55
55
55
55
5
54
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54
54
54
54
55
55
55
55
55
55
55
55
Preliminary
Page 56
PHY_LINKON_LPHY_PINT_L
FWVDDP
PHY_LREQ_H
PHY_LPS_H
PHY_CTL_1_H
PHY_CTL_0_H
PHY_DATA_7_H
PHY_DATA_6_H
PHY_DATA_0_H
PHY_DATA_1_H
PHY_DATA_2_H
PHY_DATA_3_H
PHY_DATA_4_H
PHY_DATA_5_H
(7 OF 8)
PHY_LCLK_HPHY_SCLK_H
FIREWIRE
DRAWING
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
NET_PHYSICAL_TYPE
NET_SPACING_TYPE
DIFFERENTIAL_PAIR
Page Notes
Shasta FireWire
ELECTRICAL_CONSTRAINT_SET
BOM options provided by this page:
- _PP2V5_PWRON_SB
(NONE)
(NONE)
Signal aliases required by this page:
Power aliases required by this page:
Master: Link
21
R8800
5%
1/16W
22
MF
402
2
1
C8802
0.1uF
10V
CERM
402
20%
2
1
C8801
20%
10V
CERM
402
0.1uF
2
1
C8800
0.1uF
402
CERM
10V
20%
P2
P3
P1
P6
N7
R1
L2
M3
L1
N6
M7
N1
P5
N4
N3
N2
A4J7N5
U2300
OMIT
BGA
V1.0
SHASTA
TITLE=FIZZY
ABBREV=DRAWING
051-6532
03
88 103
FW_LINKON
FW_PINT
_PP2V5_PWRON_SB
FW_DATA<0>
FW_DATA<1>
FW_DATA<2>
FW_DATA<3>
FW_DATA<4>
FW_DATA<5>
FW_DATA<7>
FW_DATA<6>
FW_CTL<1>
FW_CTL<0>
FW_LPS
FW_LREQ
FW_CLK98M_LCLK_R
FW_CLK98M_PCLK FW_CLK98M_LCLK
FW_PINT
FW_PINT
FW
FW_PCLK
FW_CLK98M_PCLK
15 MIL SPACING
FW
FW_LREQ
FW_LREQ
FW
FW_LPS
FW_LPS
FW
FW_CTL<1..0>
FW FW
FW_CLK98M_LCLK_R
15 MIL SPACING
FW_LCLK
FW_CLK98M_LCLK
15 MIL SPACING
FW
FW
FW_DATA<7..0>
FW
LAST_MODIFIED=Mon Feb 23 19:08:06 2004
45 23
57
21
57
57
57
57
57
57
57
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57
57
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57 57
57
57
57
57
57
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5
56
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Preliminary
Page 57
VCC
VSS
E2
E1
E0
SDA
SCL
WC*
FAVDDLFAVDDMFAVDDH
TDBL[1]
TDBL[2]
PLI_PCLK
TDBL[0]
TPBIAS[0]
TPAP[0]
TPAN[0]
TPBP[0]
TPBN[0]
TPBIAS[1]
TPAP[1]
TPAN[1]
TPBP[1]
TPBN[1]
TPAP[2]
TPAN[2]
TPBP[2]
TPBN[2]
TPBIAS[2]
PLI_INT
PLI_LINK
SDC
SDA
RDAC2
XTALVDD2
BIASVDD2
PLLVDD2
BIASGND PLLGND2
TEST_1394[0]
TEST_1394[1]
TVCO_24
XTALI_24
XTALO_24
CPS
ESDET1
ESDET0
ESDET2
PLI_LCLK
PLI_DATA[7]
PLI_DATA[0]
PLI_DATA[1]
PLI_DATA[2]
PLI_DATA[3]
PLI_DATA[4]
PLI_DATA[5]
PLI_DATA[6]
PLI_CTL[0]
PWR_CLASS
PLI_CTL[1]
PLI_LPS
PLI_LREQ
LPWR_1394
DS_ONLY_EN0
3 OF 3
VESTA FW
DRAWING
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
CRYSTAL LOAD CAPACITANCE IS 12PF
Put crystal circuit close to PHY
Vesta Config Straps:
PWR_CLASS - FireWire Power Class
1 - Sets Power Class to 0x4
0 - Sets Power Class to 0x0
(Internal Pull-up)
DS_ONLY_EN0 - Port 0 Data/Strobe
1 - Port 0 Data/Strobe mode only
(Internal Pull-down)
0 - Port 0 Bilingual mode
Page Notes
- _PP1V2_ENETFW
- _PP2V5_ENETFW
- _PP3V3_ENETFW
DIFFERENTIAL_PAIR
NET_SPACING_TYPE
Power aliases required by this page:
- _PPFW_PHY
- _PP3V3_FW
ESR < 0.5 ohms
Internal Pull-Down
Internal Pull-Up
Vesta FireWire PHY
(I2C_VESTA_SDA)
I2C Addr A0
(I2C_VESTA_SCL)
ELECTRICAL_CONSTRAINT_SET
(PROVIDED BY LINK PAGE)
counter internal pull-down in Vesta.
If stuffed, adds external pull-up to
Signal aliases required by this page:
BOM options provided by this page:
(NONE)
- VESTA_DS_ONLY_EN0
See straps table for more information.
Net Spacing Type: FW
Line To Line: 15 mils
Secondary Length: 500 mils
Secondary Max Sep: 100 mils
NOTE: Target differential impedance for
Primary Max Sep: 7.5 mils
FW data pairs is 110 ohms.
Length Tolerance: 100 mils
See straps table for more information.
- VESTA_PWR_CLASS_0
If stuffed, adds external pull-down to
counter internal pull-up in Vesta.
Master: Link
54
RP8900
1/16W
22
SM1
5%
63
RP8900
1/16W
5%
SM1
22
72
RP8900
22
SM1
1/16W
5%
81
RP8900
5%
1/16W
SM1
22
63
RP8901
22
SM1
1/16W
5%
81
RP8901
22
SM1
1/16W
5%
54
RP8901
22
5%
1/16W
SM1
72
RP8901
5%
1/16W
SM1
22
21
R8900
5%
1/16W
MF
402
22
21
R8901
5%
1/16W
MF
402
22
21
R8902
1/16W
5%
MF
402
22
2
1
R8909
2K
402
MF
1/16W
1%
2
1
R8911
402
MF
VESTA_DS_ONLY_EN0
1/16W
10K
5%
2
1
R8912
5%
1/16W
MF
402
10K
VESTA_PWR_CLASS_0
2
1
C8913
0.1uF
10V
20%
CERM
402
2
1
C8914
20%
10V
CERM
402
0.1uF
2
1
C8915
20%
10V
CERM
0.1uF
402
2
1
C8911
0.1uF
402
CERM
10V
20%
2
1
C8909
20%
10V
CERM
402
0.1uF
2
1
C8908
20%
10V
CERM
402
0.1uF
2
1
C8907
CERM
20%
10V
402
0.1uF
2
1
C8906
0.1uF
402
CERM
10V
20%
2
1
C8903
402
CERM
20%
0.1uF
10V
21
L8901
FERR-EMI-600-OHM
SM
2
1
C8901
0.001uF
402
CERM
20%
50V
2
1
C8900
CERM
20%
10uF
6.3V
1206
21
L8900
SM
FERR-EMI-600-OHM
2
1
C8905
20%
50V
CERM
402
0.001uF
2
1
C8904
805
6.3V
10uF
20%
CERM
21
L8902
SM
FERR-EMI-600-OHM
2
1
R8921
1/16W
402
MF
5%
0
21
Y8920
CRITICAL
24.576M
8X4.5MM-SM
2
1
R8903
1K
402
MF
1/16W
1%
7
4
8
5
6
3
2
1
U8950
OMIT
16KX8_M24128B
SOI
2
1
C8950
0.1uF
402
CERM
10V
20%
2
1
R8956
10K
5%
1/16W
MF
402
2
1
R8914
1/16W
5%
390K
MF
402
N15
P13
P14
N13
H15
K15
M15
H14
K14
M14
H13
J13
L13
G15
J15
L15
G14
J14
L14
J4
J5
B14
B13
A14
H1
H2
R15
A12
P15
N14
E15
D12
D11
D14
D15
D13
G11
G12
G13
F13
F12
F11
E11
E12
E13
E14
J3
M12
M11
L12
L11
N12
N11
M10
L10
K13
K12
K11
C13
C12
C11
A13
R13
R14
P12
U8600
BCM5462
FBGA-200
OMIT
2
1
R8915
1/16W
5%
MF
402
10K
2
1
R8916
10K
1/16W
5%
MF
402
21
L8906
FERR-EMI-600-OHM
SM
21
L8909
SM
FERR-EMI-600-OHM
21
L8913
SM
FERR-EMI-600-OHM
2
1
C8917
805
CERM
10uF
6.3V
20%
2
1
C8918
CERM
805
20%
10uF
6.3V
2
1
C8919
CERM
20%
10uF
805
6.3V
2
1
C8920
5%
50V
CERM
402
22pF
2
1
C8921
402
CERM
50V
5%
22pF
2
1
R8904
1%
1/16W
MF
402
10K
ABBREV=DRAWING
TITLE=FIZZY
10389
03
051-6532
FW_TPBIAS<2>
MIN_LINE_WIDTH=10 mil
MIN_NECK_WIDTH=10 mil
FW_TPBIAS<1>
MIN_LINE_WIDTH=10 mil
MIN_NECK_WIDTH=10 mil
FW_TPBIAS<0>
MIN_LINE_WIDTH=10 mil
MIN_NECK_WIDTH=10 mil
FW_TPB2
FW
FW_TPB1
FW_TPB_P<1>
15 MIL SPACING
VESTA_CLK24M_XTALO
FW_TPA_P<1>
_PP3V3_FW
FW_DATA<3>
_PPFW_PHY
FW_CTL<0>
FW_DATA<6>
FW_DATA<4>
FW_DATA<2>
FW_DATA<0>
FW_CTL<1>
FW_DATA<7>
FW_DATA<5>
FW_DATA<1>
FW_CLK98M_PCLK
FW_PINT
FW_TPA_P<2>
FW_TPA_P<0>
FW_TPB_N<0>
TP_VESTA_TDBL<0>
TP_VESTA_TDBL<2>
_PP3V3_ENETFW
_PP2V5_ENETFW
FW_TPB_N<2>
FW_TPA_N<1>
_PP2V5_ENETFW
FW_DATA_R<1>
FW_DATA_R<0>
FW_CLK98M_LCLK
FW_LOWPWR
TP_VESTA_ESDET<1>
TP_VESTA_TEST_1394<1>
VESTA_CLK24M_XTALO_R
FW_LREQ
VESTA_CLK24M_XTALI
_PP3V3_FW
VESTA_RDAC2_PD
_PP1V2_ENETFW
_PP1V2_ENETFW
MIN_NECK_WIDTH=15 mil
MIN_LINE_WIDTH=20 mil
VOLTAGE=2.5V
PP2V5_VESTA_BIASVDD2
MIN_NECK_WIDTH=15 mil
MIN_LINE_WIDTH=20 mil
PP2V5_VESTA_XTALVDD2
VOLTAGE=2.5V
TP_VESTA_TDBL<1>
FW_TPB_P<2>
15 MIL SPACING
VESTA_CLK24M_XTAL
VESTA_CLK24M_XTALI
15 MIL SPACING
VESTA_CLK24M_XTALO_R
FW_TPB1
FW
FW_TPB0
FW_TPB_P<0>
FW_TPB1
FW
FW_TPB0
FW_TPB_N<0>
FW_TPA2
FW
FW_TPA_P<1>
FW_TPA1
FW_TPA2
FW
FW_TPA1
FW_TPA_N<1>
FW_TPB2
FW
FW_TPB_N<1>
FW_TPB1
FW_TPA3
FW
FW_TPA_P<2>
FW_TPA2
FW_TPB3
FW
FW_TPB_P<2>
FW_TPB2
FW_TPB3
FW
FW_TPB_N<2>
FW_TPB2
15 MIL SPACING
FW_CLK98M_PCLK_R
FW_TPA0FW_TPA1
FW
FW_TPA_N<0>
PP1V2_VESTA_PLLVDD2
MIN_NECK_WIDTH=15 mil
MIN_LINE_WIDTH=20 mil
VOLTAGE=1.2V
FW_TPA3
FW
FW_TPA_N<2>
FW_TPA2
FW_TPA1
FW
FW_TPA_P<0>
FW_TPA0
MIN_LINE_WIDTH=20 mil
VOLTAGE=1.2V
MIN_NECK_WIDTH=15 mil
PP1V2_VESTA_FAVDDL
MIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=15 mil
VOLTAGE=2.5V
PP2V5_VESTA_FAVDDM
MIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=15 mil
VOLTAGE=3.3V
PP3V3_VESTA_FAVDDH
I2C_VESTA_SCL
FW_TPA_N<2>
FW_TPB_P<1>
VESTA_CLK24M_XTALO
VESTA_DS_ONLY_EN0
FW_DATA_R<4>
FW_DATA_R<5>
FW_DATA_R<6>
TP_VESTA_TEST_1394<0>
FW_LPS
FW_CLK98M_PCLK_R
FW_LINKON
FW_TPA_N<0>
FW_TPB_N<1>
FW_TPB_P<0>
FW_CTL_R<1>
FW_DATA_R<7>
FW_DATA_R<3>
FW_DATA_R<2>
FW_CTL_R<0>
TP_VESTA_TVCO_24
VESTA_PWR_CLASS
FWEEPROM_WP_PD
I2C_VESTA_SDA
TP_VESTA_ESDET<0>
TP_VESTA_ESDET<2>
FW_CPS
LAST_MODIFIED=Mon Feb 23 19:08:14 2004
58
57 57
58
57
57
58
58
57
58
58
58
54
58
58
54
57
54
54
58
58
58
58
58
58
58
58
58
58
58
58
58
58
58
58
58
58
58
58
57
57
57
12
56
12
56
56
56
56
56
56
56
56
56
56
56
57
57
57
12
12
57
57
12
56
23
57
56
57
12
12
12
57
57
57
57
57
57
57
57
57
57
57
57
57
57
57
57
57
57
56
57
56
57
57
57
Preliminary
Page 58
SYM_VER-1
SYM_VER-1
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
VP
VGND
TPI#
TPO
TPI
TPO#
ALIAS
ALIAS
ALIAS
SYM_VER-2
SYM_VER-2
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
DRAWING
to apply to entire TPA/TPB XNets.
Place close to FireWire PHY
properly terminate unused signals.
connected to a beta-only device,
"Snapback" & "Late VG" Protection
appropriate connectors and/or to
assumed that FireWire PHY page will
AREF needs to be isolated from
PAGE
PHY
BY
PROVIDED
ELECTRICAL_CONSTRAINT_SET
ESD Rail
1394b implementation based on Apple
FireWire Design Guide (FWDG 0.6, 5/14/03)
provide the appropriate constraints
- _PPFW_PORT2
- _PPFW_PORT1
- _PPFW_PORT3
- _PP3V3_FW
- _GND_CHASSIS_FW_PORT2
(NONE)
(NONE)
- _GND_CHASSIS_FW_PORT3
- _GND_CHASSIS_FW_PORT1
Power aliases required by this page:
Page Notes
BOM options provided by this page:
NOTE: FireWire TPA/TPB pairs are NOT
constrained on this page. It is
Signal aliases required by this page:
necessary aliases to map the
FireWire TPA/TPB pairs to their
NOTE: This page is expected to contain the
NET_SPACING_TYPE
DIFFERENTIAL_PAIR
Cable Power
514-0057
PORT 2
(TPA+)
(TPB+)
(TPA-)
(TPB-)
logic ground for speed signaling
per 1394b V1.33
there is no DC path between them
When a bilingual device is
(to avoid ground offset issue)
all local grounds per 1394b spec
BREF should be hard-connected to
and connection detection currents
(GND_FW_PORT1_VG)
FireWire Ports
NC
OUTPUT
INPUT
TPBÂTPB<R>
TPB+
TPA+
TPA<R>
TPA-
NC
VG
(FW_PORT1_BREF)
(PPFW_PORT1_VP)
(Is this correct for Vesta?)
Termination
(PPFW_PORT2_VP)
1394A
PORT 1
BILINGUAL
Cable Power
VP
514S0058
"Snapback" & "Late VG" Protection
3rd TPA/TPB pair unused
21
L9090
400-OHM-EMI
SM-1
2
1
C9092
0.001uF
20%
50V
CERM
402
2
1
C9091
20%
10V
CERM
402
0.1uF
21
R9090
5%
1/16W
MF
402
0
2
1
C9090
0.1uF
20%
10V
CERM
402
3
1
D9090
1N5227B
SOT23
21
L9020
SM
FERR-250-OHM
2
1
C9024
50V
0.001uF
CERM
20%
402
21
F9020
SM
1.5AMP-33V
3
5
4
DP9020
BAV99DW
SOT-363
2
1
C9021
0.001uF
402
CERM
50V
20%
2
1
C9025
402
CERM
16V
20%
0.01uF
2
1
C9026
20%
16V
CERM
402
0.01uF
3
5
4
DP9021
SOT-363
BAV99DW
2
1
C9023
20%
0.001uF
402
CERM
50V
6
2
1
DP9020
SOT-363
BAV99DW
2
1
C9020
20%
50V
CERM
402
0.001uF
6
2
1
DP9021
SOT-363
BAV99DW
2
1
C9022
402
50V
20%
CERM
0.001uF
2
1
C9019
0.01uF
20%
16V
402
CERM
NO STUFF
21
L9010
FERR-250-OHM
SM
2
1
C9014
0.001uF
402
CERM
50V
20%
3
5
4
DP9010
BAV99DW
SOT-363
2
1
C9011
CERM
402
0.001uF
50V
20%
2
1
C9018
0.01uF
402
CERM
20%
NO STUFF
16V
2
1
C9017
0.01uF
NO STUFF
402
CERM
16V
20%
2
1
C9015
603-1
X7R
50V
0.1uF
10%
2
1
C9016
0.01uF
NO STUFF
16V
20%
CERM
402
2
1
R9011
1M
1/16W
MF
402
5%
2
1
R9010
805
0
FF
5%
1/10W
3
5
4
DP9011
SOT-363
BAV99DW
2
1
C9013
0.001uF
402
CERM
50V
20%
6
2
1
DP9010
SOT-363
BAV99DW
2
1
C9010
CERM
402
0.001uF
50V
20%
6
2
1
DP9011
SOT-363
BAV99DW
2
1
C9012
0.001uF
402
CERM
50V
20%
4
32
1
FL9010
2012H
90-OHM-300mA
4
32
1
FL9011
2012H
90-OHM-300mA
2
1
C9060
CERM
402
6.3V
10%
1uF
2
1
C9050
CERM
1uF
6.3V
10%
402
2
1
R9061
1%
1/16W
MF
402
56.2
2
1
R9060
56.2
402
MF
1%
1/16W
2
1
R9063
56.2
402
MF
1/16W
1%
2
1
R9062
1/16W
402
MF
1%
56.2
2
1
R9051
1%
1/16W
MF
402
56.2
2
1
R9050
56.2
1%
1/16W
MF
402
2
1
R9053
56.2
1%
1/16W
MF
402
2
1
R9052
56.2
1%
1/16W
MF
402
2
1
R9064
MF
4.99K
402
1/16W
1%
2
1
C9064
270pF
402
CERM
25V
5%
2
1
R9054
402
4.99K
1%
1/16W
MF
2
1
C9054
25V
5%
CERM
402
270pF
2
1
R9070
1K
5%
402
MF
1/16W
9
8
7
6
5
4
3
2
15
14
13
12
11
10
1
J9010
1394B-Q41
F-RT-SM
CRITICAL
1
2
5
6
3
4
10
987
J9020
1394A
F-RT-TH
CRITICAL
21
R9020
1/10W
5%
FF
805
0
3
21
4
FL9020
260-OHM-330MA
SM1
3
21
4
FL9021
260-OHM-330MA
SM1
10390
03
051-6532
ABBREV=DRAWING
TITLE=FIZZY
FW_TPB_N<1>
FW
FW_PORT1_TPA_P_FL
FW_PORT1_TPA_FL
_GND_CHASSIS_FW_PORT2
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
VOLTAGE=0V
GND_FW_PORT1_VG
MIN_NECK_WIDTH=10 mil
PPFW_PORT1_VP
VOLTAGE=33V
MIN_LINE_WIDTH=25 mil
PP3V3_FW_ESD
_PPFW_PORT1
MIN_NECK_WIDTH=10 mil
PP3V3_FW_ESD
VOLTAGE=3.3V
MIN_LINE_WIDTH=15 mil
FW_TPA_P<0>
FW_TPB2_PD
MAKE_BASE=TRUE
FW_TPB_N<2>
FW_TPB_P<2>
FW_TPBIAS<2>
FW_PORT1_TPB_N_FL
MAKE_BASE=TRUE
FW_PORT1_TPB_N
MAKE_BASE=TRUE
FW_PORT1_TPB_P
FW_PORT1_TPB_P_FL
FW
FW_PORT1_TPA_N_FL
FW_PORT1_TPA_FL
FW
FW_PORT1_TPB_P_FL
FW_PORT1_TPB_FL
FW_PORT1_TPB_N_FL
FW
FW_PORT1_TPB_FL
FW_TPBIAS<0>
FW_TPA_C<0>
MAKE_BASE=TRUE
FW_PORT2_TPA_N
MAKE_BASE=TRUE
FW_PORT2_TPB_P
MAKE_BASE=TRUE
FW_PORT2_TPB_N
MAKE_BASE=TRUE
FW_PORT1_TPA_P
MAKE_BASE=TRUE
FW_PORT1_TPA_N
MIN_NECK_WIDTH=10 mil
VOLTAGE=3.3V
PP3V3_FW_ESD_F
MIN_LINE_WIDTH=15 mil
_PP3V3_FW
FW_PORT2_TPB_N_FL
FW
FW_PORT2_TPB_FL
FW
FW_PORT2_TPB_P_FL
FW_PORT2_TPB_FL
FW
FW_PORT2_TPA_FL
FW_PORT2_TPA_P_FL
FW
FW_PORT2_TPA_N_FL
FW_PORT2_TPA_FL
MIN_NECK_WIDTH=10 mil
PPFW_PORT2_VP_F
VOLTAGE=33V
MIN_LINE_WIDTH=25 mil
MAKE_BASE=TRUE
FW_PORT2_TPA_P
FW_TPB_P<0>
FW_TPA_N<2>
FW_TPA_P<2>
FW_TPBIAS<1>
FW_PORT1_TPA_P
FW_PORT1_TPB_N
_PPFW_PORT2
FW_TPA_N<0>
FW_TPA_C<1>
MAKE_BASE=TRUE
NC_FW_TPA_N2
NO_TEST=TRUE
NC_FW_TPBIAS2
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_FW_TPA_P2
FW_PORT1_TPA_P_FL
FW_PORT1_AREF
FW_PORT1_TPA_N_FL
FW_PORT1_TPB_P
_GND_CHASSIS_FW_PORT1
FW_PORT1_TPA_N
PP3V3_FW_ESD
FW_TPB_N<0>
FW_TPB_P<1>
FW_TPA_P<1>
FW_TPA_N<1>
FW_PORT2_TPA_N_FL
FW_PORT2_TPA_N
MIN_NECK_WIDTH=10 mil
PPFW_PORT2_VP
VOLTAGE=33V
MIN_LINE_WIDTH=25 mil
GND_FW_PORT2_VG
VOLTAGE=0V
MIN_LINE_WIDTH=25 mil
MIN_NECK_WIDTH=10 mil
FW_PORT2_TPB_N_FL
FW_PORT2_TPB_N
FW_PORT2_TPA_P
FW_PORT2_TPA_P_FL
FW_PORT2_TPB_P_FL
FW_PORT2_TPB_P
LAST_MODIFIED=Mon Feb 23 19:08:30 2004
58
58
58
58
58
58
57
58
58
58
58
58
58
58
58
58
58
57
6
5
6
6
58
12
58
57
57
57
57
6
58
58
6
6
6
6
57
58
58
58
58
58
12
6
6
6
6
58
57
57
57
57
58
58
12
57
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6
6
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5
58
58
57
57
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58
6
6
6
58
58
6
6
58
Preliminary
Page 59
DM1
DP1
DM2
DP2
RSDM2
RSDP1
RSDM1
RSDP2
AVDD
DM3
DP3
RSDM3
RSDP3
PPON1
OCI2
OCI1
OCI3
OCI4
OCI5
PPON2
PPON5
PPON4
PPON3
RSDM4
DM4
DP4
DM5
DP5
RSDP4
RSDM5
RSDP5
RREF
AVSS(R)
AVSS
NC1
NC2
XT1/SCLK
XT2
VDD
VSS
(8 OF 8)
NC0
NC1
NC3
NC2
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC12
NC11
NC14
NC13
NC15
NC19
NC18
NC17
NC16
NC20
NC22
NC23
NC24
NC21
NC25
NC29
NC28
NC27
NC26
DRAWING
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
NET_PHYSICAL_TYPE
NET_SPACING_TYPE
DIFFERENTIAL_PAIR
(USB2_OC<3>)
(USB2_OC<4>)
(USB2_OC<0>)
(USB2_OC<1>)
Tie to GND at ball N11
(USB2_N<4>)
(USB2_P<4>)
(USB2_N<3>)
(USB2_P<3>)
(USB2_P<2>)
(USB2_N<2>)
(USB2_P<1>)
(USB2_N<1>)
(USB2_N<0>)
(USB2_P<0>)
USB Host Interfaces
ELECTRICAL_CONSTRAINT_SET
(USB2_OC<2>)
Y9145 LOAD CAPACITANCE IS 16pF
Master: Fizzy
Secondary Max Sep: 100 mils
Secondary Length: 500 mils
Length Tolerance: 50 mils
Line To Line: 19.5 mils
Primary Max Sep: 7.5 mils
USB2 data pairs is 90 ohms.
(NONE)
Net Spacing Type: USB2
NOTE: Target differential impedance for
BOM options provided by this page:
- _PP3V3_PWRON_USB
Power aliases required by this page:
Signal aliases required by this page:
(NONE)
Page Notes
21
R9102
36
402
MF
1/16W
1%
21
R9103
MF
402
36
1/16W
1%
21
R9104
36
1%
1/16W
MF
402
21
R9105
36
402
MF
1/16W
1%
21
R9106
1%
1/16W
MF
402
36
21
R9107
36
402
1/16W
1%
MF
21
R9108
36
402
MF
1/16W
1%
21
R9109
1%
1/16W
MF
402
36
2
1
R9138
1/16W
MF
1%
9.09K
402
2
1
C9125
20%
0.1uF
CERM
10V
402
2
1
C9124
0.1uF
20%
10V
CERM
402
2
1
C9130
402
0.1uF
CERM
10V
20%
2
1
C9129
20%
10V
CERM
0.1uF
402
12
R9139
603
MF
5%
0
1/16W
2
1
R9141
5%
1/16W
MF
402
1.5K
P8
L9
N2B2A2
B14
H14
N14
P10
N1
D8
F11
J11
G4
D12
H12
L12
M11
B13
N13
B1
L13
N8E2A3
A12
A13
P12
P3
D7H4G12
D13
F13
H13
J13
P2
C14
E14
G14
J12
K13
E13
F12
H11
K14
M14
P11
A9
C10
C11
A11
C12
B9
A10
B10
B11
B12
M6
P6
C13
E12
G13
J14
L14
D14
F14
G11
K12
M13
N11
M12
P13
N12
N10
U7700
NEC_uPD720101_USB2
FBGA
CRITICAL
1
2
R9145
402
100
5%
1/16W
MF
2
1
C9146
402
CERM
50V
5%
22pF
2
1
C9123
402
0.1uF
CERM
10V
20%
2
1
C9122
20%
10V
CERM
0.1uF
402
2
1
C9128
CERM
10V
20%
402
0.1uF
2
1
C9127
20%
10V
CERM
0.1uF
402
2
1
C9121
402
0.1uF
CERM
10V
20%
2
1
C9126
20%
10V
CERM
0.1uF
402
5678
4321
RP9110
SM1
1/16W
5%
10K
1
2
R9110
402
MF
1/16W
5%
10K
2
1
C9120
20%
CERM
805
6.3V
10uF
2
1
R9140
5%
1/16W
1.5K
402
MF
21
Y9145
CRITICAL
30.0000M
8X4.5MM-SM
2
1
C9145
402
CERM
50V
5%
22pF
T2
T1
R8
R7
R6
R5
R4
Y3
Y1
W3
W1
V4
V3
V2
V1
U6
U5
R3
U4
U3
U2
U1
T8
T7
T6
T5
T4
T3
P8
P7
U2300
OMIT
SHASTA
BGA
V1.0
2
1
C9137
CERM
10V
402
0.1uF
20%
2
1
C9136
402
CERM
10V
20%
0.1uF
C9135
20%
10uF
6.3V
CERM
805
21
L9135
FERR-EMI-100-OHM
SM
21
R9135
603
4.7
MF
1/16W
5%
21
R9100
1/16W
1%
36
MF
402
21
R9101
36
1/16W
1%
MF
402
TITLE=FIZZY
ABBREV=DRAWING
03
051-6532
91 103
NEC_NC2_PU
USB2_PWREN<0>
USB2_PWREN<2>
TP_SB_NC_R4
USB2_P<3>
USB2_N<3>
_PP3V3_PWRON_USB
PP3V3_PWRON_NEC_AVDD
VOLTAGE=3.3V
MIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=10 mil
VOLTAGE=0V
GND_NEC_AVSS_R
MIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=10 mil
USB2_N<1>
USB_NEC_N<0>
USB_NEC_P<0>
USB_NEC_N<1>
USB_NEC_P<1>
USB_NEC_N<2>
USB_NEC_P<2>
USB_NEC_N<3>
USB_NEC_P<3>
USB_NEC_N<4>
USB_NEC_P<4>
USB2_N<0>
USB2_P<0>
USB2_P<1>
USB2_P<2>
USB2_N<2>
USB2_P<4>
USB2_OC<0>
NEC_CLK30M_XT2
_PP3V3_PWRON_USB
USB2_OC<1>
USB2_OC<3>
USB2_OC<2>
USB2_OC<4>
_PP3V3_PWRON_USB
NEC_CLK30M_XT1
NEC_RREF_PD
NEC_NC1_PU
NEC_CLK30M_XT2_R
USB2_PWREN<4>
USB2_PWREN<3>
USB2_PWREN<1>
TP_SB_NC_Y1
TP_SB_NC_Y3
TP_SB_NC_W3
TP_SB_NC_W1
TP_SB_NC_V2
TP_SB_NC_V3
TP_SB_NC_V4
TP_SB_NC_V1
TP_SB_NC_U6
TP_SB_NC_U5
TP_SB_NC_U3
TP_SB_NC_U4
TP_SB_NC_U2
TP_SB_NC_T8
TP_SB_NC_U1
TP_SB_NC_T7
TP_SB_NC_T6
TP_SB_NC_T5
TP_SB_NC_T3
TP_SB_NC_T4
TP_SB_NC_T2
TP_SB_NC_T1
TP_SB_NC_R8
TP_SB_NC_R6
TP_SB_NC_R7
TP_SB_NC_R5
TP_SB_NC_R3
TP_SB_NC_P7
TP_SB_NC_P8
USB2_N<4>
USB2_1USB2_1
USB2_N<1>
USB2USB2
USB2_0USB2_0
USB2_P<0>
USB2USB2
USB2_2 USB2_2
USB2_P<2>
USB2USB2
USB2_1
USB2_P<1>
USB2_1
USB2USB2
USB2_0USB2_0
USB2_N<0>
USB2USB2
USB2_4 USB2_4
USB2_N<4>
USB2USB2
USB2_2
USB2_N<2>
USB2_2
USB2USB2
USB2_3
USB2_N<3>
USB2_3
USB2USB2
USB2_4
USB2_P<4>
USB2_4
USB2USB2
USB2_NEC_XTAL
NEC_CLK30M_XT1
15 MIL SPACING
NEC_CLK30M_XT2
15 MIL SPACING
NEC_CLK30M_XT2_R
15 MIL SPACING
USB2_3 USB2_3
USB2_P<3>
USB2USB2
LAST_MODIFIED=Mon Feb 23 19:08:38 2004
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59
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6
6
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6
6
6
6
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6
6
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6
6
6
6
6
6
6
6
6
6
6
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5
5
5
5
5
5
5
5
5
5
5
5
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5
5
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5
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5
5
5
5
5
5
5
5
5
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5
Preliminary
Page 60
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
DRAWING
516S0143
(DTR#)
(SCCA)
- _PP3V3_PWRON_MODEM
to 5V power supply output caps
(RTS#)
(TXD#)
(RXD)
Modem Interface
(NONE)
(GPIO#)
(TRXC)
MOVE TO GPIO PAGE!
Page Notes
BOM options provided by this page:
(NONE)
Signal aliases required by this page:
Spec Load: 0.5 A active, 3 mA auxiliary
Supports both The Last Dash and Q52 Modems
Removed 10uF bulk cap because modem connector is close
Modem Connector
Power aliases required by this page:
9
8 7
6 5
4 3
2
16 15
14 13
12 11
10
1
J9400
QT510166-L010
F-ST-SM1
CRITICAL
2
1
C9403
10uF
20%
6.3V
CERM
805
2
1
R9400
402
10K
MF
1/16W
5%
2
1
R9411
15K
5%
1/16W
MF
402
2
1
R9410
15K
5%
1/16W
MF
402
03
10394
051-6532
ABBREV=DRAWING
TITLE=FIZZY
USB_MODEM_P
I2S1_RESET_L
UDASH_SDOWN
I2C_MODEM_SDA
_PP5V_PWRON_MODEM
I2S1_SB_TO_DEV_DTO
I2C_MODEM_SCL
I2S1_SYNC
I2S1_DEV_TO_SB_DTI
_PP3V3_PWRON_MODEM
I2S1_BITCLK
USB_MODEM_N
MODEM_RING2SYS_L
I2S1_MCLK
LAST_MODIFIED=Mon Feb 23 19:08:46 2004
23
23 23
23
23
23
16
23
16 16
16
16
23
16
5
6
6
18
5
6
18
6
6
5
6
5
6
6
Preliminary
Page 61
DRAWING
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
AUDIO_LI_OPTICAL_PLUG_L - 100k PU on Kazoo (pg 8)
AUDIO_LO_OPTICAL_PLUG_L - 100k PU on Kazoo (pg 6)
(SLEEP_LED_GND)
516S0154
EMI Filtering
for ALL audio GPIOs.
BOM options provided by this page:
(NONE)
(NONE)
appropriate pull-ups and pull-downs
NOTE: It is considered the responsibility
of the audio section to provide the
- _PP5V_PWRON_AUDIO
Power aliases required by this page:
Signal aliases required by this page:
- _PP3V3_PWRON_AUDIO
Page Notes
Audio GPIO Pull-ups & Pull-downs
AUDIO_LO_DET_L - 100k PU on Kazoo (pg 6)
AUDIO_LO_MUTE_L - 100k PD on Kazoo (pg 6)
AUDIO_SPKR_MUTE_L - 100k PD on Kazoo (pg 5)
AUDIO_EXT_MCLK_SEL - 100k PD on Kazoo (pg 8)
AUDIO_GPIO_11 - 100k PD on Kazoo (pg 8)
I2S0_RESET_L - 100k PD on Kazoo (pg 4)
I2S2_RESET_L - 100k PD on Kazoo (pg 8)
Audio Interface
AUDIO_LI_DET_L - 100k PU on Kazoo (pg 7)
Sound Board Connector
Place shorts at 3.3V and 5V regulators
Place shorts at 3.3V and 5V regulators
This is an internal board short
This is an internal board short
This is an internal board short
Place ground short near 3.3V and 5V regulators
21
L9530
FERR-220-OHM
0402
21
L9531
0402
FERR-220-OHM
21
L9532
0402
FERR-220-OHM
21
L9533
FERR-220-OHM
0402
21
L9534
FERR-220-OHM
0402
21
L9535
FERR-220-OHM
0402
21
L9536
FERR-220-OHM
0402
9
87
65
40
4
39
3837
3635
3433
3231
30
3
29
2827
2625
2423
2221
20
2
19
1817
1615
1413
1211
10
1
4443
4241
J9500
CRITICAL
M-ST-SM1
QT500406-L111
2 1
XW9505
SM
2 1
XW9500
SM
21
L9538
0402
FERR-220-OHM
21
L9537
FERR-220-OHM
0402
21
L9539
0402
FERR-220-OHM
21
L9540
FERR-220-OHM
0402
2 1
XW9503
SM
21
R9515
NO STUFF
10K
MF
5%
1/16W
402
21
R9504
10K
MF
1/16W
5%
402
21
R9505
402
1/16W
5%
MF
10K
21
R9507
10K
MF
1/16W
5%
402
21
R9511
10K
MF
1/16W
5%
402
ABBREV=DRAWING
TITLE=LINK
03
051-6532
95 103
_PP5V_RUN_AUDIO
PP5V_PWRON_AUDIO
MIN_LINE_WIDTH=20 mil
VOLTAGE=5V
MIN_NECK_WIDTH=10 mil
_PP5V_PWRON_AUDIO
AUDIO_GPIO_11
I2S0_SB_TO_DEV_DTO_F
MIN_LINE_WIDTH=20 mil
VOLTAGE=0V
MIN_NECK_WIDTH=10 mil
GND_AUDIO
_PP3V3_PWRON_AUDIO
I2S0_BITCLK_F
I2S0_SYNC_F
AUDIO_EXT_MCLK_SEL
AUDIO_GPIO_12
AUDIO_HP_MUTE_L
AUDIO_SPKR_DET_L
_PP3V3_PWRON_AUDIO
AUDIO_HP_DET_L
I2S0_SB_TO_DEV_DTO
I2S0_SB_TO_DEV_DTO_F
I2S0_BITCLK
I2S0_DEV_TO_SB_DTI
I2S0_MCLK
I2S0_SYNC
I2S0_SYNC_F
I2S2_DEV_TO_SB_DTI
I2S2_DEV_TO_SB_DTI_F
I2S2_BITCLK
I2S2_BITCLK_F
I2S2_SYNC_F
I2S0_BITCLK_F
I2S0_RESET_L
I2S2_RESET_L_F
I2S2_RESET_L
I2S0_DEV_TO_SB_DTI_F
I2S2_DEV_TO_SB_DTI_F
I2S2_SYNC_F
I2S0_DEV_TO_SB_DTI_F
I2S0_MCLK_F
AUDIO_SPKR_MUTE_L_F
I2S2_SYNC
I2S2_BITCLK_F
MIN_LINE_WIDTH=20 mil
PP3V3_PWRON_AUDIO
VOLTAGE=3.3V
MIN_NECK_WIDTH=10 mil
I2S0_RESET_L_F
AUDIO_SPKR_MUTE_L
I2S0_MCLK_F
AUDIO_LO_MUTE_L
AUDIO_LI_DET_L
AUDIO_SPKR_MUTE_L_F
AUDIO_LO_OPTICAL_PLUG_L
AUDIO_LO_DET_L
AUDIO_LI_OPTICAL_PLUG_L
I2C_AUDIO_SDA
I2S0_RESET_L_F
I2S2_RESET_L_F
I2C_AUDIO_SCL
SLEEPLED_ANODE
LAST_MODIFIED=Mon Feb 23 19:08:54 2004
23
61
61
61
61
23
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
23
61
23
23
23
23
23
61
61
19
5
6
5
6
6
6
5
6
6
6
23
23
23
5
23
23
6
23
23
23
23
6
23
6
23
6
6
6
23
6
23
6
6
6
6
6
61
23
6
6
6
6
6
6
6
61
6
6
6
18
6
6
18
6
Preliminary
Page 62
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
DRAWING
DIFFERENTIAL_PAIR
ELECTRICAL_CONSTRAINT_SET
DIFFERENTIAL_PAIR
ELECTRICAL_CONSTRAINT_SET
NET_SPACING_TYPE
NET_SPACING_TYPE
ELECTRICAL_CONSTRAINT_SET
Electrical Constraints
DIFFERENTIAL_PAIR
No series termination on PCI signals
Electrical Constraints
NET_SPACING_TYPE
ELECTRICAL_CONSTRAINT_SET
DIFFERENTIAL_PAIR
NET_SPACING_TYPE
051-6532
03
99 103
TITLE=LINK
ABBREV=DRAWING
LAST_MODIFIED=Mon Feb 23 18:36:43 2004
RAM_CAD
RAM_DQS<1>
RAM_DQS1
SI_TMDS_DP<2>
TMDS
SI_TMDS_D2
TMDS
SI_TMDS_DN<3>
SI_TMDS_D3
SI_TMDS_DP<3>
TMDS
SI_TMDS_D3
TMDS
TMDS_DN<5>
TMDS_D5
PCI_SB_IRDY_L
PCI_TRDY_L
MAKE_BASE=TRUE
PCI_SB_AD<26>
TMDS_CONN_DP<1>
TMDS CONN_TMDS_D1
TMDS_CONN_DP<0>
TMDS CONN_TMDS_D0
TMDS
TMDS_DP<4>
TMDS_D4
TMDS
TMDS_DN<3>
TMDS_D3
TMDS_DP<3>
TMDS
TMDS_D3
TMDS_CLKN
TMDS TMDS_CLK
EI_CPU_TO_NB_CLK
EI_CPU_TO_NB_CLK_P
EI_NB_TO_CPU_CLK
EI_NB_TO_CPU_CLK_N
RAM_CLK
RAM_CLK0
RAM_CLK_A_P
RAM_CLK_A
TMDS
GPU_TMDS_DN_R<2>
GPU_TMDS_D2_R
TMDS
GPU_TMDS_CLKP_R
GPU_TMDS_CLK_R
TMDS
GPU_TMDS_DP_R<2>
GPU_TMDS_D2_R
RAM_CAD
RAM_DQS15
RAM_DQ<127..120>
RAM_CAD
RAM_DQS13
RAM_DQ<111..104>
RAM_CAD
RAM_DQS13
RAM_DQS<13>
SI_TMDS_DN<5>
TMDS
SI_TMDS_D5
GPU_TMDS_DP<0>
TMDS
GPU_TMDS_D0
GPU_TMDS_DN<0>
GPU_TMDS_D0
TMDS
TMDS_DN<4>
TMDS
TMDS_D4
TMDS_DN<1>
TMDS
TMDS_D1
TMDS_DP<1>
TMDS
TMDS_D1
TMDS_DN<0>
TMDS
TMDS_D0
TMDS
TMDS_DP<2>
TMDS_D2
TMDS_CLKP
TMDS_CLKTMDS
TMDS_DN<2>
TMDS
TMDS_D2
TMDS
TMDS_DP<0>
TMDS_D0
PCI_DEVSEL_L
MAKE_BASE=TRUE
PCI_FRAME_L
MAKE_BASE=TRUE
PCI_IRDY_L
MAKE_BASE=TRUE
PCI_STOP_L
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PCI_PAR
PCI_SB_PAR
PCI_SB_STOP_L
PCI_SB_TRDY_L
PCI_SB_FRAME_L
PCI_SB_DEVSEL_L
GPU_TMDS_CLKP
TMDS GPU_TMDS_CLK
PCI_SB_AD<31>
PCI_SB_AD<15>
PCI_SB_CBE_L<3>
PCI_SB_CBE_L<2>
PCI_SB_CBE_L<1>
PCI_SB_CBE_L<0>
PCI_CBE_L<3>
MAKE_BASE=TRUE
PCI_CBE_L<2>
MAKE_BASE=TRUE
PCI_CBE_L<1>
MAKE_BASE=TRUE
PCI_CBE_L<0>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PCI_AD<0>
PCI_AD<1>
MAKE_BASE=TRUE
PCI_AD<2>
MAKE_BASE=TRUE
PCI_AD<3>
MAKE_BASE=TRUE
PCI_SB_AD<0>
PCI_SB_AD<1>
PCI_SB_AD<2>
PCI_SB_AD<3>
PCI_SB_AD<24>
PCI_SB_AD<25>
PCI_SB_AD<27>
PCI_AD<18>
MAKE_BASE=TRUE
TMDS
SI_TMDS_DP<5>
SI_TMDS_D5
RAM_CAD
RAM_DQS<0>
RAM_DQS0
RAM_CLK_A_N_R
RAM_CLK_A_R
RAM_CLK
RAM_CLK_B_R
RAM_CLK_B_P_R
RAM_CLK
RAM_CLK_B_R
RAM_CLK_B_N_R
RAM_CLK
RAM_CLK_D_P_R
RAM_CLK_D_R
RAM_CLK
RAM_CLK_E_P_R
RAM_CLK_E_R
RAM_CLK
RAM_CLK_E_N_R
RAM_CLK_E_R
RAM_CLK
RAM_CLK_A_N
RAM_CLK_A
RAM_CLK0
RAM_CLK
RAM_CLK_B_P
RAM_CLK_B
RAM_CLK0
RAM_CLK
RAM_CLK_B_N
RAM_CLK_B
RAM_CLK0
RAM_CLK
RAM_CLK_D_N
RAM_CLK_D
RAM_CLK1
RAM_CLK
RAM_CLK_E_P
RAM_CLK_E
RAM_CLK1
RAM_CLK
RAM_CLK_E_N
RAM_CLK_E
RAM_CLK1
RAM_CLK
RAM_CKE_R<5..4>
RAM_CAD
RAM_CKE0
RAM_CKE<0>
RAM_CAD
RAM_CKE0
RAM_CKE<1>
RAM_CAD
RAM_CKE1
RAM_CKE<4>
RAM_CAD
RAM_CKE1
RAM_CKE<5>
RAM_CAD
RAM_CAD
RAM_CS_L_R<9..8>
RAM_CS0 RAM_CAD
RAM_CS_L<0>
RAM_CAD
RAM_BA_R<1..0>
RAM_CAD
RAM_RAS_L_R
RAM_CAD
RAM_CAS_L_R
RAM_BA_R<1..0>
RAM_CAD
RAM_A_CTL
RAM_RAS_L_R
RAM_CAD
RAM_A_CTL
RAM_CAS_L_R
RAM_CAD
RAM_A_CTL
RAM_WE_L_R
RAM_CAD
RAM_A_CTL
RAM_CLK_D_P
RAM_CLK_D
RAM_CLK1
RAM_CLK
RAM_CLK_A_R
RAM_CLK
RAM_CLK_A_P_R
RAM_A<13..0>
RAM_A_CTL
RAM_CAD
RAM_WE_L_R
RAM_CAD
RAM_A_R<13..0>
RAM_CAD
RAM_CS1 RAM_CAD
RAM_CS_L<9>
RAM_CS1 RAM_CAD
RAM_CS_L<8>
RAM_CS0 RAM_CAD
RAM_CS_L<1>
RAM_CS_L_R<1..0>
RAM_CAD
RAM_CAD
RAM_CKE_R<1..0>
RAM_CAD
RAM_DQ_R<127..0>
RAM_CAD
RAM_DQS_R<15..0>
RAM_CAD
RAM_DQ<23..16>
RAM_DQS2
RAM_CAD
RAM_DQS<2>
RAM_DQS2
RAM_DQ<31..24>
RAM_CAD
RAM_DQS3
RAM_DQS<4>
RAM_CAD
RAM_DQS4
RAM_DQ<39..32>
RAM_CAD
RAM_DQS4
RAM_CAD
RAM_DQS5
RAM_DQ<47..40>
RAM_DQ<63..56>
RAM_CAD
RAM_DQS7
RAM_DQS<7>
RAM_CAD
RAM_DQS7
RAM_DQS<8>
RAM_CAD
RAM_DQS8
RAM_DQS<9>
RAM_CAD
RAM_DQS9
RAM_DQ<71..64>
RAM_CAD
RAM_DQS8
RAM_CAD
RAM_DQS<10>
RAM_DQS10
RAM_CAD
RAM_DQS10
RAM_DQ<87..80>
RAM_CAD
RAM_DQS11
RAM_DQS<11>
RAM_CAD
RAM_DQS11
RAM_DQ<95..88>
RAM_CAD
RAM_DQS12
RAM_DQ<103..96>
RAM_CAD
RAM_DQS14
RAM_DQS<14>
RAM_CAD
RAM_DQS14
RAM_DQ<119..112>
RAM_CAD
RAM_DQS15
RAM_DQS<15>
EI_CPU_TO_NB_CLK
EI_CPU_TO_NB_CLK_N
EI_NB_TO_CPU_CLK
EI_NB_TO_CPU_CLK_P
EI_CPU_TO_NB_AD<43..0>
EI_CPU_NB_DATA
EI_NB_TO_CPU_AD<43..0>
EI_NB_CPU_DATA
EI_CPU_TO_NB_CAD
EI_CPU_TO_NB_SR_P<0>
EI_CPU_TO_NB_CAD
EI_CPU_TO_NB_SR_N<0>
EI_CPU_TO_NB_CAD
EI_CPU_TO_NB_SR_N<1>
EI_CPU_TO_NB_CAD
EI_CPU_TO_NB_SR_P<1>
EI_NB_TO_CPU_CAD
EI_NB_TO_CPU_SR_P<0>
EI_NB_TO_CPU_CAD
EI_NB_TO_CPU_SR_N<1>
EI_NB_TO_CPU_CAD
EI_NB_TO_CPU_SR_P<1>
EI_NB_TO_CPU_CAD
EI_NB_TO_CPU_SR_N<0>
RAM_DQ<55..48>
RAM_CAD
RAM_DQS6
RAM_CAD
RAM_DQS<5>
RAM_DQS5
RAM_DQS<3>
RAM_CAD
RAM_DQS3
TMDS_CONN_DN<0>
TMDS CONN_TMDS_D0
TMDS_CONN_DN<1>
TMDS CONN_TMDS_D1
TMDS_CONN_DN<2>
TMDS CONN_TMDS_D2
TMDS
TMDS_CONN_CLKN
CONN_TMDS_CLK
TMDS_CONN_DP<4>
TMDS CONN_TMDS_D4
TMDS_CONN_DN<4>
TMDS CONN_TMDS_D4
TMDS
SI_TMDS_DP<0>
SI_TMDS_D0
SI_TMDS_DN<2>
TMDS
SI_TMDS_D2
SI_TMDS_CLKP
TMDS
SI_TMDS_CLK
GPU_TMDS_DN<2>
TMDS
GPU_TMDS_D2
TMDS
GPU_TMDS_DP_R<0>
GPU_TMDS_D0_R
TMDS
GPU_TMDS_DN_R<0>
GPU_TMDS_D0_R
TMDS
GPU_TMDS_DN_R<1>
GPU_TMDS_D1_R
TMDS
GPU_TMDS_CLKN
GPU_TMDS_CLK
TMDS CONN_TMDS_D3
TMDS_CONN_DN<3>
TMDS_CONN_DP<3>
TMDS CONN_TMDS_D3
TMDS
SI_TMDS_CLKN
SI_TMDS_CLK
SI_TMDS_DP<4>
TMDS
SI_TMDS_D4
TMDS
SI_TMDS_DN<4>
SI_TMDS_D4
TMDS
GPU_TMDS_DP_R<1>
GPU_TMDS_D1_R
GPU_TMDS_DP<2>
TMDS
GPU_TMDS_D2
TMDS_CONN_DP<5>
TMDS CONN_TMDS_D5
TMDS
TMDS_CONN_CLKP
CONN_TMDS_CLK
TMDS
GPU_TMDS_CLKN_R
GPU_TMDS_CLK_R
RAM_CLK_D_N_R
RAM_CLK_D_R
RAM_CLK
RAM_CAD
RAM_DQS12
RAM_DQS<12>
RAM_DQ<79..72>
RAM_CAD
RAM_DQS9
RAM_DQS<6>
RAM_CAD
RAM_DQS6
RAM_CAD
RAM_DQ<15..8>
RAM_DQS1
RAM_CAD
RAM_DQ<7..0>
RAM_DQS0
GPU_TMDS_DN<1>
GPU_TMDS_D1
TMDS
GPU_TMDS_DP<1>
TMDS
GPU_TMDS_D1
TMDS
SI_TMDS_DN<1>
SI_TMDS_D1
SI_TMDS_DP<1>
TMDS
SI_TMDS_D1
SI_TMDS_DN<0>
TMDS
SI_TMDS_D0
TMDS_CONN_DN<5>
TMDS CONN_TMDS_D5
TMDS_DP<5>
TMDS
TMDS_D5
TMDS_CONN_DP<2>
TMDS CONN_TMDS_D2
PCI_SB_AD<12>
PCI_SB_AD<13>
PCI_SB_AD<14>
PCI_SB_AD<4>
PCI_SB_AD<5>
PCI_SB_AD<6>
PCI_SB_AD<7>
PCI_SB_AD<8>
PCI_SB_AD<9>
PCI_SB_AD<10>
PCI_SB_AD<11>
PCI_AD<4>
MAKE_BASE=TRUE
PCI_AD<5>
MAKE_BASE=TRUE
PCI_AD<6>
MAKE_BASE=TRUE
PCI_AD<7>
MAKE_BASE=TRUE
PCI_AD<8>
MAKE_BASE=TRUE
PCI_AD<9>
MAKE_BASE=TRUE
PCI_AD<10>
MAKE_BASE=TRUE
PCI_AD<11>
MAKE_BASE=TRUE
PCI_AD<12>
MAKE_BASE=TRUE
PCI_AD<13>
MAKE_BASE=TRUE
PCI_AD<14>
MAKE_BASE=TRUE
PCI_AD<15>
MAKE_BASE=TRUE
PCI_AD<31>
MAKE_BASE=TRUE
PCI_AD<30>
MAKE_BASE=TRUE
PCI_AD<29>
MAKE_BASE=TRUE
PCI_AD<28>
MAKE_BASE=TRUE
PCI_AD<27>
MAKE_BASE=TRUE
PCI_AD<25>
MAKE_BASE=TRUE
PCI_AD<23>
MAKE_BASE=TRUE
PCI_AD<22>
MAKE_BASE=TRUE
PCI_AD<21>
MAKE_BASE=TRUE
PCI_AD<20>
MAKE_BASE=TRUE
PCI_AD<19>
MAKE_BASE=TRUE
PCI_AD<17>
MAKE_BASE=TRUE
PCI_AD<16>
MAKE_BASE=TRUE
PCI_SB_AD<23>
PCI_SB_AD<22>
PCI_SB_AD<21>
PCI_SB_AD<20>
PCI_SB_AD<19>
PCI_SB_AD<18>
PCI_SB_AD<17>
PCI_SB_AD<16>
PCI_SB_AD<30>
PCI_SB_AD<29>
PCI_SB_AD<28>
PCI_AD<26>
MAKE_BASE=TRUE
PCI_AD<24>
MAKE_BASE=TRUE
49
49
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49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
48
48
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48
48
48
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48
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48
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Preliminary
Page 63
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
100
*** Signal Cross-Reference for the entire design ***
1V2PWRON_ITH 9B6<>
1V2PWRON_ITH_RC 9A7<
1V2PWRON_MODE 9A6<>
1V2PWRON_PGOOD 9B4<>
1V2PWRON_RT 9B6<
1V2PWRON_RUNSS 9B6<>
1V2PWRON_SGND 9A6<>
1V2PWRON_SW 9B4<>
1V2PWRON_VFB 9A5<>
1V2PWRON_VFB_DIV 9A5<
1V2RUN_EN 9A2<> 14C6<
1V5PWRON_SW 9C5<>
1V5PWRON_VFB_DIV 9B5<
1V5RUN_EN 9C2<> 14C6<
1V8RUN_CC 9D5<>
1V8RUN_PGOOD 9D5<> 14B8<
1V8RUN_SHDN_L 9D6<> 14B6<
2V5NBVCORE_STBY_L 11C3< 14D6<
2V5PWRON_SW 11C3<>
2V5RUN_EN_L 11D2<> 14C6<
2V5_BOOST_ESR 11C3<>
2V5_BST_HI 11C4<>
2V5_BST_LO 11C4<>
2V5_FB 11C4<>
2V5_FB_RC 11B2<
2V5_HI_GATE 11C4<>
2V5_INV 11C4<
2V5_INV_RC 11C1<
2V5_ITRIP 11C4<
2V5_LO_GATE 11C4<>
2V5_NBVCORE_CT 11C4<>
2V5_NBVCORE_FLT 11C4<>
2V5_NBVCORE_PGOOD 11B4<> 14B8<
2V5_NBVCORE_PWM 11B5<
2V5_NBVCORE_REF 11C4<>
2V5_NBVCORE_VCC 11D3<
2V5_NBVCORE_VREF5 11D5<>
2V5_SS 11C4<>
3V3ALL_ESR 11A3<
3V3ALL_FB 11A4<
3V3PWRON_BOOST_ESR 10D3<>
3V3PWRON_FB 10C4<>
3V3PWRON_FB_RC 10C2<
3V3PWRON_INV 10C4<
3V3PWRON_INV_RC 10C2<
3V3PWRON_LH 10C4<>
3V3PWRON_LL 10C4<>
3V3PWRON_OUT_D 10C4<>
3V3PWRON_OUT_U 10C4<>
3V3PWRON_SS 10C4<>
3V3PWRON_SW 10C2<>
3V3PWRON_TRIP 10C4<
3V3RUN_EN_L 10A4<> 14C5<
3V3_STBY_L 10D4< 14D6<
4V85ALL_ESR 11A5<
4V85ALL_FB 11A6<
5V3VPWRON_CT 10C4<>
5V3VPWRON_FLT 10C4<>
5V3VPWRON_PGOOD 10C5<> 14B8<
5V3VPWRON_REF 10C4<>
5V3VPWRON_SKIP 10C5<
5VPWRON_BOOST_ESR 10D6<>
5VPWRON_FB 10C5<>
5VPWRON_FB_RC 10C7<
5VPWRON_INV 10C5<
5VPWRON_INV_RC 10C7<
5VPWRON_LH 10C5<>
5VPWRON_LL 10C5<>
5VPWRON_OUT_D 10C5<>
5VPWRON_OUT_U 10C5<>
5VPWRON_SS 10C5<>
5VPWRON_SW 10C7<>
5VPWRON_TRIP 10C5<
5VRUNHD_EN_L 10B6<> 14D5<
5VRUN_EN_L 10A6<> 14D5<
5V_STBY_L 10D5< 14D4<
ACIN_1V20_REF 7C6<
ACIN_DIV 7C6<
ACIN_ENABLE_L 7C3<>
ACIN_ENABLE_L_DIV 7D3<>
ADAPTER_ID 6A3> 17D7<>
ADAPTER_PD 7C6<
ADC_REF 32A6<> 32B2< 32B3< 32C4<
AGP_AD<0> 36D4<> 37C7<>
AGP_AD<15..0> 36D3<
AGP_AD<1> 36D4<> 37C7<>
AGP_AD<2> 36D4<> 37C7<>
AGP_AD<3> 36D4<> 37C7<>
AGP_AD<4> 36D4<> 37C7<>
AGP_AD<5> 36D4<> 37C7<>
AGP_AD<6> 36D4<> 37C7<>
AGP_AD<7> 36D4<> 37C7<>
AGP_AD<8> 36D4<> 37C7<>
AGP_AD<9> 36D4<> 37C7<>
AGP_AD<10> 36D4<> 37C7<>
AGP_AD<11> 36C4<> 37C7<>
AGP_AD<12> 36C4<> 37C7<>
AGP_AD<13> 36C4<> 37C7<>
AGP_AD<14> 36C4<> 37C7<>
AGP_AD<15> 36C4<> 37C7<>
AGP_AD<16> 36C4<> 37C7<>
AGP_AD<31..16> 36D3<
AGP_AD<17> 36C4<> 37C7<>
AGP_AD<18> 36C4<> 37C7<>
AGP_AD<19> 36C4<> 37C7<>
AGP_AD<20> 36C4<> 37C7<>
AGP_AD<21> 36C4<> 37C7<>
AGP_AD<22> 36C4<> 37C7<>
AGP_AD<23> 36C4<> 37C7<>
AGP_AD<24> 36C4<> 37C7<>
AGP_AD<25> 36C4<> 37D7<>
AGP_AD<26> 36C4<> 37D7<>
AGP_AD<27> 36C4<> 37D7<>
AGP_AD<28> 36C4<> 37D7<>
AGP_AD<29> 36C4<> 37D7<>
AGP_AD<30> 36C4<> 37D7<>
AGP_AD<31> 36C4<> 37D7<>
AGP_AD_STBF<0> 36D3< 36D7<> 37D6<>
AGP_AD_STBF<1> 36C7<> 36D3< 37D6<>
AGP_AD_STBS<0> 36D3< 36D7<> 37D6<>
AGP_AD_STBS<1> 36C7<> 36D3< 37D6<>
AGP_ATI_MVREF 37B7<
AGP_ATI_VREFG 37B7<
AGP_BUSY_L 36C3<> 37D6>
AGP_BUSY_L_F 36C2<>
AGP_CBE<0> 36D7<> 37B7<>
AGP_CBE<1..0> 36D3<
AGP_CBE<1> 36D7<> 37B7<>
AGP_CBE<2> 36C7<> 37B7<>
AGP_CBE<3..2> 36D3<
AGP_CBE<3> 36C7<> 37C7<>
AGP_CLK66M_GPU 25B1< 25D8< 37B7<
AGP_CLK66M_GPU_R 25B4<>
AGP_CLK66M_NB 25B1< 25D8< 36B4<>
AGP_CLK66M_NB_R 25B4<>
AGP_DBI_HI 36C7<> 36D3< 37C6<>
AGP_DBI_LO 36D3< 36D7<> 37C6<>
AGP_DEVSEL 36B7<> 37B7<>
AGP_FRAME 36B7<> 37B7<>
AGP_GNT 36B7> 37B7<
AGP_INT_L 23B3<> 37B7<>
AGP_IRDY 36B7<> 37B7<>
AGP_PAR 36B7<> 37B7>
AGP_PVTREF1 36B5<>
AGP_PVTREF2 36B5<>
AGP_RBF 36B7< 37C6>
AGP_REQ 36B7< 37B7<>
AGP_SBA_L<0> 36C4< 37C6>
AGP_SBA_L<7..0> 36D3<
AGP_SBA_L<1> 36C4< 37C6>
AGP_SBA_L<2> 36C4< 37C6>
AGP_SBA_L<3> 36C4< 37C6>
AGP_SBA_L<4> 36B4< 37C6>
AGP_SBA_L<5> 36B4< 37C6>
AGP_SBA_L<6> 36B4< 37C6>
AGP_SBA_L<7> 36B4< 37C6<>
AGP_SB_STBF 36C7< 36D3< 37C6<>
AGP_SB_STBS 36C7< 36D3< 37C6<>
AGP_ST<0> 36B7> 37C6<
AGP_ST<1> 36B7> 37C6<
AGP_ST<2> 36B7> 37C6<
AGP_STOP 36B7<> 37B7<>
AGP_SUS_STAT_L_PU 37C6<
AGP_TRDY 36B7<> 37B7<>
AGP_TYPEDET_L 36B7< 37D5<
AGP_VREF_GC 36B4<> 37D5< 37D7<
AGP_WBF 36B7< 37B7>
AIRPORT_CLKRUN_L_PD 6A8> 47B5<>
ALS0_OUT 6B3> 13A7> 17C5<
ALS0_OUT_R 17D7<>
ALS1_GAIN_BOOST_L 19C7<>
ALS1_OP_IN 19D8<
ALS1_OUT 13A7> 19D5<
ALS1_OUT_DIV 19C7<
ALS1_OUT_R 19D7<>
ALS1_PHOTODIODE 19C8<>
ALS_GAIN_BOOST 6A3> 13A7> 17D6<> 19C7<>
ATI_DVOVMODE 40A3<
ATI_RSTB_MSK 37C6<>
AUDIO_EXT_MCLK_SEL 6C2> 23A3<> 61C5<>
AUDIO_GPIO_11 6C2> 23A3<> 61C5<>
AUDIO_GPIO_12 23A3<> 61B2<
AUDIO_HP_DET_L 23B3<> 61C2<
AUDIO_HP_MUTE_L 23A3<> 61B2<
AUDIO_LI_DET_L 6C2> 23B3<> 61C4<>
AUDIO_LI_OPTICAL_PLUG_L 6C2> 23B3<> 61C4<>
AUDIO_LO_DET_L 6C2> 23B3<> 61C4<>
AUDIO_LO_MUTE_L 6C2> 23A3<> 61C5<>
AUDIO_LO_OPTICAL_PLUG_L 6C2> 23B3<> 61C4<>
AUDIO_SPKR_DET_L 23A3<> 61C2<
AUDIO_SPKR_MUTE_L 6C2> 23A3<> 61C8<
AUDIO_SPKR_MUTE_L_F 61C4<> 61C7<
AVPRESET_L 27B8<> 28B3<
BATT_ACIN_L_RC 8B2<>
BATT_DET_L 6A5> 7A7<>
BATT_PBUSA_EN_L 8B2<>
BATT_PBUSB_EN_L 8C2<>
BATT_PBUS_EN_L 8B2<>
BIMODE_L 27B8<> 28C7<
BKFD_PROT_EN_L 8D8<>
BKFD_PROT_EN_L_DIV 8D8<>
BRIGHT_PWM 6A7> 42A2<>
BRIGHT_PWM_UF 42A2<>
BUSCFG0 27B6<> 28B3<
BUSCFG1 27B6<> 28B3<
BUSCFG2 27B6<> 28B3<
C1UNDGLOBAL 27B8<> 28C8<
C2UNDGLOBAL 27B8<> 28C8<
CBUS_ADDR16_R 49B4<>
CBUS_ADDR<0> 49B1<> 49B3>
CBUS_ADDR<1> 49B1<> 49B3>
CBUS_ADDR<2> 49B1<> 49B3>
CBUS_ADDR<3> 49B1<> 49B3>
CBUS_ADDR<4> 49B1<> 49B3>
CBUS_ADDR<5> 49B1<> 49B3>
CBUS_ADDR<6> 49B1<> 49B3>
CBUS_ADDR<7> 49B1<> 49B3>
CBUS_ADDR<8> 49B1<> 49B3>
CBUS_ADDR<9> 49B1<> 49B3>
CBUS_ADDR<10> 49B3> 49C1<>
CBUS_ADDR<11> 49B1<> 49B3>
CBUS_ADDR<12> 49B1<> 49B3>
CBUS_ADDR<13> 49B1<> 49B3>
CBUS_ADDR<14> 49B1<> 49B3>
CBUS_ADDR<15> 49B1<> 49B3>
CBUS_ADDR<16> 49B1<> 49B3<
CBUS_ADDR<17> 49B2<> 49B3>
CBUS_ADDR<18> 49B2<> 49B3>
CBUS_ADDR<19> 49B2<> 49B3>
CBUS_ADDR<20> 49B2<> 49B3>
CBUS_ADDR<21> 49A3> 49B2<>
CBUS_ADDR<22> 49A3> 49B2<>
CBUS_ADDR<23> 49A3> 49B2<>
CBUS_ADDR<24> 49A3> 49B2<>
CBUS_ADDR<25> 49A3> 49B2<>
CBUS_BVD1_L 49A2<> 49C3<
CBUS_BVD2_L 49B2<> 49C3<
CBUS_CE1_L 49C1<> 49C3>
CBUS_CE2_L 49B2<> 49B3>
CBUS_DATA<0> 49A1<> 49A3<>
CBUS_DATA<1> 49A1<> 49A3<>
CBUS_DATA<2> 49A1<> 49A3<>
CBUS_DATA<3> 49A3<> 49C1<>
CBUS_DATA<4> 49A3<> 49C1<>
CBUS_DATA<5> 49A3<> 49C1<>
CBUS_DATA<6> 49A3<> 49C1<>
CBUS_DATA<7> 49A3<> 49C1<>
CBUS_DATA<8> 49A2<> 49A3<>
CBUS_DATA<9> 49A2<> 49A3<>
CBUS_DATA<10> 49A2<> 49A3<>
CBUS_DATA<11> 49A3<> 49C2<>
CBUS_DATA<12> 49A3<> 49C2<>
CBUS_DATA<13> 49A3<> 49C2<>
CBUS_DATA<14> 49A3<> 49C2<>
CBUS_DATA<15> 49A3<> 49C2<>
CBUS_DET_1_L 49C2<> 49C3<
CBUS_DET_2_L 49A2<> 49C3<
CBUS_INPACK_L 49B2<> 49B3<
CBUS_IORD_L 49B2<> 49C3>
CBUS_IOWR_L 49B2<> 49C3>
CBUS_MFUNC1_PD 49A6<>
CBUS_MFUNC2_PD 49A6<>
CBUS_MFUNC3_PD 49A6<>
CBUS_MFUNC4_PD 49A6<>
CBUS_MFUNC5_PD 49A6<>
CBUS_MFUNC6_PD 49A6<>
CBUS_OE_L 49B1<> 49C3>
CBUS_PERR_L_PU 49B6<> 49C7<
CBUS_READY 49B1<> 49C3<
CBUS_REG_L 49B2<> 49C3>
CBUS_RESET_L 49B2<> 49C3>
CBUS_SERR_L_PU 49B6> 49B7<
CBUS_SUSPEND_L_PU 49A6< 49B7<
CBUS_VCCD0_L 49C4<>
CBUS_VCCD1_L 49C4<>
CBUS_VPPD0 49C4<>
CBUS_VPPD1 49C4<>
CBUS_VR_EN_L_PU 49C6< 49C7<
CBUS_VS1 49B2<> 49C3<>
CBUS_VS2 49B2<> 49C3<>
CBUS_WAIT_L 49B2<> 49B3<
CBUS_WE_L 49B1<> 49C3>
CBUS_WP_L 49A1<> 49B3<
CHGR_ACIN 8B6<
CHGR_ACIN_RC 8C4<>
CHGR_CCI 8A6<
CHGR_CCI_RC 8A8<
CHGR_CCS 8A6<
CHGR_CCS_RC 8A8<
CHGR_CCV 8A6<
CHGR_CCV_RC 8A7<
CHGR_CHARGE_EN_L 8B2<>
CHGR_CHARGE_EN_L_DIV 8C2<>
CHGR_CSIN 8A6<
CHGR_CSIP 8A6<
CHGR_CSSN 8B6<
CHGR_CSSP 8B6<
CHGR_DAC 8A5<>
CHGR_DCIN 8B6<>
CHGR_DHI 8B5<>
CHGR_DHIV 8B5<>
CHGR_DLO 8A5<>
CHGR_DLOV 8B6<>
CHGR_DLOV_RC 8B5<
CHGR_IMAX 8B6<
CHGR_PBUS_EN_L 8D3<>
CHGR_PBUS_EN_L_DIV 8D4<>
CHGR_REF 8B5<> 8B7<
CHGR_THM 8A5<
CHGR_VMAX 8B6<
CHKSTOP_L 16A5< 27A5< 27B8<>
CKTERMDIS_L 27B6<> 28A8<
CLKLVDS_LN 6B7> 39A5> 39D6> 42A4<>
CLKLVDS_LP 6B7> 39A5> 39D6> 42A4<>
CLKLVDS_UN 6A7> 39A5> 39D6> 42A4<>
CLKLVDS_UP 6A7> 39A5> 39D6> 42A4<>
CLOCK_ERROR_L 25B4>
CLOCK_RESET_L 13B3<> 25C6<
COMP_DISABLE 42C2<>
COMP_ENABLE 42C1<>
CORE_ISNS_N 32C6<
CORE_ISNS_P 32B6<
CPU1_HTBEN_R 5A7< 25B4>
CPUIMON_PHASE1_N 32C7<>
CPUIMON_PHASE1_P 32C7<>
CPUIMON_PHASE2_N 32C7<>
CPUIMON_PHASE2_P 32C7<>
CPUVCORE_BSTM 31C5<>
CPUVCORE_BSTM_R 31D5<>
CPUVCORE_BSTS 31C6<>
CPUVCORE_BSTS_R 31C5<>
CPUVCORE_CCI 31C6<>
CPUVCORE_CCI_C 31B5<
CPUVCORE_CCV 31C6<>
CPUVCORE_CM_N 31A3> 31A6<>
CPUVCORE_CM_N_R 31C7<
CPUVCORE_CM_P 31A3> 31A6< 32C8<>
CPUVCORE_CM_P_R 31C7<
CPUVCORE_CS_N 31A6<> 31B3>
CPUVCORE_CS_N_R 31C7<
CPUVCORE_CS_P 31B3< 31B3> 32C8<>
CPUVCORE_CS_P_R 31C7<
CPUVCORE_DHM 31C6<>
CPUVCORE_DHS 31C6<>
CPUVCORE_DLM 31C6<>
CPUVCORE_DLS 31C6<>
CPUVCORE_FB 31B7<
CPUVCORE_GNDS 31A6< 31B3>
CPUVCORE_GNDSENSE 31A1<>
CPUVCORE_GNDS_RC 31B7<
CPUVCORE_ILIM 31C6<>
CPUVCORE_LXM 31C5<>
CPUVCORE_LXS 31C5<>
CPUVCORE_OAIN_N 31B7<
CPUVCORE_OAIN_P 31B7<
CPUVCORE_OFS 31C7<
CPUVCORE_OVP 31C7<
CPUVCORE_SENSE 31A1<>
CPUVCORE_SHDN_L 14B6< 31C7<
CPUVCORE_SKIP_L 31C7<
CPUVCORE_SNS 31A6< 31B3>
CPUVCORE_SW_TIME 31B5<
CPUVCORE_TIME 31C6<>
CPUVCORE_TON 31C7<
CPUVCORE_VID<3> 31C7< 31D6< 31D8<
CPUVCORE_VID<4> 31C7< 31D6< 31D8<
CPUVCORE_VREF 31D7<>
CPU_APSYNC 27B6<>
CPU_AVDD_EN 14B6< 29D8<>
CPU_AVDD_NOISE 29D7<>
CPU_BYPASS_L 13C6<> 27B6<> 28B8<
CPU_CHKSTOP_L 26B5<> 27A7<
CPU_HRESET_L 13B3<> 27B8<> 28B7<
CPU_HTBEN 25B1< 27A8< 27B8<> 28A7<
CPU_HTBEN_R 25B4<>
CPU_INT_L 23B8< 27B6<> 28B7<
CPU_SENSE_I 13C6<> 32C5<
CPU_SENSE_I_R 32C6<>
CPU_SENSE_V 13C6<> 32B5<
CPU_SENSE_V_R 32B7<>
CPU_SPARE 27B6<> 28B6<
CPU_SRESET_L 23B3<> 23D2< 27B8<> 28B7<
CPU_TDIODE_NEG 32B4<>
CPU_TDIODE_POS 32B4<>
CPU_TEMP 13C6<> 32B1<
CPU_TEMP_R 32B2<>
CPU_VID<0> 13A5< 13C3<> 31C7< 31D8<
CPU_VID<1> 13A5< 13C3<> 31C7< 31D8<
CPU_VID<2> 13A5< 13C3<> 31C7< 31D8<
CPU_VID<3> 13C3<> 31D7<
CPU_VID<4> 6A1> 13C3<> 31D7<
CPU_VID<5> 6A1> 13C3<>
D3001_1 16A5<
D3002_1 16A4<
DAGND 32A6<> 32B2< 32B3< 32C2< 32C3<
32C4< 32C4< 32C6<> 32C6< 32D3<>
DAVDD 32B2< 32C3< 32C3< 32C6< 32D3<
DDC_CLK_ISO 42D4<>
DI2_L 27B8<> 28C7<
DVI_DDC_CLK 42D4<>
DVI_DDC_CLK_UF 6C7> 42C5<> 42D3<>
DVI_DDC_DATA 42C4<>
DVI_DDC_DATA_UF 6C7> 42C5<>
DVI_HPD 42C4<>
DVI_HPD_DIV 42C3<
DVI_HPD_UF 6C7> 42C3< 42C5<>
DVI_TRUN_ON_ILIM 42D2<
DVI_TURN_ON 42D2<>
DVI_TURN_ON_BASE 42D2<
EI_APCLK_VREF 26B4<
EI_CPU1_CLK_N 25D8<
EI_CPU1_CLK_N_R 5A7< 25C4>
EI_CPU1_CLK_P 25D8<
EI_CPU1_CLK_P_R 5A7< 25C4>
EI_CPU1_SYNC 25D8<
EI_CPU1_SYNC_R 5A7< 25B4>
EI_CPU_CLK_N 25C1< 25D8< 27D8<>
EI_CPU_CLK_N_C 25C4<>
EI_CPU_CLK_P 25C1< 25D8< 27D8<>
EI_CPU_CLK_P_C 25C4<>
EI_CPU_SYNC 25B1< 25D8< 27B5<
EI_CPU_SYNC_R 25B4<>
EI_CPU_TO_NB_AD<0> 26D5< 27C6<>
EI_CPU_TO_NB_AD<0..43> 26D4< 62A4>
EI_CPU_TO_NB_AD<1> 26D5< 27C6<>
EI_CPU_TO_NB_AD<2> 26C5< 27C6<>
EI_CPU_TO_NB_AD<3> 26C5< 27C6<>
EI_CPU_TO_NB_AD<4> 26C5< 27C6<>
EI_CPU_TO_NB_AD<5> 26C5< 27C6<>
EI_CPU_TO_NB_AD<6> 26C5< 27C6<>
EI_CPU_TO_NB_AD<7> 26C5< 27C6<>
EI_CPU_TO_NB_AD<8> 26C5< 27C6<>
EI_CPU_TO_NB_AD<9> 26C5< 27C6<>
EI_CPU_TO_NB_AD<10> 26C5< 27C6<>
EI_CPU_TO_NB_AD<11> 26C5< 27C6<>
EI_CPU_TO_NB_AD<12> 26C5< 27C6<>
EI_CPU_TO_NB_AD<13> 26C5< 27C6<>
EI_CPU_TO_NB_AD<14> 26C5< 27C6<>
EI_CPU_TO_NB_AD<15> 26C5< 27C6<>
EI_CPU_TO_NB_AD<16> 26C5< 27C6<>
EI_CPU_TO_NB_AD<17> 26C5< 27C6<>
EI_CPU_TO_NB_AD<18> 26C5< 27C6<>
EI_CPU_TO_NB_AD<19> 26C5< 27C6<>
EI_CPU_TO_NB_AD<20> 26C5< 27C6<>
EI_CPU_TO_NB_AD<21> 26C5< 27C6<>
EI_CPU_TO_NB_AD<22> 26C5< 27C6<>
EI_CPU_TO_NB_AD<23> 26C5< 27C6<>
EI_CPU_TO_NB_AD<24> 26C5< 27C6<>
EI_CPU_TO_NB_AD<25> 26C5< 27C6<>
EI_CPU_TO_NB_AD<26> 26C5< 27C6<>
EI_CPU_TO_NB_AD<27> 26C5< 27C6<>
EI_CPU_TO_NB_AD<28> 26B5< 27C6<>
EI_CPU_TO_NB_AD<29> 26B5< 27C6<>
EI_CPU_TO_NB_AD<30> 26B5< 27C6<>
EI_CPU_TO_NB_AD<31> 26B5< 27C6<>
EI_CPU_TO_NB_AD<32> 26B5< 27C6<>
EI_CPU_TO_NB_AD<33> 26B5< 27C6<>
EI_CPU_TO_NB_AD<34> 26B5< 27C6<>
EI_CPU_TO_NB_AD<35> 26B5< 27C6<>
EI_CPU_TO_NB_AD<36> 26B5< 27C6<>
EI_CPU_TO_NB_AD<37> 26B5< 27C6<>
EI_CPU_TO_NB_AD<38> 26B5< 27C6<>
EI_CPU_TO_NB_AD<39> 26B5< 27C6<>
EI_CPU_TO_NB_AD<40> 26B5< 27C6<>
EI_CPU_TO_NB_AD<41> 26B5< 27C6<>
EI_CPU_TO_NB_AD<42> 26B5< 27C6<>
EI_CPU_TO_NB_AD<43> 26B5< 27C6<>
EI_CPU_TO_NB_CLK_N 26D4< 26D5< 27C6<> 62A4>
EI_CPU_TO_NB_CLK_P 26D4< 26D5< 27C6<> 62A4>
EI_CPU_TO_NB_SR_N<0> 26B5< 26D4< 27B6<> 62A4>
EI_CPU_TO_NB_SR_N<1> 26B5< 26D4< 27B6<> 62A4>
EI_CPU_TO_NB_SR_P<0> 26B5< 26D4< 27B6<> 62A4>
EI_CPU_TO_NB_SR_P<1> 26B5< 26D4< 27B6<> 62A4>
EI_DISABLE 27B6<> 28B3<
EI_NB_CLK_N 25C1< 25D8< 26B3<
EI_NB_CLK_N_C 25C4<>
EI_NB_CLK_P 25C1< 25D8< 26B3<
EI_NB_CLK_P_C 25C4<>
EI_NB_SYNC 25B1< 25D8< 26B8<
EI_NB_SYNC_R 25B4<>
EI_NB_TO_CPU_AD<0> 26D7> 27C8<>
EI_NB_TO_CPU_AD<0..43> 26D4< 62A4>
EI_NB_TO_CPU_AD<1> 26D7> 27C8<>
EI_NB_TO_CPU_AD<2> 26C7> 27C8<>
EI_NB_TO_CPU_AD<3> 26C7> 27C8<>
EI_NB_TO_CPU_AD<4> 26C7> 27C8<>
EI_NB_TO_CPU_AD<5> 26C7> 27C8<>
EI_NB_TO_CPU_AD<6> 26C7> 27C8<>
EI_NB_TO_CPU_AD<7> 26C7> 27C8<>
EI_NB_TO_CPU_AD<8> 26C7> 27C8<>
EI_NB_TO_CPU_AD<9> 26C7> 27C8<>
EI_NB_TO_CPU_AD<10> 26C7> 27C8<>
EI_NB_TO_CPU_AD<11> 26C7> 27C8<>
EI_NB_TO_CPU_AD<12> 26C7> 27C8<>
EI_NB_TO_CPU_AD<13> 26C7> 27C8<>
EI_NB_TO_CPU_AD<14> 26C7> 27C8<>
EI_NB_TO_CPU_AD<15> 26C7> 27C8<>
EI_NB_TO_CPU_AD<16> 26C7> 27C8<>
EI_NB_TO_CPU_AD<17> 26C7> 27C8<>
EI_NB_TO_CPU_AD<18> 26C7> 27C8<>
EI_NB_TO_CPU_AD<19> 26C7> 27C8<>
EI_NB_TO_CPU_AD<20> 26C7> 27C8<>
EI_NB_TO_CPU_AD<21> 26C7> 27C8<>
EI_NB_TO_CPU_AD<22> 26C7> 27C8<>
EI_NB_TO_CPU_AD<23> 26C7> 27C8<>
EI_NB_TO_CPU_AD<24> 26C7> 27C8<>
EI_NB_TO_CPU_AD<25> 26C7> 27C8<>
EI_NB_TO_CPU_AD<26> 26C7> 27C8<>
EI_NB_TO_CPU_AD<27> 26C7> 27C8<>
EI_NB_TO_CPU_AD<28> 26B7> 27C8<>
EI_NB_TO_CPU_AD<29> 26B7> 27C8<>
EI_NB_TO_CPU_AD<30> 26B7> 27C8<>
EI_NB_TO_CPU_AD<31> 26B7> 27C8<>
EI_NB_TO_CPU_AD<32> 26B7> 27C8<>
EI_NB_TO_CPU_AD<33> 26B7> 27C8<>
EI_NB_TO_CPU_AD<34> 26B7> 27C8<>
EI_NB_TO_CPU_AD<35> 26B7> 27C8<>
EI_NB_TO_CPU_AD<36> 26B7> 27C8<>
EI_NB_TO_CPU_AD<37> 26B7> 27C8<>
EI_NB_TO_CPU_AD<38> 26B7> 27C8<>
EI_NB_TO_CPU_AD<39> 26B7> 27C8<>
EI_NB_TO_CPU_AD<40> 26B7> 27C8<>
EI_NB_TO_CPU_AD<41> 26B7> 27C8<>
EI_NB_TO_CPU_AD<42> 26B7> 27C8<>
EI_NB_TO_CPU_AD<43> 26B7> 27C8<>
EI_NB_TO_CPU_CLK_N 26D4< 26D7> 27C8<> 62A4>
EI_NB_TO_CPU_CLK_P 26D4< 26D7> 27C8<> 62A4>
EI_NB_TO_CPU_SR_N<0> 26B7> 26D4< 27B8<> 62A4>
EI_NB_TO_CPU_SR_N<1> 26B7> 26D4< 27B8<> 62A4>
EI_NB_TO_CPU_SR_P<0> 26B7> 26D4< 27B8<> 62A4>
EI_NB_TO_CPU_SR_P<1> 26B7> 26D4< 27B8<> 62A4>
EI_QACK_L 26B7> 27B8<>
EI_QREQ_L 26B5< 27B6<> 28C6<
EI_SE 26A7> 27B8<> 28B6<
EI_SYNC_FROM_NB 26A8< 27B5<
ENETFW_RESET 12A7< 23B3<> 23C2<
ENET_CLK25M_TX 53C6< 53D6> 54C2<
ENET_CLK25M_TX_R 54C3<> 54D6>
ENET_CLK125M_GBE_REF 53B6< 53D6> 54C2<
ENET_CLK125M_GBE_REF_R 54C3<> 54D6>
ENET_CLK125M_GTX 53B3< 53D6> 54C5<
ENET_CLK125M_GTX_R 53B4<> 53D6>
ENET_CLK125M_RX 53C6< 53D6> 54C2<
ENET_CLK125M_RX_R 54C3<> 54D6>
ENET_COL 53B6< 53D6> 54C3<>
ENET_CRS 53B6< 53D6> 54C3<>
ENET_CTAP<0> 55C5<>
ENET_CTAP<1> 55C5<>
ENET_CTAP<2> 55B5<>
ENET_CTAP<3> 55B5<>
ENET_CTAP_COMMON 55B5<
ENET_ENERGYDET 23B3<> 23C2< 54B3>
ENET_MDC 53B4> 53D6> 54C6<
ENET_MDI0 54B2<
ENET_MDI1 54B2<
ENET_MDI2 54B1<
ENET_MDI3 54B1<
ENET_MDIO 53B4<> 53D6> 54C6<>
ENET_MDI_N<0> 54B1<> 54D6> 55C6<>
ENET_MDI_N<1> 54B1<> 54D6> 55C6<>
ENET_MDI_N<2> 54B1<> 54D6> 55B6<>
ENET_MDI_N<3> 54B1<> 54D6> 55B6<>
ENET_MDI_P<0> 54B1<> 54D6> 55C6<>
ENET_MDI_P<1> 54B1<> 54D6> 55C6<>
ENET_MDI_P<2> 54B1<> 54D6> 55B6<>
ENET_MDI_P<3> 54B1<> 54D6> 55B6<>
ENET_RJ45_N<0> 55C5<> 55D6>
ENET_RJ45_N<1> 55C5<> 55D6>
ENET_RJ45_N<2> 55B5<> 55D6>
ENET_RJ45_N<3> 55B5<> 55D6>
ENET_RJ45_P<0> 55C5<> 55D6>
ENET_RJ45_P<1> 55C5<> 55D6>
ENET_RJ45_P<2> 55B5<> 55D6>
ENET_RJ45_P<3> 55B5<> 55D6>
ENET_RXD<0> 53C6< 54C3<>
ENET_RXD<7..0> 53D6>
ENET_RXD<1> 53C6< 54C3<>
ENET_RXD<2> 53B6< 54C3<>
ENET_RXD<3> 53B6< 54C3<>
ENET_RXD<4> 53B6< 54C3<>
ENET_RXD<5> 53B6< 54C3<>
ENET_RXD<6> 53B6< 54C3<>
ENET_RXD<7> 53B6< 54C3<>
ENET_RX_DV 53B6< 53D6> 54C3<>
ENET_RX_ER 53B6< 53D6> 54C3<>
ENET_TXD<0> 53C3< 54C5<
ENET_TXD<7..0> 53D6>
ENET_TXD<1> 53C3< 54C5<
ENET_TXD<2> 53C3< 54C5<
ENET_TXD<3> 53C3< 54C5<
ENET_TXD<4> 53B3< 54C5<
ENET_TXD<5> 53B3< 54C5<
ENET_TXD<6> 53B3< 54C5<
ENET_TXD<7> 53B3< 54C5<
ENET_TXD_R<0> 53C4<>
ENET_TXD_R<1> 53C4<>
ENET_TXD_R<2> 53B4<>
ENET_TXD_R<3> 53B4<>
ENET_TXD_R<4> 53B4<>
ENET_TXD_R<5> 53B4<>
ENET_TXD_R<6> 53B4<>
ENET_TXD_R<7> 53B4<>
ENET_TX_EN 53B3< 53D6> 54C5<
ENET_TX_EN_R 53B4<>
ENET_TX_ER 53B3< 53D6> 54C5<
ENET_TX_ER_R 53B4<>
EXT_LED_L 5A8<
EXT_TMDS_CLK_CMF 41B2<
EXT_TMDS_D0_CMF 41B2<
EXT_TMDS_D1_CMF 41B2<
EXT_TMDS_D2_CMF 41A2<
FAN_PWM6 13A4>
FAN_PWM7 13A4>
FAN_PWM8 13A8< 13C3<>
FAN_RPM0 6C3> 13C3<> 15C2<>
FAN_RPM1 6B3> 13C3<> 15B2<>
FAN_RPM2 5A8< 13C3<>
FAN_RPM3 13A8< 13C6<>
FAN_RPM4 13A8< 13C6<>
FAN_RPM5 13A8< 13C6<>
FAN_TACH0 6C3> 13C6<> 15C2<>
FAN_TACH1 6B3> 13C6<> 15B2<>
FAN_TACH2 5A8< 13C6<>
FAN_TACH3 5A8< 13A7< 13C6<>
FAN_TACH4 5A8< 13A7< 13C6<>
FAN_TACH5 5A8< 13A7< 13B6<>
FAN_TACH6 13A4>
FAN_TACH7 13A4>
FAN_TACH8 13A4>
FP_PWR_EN 39B6<> 42A6< 42B3<>
FP_PWR_EN_L 42B3<>
FWEEPROM_WP_PD 57A3<>
FWLM2594_VOUT 12D3<>
FWPWR_ACIN 12C7<>
FWPWR_EN 12C7<>
FWPWR_EN_L 12C6<>
FWPWR_EN_L_DIV 12C7<>
FWPWR_PWRON 12C8<> 14D4<
FWPWR_RUN 12C7<>
FW_CLK98M_LCLK 56B3< 56D6> 57C5<
FW_CLK98M_LCLK_R 56B4<> 56D6>
FW_CLK98M_PCLK 56B5<> 56D6> 57C2<
FW_CLK98M_PCLK_R 57C3<> 57D6>
FW_CPS 57C5<>
FW_CTL<0> 56B4<> 57B7<
FW_CTL<1..0> 56D6>
FW_CTL<1> 56B4<> 57B7<
FW_CTL_R<0> 57B5<>
FW_CTL_R<1> 57B5<>
FW_DATA<0> 56C4<> 57C7<
FW_DATA<7..0> 56D6>
FW_DATA<1> 56C4<> 57C7<
FW_DATA<2> 56C4<> 57C7<
FW_DATA<3> 56C4<> 57B7<
FW_DATA<4> 56B4<> 57B7<
FW_DATA<5> 56B4<> 57B7<
FW_DATA<6> 56B4<> 57B7<
FW_DATA<7> 56B4<> 57B7<
FW_DATA_R<0> 57B5<>
FW_DATA_R<1> 57B5<>
FW_DATA_R<2> 57B5<>
FW_DATA_R<3> 57B5<>
FW_DATA_R<4> 57B5<>
FW_DATA_R<5> 57B5<>
FW_DATA_R<6> 57B5<>
FW_DATA_R<7> 57B5<>
FW_LINKON 56B4< 57C3>
FW_LOWPWR 23B3<> 23C2< 57B5<
FW_LPS 56B4> 56D6> 57B5<
FW_LREQ 56B4> 56D6> 57B5<
FW_PINT 56B5< 56D6> 57C3>
FW_PORT1_AREF 6D3> 58C2<>
FW_PORT1_TPA_N 58C5> 58C5<>
FW_PORT1_TPA_N_FL 6D3> 58C2<> 58D6>
FW_PORT1_TPA_P 58C5> 58C5<>
FW_PORT1_TPA_P_FL 6D3> 58C2<> 58D6>
FW_PORT1_TPB_N 58C5> 58D5<>
FW_PORT1_TPB_N_FL 6D3> 58D2<> 58D6>
FW_PORT1_TPB_P 58C5> 58D5<>
FW_PORT1_TPB_P_FL 6D3> 58D2<> 58D6>
FW_PORT2_TPA_N 58A5<> 58C5>
FW_PORT2_TPA_N_FL 6C3> 58A3<> 58D6>
FW_PORT2_TPA_P 58B5<> 58C5>
FW_PORT2_TPA_P_FL 6C3> 58A3<> 58D6>
FW_PORT2_TPB_N 58A5<> 58C5>
FW_PORT2_TPB_N_FL 6C3> 58A3<> 58D6>
FW_PORT2_TPB_P 58A5<> 58C5>
FW_PORT2_TPB_P_FL 6C3> 58A3<> 58D6>
FW_TPA_C<0> 58C7<
FW_TPA_C<1> 58C6<
FW_TPA_N<0> 57B3<> 57D6> 58C7<
FW_TPA_N<1> 57B3<> 57D6> 58C7<
FW_TPA_N<2> 57B3<> 57D6> 58B7<
FW_TPA_P<0> 57B3<> 57D6> 58C7<
FW_TPA_P<1> 57B3<> 57D6> 58C7<
FW_TPA_P<2> 57B3<> 57D6> 58B7<
FW_TPB2_PD 58B6<
FW_TPBIAS<0> 57B3<> 58D7<
FW_TPBIAS<1> 57B3<> 58D7<
FW_TPBIAS<2> 57B3<> 58B7<
FW_TPB_N<0> 57B3<> 57D6> 58C7<
FW_TPB_N<1> 57B3<> 57D6> 58C7<
FW_TPB_N<2> 57B3<> 57D6> 58B7<
FW_TPB_P<0> 57B3<> 57D6> 58C7<
FW_TPB_P<1> 57B3<> 57D6> 58C7<
FW_TPB_P<2> 57B3<> 57D6> 58B7<
GND_2V5_NBVCORE 11B5<>
GND_5V3V 10B3<>
GND_AUDIO 6C2> 61B5<>
GND_BATT 6A5> 7B6<>
GND_CHASSIS_DVI 5A4< 17C2<>
GND_CHASSIS_INVERTER 5A4< 17B4<>
GND_CHASSIS_IO 5A4< 6C7> 17B2<>
GND_CHASSIS_LVDS 5A4< 6A7>
GND_CHGR 8A8<>
GND_CPUVCORE 31B5<>
GND_CPU_AVDD 29B5<>
GND_FW_PORT1_VG 6D3> 58C2<>
GND_FW_PORT2_VG 6C3> 58A3<>
GND_GPUVCORE 38B7<> 38C6< 38D5<
GND_NEC_AVSS_R 59A3<
GND_SMU_AVSS 13A4<> 13D4< 17C5< 17D5< 19C5<
32B1< 32B6< 32C5<
GND_SPARE_GND 29A3< 29B3<>
GND_Z_OUT 29B3< 29D2<>
GND_Z_SENSE 29B3< 29D2<>
GPOVCORE_LX_RC 38C3<
GPUL_DBG 27B6<> 28A8<
GPUPVDD_EN 14A6< 40B8<> 40D8<>
GPUPVDD_NOISE 40D7<>
GPUSS_CLK27M 37B2< 37D1<
GPUSS_S0 37B2<
GPUSS_S1 37B2<
GPUTPVDD_NOISE 40B7<>
GPUVCORE_BST 38C5<>
GPUVCORE_BST_RC 38D5<>
GPUVCORE_CNTL_L 38C7<> 39A7<>
GPUVCORE_CSN 38C7<
GPUVCORE_CSP 38C7<
GPUVCORE_DH 38C5<>
GPUVCORE_DL 38C5<>
GPUVCORE_FB 38C5<>
GPUVCORE_FBLANK 38C7<>
GPUVCORE_ILIM 38C5<>
GPUVCORE_LSAT 38C5<>
GPUVCORE_LX 38C5<>
GPUVCORE_OD 38C7<>
GPUVCORE_OVP_UVP 38C7<>
GPUVCORE_PGOOD 14A8< 38C7<>
GPUVCORE_REF 38C5<>
GPUVCORE_REFIN 38C5<
GPUVCORE_SHDN_L 14B6< 38B6<>
GPUVCORE_SKIP_L 38C7<
GPUVCORE_TON 38C7<>
GPUVDD15_EN 14A6< 39D4<>
GPU_AGP_FBSKEW<0> 39B2< 39B7<>
GPU_AGP_FBSKEW<1> 39B2< 39B7<>
GPU_AGP_TEST 37D6<
GPU_AUXWIN 39B6<>
GPU_B 39C6<> 42D8<
GPU_BUS_CFG<0> 39B2< 39B7<>
GPU_BUS_CFG<1> 39B2< 39B7<>
GPU_BUS_CFG<2> 39B2< 39B7<>
GPU_C 39B6<> 42A8<
GPU_CLK27M_DIV 37C1< 39A7<
GPU_CLK27M_OSC 37D2<
GPU_COMP 39B6<> 42A8<
GPU_DVI_DDC_CLK 39B5<> 42D3<>
GPU_DVI_DDC_DATA 39B5<> 42C3<>
GPU_DVOD<0> 39C7<> 41B8<>
GPU_DVOD<0..19> 39D6>
GPU_DVOD<1> 39C7<> 41B8<>
GPU_DVOD<2> 39C7<> 41B8<>
GPU_DVOD<3> 39C7<> 41B8<>
GPU_DVOD<4> 39C7<> 41B8<>
GPU_DVOD<5> 39C7<> 41B8<>
GPU_DVOD<6> 39C7<> 41B8<>
GPU_DVOD<7> 39C7<> 41B8<>
GPU_DVOD<8> 39C7<> 41B8<>
GPU_DVOD<9> 39C7<> 41B8<>
GPU_DVOD<10> 39C7<> 41B8<>
GPU_DVOD<11> 39C7<> 41B8<>
GPU_DVOD<12> 39C7<> 41B8<>
GPU_DVOD<13> 39C7<> 41B8<>
GPU_DVOD<14> 39C7<> 41B8<>
GPU_DVOD<15> 39C7<> 41B8<>
GPU_DVOD<16> 39B7<> 41B8<>
GPU_DVOD<17> 39B7<> 41A8<>
GPU_DVOD<18> 39B7<> 41A8<>
GPU_DVOD<19> 39B7<> 41A8<>
GPU_DVOD<20> 39B7<> 39D6> 41A8<>
GPU_DVOD<21> 39B7<> 41A8<>
GPU_DVOD<21..23> 39D6>
GPU_DVOD<22> 39B7<> 41A8<>
GPU_DVOD<23> 39B7<> 41A8<>
GPU_DVO_CLKP 39B7<> 39C6> 41A8<>
GPU_DVO_DE 39B7<> 39C6> 41A8<>
GPU_DVO_HSYNC 39B7<> 39D6> 41A8<>
GPU_DVO_VSYNC 39B7<> 39C6> 41A8<>
GPU_G 39C6<> 42D8<
GPU_GPIO8_PD 39B7<>
GPU_HPD 39B6< 42C3<>
GPU_HSYNC 39C6<> 42C8<
GPU_MEMTEST 37A6<>
GPU_MEMVMODE0 37A7<
GPU_MEMVMODE1 37A7<
GPU_OSC_OE 37D2<
GPU_R 39C6<> 42D8<
GPU_R2SET 39C6<>
GPU_RESET_L_R 37B7<
GPU_RSET 39C6<>
GPU_SSCLK_IN 37B1< 39A7<>
GPU_SSCLK_UF 37B1<>
GPU_TESTEN 39A7<
GPU_THMDIODE_N 15A8< 37A6<>
GPU_THMDIODE_P 15A8< 37A6<>
GPU_TMDS_CLKN 39A7> 41D5< 62B4>
GPU_TMDS_CLKN_R 41D2< 41D2< 41D4< 62B4>
GPU_TMDS_CLKP 39A7> 41D5< 62B4>
GPU_TMDS_CLKP_R 41D2< 41D3< 41D4< 62B4>
GPU_TMDS_DN<0> 39A7> 41D5< 62B4>
GPU_TMDS_DN<1> 39A7> 41C5< 62B4>
GPU_TMDS_DN<2> 39A7> 41C5< 62B4>
GPU_TMDS_DN_R<0> 41D2< 41D2< 41D4< 62B4>
GPU_TMDS_DN_R<1> 41C2< 41C2< 41C4< 62B4>
GPU_TMDS_DN_R<2> 41C2< 41C2< 41C4< 62B4>
GPU_TMDS_DP<0> 39A7> 41C5< 62B4>
GPU_TMDS_DP<1> 39A7> 41C5< 62B4>
GPU_TMDS_DP<2> 39A7> 41C5< 62B4>
GPU_TMDS_DP_R<0> 41C4< 41D2< 41D4< 62B4>
GPU_TMDS_DP_R<1> 41C2< 41C4< 41C4< 62B4>
GPU_TMDS_DP_R<2> 41C2< 41C4< 41C4< 62B4>
GPU_TV_GND1 42B8<>
GPU_TV_GND2 42A8<>
GPU_VSYNC 39C6<> 42C8<
GPU_X1CLK_SKEW<0> 39B2< 39B7<>
GPU_X1CLK_SKEW<1> 39B2< 39B7<>
GPU_Y 39C6<> 42A8<
HPD_4V_REF 42C3<
HPD_BASE 42C1<
HPD_ON 42C2<>
HPD_ON_RC 42C2<
HPD_PWR_SNS_EN 39A7<> 42C3<>
HPD_PWR_SW 42C2<>
HT_CLK66M_NB 25C1< 25D8< 43D6<
HT_CLK66M_NB_R 25C4<>
HT_CLK66M_SB 25B1< 25D8< 44B6<
HT_CLK66M_SB_C 44B5< 44D6>
HT_CLK66M_SB_R 25B4<>
HT_LDTREQ_L 43B3< 43C8<> 44B4<>
HT_LDTSTOP_L 43C3< 43C8<> 44B5<>
HT_NB_PVTREF0 43C5<>
HT_NB_PVTREF1 43C5<>
HT_NB_TO_SB_CAD_N<0> 43D3< 43D4> 44C5<
HT_NB_TO_SB_CAD_N<1> 43D3< 43D4> 44C5<
HT_NB_TO_SB_CAD_N<2> 43C4> 43D3< 44B5<
HT_NB_TO_SB_CAD_N<3> 43C4> 43D3< 44B5<
HT_NB_TO_SB_CAD_N<4> 43C4> 43D3< 44B5<
HT_NB_TO_SB_CAD_N<5> 43C4> 43D3< 44B5<
HT_NB_TO_SB_CAD_N<6> 43C4> 43D3< 44B5<
HT_NB_TO_SB_CAD_N<7> 43C3< 43C4> 44B5<
HT_NB_TO_SB_CAD_P<0> 43D3< 43D4> 44C5<
HT_NB_TO_SB_CAD_P<1> 43D3< 43D4> 44C5<
HT_NB_TO_SB_CAD_P<2> 43C4> 43D3< 44C5<
HT_NB_TO_SB_CAD_P<3> 43C4> 43D3< 44B5<
HT_NB_TO_SB_CAD_P<4> 43C4> 43D3< 44B5<
HT_NB_TO_SB_CAD_P<5> 43C4> 43D3< 44B5<
HT_NB_TO_SB_CAD_P<6> 43C4> 43D3< 44B5<
HT_NB_TO_SB_CAD_P<7> 43C4> 43D3< 44B5<
HT_NB_TO_SB_CLK_N 43D3< 43D4> 44C5<
HT_NB_TO_SB_CLK_P 43D3< 43D4> 44C5<
HT_NB_TO_SB_CTL_N 43C4> 43D3< 44B5<
HT_NB_TO_SB_CTL_P 43C4> 43D3< 44B5<
HT_PWROK 43C3< 43C8<> 44B5<
HT_RESET_L 43C3< 43C8<> 44B5<>
HT_SB_TO_NB_CAD_N<0> 43C3< 43D6< 44C4>
HT_SB_TO_NB_CAD_N<1> 43C3< 43D6< 44C4>
HT_SB_TO_NB_CAD_N<2> 43C3< 43C6< 44B4>
HT_SB_TO_NB_CAD_N<3> 43C3< 43C6< 44B4>
HT_SB_TO_NB_CAD_N<4> 43C3< 43C6< 44B4>
HT_SB_TO_NB_CAD_N<5> 43C3< 43C6< 44B4>
HT_SB_TO_NB_CAD_N<6> 43C3< 43C6< 44B4>
HT_SB_TO_NB_CAD_N<7> 43C3< 43C6< 44B4>
HT_SB_TO_NB_CAD_P<0> 43C3< 43D6< 44C4>
HT_SB_TO_NB_CAD_P<1> 43C3< 43D6< 44C4>
HT_SB_TO_NB_CAD_P<2> 43C3< 43C6< 44C4>
HT_SB_TO_NB_CAD_P<3> 43C3< 43C6< 44B4>
HT_SB_TO_NB_CAD_P<4> 43C3< 43C6< 44B4>
HT_SB_TO_NB_CAD_P<5> 43C3< 43C6< 44B4>
HT_SB_TO_NB_CAD_P<6> 43C3< 43C6< 44B4>
HT_SB_TO_NB_CAD_P<7> 43C3< 43C6< 44B4>
HT_SB_TO_NB_CLK_N 43C3< 43D6< 44C4>
HT_SB_TO_NB_CLK_P 43C3< 43D6< 44C4>
HT_SB_TO_NB_CTL_N 43C3< 43C6< 44B4>
HT_SB_TO_NB_CTL_P 43C3< 43C6< 44B4>
I2CGO 27B6<> 28A7<
I2C_0V546_REF 18C4<
I2C_AUDIO_SCL 18A1> 61B4<>
I2C_AUDIO_SDA 18A1> 61C4<>
I2C_BATT_SCL 7B5< 18A3>
I2C_BATT_SCL_F 7A7<>
I2C_BATT_SDA 7A5< 18A3>
I2C_BATT_SDA_F 7A7<>
I2C_CHGR_SCL 8B6< 18A3>
I2C_CHGR_SDA 8B6<> 18A3>
I2C_CLOCK_SCL 18B5> 25C6<>
I2C_CLOCK_SDA 18B5> 25C6<>
I2C_CPU_A_SCL 18C3< 18D6> 27B6<>
I2C_CPU_A_SDA 18C3< 18D6> 27B6<>
I2C_CPU_A_SDA_TO_SMU 18C6< 18D6>
I2C_DIMM_SCL 18C1> 35A3<> 35A7<>
I2C_DIMM_SDA 18C1> 35A3<> 35A7<>
I2C_DS1775_SCL 17A8<> 18A5>
I2C_DS1775_SDA 17A8<> 18A5>
I2C_MAX1989_SCL 15D3< 18A5>
I2C_MAX1989_SDA 15D3<> 18A5>
I2C_MODEM_SCL 18B1> 60B3<>
I2C_MODEM_SDA 18B1> 60B3<>
I2C_NB_A_SCL 18D3> 22D4<>
I2C_NB_A_SDA 18D3> 22C4<>
I2C_NB_B_SCL 18D2< 18D6> 22C4<>
I2C_NB_B_SDA 18D2< 18D6> 22C4<>
I2C_NB_C_SCL 18C2< 18D6> 22C4<>
I2C_NB_C_SDA 18C2< 18D6> 22C4<>
I2C_RTC_SCL 13D2<> 18B3>
I2C_RTC_SDA 13D2<> 18B3>
I2C_SB_SCL 6A2> 18B2< 18C6> 23B5<>
I2C_SB_SDA 6A2> 18B2< 18C6> 23B5<>
I2C_SMU_A_SCL_IN 13B6<> 18D6< 18D6>
I2C_SMU_A_SCL_OUT 13B6<> 18B8<> 18D6>
I2C_SMU_A_SCL_OUT_L 18C7<> 18D6<
I2C_SMU_A_SDA_IN 13B6<> 18D6> 18D6<
I2C_SMU_A_SDA_OUT 13B6<> 18B8<> 18D6>
I2C_SMU_A_SDA_OUT_L 18B7<> 18D6<
I2C_SMU_B_SCL 6A4> 13C3<> 18B7< 18D6>
I2C_SMU_B_SDA 6A4> 13C3<> 18B7< 18D6>
I2C_SMU_CPU_SCL_IN 13A5< 13C3<> 18C7< 18D6>
I2C_SMU_CPU_SCL_OUT 13B3<> 18C7< 18D6>
I2C_SMU_CPU_SDA_IN 13A5< 13C3<> 18C7< 18D6>
I2C_SMU_CPU_SDA_OUT 13C3<> 18C7< 18D6>
I2C_SMU_D_SCL 5A8< 13B6<>
I2C_SMU_D_SDA 13B6<>
I2C_SMU_E_SCL 6A5> 13C6<> 18B5<
I2C_SMU_E_SDA 6A5> 13C6<> 18B5<
I2C_VESTA_SCL 57B3<>
I2C_VESTA_SDA 57B3<>
I2S0_BITCLK 23C6< 23D6> 61B8<
I2S0_BITCLK_F 6D2> 61B7< 61C5<>
I2S0_BITCLK_R 23C5<>
I2S0_DEV_TO_SB_DTI 23C6< 23D6> 61C8<
I2S0_DEV_TO_SB_DTI_F 6D2> 61C5<> 61C7<
I2S0_MCLK 23C6< 23D6> 61C8<
I2S0_MCLK_F 6D2> 61C5<> 61C7<
I2S0_MCLK_R 23C5<>
I2S0_RESET_L 23A3<> 61B8<
I2S0_RESET_L_F 6C2> 61B7< 61C4<>
I2S0_SB_TO_DEV_DTO 23C6< 23D6> 61C8<
I2S0_SB_TO_DEV_DTO_F 6D2> 61C5<> 61C7<
I2S0_SB_TO_DEV_DTO_R 23C5<>
I2S0_SYNC 23C6< 23D6> 61C8<
I2S0_SYNC_F 6D2> 61C5<> 61C7<
I2S0_SYNC_R 23C5<>
I2S1_BITCLK 6B2> 16C4<> 23B6< 23D6> 60B5<>
I2S1_BITCLK_R 23B5<>
I2S1_DEV_TO_SB_DTI 6B2> 16C4<> 23C6< 23D6> 60B5<>
I2S1_MCLK 6B2> 16C3<> 23B6< 23D6> 60B3<>
I2S1_MCLK_R 23B5<>
I2S1_RESET_L 6B2> 16C3<> 23B6<> 23C2< 60B3<>
I2S1_SB_TO_DEV_DTO 6B2> 16C3<> 23B6< 23D6> 60C3<>
I2S1_SB_TO_DEV_DTO_R 23B5<>
I2S1_SYNC 6B2> 16C4<> 23B6< 23D6> 60C5<>
I2S1_SYNC_R 23B5<>
I2S2_BITCLK 23B6< 23D6> 61B8<
I2S2_BITCLK_F 6C2> 61B5<> 61B7<
I2S2_BITCLK_R 23B5<>
I2S2_DEV_TO_SB_DTI 23B6< 23D6> 61B8<
I2S2_DEV_TO_SB_DTI_F 6D2> 61B5<> 61B7<
I2S2_MCLK 23B6< 23D6>
I2S2_MCLK_R 23B5<>
I2S2_RESET_L 23B6<> 61A8<
I2S2_RESET_L_F 6C2> 61A7< 61C4<>
I2S2_SB_TO_DEV_DTO 23B6< 23D6>
I2S2_SB_TO_DEV_DTO_R 23B5<>
I2S2_SYNC 23B6< 23D6> 61B8<
I2S2_SYNC_F 6C2> 61B5<> 61B7<
I2S2_SYNC_R 23B5<>
INT_TMDS_CLK_CMF 41D2<
INT_TMDS_D0_CMF 41D2<
INT_TMDS_D1_CMF 41C2<
INT_TMDS_D2_CMF 41C2<
INV_ON_PWM 39B6<> 42A3<
ISNS0 32C6<
ISNS1 32C6<
JTAGMODE_SPARE2 27B6<> 28D6<
JTAG_CPU_TCK 6B1> 18C5< 27B6<> 28D4<
JTAG_CPU_TDI 6B1> 18C5< 27B6<> 28D4<
JTAG_CPU_TDO 6B1> 18C5< 27B6<> 28C7<
JTAG_CPU_TMS 6C1> 18C5< 27B6<> 28C4<
JTAG_CPU_TRST_L 6B1> 27B6<> 28C7<
JTAG_NB_TCK 6C1> 22D8<>
JTAG_NB_TDI 6D1> 22D8<>
JTAG_NB_TDO 6D1> 22D8<>
JTAG_NB_TMS 6D1> 22C8<>
JTAG_NB_TRST_L 6C1> 22C8<>
JTAG_SB_TCK 6C1> 18A7< 23A5<
JTAG_SB_TDI 6C1> 18A7< 23B5<
JTAG_SB_TDO 6C1> 23A5>
JTAG_SB_TMS 6C1> 18A7< 23A5<
JTAG_SB_TRST_L 6C1> 18A7< 23A5<
JTAG_SEL 28D4<
JTAG_VESTA_TCK 6C1> 12A6<
JTAG_VESTA_TDI 6C1> 12A6<
JTAG_VESTA_TDO 6C1> 12A6>
JTAG_VESTA_TMS 6C1> 12A6<
JTAG_VESTA_TRST_L 6C1> 12A6<
KBDLED_ANODE 6A4> 17A8<> 19A5<>
KBDLED_COMP 19A7<
KBDLED_LX 19B6<>
KBDLED_RETURN 6A4> 17A8<> 19A5<
KPGND2 29A3<>
KPVDD2 29A3<>
LCD_DIGON_L 42A6<
LCD_PWREN_L 42A5<>
LSSDMODE 27B8<> 28D6<
LSSDSCANENABLE 27B8<> 28D6<
LSSDSTOPC2ENABLE 27B8<> 28C6<
LSSDSTOPC2STARENABLE 27B8<> 28C6<
LSSDSTOPENABLE 27B8<> 28C6<
LTUSB_OVERCURRENT 5C7> 17D6<>
LTUSB_PWREN 5C7> 17D6<>
LVDS_DDC_CLK 6A7> 39B5<> 42B5<>
LVDS_DDC_DATA 6A7> 39B5<> 42B5<>
LVDS_L0N 6B7> 39A5> 39D6> 42B4<>
LVDS_L0P 6B7> 39A5> 39D6> 42B4<>
LVDS_L1N 6B7> 39A5> 39D6> 42B4<>
LVDS_L1P 6B7> 39A5> 39D6> 42B4<>
LVDS_L2N 6B7> 39A5> 39D6> 42B4<>
LVDS_L2P 6B7> 39A5> 39D6> 42B4<>
LVDS_U0N 6B7> 39B5> 39D6> 42A4<>
LVDS_U0P 6B7> 39B5> 39D6> 42A4<>
LVDS_U1N 6B7> 39A5> 39D6> 42A4<>
LVDS_U1P 6B7> 39A5> 39D6> 42A4<>
LVDS_U2N 6A7> 39A5> 39D6> 42A4<>
LVDS_U2P 6A7> 39A5> 39D6> 42A4<>
MAX1989_D1_N 15B5< 15D5< 15D6>
MAX1989_D1_P 15B5< 15D5< 15D6>
MAX1989_D2_N 15B5< 15D5< 15D6>
MAX1989_D2_P 15B5< 15D5< 15D6>
MAX1989_D3_N 15A5< 15C5< 15D6>
MAX1989_D3_P 15A5< 15D5< 15D6>
MAX1989_D4_N 15A7< 15C5< 15D6>
MAX1989_D4_P 15A7< 15C5< 15D6>
MCP_L 27A5< 27B8<>
MODEM_RING2SYS_L 6A2> 23B5<> 23D2< 60B5<>
NBVCORE_BOOST_ESR 11C6<>
NBVCORE_BST_HI 11C5<>
NBVCORE_BST_LO 11C5<>
NBVCORE_FB 11C5<>
NBVCORE_FB_RC 11B6<
NBVCORE_HI_GATE 11C5<>
NBVCORE_INV2 11C5<
NBVCORE_INV_RC 11C7<
NBVCORE_ITRIP 11C5<
NBVCORE_LO_GATE 11C5<>
NBVCORE_SS 11C5<>
NBVCORE_SW 11C6<>
NB_AGP_BUSY_L 36B4< 36C1<>
NB_AGP_GCDET_L 36B7< 37C6<>
NB_APSYNC 26B7<>
NB_INT_L 22C4<> 23B8<
NB_INT_L_R 23B7<
NB_MC_PD 22C6<>
NB_PMR_OBSV 5A8< 22C4<>
NB_PU_RESET 22B7<>
NB_PU_RST_L 22B6<> 22D4<>
NB_RESET 22B5<>
NB_RE_PD 22C6<>
NB_RI_PU 22C6<>
NB_RST_L 22B3<> 22D4<>
NB_STOP_AGP_L 36B3< 36B4>
NB_SUSPENDACK_L 13B3<> 22B1<
NB_SUSPEND_ACK 22B2<>
NB_SUSPEND_ACK_L 22B3<> 22D4<>
NB_SUSPEND_REQ_L 22D1<> 22D4<>
NB_TEST_PD 22C6<>
NB_THMI 5A8< 22C4<>
NB_THMO 5A8< 22C4<>
NB_TO_SB_INT 23A3<> 23B7<
NB_VSP_CLK_VREF 22D6<
NC_FW_TPA_N2 58B6>
NC_FW_TPA_P2 58B6>
NC_FW_TPBIAS2 58B6>
NEC_CLK30M_XT1 59A5< 59D6>
NEC_CLK30M_XT2 59A5< 59D6>
NEC_CLK30M_XT2_R 59A5<> 59D6>
NEC_CRUN_L_PD 48A5<>
NEC_INTA_L 48B5<>
NEC_INTB_L 48B5<>
NEC_INTC_L 48B5<>
NEC_LEGC_PD 48A5<
NEC_NC1_PU 59A5<>
NEC_NC2_PU 59A5<>
NEC_PERR_L_PU 48B5<>
NEC_PME_L 48A5<>
NEC_RREF_PD 59A3<>
NEC_SERR_L_PU 48B5<>
NEC_VBBRST_L 48A5<
NEC_VCCRST_L 48A5<
PATA_CS0_L 6B5> 51B1< 51D6> 52B3<>
PATA_CS0_L_R 51B2< 51B4<>
PATA_CS1_L 6B5> 51B1< 51D6> 52B2<>
PATA_CS1_L_R 51B2< 51B4<>
PATA_DA<0> 6B5> 51B1< 52B3<>
PATA_DA<3..0> 51D6>
PATA_DA<1> 6B5> 51B1< 52B3<>
PATA_DA<2> 6B5> 51B1< 52B2<>
PATA_DA_R<0> 51B2< 51C4<>
PATA_DA_R<1> 51B2< 51C4<>
PATA_DA_R<2> 51B2< 51B4<>
PATA_DD<0> 6C5> 51D1< 52B3<>
PATA_DD<6..0> 51D6>
PATA_DD<1> 6C5> 51D1< 52B3<>
PATA_DD<2> 6C5> 51D1< 52B3<>
PATA_DD<3> 6C5> 51D1< 52B3<>
PATA_DD<4> 6C5> 51D1< 52C3<>
PATA_DD<5> 6C5> 51D1< 52C3<>
PATA_DD<6> 6C5> 51C1< 52C3<>
PATA_DD<7> 6C5> 51C1< 51D6> 52C3<>
PATA_DD<8> 6C5> 51C1< 52C2<>
PATA_DD<15..8> 51D6>
PATA_DD<9> 6C5> 51C1< 52C2<>
PATA_DD<10> 6C5> 51C1< 52C2<>
PATA_DD<11> 6C5> 51C1< 52C2<>
PATA_DD<12> 6C5> 51C1< 52B2<>
PATA_DD<13> 6B5> 51C1< 52B2<>
PATA_DD<14> 6B5> 51B1< 52B2<>
PATA_DD<15> 6B5> 51B1< 52B2<>
PATA_DD_R<0> 51C4<> 51D2<
PATA_DD_R<1> 51C4<> 51D2<
PATA_DD_R<2> 51C4<> 51D2<
PATA_DD_R<3> 51C4<> 51D2<
PATA_DD_R<4> 51C4<> 51D2<
PATA_DD_R<5> 51C4<> 51D2<
PATA_DD_R<6> 51C2< 51C4<>
PATA_DD_R<7> 51C2< 51C4<>
PATA_DD_R<8> 51C2< 51C4<>
PATA_DD_R<9> 51C2< 51C4<>
PATA_DD_R<10> 51C2< 51C4<>
PATA_DD_R<11> 51C2< 51C4<>
PATA_DD_R<12> 51C2< 51C4<>
PATA_DD_R<13> 51C2< 51C4<>
PATA_DD_R<14> 51B2< 51C4<>
PATA_DD_R<15> 51B2< 51C4<>
PATA_DMACK_L 6B5> 51A1< 51D6> 52B3<>
PATA_DMACK_L_R 51A2< 51B4<>
PATA_DMARQ 51B5<> 51D6> 52B4<
PATA_DMARQ_R 6B5> 52B3<>
PATA_DSTROBE 51B5<> 51D6> 52B1<
PATA_DSTROBE_R 6B5> 52B2<>
PATA_HSTROBE 6B5> 51B1< 51D6> 52B3<>
PATA_HSTROBE_R 51B2< 51B4<>
PATA_INTRQ 51B5<> 51D6> 52B1<
PATA_INTRQ_R 6A5> 52B2<>
PATA_RESET_L 6B5> 51A1< 51D6> 52C3<>
PATA_RESET_L_R 51A2< 51B4<>
PATA_STOP 6A5> 51B1< 51D6> 52B2<>
PATA_STOP_R 51B2< 51B4<>
PCI_AD<0> 6D8> 46C5< 47B4<> 48D5<> 49C6<>
62D1>
PCI_AD<16..0> 45D6>
PCI_AD<1> 6D8> 46C5< 47B5<> 48C5<> 49C6<>
62D1>
PCI_AD<2> 6D8> 46C5< 47B4<> 48C5<> 49C6<>
62D1>
PCI_AD<3> 6D8> 46C5< 47B5<> 48C5<> 49C6<>
62D1>
PCI_AD<4> 6D8> 46C5< 47B4<> 48C5<> 49C6<>
62D1>
PCI_AD<5> 6D8> 46C5< 47B5<> 48C5<> 49C6<>
62D1>
PCI_AD<6> 6D8> 46C5< 47B4<> 48C5<> 49C6<>
62D1>
PCI_AD<7> 6D8> 46C5< 47B5<> 48C5<> 49C6<>
62D1>
PCI_AD<8> 6D8> 46B5< 47B5<> 48C5<> 49C6<>
62D1>
PCI_AD<9> 6D8> 46B5< 47B4<> 48C5<> 49C6<>
62D1>
PCI_AD<10> 6D8> 46B5< 47B5<> 48C5<> 49C6<>
62D1>
PCI_AD<11> 6C8> 46B5< 47B4<> 48C5<> 49C6<>
62C1>
PCI_AD<12> 6C8> 46B5< 47B5<> 48C5<> 49C6<>
62C1>
PCI_AD<13> 6C8> 46B5< 47B4<> 48C5<> 49C6<>
62C1>
PCI_AD<14> 6C8> 46B5< 47B5<> 48C5<> 49C6<>
62C1>
PCI_AD<15> 6C8> 46B5< 47B4<> 48C5<> 49C6<>
62C1>
PCI_AD<16> 6C8> 46B5< 47C4<> 48C5<> 49C6<>
62C1>
PCI_AD<17> 6C8> 45D6> 46B5< 47C3< 47C5<>
48C5<> 49B6<> 62C1>
PCI_AD<18> 6C8> 46B5< 47C4<> 48C5<> 49B6<>
62C1>
PCI_AD<19..18> 45D6>
PCI_AD<19> 6C8> 46B5< 47C5<> 48C5<> 49B6<>
62C1>
PCI_AD<20> 6C8> 45D6> 46B5< 47C4<> 48C5<>
49B6<> 62C1>
PCI_AD<21> 6C8> 45D6> 47C5<> 48C5<> 49B7<>
62C1>
PCI_AD<22> 6C8> 45D6> 47C4<> 48C5<> 49B6<>
62C1>
PCI_AD<23> 6C8> 45D6> 47C5<> 48C5<> 49B6<>
62C1>
PCI_AD<24> 6B8> 46C3<> 47C4<> 48C5<> 49B6<>
62C1>
PCI_AD<26..24> 45D6>
PCI_AD<25> 6B8> 46C3<> 47C5<> 48C5<> 49B6<>
62C1>
PCI_AD<26> 6B8> 46C3<> 47C4<> 48C5<> 49B6<>
62C1>
PCI_AD<27> 6B8> 45D6> 46C3<> 47C5<> 48B6<>
49B6<> 62C1>
PCI_AD<28> 6B8> 46C3<> 47C4<> 48B5<> 49B6<>
62B1>
PCI_AD<31..28> 45D6>
PCI_AD<29> 6B8> 46C3<> 47C5<> 48B5<> 49B6<>
62B1>
PCI_AD<30> 6B8> 46C3<> 47C4<> 48B5<> 49B6<>
62B1>
PCI_AD<31> 6B8> 46C3<> 47C5<> 48B5<> 49B6<>
62B1>
PCI_CBE_L<0> 6A8> 47B4<> 48B5<> 49B6<> 62B1>
PCI_CBE_L<3..0> 45D6>
PCI_CBE_L<1> 6A8> 47B5<> 48B5<> 49B6<> 62B1>
PCI_CBE_L<2> 6A8> 47B5<> 48B5<> 49B6<> 62B1>
PCI_CBE_L<3> 6A8> 47C5<> 48B5<> 49B6<> 62B1>
PCI_CBUS_RESET_L_R 49A6< 49D3<
PCI_CLK33M_AIRPORT 5D8< 6A8>
PCI_CLK33M_CBUS 5D8<
PCI_CLK33M_SB_EXT 5C8< 25C8< 45B5<
PCI_CLK33M_USB2 5D8<
PCI_CLK66M_SB_INT 25B1< 25D8< 45C5<
PCI_CLK66M_SB_INT_R 25B4<>
PCI_CLK_GP0 5D7> 25D1<
PCI_CLK_GP0_R 25C4<>
PCI_CLK_GP1 5D7> 25D1<
PCI_CLK_GP1_R 25C4<>
PCI_CLK_P1 5C7> 25B1<
PCI_CLK_P1_R 25B4<>
PCI_CLK_P3 5D7> 25B1<
PCI_CLK_P3_R 25B4<>
PCI_CLK_P4 5C7> 25B1<
PCI_CLK_P4_R 25B4<>
PCI_DEVSEL_L 6B8> 45B2< 45D6> 47B4<> 48B5<>
49A6<> 62B1>
PCI_FRAME_L 6B8> 45B2< 45D6> 47B4<> 48B5<>
49B6<> 62B1>
PCI_IRDY_L 6B8> 45B2< 45D6> 47B5<> 48B5<>
49B6<> 62B1>
PCI_PAR 6A8> 45D6> 47C4<> 48B5<> 49B6<>
62B1>
PCI_RESET_L 5D8< 5D8< 45A2<> 46B5< 47C5<>
48A7<
PCI_SB_AD<0> 45C3<> 62D2<
PCI_SB_AD<1> 45B3<> 62D2<
PCI_SB_AD<2> 45B3<> 62D2<
PCI_SB_AD<3> 45B3<> 62D2<
PCI_SB_AD<4> 45B3<> 62D2<
PCI_SB_AD<5> 45B3<> 62D2<
PCI_SB_AD<6> 45B3<> 62D2<
PCI_SB_AD<7> 45B3<> 62D2<
PCI_SB_AD<8> 45B3<> 62D2<
PCI_SB_AD<9> 45B3<> 62D2<
PCI_SB_AD<10> 45B3<> 62D2<
PCI_SB_AD<11> 45B3<> 62C2<
PCI_SB_AD<12> 45B3<> 62C2<
PCI_SB_AD<13> 45B3<> 62C2<
PCI_SB_AD<14> 45B3<> 62C2<
PCI_SB_AD<15> 45B3<> 62C2<
PCI_SB_AD<16> 45B3<> 62C2<
PCI_SB_AD<17> 45B3<> 62C2<
PCI_SB_AD<18> 45B3<> 62C2<
PCI_SB_AD<19> 45B3<> 62C2<
PCI_SB_AD<20> 45B3<> 62C2<
PCI_SB_AD<21> 45B3<> 62C2<
PCI_SB_AD<22> 45B3<> 62C2<
PCI_SB_AD<23> 45B3<> 62C2<
PCI_SB_AD<24> 45B3<> 62C2<
PCI_SB_AD<25> 45B3<> 62C2<
PCI_SB_AD<26> 45B3<> 62C2<
PCI_SB_AD<27> 45A3<> 48B6< 62C2<
PCI_SB_AD<28> 45A3<> 62B2<
PCI_SB_AD<29> 45A3<> 62B2<
PCI_SB_AD<30> 45A3<> 62B2<
PCI_SB_AD<31> 45A3<> 62B2<
PCI_SB_CBE_L<0> 45A3<> 62B2<
PCI_SB_CBE_L<1> 45A3<> 62B2<
PCI_SB_CBE_L<2> 45A3<> 62B2<
PCI_SB_CBE_L<3> 45A3<> 62B2<
PCI_SB_DEVSEL_L 45A3<> 62B2<
PCI_SB_FRAME_L 45A3<> 62B2<
PCI_SB_IRDY_L 45A3<> 62B2<
PCI_SB_PAR 45A3<> 62B2<
PCI_SB_STOP_L 45A3<> 62B2<
PCI_SB_TRDY_L 45A3<> 62B2<
PCI_SLOTA_GNT_L 6A8> 45B5<> 45B7< 47C4<>
PCI_SLOTA_IDSEL 6A8> 47C4<>
PCI_SLOTA_INT_L 6A8> 23A7< 23B3<> 47C4<>
PCI_SLOTA_REQ_L 6A8> 45B5<> 45B7< 47C5<>
PCI_SLOTB_INT_L 23B3<> 23C2<
PCI_SLOTC_INT_L 23B2< 23B3<>
PCI_SLOTD_GNT_L 45A7< 45B5<>
PCI_SLOTD_INT_L 23A7< 23B3<>
PCI_SLOTD_REQ_L 45B5<> 45B7<
PCI_SLOTE_GNT_L 23A7< 23C3<> 49A6<
PCI_SLOTE_IDSEL 49B6<
PCI_SLOTE_INT_L 23A7< 23B3<> 49A6<>
PCI_SLOTE_REQ_L 23A7< 23C3<> 49A6>
PCI_SLOTF_GNT_L 23A7< 23C3<>
PCI_SLOTF_INT_L 23B2< 23B3<>
PCI_SLOTF_REQ_L 23A7< 23C3<>
PCI_SLOTG_GNT_L 45B5<> 45B7< 48B5<
PCI_SLOTG_IDSEL 48B5<
PCI_SLOTG_INT_L 23A7< 23B3<> 48B7<
PCI_SLOTG_REQ_L 45B5<> 45B7< 48B5>
PCI_STOP_L 6B8> 45A2< 45D6> 47B4<> 48B5<>
49A6<> 62B1>
PCI_TRDY_L 6B8> 45A2< 45D6> 47B4<> 48B5<>
49A6<> 62B1>
PLLLOCK 16A6< 27B6<>
PLLMULT 27B6<> 28B3<
PLLRANGE0 27B6<> 28B3<
PLLRANGE1 27B6<> 28B3<
PLLTEST 27B6<> 28A8<
PLLTESTOUT 27B6<> 28C4<
PLS_CLK_66M_0_R 25C4<>
PLS_CLK_66M_1_R 25C4<>
PLS_EXTCLK 25B7<> 25C8<
PLS_FORCE_P0_L_R 25B6<
PLS_INTERM 25A7<
PLS_POWER_DOWN 25B6<
PLS_PRES_CML 25B6<>
PLS_REF15 25B6<>
PLS_REF25 25B6<>
PLS_REF33 25B6<>
PLS_RESET_L 25C6<
PLS_SCAN_MODE 25B6<>
PLS_X_ADDRSEL 25B6<
PLS_X_IN 25C6<
PLS_X_IN_B 25A7<
PLS_X_OUT 25C6<>
PLS_X_OUT_B 25A6<
PMU_SUSPEND_REQ 22D2<>
PP1V2_EI_CPU 5A1<> 18C3< 27A6< 27D6< 28B2<
28B5< 28D4< 28D8< 29D4<>
PP1V2_EI_NB 5B1<> 18D3< 26A8< 26B4< 26D6<
PP1V2_HT 5B1> 22D7< 43B7< 43D5<
PP1V2_PULSAR 5B1> 24A4< 24C3< 24D3<
PP1V2_PWRON_HT_PLLAVDD 44C5<
PP1V2_PWRON_HT_PLLDVDD 44D5<
PP1V2_PWRON_REG 5B5<>
PP1V2_PWRON_SB_PLL45VDD 23D4<
PP1V2_PWRON_SB_PLL49VDD 23D4<
PP1V2_RUN_GPU 5C6<> 6B1>
PP1V2_VESTA 12B7< 12C1<
PP1V2_VESTA_AVDDL 12B6<
PP1V2_VESTA_FAVDDL 57C3<
PP1V2_VESTA_PLLVDD1 54D4<
PP1V2_VESTA_PLLVDD2 57D4<
PP1V5_AGP 5B1> 36A7< 36B3< 36C2< 36D5< 37D8<
PP1V5_AGP_NECK 39A2<>
PP1V5_GPU 5A5>
PP1V5_GPU_NECK 40D2<>
PP1V5_GPU_VDD15 39A3<> 39D3<
PP1V5_GPU_VDD15_NECK 39A3<>
PP1V5_GPU_VDD15_UF 39D5<>
PP1V5_GPU_VDDP 40C6<
PP1V5_PSL_PLL1 24D7<
PP1V5_PSL_PLL2 24D7<
PP1V5_PSL_PLL3 24C7<
PP1V5_PSL_PLL4 24C7<
PP1V5_PWRON_AGP_NB_AVDD 36D7<
PP1V5_PWRON_EI_NB_AVDD 26D7<
PP1V5_PWRON_HT_NB_AVDD 43D6<
PP1V5_PWRON_NB_AVDD 5B3> 26D8< 33D5< 36D8< 43D7<
PP1V5_PWRON_RAM_NB_AVDD 33D4<
PP1V5_PWRON_REG 5B5<>
PP1V5_RUN 5B6<
PP1V8_GPU 5B5>
PP1V8_GPU_A2VDDQ 40C7<
PP1V8_GPU_AVDD 40D6<
PP1V8_GPU_LPVDD 40B6<
PP1V8_GPU_LVDDR 40A6<
PP1V8_GPU_MPVDD 40A6<
PP1V8_GPU_NECK 40D2<>
PP1V8_GPU_PVDD 14A6<> 40D6<
PP1V8_GPU_PVDD_LDO 39A3<> 40A7< 40B7< 40D7<>
PP1V8_GPU_PVDD_NECK 39A3<>
PP1V8_GPU_TPVDD 40B6<
PP1V8_GPU_TPVDD_LDO 40B7<>
PP1V8_GPU_VDDDI 40C7<
PP1V8_RUN 5B6< 5B7< 6B1>
PP1V8_RUN_LDO 5B2<>
PP1V25_PWRON_RAM_VREF_NB 33C4<>
PP2V5_GPU 5B6>
PP2V5_GPU_A2VDD 40D7<
PP2V5_GPU_LVDDR 40A6<
PP2V5_GPU_NECK2 40D2<>
PP2V5_HT 5C3> 43B8< 43C8< 43D5<
PP2V5_PWRON 6B1>
PP2V5_PWRON_RAM 5B3> 24B5< 24D3< 33A8< 33C4< 33D2<
33D8<
PP2V5_PWRON_REG 5C5<>
PP2V5_PWRON_SB_XTAL18VDD 23D4<
PP2V5_PWRON_SB_XTALVDD 23C4<
PP2V5_RUN 5B7< 5C7<
PP2V5_RUN_CPU 5C1> 29D7<
PP2V5_RUN_CPU_AVDD 29D7<>
PP2V5_RUN_CPU_AVDD_R 29D6<
PP2V5_RUN_CPU_AVDD_R_L 29D5<>
PP2V5_RUN_NECK1 39A2<>
PP2V5_SMU_VREF 5D3< 32A6>
PP2V5_VESTA 12B2< 12D1<>
PP2V5_VESTA_BIASVDD1 54D4<
PP2V5_VESTA_BIASVDD2 57D4<
PP2V5_VESTA_FAVDDM 57D3<
PP2V5_VESTA_XTALVDD1 54D4<
PP2V5_VESTA_XTALVDD2 57C4<
PP3V3_AGP 5B5> 36B2< 36B2< 36C3<
PP3V3_ALL 6A4> 6B1>
PP3V3_ALL_SMU_AVCC 13D4<
PP3V3_FW_ESD 58A6<> 58B5<> 58D5<>
PP3V3_FW_ESD_F 58A7<
PP3V3_GPU 5B5>
PP3V3_GPUSS_VDD 37C2<
PP3V3_GPU_NECK 40D2<>
PP3V3_GPU_OSC 37D2<
PP3V3_GPU_VDDR3 40B2<
PP3V3_LCD 6A7> 42B4<>
PP3V3_LCD_FET 42A4<>
PP3V3_PSL_XTAL 24B7<
PP3V3_PWRON 6A4> 17B7<> 25B7<
PP3V3_PWRON_AUDIO 6B2> 61C4<>
PP3V3_PWRON_MAX1989 15D3<
PP3V3_PWRON_NEC_AVDD 59D4<
PP3V3_PWRON_REG 5C5<>
PP3V3_RUN 5C6< 6A4> 6A8>
PP3V3_SATABR_VAA 51D4<
PP3V3_SI_AVCC 41D6<
PP3V3_SI_PVCC 41C8<>
PP3V3_SI_VCC 41C6<
PP3V3_VESTA 12A2< 12A6< 12C4< 12C6< 12D3<
12D3<>
PP3V3_VESTA_FAVDDH 57D3<
PP4V6_ALL 11A4<>
PP4V85_ALL_LDO 11A5<>
PP5V4_CHGR_LDO 8B5<>
PP5V_5V3V_VREF5 10D6<>
PP5V_CPUVCORE_VCC 31D7<
PP5V_GPUVCORE_VCC 38D7<
PP5V_INVERTER 6A7> 42B2<>
PP5V_INVERTER_F 42B2<>
PP5V_PWRON 6A4> 6B3> 11C5<
PP5V_PWRON_AUDIO 6B2> 61C5<>
PP5V_PWRON_REG 5D5<>
PP5V_RUN 6B4>
PP5V_RUN_CPU 5D1> 16B4< 16B5< 29D8<
PP5V_RUN_DDC 6C7> 42D3<> 42D5<>
PP5V_RUN_DDC_F 42D6<
PP5V_RUN_HD 5D1> 6A5>
PP18V5_ALL_4V85ALL 11A7<>
PP18V5_ALL_DCIN 6A5> 7D5<> 11B8<
PP18V5_ALL_DCIN_R 11B6<>
PP18V5_ALL_INRUSH 7D2<> 8D8<>
PP18V5_ALL_SENSE 8D7<>
PPBATT_ALL 7A5< 8C2<
PPBATT_ALL_F 6A5> 7A7<>
PPBATT_ALL_FUSEA 8C2<> 11A8<>
PPBATT_ALL_FUSEA_ZENER 11A7<>
PPBATT_ALL_FUSEB 8C1<>
PPBATT_ALL_VSNS 7A5< 8A5<
PPBATT_CHGR_OUT 8A3< 8C3<>
PPBATT_CHGR_RSNS 8B3<
PPBATT_CHGR_SW 8A4<>
PPBBATT_BOOST_OUT 11A8<> 17A4<>
PPBUS_ALL_A 5D7< 6A3> 6A7>
PPBUS_ALL_B 5D7< 6A3> 6B1>
PPBUS_FW_FUSE 12D7<>
PPBUS_INVERTER 42B1<>
PPDVO_GPU_VDDR4 40B2<
PPFW_COMBINED 12D5<> 12D5<>
PPFW_PORT1_VP 6C3> 58D2<>
PPFW_PORT2_VP 6C3> 58B3<>
PPFW_PORT2_VP_F 58B3<
PPFW_SWITCH 12D6<>
PPLOGIC_PATA 6A5> 52C4<>
PPVCC_ALL_3V5V 10D4<
PPVCC_CBUS 49B1<> 49B2<> 49D1<>
PPVCC_CBUS_XW 49C4<>
PPVCORE_CPU 5C5> 27D4< 29A4< 29D5<> 30D7<
31D4< 32B3< 32B7<>
PPVCORE_GPU 5C5> 37A6< 39A3<> 39D4<
PPVCORE_GPUFB 5B6>
PPVCORE_GPUFB_VDDM 40B6<
PPVCORE_GPUFB_VDDRH 40C6<
051-6532 03
103100
Preliminary
Page 64
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
101
PPVCORE_GPU_NECK 39A3<>
PPVCORE_GPU_REG 5C7<>
PPVCORE_GPU_VDDCI 37B5<
PPVCORE_NB_REG 5B5<>
PPVCORE_PULSAR 5B1> 24B4< 24C3< 24D3<
PPVCORE_PWRON_NB 5B3<>
PPVCORE_PWRON_PULSAR 5B3> 24B5< 24D3< 24D8<
PPVCORE_RUN_CPU 5C6> 6B1>
PPVIN_1V8RUN 9D6<
PPVIN_FWLM2594 12D4<>
PPVIO_GPUFB 40B5< 40C1<
PPVOUT_VESTA1V2 12C3<
PPVPP_CBUS 49B1<> 49B2<> 49D1<>
PROCID0 27B8<> 28A6<
PROCID1 27B8<> 28A6<
PROCID2 27B8<> 28A6<
PROC_THERM_INT_L 27B8<> 28B7<
PULSESEL0 27B8<> 28B6<
PULSESEL1 27B8<> 28B6<
PULSESEL2 27B8<> 28A6<
PWRON_REGS_PGOOD 14B7<
Q3001_B 16A6<
Q3001_C 16A5<
Q3002_B 16A5<
Q3002_E 16A5<
Q3003_B 16A4<
Q3004_D 16A4<
Q3004_G 16A4<
RAMSTOPENABLE 27B8<> 28C6<
RAM_A<0> 34C5< 35B4<> 35B5<>
RAM_A<13..0> 62A6>
RAM_A<1> 34C5< 35B3<> 35B7<>
RAM_A<2> 34C5< 35B4<> 35B5<>
RAM_A<3> 34C5< 35B3<> 35B7<>
RAM_A<4> 34C5< 35B4<> 35B5<>
RAM_A<5> 34C5< 35B3<> 35B7<>
RAM_A<6> 34C5< 35B4<> 35B5<>
RAM_A<7> 34B5< 35B3<> 35B7<>
RAM_A<8> 34B5< 35B4<> 35B5<>
RAM_A<9> 34B5< 35B3<> 35B7<>
RAM_A<10> 34B5< 35B3<> 35B7<>
RAM_A<11> 34B5< 35B4<> 35B5<>
RAM_A<12> 34B5< 35B3<> 35B7<>
RAM_A<13> 34B5< 35B3<> 35B7<>
RAM_A_R<0> 33C2> 34C6<
RAM_A_R<13..0> 62A6>
RAM_A_R<1> 33C2> 34C6<
RAM_A_R<2> 33C2> 34C6<
RAM_A_R<3> 33C2> 34C6<
RAM_A_R<4> 33C2> 34C6<
RAM_A_R<5> 33C2> 34C6<
RAM_A_R<6> 33C2> 34C6<
RAM_A_R<7> 33C2> 34B6<
RAM_A_R<8> 33C2> 34B6<
RAM_A_R<9> 33C2> 34B6<
RAM_A_R<10> 33C2> 34B6<
RAM_A_R<11> 33C2> 34B6<
RAM_A_R<12> 33C2> 34B6<
RAM_A_R<13> 33C2> 34B6<
RAM_BA<0> 34B5< 35B3<> 35B7<>
RAM_BA<1> 34B5< 35B4<> 35B5<>
RAM_BA_R<0> 33D2> 34B6<
RAM_BA_R<1..0> 62A6> 62A6>
RAM_BA_R<1> 33D2> 34B6<
RAM_CAS_L 34A5< 35B4<> 35B5<>
RAM_CAS_L_R 33D2> 34A6< 62A6> 62A6>
RAM_CKE<0> 34A8< 34D5< 35B5<> 62A6>
RAM_CKE<1> 34A8< 34D5< 35B7<> 62A6>
RAM_CKE<4> 34A8< 34D5< 35B4<> 62A6>
RAM_CKE<5> 34A8< 34C5< 35B3<> 62A6>
RAM_CKE_R<0> 33C4> 34D6<
RAM_CKE_R<1..0> 62B6>
RAM_CKE_R<1> 33C4> 34D6<
RAM_CKE_R<2> 5A7< 33C4>
RAM_CKE_R<3> 5A7< 33C4>
RAM_CKE_R<4> 33C4> 34D6<
RAM_CKE_R<5..4> 62A6>
RAM_CKE_R<5> 33C4> 34C6<
RAM_CKE_R<6> 5A7< 33C4>
RAM_CKE_R<7> 5A7< 33C4>
RAM_CLK66M_NB 25B1< 33D4<
RAM_CLK66M_NB_R 25B4<>
RAM_CLK_A_N 34C7< 35D7<> 62B6>
RAM_CLK_A_N_R 33D4<> 34C8< 62B6>
RAM_CLK_A_P 34C7< 35D7<> 62B6>
RAM_CLK_A_P_R 33D4<> 34C8< 62B6>
RAM_CLK_B_N 34C7< 35A5<> 62B6>
RAM_CLK_B_N_R 33D4<> 34C8< 62B6>
RAM_CLK_B_P 34C7< 35A5<> 62B6>
RAM_CLK_B_P_R 33D4<> 34C8< 62B6>
RAM_CLK_C_N_R 33D4<> 34D8<
RAM_CLK_C_P_R 33D4<> 34D8<
RAM_CLK_D_N 34B7< 35D3<> 62B6>
RAM_CLK_D_N_R 33C4<> 34B8< 62B6>
RAM_CLK_D_P 34C7< 35D3<> 62B6>
RAM_CLK_D_P_R 33D4<> 34C8< 62B6>
RAM_CLK_E_N 34B7< 35A4<> 62B6>
RAM_CLK_E_N_R 33C4<> 34B8< 62B6>
RAM_CLK_E_P 34B7< 35A4<> 62B6>
RAM_CLK_E_P_R 33C4<> 34B8< 62B6>
RAM_CLK_F_N_R 33C4<> 34D8<
RAM_CLK_F_P_R 33C4<> 34D8<
RAM_CS_L<0> 34D5< 35B7<> 62A6>
RAM_CS_L<1> 34D5< 35B5<> 62A6>
RAM_CS_L<8> 34D5< 35B3<> 62A6>
RAM_CS_L<9> 34D5< 35B4<> 62A6>
RAM_CS_L_R<0> 33C2> 34D6<
RAM_CS_L_R<1..0> 62A6>
RAM_CS_L_R<1> 33C2> 34D6<
RAM_CS_L_R<2> 5A7< 33C2>
RAM_CS_L_R<3> 5A7< 33C2>
RAM_CS_L_R<8> 33C2> 34D6<
RAM_CS_L_R<9..8> 62A6>
RAM_CS_L_R<9> 33C2> 34D6<
RAM_CS_L_R<10> 5A7< 33C2>
RAM_CS_L_R<11> 5A7< 33C2>
RAM_DQ<0> 34D4> 35D7<>
RAM_DQ<7..0> 62D6>
RAM_DQ<1> 34D4> 35D7<>
RAM_DQ<2> 34D4> 35D7<>
RAM_DQ<3> 34D4> 35D7<>
RAM_DQ<4> 34D4> 35D5<>
RAM_DQ<5> 34D4> 35D5<>
RAM_DQ<6> 34D4> 35D5<>
RAM_DQ<7> 34D4> 35D5<>
RAM_DQ<8> 34D4> 35D7<>
RAM_DQ<15..8> 62D6>
RAM_DQ<9> 34D4> 35D7<>
RAM_DQ<10> 34D4> 35D7<>
RAM_DQ<11> 34D4> 35D7<>
RAM_DQ<12> 34D4> 35D5<>
RAM_DQ<13> 34C4> 35D5<>
RAM_DQ<14> 34C4> 35D5<>
RAM_DQ<15> 34C4> 35D5<>
RAM_DQ<16> 34C4> 35D7<>
RAM_DQ<23..16> 62C6>
RAM_DQ<17> 34C4> 35C7<>
RAM_DQ<18> 34C4> 35C7<>
RAM_DQ<19> 34C4> 35C7<>
RAM_DQ<20> 34C4> 35D5<>
RAM_DQ<21> 34C4> 35C5<>
RAM_DQ<22> 34C4> 35C5<>
RAM_DQ<23> 34C4> 35C5<>
RAM_DQ<24> 34C4> 35C7<>
RAM_DQ<31..24> 62C6>
RAM_DQ<25> 34C4> 35C7<>
RAM_DQ<26> 34C4> 35C7<>
RAM_DQ<27> 34C4> 35C7<>
RAM_DQ<28> 34C4> 35C5<>
RAM_DQ<29> 34C4> 35C5<>
RAM_DQ<30> 34B4> 35C5<>
RAM_DQ<31> 34B4> 35C5<>
RAM_DQ<32> 34B4> 35B7<>
RAM_DQ<39..32> 62C6>
RAM_DQ<33> 34B4> 35B7<>
RAM_DQ<34> 34B4> 35B7<>
RAM_DQ<35> 34B4> 35B7<>
RAM_DQ<36> 34B4> 35B5<>
RAM_DQ<37> 34B4> 35B5<>
RAM_DQ<38> 34B4> 35B5<>
RAM_DQ<39> 34B4> 35B5<>
RAM_DQ<40> 34B4> 35B7<>
RAM_DQ<47..40> 62C6>
RAM_DQ<41> 34B4> 35B7<>
RAM_DQ<42> 34B4> 35A7<>
RAM_DQ<43> 34B4> 35A7<>
RAM_DQ<44> 34B4> 35A5<>
RAM_DQ<45> 34B4> 35B5<>
RAM_DQ<46> 34B4> 35A5<>
RAM_DQ<47> 34A4> 35B5<>
RAM_DQ<48> 34A4> 35A7<>
RAM_DQ<55..48> 62C6>
RAM_DQ<49> 34A4> 35A7<>
RAM_DQ<50> 34A4> 35A7<>
RAM_DQ<51> 34A4> 35A7<>
RAM_DQ<52> 34A4> 35A5<>
RAM_DQ<53> 34A4> 35A5<>
RAM_DQ<54> 34A4> 35A5<>
RAM_DQ<55> 34A4> 35A5<>
RAM_DQ<56> 34A4> 35A7<>
RAM_DQ<63..56> 62C6>
RAM_DQ<57> 34A4> 35A7<>
RAM_DQ<58> 34A4> 35A7<>
RAM_DQ<59> 34A4> 35A7<>
RAM_DQ<60> 34A4> 35A5<>
RAM_DQ<61> 34A4> 35A5<>
RAM_DQ<62> 34A4> 35A5<>
RAM_DQ<63> 34A4> 35A5<>
RAM_DQ<64> 34D3> 35D3<>
RAM_DQ<71..64> 62C6>
RAM_DQ<65> 34D3> 35D3<>
RAM_DQ<66> 34D3> 35D3<>
RAM_DQ<67> 34D3> 35D3<>
RAM_DQ<68> 34D3> 35D4<>
RAM_DQ<69> 34D3> 35D4<>
RAM_DQ<70> 34D3> 35D4<>
RAM_DQ<71> 34D3> 35D4<>
RAM_DQ<72> 34D3> 35D3<>
RAM_DQ<79..72> 62C6>
RAM_DQ<73> 34D3> 35D3<>
RAM_DQ<74> 34D3> 35D3<>
RAM_DQ<75> 34D3> 35D3<>
RAM_DQ<76> 34D3> 35D4<>
RAM_DQ<77> 34C3> 35D4<>
RAM_DQ<78> 34C3> 35D4<>
RAM_DQ<79> 34C3> 35D4<>
RAM_DQ<80> 34C3> 35D3<>
RAM_DQ<87..80> 62C6>
RAM_DQ<81> 34C3> 35C3<>
RAM_DQ<82> 34C3> 35C3<>
RAM_DQ<83> 34C3> 35C3<>
RAM_DQ<84> 34C3> 35D4<>
RAM_DQ<85> 34C3> 35C4<>
RAM_DQ<86> 34C3> 35C4<>
RAM_DQ<87> 34C3> 35C4<>
RAM_DQ<88> 34C3> 35C3<>
RAM_DQ<95..88> 62C6>
RAM_DQ<89> 34C3> 35C3<>
RAM_DQ<90> 34C3> 35C3<>
RAM_DQ<91> 34C3> 35C3<>
RAM_DQ<92> 34C3> 35C4<>
RAM_DQ<93> 34C3> 35C4<>
RAM_DQ<94> 34B3> 35C4<>
RAM_DQ<95> 34B3> 35C4<>
RAM_DQ<96> 34B3> 35B3<>
RAM_DQ<103..96> 62C6>
RAM_DQ<97> 34B3> 35B3<>
RAM_DQ<98> 34B3> 35B3<>
RAM_DQ<99> 34B3> 35B3<>
RAM_DQ<100> 34B3> 35B4<>
RAM_DQ<101> 34B3> 35B4<>
RAM_DQ<102> 34B3> 35B4<>
RAM_DQ<103> 34B3> 35B4<>
RAM_DQ<104> 34B3> 35B3<>
RAM_DQ<111..104> 62C6>
RAM_DQ<105> 34B3> 35B3<>
RAM_DQ<106> 34B3> 35A3<>
RAM_DQ<107> 34B3> 35A3<>
RAM_DQ<108> 34B3> 35B4<>
RAM_DQ<109> 34B3> 35B4<>
RAM_DQ<110> 34B3> 35A4<>
RAM_DQ<111> 34A3> 35A4<>
RAM_DQ<112> 34A3> 35A3<>
RAM_DQ<119..112> 62C6>
RAM_DQ<113> 34A3> 35A3<>
RAM_DQ<114> 34A3> 35A3<>
RAM_DQ<115> 34A3> 35A3<>
RAM_DQ<116> 34A3> 35A4<>
RAM_DQ<117> 34A3> 35A4<>
RAM_DQ<118> 34A3> 35A4<>
RAM_DQ<119> 34A3> 35A4<>
RAM_DQ<120> 34A3> 35A3<>
RAM_DQ<127..120> 62B6>
RAM_DQ<121> 34A3> 35A3<>
RAM_DQ<122> 34A3> 35A3<>
RAM_DQ<123> 34A3> 35A3<>
RAM_DQ<124> 34A3> 35A4<>
RAM_DQ<125> 34A3> 35A4<>
RAM_DQ<126> 34A3> 35A4<>
RAM_DQ<127> 34A3> 35A4<>
RAM_DQS<0> 34D1> 35D7<> 62D6>
RAM_DQS<1> 34D1> 35D7<> 62D6>
RAM_DQS<2> 34D1> 35C7<> 62D6>
RAM_DQS<3> 34D1> 35C7<> 62C6>
RAM_DQS<4> 34D1> 35B7<> 62C6>
RAM_DQS<5> 34D1> 35A7<> 62C6>
RAM_DQS<6> 34D1> 35A7<> 62C6>
RAM_DQS<7> 34D1> 35A7<> 62C6>
RAM_DQS<8> 34D1> 35D3<> 62C6>
RAM_DQS<9> 34D1> 35D3<> 62C6>
RAM_DQS<10> 34D1> 35C3<> 62C6>
RAM_DQS<11> 34D1> 35C3<> 62C6>
RAM_DQS<12> 34D1> 35B3<> 62C6>
RAM_DQS<13> 34C1> 35A3<> 62C6>
RAM_DQS<14> 34C1> 35A3<> 62C6>
RAM_DQS<15> 34C1> 35A3<> 62C6>
RAM_DQS_R<0> 33B2<> 34D2<
RAM_DQS_R<15..0> 62D6>
RAM_DQS_R<1> 33B2<> 34D2<
RAM_DQS_R<2> 33B2<> 34D2<
RAM_DQS_R<3> 33B2<> 34D2<
RAM_DQS_R<4> 33B2<> 34D2<
RAM_DQS_R<5> 33B2<> 34D2<
RAM_DQS_R<6> 33B2<> 34D2<
RAM_DQS_R<7> 33B2<> 34D2<
RAM_DQS_R<8> 33B2<> 34D2<
RAM_DQS_R<9> 33B2<> 34D2<
RAM_DQS_R<10> 33B2<> 34D2<
RAM_DQS_R<11> 33B2<> 34D2<
RAM_DQS_R<12> 33B2<> 34D2<
RAM_DQS_R<13> 33B2<> 34C2<
RAM_DQS_R<14> 33B2<> 34C2<
RAM_DQS_R<15> 33B2<> 34C2<
RAM_DQ_R<0> 33D8<> 34D5<
RAM_DQ_R<127..0> 62D6>
RAM_DQ_R<1> 33D8<> 34D5<
RAM_DQ_R<2> 33D8<> 34D5<
RAM_DQ_R<3> 33D8<> 34D5<
RAM_DQ_R<4> 33D8<> 34D5<
RAM_DQ_R<5> 33D8<> 34D5<
RAM_DQ_R<6> 33D8<> 34D5<
RAM_DQ_R<7> 33D8<> 34D5<
RAM_DQ_R<8> 33D8<> 34D5<
RAM_DQ_R<9> 33D8<> 34D5<
RAM_DQ_R<10> 33D8<> 34D5<
RAM_DQ_R<11> 33C8<> 34D5<
RAM_DQ_R<12> 33C8<> 34D5<
RAM_DQ_R<13> 33C8<> 34C5<
RAM_DQ_R<14> 33C8<> 34C5<
RAM_DQ_R<15> 33C8<> 34C5<
RAM_DQ_R<16> 33C8<> 34C5<
RAM_DQ_R<17> 33C8<> 34C5<
RAM_DQ_R<18> 33C8<> 34C5<
RAM_DQ_R<19> 33C8<> 34C5<
RAM_DQ_R<20> 33C8<> 34C5<
RAM_DQ_R<21> 33C8<> 34C5<
RAM_DQ_R<22> 33C8<> 34C5<
RAM_DQ_R<23> 33C8<> 34C5<
RAM_DQ_R<24> 33C8<> 34C5<
RAM_DQ_R<25> 33C8<> 34C5<
RAM_DQ_R<26> 33C8<> 34C5<
RAM_DQ_R<27> 33C8<> 34C5<
RAM_DQ_R<28> 33C8<> 34C5<
RAM_DQ_R<29> 33C8<> 34C5<
RAM_DQ_R<30> 33C8<> 34B5<
RAM_DQ_R<31> 33C8<> 34B5<
RAM_DQ_R<32> 33C8<> 34B5<
RAM_DQ_R<33> 33C8<> 34B5<
RAM_DQ_R<34> 33C8<> 34B5<
RAM_DQ_R<35> 33C8<> 34B5<
RAM_DQ_R<36> 33C8<> 34B5<
RAM_DQ_R<37> 33B8<> 34B5<
RAM_DQ_R<38> 33B8<> 34B5<
RAM_DQ_R<39> 33B8<> 34B5<
RAM_DQ_R<40> 33B8<> 34B5<
RAM_DQ_R<41> 33B8<> 34B5<
RAM_DQ_R<42> 33B8<> 34B5<
RAM_DQ_R<43> 33B8<> 34B5<
RAM_DQ_R<44> 33B8<> 34B5<
RAM_DQ_R<45> 33B8<> 34B5<
RAM_DQ_R<46> 33B8<> 34B5<
RAM_DQ_R<47> 33B8<> 34A5<
RAM_DQ_R<48> 33B8<> 34A5<
RAM_DQ_R<49> 33B8<> 34A5<
RAM_DQ_R<50> 33B8<> 34A5<
RAM_DQ_R<51> 33B8<> 34A5<
RAM_DQ_R<52> 33B8<> 34A5<
RAM_DQ_R<53> 33B8<> 34A5<
RAM_DQ_R<54> 33B8<> 34A5<
RAM_DQ_R<55> 33B8<> 34A5<
RAM_DQ_R<56> 33B8<> 34A5<
RAM_DQ_R<57> 33B8<> 34A5<
RAM_DQ_R<58> 33B8<> 34A5<
RAM_DQ_R<59> 33B8<> 34A5<
RAM_DQ_R<60> 33B8<> 34A5<
RAM_DQ_R<61> 33B8<> 34A5<
RAM_DQ_R<62> 33B8<> 34A5<
RAM_DQ_R<63> 33A8<> 34A5<
RAM_DQ_R<64> 33D6<> 34D3<
RAM_DQ_R<65> 33D6<> 34D3<
RAM_DQ_R<66> 33D6<> 34D3<
RAM_DQ_R<67> 33D6<> 34D3<
RAM_DQ_R<68> 33D6<> 34D3<
RAM_DQ_R<69> 33D6<> 34D3<
RAM_DQ_R<70> 33D6<> 34D3<
RAM_DQ_R<71> 33D6<> 34D3<
RAM_DQ_R<72> 33D6<> 34D3<
RAM_DQ_R<73> 33D6<> 34D3<
RAM_DQ_R<74> 33D6<> 34D3<
RAM_DQ_R<75> 33C6<> 34D3<
RAM_DQ_R<76> 33C6<> 34D3<
RAM_DQ_R<77> 33C6<> 34C3<
RAM_DQ_R<78> 33C6<> 34C3<
RAM_DQ_R<79> 33C6<> 34C3<
RAM_DQ_R<80> 33C6<> 34C3<
RAM_DQ_R<81> 33C6<> 34C3<
RAM_DQ_R<82> 33C6<> 34C3<
RAM_DQ_R<83> 33C6<> 34C3<
RAM_DQ_R<84> 33C6<> 34C3<
RAM_DQ_R<85> 33C6<> 34C3<
RAM_DQ_R<86> 33C6<> 34C3<
RAM_DQ_R<87> 33C6<> 34C3<
RAM_DQ_R<88> 33C6<> 34C3<
RAM_DQ_R<89> 33C6<> 34C3<
RAM_DQ_R<90> 33C6<> 34C3<
RAM_DQ_R<91> 33C6<> 34C3<
RAM_DQ_R<92> 33C6<> 34C3<
RAM_DQ_R<93> 33C6<> 34C3<
RAM_DQ_R<94> 33C6<> 34B3<
RAM_DQ_R<95> 33C6<> 34B3<
RAM_DQ_R<96> 33C6<> 34B3<
RAM_DQ_R<97> 33C6<> 34B3<
RAM_DQ_R<98> 33C6<> 34B3<
RAM_DQ_R<99> 33C6<> 34B3<
RAM_DQ_R<100> 33C6<> 34B3<
RAM_DQ_R<101> 33B6<> 34B3<
RAM_DQ_R<102> 33B6<> 34B3<
RAM_DQ_R<103> 33B6<> 34B3<
RAM_DQ_R<104> 33B6<> 34B3<
RAM_DQ_R<105> 33B6<> 34B3<
RAM_DQ_R<106> 33B6<> 34B3<
RAM_DQ_R<107> 33B6<> 34B3<
RAM_DQ_R<108> 33B6<> 34B3<
RAM_DQ_R<109> 33B6<> 34B3<
RAM_DQ_R<110> 33B6<> 34B3<
RAM_DQ_R<111> 33B6<> 34A3<
RAM_DQ_R<112> 33B6<> 34A3<
RAM_DQ_R<113> 33B6<> 34A3<
RAM_DQ_R<114> 33B6<> 34A3<
RAM_DQ_R<115> 33B6<> 34A3<
RAM_DQ_R<116> 33B6<> 34A3<
RAM_DQ_R<117> 33B6<> 34A3<
RAM_DQ_R<118> 33B6<> 34A3<
RAM_DQ_R<119> 33B6<> 34A3<
RAM_DQ_R<120> 33B6<> 34A3<
RAM_DQ_R<121> 33B6<> 34A3<
RAM_DQ_R<122> 33B6<> 34A3<
RAM_DQ_R<123> 33B6<> 34A3<
RAM_DQ_R<124> 33B6<> 34A3<
RAM_DQ_R<125> 33B6<> 34A3<
RAM_DQ_R<126> 33B6<> 34A3<
RAM_DQ_R<127> 33A6<> 34A3<
RAM_MUXEN0 5A6< 33C2>
RAM_MUXEN4 5A6< 33C2>
RAM_RAS_L 34A5< 35B4<> 35B5<>
RAM_RAS_L_R 33D2> 34A6< 62A6> 62A6>
RAM_VREF_DIMM 35D1< 35D3<> 35D4<> 35D5<> 35D7<>
RAM_WE_L 34A5< 35B3<> 35B7<>
RAM_WE_L_R 33D2> 34A6< 62A6> 62A6>
RI_L 27B8<> 28B7<
ROM_CS_L 6D1> 45A5> 46B6< 47B5<>
ROM_OE_L 6D1> 45A5> 46B5< 47B4<>
ROM_ONBOARD_CS_L 6D1> 46B5< 47B5<>
ROM_WE_L 6D1> 45A5> 46B5< 47B5<>
ROM_WP_L 46B5<
RTC_CLK32K_X1 13D1<> 13D6>
RTC_CLK32K_X2 13D1<> 13D6>
RTUSB_OVERCURRENT 5C7> 17A3<>
RTUSB_PWREN 5C7> 17A3<>
SATABR_ISET_PD 51B4<>
SATABR_RESET_L 51B5<>
SATABR_RESET_ST 51B6<>
SATABR_VSS 51B4< 51D3<
SATA_BR_RXD_N 51C5< 51D6>
SATA_BR_RXD_P 51C5< 51D6>
SATA_BR_TXD_N 51C4<> 51D6>
SATA_BR_TXD_P 51C4<> 51D6>
SATA_CLK25M 5C8<
SATA_CLK25M_R 25B4<>
SATA_RXD_N1_C 50A5< 50D6> 51C3<
SATA_RXD_N2_C 5A8< 50A5< 50D6>
SATA_RXD_P1_C 50B5< 50D6> 51C3<
SATA_RXD_P2_C 5A8< 50A5< 50D6>
SATA_TXD_N1 50A4> 50D6> 51C6<
SATA_TXD_N2 5A8< 50A4> 50D6>
SATA_TXD_P1 50B4> 50D6> 51C6<
SATA_TXD_P2 5A8< 50A4> 50D6>
SB_CLK18M_XTALI 23A5< 23D6>
SB_CLK18M_XTALO 23A5< 23D6>
SB_CLK18M_XTALO_R 23A5<> 23D6>
SB_CLK25M_ATA 23A5< 23D6> 25B1<
SB_CLK25M_ATA_R 25B4<>
SB_GPIO12 23B3<> 23C2<
SB_GPIO23 23B2< 23B3<>
SB_GPIO24 23B2< 23B3<>
SB_GPIO25 23B2< 23B3<>
SB_GPIO30 23B2< 23B3<>
SB_GPIO45 23A3<> 23B2<
SB_GPIO46 23A3<> 23B2<
SB_GPIO47 23A3<> 23B2<
SB_GPIO49 23A3<> 23B2<
SB_GPIO50 23A3<> 23B2<
SB_GPIO51 23A2< 23A3<>
SB_GPIO52 23A2< 23A3<>
SB_HT_R100_N 44B4<
SB_HT_R100_P 44B4<>
SB_HT_S100M66M 44B5<
SB_INT_L 23B5<> 23B7<
SB_PCI_RESET_L 45A4<>
SB_PCI_SEL32BIT 23B5<>
SB_SATABR_RESET_L 23B3<> 23C2< 51B7<
SB_SELHT100 44B5<
SB_STOPXTALS_L 13B3<> 23B5<
SB_SUSPENDACK_L 13B3<> 23B5>
SB_TEST_MODE_PD 23A5<
SB_TO_SMU_INT_L 13B3<> 23C3<> 23D2<
SI_DDC_CLK 39B5<> 41C8<>
SI_DDC_DATA 39B5<> 41C8<>
SI_DUAL_MODE 41B8<>
SI_HTP 41B8<>
SI_I2CSEL 41C8<>
SI_MEXTSWING 41A6<
SI_MSEN_OC 41C5<>
SI_PRIMARY 41B8<>
SI_RESET_L 39B7<> 41B8<>
SI_SECONDARY 41A8<>
SI_SEXTSWING 41A6<>
SI_SYNC 41B8<>
SI_TMDS_CLKN 41B4< 41C5<> 62C4>
SI_TMDS_CLKP 41B4< 41C5<> 62C4>
SI_TMDS_DN<0> 41B4< 41B5<> 62C4>
SI_TMDS_DN<1> 41B4< 41B5<> 62C4>
SI_TMDS_DN<2> 41A4< 41B5<> 62C4>
SI_TMDS_DN<3> 41A4< 41B5<> 62C4>
SI_TMDS_DN<4> 41A4< 41B5<> 62B4>
SI_TMDS_DN<5> 41A4< 41B5<> 62B4>
SI_TMDS_DP<0> 41B4< 41C5<> 62C4>
SI_TMDS_DP<1> 41B4< 41B5<> 62C4>
SI_TMDS_DP<2> 41A4< 41B5<> 62C4>
SI_TMDS_DP<3> 41A4< 41B5<> 62C4>
SI_TMDS_DP<4> 41A4< 41B5<> 62C4>
SI_TMDS_DP<5> 41A4< 41B5<> 62B4>
SI_VREF 41A5<>
SLEEPLED_ANODE 6C2> 19A3< 61B4<>
SLEEPLED_ANODE_F 19B3<
SLEEPLED_ANODE_F_Q 19B3<
SLEEPLED_EN_L 19A3<>
SLEEPLED_EN_L_DIV 19B4<
SLEWING_L_R 25B4<>
SMU_ACIN 7C4<> 8C8<> 8D4<> 12C8< 13A7>
SMU_ACIN_L 7C4<> 8B2<>
SMU_BATT_DET_L 7A5< 13A7>
SMU_BOOT_BUSY 13D3> 16C3<>
SMU_BOOT_CE 13D3> 16C4<>
SMU_BOOT_CNVSS 6A1> 13B6< 16C4<>
SMU_BOOT_RXD 6A1> 13C3<> 16C3<>
SMU_BOOT_SCLK 13D3> 16C4<>
SMU_BOOT_TXD 6A1> 13C3<> 16C3<>
SMU_CHARGE_BATT 8A6<> 8B3<> 13B6<>
SMU_CHARGE_BATT_L 8A6<>
SMU_CLK10M_XIN 13B6< 13D6>
SMU_CLK10M_XOUT 13A6< 13D6>
SMU_CLK10M_XOUT_R 13B6<> 13D6>
SMU_CPU_JTAG_OR_I2C 18C6< 18D6>
SMU_ONEWIRE 13C6<> 17D5<
SMU_PWRSEQ_P1_0 13C6<> 14D8<
SMU_PWRSEQ_P1_1 13C6<> 14D8<
SMU_PWRSEQ_P1_2 13C6<> 14C8<
SMU_PWRSEQ_P1_3 13C6<> 14B8<
SMU_PWRSEQ_P1_4 13C6<> 14B8<
SMU_PWRSEQ_P9_5 13B3<> 14A8<
SMU_PWRSEQ_P9_6 13B3<> 14A8<
SMU_RESET_L 6B1> 13B6< 16C4<> 19D4<>
SMU_SLEEP 5A8< 13B1< 13B3<>
SMU_SUSPENDREQ_L 13B1< 13B3<> 22D3<> 23B5<
SMU_TO_SB_INT_L 13B6< 23A2< 23A3<>
SMU_WARM_RESET_L 5A8< 13B3<> 22B5<>
STOP_AGP_L 36B1< 37C6<
STOP_AGP_L_F 36B2<
STOP_AGP_L_R 36B3<
SYNCENABLE 27B8<> 28C6<
SYSCLK_TERM 27D6<
SYS_COLD_RESET_L 13B1< 13C3<> 22A6> 22B8<> 51B7<
SYS_DOOR_AJAR 6A4>
SYS_DOOR_AJAR_L 13A8< 13C6<>
SYS_DRIVE_BAY_INT_L 13A8< 13C6<>
SYS_KBDLED 13A7> 19A7<>
SYS_LED 13C3<> 19A4<>
SYS_LED_BLUE 13A6>
SYS_LED_GREEN 13A6>
SYS_LED_RED 13A6>
SYS_LID_OPEN 13A7> 17B8<>
SYS_OVERTEMP_L 6A4> 13B6<> 15D3> 17A8<> 23B3<>
23D2< 25B8<
SYS_PME_L 13B1< 13C3<> 23B5> 48A7<
SYS_POWERFAIL_L 13A8< 13C6<>
SYS_POWERUP 6A3> 14D5<>
SYS_POWERUP_L 6A1> 13C1< 13C3<> 14D8<
SYS_POWERUP_L_R 14D6<>
SYS_POWER_BUTTON_L 6A4> 6B1> 13B3<> 13C1< 16B4<
17A8<> 42D1<
SYS_PWRSEQ_1 14D7<
SYS_PWRSEQ_2 14D7<>
SYS_PWRSEQ_2_L 14D6<>
SYS_PWRSEQ_3_L 14C7<>
SYS_PWRSEQ_3_LS5 14C7<>
SYS_PWRSEQ_4 14B7<
SYS_PWRSEQ_5 14B7<
SYS_PWRSEQ_6_L 14A7<>
SYS_PWRSEQ_6_LS5 14A7<>
SYS_PWRSEQ_7 14A7<>
SYS_RESET_BUTTON_L 6B1> 13B3<> 16B4<
SYS_SLEEP 5A7> 10B6< 11B6< 25B8<
SYS_SLEWING_L 13B1< 13C3<> 23A3<> 23D2< 25B3<
31C6<>
SYS_SLOT_PWR 13B3<>
SYS_WARM_RESET_L 5A6< 22A6> 23B5< 45A4< 48A7<
TD1 32C4<
TD2 32C4<
TD3 32B3<
TD4 32B3<
TDIODE_NEG 29B4<> 32B5<>
TDIODE_POS 29D4<> 32B5<>
TD_BUFFERED 32C3<>
TD_CURRENT 32C3<>
THERM_1B_N 15B6< 15B6< 15D6>
THERM_1B_P 15B6< 15B6< 15D6>
THERM_1_N 15B6< 15B7< 15D6>
THERM_1_P 15B6< 15B7< 15D6>
THERM_2B_N 15A6< 15B6< 15D6>
THERM_2B_P 15B6< 15B6< 15D6>
THERM_2_N 15B6< 15B7< 15D6>
THERM_2_P 15B6< 15B7< 15D6>
THERM_3B_N 15A6< 15A6< 15D6>
THERM_3B_P 15A6< 15A6< 15D6>
THERM_3_N 15A6< 15A7< 15D6>
THERM_3_P 15A6< 15A7< 15D6>
TMDS_CLKN 41B2< 41B3< 41D1< 42B6<> 62D4>
TMDS_CLKP 41B3< 41B3< 41D1< 42B6<> 62D4>
TMDS_CONN_CLKN 6D7> 42B5<> 42C7<> 62C4>
TMDS_CONN_CLKP 6C7> 42B5<> 42C7<> 62C4>
TMDS_CONN_DN<0> 42C7<> 42D6<> 62C4>
TMDS_CONN_DN<1> 42B7<> 42D5<> 62C4>
TMDS_CONN_DN<2> 42B7<> 42D5<> 62C4>
TMDS_CONN_DN<3> 42C5<> 42C6<> 62C4>
TMDS_CONN_DN<4> 42B6<> 42C5<> 62C4>
TMDS_CONN_DN<5> 42B6<> 42C6<> 62C4>
TMDS_CONN_DP<0> 42B7<> 42D6<> 62C4>
TMDS_CONN_DP<1> 42B7<> 42D5<> 62C4>
TMDS_CONN_DP<2> 42B7<> 42D5<> 62C4>
TMDS_CONN_DP<3> 42B6<> 42C5<> 62C4>
TMDS_CONN_DP<4> 42B6<> 42C5<> 62C4>
TMDS_CONN_DP<5> 42B6<> 42C6<> 62C4>
TMDS_D3_CMF 41B1<
TMDS_D4_CMF 41B1<
TMDS_D5_CMF 41A1<
TMDS_DN<0> 6D7> 41B2< 41B3< 41D1< 42C8<>
62D4>
TMDS_DN<1> 6D7> 41A2< 41B3< 41C1< 42B8<>
62D4>
TMDS_DN<2> 6D7> 41A2< 41A3< 41C1< 42B8<>
62D4>
TMDS_DN<3> 41A3< 41B1< 42C7<> 62D4>
TMDS_DN<4> 41A3< 41B1< 42B7<> 62D4>
TMDS_DN<5> 41A1< 41A3< 42B7<> 62C4>
TMDS_DP<0> 6D7> 41B3< 41B3< 41D1< 42B8<>
62D4>
TMDS_DP<1> 6D7> 41A3< 41B3< 41C1< 42B8<>
62D4>
TMDS_DP<2> 6D7> 41A3< 41A3< 41C1< 42B8<>
62D4>
TMDS_DP<3> 41A3< 41B2< 42B7<> 62D4>
TMDS_DP<4> 41A3< 41B2< 42B7<> 62D4>
TMDS_DP<5> 41A2< 41A3< 42B7<> 62D4>
TP_AFN 27B8<>
TP_AGP_MB_AGP8X_DET_L 36B4>
TP_AIRPORT_PME_L 6A8> 47C4<>
TP_AIRPORT_RF_DISABLE 6A8> 47C5<>
TP_ATTENTION 27B6<>
TP_CPU1_HTBEN_R 5A6>
TP_DUMMY_A 22C4<>
TP_DUMMY_B 22C4<>
TP_EI_CPU1_CLK_N 5A6>
TP_EI_CPU1_CLK_P 5A6>
TP_EI_CPU1_SYNC_R 5A6>
TP_EXT_LED_L 5A7>
TP_FAN_RPM2 5A7>
TP_FAN_TACH2 5A7>
TP_FAN_TACH3 5A7>
TP_FAN_TACH4 5A7>
TP_FAN_TACH5 5A7>
TP_I2C_SMU_D_SCL 5A7>
TP_LVDS_L3N 39A5>
TP_LVDS_L3P 39A5>
TP_LVDS_U3N 39A5>
TP_LVDS_U3P 39A5>
TP_NB_PMR_OBSV 5A7>
TP_NB_PM_SLEEP0 22C5<>
TP_NB_THMI 5A7>
TP_NB_THMO 5A7>
TP_NEC_AMC 48A3<
TP_NEC_NANDTEST 48A3<
TP_NEC_NTEST1 48B3<
TP_NEC_SMC 48B3<
TP_NEC_SMI_L 48A5>
TP_NEC_SRCLK 48A3>
TP_NEC_SRDATA 48A3<>
TP_NEC_SRMOD 48A3<
TP_NEC_TEB 48B3<
TP_NEC_TEST 48A3<
TP_PLS_CLK_66M_0 25C1<
TP_PLS_CLK_66M_1 25C1<
TP_PLS_REF_CML 25B6<>
TP_PLS_TEST1 25B6<>
TP_PLS_TEST2 25B6<>
TP_PLS_TEST3 25B6<>
TP_PROC_SENSE_COMMON 32C5<>
TP_PROC_TRIGGER_OUT 27B8<>
TP_PSRO1 27B8<>
TP_PSRO2 27B8<>
TP_PSYNCOUT 27B8<>
TP_RAM_CKE_R<2> 5A6>
TP_RAM_CKE_R<3> 5A6>
TP_RAM_CKE_R<6> 5A6>
TP_RAM_CKE_R<7> 5A6>
TP_RAM_CLK_C_N 34D7>
TP_RAM_CLK_C_P 34D7>
TP_RAM_CLK_F_N 34D7>
TP_RAM_CLK_F_P 34D7>
TP_RAM_CS_L_R<2> 5A6>
TP_RAM_CS_L_R<3> 5A6>
TP_RAM_CS_L_R<10> 5A6>
TP_RAM_CS_L_R<11> 5A6>
TP_RAM_MUXEN0 5A5>
TP_RAM_MUXEN4 5A5>
TP_SATABR_CLK25M_XTLOUT 51B5>
TP_SATABR_T7 51C5<>
TP_SATABR_UAI 51C5<
TP_SATABR_UAO 51C5>
TP_SATA_CLK25M 25B1<
TP_SATA_RXD_N2 5A7>
TP_SATA_RXD_P2 5A7>
TP_SATA_TXD_N2 5A7>
TP_SATA_TXD_P2 5A7>
TP_SB_FSTEST 23A5>
TP_SB_NC_P7 59B7<>
TP_SB_NC_P8 59B7<>
TP_SB_NC_R3 59B7<>
TP_SB_NC_R4 59B7<>
TP_SB_NC_R5 59B7<>
TP_SB_NC_R6 59B7<>
TP_SB_NC_R7 59B7<>
TP_SB_NC_R8 59B7<>
TP_SB_NC_T1 59B7<>
TP_SB_NC_T2 59B7<>
TP_SB_NC_T3 59B7<>
TP_SB_NC_T4 59B7<>
TP_SB_NC_T5 59B7<>
TP_SB_NC_T6 59B7<>
TP_SB_NC_T7 59B7<>
TP_SB_NC_T8 59B7<>
TP_SB_NC_U1 59B7<>
TP_SB_NC_U2 59B7<>
TP_SB_NC_U3 59B7<>
TP_SB_NC_U4 59B7<>
TP_SB_NC_U5 59B7<>
TP_SB_NC_U6 59B7<>
TP_SB_NC_V1 59B7<>
TP_SB_NC_V2 59B7<>
TP_SB_NC_V3 59B7<>
TP_SB_NC_V4 59A7<>
TP_SB_NC_W1 59A7<>
TP_SB_NC_W3 59A7<>
TP_SB_NC_Y1 59A7<>
TP_SB_NC_Y3 59A7<>
TP_SB_PLLTEST 23A5>
TP_SB_WATCHDOG 23B5>
TP_SMU_SPARE_P8_3 13C3<>
TP_SMU_SPARE_P10_0 13B3<>
TP_USB2_PWREN2 5B7>
TP_USB2_PWREN3 5B7>
TP_USB2_PWREN4 5B7>
TP_VESTA_2_5V_EN 12A3<
TP_VESTA_ACTLED_L 54B3>
TP_VESTA_AN_EN 54B3<>
TP_VESTA_DNC_B9 12A6<>
TP_VESTA_DNC_C9 12A6<>
TP_VESTA_DNC_E9 12A6<>
TP_VESTA_EN_10B 54B5<
TP_VESTA_ER 54B5<
TP_VESTA_ESDET<0> 57C5<
TP_VESTA_ESDET<1> 57C5<
TP_VESTA_ESDET<2> 57C5<
TP_VESTA_F1000 54B5<
TP_VESTA_FDX 54B5<
TP_VESTA_FDXLED_L 54B3>
TP_VESTA_HUB 54B5<
TP_VESTA_LINK1_L 54B3>
TP_VESTA_LINK2_L 54B3>
TP_VESTA_MANMS 54B5<
TP_VESTA_PHYA<0> 54B5<
TP_VESTA_PHYA<1> 54B5<
TP_VESTA_PHYA<2> 54B5<
TP_VESTA_PHYA<3> 54B5<
TP_VESTA_PHYA<4> 54B5<
TP_VESTA_RBC0 54B3<>
TP_VESTA_RBC1 54B3<>
TP_VESTA_REGCTL1 12A3<
TP_VESTA_REGCTL2 12A3<
TP_VESTA_REGSEN1 12A3<
TP_VESTA_REGSEN2 12A3<
TP_VESTA_REGSUP1 12A3<
TP_VESTA_REGSUP2 12A3<
TP_VESTA_RGMIIEN 54B5<
TP_VESTA_SPD0 54B5<
TP_VESTA_TDBL<0> 57C3>
TP_VESTA_TDBL<1> 57C3>
TP_VESTA_TDBL<2> 57C3>
TP_VESTA_TEST<0> 54B5<
TP_VESTA_TEST<1> 54B5<
TP_VESTA_TEST_1394<0> 57B5<
TP_VESTA_TEST_1394<1> 57B5<
TP_VESTA_TVCO 54B5<>
TP_VESTA_TVCO_24 57B5<>
TP_VESTA_TXC_RXC_DELAY 54B3<>
TP_VESTA_XMTLED_L 54B3>
TP_VREF_CG 36B4<>
TV_C 6D5> 42A6<>
TV_COMP 6D5> 42A6<>
TV_GND1 6D5> 42B6<>
TV_GND2 6D5> 42A6<>
TV_Y 6D5> 42A6<>
UATA_CS0_L 6B4> 50B1< 50D6> 52B5<>
UATA_CS0_L_R 50B2< 50B4>
UATA_CS1_L 6B4> 50B1< 50D6> 52B7<>
UATA_CS1_L_R 50B2< 50B4>
UATA_DA<0> 6C4> 50B1< 52B5<>
UATA_DA<2..0> 50D6>
UATA_DA<1> 6B4> 50B1< 52B5<>
UATA_DA<2> 6B4> 50B1< 52B7<>
UATA_DA_R<0> 50B2< 50B4>
UATA_DA_R<1> 50B2< 50B4>
UATA_DA_R<2> 50B2< 50B4>
UATA_DD<0> 6D4> 50D1< 52B5<>
UATA_DD<6..0> 50D6>
UATA_DD<1> 6D4> 50D1< 52B5<>
UATA_DD<2> 6D4> 50D1< 52B5<>
UATA_DD<3> 6D4> 50D1< 52B5<>
UATA_DD<4> 6D4> 50D1< 52C5<>
UATA_DD<5> 6D4> 50D1< 52C5<>
UATA_DD<6> 6C4> 50C1< 52C5<>
UATA_DD<7> 6C4> 50C1< 50D6> 52C5<>
UATA_DD<8> 6C4> 50C1< 52C7<>
UATA_DD<15..8> 50D6>
UATA_DD<9> 6C4> 50C1< 52C7<>
UATA_DD<10> 6C4> 50C1< 52C7<>
UATA_DD<11> 6C4> 50C1< 52C7<>
UATA_DD<12> 6C4> 50C1< 52B7<>
UATA_DD<13> 6C4> 50C1< 52B7<>
UATA_DD<14> 6C4> 50B1< 52B7<>
UATA_DD<15> 6C4> 50B1< 52B7<>
UATA_DD_R<0> 50C4<> 50D2<
UATA_DD_R<1> 50C4<> 50D2<
UATA_DD_R<2> 50B4<> 50D2<
UATA_DD_R<3> 50B4<> 50D2<
UATA_DD_R<4> 50B4<> 50D2<
UATA_DD_R<5> 50B4<> 50D2<
UATA_DD_R<6> 50B4<> 50C2<
UATA_DD_R<7> 50B4<> 50C2<
UATA_DD_R<8> 50B4<> 50C2<
UATA_DD_R<9> 50B4<> 50C2<
UATA_DD_R<10> 50B4<> 50C2<
UATA_DD_R<11> 50B4<> 50C2<
UATA_DD_R<12> 50B4<> 50C2<
UATA_DD_R<13> 50B4<> 50C2<
UATA_DD_R<14> 50B2< 50B4<>
UATA_DD_R<15> 50B2< 50B4<>
UATA_DMACK_L 6C4> 50A1< 50D6> 52B7<>
UATA_DMACK_L_R 50A2< 50B4>
UATA_DMARQ 50B5< 50C6> 52B8<
UATA_DMARQ_R 6C4> 52B7<>
UATA_DSTROBE 50B5< 50D6> 52B5<
UATA_DSTROBE_R 6B4> 52B6<>
UATA_HSTROBE 6B4> 50B1< 50D6> 52B7<>
UATA_HSTROBE_R 50B2< 50B4>
UATA_INTRQ 50B5< 50C6> 52B5<
UATA_INTRQ_R 6B4> 52B6<>
UATA_RESET_L 6B4> 50B1< 50D6> 52C5<>
UATA_RESET_L_R 50B2< 50B4>
UATA_STOP 6B4> 50A1< 50D6> 52B5<>
UATA_STOP_R 50A2< 50B4>
UDASH_RESET_L 23B3<> 23D2<
UDASH_SDOWN 6A2> 23B3<> 60B3<>
USB2_LT_N 5C7> 17D6<>
USB2_LT_P 5C7> 17D6<>
USB2_N<0> 5C8< 6B3> 59C2<> 59D6>
USB2_N<1> 5C8< 6A3> 59C2<> 59D6>
USB2_N<2> 5B8< 6B3> 59B2<> 59D6>
USB2_N<3> 5B8< 6B2> 59B2<> 59D6>
USB2_N<4> 5B8< 6A4> 59A2<> 59D6>
USB2_OC2_PU 5B7>
USB2_OC3_PU 5B7>
USB2_OC4_PU 5B7>
USB2_OC<0> 5C8< 6B3> 59B6<
USB2_OC<1> 5C8< 6A3> 59B6<
USB2_OC<2> 5B8< 59B6<
USB2_OC<3> 5B8< 59B6<
USB2_OC<4> 5B8< 59B6<
USB2_P<0> 5C8< 6B3> 59C2<> 59D6>
USB2_P<1> 5C8< 6A3> 59C2<> 59D6>
USB2_P<2> 5B8< 6B3> 59B2<> 59D6>
USB2_P<3> 5B8< 6A2> 59B2<> 59D6>
USB2_P<4> 5B8< 6A4> 59A2<> 59D6>
USB2_PWREN<0> 5C8< 6B3> 59B5>
USB2_PWREN<1> 5C8< 6A3> 59B5>
USB2_PWREN<2> 5B8< 59B5>
USB2_PWREN<3> 5B8< 59B5>
USB2_PWREN<4> 5B8< 59B5>
USB2_RT_N 5C7> 17A3<>
USB2_RT_P 5C7> 17A3<>
USB_BT_N 5B7> 17D6<>
USB_BT_P 5B7> 17D6<>
USB_MODEM_N 5B7> 60B5<>
USB_MODEM_P 5B7> 60B5<>
USB_NEC_N<0> 59C3<>
USB_NEC_N<1> 59C3<>
USB_NEC_N<2> 59B3<>
USB_NEC_N<3> 59B3<>
USB_NEC_N<4> 59A3<>
USB_NEC_P<0> 59C3<>
USB_NEC_P<1> 59C3<>
USB_NEC_P<2> 59B3<>
USB_NEC_P<3> 59B3<>
USB_NEC_P<4> 59A3<>
USB_TPAD_N 5B7> 17A8<>
USB_TPAD_P 5B7> 17A8<>
VCORE_SWITCHING 14A6> 31B4<
VESTA1V2_ITH 12C2<>
VESTA1V2_ITH_RC 12C2<
VESTA1V2_MODE 12C3<>
VESTA1V2_RT 12C3<>
VESTA1V2_SGND 12B2<>
VESTA1V2_SW 12C2<>
VESTA1V2_VFB 12C2<>
VESTA2V5_NOISE 12D2<>
VESTA_CLK24M_XTALI 57B5< 57D6>
VESTA_CLK24M_XTALO 57A4< 57D6>
VESTA_CLK24M_XTALO_R 57B5<> 57D6>
VESTA_CLK25M_XTALI 54B5< 54D6>
VESTA_CLK25M_XTALO 54A4< 54D6>
VESTA_CLK25M_XTALO_R 54B5<> 54D6>
VESTA_DS_ONLY_EN0 57B5<
VESTA_ENET_LOWPWR 12C6<> 54B5<
VESTA_PWR_CLASS 57B5<
VESTA_RDAC1_PD 54B3<>
VESTA_RDAC2_PD 57B3<>
VESTA_RESET_L 12A6<
VGA_B 6C7> 42C6<> 42D7<
VGA_G 6C7> 42C5<> 42D7<
VGA_HSYNC 6C7> 42C6<> 42C7<
VGA_HSYNC_BUF 42C8<>
VGA_R 6C7> 42C5<> 42D7<
VGA_VSYNC 6C7> 42C5<> 42C7<
VGA_VSYNC_BUF 42C8<>
VSP_NB_CLK_N 22D6<> 25D1< 25D8<
VSP_NB_CLK_N_C 25C4<>
VSP_NB_CLK_P 22D6<> 25D1< 25D8<
VSP_NB_CLK_P_C 25C4<>
_GND_CHASSIS_DVI_BOTTOM 5A3> 42C5<>
_GND_CHASSIS_DVI_TOP 5A3> 42C4<>
_GND_CHASSIS_ENET 5A3> 55A3<>
_GND_CHASSIS_FW_PORT1 5A3> 58C1<>
_GND_CHASSIS_FW_PORT2 5A3> 58A2<>
_GND_CHASSIS_INV 5A3> 42A1< 42A2<
_GND_CHASSIS_LVDS 5A3> 42A4< 42A4<> 42B3<>
_GND_CHASSIS_SVIDEO 5A3> 42A7<>
_GPU_RESET_L 5D7> 37C8< 41C8<
_PCI_CBUS_RESET_L 5D7> 49A7<
_PCI_CLK33M_AIRPORT 5D7> 47C4<> 47D6>
_PCI_CLK33M_CBUS 5D7> 49A6< 49D6>
_PCI_CLK33M_USB2 5D7> 48B5< 48D6>
_PP1V2_ENETFW 12C1> 54D2< 57C1< 57D5<
_PP1V2_PWRON_1V2RUN 5B3> 9B3<>
_PP1V2_PWRON_DISK_SB 5B3> 50C6<
_PP1V2_PWRON_HT 5B3> 44A6< 44C3< 44D3< 44D6<
_PP1V2_PWRON_REG 5B5< 9A3<
_PP1V2_PWRON_SB 5B3> 23D2<
_PP1V2_RUN_FET 5B2<> 9B2<>
_PP1V5_GPU_AGP 5A5< 37D6< 39A1<> 39D5<> 40C8<
40D3<>
_PP1V5_PWRON_1V5RUN 5B3> 9C3<>
_PP1V5_PWRON_REG 5B5< 9C4<
_PP1V5_RUN_FET 5A3<> 5B2< 9C2<>
_PP1V8_GPU 5B5< 37A8< 39C8< 40A2< 40A7< 40B1<
40C7< 40C7< 40D3<> 40D6< 41A5<
_PP1V8_RUN_LDO 5C2< 9D5<>
_PP1V8_SATABR 5B1> 51D3<
_PP2V5_ENET 5C3> 55C6<>
_PP2V5_ENETFW 12D1> 54D5< 57D1< 57D5<
_PP2V5_GPU 5B6< 40A7< 40B8< 40D3<> 40D7<
40D8<
_PP2V5_PCI 5C1> 49C7<
_PP2V5_PWRON_1V8RUN 5C3> 9D7<
_PP2V5_PWRON_2V5RUN 5C3> 11D2<>
_PP2V5_PWRON_DIMM 5C3> 35B3< 35C3< 35D2< 35D3<>
35D5<> 35D5<> 35D7<>
_PP2V5_PWRON_HT 5C3> 44D3<
_PP2V5_PWRON_REG 5C5< 11C1<
_PP2V5_PWRON_SB 5C3> 21B2< 21C2< 23D6< 45C3< 56C6<
_PP2V5_RUN_FET 5C2< 11D1<>
_PP3V3_ALL_ACIN 5D1> 7D5<>
_PP3V3_ALL_DCILIM 5D1>
_PP3V3_ALL_HALLEFFECT 5D1> 17B7<>
_PP3V3_ALL_LDO 5D3< 11A3<
_PP3V3_ALL_RTC 5D1> 13D2<
_PP3V3_ALL_SMU 5D1> 13B7< 13C2< 13D2< 13D6<
16C4<> 18B4<
_PP3V3_CBUS 5C3> 49D3<
_PP3V3_CPUTHERM 5C3> 32A7<
_PP3V3_CPUVCORE 5C1> 31D8<
_PP3V3_ENET 12D3> 54C6<
_PP3V3_ENETFW 12D3> 57D1<
_PP3V3_FW 12D3> 57A4< 57C6< 58A8<
_PP3V3_GPU 5B5< 37B3< 37C8< 37C8< 37D3< 37D6<
39B6< 39B7< 39C4< 39C8< 40B1< 40D1<>
_PP3V3_PATA 5C1> 52C4<
_PP3V3_PCI 5C1> 23B8< 45B1< 45B8< 46B6<
46C5<> 47C5<> 48B6< 49C8< 49D7<
_PP3V3_PWRON_1V8RUN 5C3> 9D7<
_PP3V3_PWRON_3V3RUN 5C3> 10B4<>
_PP3V3_PWRON_ALS1 5C3> 19D7<
_PP3V3_PWRON_AUDIO 5C3> 61C1< 61C3<>
_PP3V3_PWRON_BT 5C3> 17D7<>
_PP3V3_PWRON_MODEM 5C3> 60C5<>
_PP3V3_PWRON_REG 5C5< 10C1<
_PP3V3_PWRON_SB 5C3> 18A8< 21B7< 23B6< 23C1<
23C3<> 23D1< 45A3<
_PP3V3_PWRON_THERM 5C3> 15D5<
_PP3V3_PWRON_USB 5C3> 59B6< 59C6< 59D5<
_PP3V3_RUN_FAN 5C1> 15B2< 15C2<
_PP3V3_RUN_FET 5C3< 10B3<>
_PP3V3_RUN_SI 5C1> 41D5<
_PP3V3_SATABR 5C1> 51B7< 51D2< 51D6<>
_PP3V3_SB_PCI 5C1> 45C7<
_PP5V_CBUS 5D3> 49D3<
_PP5V_CPUTHERM 5D3> 32D6<
_PP5V_CPUVCORE_VDD 5D3> 31D5<>
_PP5V_PATA 5D1> 52C4<>
_PP5V_PWRON_3V3ALL 5D3> 11A5<>
_PP5V_PWRON_5VRUN 5D3> 10B7<>
_PP5V_PWRON_AUDIO 5D3> 61C6<>
_PP5V_PWRON_FAN 5D3> 15B2<> 15C2<>
_PP5V_PWRON_GPUVCORE 5D3> 38D7<>
_PP5V_PWRON_LTUSB 5D3> 17D7<>
_PP5V_PWRON_MODEM 5D3> 60C4<>
_PP5V_PWRON_REG 5D5< 10C8<
_PP5V_PWRON_RTUSB 5D3> 17A3<>
_PP5V_PWRON_SERIAL 5D3> 16C3<>
_PP5V_PWRON_SLEEPLED 5D3> 19B4<
_PP5V_PWRON_TPAD 5D3> 17B7<>
_PP5V_RUN_AUDIO 5D1> 61C6<>
_PP5V_RUN_FET 5D3< 10A5<>
_PP5V_RUN_HD_FET 5D3< 10B5<>
_PP5V_RUN_KBDLED 5D1> 19B7<
_PP5V_UATA 5D1> 52C7<>
_PPBUSA_BBATT 5D6> 17A3<>
_PPBUSB_BBATT 5D6> 17A3<>
_PPBUS_ALL_A 5D6> 8B5<> 8C2<> 8D3<> 17D2<
42C2<>
_PPBUS_ALL_B 5D6> 8C1<> 8D5<> 17D2<
_PPBUS_FW 5D6> 12D7<
_PPBUS_INV 5D6> 42B2<
_PPBU_RUN_FW 5D1> 12D5<>
_PPFW_PHY 12C5> 57C5<
_PPFW_PORT1 12C5> 58D3<
_PPFW_PORT2 12C5> 58B4<
_PPPCI32_PWRON_SB 5C3> 21C2<>
_PPPCI64_PWRON_SB 5C3> 21C2<>
_PPSPD_DIMM 5C3> 35A3<> 35A4<> 35A7<>
_PPVCORE_CPU_REG 5C7< 31D2<> 32C8<> 32C8<>
_PPVCORE_GPUFB 5B6< 37A6<> 37B8< 40B8< 40C3<
40C8<
_PPVCORE_GPU_REG 5C7< 38C1<>
_PPVCORE_NB_REG 5B5< 11C8<
_PPVCORE_PWRON_NB 5B3> 20D6<
_PPVCORE_PWRON_SB 5B3> 21C7<
_PPVIN_1V2PWRON 5D3> 9B7<
_PPVIN_1V5PWRON 5C3> 9C7<
_PPVIN_2V5_NBVCORE_PWRON 5D6> 11D5<>
_PPVIN_5V3VPWRON 5D6> 10D7<>
_PPVIN_CPUVCORE 5D6> 31D6<>
_PPVIN_GPUVCORE 5D6> 38D4<> 38D7<>
_PPVIO_PCI_CBUS 5C1> 49D4<
_PPVIO_PCI_USB2 5C1> 48D5<
_PPVREF_SMU 5D1> 13B6<
_SATA_CLK25M 5C7> 51B5< 51D6>
051-6532 03
103101
Preliminary
Page 65
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
102
*** Part Cross-Reference for the entire design ***
BS510 PCB_STANDOFF 17
C700 CAP 7
C710 CAP 7
C720 CAP 7
C800 CAP 8
C801 CAP 8
C802 CAP 8
C805 CAP 8
C806 CAP 8
C807 CAP 8
C808 CAP 8
C811 CAP 8
C812 CAP 8
C813 CAP 8
C814 CAP 8
C815 CAP 8
C816 CAP 8
C817 CAP 8
C818 CAP_P 8
C820 CAP 8
C822 CAP 8
C823 CAP 8
C824 CAP 8
C825 CAP 8
C826 CAP 8
C827 CAP 8
C828 CAP 8
C829 CAP 8
C830 CAP 8
C831 CAP 8
C851 CAP 8
C860 CAP_P 17
C861 CAP_P 17
C862 CAP_P 17
C863 CAP_P 17
C864 CAP_P 17
C865 CAP_P 17
C882 CAP 8
C897 CAP 8
C940 CAP 9
C941 CAP 9
C942 CAP 9
C950 CAP 9
C951 CAP 9
C952 CAP 9
C953 CAP 9
C954 CAP 9
C955 CAP 9
C956 CAP 9
C957 CAP 9
C960 CAP 9
C961 CAP 9
C970 CAP 9
C971 CAP 9
C972 CAP 9
C980 CAP 9
C981 CAP 9
C1001 CAP_P 10
C1003 CAP 10
C1004 CAP_P 10
C1005 CAP 10
C1006 CAP 10
C1009 CAP 10
C1011 CAP 10
C1012 CAP 10
C1013 CAP_P 10
C1031 CAP 10
C1035 CAP 10
C1050 CAP 10
C1051 CAP 10
C1052 CAP 10
C1053 CAP 10
C1054 CAP 10
C1055 CAP 10
C1056 CAP 10
C1057 CAP 10
C1058 CAP 10
C1059 CAP 10
C1060 CAP 10
C1061 CAP 10
C1062 CAP 10
C1063 CAP 10
C1065 CAP 10
C1066 CAP 10
C1067 CAP 10
C1068 CAP 10
C1070 CAP 10
C1071 CAP 10
C1072 CAP 10
C1074 CAP_P 10
C1075 CAP_P 10
C1076 CAP 10
C1077 CAP 10
C1080 CAP 10
C1081 CAP 10
C1082 CAP 10
C1085 CAP 10
C1086 CAP 10
C1087 CAP_P 10
C1100 CAP 11
C1101 CAP 11
C1102 CAP 11
C1103 CAP 11
C1104 CAP 11
C1105 CAP 11
C1106 CAP 11
C1107 CAP 11
C1108 CAP 11
C1109 CAP 11
C1110 CAP 11
C1111 CAP 11
C1112 CAP 11
C1113 CAP 11
C1115 CAP 11
C1116 CAP 11
C1117 CAP 11
C1118 CAP 11
C1120 CAP 11
C1121 CAP 11
C1122 CAP 11
C1125 CAP_P 11
C1126 CAP 11
C1127 CAP 11
C1131 CAP 11
C1135 CAP 11
C1140 CAP 11
C1141 CAP 11
C1142 CAP 11
C1145 CAP 11
C1146 CAP 11
C1147 CAP_P 11
C1148 CAP_P 11
C1160 CAP 11
C1161 CAP 11
C1162 CAP 11
C1164 CAP 11
C1170 CAP 11
C1171 CAP 11
C1190 CAP 11
C1192 CAP 11
C1193 CAP_P 11
C1200 CAP 12
C1201 CAP 12
C1202 CAP 12
C1203 CAP 12
C1208 CAP 12
C1210 CAP 12
C1211 CAP 12
C1212 CAP 12
C1213 CAP 12
C1220 CAP 12
C1221 CAP 12
C1222 CAP 12
C1223 CAP 12
C1224 CAP 12
C1225 CAP 12
C1230 CAP 12
C1231 CAP 12
C1240 CAP 12
C1241 CAP 12
C1242 CAP 12
C1243 CAP 12
C1250 CAP 12
C1265 CAP 12
C1270 CAP 12
C1271 CAP_P 12
C1280 CAP 12
C1281 CAP 12
C1282 CAP 12
C1290 CAP 12
C1291 CAP 12
C1292 CAP 12
C1293 CAP 12
C1294 CAP 12
C1295 CAP 12
C1300 CAP 13
C1301 CAP 13
C1302 CAP 13
C1303 CAP 13
C1304 CAP 13
C1305 CAP 13
C1308 CAP 13
C1309 CAP 13
C1310 CAP 13
C1325 CAP 13
C1500 CAP 15
C1501 CAP 15
C1502 CAP 15
C1503 CAP 15
C1504 CAP 15
C1505 CAP 15
C1506 CAP 15
C1507 CAP 15
C1508 CAP 15
C1510 CAP 15
C1515 CAP 15
C1520 CAP 15
C1525 CAP 15
C1530 CAP 15
C1535 CAP 15
C1540 CAP 15
C1591 CAP 15
C1592 CAP 15
C1605 CAP 17
C1610 CAP 17
C2015 CAP 18
C2016 CAP 18
C2110 CAP 19
C2111 CAP 19
C2112 CAP 19
C2115 CAP 19
C2150 CAP 19
C2151 CAP 19
C2152 CAP 19
C2199 CAP 19
C2222 CAP 20
C2223 CAP 20
C2224 CAP 20
C2225 CAP 20
C2226 CAP 20
C2227 CAP 20
C2228 CAP 20
C2229 CAP 20
C2230 CAP 20
C2231 CAP 20
C2232 CAP 20
C2233 CAP 20
C2234 CAP 20
C2235 CAP 20
C2236 CAP 20
C2237 CAP 20
C2238 CAP 20
C2239 CAP 20
C2240 CAP 20
C2241 CAP 20
C2242 CAP 20
C2243 CAP 20
C2244 CAP 20
C2245 CAP 20
C2246 CAP 20
C2247 CAP 20
C2300 CAP 21
C2301 CAP 21
C2302 CAP 21
C2303 CAP 21
C2304 CAP 21
C2305 CAP 21
C2306 CAP 21
C2307 CAP 21
C2308 CAP 21
C2309 CAP 21
C2310 CAP 21
C2311 CAP 21
C2312 CAP 21
C2313 CAP 21
C2314 CAP 21
C2320 CAP 21
C2321 CAP 21
C2322 CAP 21
C2323 CAP 21
C2324 CAP 21
C2325 CAP 21
C2326 CAP 21
C2327 CAP 21
C2328 CAP 21
C2329 CAP 21
C2330 CAP 21
C2331 CAP 21
C2332 CAP 21
C2333 CAP 21
C2334 CAP 21
C2335 CAP 21
C2336 CAP 21
C2337 CAP 21
C2338 CAP 21
C2339 CAP 21
C2350 CAP 21
C2351 CAP 21
C2355 CAP 21
C2356 CAP 21
C2357 CAP 21
C2360 CAP 21
C2361 CAP 21
C2362 CAP 21
C2365 CAP 21
C2400 CAP 22
C2401 CAP 22
C2500 CAP 23
C2501 CAP 23
C2510 CAP 23
C2511 CAP 23
C2520 CAP 23
C2521 CAP 23
C2530 CAP 23
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C2540 CAP 23
C2590 CAP 23
C2591 CAP 23
C2601 CAP 24
C2603 CAP 24
C2605 CAP 24
C2607 CAP 24
C2609 CAP 24
C2611 CAP 24
C2613 CAP 24
C2615 CAP 24
C2617 CAP 24
C2619 CAP 24
C2620 CAP 24
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C2622 CAP 24
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C2625 CAP 24
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C2627 CAP 24
C2628 CAP 24
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C2632 CAP 24
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C2634 CAP 24
C2635 CAP 24
C2636 CAP 24
C2637 CAP 24
C2638 CAP 24
C2639 CAP 24
C2640 CAP 24
C2645 CAP 24
C2651 CAP 24
C2665 CAP 24
C2667 CAP 24
C2669 CAP 24
C2671 CAP 24
C2700 CAP 25
C2702 CAP 25
C2705 CAP 25
C2707 CAP 25
C2708 CAP 25
C2710 CAP 25
C2713 CAP 25
C2715 CAP 25
C2800 CAP 26
C2801 CAP 26
C2802 CAP 26
C2803 CAP 26
C2804 CAP 26
C2805 CAP 26
C2806 CAP 26
C2807 CAP 26
C2808 CAP 26
C2809 CAP 26
C2810 CAP 26
C2811 CAP 26
C2812 CAP 26
C2813 CAP 26
C2814 CAP 26
C2815 CAP 26
C2816 CAP 26
C2817 CAP 26
C2818 CAP 26
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C2820 CAP 26
C2821 CAP 26
C2900 CAP 27
C2901 CAP 27
C2902 CAP 27
C2903 CAP 27
C2904 CAP 27
C2905 CAP 27
C2906 CAP 27
C2907 CAP 27
C2908 CAP 27
C2909 CAP 27
C2910 CAP 27
C2911 CAP 27
C2912 CAP 27
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C2914 CAP 27
C2915 CAP 27
C2916 CAP 27
C2917 CAP 27
C2918 CAP 27
C2919 CAP 27
C2920 CAP 27
C2921 CAP 27
C2922 CAP 27
C2923 CAP 27
C2924 CAP 27
C2925 CAP 27
C2926 CAP 27
C2927 CAP 27
C2928 CAP 27
C2929 CAP 27
C2930 CAP 27
C2931 CAP 27
C2932 CAP 27
C2933 CAP 27
C2934 CAP 27
C2935 CAP 27
C2936 CAP 27
C2937 CAP 27
C2938 CAP 27
C2939 CAP 27
C2940 CAP 27
C2941 CAP 27
C2942 CAP 27
C2943 CAP 27
C2944 CAP 27
C2945 CAP 27
C2946 CAP 27
C2947 CAP 27
C2948 CAP 27
C2949 CAP 27
C2950 CAP 27
C2951 CAP 27
C2952 CAP 27
C2953 CAP 27
C2954 CAP 27
C2955 CAP 27
C2956 CAP 27
C2957 CAP 27
C2958 CAP 27
C2959 CAP 27
C2960 CAP 27
C3100 CAP 29
C3101 CAP 29
C3102 CAP 29
C3103 CAP 29
C3104 CAP 29
C3105 CAP 29
C3106 CAP 29
C3107 CAP 29
C3108 CAP 29
C3109 CAP 29
C3110 CAP 29
C3111 CAP 29
C3112 CAP 29
C3113 CAP 29
C3114 CAP 29
C3115 CAP 29
C3116 CAP 29
C3117 CAP 29
C3118 CAP 29
C3119 CAP 29
C3120 CAP 29
C3121 CAP 29
C3122 CAP 29
C3123 CAP 29
C3124 CAP 29
C3125 CAP 29
C3126 CAP 29
C3127 CAP 29
C3128 CAP 29
C3129 CAP 29
C3130 CAP 29
C3131 CAP 29
C3132 CAP 29
C3133 CAP 29
C3134 CAP 29
C3135 CAP 29
C3136 CAP 29
C3137 CAP 29
C3138 CAP 29
C3139 CAP 29
C3140 CAP 29
C3141 CAP 29
C3142 CAP 29
C3143 CAP 29
C3144 CAP 29
C3145 CAP 29
C3146 CAP 29
C3147 CAP 29
C3148 CAP 29
C3149 CAP 29
C3150 CAP 29
C3199 CAP 29
C3200 CAP 30
C3201 CAP 30
C3202 CAP 30
C3203 CAP 30
C3204 CAP 30
C3205 CAP 30
C3206 CAP 30
C3207 CAP 30
C3208 CAP 30
C3209 CAP 30
C3210 CAP 30
C3211 CAP 30
C3212 CAP 30
C3213 CAP 30
C3214 CAP 30
C3215 CAP 30
C3216 CAP 30
C3217 CAP 30
C3218 CAP 30
C3219 CAP 30
C3220 CAP 30
C3221 CAP 30
C3222 CAP 30
C3223 CAP 30
C3224 CAP 30
C3225 CAP 30
C3226 CAP 30
C3227 CAP 30
C3228 CAP 30
C3229 CAP 30
C3230 CAP 30
C3231 CAP 30
C3232 CAP 30
C3233 CAP 30
C3234 CAP 30
C3235 CAP 30
C3236 CAP 30
C3237 CAP 30
C3238 CAP 30
C3239 CAP 30
C3240 CAP 30
C3241 CAP 30
C3242 CAP 30
C3243 CAP 30
C3244 CAP 30
C3245 CAP 30
C3246 CAP 30
C3247 CAP 30
C3248 CAP 30
C3249 CAP 30
C3250 CAP 30
C3251 CAP 30
C3252 CAP 30
C3253 CAP 30
C3254 CAP 30
C3255 CAP 30
C3256 CAP 30
C3257 CAP 30
C3258 CAP 30
C3259 CAP 30
C3260 CAP 30
C3261 CAP 30
C3262 CAP 30
C3263 CAP 30
C3264 CAP 30
C3265 CAP 30
C3266 CAP 30
C3267 CAP 30
C3268 CAP 30
C3269 CAP 30
C3270 CAP 30
C3271 CAP 30
C3272 CAP 30
C3273 CAP 30
C3274 CAP 30
C3275 CAP 30
C3276 CAP 30
C3277 CAP 30
C3278 CAP 30
C3279 CAP 30
C3280 CAP 30
C3281 CAP 30
C3282 CAP 30
C3283 CAP 30
C3284 CAP 30
C3285 CAP 30
C3286 CAP 30
C3287 CAP 30
C3288 CAP 30
C3289 CAP 30
C3290 CAP 30
C3291 CAP 30
C3292 CAP 30
C3293 CAP 30
C3294 CAP 30
C3295 CAP 30
C3296 CAP 30
C3297 CAP 30
C3298 CAP 30
C3299 CAP 30
C3300 CAP 31
C3301 CAP 31
C3302 CAP 31
C3303 CAP 31
C3304 CAP 31
C3306 CAP 31
C3310 CAP 31
C3311 CAP 31
C3312 CAP 31
C3313 CAP 31
C3315 CAP 31
C3316 CAP 31
C3319 CAP 31
C3320 CAP 31
C3321 CAP 31
C3322 CAP 31
C3323 CAP 31
C3325 CAP 31
C3326 CAP 31
C3329 CAP 31
C3330 CAP 31
C3332 CAP 31
C3333 CAP 31
C3350 CAP 31
C3351 CAP 31
C3352 CAP 31
C3353 CAP 31
C3354 CAP 31
C3355 CAP 31
C3356 CAP 31
C3357 CAP 31
C3359 CAP 31
C3360 CAP_P 31
C3361 CAP_P 31
C3362 CAP_P 31
C3363 CAP_P 31
C3364 CAP_P 31
C3365 CAP_P 31
C3366 CAP_P 31
C3367 CAP_P 31
C3370 CAP 31
C3371 CAP 31
C3372 CAP 31
C3373 CAP 31
C3374 CAP 31
C3375 CAP 31
C3376 CAP 31
C3377 CAP 31
C3378 CAP 31
C3379 CAP 31
C3380 CAP 31
C3381 CAP 31
C3382 CAP 31
C3383 CAP 31
C3384 CAP 31
C3385 CAP 31
C3386 CAP 31
C3387 CAP 31
C3388 CAP 31
C3389 CAP 31
C3391 CAP 31
C3392 CAP 31
C3393 CAP 31
C3394 CAP 31
C3395 CAP 31
C3396 CAP 31
C3397 CAP 31
C3398 CAP 31
C3399 CAP 31
C3630 CAP 32
C3631 CAP 32
C3636 CAP 32
C3639 CAP 32
C3640 CAP 32
C3650 CAP 32
C3651 CAP 32
C3660 CAP 32
C3669 CAP 32
C3670 CAP 32
C3671 CAP 32
C3676 CAP 32
C3679 CAP 32
C3698 CAP 32
C3699 CAP 32
C3700 CAP 33
C3701 CAP 33
C3702 CAP 33
C3703 CAP 33
C3704 CAP 33
C3705 CAP 33
C3706 CAP 33
C3707 CAP 33
C3708 CAP 33
C3709 CAP 33
C3710 CAP 33
C3711 CAP 33
C3712 CAP 33
C3713 CAP 33
C3714 CAP 33
C3715 CAP 33
C3716 CAP 33
C3717 CAP 33
C3718 CAP 33
C3719 CAP 33
C3720 CAP 33
C3721 CAP 33
C3722 CAP 33
C3724 CAP 33
C3725 CAP 33
C3726 CAP 33
C3727 CAP 33
C3728 CAP 33
C3729 CAP 33
C3730 CAP 33
C3731 CAP 33
C3732 CAP 33
C3733 CAP 33
C3734 CAP 33
C3735 CAP 33
C3736 CAP 33
C3737 CAP 33
C3738 CAP 33
C3739 CAP 33
C3740 CAP 33
C3742 CAP 33
C3743 CAP 33
C3744 CAP 33
C3745 CAP 33
C3746 CAP 33
C3747 CAP 33
C3748 CAP 33
C4001 CAP 35
C4002 CAP 35
C4008 CAP 35
C4009 CAP 35
C4010 CAP 35
C4011 CAP 35
C4012 CAP 35
C4013 CAP 35
C4014 CAP 35
C4015 CAP 35
C4016 CAP 35
C4017 CAP 35
C4018 CAP 35
C4019 CAP 35
C4020 CAP 35
C4021 CAP 35
C4022 CAP 35
C4023 CAP 35
C4024 CAP 35
C4025 CAP 35
C4026 CAP 35
C4027 CAP 35
C4028 CAP 35
C4029 CAP 35
C4030 CAP 35
C4031 CAP 35
C4800 CAP 36
C4801 CAP 36
C4802 CAP 36
C4803 CAP 36
C4804 CAP 36
C4805 CAP 36
C4806 CAP 36
C4807 CAP 36
C4808 CAP 36
C4810 CAP 36
C4811 CAP 36
C4812 CAP 36
C4813 CAP 36
C4814 CAP 36
C4815 CAP 36
C4816 CAP 36
C4817 CAP 36
C4818 CAP 37
C4900 CAP 37
C4901 CAP 37
C4902 CAP 37
C4903 CAP 37
C4904 CAP 37
C4906 CAP 37
C4907 CAP 37
C4912 CAP 37
C4913 CAP 37
C4980 CAP 37
C4981 CAP 37
C4990 CAP 37
C4991 CAP 37
C5000 CAP 38
C5001 CAP 38
C5002 CAP 38
C5008 CAP 38
C5011 CAP 38
C5012 CAP 38
C5015 CAP 38
C5019 CAP 38
C5030 CAP 38
C5031 CAP 38
C5032 CAP 38
C5033 CAP 38
C5034 CAP 38
C5035 CAP_P 38
C5036 CAP_P 38
C5037 CAP_P 38
C5038 CAP 38
C5100 CAP 39
C5101 CAP 39
C5102 CAP 39
C5103 CAP 39
C5104 CAP 39
C5105 CAP 39
C5106 CAP 39
C5107 CAP 39
C5108 CAP 39
C5109 CAP 39
C5110 CAP 39
C5111 CAP 39
C5112 CAP 39
C5113 CAP 39
C5114 CAP 39
C5115 CAP 39
C5116 CAP 39
C5117 CAP 39
C5118 CAP 39
C5119 CAP 39
C5120 CAP 39
C5121 CAP 39
C5122 CAP 39
C5123 CAP 39
C5124 CAP 39
C5125 CAP 39
C5126 CAP 39
C5127 CAP 39
C5128 CAP 39
C5129 CAP 39
C5130 CAP 39
C5131 CAP 39
C5132 CAP 39
C5133 CAP 39
C5200 CAP 40
C5201 CAP 40
C5202 CAP 40
C5203 CAP 40
C5204 CAP 40
C5205 CAP 40
C5206 CAP 40
C5207 CAP 40
C5208 CAP 40
C5209 CAP 40
C5210 CAP 40
C5211 CAP 40
C5212 CAP 40
C5213 CAP 40
C5214 CAP 40
C5215 CAP 40
C5216 CAP 40
C5217 CAP 40
C5218 CAP 40
C5219 CAP 40
C5220 CAP 40
C5221 CAP 40
C5222 CAP 40
C5223 CAP 40
C5224 CAP 40
C5225 CAP 40
C5226 CAP 40
C5227 CAP 40
C5228 CAP 40
C5229 CAP 40
C5230 CAP 40
C5231 CAP 40
C5232 CAP 40
C5233 CAP 40
C5234 CAP 40
C5235 CAP 40
C5236 CAP 40
C5237 CAP 40
C5238 CAP 40
C5239 CAP 40
C5240 CAP 40
C5241 CAP 40
C5242 CAP 40
C5243 CAP 40
C5244 CAP 40
C5245 CAP 40
C5246 CAP 40
C5247 CAP 40
C5248 CAP 40
C5249 CAP 40
C5250 CAP 40
C5251 CAP 40
C5252 CAP 40
C5253 CAP 40
C5254 CAP 40
C5255 CAP 40
C5256 CAP 40
C5257 CAP 40
C5258 CAP 40
C5259 CAP 40
C5260 CAP 40
C5261 CAP 40
C5262 CAP 40
C5263 CAP 40
C5264 CAP 40
C5265 CAP 40
C5266 CAP 40
C5267 CAP 40
C5268 CAP 40
C5269 CAP 40
C5270 CAP 40
C5271 CAP 40
C5272 CAP 40
C5273 CAP 40
C5274 CAP 40
C5275 CAP 40
C5276 CAP 40
C5277 CAP 40
C5278 CAP 40
C5279 CAP 40
C5280 CAP 40
C5281 CAP 40
C5282 CAP 40
C5283 CAP 40
C5284 CAP 40
C5292 CAP 40
C5293 CAP 40
C5294 CAP 40
C5295 CAP 40
C5296 CAP 40
C5297 CAP 40
C5298 CAP 40
C5299 CAP 40
C5700 CAP 41
C5701 CAP 41
C5702 CAP 41
C5703 CAP 41
C5704 CAP 41
C5705 CAP 41
C5710 CAP 41
C5711 CAP 41
C5712 CAP 41
C5713 CAP 41
C5714 CAP 41
C5715 CAP 41
C5716 CAP 41
C5717 CAP 41
C5720 CAP 41
C5721 CAP 41
C5722 CAP 41
C5723 CAP 41
C5724 CAP 41
C5725 CAP 41
C5726 CAP 41
C5730 CAP 41
C5731 CAP 41
C5732 CAP 41
C5733 CAP 41
C5734 CAP 41
C5735 CAP 41
C5736 CAP 41
C5737 CAP 41
C5738 CAP 41
C5739 CAP 41
C5740 CAP 41
C5760 CAP 41
C5761 CAP 41
C5762 CAP 41
C5763 CAP 41
C5764 CAP 41
C5765 CAP 41
C5766 CAP 41
C5767 CAP 41
C5900 CAP 42
C5904 CAP 42
C5905 CAP 42
C5906 CAP 42
C5910 CAP 42
C5911 CAP 42
C5912 CAP 42
C5920 CAP 42
C5929 CAP 42
C5960 CAP 42
C5961 CAP 42
C5962 CAP 42
C5963 CAP 42
C5964 CAP 42
C5967 CAP 42
C5968 CAP 42
C5969 CAP 42
C5970 CAP 42
C5971 CAP 42
C5972 CAP 42
C5973 CAP 42
C5975 CAP 42
C5976 CAP 42
C5980 CAP 42
C5981 CAP 42
C5982 CAP 42
C5983 CAP 42
C5984 CAP 42
C5999 CAP 42
C6000 CAP 43
C6001 CAP 43
C6002 CAP 43
C6004 CAP 43
C6005 CAP 43
C6006 CAP 43
C6007 CAP 43
C6008 CAP 43
C6010 CAP 43
C6011 CAP 43
C6012 CAP 43
C6013 CAP 43
C6200 CAP 44
C6201 CAP 44
C6210 CAP 44
C6211 CAP 44
C6220 CAP 44
C6230 CAP 44
C6231 CAP 44
C6232 CAP 44
C6240 CAP 44
C6241 CAP 44
C6242 CAP 44
C6250 CAP 44
C6251 CAP 44
C6255 CAP 44
C7400 CAP 45
C7401 CAP 45
C7402 CAP 45
C7403 CAP 45
C7404 CAP 45
C7405 CAP 45
C7406 CAP 45
C7407 CAP 45
C7408 CAP 45
C7409 CAP 45
C7410 CAP 45
C7411 CAP 45
C7420 CAP 45
C7421 CAP 45
C7422 CAP 45
C7423 CAP 45
C7450 CAP 45
C7500 CAP 46
C7501 CAP 46
C7502 CAP 46
C7703 CAP 48
C7800 CAP 49
C7801 CAP 49
C7802 CAP 49
C7803 CAP 49
C7804 CAP 49
C7805 CAP 49
C7806 CAP 49
C7807 CAP 49
C7808 CAP 49
C7809 CAP 49
C7810 CAP 49
C7811 CAP 49
C8000 CAP 50
C8001 CAP 50
C8002 CAP 50
C8003 CAP 50
C8004 CAP 50
C8150 CAP 51
C8151 CAP 51
C8152 CAP 51
C8153 CAP 51
C8154 CAP 51
C8155 CAP 51
C8156 CAP 51
C8157 CAP 51
C8158 CAP 51
C8159 CAP 51
C8160 CAP 51
C8161 CAP 51
C8162 CAP 51
C8163 CAP 51
C8198 CAP 51
C8199 CAP 51
C8308 CAP 52
C8358 CAP 52
C8601 CAP 54
C8602 CAP 54
C8603 CAP 54
C8604 CAP 54
C8605 CAP 54
C8618 CAP 54
C8619 CAP 54
C8620 CAP 54
C8621 CAP 54
C8622 CAP 54
C8623 CAP 54
C8700 CAP 55
C8701 CAP 55
C8702 CAP 55
C8703 CAP 55
C8705 CAP 55
C8800 CAP 56
C8801 CAP 56
C8802 CAP 56
C8900 CAP 57
C8901 CAP 57
C8903 CAP 57
C8904 CAP 57
C8905 CAP 57
C8906 CAP 57
C8907 CAP 57
C8908 CAP 57
C8909 CAP 57
C8911 CAP 57
C8913 CAP 57
C8914 CAP 57
C8915 CAP 57
C8917 CAP 57
C8918 CAP 57
C8919 CAP 57
C8920 CAP 57
C8921 CAP 57
C8950 CAP 57
C9010 CAP 58
C9011 CAP 58
C9012 CAP 58
C9013 CAP 58
C9014 CAP 58
C9015 CAP 58
C9016 CAP 58
C9017 CAP 58
C9018 CAP 58
C9019 CAP 58
C9020 CAP 58
C9021 CAP 58
C9022 CAP 58
C9023 CAP 58
C9024 CAP 58
C9025 CAP 58
C9026 CAP 58
C9050 CAP 58
C9054 CAP 58
C9060 CAP 58
C9064 CAP 58
C9090 CAP 58
C9091 CAP 58
C9092 CAP 58
C9120 CAP 59
C9121 CAP 59
C9122 CAP 59
C9123 CAP 59
C9124 CAP 59
C9125 CAP 59
C9126 CAP 59
C9127 CAP 59
C9128 CAP 59
C9129 CAP 59
C9130 CAP 59
C9135 CAP 59
C9136 CAP 59
C9137 CAP 59
C9145 CAP 59
C9146 CAP 59
C9403 CAP 60
D790 DIODE_SCHOT 17
D800 DIODE 8
D810 DIODE_SCHOT 8
D1030 DIODE_SCHOT 10
D1031 DIODE_SCHOT 10
D1035 DIODE_SCHOT 10
D1036 DIODE_SCHOT 10
D1060 DIODE_SCHOT 10
D1110 DIODE_SCHOT 11
D1115 DIODE_SCHOT 11
D1130 DIODE_SCHOT 11
D1131 DIODE_SCHOT 11
D1135 DIODE_SCHOT 11
D1136 DIODE_SCHOT 11
D1160 DIODE_SCHOT 11
D1161 DIODE 11
D1162 DIODE_SCHOT 11
D1163 DIODE_SCHOT 11
D1164 DIODE_SCHOT 11
D1165 ZENER 11
D1265 DIODE_SCHOT 12
D1270 DIODE_SCHOT_3P2 12
D1271 DIODE_SCHOT 12
D1310 DIODE 13
D2150 DIODE_SCHOT 19
D3001 LED 16
D3002 LED 16
D3310 DIODE_3P_C 31
D3315 DIODE_SCHOT 31
D3320 DIODE_3P_C 31
D3325 DIODE_SCHOT 31
D3699 VREF_LM4050 32
D5011 DIODE_SCHOT 38
D5030 DIODE_SCHOT 38
D5900 DIODE_SCHOT 42
D9090 ZENER 58
DP800 DPAK3P 8
DP1260 DPAK3P 12
DP5190 DPAK3P 39
DP5290 DPAK3P 40
DP9010 DIODE_DUAL_6P 58
DP9011 DIODE_DUAL_6P 58
DP9020 DIODE_DUAL_6P 58
DP9021 DIODE_DUAL_6P 58
F895 FUSE 8
F899 FUSE 8
F1265 FUSE 12
F5900 FUSE 42
F9020 FUSE 58
FL5910 FILTER_LC 42
FL5911 FILTER_LC 42
FL5912 FILTER_LC 42
FL9010 FILTER_4P 58
FL9011 FILTER_4P 58
FL9020 FILTER_4P 58
FL9021 FILTER_4P 58
G4980 OSC 37
J700 CON_M4RT_S_SM 7
J750 CON_M10RT_S_SM 7
J790 CON_F14RT_S2MT_SM 17
J1591 CON_4RT_WRIB 15
J1592 CON_4RT_WRIB 15
J1600 CON_F14RT_S2MT_SM 17
J1699 CON_F16ST_D_SMA 16
J2130 CON_F14RT_S2MT_SM 17
J2700 CON_F1ST_S2MT_SM 25
J4010 CON_F200RT_DDRDIMM_SM1 35
J4020 CON_F200RT_DDRDIMM_SM2 35
J5900 CON_F30RT_T6MT_TH1 42
J5960 CON_F5RT_MINIDIN_TH 42
J5970 CON_F30RT_S2MT_SM 42
J5980 CON_4RT_WRIB 42
J7600 CON_M80ST_D2MT_SM3 47
J7800 CON_M80ST_D4MT_SM 49
J8300 CON_M50SM_5MM 52
J8350 CON_M50SM_5MM 52
J8710 CON_RJ45_SHORT_4MT_TH 55
J9010 CON_F9RT_1394B_S6MT_SMA 58
J9020 CON_F6RT_S4MT_TH1 58
J9400 CON_F16ST_D_SMA 60
J9500 CON_M40ST_D4MT_SM 61
L750 IND 7
L751 IND 7
L755 IND 7
L756 IND 7
L759 IND 7
L810 IND 8
L950 IND 9
L970 IND 9
L1060 IND 10
L1065 IND 10
L1110 IND 11
L1115 IND 11
L1200 IND 12
L1270 IND 12
L1290 IND 12
L2150 IND 19
L2199 IND 19
L2601 IND 24
L2603 IND 24
L2605 IND 24
L2607 IND 24
L2609 IND 24
L3101 IND 29
L3310 IND 31
L3320 IND 31
L4900 IND 37
L4980 IND 37
L4990 IND 37
L5030 IND_3P 38
L5126 IND 39
L5200 IND 40
L5201 IND 40
L5202 IND 40
L5203 IND 40
L5204 IND 40
L5205 IND 40
L5206 IND 40
L5207 IND 40
L5208 IND 40
L5209 IND 40
L5210 IND 40
L5211 IND 40
L5212 IND 40
L5213 IND 40
L5214 IND 40
L5280 IND 40
L5720 IND 41
L5730 IND 41
L5739 IND 41
L5900 IND 42
L5915 FILTER_4P 42
L5916 FILTER_4P 42
L5917 FILTER_4P 42
L5918 FILTER_4P 42
L5919 FILTER_4P 42
L5920 FILTER_4P 42
L5921 FILTER_4P 42
L5960 IND 42
L5961 IND 42
L5962 IND 42
L5963 IND 42
L5964 IND 42
L5975 IND 42
L5980 IND 42
L5981 IND 42
L5982 IND 42
L8155 IND 51
L8600 IND 54
L8601 IND 54
L8602 IND 54
L8900 IND 57
L8901 IND 57
L8902 IND 57
L8906 IND 57
L8909 IND 57
L8913 IND 57
L9010 IND 58
L9020 IND 58
L9090 IND 58
L9135 IND 59
L9530 IND 61
L9531 IND 61
L9532 IND 61
L9533 IND 61
L9534 IND 61
L9535 IND 61
L9536 IND 61
L9537 IND 61
L9538 IND 61
L9539 IND 61
L9540 IND 61
Q715 TRA_2N7002DW 7
Q720 TRA_SI4405DY 7
Q800 TRA_2N7002DW 8
Q810 TRA_SI4835BDY 8
Q811 TRA_MOSFET_NCHN_8P 8
Q850 TRA_SI4405DY 8
Q877 TRA_2N7002DW 8
Q880 TRA_SI4435DY 8
Q882 TRA_2N7002DW 8
Q890 TRA_SI4435DY 8
Q895 TRA_SUD45P03 8
Q899 TRA_SUD45P03 8
Q960 TRA_SI3446DV 9
Q980 TRA_SI3446DV 9
Q1003 TRA_SI3443DV 10
Q1004 TRA_SI3443DV 10
Q1007 TRA_SI3443DV 10
Q1060 TRA_IRF7821 10
Q1061 TRA_MOSFET_NCHN_8P 10
Q1065 TRA_SI4816DY 10
Q1110 TRA_IRF7821 11
Q1111 TRA_MOSFET_NCHN_8P 11
Q1115 TRA_SI7392DP 11
Q1116 TRA_MOSFET_NCHN_8P 11
Q1190 TRA_SI6467BDQ 11
Q1250 TRA_2N7002 12
Q1260 TRA_2N7002DW 12
Q1265 TRA_NDS9407 12
Q1400 TRA_2N7002DW 14
Q1435 TRA_2N7002DW 14
Q1510 TRA_2N3904 15
Q1515 TRA_2N3904 15
Q1520 TRA_2N3904 15
Q1525 TRA_2N3904 15
Q1530 TRA_2N3904 15
Q1535 TRA_2N3904 15
Q2000 TRA_2N7002DW 18
Q2191 TRA_2N7002DW 19
Q2199 TRA_2N3906 19
Q2404 TRA_2N7002DW 22
Q2407 TRA_2N7002 22
Q2408 TRA_SI2302DS 22
Q2409 TRA_2N7002DW 22
Q2412 TRA_2N7002DW 22
Q2576 TRA_2N3904 23
Q3001 TRA_2N3904 16
Q3002 TRA_2N3906 16
Q3003 TRA_2N3904 16
Q3004 TRA_2N7002 16
Q3309 TRA_2N7002 31
Q3310 TRA_SI7392DP 31
Q3312 TRA_MOSFET_NCHN_8P 31
Q3313 TRA_MOSFET_NCHN_8P 31
Q3320 TRA_SI7392DP 31
Q3322 TRA_MOSFET_NCHN_8P 31
Q3323 TRA_MOSFET_NCHN_8P 31
Q4801 TRA_2N7002DW 36
Q4802 TRA_2N3904 36
Q4803 TRA_2N7002 36
Q5030 TRA_SI7392DP 38
Q5031 TRA_MOSFET_NCHN_8P 38
Q5100 TRA_SI3446DV 39
Q5907 TRA_2N7002DW 42
Q5909 TRA_2N7002DW 19 42
Q5925 TRA_2N7002DW 42
Q5926 TRA_TP0610 42
Q5930 TRA_2N3904 42
Q5933 TRA_TP0610 42
Q5935 TRA_2N3904 42
Q5975 TRA_SI3443DV 42
Q5977 TRA_2N7002 42
Q5984 TRA_FDG6324L 42
R500 RES 5
R501 RES 5
R502 RES 5
R503 RES 5
R504 RES 5
R505 RES 5
R599 RES 5
R705 RES 7
R706 RES 7
R708 RES 7
R709 RES 7
R710 RES 7
R711 RES 7
R712 RES 7
R713 RES 7
R715 RES 7
R719 RES 7
R720 RES 7
R754 RES 7
R755 RES 7
R800 RES 8
R801 RES 8
R802 RES 8
R805 RES 8
R806 RES 8
R810 RES 8
R811 RES 8
R812 RES 8
R820 RES 8
R821 RES 8
R822 RES 8
R823 RES 8
R824 RES 8
R825 RES 8
R826 RES 8
R827 RES 8
R828 RES 8
R829 RES 8
R830 RES 8
R850 RES 8
R851 RES 8
R880 RES 8
R881 RES 8
R882 RES 8
R890 RES 8
R891 RES 8
R892 RES 8
R895 RES 8
R896 RES 8
R897 RES 8
R898 RES 8
R899 RES 8
R940 RES 9
R941 RES 9
R950 RES 9
R951 RES 9
R952 RES 9
R953 RES 9
R954 RES 9
R955 RES 9
R956 RES 9
R957 RES 9
R958 RES 9
R970 RES 9
R971 RES 9
R1031 RES 10
R1032 RES 10
R1033 RES 10
R1035 RES 10
R1036 RES 10
R1050 RES 10
R1052 RES 10
R1053 RES 10
R1070 RES 10
R1071 RES 10
R1072 RES 10
R1073 RES 10
R1080 RES 10
R1081 RES 10
R1082 RES 10
R1083 RES 10
R1100 RES 11
R1102 RES 11
R1103 RES 11
R1120 RES 11
R1121 RES 11
R1122 RES 11
R1123 RES 11
R1131 RES 11
R1132 RES 11
R1133 RES 11
R1135 RES 11
R1136 RES 11
R1140 RES 11
R1141 RES 11
R1142 RES 11
R1143 RES 11
R1161 RES 11
R1162 RES 11
R1163 RES 11
R1164 RES 11
R1166 RES 11
R1171 RES 11
R1250 RES 12
R1251 RES 12
R1260 RES 12
R1261 RES 12
R1262 RES 12
R1263 RES 12
R1265 RES 12
R1266 RES 12
R1290 RES 12
R1291 RES 12
R1292 RES 12
R1293 RES 12
R1294 RES 12
R1295 RES 12
R1296 RES 12
R1297 RES 12
R1298 RES 12
R1300 RES 13
R1302 RES 13
R1304 RES 13
R1310 RES 13
R1311 RES 13
R1312 RES 13
051-6532 03
103102
Preliminary
Page 66
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
103
R1313 RES 13
R1315 RES 13
R1316 RES 13
R1317 RES 13
R1322 RES 13
R1325 RES 13
R1327 RES 13
R1399 RES 13
R1400 RES 14
R1401 RES 14
R1402 RES 14
R1403 RES 14
R1410 RES 14
R1411 RES 14
R1412 RES 14
R1420 RES 14
R1421 RES 14
R1422 RES 14
R1429 RES 14
R1430 RES 14
R1435 RES 14
R1436 RES 14
R1437 RES 14
R1440 RES 14
R1441 RES 14
R1448 RES 14
R1449 RES 14
R1450 RES 14
R1451 RES 14
R1458 RES 14
R1459 RES 14
R1465 RES 14
R1466 RES 14
R1467 RES 14
R1469 RES 14
R1500 RES 15
R1510 RES 15
R1511 RES 15
R1515 RES 15
R1516 RES 15
R1520 RES 15
R1521 RES 15
R1525 RES 15
R1526 RES 15
R1530 RES 15
R1531 RES 15
R1535 RES 15
R1536 RES 15
R1591 RES 15
R1592 RES 15
R1600 RES 17
R1601 RES 17
R1610 RES 17
R1611 RES 17
R1620 RES 17
R1621 RES 17
R1690 RES 16
R1691 RES 16
R2010 RES 18
R2011 RES 18
R2015 RES 18
R2016 RES 18
R2018 RES 18
R2019 RES 18
R2020 RES 18
R2021 RES 18
R2028 RES 18
R2029 RES 18
R2030 RES 18
R2031 RES 18
R2040 RES 18
R2041 RES 18
R2050 RES 18
R2051 RES 18
R2080 RES 18
R2081 RES 18
R2082 RES 18
R2083 RES 18
R2110 RES 19
R2111 RES 19
R2112 RES 19
R2113 RES 19
R2114 RES 19
R2115 RES 19
R2116 RES 19
R2130 RES 17
R2131 RES 17
R2132 RES 17
R2150 RES 19
R2191 RES 19
R2192 RES 19
R2193 RES 19
R2199 RES 19
R2400 RES 22
R2401 RES 22
R2402 RES 22
R2403 RES 22
R2405 RES 22
R2406 RES 22
R2407 RES 22
R2408 RES 22
R2409 RES 22
R2418 RES 22
R2419 RES 22
R2420 RES 22
R2421 RES 22
R2422 RES 22
R2423 RES 22
R2424 RES 22
R2426 RES 22
R2429 RES 22
R2431 RES 22
R2433 RES 22
R2435 RES 22
R2436 RES 22
R2438 RES 22
R2442 RES 22
R2443 RES 22
R2444 RES 22
R2500 RES 23
R2501 RES 23
R2505 RES 23
R2510 RES 23
R2520 RES 23
R2530 RES 23
R2550 RES 23
R2551 RES 23
R2552 RES 23
R2553 RES 23
R2554 RES 23
R2555 RES 23
R2556 RES 23
R2557 RES 23
R2558 RES 23
R2559 RES 23
R2560 RES 23
R2561 RES 23
R2562 RES 23
R2563 RES 23
R2564 RES 23
R2565 RES 23
R2566 RES 23
R2567 RES 23
R2568 RES 23
R2575 RES 23
R2576 RES 23
R2578 RES 23
R2579 RES 23
R2580 RES 23
R2590 RES 23
R2601 RES 24
R2603 RES 24
R2605 RES 24
R2607 RES 24
R2609 RES 24
R2700 RES 25
R2701 RES 25
R2702 RES 25
R2703 RES 25
R2704 RES 25
R2705 RES 25
R2706 RES 25
R2707 RES 25
R2709 RES 25
R2711 RES 25
R2715 RES 25
R2717 RES 25
R2719 RES 25
R2720 RES 25
R2722 RES 25
R2724 RES 25
R2738 RES 25
R2740 RES 25
R2742 RES 25
R2744 RES 25
R2746 RES 25
R2748 RES 25
R2750 RES 25
R2752 RES 25
R2754 RES 25
R2756 RES 25
R2758 RES 25
R2761 RES 25
R2762 RES 25
R2764 RES 25
R2768 RES 25
R2770 RES 25
R2772 RES 25
R2775 RES 25
R2776 RES 25
R2779 RES 25
R2800 RES 26
R2801 RES 26
R2802 RES 26
R2803 RES 26
R2804 RES 26
R2805 RES 26
R2806 RES 26
R2901 RES 27
R2902 RES 27
R2903 RES 27
R2904 RES 27
R2905 RES 27
R2906 RES 27
R2907 RES 27
R2908 RES 27
R2909 RES 27
R2910 RES 27
R2911 RES 27
R3000 RES 28
R3001 RES 28
R3002 RES 28
R3003 RES 28
R3004 RES 28
R3005 RES 28
R3006 RES 28
R3007 RES 28
R3008 RES 28
R3009 RES 28
R3010 RES 28
R3012 RES 28
R3014 RES 28
R3016 RES 28
R3018 RES 28
R3020 RES 28
R3022 RES 28
R3024 RES 28
R3026 RES 28
R3028 RES 28
R3030 RES 28
R3031 RES 28
R3032 RES 28
R3033 RES 28
R3034 RES 28
R3035 RES 28
R3036 RES 28
R3037 RES 28
R3038 RES 28
R3039 RES 28
R3040 RES 28
R3041 RES 28
R3042 RES 28
R3043 RES 28
R3044 RES 16
R3045 RES 28
R3046 RES 16
R3047 RES 28
R3048 RES 16
R3049 RES 28
R3050 RES 16
R3051 RES 28
R3052 RES 16
R3053 RES 28
R3054 RES 16
R3055 RES 28
R3057 RES 28
R3059 RES 28
R3061 RES 28
R3063 RES 28
R3065 RES 28
R3067 RES 28
R3068 RES 28
R3069 RES 28
R3070 RES 16
R3071 RES 28
R3073 RES 28
R3075 RES 28
R3077 RES 28
R3079 RES 28
R3081 RES 28
R3083 RES 28
R3085 RES 28
R3087 RES 28
R3089 RES 28
R3091 RES 28
R3093 RES 28
R3095 RES 28
R3097 RES 28
R3099 RES 28
R3101 RES 29
R3103 RES 29
R3105 RES 29
R3127 RES 29
R3129 RES 29
R3131 RES 29
R3132 RES 29
R3300 RES 31
R3301 RES 31
R3302 RES 31
R3303 RES 31
R3304 RES 31
R3305 RES 31
R3306 RES 31
R3307 RES 31
R3309 RES 31
R3310 RES 31
R3311 RES 31
R3312 RES 31
R3316 RES 31
R3318 RES 31
R3319 RES 31
R3320 RES 31
R3321 RES 31
R3322 RES 31
R3326 RES 31
R3328 RES 31
R3329 RES 31
R3330 RES 31
R3331 RES 31
R3332 RES 31
R3333 RES 31
R3340 RES 31
R3341 RES 31
R3360 RES 31
R3361 RES 31
R3366 RES 31
R3370 RES 31
R3371 RES 31
R3397 RES 31
R3398 RES 31
R3399 RES 31
R3600 RES 32
R3610 RES 32
R3611 RES 32
R3620 RES 32
R3621 RES 32
R3630 RES 32
R3631 RES 32
R3635 RES 32
R3636 RES 32
R3639 RES 32
R3640 RES 32
R3655 RES 32
R3656 RES 32
R3660 RES 32
R3661 RES 32
R3662 RES 32
R3665 RES 32
R3666 RES 32
R3669 RES 32
R3670 RES 32
R3671 RES 32
R3672 RES 32
R3675 RES 32
R3676 RES 32
R3677 RES 32
R3679 RES 32
R3699 RES 32
R3700 RES 33
R3701 RES 33
R3702 RES 33
R3840 RES 34
R3841 RES 34
R3842 RES 34
R4000 RES 35
R4001 RES 35
R4800 RES 36
R4801 RES 36
R4802 RES 37
R4803 RES 37
R4807 RES 36
R4808 RES 36
R4809 RES 36
R4810 RES 36
R4811 RES 36
R4812 RES 36
R4813 RES 36
R4900 RES 37
R4901 RES 37
R4902 RES 37
R4904 RES 37
R4905 RES 37
R4906 RES 37
R4907 RES 37
R4908 RES 37
R4909 RES 37
R4910 RES 37
R4911 RES 37
R4912 RES 37
R4913 RES 37
R4914 RES 37
R4920 RES 37
R4923 RES 37
R4924 RES 37
R4980 RES 37
R4981 RES 37
R4982 RES 37
R4985 RES 37
R4990 RES 37
R4991 RES 37
R4992 RES 37
R4993 RES 37
R4995 RES 37
R5001 RES 38
R5002 RES 38
R5003 RES 38
R5004 RES 38
R5005 RES 38
R5006 RES 38
R5007 RES 38
R5008 RES 38
R5009 RES 38
R5010 RES 38
R5011 RES 38
R5012 RES 38
R5013 RES 38
R5014 RES 38
R5015 RES 38
R5016 RES 38
R5017 RES 38
R5018 RES 38
R5019 RES 38
R5034 RES 38
R5100 RES 39
R5101 RES 39
R5102 RES 39
R5103 RES 39
R5104 RES 39
R5105 RES 39
R5106 RES 39
R5107 RES 39
R5108 RES 39
R5109 RES 39
R5110 RES 39
R5111 RES 39
R5112 RES 39
R5113 RES 39
R5114 RES 39
R5115 RES 39
R5116 RES 39
R5117 RES 39
R5118 RES 39
R5119 RES 39
R5120 RES 39
R5121 RES 39
R5122 RES 39
R5123 RES 39
R5124 RES 39
R5125 RES 39
R5126 RES 39
R5127 RES 39
R5128 RES 39
R5129 RES 39
R5200 RES 40
R5201 RES 40
R5280 RES 40
R5700 RES 41
R5701 RES 41
R5702 RES 41
R5703 RES 41
R5704 RES 41
R5705 RES 41
R5707 RES 41
R5708 RES 41
R5709 RES 41
R5710 RES 41
R5711 RES 41
R5712 RES 41
R5713 RES 41
R5714 RES 41
R5740 RES 41
R5741 RES 41
R5745 RES 41
R5746 RES 41
R5750 RES 41
R5751 RES 41
R5752 RES 41
R5753 RES 41
R5754 RES 41
R5755 RES 41
R5756 RES 41
R5757 RES 41
R5758 RES 41
R5760 RES 41
R5761 RES 41
R5762 RES 41
R5763 RES 41
R5764 RES 41
R5765 RES 41
R5766 RES 41
R5767 RES 41
R5900 RES 42
R5901 RES 42
R5902 RES 42
R5903 RES 42
R5904 RES 42
R5905 RES 42
R5906 RES 42
R5907 RES 42
R5908 RES 42
R5909 RES 42
R5913 RES 42
R5914 RES 42
R5920 RES 42
R5921 RES 42
R5922 RES 42
R5923 RES 42
R5925 RES 42
R5926 RES 42
R5927 RES 42
R5928 RES 42
R5929 RES 42
R5930 RES 42
R5933 RES 42
R5934 RES 42
R5935 RES 42
R5972 RES 42
R5973 RES 42
R5976 RES 42
R5977 RES 42
R5984 RES 42
R5999 RES 42
R6000 RES 43
R6001 RES 43
R6002 RES 43
R6003 RES 43
R6004 RES 43
R6005 RES 43
R6200 RES 44
R6210 RES 44
R6250 RES 44
R6251 RES 44
R6252 RES 44
R6253 RES 44
R6254 RES 44
R6255 RES 44
R7450 RES 45
R7455 RES 45
R7500 RES 46
R7501 RES 46
R7502 RES 46
R7600 RES 47
R7601 RES 47
R7713 RES 48
R7714 RES 48
R7715 RES 48
R7716 RES 48
R7802 RES 49
R7803 RES 49
R7804 RES 49
R7805 RES 49
R7806 RES 49
R7808 RES 49
R7809 RES 49
R8000 RES 50
R8001 RES 50
R8002 RES 50
R8003 RES 50
R8004 RES 50
R8005 RES 50
R8160 RES 51
R8170 RES 51
R8171 RES 51
R8172 RES 51
R8173 RES 51
R8174 RES 51
R8175 RES 51
R8179 RES 51
R8198 RES 51
R8300 RES 52
R8301 RES 52
R8302 RES 52
R8304 RES 52
R8305 RES 52
R8307 RES 52
R8308 RES 52
R8309 RES 52
R8350 RES 52
R8351 RES 52
R8352 RES 52
R8354 RES 52
R8355 RES 52
R8357 RES 52
R8358 RES 52
R8359 RES 52
R8363 RES 52
R8365 RES 52
R8400 RES 53
R8401 RES 53
R8402 RES 53
R8600 RES 54
R8601 RES 54
R8602 RES 54
R8609 RES 54
R8613 RES 54
R8614 RES 54
R8615 RES 54
R8616 RES 54
R8617 RES 54
R8618 RES 54
R8619 RES 54
R8620 RES 54
R8621 RES 54
R8650 RES 54
R8705 RES 55
R8706 RES 55
R8707 RES 55
R8708 RES 55
R8710 RES 55
R8800 RES 56
R8900 RES 57
R8901 RES 57
R8902 RES 57
R8903 RES 57
R8904 RES 57
R8909 RES 57
R8911 RES 57
R8912 RES 57
R8914 RES 57
R8915 RES 57
R8916 RES 57
R8921 RES 57
R8956 RES 57
R9010 RES 58
R9011 RES 58
R9020 RES 58
R9050 RES 58
R9051 RES 58
R9052 RES 58
R9053 RES 58
R9054 RES 58
R9060 RES 58
R9061 RES 58
R9062 RES 58
R9063 RES 58
R9064 RES 58
R9070 RES 58
R9090 RES 58
R9100 RES 59
R9101 RES 59
R9102 RES 59
R9103 RES 59
R9104 RES 59
R9105 RES 59
R9106 RES 59
R9107 RES 59
R9108 RES 59
R9109 RES 59
R9110 RES 59
R9135 RES 59
R9138 RES 59
R9139 RES 59
R9140 RES 59
R9141 RES 59
R9145 RES 59
R9400 RES 60
R9410 RES 60
R9411 RES 60
R9504 RES 61
R9505 RES 61
R9507 RES 61
R9511 RES 61
R9515 RES 61
RD2111 PHOTODIODE_2P 19
RP2060 RPAK4P 18
RP2080 RPAK4P 18
RP2085 RPAK4P 18
RP2510 RPAK4P 23
RP2520 RPAK4P 23
RP2530 RPAK4P 23
RP2550 RPAK4P 23
RP2551 RPAK4P 23
RP2552 RPAK4P 23
RP2553 RPAK4P 23
RP3300 RPAK4P 31
RP3800 RPAK4P 34
RP3801 RPAK4P 34
RP3810 RPAK4P 34
RP3820 RPAK4P 34
RP3830 RPAK4P 34
RP3831 RPAK4P 34
RP3832 RPAK4P 34
RP3833 RPAK4P 34
RP3850 RPAK4P 34
RP5702 RPAK2P 41
RP5703 RPAK2P 41
RP5704 RPAK2P 41
RP5706 RPAK2P 41
RP5707 RPAK2P 41
RP5708 RPAK2P 41
RP5709 RPAK2P 41
RP5710 RPAK2P 41
RP5711 RPAK2P 41
RP5712 RPAK2P 41
RP5713 RPAK2P 41
RP5714 RPAK2P 41
RP5715 RPAK2P 41
RP5716 RPAK2P 41
RP5717 RPAK2P 41
RP7400 RPAK4P 45
RP7401 RPAK4P 45
RP7402 RPAK4P 45
RP7702 RPAK4P 48
RP7703 RPAK4P 48
RP7800 RPAK10P2C 49
RP8000 RPAK4P 50
RP8001 RPAK4P 50
RP8002 RPAK4P 50
RP8003 RPAK4P 50
RP8004 RPAK4P 50
RP8170 RPAK4P 51
RP8171 RPAK4P 51
RP8172 RPAK4P 51
RP8173 RPAK4P 51
RP8174 RPAK4P 51
RP8400 RPAK4P 53
RP8401 RPAK4P 53
RP8900 RPAK4P 57
RP8901 RPAK4P 57
RP9110 RPAK4P 59
SP500 SPKR_CLIP_P84 17
SP501 SPKR_CLIP_P84 17
SP502 SPKR_CLIP_P84 17
SP503 SPKR_CLIP_P84 17
SP504 SPKR_CLIP_P84 17
SP505 SPKR_CLIP_P84 17
SP9900 SPKR_CLIP_P84 17
SW2100 SWI_4W219SM_H63 19
T8700 XFR_ENET_1000BT 55
U3 U3LITE 20 22 26 33 36 43
U710 COMPARATOR_LMC7211 7
U800 MAX1535 8
U940 VREG_LP3982 9
U950 LTC3412 9
U970 TPS62050 9
U1000 TPS5120 10
U1100 TPS5120 11
U1160 VREG_LP2951 11
U1170 VREG_LP2951 11
U1270 VREG_LM2594 12
U1280 VREG_MM1572FN 12
U1290 LTC3411 12
U1300 M30280F8 13
U1301 DS1338 13
U1500 MAX1668 15
U2015 COMPARATOR_LM339A 18
U2110 OPAMP_MAX4236EUTT 19
U2150 MAX1561 19
U2300 SHASTA 21 23 44 45 50 53 56 59
U2600 PULSAR 24 25
U2900 GPUL 27 29
U3300 MAX1544 31
U3630 OPAMP_LMV2011 32
U3660 OPAMP_LMV2011 32
U3669 OPAMP_LMV2011 32
U3670 OPAMP_LMV2011 32
U4900 RAGE_MBLTY_M10_CSP64_667 37 39 40
U4990 CLK_GEN_CY25811 37
U5000 MAX1993 38
U5280 VREG_MM1571J 40
U5290 VREG_MM1571J 40
U5700 SIL1178 41
U5913 741G32 42
U5914 741G32 42
U5920 COMPARATOR_LMC7211 42
U5983 741G32 42
U7450 MC74VHC1G08 45
U7500 FEPR_1MX8 46
U7700 UPD720101_FBGA_SPLIT 48 59
U7800 PCI1510GGU 49
U7801 PWR_CNTRL_TPS2211 49
U8150 88SA8040 51
U8198 741G14 51
U8199 741G14 51
U8600 BCM5462 12 54 57
U8950 EEPROM_16KX8_M24128B 57
VR3100 VREG_MM1572FN 29
XW510 JUMPER 5
XW518 JUMPER 5
XW520 JUMPER 5
XW530 JUMPER 5
XW540 JUMPER 5
XW552 JUMPER 5
XW560 JUMPER 5
XW561 JUMPER 5
XW590 JUMPER 5
XW591 JUMPER 5
XW592 JUMPER 5
XW800 SHORT 8
XW950 SHORT 9
XW1003 SHORT 10
XW1104 SHORT 11
XW1290 SHORT 12
XW1300 SHORT 13
XW1470 SHORT 14
XW3100 SHORT 29
XW3300 SHORT 31
XW3310 SHORT 31
XW3320 SHORT 31
XW3360 SHORT 31
XW3361 SHORT 31
XW3600 SHORT 32
XW3610 SHORT 32
XW3611 SHORT 32
XW3620 SHORT 32
XW3621 SHORT 32
XW3630 SHORT 32
XW3640 SHORT 32
XW3650 SHORT 32
XW3651 SHORT 32
XW5001 SHORT 38
XW5190 SHORT 39
XW5191 SHORT 39
XW5192 SHORT 39
XW5193 SHORT 39
XW5194 SHORT 39
XW5290 SHORT 40
XW5291 SHORT 40
XW5292 SHORT 40
XW5293 SHORT 40
XW5960 SHORT 42
XW5961 SHORT 42
XW7800 SHORT 49
XW9500 SHORT 61
XW9503 SHORT 61
XW9505 SHORT 61
Y1300 CRYSTAL 13
Y1301 CRYSTAL_4PIN 13
Y2590 CRYSTAL 23
Y2701 CRYSTAL 25
Y8600 CRYSTAL 54
Y8920 CRYSTAL 57
Y9145 CRYSTAL 59
ZT500 MTGHOLE 17
ZT501 MTGHOLE 17
ZT502 MTGHOLE 17
ZT503 MTGHOLE 17
ZT504 MTGHOLE 17
ZT505 MTGHOLE 17
ZT510 MTGHOLE 17
ZT511 MTGHOLE 17
ZT2800 HOLE_VIA 26
ZT2801 HOLE_VIA 26
ZT2802 HOLE_VIA 26
ZT2803 HOLE_VIA 26
ZT2804 HOLE_VIA 26
ZT2805 HOLE_VIA 26
ZT2806 HOLE_VIA 26
ZT2807 HOLE_VIA 26
ZT2808 HOLE_VIA 26
ZT2809 HOLE_VIA 26
ZT2810 HOLE_VIA 26
ZT2811 HOLE_VIA 26
ZT2812 HOLE_VIA 26
ZT2813 HOLE_VIA 26
ZT2814 HOLE_VIA 26
ZT2815 HOLE_VIA 26
ZT2816 HOLE_VIA 26
ZT2817 HOLE_VIA 26
ZT2818 HOLE_VIA 26
ZT2819 HOLE_VIA 26
ZT2820 HOLE_VIA 26
ZT2821 HOLE_VIA 26
ZT2822 HOLE_VIA 26
ZT2823 HOLE_VIA 26
ZT2824 HOLE_VIA 26
ZT2825 HOLE_VIA 26
ZT2826 HOLE_VIA 26
ZT2827 HOLE_VIA 26
ZT2828 HOLE_VIA 26
ZT2829 HOLE_VIA 26
ZT2830 HOLE_VIA 26
ZT2831 HOLE_VIA 26
ZT2832 HOLE_VIA 26
ZT2833 HOLE_VIA 26
ZT2834 HOLE_VIA 26
ZT2835 HOLE_VIA 26
ZT2836 HOLE_VIA 26
ZT2837 HOLE_VIA 26
ZT2838 HOLE_VIA 26
ZT2839 HOLE_VIA 26
ZT2840 HOLE_VIA 26
ZT2841 HOLE_VIA 26
ZT2842 HOLE_VIA 26
ZT2843 HOLE_VIA 26
ZT2844 HOLE_VIA 26
ZT2845 HOLE_VIA 26
ZT2846 HOLE_VIA 26
ZT2847 HOLE_VIA 26
ZT2848 HOLE_VIA 26
ZT2849 HOLE_VIA 26
ZT2850 HOLE_VIA 26
ZT2851 HOLE_VIA 26
ZT2852 HOLE_VIA 26
ZT2853 HOLE_VIA 26
ZT2854 HOLE_VIA 26
ZT2855 HOLE_VIA 26
ZT2856 HOLE_VIA 26
ZT2857 HOLE_VIA 26
ZT2858 HOLE_VIA 26
ZT2859 HOLE_VIA 26
ZT2860 HOLE_VIA 26
ZT2861 HOLE_VIA 26
ZT2862 HOLE_VIA 26
ZT2863 HOLE_VIA 26
ZT2864 HOLE_VIA 26
ZT2865 HOLE_VIA 26
ZT2866 HOLE_VIA 26
ZT2867 HOLE_VIA 26
ZT2868 HOLE_VIA 26
ZT2869 HOLE_VIA 26
ZT9900 HOLE_VIA 17
ZT9901 HOLE_VIA 17
ZT9902 HOLE_VIA 17
ZT9903 HOLE_VIA 17
051-6532 03
103103
Preliminary
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