How it Works
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IMAC M51
Schematics
69 pgs2.31 Mb0
Schematics
69 pgs2.3 Mb0

Apple IMAC M51 Schematics

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CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
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3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
DATE
APPD
ENG
DATE
APPD
CK
ECN
ZONE
REV
DO NOT SCALE DRAWING
X.XXX
X.XX
XX
DIMENSIONS ARE IN MILLIMETERS
THIRD ANGLE PROJECTION
D
SIZE
APPLICABLE
NOTED AS
MATERIAL/FINISH
NONE
SCALE
DESIGNER
MFG APPD
DESIGN CK
RELEASE
QA APPD
ENG APPD
DRAFTER
METRIC
OF
SHT
DRAWING NUMBER
TITLE
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
Apple Computer Inc.
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
DESCRIPTION OF CHANGE
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CURRENT: REV D 10/17 SCH: REV G
SANTANA - M51 MLB
Schematic / PCB #’s
NEW 630 BOMS AS OF 9/7
PRODUCTION RELEASED
08/04/2006
Power Block Diagram
3
M51_PAUL
3
NB CPU Interface
12 12
08/04/2006
M50_HENRY
55
FUNC TEST 1 OF 2
08/04/2006
M51_HENRY
7
CPU 1 OF 2-FSB
08/04/2006
7
M50_HENRY
CPU 2 OF 2-PWR/GND
08/04/2006
88
M50_HENRY
08/04/2006
M51_DOUG
FW: 1394B-LINK/PHY
4438
68
08/04/2006
AUDIO: CODEC
51
AUDIO
11
M50_HENRY
11
CPU ITP700FLEX DEBUG
08/04/2006
08/04/2006
69
AUDIO: LINE INPUT AMP
52
AUDIO
CSA MASTER DATEPDF
CONTENTS
AUDIO: SPEAKER AMP_1
71
08/04/2006
54
AUDIO
FIREWIRE CONNECTORS
46
08/04/2006
40
M51_DOUG
08/04/2006
26
M50_DOUG
26
SB: MISC
M51_PAUL7808/04/2006
3V DC/DC 2.5V
61
1
PCB,SCHEM,MLB,M51
051-7039 SCH1
1
PCB,FAB,MLB,M51
820-1984 MLB1
39 45
08/04/2006
FW: 1394B MISC
M51_DOUG
47
08/04/2006
USB Device Interfaces
41
M51_DOUG
08/04/2006
5443
M51_DOUG
PCI-E CONNECTIONS
SMC & TPM SUPPORT
59
07/31/2006
45
M51_HENRY
60
08/04/2006
LPC+ CONN
46
M51_HENRY
08/04/2006
70
AUDIO: COMBO OUT AMP
53
AUDIO
72
08/04/2006
AUDIO: SPEAKER AMP
55
AUDIO
73
08/04/2006
AUDIO: CONNECTORS
56
AUDIO
74
08/04/2006
AUDIO: POWER SUPPLIES
57
AUDIO
75
08/04/2006
IMVP6 CPU VCore Regulator
58
M51_PAUL
76
(MASTER)
CPU & SYSTEM SENSE
59
M51_DAVE
77
08/04/2006
PWR GOOD
60
M51_PAUL
79
08/04/2006
1.8V & 1.2V VREG
62
M51_PAUL
S0 AND S3 FETS
83
08/04/2006
65
M51_PAUL
84
(MASTER)
MXM PCI-E & PWR
66
M51_DAVE
85
(MASTER)
MXM I/O
67
M51_DAVE
94
(MASTER)
Internal Display Conns
68
M51_DAVE
97
(MASTER)
External Display Conns
69
M51_DAVE
M51_HENRY
08/04/2006
99
CPU DECAPS & VID<>
ASIC TEMP SENSORS
(MASTER)
10
M51_DAVE
10
08/04/2006
13
M50_HENRY
13
NB PEG / Video Interfaces
14
M50_HENRY
14
NB Misc Interfaces
08/04/2006
08/04/2006
15
M50_HENRY
15
NB DDR2 Interfaces
08/04/2006
16
M51_HENRY
16
NB Power 1
NB Power 2
08/04/2006
17
M51_HENRY
17
08/04/2006
18
M50_HENRY
18
NB Grounds
(MASTER)
19
M51_DAVE
19
NB (GM) Decoupling
08/04/2006
21
M50_DOUG
21
SB: 1 OF 4
SB: 2 OF 4
08/04/2006
22
M51_DOUG
22
08/04/2006
23
M51_DOUG
23
SB: 3 OF 4
08/04/2006
24
M50_DOUG
24
SB: 4 OF 4
08/04/2006
25
M51_DOUG
25
SB:DECOUPLING
(MASTER)
27
M51_DAVE
27
M51 SMBus Connections
08/04/2006
28
M51_HENRY
28
DDR2 SO-DIMM Connector A
08/04/2006
29
M51_HENRY
29
DDR2 SO-DIMM Connector B
08/04/2006
30
M50_HENRY
30
Memory Active Termination
31
08/04/2006
M50_HENRY
31
Memory Vtt Supply
08/04/2006
32
M50_HENRY
33 CLOCKS
08/04/2006
33
M51_HENRY
34
CLOCKS: TERMINATIONS
08/04/2006
34
M51_DOUG
38
Disk Connectors
08/04/2006
36
M51_DOUG
42
ETHERNET MISC
08/04/2006
37
M51_DOUG
43
ETHERNET CONNECTOR
M51_HENRY
08/04/2006
65
HD AND OD FAN
48
42
AIRPORT CONN
53
08/04/2006
M51_DOUG
58
08/04/2006
SMC44
M51_HENRY
82
08/04/2006
5V DC/DC
64
M51_PAUL
1.5V_S0 & 1.05V_S0 VREG
80
08/04/2006
63
M51_PAUL
08/04/2006
35
M50_DOUG
41
ETHERNET CONTROLLER
NB Config Straps
08/04/2006
20
M50_HENRY
20
M51_HENRY
TPM67
08/04/2006
50
POWER CONN / MISC
M51_PAUL
08/04/2006
66
CSAPDF MASTER
CONTENTS
DATE
2
M51_PAUL
08/04/2006
System Block Diagram
2
M51_HENRY
08/04/2006
CPU FAN, HD & OD TEMP
49 66
63
08/04/2006
SPI BOOTROM
47
M50_DOUG
BOM Config
M51_DAVE (MASTER)
44
051-7039
SCHEM SANTANA
H
1
97
10/17/06 06/22/04
H
468168 PRODUCTION RELEASED
www.Vinafix.vn
Preliminary
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
SEE I2C PG 27
TEMP SENSE
PG 3
POWER SENSE
SEE POWER BLOCK DIAGRAM
ADC
PAGE 28-29
B,0
A
SMB
U5800
FAN
PAGE 27
CORE (1.05V)
CK410M
PAGE 22
PAGE 63
CONTROL = 2.5V
64-BIT
1.8V/667MHZ
DDR2 - DUAL CHAN
J2800
AZALIA
U6800
STA9221
PAGE 68
PORT A
J2901 ALS+AMBIENT TSENS P. 59
U6300/01
FSB
USB
CONNECTORS
CAMERA
JE310/JE320/JE330
PAGE 47
4-BIT (3.3V/33MHZ)
PAGE 67
CAMERA
PAGE 47
JE351
IR RCV
PAGE 58
IR
7
PAGE 47
J5300 (AIRPORT CONN)
TPM
LPC+
JE350
NB- GM
(TMDS - VGA)
2 Diff pairs
JE000, JE001
FIREWIRE B CONNECTORS
PAGE 21
PAGE 14
DMI
PAGE 16-17
CORE (1.05V)
J5300
0
1.2V/1.5GHZ
PAGE 15
PCI-E
PAGE 12
U1200
MAIN MEMORY
PAGE
6DUAL CHANNEL LVDS - 6BIT
MXM CONNECTOR
LVDS
PAGE 97 PAGE 94
8-BIT
TSB82AA2
33MHZ
PAGE 46
3.3V/133MHZ
PAGE 38
OPTICAL
CONNECTOR
PCI-E
UATA
PAGES 84-85
J8400
U2100
667MHZ
J0700
CORE
CONNECTOR
SATA
JC900
(1.83/2.17GHZ)
PAGE 7
PAGE 8
CORE (~1.2V)
CPU
MINI-DVI
(INTERNAL)
J9402J9700
SB
SATA2
PAGE 38
HARD DRIVE
SATA0
PAGE 21
SATA
UATA/133
UATA
JC901
PORT
#0
#2-5
PAGE 22
#1
MINI-PCIE
PAGE 53
AIRPORT
X1 - 1.5GHZ
X1 - 1.5GHZ
YUKON
GIG ETHERNET
ETHERNET CONNECTOR
JD600
PAGE 43
U4101
PAGE 41
PAGES 30
PARALLEL
TERM
J2900
DIMM
PAGE 21
PORT PORT
PAGE 22
PCI
DMI
PAGE 22 PAGE 22
SPI
PAGE 21
04
J5300
3,7
2 3
156
PAGE 48
J4700
CONN
BT
USB
AIRPORT
U3301
DIMM’S
J2900
J2800
PAGE 24
GPIOS
PAGE 23
ITP CONN
J1101
PAGE 11
PAGE 60
J6000
PAGE 34
TERMS
CLOCKS
PAGE 33
CK410
U3301
64-BIT
4 Diff pairs
MISC
SPI
CONN
DMI
SMC
U6700
4-BIT
LPC
0,2,4
BOOTROM
SMB
100MHZ
FIREWIRE B
2
PAGE 45
1
TSB81BA3
32-BIT
PAGE 73
COMBO OUT CONNECTOR
J7303
OPTICAL OUT
S/PDIF
R/L SPEAKER
CONNECTORS
PAGE 73
J7301,J7302
LINE OUT
PAGE 72
SPEAKER
AMP
AUDIO CODEC
PORT B
PORT C
MIC IN
JE350
BNDI
INTERFACE
PORT F
CONNECTOR
J7303
OPTICAL IN
COMBO IN
LINE IN
PAGE 73
PAGE 44
FIREWIRE B
13
PAGE 14
1.2V/800MHZ
J6500,J6501,J6600 FAN CONNS
SYNC_DATE=08/04/2006SYNC_MASTER=M51_PAUL
2
H
051-7039
97
System Block Diagram
www.Vinafix.vn
Preliminary
OUT
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
?A PEAK
1.7A AVG
PAGE 75
SWITCHER
34A AVG
36A PEAK
CPU VCORE (1.25V)
3.5A PEAK
230W AC/DC POWER SUPPLY
5V, 3.4A PK [2.2A AVG]
U7600
ISENSE AND VSENSE
PAGE 80
SWITCHER
2.4A AVG
1.2A AVG FET PG 83
PAGE 31
1.0A PEAK
0.4A AVG LINEAR
PAGE 79
SWITCHER
6.3A AVG
14.5A PEAK
7.4A PEAK
5.5A AVG
0.4A PEAK
0.3A AVG
PAGE 79
4.5A AVG SWITCHER
8.4A PEAK
PAGE 81
12V, 14.5A PK [9.4A AVG]
MXM_PWRSRC (12V) U8450
ISENSE + VSENSE
FET PG 83
?A AVG FET PG 83
?A AVG
?A PEAK
AC/DC BOARD
1.7A PEAK
SWITCHER PAGE 82
?A PEAK ?A AVG
1.5A AVG
12V, ?A
LINEAR
0.1A PEAK
0.1A AVG
LINEAR
0.2A AVG
HDD
ODD
SWITCHER PAGE 78
3.4A AVG
6.0A PEAK
FET PG 83
AC/DC
0.3A AVG
0.4A PEAK
FET PG ?
3.0A AVG
3.3A PEAK
S5 S5
SYSTEM (12V) ISENSE AND VSENSE U7650
ALWAYS ON WHEN UNIT HAS AC POWER (TRICKLE)
ONLY ON IN RUN
"S0" RAILS
"S5" RAILS
"S3" RAILS
ON IN RUN AND SLEEP
0.6A PEAK
0.2A AVG LINEAR
GRAPHICS
0.6A PEAK
0.2A AVG
PAGE 83
LINEAR
PAGE 45
24V, ?A
FET PG 83
3.4A PEAK
2.2A AVG
FET PG 83
24V, 3.7A PK [3.3A AVG]
0.9A AVG
1.1A PEAK
FET PG 83
1.5A PEAK
LINEAR PG 82
3.3V, 7.1A PK [4.1A AVG]
0.2A PEAK
5.8A PEAK
PAGE 78
5 78
83
21
XW302
SM
OMIT
21
L300
TH-VERT-LF
1UH-20A-4.5MOHM
21
XW301
OMIT
SM
SYNC_MASTER=M51_PAUL
3 97
H
051-7039
Power Block Diagram
SYNC_DATE=08/04/2006
VOLTAGE=1.5V
PP1V5_S0
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.15MM
MAKE_BASE=TRUE
VOLTAGE=2.5V
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.15MM
PP2V5_S0
MAKE_BASE=TRUE
PP1V95_S5
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.95V
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
PP3V3_S5
MIN_NECK_WIDTH=0.2MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
VOLTAGE=2.5V
PP2V5_S5
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.3MM
=PP1V5_S0_SB_VCCSATAPLL
=PP1V5_S0_NB_3GPLL
=PP1V5_S0_SB_VCC1_5_A
=PP1V5_S0_NB_PLL
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.25MM
PP12V_S5
MIN_LINE_WIDTH=0.60MM
VOLTAGE=12V
=PP1V5_S0_CPU
=PPV_S0_MXM_PWRSRC
VOLTAGE=3.3V
PP3V3_S3
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM
=PP3V3_S3_BT =PP3V3_S3_I2C
=PP3V3_S3_FW
MIN_NECK_WIDTH=0.2MM
PP5V_S5
VOLTAGE=5V
MIN_LINE_WIDTH=0.6MM
MAKE_BASE=TRUE
=PP1V8_S3_1V2_LDO
PP1V8_S3
MIN_LINE_WIDTH=0.6MM
VOLTAGE=1.8V
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2MM
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.6MM
PP1V8_S0
VOLTAGE=1.8V
MAKE_BASE=TRUE
=PP5V_S0_MEMVTT
=PP5V_S0_AUDIO
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=5V
PP5V_S3
=PP3V3_S5_SB
=PP3V3_S5_SB_USB
=PP3V3_S5_SB_VCCSUS3_3
=PP3V3_S5_SB_VCCSUS3_3_USB
=PP3V3_S5_SB_IO
=PP5V_S0_PATA
=PP3V3_S5_DEBUG
=PP1V95_S5_FWPHY
=PP3V3_S3_TPM
=PP5V_S0_DEBUG
PP24V_S0
MIN_NECK_WIDTH=0.25MM
VOLTAGE=24V
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
PP24V_S5
VOLTAGE=24V
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM
=PPV_S0_INVERTER
=PPV_S5_FW
=PP3V3_S5_SB_PM
=PP3V3_S5_SB_3V3_1V5_VCCSUSHDA
=PP3V3_S5_FW
=PP3V3_S5_SMC
=PP3V3_S5_2V5_LDO
=PP3V3_S5_ROM
=PP5V_S0_MXM
=PP1V2_S3_LAN
=PP5V_S3_BNDI
=PP4V5_S5_AUDIO_ANALOG
MIN_LINE_WIDTH=0.6MM
MAKE_BASE=TRUE
PP4V5_S5_AUDIO_ANALOG
MIN_NECK_WIDTH=0.25MM
VOLTAGE=4.5V
=PPSPD_S0_MEM
=PP3V3_S0_VIDEO
=PP3V3_S0_TPM
=PP3V3_S0_SB_VCCLAN3_3
=PP3V3_S0_SB_VCC3_3_PCI
=PP3V3_S0_SB_VCC3_3
=PP3V3_S0_SB_PCI
=PP3V3_S0_SB_3V3_1V5_VCCHDA
=PP3V3_S0_SB
=PP3V3_S0_SATA
=PP3V3_S0_PATA
=PP3V3_S0_ODD_TSENS
=PP3V3_S0_NB_VCC_HV
=PP3V3_S0_NB
=PP3V3_S0_HD_TSENS
=PP3V3_S0_FAN
=PP3V3_S0_CK410
=PP3V3_S0_AIRPORT
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
VOLTAGE=5V
PP5V_S0
MIN_NECK_WIDTH=0.25MM
=PP3V3_S0_IMVP
=PP3V3_S0_AUDIO
=PP3V3_S3_ENET
=PP5V_S5_SB
=PP5V_S3_USB
=PP5V_S0_SB
=PP5V_S0_SATA
=PP5V_S5_AUDIO_LDO
=PPV_S0_LCD
=PP12V_S0_FAN
=PP3V3_S0_MXM
=PP3V3_S0_SB_GPIO
=PP3V3_S0_SB_VCC3_3_IDE
=PP3V3_S0_SB_PM
MAKE_BASE=TRUE
PP3V3_S0
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
MAKE_BASE=TRUE
VOLTAGE=1.8V
PP1V2_S3
=PP12V_S5_AUDIO_SPKRAMP
MAKE_BASE=TRUE
PP12V_S5_AUDIO_SPKRAMP
MIN_NECK_WIDTH=0.15MM
VOLTAGE=12V
MIN_LINE_WIDTH=0.6MM
MAKE_BASE=TRUE
PP12V_S0
=PP12V_S0_SATA
VOLTAGE=0.9V
MIN_NECK_WIDTH=0.15MM
MAKE_BASE=TRUE
PP0V9_S0
MIN_LINE_WIDTH=0.3MM
=PP1V8_S0_MXM
=PP1V8_S3_MEM_NB
=PP1V8_S0_MEMVTT
=PP1V8_S3_MEM
=PP0V9_S0_MEM_TERM
=PP0V9_S0_MEMVTT_LDO
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.6MM
MAKE_BASE=TRUE
VOLTAGE=1.25V
PPVCORE_CPU
=PPVCORE_S0_CPU
PP12V_S5_CPU_REG
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.15MM
VOLTAGE=12V
PP12V_S0_B
MIN_NECK_WIDTH=0.15MM
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
VOLTAGE=12V
VOLTAGE=1.05V
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.3MM
MAKE_BASE=TRUE
PP1V05_S0
=PPVCORE_S0_SB
=PPVCORE_S0_NB
=PP1V05_S0_SB_CPU_IO
=PP1V05_S0_NB_VTT
=PP1V05_S0_FSB_NB
=PP1V05_S0_CPU
=PP2V5_S0_NB_VCCA_3GBG
=PP2V5_S0_MXM
=PP1V5_S0_SB_VCCUSBPLL
=PP1V5_S0_SB_VCC1_5_A_USB_CORE
=PP1V5_S0_SB_VCC1_5_A_ATX
=PP1V5_S0_SB_VCC1_5_A_ARX
=PP1V5_S0_SB
=PP1V5_S0_NB_VCCD_HMPLL
=PP1V5_S0_NB_VCCAUX
=PP1V5_S0_NB_TVDAC
=PP1V5_S0_NB_PCIE
=PP1V5_S0_NB
=PP1V5_S0_AIRPORT
83 80
84
79
83
83
78
82
76
77
83 80
45 76
82 79
41 66
80 78 97
74
27 65
79
83
77 83
73
26
11
26
78
53
75
83
26
46
59
66
75
72
43
27
10
19
76
76
80
25
9
19
80
83
6
25
25
77
27
45
59
79
83
25
25
25
45
83 83
23
45
58
29
97
25
25
25
25
25
19
20
65
34
59
71
42
66
23
25
6
79
72
16
29
30
75
9
83
34
25
19
24
19
8
19
25
25
25
25
17
5
78
45
5
24
19
24
19
76
8
84
6
47
47
44
5
79
5
83
31
70
59
23
22
24
24
22
38
60
44
67
60
5 6
94
46
11
24
44
27
78
63
84
42
47
68
82
28
94
67
24
24
24
26
24
22
6
38
66
17
14
66
59
33
53
5
75
68
41
25
47
25
6
82
94
65
85
21
24
26
5
5
71
83
6
79
84
14
31
28
29
31
5
8
75
76
5
24
16
21
17
12
7
17
85
24
24
24
24
25
17
16
19
13
19
53
www.Vinafix.vn
Preliminary
DESCRIPTION
REFERENCE DES
BOM OPTION
QTY
PART NUMBER
CRITICAL
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
DESCRIPTION
REFERENCE DES
BOM OPTION
QTY
PART NUMBER
CRITICAL
TABLE_BOMGROUP_ITEM
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)
BOM OPTION
TABLE_5_HEAD
QTY
DESCRIPTION
PART#
TABLE_5_ITEM
TABLE_ALT_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
DESCRIPTION
REFERENCE DES
BOM OPTION
QTY
PART NUMBER
CRITICAL
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)
BOM OPTION
TABLE_5_HEAD
QTY
DESCRIPTION
PART#
TABLE_5_ITEM
TABLE_5_ITEM
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
BOM OPTIONS
BOM GROUP
TABLE_BOMGROUP_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
REFERENCE DESIGNATOR(S)
BOM OPTION
TABLE_5_HEAD
QTY
DESCRIPTION
PART#
TABLE_ALT_ITEM
DESCRIPTION
REFERENCE DES
BOM OPTION
QTY
PART NUMBER
CRITICAL
BOM OPTIONS
BOM NAME
BOM NUMBER
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
BOM OPTIONS
BOM NAME
BOM NUMBER
TABLE_BOMGROUP_HEAD
BOMOPTION Groups
Production BOM
BarCode Label / EEE #’s
MEROM BOM OPTION DUE TO PAGE 76 SHARING W/ M50
MUST STUFF WHEN MXM_PWR_SENSE IS NOT STUFFED (IF THIS MOVES TO DEV BOM)
BATTERY IS INSTALLED AT FATP
CHIPSET, ROMS, ETC.
Misc. Parts
(338S0274)
(335S0384)
PROCESSORS
Alternate Parts
WHEN DEVELOPMENT SENSORS ARE GONE
PULL-DOWNS FOR UNUSED PINS
WHEN DEVELOPMENT SENSORS ARE GONE
PULL-DOWNS FOR UNUSED PINS
WHEN DEVELOPMENT SENSORS ARE GONE
PULL-DOWNS FOR UNUSED PINS
MUST STUFF WHEN SYS_PWR_SENSE IS NOT STUFFED (I.E. WHEN DEVELOPMENT BOM IS NOT STUFFED)
(335S0382)
SENSOR STUFFING OPTIONS
MUST STUFF WHEN CPU_PWR_SENSE IS NOT STUFFED (IF THIS MOVES TO DEV BOM)
Development BOM
BOM Config
SYNC_DATE=(MASTER)
974
H
051-7039
SYNC_MASTER=M51_DAVE
MEROM 2.16GHZ, M51
CPU337S3390 1
M51_BETTER
CRITICAL
116S0090
RES,10K-OHM,5%,0402
NOSTUFF
C7612
1
C7602
1
NOSTUFF
116S0090
RES,10K-OHM,5%,0402
C8459
1
116S0090 PRODUCTION
RES,10K-OHM,5%,0402
IO ALIGNMENT BOARD, M51
1 PCB2820-2038 CRITICAL
IO ALIGNMENT BOARD ADHESIVE
946-0743 1 ADH1 CRITICAL
116S0090
C7650
1
RES,10K-OHM,5%,0402
PRODUCTION
1
RES,10K-OHM,5%,0402
C7650
116S0090 PRODUCTION
IC,88E8053,GIGABIT ENET XCVR,64P QFN,NO
U4101 CRITICAL338S0270 1
CRITICAL
MEROM 2.33GHZ, M51
M51_BEST337S3392 CPU1
1
PRODUCTION
RES,0-OHM,2010
R7650
102S0699
Sanyo alt for Nich.
ALL
126S0078126S0086
BAT,COIN,3V,220MAH,CR2032
BT2600 CRITICAL1 NOSTUFF742-0048
C8458
1
116S0090 PRODUCTION
RES,10K-OHM,5%,0402
RES,0-OHM,2512
R8450
107S0070
1
PRODUCTION
CPU_TSENS_INT,SYS_PWR_SENSE,MXM_PWR_SENSE
M51_DEV1
COMMON,M51_COMMON1,M51_COMMON2,ALTERNATE
M51_COMMON
CPU_TSENS_EXT,GPU_TSENS_INT,GPU_TSENS_EXT,MXM_ROM,NBCFG_PEG_REVERSE
M51_COMMON1
SB_SYSRST_4_PVT,ITP,MEROM,AMB_TSENS,CPU_PWR_SENSE
M51_COMMON2
DEVELOPMENT,M51_DEV1
M51_DEVELOPMENT
BAR CODE LABLE, MLB, M51
[EEE:WZD]
EEE_WZDCRITICAL825-6447 1
BAR CODE LABLE, MLB, M51
[EEE:WZC]
EEE_WZCCRITICAL825-6447 1
U1200 CRITICAL
IC,945PM,NORTHBRIDGE
338S0328 1
CRITICALU33011
IC,SLG84435,CLK GEN,68PIN QFN
359S0117
IC,SMC,M51
CRITICAL1 U5800341T0020
IC,EFI BOOT ROM,M51
U6301341T0019 CRITICAL1
IC,TPM,TSSOP,28P
U6700341S1789 CRITICAL TPM1
IC,ENET LAN ROM
341S1797 U41021 CRITICAL
630-7899
PCBA,MLB,2.33GHz,M51
M51_COMMON,M51_BEST,EEE_WZD,PRODUCTION
PCBA,MLB,2.16GHz,M51 M51_COMMON,M51_BETTER,EEE_WZC,PRODUCTION
630-7898
PCBA,DEVBOM,M51
603-8960
M51_DEVELOPMENT
IC,2K I2C EEPROM,MXM,M51
341S1892 CRITICALU85701 MXM_ROM
IC,CPU VREG,IMVP,TWO PHASE,SCREENED
CRITICAL353S1465 U75001
CRITICAL
IC,SB,652BGA
1 U2100343S0385
J0700 CRITICAL
IC,CPU-SKT,479BGA
1511S0025
126S0068 126S0088
Sanyo alt for Nich.
ALL
Sanyo alt for Nich.
126S0099 126S0073
ALL
124-0339124-0361
SANYO ALT
ALL
378S0141
GREEN LED ALT.
378S0140
ALL
U7500
353S1461
CPU VREG NEW REV
353S1465
ALL
CAP CONSOLIDATION
138S0567 138S0516
ALL
376S0388 376S0444
ON SEMI 2ND SRC FOR IR
DVI DDC (LITTLEFUSE)
F9710
740S0028740S0044
www.Vinafix.vn
Preliminary
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
PP
PP
PP
PP
PP
PP
PP
PP
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
PP
PP
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
PP
PP
PP
PP
PP
PP
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
LAYOUT: PLACE CLOSE TO DESTINATION
* OPPOSITE END FROM CLOCK BUFFER
FSB SIGNALS
MISC GROUND VIAS
LAYOUT NOTE: PLACE NEAR SOUTHBRIDGE
SPARE USB PORT
ALL I2C BUSSES (PLACE IN ACCESSIBLE LOCATION TOP SIDE)
LAYOUT NOTE: PLACE NEAR NORTHBRIDGE
INVERTER DOES NOT USE THIS SIGNAL
1
PP6C5
OMIT
SM
P4MM
1
PP6C4
P4MM
SM
OMIT
1
PP6C6
SM
OMIT
P4MM
1
PP6C8
SM
P4MM
OMIT
1
PP6C7
OMIT
P4MM
SM
1
PP6D0
SM
P4MM
OMIT
1
PP6D3
SM
P4MM
OMIT
1
PP6D4
SM
P4MM
OMIT
1
PP6D8
P4MM
SM
OMIT
1
PP6D9
SM
OMIT
P4MM
1
PP6E0
P4MM
OMIT
SM
1
PP6E1
P4MM
OMIT
SM
58 59 60
58 59 60
58 59 60
58 59 60
58 60
7
11
7
11
7
11
7
11
7
11
58 59 60
58 59 60
59
5
59
5
26
1
ZH500
HOLE-VIA
1
ZH501
HOLE-VIA
1
ZH502
HOLE-VIA
1
ZH503
HOLE-VIA
1
ZH504
HOLE-VIA
1
ZH505
HOLE-VIA
1
ZH506
HOLE-VIA
1
ZH507
HOLE-VIA
1
ZH508
HOLE-VIA
1
ZH509
HOLE-VIA
1
ZH510
HOLE-VIA
1
ZH511
HOLE-VIA
1
ZH512
HOLE-VIA
1
ZH513
HOLE-VIA
1
ZH514
HOLE-VIA
1
ZH515
HOLE-VIA
1
ZH516
HOLE-VIA
1
ZH517
HOLE-VIA
1
ZH518
HOLE-VIA
1
ZH519
HOLE-VIA
1
ZH520
HOLE-VIA
1
ZH521
HOLE-VIA
1
ZH522
HOLE-VIA
1
ZH523
HOLE-VIA
1
ZH524
HOLE-VIA
1
ZH525
HOLE-VIA
1
ZH526
HOLE-VIA
1
ZH527
HOLE-VIA
1
ZH528
HOLE-VIA
1
ZH529
HOLE-VIA
1
PP600
SM
OMIT
P4MM
1
PP601
SM
P4MM
OMIT
1
PP604
SM
OMIT
P4MM
1
PP605
OMIT
P4MM
SM
1
PP611
SM
OMIT
P4MM
1
PP610
P4MM
OMIT
SM
1
PP612
SM
OMIT
P4MM
1
PP613
P4MM
OMIT
SM
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
13 84
I473
I474
I475
I476
I477
I478
I479
I480
I481
I482
I483
68
59
68
68
59
59
59
59
59
59
59
59
59
59
59
59
59
59
59
68
NC_AUD_BI_PORT_E_L
68
59
68
68
68
84
1
PP626
OMIT
P4MM
SM
1
PP627
SM
OMIT
P4MM
I513
10
NB_TSENS_HS_DXP
10
NB_TSENS_HS_DXN
11 34
CPU_XDP_CLK_N
11 34
CPU_XDP_CLK_P
11
7
11
7
11
7
11
7
11
7
11
7
11 26
5
26
5
59
21 58 60 67
21 58 60 67
21 58 60 67
21 58 60 67
5
21 58 60 67
22 58 60
23 58 60 67
21 59 60
6
60
23 58 60 67
34 60
58 60
23 58 60 67
58 59 60
23 60
58 60
58 76
94
85 94
8
75
8
75
8
75
8
75
8
75
8
75
8
75
14 23 75
5
14 26 75
7
21 75
23 26
26 58 77 84
23 58 77
3
75 76
23 58 77 79 80
3 5 6
26 65 66 76 77 78 79 80
83
3
78 83
3
79 83
3
80
3
79
3
34 80
3 5
59 75 77 78 79 80 82 83
7
11
3
59 75 83 97
3 5 6
26 65 66 76 77 78 79 80
83
3 5
59 75 77 78 79 80 82 83
3 6
10 26 27 41 45 76 83 84
3
83
73
NC_J7302_3
73
29
29
1
PP621
OMIT
SM
P4MM
1
PP666
P4MM
OMIT
SM
1
PP665
OMIT
SM
P4MM
1
PP673
OMIT
SM
P4MM
1
PP674
OMIT
SM
P4MM
1
PP675
P4MM
OMIT
SM
H
5 97
051-7039
FUNC TEST 1 OF 2
SYNC_MASTER=M51_HENRY
SYNC_DATE=08/04/2006
NO_TEST=TRUE
PEG_R2D_P<2>
NO_TEST=TRUE
PEG_R2D_N<4>
NO_TEST=TRUE
PEG_R2D_P<5>
NO_TEST=TRUE
PEG_R2D_C_N<0>
NO_TEST=TRUE
NC_SMS_Z_AXIS
NC_SMS_Y_AXIS
NO_TEST=TRUE
NO_TEST=TRUE
NC_AUD_VREF_PORT_C
NC_ALS_GAIN
NO_TEST=TRUE
NC_AUD_BI_PORT_G_L
NO_TEST=TRUE
NC_SMC_P22
NO_TEST=TRUE
NC_SMC_BATT_CHG_EN
NO_TEST=TRUE
NO_TEST=TRUE
PEG_D2R_P<2>
NC_SMC_P21
NO_TEST=TRUE
NO_TEST=TRUE
NC_SMC_P26 NC_SMC_P27
NO_TEST=TRUE
NC_SMC_SYS_ISET
NO_TEST=TRUE
NC_SMC_P20
NO_TEST=TRUE
NC_SMC_BATT_VSET
NO_TEST=TRUE
NC_SMC_BATT_TRICKLE_EN_L
NO_TEST=TRUE
LVDS_BKLTEN
TP_USB_F_P
MAKE_BASE=TRUE
USB_F_N
TP_USB_F_N
MAKE_BASE=TRUE
PEG_D2R_N<0>
NO_TEST=TRUE
NO_TEST=TRUE
PEG_D2R_P<0>
PEG_D2R_P<1>
NO_TEST=TRUE
PEG_D2R_N<2>
NO_TEST=TRUE
NO_TEST=TRUE
PEG_D2R_N<4>
PM_DPRSLPVR
FUNC_TEST=TRUE
PEG_R2D_N<1>
NO_TEST=TRUE
PCI_CLK_SMC
PCI_CLK_FW
SPI_SI
PCIE_B_D2R_N
IDE_PDIORDY IDE_PDD<9>
IDE_PDIOR_L
DMI_N2S_P<0>
USB_F_P
MAKE_BASE=TRUE
TP_LVDS_BKLTEN
SMBUS_SB_SDA
VR_PWRGOOD_DELAY
SMBUS_SMC_A_S3_SCL
SMBUS_SB_SCL
DMI_S2N_P<0>
NB_RST_IN_L_R
FUNC_TEST=TRUE
XDP_TRST_L
FUNC_TEST=TRUE
SMC_TCK
MAKE_BASE=TRUE
NC_NB_CFG<17>
MAKE_BASE=TRUE
NC_NB_CFG<15>
MAKE_BASE=TRUE
NC_NB_CFG<14>
NC_NB_CFG<11>
MAKE_BASE=TRUE
NC_NB_CFG<8>
MAKE_BASE=TRUE
NC_NB_CFG<10>
MAKE_BASE=TRUE
NB_CFG<10>
NB_CFG<13>
NB_CFG<17>
NB_CFG<15>
NB_CFG<14>
MAKE_BASE=TRUE
NC_NB_CFG<13>
NB_CFG<6>
NC_NB_CFG<4>
MAKE_BASE=TRUE
NC_NB_CFG<3>
MAKE_BASE=TRUE
NB_CFG<3>
NC_NB_CFG<6>
MAKE_BASE=TRUE
NB_CFG<4>
NB_CFG<8>
NB_CFG<11>
NB_CFG<12>
NC_NB_CFG<12>
MAKE_BASE=TRUE
PEG_D2R_N<1>
NO_TEST=TRUE
NO_TEST=TRUE
PEG_D2R_N<3>
NO_TEST=TRUE
PEG_D2R_P<4>
NO_TEST=TRUE
PEG_D2R_N<6>
NO_TEST=TRUE
PEG_D2R_P<5>
NO_TEST=TRUE
PEG_D2R_N<5>
NO_TEST=TRUE
PEG_D2R_P<6>
NO_TEST=TRUE
PEG_D2R_P<7>
NO_TEST=TRUE
PEG_D2R_N<7>
NO_TEST=TRUE
PEG_D2R_N<8>
NO_TEST=TRUE
PEG_R2D_N<3>
NO_TEST=TRUE
PEG_R2D_P<3>
NO_TEST=TRUE
PEG_R2D_P<4>
NO_TEST=TRUE
PEG_R2D_N<5>
NO_TEST=TRUE
PEG_R2D_N<6>
NO_TEST=TRUE
PEG_R2D_P<6>
NO_TEST=TRUE
PEG_R2D_N<8>
NO_TEST=TRUE
PEG_R2D_N<7>
NO_TEST=TRUE
PEG_R2D_P<7>
NO_TEST=TRUE
PEG_D2R_P<8>
NO_TEST=TRUE
PEG_D2R_N<10>
NO_TEST=TRUE
PEG_D2R_N<9>
NO_TEST=TRUE
PEG_D2R_P<9>
NO_TEST=TRUE
PEG_D2R_P<10>
NO_TEST=TRUE
PEG_D2R_N<11>
NO_TEST=TRUE
PEG_D2R_P<11>
NO_TEST=TRUE
PEG_D2R_N<12>
NO_TEST=TRUE
PEG_D2R_P<12>
NO_TEST=TRUE
PEG_D2R_N<13>
NO_TEST=TRUE
PEG_D2R_P<13>
NO_TEST=TRUE
PEG_D2R_P<14>
NO_TEST=TRUE
PEG_D2R_N<14>
NO_TEST=TRUE
PEG_D2R_N<15>
NO_TEST=TRUE
PEG_D2R_P<15>
NO_TEST=TRUE
PEG_R2D_P<8>
NO_TEST=TRUE
PEG_R2D_P<9>
NO_TEST=TRUE
PEG_R2D_N<9>
NO_TEST=TRUE
PEG_R2D_N<10>
NO_TEST=TRUE
PEG_R2D_P<10>
NO_TEST=TRUE
PEG_R2D_N<11>
NO_TEST=TRUE
PEG_R2D_P<11>
NO_TEST=TRUE
PEG_R2D_N<12>
NO_TEST=TRUE
PEG_R2D_P<12>
NO_TEST=TRUE
PEG_R2D_P<13>
NO_TEST=TRUE
PEG_R2D_N<13>
NO_TEST=TRUE
PEG_R2D_N<14>
NO_TEST=TRUE
PEG_R2D_P<14>
NO_TEST=TRUE
PEG_R2D_N<15>
NO_TEST=TRUE
PEG_R2D_P<15>
NO_TEST=TRUE
PEG_R2D_C_N<1>
NO_TEST=TRUE
PEG_R2D_C_P<1>
PEG_R2D_C_N<2>
NO_TEST=TRUE
PEG_R2D_C_P<2>
NO_TEST=TRUE
PEG_R2D_C_N<3>
NO_TEST=TRUE
PEG_R2D_C_P<3>
NO_TEST=TRUE
PEG_R2D_C_N<4>
NO_TEST=TRUE
PEG_R2D_C_P<4>
NO_TEST=TRUE
PEG_R2D_C_N<5>
NO_TEST=TRUE
PEG_R2D_C_P<5>
NO_TEST=TRUE
PEG_R2D_C_N<6>
NO_TEST=TRUE
PEG_R2D_C_P<6>
NO_TEST=TRUE
PEG_R2D_C_N<7>
NO_TEST=TRUE
PEG_R2D_C_P<7>
NO_TEST=TRUE
PEG_R2D_C_N<8>
NO_TEST=TRUE
PEG_R2D_C_P<8>
NO_TEST=TRUE
PEG_R2D_C_N<9>
NO_TEST=TRUE
PEG_R2D_C_P<9>
NO_TEST=TRUE
PEG_R2D_C_N<10>
NO_TEST=TRUE
PEG_R2D_C_P<10>
NO_TEST=TRUE
PEG_R2D_C_N<11>
NO_TEST=TRUE
PEG_R2D_C_P<11>
NO_TEST=TRUE
PEG_R2D_C_N<12>
NO_TEST=TRUE
PEG_R2D_C_P<12>
NO_TEST=TRUE
PEG_R2D_C_P<13>
NO_TEST=TRUE
PEG_R2D_C_N<13>
NO_TEST=TRUE
PEG_R2D_C_N<14>
NO_TEST=TRUE
PEG_R2D_C_P<14>
NO_TEST=TRUE
PEG_R2D_C_N<15>
NO_TEST=TRUE
PEG_R2D_C_P<15>
NO_TEST=TRUE
NC_SMC_P23
NO_TEST=TRUE
NC_SMS_X_AXIS
NO_TEST=TRUE
NC_AUD_VREF_PORT_D
NO_TEST=TRUE
PCI_CLK_SB
PCIE_B_D2R_P
DMI_N2S_N<0>
SPI_SO
LPC_FRAME_L
MEM_VREF_NB_0
MEM_VREF_NB_1
DMI_S2N_N<0>
PCI_GNT3_L
TP_PCI_GNT3_L
MAKE_BASE=TRUE
NO_TEST=TRUE
PEG_R2D_C_P<0>
PEG_D2R_P<3>
NO_TEST=TRUE
FUNC_TEST=TRUE
SW_RST_BTN_L
FUNC_TEST=TRUE
XDP_TCK
FUNC_TEST=TRUE
SMC_RX_L
FUNC_TEST=TRUE
XDP_TDI
FUNC_TEST=TRUE
XDP_TDO
FUNC_TEST=TRUE
POWER_BUTTON_L
FUNC_TEST=TRUE
XDP_TMS
FUNC_TEST=TRUE
SMC_MANUAL_RST_L
FUNC_TEST=TRUE
SMC_TDO
FUNC_TEST=TRUE
SMC_TDI
FUNC_TEST=TRUE
SMC_TMS
FUNC_TEST=TRUE
SMC_TRST_L
FUNC_TEST=TRUE
SMC_TX_L
FUNC_TEST=TRUE
ITPRESET_L
FUNC_TEST=TRUE
XDP_BPM_L<4>
FUNC_TEST=TRUE
XDP_BPM_L<5>
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
NC_SMC_BATT_ISET
NO_TEST=TRUE
NO_TEST=TRUE
PEG_R2D_P<1>
PEG_R2D_N<2>
NO_TEST=TRUE
FUNC_TEST=TRUE
XDP_BPM_L<2>
FUNC_TEST=TRUE
XDP_BPM_L<3>
FUNC_TEST=TRUE
XDP_BPM_L<0>
FUNC_TEST=TRUE
XDP_BPM_L<1>
FUNC_TEST=TRUE
XDP_DBRESET_L
FUNC_TEST=TRUE
POWER_BUTTON_L
FUNC_TEST=TRUE
SW_RST_BTN_L
FUNC_TEST=TRUE
LPC_AD<0>
FUNC_TEST=TRUE
LPC_AD<2>
FUNC_TEST=TRUE
LPC_AD<1>
FUNC_TEST=TRUE
LPC_AD<3>
PM_CLKRUN_L
FUNC_TEST=TRUE
FUNC_TEST=TRUE
DEBUG_RST_L
FUNC_TEST=TRUE
PCI_CLK_PORT80
FUNC_TEST=TRUE
FWH_INIT_L
FUNC_TEST=TRUE
INT_SERIRQ
FUNC_TEST=TRUE
PM_SUS_STAT_L
FUNC_TEST=TRUE
SMC_MD1
FUNC_TEST=TRUE
SMC_NMI
FUNC_TEST=TRUE
SMC_RST_L
FUNC_TEST=TRUE
SV_SET_UP
FUNC_TEST=TRUE
ISENSE_CAL_EN
CPU_VID<0>
FUNC_TEST=TRUE
INV_ENABLE_BL
FUNC_TEST=TRUE
LCD_PWM
FUNC_TEST=TRUE
CPU_VID<1>
FUNC_TEST=TRUE
CPU_VID<2>
FUNC_TEST=TRUE
CPU_VID<3>
FUNC_TEST=TRUE
CPU_VID<4>
FUNC_TEST=TRUE
CPU_VID<5>
FUNC_TEST=TRUE
CPU_VID<6>
FUNC_TEST=TRUE
CPU_DPRSTP_L
FUNC_TEST=TRUE
VR_PWRGOOD_DELAY
FUNC_TEST=TRUE
ALL_SYS_PWRGD
FUNC_TEST=TRUE
VR_PWRGD_CK410
FUNC_TEST=TRUE
PM_SLP_S3_L
FUNC_TEST=TRUE
PM_SLP_S4_L
FUNC_TEST=TRUE
FUNC_TEST=TRUE
PP2V5_S5
FUNC_TEST=TRUE
PP3V3_S5
FUNC_TEST=TRUE
PPVCORE_CPU
FUNC_TEST=TRUE
PP1V8_S3
FUNC_TEST=TRUE
PP1V2_S3
FUNC_TEST=TRUE
PP5V_S5
FUNC_TEST=TRUE
PP5V_S0
PP3V3_S5
FUNC_TEST=TRUE
FUNC_TEST=TRUE
PP5V_S5
PP3V3_S0
FUNC_TEST=TRUE
PP24V_S0
FUNC_TEST=TRUE
FUNC_TEST=TRUE
BOOT_LPC_SPI_L
FUNC_TEST=TRUE
LPC_FRAME_L
SMBUS_SMC_A_S3_SDA
FUNC_TEST=TRUE
PP1V5_S0
FUNC_TEST=TRUE
PP1V05_S0
SB_CLK100M_SATA_N
SB_CLK100M_SATA_P
SB_CLK14P3M_TIMER
FSB_CPURST_L
NC_SMC_SYS_VSET
NO_TEST=TRUE
NO_TEST=TRUE
PEG_R2D_P<0>
NO_TEST=TRUE
PEG_R2D_N<0>
SB_CLK48M_USBCTLR
NC_AUD_VREF_PORT_B
NO_TEST=TRUE
NC_AUD_BI_PORT_H_R
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NC_J7302_6
NO_TEST=TRUE
NC_SMC_MEM_ISENSE
NO_TEST=TRUE
NC_AUD_BI_PORT_H_L
NO_TEST=TRUE NO_TEST=TRUE
TP_MEM_B_A<15>
NO_TEST=TRUE
TP_MEM_B_A<14>
NC_AUD_BI_PORT_E_R
NO_TEST=TRUE
67
75
60
63
26
63
58
12
19
58
44
58
54
38
38
38
22
14
22
34
54
22
58
21
19
19
22
34
34
34
11
34
13
22
34
34
22
22
21
21
21
14
22
19
27
5
27
27
14
14
14
14
14
14
14
14
14
14
14
14
14
22
22
14
22
5
14
14
14
22
27
21
21
23
7
23
www.Vinafix.vn
Preliminary
125
125
125
125
OUT
G
D
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
FROM AC/DC
NEEDED AND THERE IS NO FREE PIN ON THE CONNECTOR
NOT SENDING 3.3V TO THE DRIVE BECAUSE IT IS NOT
TO HDD
SILKSCREEN:RUN
CHASSIS HOLE UPPER RIGHT CORNER OF BOARD
CHASSIS HOLE NEAR POWER SWITCH CONNECTOR (BOT RIGHT)
TO NONPLATED HOLE TO LEFT OF EXTERNAL AUDIO CONNECTORS
SILKSCREEN:1
SYSTEM STATUS
GND RAILS
TO SYS ISENSE
CHASSIS GND
TO NONPLATED SLOT TO RIGHT OF EXTERNAL IO
CHASSIS NEXT TO AUDIO CONNECTORS
CHASSIS HOLE NEAR MXM
LOCATED NORTH OF CPU
HEATSINK BACKER PLATE STANDOFFS
CHASSIS HOLE NEAR ODD CONNECTOR (TOP MID)
AC/DC CONN
SILKSCREEN:2
SILKSCREEN:4
SILKSCREEN:3
21
XW601
OMIT
SM
21
XW602
OMIT
SM
3
14
17
2
U600
CRITICAL
TSSOP
74LC125
2
1
C600
0.1UF
CERM 402
20% 10V
2
1
LED601
2.0X1.25MM-SM
GREEN-3.6MCD
1
ZH631
4P25R3P5
OMIT
2
1
C631
NOSTUFF
0.01UF
402
16V CERM
20%
2
1
R602
402
MF-LF
5% 1/16W
1K
1
ZH630
OMIT
4P25R3P5
2
1
C630
16V CERM
NOSTUFF
402
20%
0.01UF
6
14
47
5
U600
TSSOP
CRITICAL
74LC125
8
14
10
7
9
U600
CRITICAL
TSSOP
74LC125
11
14
13
7
12
U600
CRITICAL
74LC125
TSSOP
21
R612
MF-LF
68
1/16W
5%
402
21
R611
68
1/16W MF-LF
5%
402
21
R614
68
1/16W MF-LF
402
5%
21
R615
TPM
68
MF-LF
1/16W
5%
402
21
R616
68
MF-LF
1/16W
402
5%
21
R617
1/16W MF-LF
68
5%
402
21
R618
1/16W MF-LF
402
68
5%
21
R619
402
5%
68
MF-LF
1/16W
2
1
R600
MF-LF
5%
1K
402
1/16W
2
1
LED602
2.0X1.25MM-SM
GREEN-3.6MCD
2
1
R605
5%
402
DEVELOPMENT
MF-LF
1/16W
1K
2
1
LED600
GREEN-3.6MCD
2.0X1.25MM-SM
DEVELOPMENT
9
8
7
6
5
4
3
2
12
11
10
1
J601
M-RT-TH
HM9606E-M2
CRITICAL
2
1
LED603
GREEN-3.6MCD
2.0X1.25MM-SM
2
1
R601
5%
MF-LF
1/16W
402
3.3K
2
1
R604
402
5%
MF-LF
1/16W
1K
2
1
LED604
GREEN-3.6MCD
2.0X1.25MM-SM
2
1
C620
5% 50V CERM 402
NOSTUFF
100PF
2
1
C621
402
CERM
50V
5%
NOSTUFF
100PF
2
1
R606
402
1.5K
MF-LF
1% 1/16W
3
2
1
C622
5% 50V CERM 402
100PF
NOSTUFF
21
XW603
OMIT
SM
1
ZH611
OMIT
4P25R3P5
2
1
C624
100UF
20% 16V ELEC
6.3X5.5-SM
NOSTUFF
2
1
C623
ELEC SM
6.3V
20%
150UF
NOSTUFF
1
SDF600
TH
HSK-NUT-6.5MM
1
SDF601
HSK-NUT-6.5MM
TH
1
ZH632
4P25R3P5
OMIT
1
ZH633
4P25R3P5
OMIT
2
1
C633
NOSTUFF
402
16V CERM
0.01UF
20%
1
ZH634
4P25R3P5
OMIT
2
1
C634
NOSTUFF
402
16V CERM
20%
0.01UF
2
1
R607
10K
5% 1/16W MF-LF 402
2
1
C625
NOSTUFF
20%
ELEC
100UF
35V
2
1
3
Q600
SOT23-LF
2N7002
2
1
R609
402
10K
1/16W MF-LF
5%
SYNC_MASTER=M51_PAUL
POWER CONN / MISC
SYNC_DATE=08/04/2006
H
976
051-7039
GPU_PRESENT
PP3V3_S0
PP24V_S5
=PP5V_S0_SATA
GND_CHASSIS_POWER_CONN
pp3v3_s5
SYS_POWERFAIL_L
GND_AUDIO
PP12V_S5_AC_DC
GND_CHASSIS_USB
PLT_RST_L
LCD_SHOULD_ON
GND_CHASSIS_NEAR_PWR_SW
VOLTAGE=0
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
GND_CHASSIS_CPU_TEMP
GND_CHASSIS_NEAR_ODD_CON MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0
GND_CHASSIS_RJ45
GND_CHASSIS_GPU_TEMP
GND_CHASSIS_AUDIO_INTERNAL
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
VOLTAGE=0
MAKE_BASE=TRUE
GND_CHASSIS_IO_RIGHT
GND_CHASSIS_DVI
GND_CHASSIS_ODD_TEMP
GND_CHASSIS_BNDI MIN_NECK_WIDTH=0.2MM
MAKE_BASE=TRUE
VOLTAGE=0
MIN_LINE_WIDTH=0.6MM
GND_CHASSIS_TOP_RIGHT MAKE_BASE=TRUE VOLTAGE=0
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM
GND_CHASSIS_HDD_TEMP
=PP3V3_S0_SATA
GND_AUDIO_SPKRAMP
FW_RST_L
GND_CHASSIS_AUDIO_EXTERNAL
GND_CHASSIS_FIREWIRE
ITS_ALIVE
ITS_PLUGGED_IN
U600_11
ENET_RST_L
U600_3
SMC_LRESET_L
NB_RST_IN_L
PEG_RESET_L
TPM_LRESET_L
AIRPORT_RST_L
PP12V_LCD_CONN
PP3V3_S3PP3V3_S5
DEBUG_RST_L
ITS_RUNNING
MIN_NECK_WIDTH=0.2MM
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
VOLTAGE=0
GND_CHASSIS_IO_LEFT
PP3V3_S0
GND_CHASSIS_NEAR_MXM
VOLTAGE=0 MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
MAKE_BASE=TRUE
GPU_PRESENT_R
PP3V3_S0
=PP12V_S0_SATA
ACDC_TEMP
PP3V3_S5
U600_8
U600_6
83
83
83
84
80
80
84
84
80
83
79
79
83
83
79
76
78
78
76
76
78
45
77
77
45
45
77
41
76
76
41
41
76
27
66
66
27
27
66
26
65
65
26
26
65
10
26
83 26
10
10
26
6
6
82
53
6
6
6
6
5
83
5
78
72
74
27
5
60
5
5
5
3
3
3
3
76
74
76
47
22
10
43
10
73
97
66
47
66
71
45
73
46
42
58
14
85
67
53
94
3 3
5
3
23
3
3
59
3
www.Vinafix.vn
Preliminary
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IN
IN
IN
IN
IN
IN
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
OUT
OUT
OUT
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
A3*
A4*
A5*
A6*
A8*
A10*
A11*
A12*
A13*
A16*
A15*
A14*
ADSTB0*
REQ2*
REQ0*
REQ1*
REQ3*
REQ4*
A17*
A18*
A19*
A20*
A21*
A23*
A22*
A24*
A25*
A26*
A29*
A28*
A27*
A31*
A30*
ADSTB1*
A20M*
FERR*
IGNNE*
STPCLK*
LINT1
LINT0
SMI*
RSVD10
RSVD9
RSVD5
RSVD4
RSVD3
RSVD2
RSVD1
RSVD8
RSVD7
RSVD6
RSVD11
ADS*
BNR*
BPRI*
DEFER*
DRDY*
DBSY*
BR0*
IERR*
INIT*
LOCK*
RESET*
RS0*
RS1*
RS2*
TRDY*
HIT*
HITM*
BPM0*
BPM2*
BPM1*
BPM3*
PRDY*
PREQ*
TCK
TDI
TDO
TMS
TRST*
DBR*
PROCHOT*
THERMDA
THERMDC
THERMTRIP*
RSVD12
RSVD13
RSVD16
RSVD19
RSVD18
RSVD17
RSVD20
BCLK0
BCLK1
RSVD15
RSVD14
A7*
A9*
ADDR GROUP0
XDP/ITP SIGNALS
CONTROL
ADDR GROUP1
RESERVED
HCLK
THERM
(1 OF 4)
PSI*
SLP*
PWRGOOD
DPRSTP*
DPSLP*
DPWR*
COMP2
COMP3
COMP1
COMP0
DSTBP3*
DSTBN3*
DINV3*
D63*
D62*
D61*
D60*
D59*
D58*
D57*
D56*
D55*
D54*
D52*
D53*
D51*
D50*
D49*
D48*
DINV2*
DSTBN2*
D47*
DSTBP2*
D45*
D46*
D44*
D43*
D42*
D41*
D40*
D39*
D38*
D37*
D36*
D35*
D34*
D33*
D32*
BSEL2
DSTBN1*
BSEL0
BSEL1
TEST2
GTLREF
DINV1*
DSTBP1*
D31*
D30*
D29*
D26*
D27*
D28*
D24*
D25*
D23*
D21*
D22*
D20*
D19*
D18*
D16*
D17*
DINV0*
DSTBP0*
DSTBN0*
D15*
D14*
D13*
D12*
D11*
D10*
D9*
D8*
D7*
D6*
D5*
D4*
D3*
D2*
D1*
D0*
TEST1
NC
(2 OF 4)
MISC
DATA GRP0
DATA GRP2
DATA GRP1
DATA GRP3
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
NO STUFF R0701 IF USING ITP
TP_CPU_M_TEST3
SPARE[7-0],HFPLL:
ROUTE TO TP VIA AND
PLACE GND VIA W/IN 1000 MILS
TP_CPU_M_TEST4
CPU SCH AND PCB
LAYOUT NOTE: 0.5" MAX LENGTH
PIN ACTUALLY DRIVEN BY ITP
DUMMY PIN
NOTE:
STUB)
WITHOUT T-ING (NO
ICH6-M AND GMCH
PM_THRMTRIP#
SHOULD CONNECT TO
PLACE TESTPOINT ON
0.1" AWAY
SYMBOL NEED TO CHECK
FSB_IERR# WITH A GND
ON ITP SIGNALS?
NO SPACE FOR ITP
CONNECTOR, NEED TERM
CPU_PROCHOT_L TO SMC
AND CPU VR TO INFORM
CPU IS HOT
TRACE LENGTH SHORTER THAN 0.5".
TRACE LENGTH SHORTER THAN 0.5".
COMP0,2 CONNECT WITH ZO=27.4OHM, MAKE
COMP1,3 CONNECT WITH ZO=55OHM, MAKE
LAYOUT NOTE:
2
1
R0703
1%
54.9
MF-LF 402
1/16W
2
1
R0704
MF-LF 402
5% 1/16W
68
2
1
R0705
1/16W
1%
402
MF-LF
1K
2
1
R0706
1/16W
1%
402
MF-LF
2.0K
21
R0720
54.9
MF-LF
402
1%
1/16W
21
R0721
1%
54.9
MF-LF
402
1/16W
21
R0722
54.9
MF-LF
402
1%
1/16W
21
R0719
1%
402
54.9
21
R0718
27.4
21
R0717
1%
402
54.9
21
R0716
27.4
402
21
R0730
0
402
NOSTUFF
2
1
R0712
1K
MF-LF 402
5% 1/16W
NOSTUFF
2
1
R0707
MF-LF 402
5% 1/16W
51
AB6
G2
AB5
C7
A25
A24
AB3
AA6
AC5
D5
A3
B2
V3
T2
N5
M4
AA3
AB2
C24
AA4
C23
D22
AF1
C1
D3
F6
D2
T22
B25
C3
AA1
G3
F4
F3
B1
L5
J3
K2
H2
K3
D21
AC1
AC2
H4
B4
C6
B3
C4
D20
E4
G6
A5
F21
H5
E1
C20
F1
G5
AC4
AD1
AD3
AD4
E2
A21
A22
V4
L2
H1
J1
N2
M1
K5
M3
L4
Y1
W2
J4
Y4
W5
W3
T3
T5
R4
U2
Y5
U4
A6
W6
R3
U5
Y2
R1
P1
P4
L1
P2
P5
N3
J0700
BGA
YONAH-SKT
CPU
OMIT
D25
C26
D7
D6
AE6
A2
AD26
AE24
Y25
N25
G22
AD23
W24
M24
H23
D24
B5
E5
AC20
V23
M26
J26
G24
K24
E23
AF26
AF22
AF25
AE25
E25
AD21
AE21
AD24
AF23
AE22
AD20
AC25
AB21
AA21
AB22
G25
AC23
AC22
AA24
AC26
Y22
Y26
AA26
Y23
W22
AB25
F23
U22
U25
U23
W25
V26
V24
AB24
AA23
N24
T25
H22
L26
R24
T24
P23
P22
P25
M23
L23
L22
L25
E26
R23
P26
K25
N22
H25
K22
F26
H26
J23
J24
F24
E22
V1
U1
U26
R26
C21
B23
B22
J0700
BGA
CPU
YONAH-SKT
OMIT
2
1
R0702
1%
54.9
1/16W MF-LF 402
2
1
R0701
1/16W
1%
402
MF-LF
54.9
97
051-7039
H
7
CPU 1 OF 2-FSB
SYNC_MASTER=M50_HENRY
SYNC_DATE=08/04/2006
TP_CPU_SPARE7
TP_CPU_SPARE4
TP_CPU_SPARE3
TP_CPU_SPARE2
CPU_GTLREF
FSB_IERR_L
FSB_DSTBP_L<0>
CPU_PSI_L
FSB_SLPCPU_L
CPU_DPRSTP_L
CPU_DPSLP_L
FSB_DPWR_L
CPU_COMP<2> CPU_COMP<3>
CPU_COMP<1>
CPU_COMP<0>
FSB_DSTBP_L<3>
FSB_DSTBN_L<3>
FSB_DINV_L<3>
FSB_D_L<63>
FSB_D_L<62>
FSB_D_L<61>
FSB_D_L<60>
FSB_D_L<59>
FSB_D_L<58>
FSB_D_L<57>
FSB_D_L<56>
FSB_D_L<55>
FSB_D_L<54>
FSB_D_L<52> FSB_D_L<53>
FSB_D_L<51>
FSB_D_L<50>
FSB_D_L<49>
FSB_D_L<48>
FSB_DINV_L<2>
FSB_DSTBN_L<2>
FSB_D_L<47>
FSB_DSTBP_L<2>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<44>
FSB_D_L<43>
FSB_D_L<42>
FSB_D_L<41>
FSB_D_L<40>
FSB_D_L<39>
FSB_D_L<38>
FSB_D_L<37>
FSB_D_L<36>
FSB_D_L<35>
FSB_D_L<34>
FSB_D_L<33>
FSB_D_L<32>
CPU_BSEL<2>
FSB_DSTBN_L<1>
CPU_BSEL<0>
CPU_BSEL<1>
CPU_TEST2
FSB_DINV_L<1>
FSB_DSTBP_L<1>
FSB_D_L<31>
FSB_D_L<30>
FSB_D_L<29>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<24>
FSB_D_L<25>
FSB_D_L<23>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<20>
FSB_D_L<19>
FSB_D_L<18>
FSB_D_L<16>
FSB_D_L<17>
FSB_DSTBN_L<0>
FSB_D_L<15>
FSB_D_L<14>
FSB_D_L<13>
FSB_D_L<12>
FSB_D_L<11>
FSB_D_L<10>
FSB_D_L<9>
FSB_D_L<8>
FSB_D_L<7>
FSB_D_L<6>
FSB_D_L<5>
FSB_D_L<4>
FSB_D_L<3>
FSB_D_L<2>
FSB_D_L<1>
FSB_D_L<0>
CPU_TEST1
FSB_A_L<7>
TP_CPU_SPARE1
FSB_CLK_CPU_N
FSB_CLK_CPU_P
TP_CPU_SPARE5
TP_CPU_SPARE6
PM_THRMTRIP_L
CPU_THERMD_N
CPU_THERMD_P
XDP_DBRESET_L
XDP_TMS
XDP_TDO
XDP_TCK
XDP_BPM_L<1>
XDP_BPM_L<0>
FSB_HITM_L
FSB_HIT_L
FSB_TRDY_L
FSB_RS_L<1>
FSB_RS_L<0>
FSB_CPURST_L
FSB_LOCK_L
FSB_DBSY_L
FSB_DRDY_L
FSB_DEFER_L
FSB_BPRI_L
FSB_BNR_L
FSB_ADS_L
TP_CPU_HFPLL
TP_CPU_A37_L
TP_CPU_A38_L
TP_CPU_A33_L TP_CPU_A34_L
TP_CPU_A35_L
TP_CPU_A36_L
TP_CPU_APM0_L
TP_CPU_APM1_L
CPU_SMI_L
CPU_INTR CPU_NMI
CPU_STPCLK_L
CPU_IGNNE_L
CPU_FERR_L
CPU_A20M_L
FSB_ADSTB_L<1>
FSB_A_L<30> FSB_A_L<31>
FSB_A_L<27> FSB_A_L<28>
FSB_A_L<29>
FSB_A_L<26>
FSB_A_L<25>
FSB_A_L<24>
FSB_A_L<22> FSB_A_L<23>
FSB_A_L<21>
FSB_A_L<20>
FSB_A_L<19>
FSB_A_L<18>
FSB_A_L<17>
FSB_REQ_L<4>
FSB_REQ_L<3>
FSB_REQ_L<1>
FSB_REQ_L<0>
FSB_REQ_L<2>
FSB_ADSTB_L<0>
FSB_A_L<14> FSB_A_L<15>
FSB_A_L<16>
FSB_A_L<13>
FSB_A_L<12>
FSB_A_L<11>
FSB_A_L<10>
FSB_A_L<9>
FSB_A_L<8>
FSB_A_L<5>
FSB_A_L<4>
FSB_A_L<3>
=PP1V05_S0_CPU
=PP1V05_S0_CPU
XDP_TMS
XDP_TCK
XDP_TDI
CPU_PWRGD
XDP_BPM_L<3>
FSB_DINV_L<0>
CPU_PROCHOT_L
=PP1V05_S0_CPU
XDP_BPM_L<4> XDP_BPM_L<5>
FSB_RS_L<2>
XDP_TRST_L
XDP_TDI
XDP_BPM_L<2>
TP_CPU_SPARE0
TP_CPU_A32_L
TP_CPU_EXTBREF
TP_CPU_A39_L
FSB_A_L<6>
=PP1V05_S0_CPU
FSB_BREQ0_L
CPU_INIT_L
11
11
11
11
9
9
9
9
75
59
26
11
11
12
8
8
11
11
11
8
11
8
21
21
11
7
11
7
11
11
11
7
7
7
7
7
11
7
11
11
11
7
11
7
12
75
12
5
21
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
34
12
34
34
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
34
34
14
10
10
5
5
5
5
5
5
12
12
12
12
12
5
12
12
12
12
12
12
12
21
21
21
21
21
21
21
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
3
3
5
5
5
21
5
12
59
3
5
5
12
5
5
5
12
3
12
21
www.Vinafix.vn
Preliminary
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
VCC_67
VCC_64
VCC_66
VCC_65
VCC_63
VCC_62
VCC_61
VCC_59
VCC_60
VCC_58
VCC_57
VCC_56
VCC_54
VCC_55
VCC_53
VCC_51
VCC_52
VCC_49
VCC_50
VCC_48
VCC_47
VCC_46
VCC_44
VCC_45
VCC_43
VCC_41
VCC_42
VCC_40
VCC_39
VCC_38
VCC_36
VCC_37
VCC_33
VCC_35
VCC_34
VCC_31
VCC_32
VCC_29
VCC_30
VCC_28
VCC_26
VCC_27
VCC_23
VCC_25
VCC_24
VCC_22
VCC_21
VCC_20
VCC_18
VCC_19
VCC_17
VCC_16
VCC_15
VCC_13
VCC_14
VCC_12
VCC_10
VCC_11
VCC_8
VCC_9
VCC_7
VCC_6
VCC_5
VCC_3
VCC_4
VCC_2
VCC_1 VCC_68
VCC_69
VCC_71
VCC_70
VCC_72
VCC_74
VCC_76
VCC_75
VCC_78
VCC_77
VCC_79
VCC_81
VCC_80
VCC_84
VCC_82
VCC_83
VCC_86
VCC_85
VCC_87
VCC_89
VCC_88
VCC_90
VCC_91
VCC_92
VCC_94
VCC_93
VCC_95
VCC_96
VCC_97
VCC_99
VCC_98
VCC_100
VCCP_1
VCCP_2
VCCP_3
VCCP_4
VCCP_5
VCCP_6
VCCP_7
VCCP_9
VCCP_8
VCCP_11
VCCP_10
VCCP_12
VCCP_13
VCCP_14
VCCP_16
VCCP_15
VCCA
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VSSSENSE
VCCSENSE
VCC_73
(3 OF 4)
VSS_82
VSS_83
VSS_84
VSS_85
VSS_87
VSS_86
VSS_88
VSS_89
VSS_90
VSS_92
VSS_91
VSS_93
VSS_94
VSS_95
VSS_97
VSS_96
VSS_100
VSS_98
VSS_99
VSS_102
VSS_101
VSS_105
VSS_103
VSS_104
VSS_106
VSS_107
VSS_110
VSS_109
VSS_108
VSS_111
VSS_112
VSS_115
VSS_114
VSS_113
VSS_116
VSS_117
VSS_118
VSS_120
VSS_119
VSS_123
VSS_121
VSS_122
VSS_124
VSS_125
VSS_128
VSS_126
VSS_127
VSS_129
VSS_130
VSS_133
VSS_131
VSS_132
VSS_134
VSS_135
VSS_138
VSS_136
VSS_137
VSS_139
VSS_140
VSS_141
VSS_143
VSS_142
VSS_146
VSS_144
VSS_145
VSS_147
VSS_148
VSS_151
VSS_150
VSS_149
VSS_152
VSS_153
VSS_156
VSS_155
VSS_154
VSS_157
VSS_158
VSS_159
VSS_161
VSS_160
VSS_162
VSS_1
VSS_2
VSS_3
VSS_5
VSS_4
VSS_6
VSS_7
VSS_8
VSS_10
VSS_9
VSS_11
VSS_12
VSS_15
VSS_13
VSS_14
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_23
VSS_22
VSS_21
VSS_24
VSS_25
VSS_28
VSS_27
VSS_26
VSS_29
VSS_30
VSS_33
VSS_32
VSS_31
VSS_34
VSS_35
VSS_38
VSS_37
VSS_36
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_46
VSS_44
VSS_45
VSS_47
VSS_48
VSS_51
VSS_49
VSS_50
VSS_52
VSS_53
VSS_56
VSS_54
VSS_55
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_63
VSS_62
VSS_64
VSS_65
VSS_66
VSS_69
VSS_68
VSS_67
VSS_70
VSS_71
VSS_74
VSS_73
VSS_72
VSS_75
VSS_76
VSS_79
VSS_78
VSS_77
VSS_80
VSS_81
(4 OF 4)
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
VCCA=1.5 ONLY
LAYOUT NOTE: CONNECT R0802-03
TO VCCSENSE_P/N WITH NO STUB
PROVIDE A TEST POINT (WITH NO STUB)
BETWEEN VCCSENSE AND VSSSENSE AT THE
LOCATION WHERE THE TWO 54.9 OHM
RESISTORS TERMINATE THE 55 OHM
TRANSMISSION LINE
TO CONNECT A DIFFERENCTIAL PROBE
LAYOUT NOTE:
2
1
C0800
16V
20%
402
CERM
0.01UF
2
1
C0801
805-1
CERM
10UF
20%
6.3V
2
1
R0803
100
MF-LF 402
1% 1/16W
2
1
R0802
100
MF-LF 402
1% 1/16W
AE7
AE2
AF2
AE3
AF4
AE5
AF5
AD6
AF7
N21
M21
K21
J21
M6
K6
J6
G21
W21
V21
T6
T21
R6
R21
N6
V6
B26
AF18
AF17
AF15
AF14
AF12
AF10
AF9
AE20
AE18
AE17
A20
AE15
AE13
AE12
AE10
AE9
AD18
AD17
AD15
AD14
AD12
A18
AD10
AD9
AD7
AC18
AC17
AC15
AC13
AC12
AC9
AC7
A17
AB7
AB20
AB18
AB17
AB15
AB14
AB12
AB10
AC10
AB9
A15
AA20
AA18
AA17
AA15
AA13
AA12
AA10
AA9
AA7
F20
A13
F18
F17
F15
F14
F12
F10
F9
F7
E20
E18
A12
E17
E15
E13
E12
E10
E9
E7
D18
D17
D15
A10
D14
D12
D10
D9
C18
C17
C15
C13
C12
C10
A9
C9
B20
B18
B17
B15
B14
B12
B10
B9
AF20
B7
A7
J0700
OMIT
CPU
BGA
YONAH-SKT
V22
V5
V2
U24
U21
U6
U3
T26
T23
T4B6
T1
R25
R22
R5
R2
P24
P21
P6
P3
N26
A26
N23
N4
N1
M25
M22
M5
M2
L24
L21
L6
A23
L3
K26
K23
K4
K1
J25
J22
J5
J2
H24
A19
H21
H6
H3
G26
G23
G1
G4
F25
F22
F2
A16
F19
F16
F13
F11
F8
F5
E24
E21
E19
E16
A14
E14
E11
E8
E6
E3
D26
D23
D19
D16
D13
A11
D11
D8
D4
D1
C25
C22
C2
C19
C16
C14
A8
C11
C8
C5
AF24
AF21
AF19
B24
AF16
AF13
AF11
AF8
AF6
AF3
AE26
AE23
AE19
AE16
B21
AE14
AE11
AE8
AE4
AE1
AD25
AD22
AD19
AD16
AD13
B19
AD11
AD8
AD5
AD2
AC24
AC21
AC19
AC16
AC14
AC11
B16
AC8
AC6
AC3
AB26
AB23
AB19
AB16
AB13
AB11
AB8
B13
AB4
AB1
AA25
AA22
AA19
AA16
AA14
AA11
AA8
AA5
B11
AA2
Y24
Y21
Y6
Y3
W26
W23
W4
W1
V25
B8
A4
J0700
OMIT
CPU
YONAH-SKT
BGA
SYNC_MASTER=M50_HENRY
SYNC_DATE=08/04/2006
978
H
051-7039
CPU 2 OF 2-PWR/GND
CPU_VID<5>
CPU_VID<2>
CPU_VID<0>
=PP1V05_S0_CPU
=PPVCORE_S0_CPU
=PPVCORE_S0_CPU
CPU_VCCSENSE_N
=PP1V5_S0_CPU
=PPVCORE_S0_CPU
=PP1V5_S0_CPU
CPU_VCCSENSE_P
CPU_VID<6>
CPU_VID<4>
CPU_VID<3>
CPU_VID<1>
11
76
76
76
9
9
9
9
75
75
75
7
8
8
8
8
8
75
75
75
75
5
5
5
3
3
3
75
3
3
3
75
5
5
5
5
www.Vinafix.vn
Preliminary
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
CAVITY ON L1 (NORTH SIDE
PLACE 6 INSIDE SOCKET
CAVITY ON L1 (SOUTH SIDE
WE HAD A 330UF ELEC CAP HERE FOR 1.05V RAIL - CHECK WE CAN REMOVE
CPU HEATSINK MOUNTING HOLES
VCCP CORE DECOUPLING
ON L8 (NORTH SIDE SECONDARY)
PLACE INSIDE SOCKET CAVITY
NEED LARGE BULK FOR 1.05V
VCC CORE DECOUPLING
DESIGN FOR 44 CERAMIC AND 3 ELECT BULK 1800UF
PRIMARY)
SOUTH SIDE SECONDARY
CAVITY ON L8 (SOUTH SIDE
PLACE 8 INSIDE SOCKET
CAVITY ON L8 (NORTH SIDE
PLACE 8 INSIDE SOCKET
PLACE 6 INSIDE SOCKET
SECONDARY)
PRIMARY)
SECONDARY)
2
1
C900
22UF
6.3V
20%
X5R 805
2
1
C996
22UF
X5R 805
20%
6.3V
2
1
C993
22UF
X5R 805
20%
6.3V 2
1
C994
22UF
6.3V
20%
805
X5R
2
1
C995
22UF
X5R 805
20%
6.3V 2
1
C988
22UF
X5R 805
20%
6.3V
2
1
C992
22UF
6.3V
20%
805
X5R
2
1
C991
22UF
6.3V
20%
805
X5R
2
1
C990
22UF
X5R 805
20%
6.3V
2
1
C989
22UF
6.3V
20%
805
X5R
2
1
C941
6.3V
805
22UF
20%
X5R
2
1
C942
22UF
6.3V X5R
20%
805
2
1
C943
22UF
6.3V X5R
20%
805
2
1
C944
6.3V
22UF
X5R
20%
805
2
1
C945
X5R
22UF
6.3V
20%
805
2
1
C946
22UF
6.3V X5R
20%
805
32
1
C947
NOSTUFF
470UF
D2T
TANT
2.5V
20%
2
1
C901
22UF
20%
6.3V X5R 805
2
1
C902
805
22UF
6.3V
20%
X5R
2
1
C904
22UF
6.3V
20%
X5R 805
2
1
C905
X5R
NOSTUFF
22UF
805
20%
6.3V
2
1
C906
22UF
805
20%
6.3V X5R
2
1
C907
20%
22UF
6.3V X5R 805
2
1
C908
22UF
20%
6.3V X5R 805
2
1
C909
22UF
20%
6.3V X5R 805
2
1
C910
22UF
20%
6.3V X5R 805
2
1
C911
22UF
20%
6.3V X5R 805
2
1
C912
22UF
6.3V
20%
X5R 805
2
1
C913
22UF
20%
X5R
6.3V
805
2
1
C914
NOSTUFF
22UF
805
20%
6.3V X5R
2
1
C915
NOSTUFF
6.3V
805
22UF
20%
X5R
2
1
C916
805
X5R
6.3V
20%
22UF
2
1
C917
NOSTUFF
22UF
6.3V
805
20%
X5R
2
1
C918
22UF
X5R
20%
6.3V
805
2
1
C919
22UF
6.3V
805
20%
X5R
2
1
C920
22UF
6.3V
20%
X5R 805
2
1
C921
6.3V
22UF
X5R 805
20%
2
1
C922
22UF
6.3V X5R
20%
805
2
1
C923
22UF
6.3V X5R 805
20%
2
1
C924
22UF
6.3V
20%
X5R 805
2
1
C925
6.3V
22UF
X5R 805
20%
2
1
C926
CERM
10V 402
0.1UF
20%
2
1
C928
22UF
20%
6.3V X5R 805
2
1
C929
22UF
20%
6.3V X5R 805
2
1
C930
22UF
805
6.3V
20%
X5R
2
1
C931
20%
22UF
X5R
6.3V
805
2
1
C932
805
NOSTUFF
22UF
20%
X5R
6.3V
2
1
C934
20%
402
10V CERM
0.1UF
2
1
C935
0.1UF
CERM
10V 402
20%
2
1
C936
20%
0.1UF
402
10V CERM
2
1
C937
CERM
10V 402
0.1UF
20%
2
1
C938
20%
0.1UF
402
10V CERM
2
1
C939
22UF
6.3V
20%
X5R 805
2
1
C903
NOSTUFF
22UF
805
20%
X5R
6.3V
1
ZH607
OMIT
4P75R4
2
1
C950
402
0.01UF
CERM
20% 16V
1
ZH608
OMIT
4P75R4
2
1
C951
402
0.01UF
CERM
20% 16V
1
ZH609
OMIT
4P75R4
2
1
C952
402
0.01UF
CERM
20% 16V
1
ZH610
OMIT
4P75R4
2
1
C953
402
0.01UF
CERM
20% 16V
2
1
C999
22UF
6.3V
20%
805
X5R
2
1
C998
22UF
X5R 805
20%
6.3V 2
1
C997
22UF
6.3V
20%
805
X5R
CPU DECAPS & VID<>
979
051-7039
H
SYNC_DATE=08/04/2006
SYNC_MASTER=M51_HENRY
=PP1V05_S0_CPU
CPU_HS_ZH608 CPU_HS_ZH609CPU_HS_ZH607 CPU_HS_ZH610
=PPVCORE_S0_CPU
11
8
76 7 8 3 3
www.Vinafix.vn
Preliminary
D+
D-
ALERT*/
THM*
SCLK
SDATA
VDD
GND
THM2*
DXP
SCLK
ALERT*
SDA THM PADGND
VCC
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
AMBIENT TEMPERATURE (CPU FAN INTAKE) SENSOR
MAY NOT BE CONSISTENT WITH OTHER CARDS
(GPU INTERNAL DIODE)
MXM CARD TEMPERATURE SENSOR
THEN THIS SHOULD BE S5
ROUTE ON SAME LAYER WITH 0.254MM TRACE WIDTH & SPACING.
NOTE: IF CPU T DIODE TO BE READ IN OFF STATE,
CPU INTERNAL DIODE THERMAL SENSOR
NOTE: SYMBOL SHOULD BE SHOWN ADT7461A
I2C ADDR:0x94
LAYOUT NOTE:
I2C ADDR:0x94
I2C ADDR:0x96
ADD GND GUARD TRACES FOR CPU_THERMD_P/N
CPU AND GPU REMOTE HEATSINK THERMAL SENSORS
NB HEATSINK TEMPERATURE SENSE
I2C ADDRESS: 90 (1001 000)
NOTE: I2C ADDR:98(1001 100) ON NVIDIA CARD
1
4
7
8
5
3
2
6
U1000
CPU_TSENS_INT
ADT7461
MSOP
CRITICAL
21
R1002
MF-LF
499
1%
1/16W
402
CPU_TSENS_INT
2
1
C1000
NOSTUFF
0.001UF
50V
402
CERM
10%
2
1
C1001
CPU_TSENS_INT
16V
10%
X5R
0.1UF
402
21
R1017
499
CPU_TSENS_INT
1/16W
1%
MF-LF
402
2
1
R1001
1/16W
CPU_TSENS_INT
5%
MF-LF 402
10K
2
1
R1000
402
5%
MF-LF
10K
1/16W
CPU_TSENS_INT
21
R1060
GPU_TSENS_INT
5%
1/16W
0
21
R1061
GPU_TSENS_INT
0
1/16W
5%
7
6
5
4
3
1
J1050
M-ST-SM
GPU_TSENS_EXT
53398-05
CRITICAL
2
1
C1012
402
20%
0.1UF
10V CERM
CPU_TSENS_EXT
21
C1010
20%
CERM
16V
NOSTUFF
0.01UF
402
21
C1011
0.01UF
40216V
20%
CERM
NOSTUFF
2
1
C1052
GPU_TSENS_EXT
0.1UF
20% 10V
402
CERM
21
C1050
0.01UF
402
CERM
16V
NOSTUFF
20%
21
C1051
20%
NOSTUFF
16V
CERM
402
0.01UF
1
7
5
4
2
3
6
U1080
NB_TSENS_EXT
MAX6642ATT90
CRITICAL
TDFN
21
R1005
NOSTUFF
MF-LF
402
0
5%
1/16W
2
1
C1080
402
0.1UF
X5R
10% 16V
NB_TSENS_EXT
21
R1080
NB_TSENS_EXT
MF-LF
5%
1/16W
47
402
2
1
C1082
CERM
50V
402
0.0022uF
10%
NB_TSENS_EXT
21
XW1080
SM
OMIT
2
1
4
3
J1080
CRITICAL
SM-2MT-BLK-LF
NB_TSENS_EXT
21
R1085
5%
1/16W
0
NB_TSENS_EXT
21
R1086
NB_TSENS_EXT
0
1/16W
5%
4
3
2
1
6
5
J1000
M-RT-SM
CPU_TSENS_EXT
CRITICAL
HS8804F-B
7
6
5
4
3
2
J1070
53398-05
M-ST-SM
AMB_TSENS
CRITICAL
2
1
C1072
AMB_TSENS
CERM 402
10V
20%
0.1UF
21
C1070
NOSTUFF
20% 16V
CERM
402
0.01UF
21
C1071
0.01UF
402
CERM
16V
NOSTUFF
20%
2
1
R1087
1/16W
10K
MF-LF
5%
402
NB_TSENS_EXT
ASIC TEMP SENSORS
SYNC_DATE=(MASTER)
051-7039
H
10 97
SYNC_MASTER=M51_DAVE
NB_TSENS_HS_DXP
SMB_U1080_SCL
U1080_ALERT
SMB_U1080_SDA
U1080_VCC
NB_TSENS_HS_DXN
=SMB_NB_HS_THRM_CLK
=SMB_NB_HS_THRM_DATA
PP3V3_S0
=SMB_CPU_HS_THRM_DATA
PM_THRM_L
THERM_DX_P
CPU_THERMD_N
GND_CHASSIS_CPU_TEMP
CPU_THERMD_P
=SMB_CPU_HS_THRM_CLK
=SMB_GPU_HS_THRM_DATA
=SMB_GPU_HS_THRM_CLK
GND_CHASSIS_GPU_TEMP
GND_CHASSIS_GPU_TEMP
=SMB_AMB_TEMP_DATA
=SMB_AMB_TEMP_CLK
GND_CHASSIS_AMB_TEMP
=SMB_GPU_THRM_DATA
=SMB_GPU_THRM_CLK
SMB_GPU_THRM_CLK
PP3V3_S0
PP3V3_S0
GND_CHASSIS_AMB_TEMP
SMB_GPU_THRM_DATA
GND_CHASSIS_CPU_TEMP
PP3V3_S0
PP3V3_S0
=SMB_THRM_DATA
=SMB_THRM_CLK
THRM_THM
THRM_ALERT_L
THERM_DX_N
84
84
84
84
84
83
83
83
83
83
76
76
76
76
76
45
45
45
45
45
41
41
41
41
41
27
27
27
27
27
26
26
26
26
26
10
10
10
10
10
6
6
6
6
6
5
58
10
10
10
5
5
10
5
5
5
5
27
27
3
27
23
7
6
7
27
27
27
6
6
27
27
10
27
27 85
3
3
10
85
6
3
3
27
27
www.Vinafix.vn
Preliminary
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IO
IO
IO
IO
IO
IO
OUT
IN
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
CONNECTOR’S FBO PIN.
ROUTE THE TCK SIGNAL FROM ITP700FLEX CONNECTOR’S TCK PIN TO CPU’S
518S0320
(TCK)
(FBO)
CPU ITP700FLEX DEBUG SUPPORT
(DEBUG PORT ACTIVE)
(DBR#)
(DBA#)
NC
NC
NC
INDICATE THAT ITP IS USING TAP I/F, NC IN 945GM CHIPSET SYSTEM.
TO ICH7M SYS_RST*, AND WITH SYSTEM RESET LOGIC
(AND WITH RESET BUTTON)
(DEBUG PORT RESET)
(FROM CK410M HOST 133/167MHZ)
P7 HAS OTHER PULL UP RESISTORS THAT MAY IMPACT ITP FUNCTIONALITY
ITP TCK SIGNAL LAYOUT NOTE:
TCK PIN AND THEN FORK BACK FROM CPU TCK PIN AND ROUTE BACK TO ITP700FLEX
21
R1100
MF-LF
22.6
1%
1/16W
402
ITP
21
R1102
ITP
402
1% 1/16W MF-LF
22.6
2
1
R1103
54.9
1/16W
1%
402
ITP
MF-LF
2
1
C1100
16V
402
X5R
10%
0.1UF
ITP
2
1
R1104
240
402
MF-LF
5% 1/16W
ITP
9
8
7
6
5
4
30
3
29
28
27
26
25
24
23
22
21
20
2
19
18
17
16
15
14
13
12
11
10
1
J1101
F-RT-SM
52435-2872
DEVELOPMENT
2
1
R1101
402
54.9
1%
MF-LF
1/16W
2
1
R1106
680
402
5% 1/16W MF-LF
CPU ITP700FLEX DEBUG
SYNC_DATE=08/04/2006
051-7039
H
11 97
SYNC_MASTER=M50_HENRY
=PP1V05_S0_CPU
FSB_CPURST_L
XDP_TDO
ITPRESET_L
ITP_TDO
=PP3V3_S5_SB_PM
=PP1V05_S0_CPU
XDP_BPM_L<5>
XDP_BPM_L<4>
XDP_BPM_L<2>
XDP_TDI XDP_TMS
XDP_TCK
CPU_XDP_CLK_P
CPU_XDP_CLK_N
XDP_TCK
XDP_BPM_L<3>
XDP_BPM_L<1>
XDP_BPM_L<0>
XDP_TRST_L
XDP_DBRESET_L
11
11 9 9
8
12
8
11
11
26
7
7
7
23
7
7
7
7
7
7
7
7
7
7
7
7
7
3
5
5
5
3
3
5
5
5
5
5
5
5
5
5
5
5
5
www.Vinafix.vn
Preliminary
IO
IO
IO
OUT
OUT
OUT
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
OUT
IO
OUT
OUT
OUT
OUT
IO
IO
IO
IO
IO
IN
IO
IN
IO
IO
HD4*
HD6*
HD16*
HTRDY*
HSLPCPU*
HRS1*
HRS0*
HHITM*
HLOCK*
HHIT*
HDSTBP2*
HDTSBP3*
HDSTBP1*
HDSTBP0*
HDSTBN3*
HDSTBN1*
HDSTBN2*
HDSTBN0*
HDINV2*
HDINV3*
HDINV1*
HDINV0*
HDVREF
HDRDY*
HDPWR*
HDEFER*
HDBSY*
HCPURST*
HBREQ0*
HBPRI*
HBNR*
HAVREF
HCLKIN*
HCLKIN
HYSWING
HYRCOMP HYSCOMP
HXSWING
HXSCOMP
HXRCOMP
HA13*
HADS*
HADSTB0*
HD3*
HD2*
HD1*
HD0*
HD63*
HD62*
HD61*
HD60*
HD59*
HD58*
HD57*
HD56*
HD55*
HD54*
HD53*
HD52*
HD51*
HD50*
HD49*
HD48*
HD47*
HD46*
HD45*
HD44*
HD43*
HD42*
HD41*
HD40*
HD39*
HD38*
HD37*
HD36*
HD35*
HD34*
HD33*
HD32*
HD31*
HD29*
HD28*
HD27*
HD26*
HD25*
HD24*
HD23*
HD22*
HD21*
HD20*
HD19*
HD18*
HD17*
HD15*
HD10*
HD11* HD12*
HD13*
HD14*
HD5*
HD7*
HD8* HD9*
HA30*
HA29*
HA28*
HA27*
HA26*
HA25*
HA24*
HA23*
HA31*
HA20*
HA19*
HA18*
HA16*
HA15*
HA14*
HA21*
HA22*
HA17*
HA9*
HA8*
HA7*
HA6*
HA5*
HA4*
HA3*
HA10*
HA11* HA12*
HADSTB1*
HREQ0*
HREQ1*
HREQ2* HREQ3*
HD30*
HREQ4*
HRS2*
(1 OF 10)
HOST
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
2
1
C1211
402
X5R
16V
10%
0.1uF
2
1
R1211
200
1% 1/16W MF-LF 402
2
1
R1210
100
1% 1/16W MF-LF 402
2
1
R1220
54.9
1% 1/16W MF-LF
402
2
1
R1221
402
MF-LF
1/16W
1%
24.9
2
1
R1225
221
1% 1/16W MF-LF 402
2
1
R1226
1% 1/16W MF-LF 402
100
2
1
C1226
0.1uF
402
X5R
16V
10%
2
1
C1236
402
X5R
16V
10%
0.1uF
2
1
R1235
221
1% 1/16W MF-LF 402
2
1
R1230
54.9
1% 1/16W MF-LF
402
2
1
R1236
1% 1/16W MF-LF 402
100
2
1
R1231
402
MF-LF
1/16W
1%
24.9
W1
U1
Y1
E4
E2
E1
E7
E3
D6
E6
B4
A8
F8
B8
G8
D8
B3
D4
D3
K13
AC5
AA5
T6
K3
AC4
Y5
T7
K4
H8
J9
AB10
U3
W8
J7
C3
A7
K1
K9
G2
AC8
AD4
AD10
AB5
G1
AC6
AD7
AC1
AD9
AD1
AC2
AB3
AC11
AB11
AC9
K2
AB4
AA1
Y8
AA10
AA6
AA2
AA7
AA4
W2
AB8
H3
Y10
W5
Y7
Y3
W3
W4
AA9
AB7
T5
W6
J6
T9
U5
W7
T4
T8
T1
W9
T11
U11
U9
H1
U7
T3
W11
T10
G4
K11
J3
H4
J8
K7
J1
F1
B7
AG1
AG2
C7
F6
C6
J13
C13
B9
E8
F9
G12
F11
G11
E11
C9
D14
C14
H9
A14
C12
B14
B12
F12
G13
E13
A13
A12
C11
A11
D12
F14
J15
H13
J14
D9
G14
J12
H11
U1200
BGA
NB
945GM
OMIT
SYNC_MASTER=M50_HENRY
SYNC_DATE=08/04/2006
NB CPU Interface
H
12 97
051-7039
FSB_CPURST_L
FSB_A_L<29>
FSB_A_L<30>
NB_FSB_VREF
FSB_D_L<17>
FSB_DSTBN_L<2>
FSB_DSTBN_L<3>
FSB_DSTBP_L<1> FSB_DSTBP_L<2>
FSB_DSTBP_L<3>
FSB_DINV_L<0>
FSB_DSTBN_L<0>
FSB_DINV_L<1> FSB_DINV_L<2>
FSB_D_L<1> FSB_D_L<2>
FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>
FSB_D_L<10>
FSB_D_L<9>
FSB_D_L<8>
FSB_D_L<7>
FSB_D_L<3>
FSB_D_L<0>
FSB_D_L<16>
FSB_TRDY_L
FSB_SLPCPU_L
FSB_RS_L<1>
FSB_RS_L<0>
FSB_HITM_L FSB_LOCK_L
FSB_HIT_L
FSB_DSTBP_L<0>
FSB_DSTBN_L<1>
FSB_DINV_L<3>
FSB_DRDY_L
FSB_DPWR_L
FSB_DEFER_L
FSB_DBSY_L
FSB_BREQ0_L
FSB_BPRI_L
FSB_BNR_L
FSB_CLK_NB_N
FSB_CLK_NB_P
NB_FSB_YSWING
NB_FSB_YRCOMP NB_FSB_YSCOMP
NB_FSB_XSWING
NB_FSB_XSCOMP
FSB_A_L<13>
FSB_ADS_L
FSB_ADSTB_L<0>
FSB_D_L<63>
FSB_D_L<62>
FSB_D_L<61>
FSB_D_L<60>
FSB_D_L<59>
FSB_D_L<58>
FSB_D_L<57>
FSB_D_L<56>
FSB_D_L<55>
FSB_D_L<54>
FSB_D_L<53>
FSB_D_L<52>
FSB_D_L<51>
FSB_D_L<50>
FSB_D_L<49>
FSB_D_L<48>
FSB_D_L<47>
FSB_D_L<46>
FSB_D_L<45>
FSB_D_L<44>
FSB_D_L<43>
FSB_D_L<42>
FSB_D_L<41>
FSB_D_L<40>
FSB_D_L<39>
FSB_D_L<38>
FSB_D_L<37>
FSB_D_L<36>
FSB_D_L<35>
FSB_D_L<34>
FSB_D_L<33>
FSB_D_L<32>
FSB_D_L<31>
FSB_D_L<29>
FSB_D_L<28>
FSB_D_L<27>
FSB_D_L<26>
FSB_D_L<25>
FSB_D_L<24>
FSB_D_L<23>
FSB_D_L<22>
FSB_D_L<21>
FSB_D_L<20>
FSB_D_L<19>
FSB_D_L<18>
FSB_D_L<15>
FSB_D_L<11>
FSB_D_L<12> FSB_D_L<13>
FSB_D_L<14>
FSB_A_L<28>
FSB_A_L<27>
FSB_A_L<26>
FSB_A_L<25>
FSB_A_L<24>
FSB_A_L<23>
FSB_A_L<31>
FSB_A_L<20>
FSB_A_L<19>
FSB_A_L<18>
FSB_A_L<16>
FSB_A_L<15>
FSB_A_L<14>
FSB_A_L<21>
FSB_A_L<22>
FSB_A_L<17>
FSB_A_L<9>
FSB_A_L<8>
FSB_A_L<7>
FSB_A_L<6>
FSB_A_L<5>
FSB_A_L<4>
FSB_A_L<3>
FSB_A_L<10>
FSB_A_L<11>
FSB_A_L<12>
FSB_ADSTB_L<1>
FSB_REQ_L<0> FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>
FSB_D_L<30>
FSB_REQ_L<4>
FSB_RS_L<2>
=PP1V05_S0_FSB_NB
=PP1V05_S0_FSB_NB
=PP1V05_S0_FSB_NB
NB_FSB_XRCOMP
12
12
12
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
34
34
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
3
3
3
www.Vinafix.vn
Preliminary
CRT_BLUE*
CRT_BLUE
CRT_GREEN*
CRT_GREEN
CRT_RED
CRT_DDC_CLK
CRT_RED*
HSYNC
CRT_DDC_DATA
CRT_VSYNC
CRT_IREF
TV_IRTNC
TV_IRTNB
TV_IREF
TV_IRTNA
TV_DACB_OUT
TV_DACC_OUT
TV_DACA_OUT
LB_DATA2
LB_DATA1
LB_DATA0
LB_DATA2*
LB_DATA1*
LB_DATA0*
LA_DATA2
LA_DATA1
LA_DATA0
LA_DATA2*
LA_DATA1*
LA_DATA0*
LB_CLK
LB_CLK*
LA_CLK
LA_CLK*
L_VDDEN
L_VREFL
L_VREFH
L_VBG
L_IBG
L_DDC_CLK
L_DDC_DATA
EXP_A_COMPI
EXP_A_COMPO
EXP_A_RXN0
EXP_A_RXN1
EXP_A_RXN2
EXP_A_RXN3
EXP_A_RXN4
EXP_A_RXN5
EXP_A_RXN6
EXP_A_RXN7
EXP_A_RXN8
EXP_A_RXN9
EXP_A_RXN10
EXP_A_RXN11
EXP_A_RXN12
EXP_A_RXN13
EXP_A_RXN15
EXP_A_RXN14
EXP_A_RXP0
EXP_A_RXP1
EXP_A_RXP2
EXP_A_RXP4
EXP_A_RXP3
EXP_A_RXP5
EXP_A_RXP6
EXP_A_RXP7
EXP_A_RXP10
EXP_A_RXP9
EXP_A_RXP8
EXP_A_RXP11
EXP_A_RXP12
EXP_A_RXP14
EXP_A_RXP13
EXP_A_RXP15
EXP_A_TXN1
EXP_A_TXN0
EXP_A_TXN3
EXP_A_TXN2
EXP_A_TXN6
EXP_A_TXN5
EXP_A_TXN4
EXP_A_TXN7
EXP_A_TXN8
EXP_A_TXN9
EXP_A_TXN10
EXP_A_TXN11
EXP_A_TXN12
EXP_A_TXN14
EXP_A_TXN13
EXP_A_TXN15
EXP_A_TXP0
EXP_A_TXP2
EXP_A_TXP1
EXP_A_TXP3
EXP_A_TXP4
EXP_A_TXP5
EXP_A_TXP7
EXP_A_TXP6
EXP_A_TXP8
EXP_A_TXP9
EXP_A_TXP10
EXP_A_TXP12
EXP_A_TXP11
EXP_A_TXP13
EXP_A_TXP14
EXP_A_TXP15
L_CLKCTLB
L_BKLTEN
L_CLKCTLA
L_BKLTCTL
(3 OF 10)
LVDS
TV
VGA
PCI-EXPRESS GRAPHICS
IN
IN
OUT
IN
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
IN
OUT
OUT
IO
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IO
IO
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
IO
IO
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Tie VCC_TXLVDS and VCCA_LVDS to GND. If SDVO is used
Can leave all signals NC if LVDS is not implemented
CRT Disable
TV-Out Disable
Composite: DACA only
TV-Out Signal Usage:
HSYNC and VSYNC to GND. Tie VCCA_CRTDAC to VCC Core
Unused DAC outputs must remain powered, but can omit
S-Video: DACB & DACC only
connect to GND through 75-ohm resistors.
Tie VCCD_TVDAC, VCCD_QTVDAC, VCCA_TVDACx, and
Component: DACA, DACB & DACC
rail, and tie VSSA_CRTDAC and VCC_SYNC to GND.
VCCA_TVBG to 1.5V power rail. Tie VSSA_TVBG to GND.
Tie DACx_OUT, IRTNx, and IREF to 1.5V power rail.
filtering components. Unused DAC outputs should
Tie R/R#/G/G#/B/B# and IREF to VCC Core rail, tie
VCCD_LVDS must remain powered with proper decoupling.
LVDS Disable
Otherwise, tie VCCD_LVDS to GND also.
SDVOC_CLKP
SDVOC_BLUE
SDVOC_GREEN
SDVOC_RED
SDVOB_BLUE
SDVOB_CLKP
SDVOB_RED# SDVOB_GREEN#
SDVOB_BLUE#
SDVOB_CLKN SDVOC_RED#
SDVOC_GREEN# SDVOC_BLUE#
SDVOC_CLKN
SDVOB_RED
SDVOB_GREEN
SDVO_FLDSTALL
SDVO_INT
SDVO_TVCLKIN
SDVO_INT#
SDVO_TVCLKIN#
SDVO Alternate Function
SDVO_FLDSTALL#
B19
B18
B16
J20
A19
C18
A16
F29
F28
D30
D29
G30
F30
E27
E26
A37
A36
B35
B34
C37
B37
A33
A32
C32
C33
F32
C35
B38
G25
G26
H29
H30
J30
D32
G23
R40
P36
N40
M36
L40
J36
H40
G36
AB40
AA36
Y40
W36
V40
T36
F40
D36
T40
R36
P40
N36
M40
L36
J40
H36
AC40
AB36
AA40
Y36
W40
V36
G40
F36
R38
P34
N38
M34
L38
J34
H38
G34
AB38
AA34
Y38
W34
V38
T34
F38
D34
T38
R34
P38
N34
M38
L34
J38
H34
AC38
AB34
AA38
Y34
W38
V34
G38
F34
D38
D40
H23
B21
A21
J22
B22
C22
C25
C26
D23
E23
U1200
OMIT
945GM
NB
BGA
2
1
R1310
24.9
1% 1/16W MF-LF 402
NB PEG / Video Interfaces
SYNC_DATE=08/04/2006
SYNC_MASTER=M50_HENRY
13 97
H
051-7039
PEG_R2D_C_N<15>
PEG_R2D_C_N<13>
PEG_R2D_C_N<14>
PEG_R2D_C_N<12>
PEG_R2D_C_N<11>
PEG_R2D_C_N<10>
PEG_R2D_C_N<9>
PEG_R2D_C_N<8>
PEG_R2D_C_N<7>
PEG_R2D_C_N<4>
PEG_R2D_C_N<5>
PEG_R2D_C_N<6>
PEG_D2R_N<10>
PEG_D2R_N<8>
PEG_D2R_N<6>
PEG_D2R_N<5>
PEG_D2R_N<4>
PEG_D2R_N<3>
PEG_D2R_N<9>
PEG_D2R_N<7>
PEG_D2R_N<14>
PEG_D2R_N<13>
PEG_D2R_N<12>
PEG_D2R_N<11>
PEG_D2R_N<15>
LVDS_BKLTCTL
LVDS_CLKCTLA
PEG_D2R_P<1>
CRT_HSYNC_R
CRT_VSYNC_R
LVDS_CLKCTLB
=PP1V5_S0_NB_PCIE
LVDS_BKLTEN
PEG_R2D_C_P<15>
PEG_R2D_C_P<14>
PEG_R2D_C_P<13>
PEG_R2D_C_P<11>
PEG_R2D_C_P<12>
PEG_R2D_C_P<10>
PEG_R2D_C_P<9>
PEG_R2D_C_P<8>
PEG_R2D_C_P<6>
PEG_R2D_C_P<7>
PEG_R2D_C_P<5>
PEG_R2D_C_P<4>
PEG_R2D_C_P<3>
PEG_R2D_C_P<1>
PEG_R2D_C_P<2>
PEG_R2D_C_P<0>
PEG_R2D_C_N<2>
PEG_R2D_C_N<3>
PEG_R2D_C_N<0> PEG_R2D_C_N<1>
PEG_D2R_P<15>
PEG_D2R_P<13> PEG_D2R_P<14>
PEG_D2R_P<12>
PEG_D2R_P<11>
PEG_D2R_P<8>
PEG_D2R_P<9>
PEG_D2R_P<10>
PEG_D2R_P<7>
PEG_D2R_P<6>
PEG_D2R_P<5>
PEG_D2R_P<3>
PEG_D2R_P<4>
PEG_D2R_P<2>
PEG_D2R_P<0>
PEG_D2R_N<2>
PEG_D2R_N<1>
PEG_D2R_N<0>
PEG_COMP
LVDS_DDC_DATA
LVDS_DDC_CLK
LVDS_IBG
TP_LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDS_VDDEN
LVDS_A_CLK_N LVDS_A_CLK_P
LVDS_B_CLK_N LVDS_B_CLK_P
LVDS_A_DATA_N<0>
LVDS_A_DATA_N<1>
LVDS_A_DATA_N<2>
LVDS_A_DATA_P<0> LVDS_A_DATA_P<1>
LVDS_A_DATA_P<2>
LVDS_B_DATA_N<0> LVDS_B_DATA_N<1>
LVDS_B_DATA_N<2>
LVDS_B_DATA_P<0>
LVDS_B_DATA_P<1> LVDS_B_DATA_P<2>
CRT_IREF
CRT_DDC_DATA
CRT_RED_L
CRT_DDC_CLK
CRT_RED
CRT_GREEN
CRT_GREEN_L
CRT_BLUE CRT_BLUE_L
TV_IRTNC
TV_IRTNB
TV_IRTNA
TV_IREF
TV_DACC_OUT
TV_DACB_OUT
TV_DACA_OUT
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
84
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
19
19
5
19
19
19
3
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
www.Vinafix.vn
Preliminary
SM_CS0*
RSVD15
RSVD14
SM_CKE2
RSVD2
RSVD3
RSVD6
RSVD4
RSVD5
RSVD8
RSVD7
RSVD9
RSVD1
RSVD10
RSVD11
RSVD12
RSVD13
CFG1
CFG0
CFG2
CFG3
CFG4
CFG6
CFG5
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG17
CFG16
CFG15
CFG18
CFG19
CFG20
PM_BM_BUSY*
PM_EXTTS0*
PM_EXTTS1*
PW_THRMTRIP*
PWROK
RSTIN*
SDVO_CTRLCLK
SDVO_CTRLDATA
ICH_SYNC*
CLK_REQ*
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC0
NC1
NC13
NC12
NC11
NC10
NC18
NC17
NC16
NC15
NC14
SM_CK0
SM_CK1
SM_CK2
SM_CK0*
SM_CK3
SM_CK1*
SM_CK2*
SM_CK3*
SM_CKE0
SM_CKE1
SM_CKE3
SM_CS1*
SM_CS2*
SM_CS3*
SMOCDCOMP0
SMOCDCOMP1
SM_ODT1
SM_ODT0
SM_ODT2
SMRCOMP*
SM_ODT3
SMRCOMP
SMVREF0
SMVREF1
G_CLKIN*
G_CLKIN
D_REFCLKIN*
D_REFCLKIN
D_REFSSCLKIN*
D_REFSSCLKIN
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP2
DMI_TXP1
DMI_TXP3
DDR MUXING
CFG
NC PM
CLKDMI
MISC
(2 OF 10)
RSVD
IN
IN
IN
IN
IN
OUT
OUT
IN
IN
IN
IO
IO
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
NC NC
IPD
IPD
(LA_DATAN3)
(LA_DATAP3) (LB_DATAN3)
(LB_DATAP3)
(H_EDRDY#)
(D_PLLMON1)
(H_PROCHOT#)
(TESTIN#)
(TV_DCONSEL0)
(TV_DCONSEL1)
(H_PLLMON1)
(H_PLLMON1#)
(H_PCREQ#)
(VSS_MCHDETECT)
(D_PLLMON1#)
NC NC
NC
NC
NC
NC NC
NC
NC NC
NC
NC NC
NC
NC
NC
NC
NC NC
IPU
IPD
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
NC
NC
IPU
IPU
NC
NC
NC
NC
NC
AK41
AK1
AV9
AT9
AF10
AL20
AU21
AY20
BA12
BA13
AW21
AY21
AW12
AW13
AY29
BA29
AT20
AU20
AY40
AW40
AY7
AW7
AT1
AR1
AW35
AY35
H27
H28
K30
J19
H7
AF11
AG11
F7
F3
R32
D27
D28
A34
A35
A41
J29
T32
AH34
AH33
G6
H26
F25
G28
B41
BA1
BA2
BA3
BA39
BA40
BA41
C1
A3
A39
A4
A40
AW1
AW41
AY1
AY41
B2
C41
D1
K28
AF33
AG33
AG41
AF37
AE41
AC37
AH41
AG37
AF41
AE37
AG39
AF35
AE39
AC35
AH39
AG35
AF39
AE35
C40
D41
A27
A26
H32
G16
D16
D19
E18
F15
E15
F18
J26
J18
K27
J25
H15
G18
H16
C15
K15
G15
D15
E16
K18
K16
U1200
BGA
NB
945GM
OMIT
21
R1430
402
MF-LF
1/16W
5%
100
2
1
R1441
10K
402
5%
MF-LF
1/16W
2
1
R1440
10K
402
5% 1/16W MF-LF
2
1
C1416
0.1uF
402
CERM
10V
20%
2
1
C1415
0.1uF
402
CERM
10V
20%
2
1
R1410
1/16W
1%
402
MF-LF
80.6
2
1
R1411
1/16W
1%
402
MF-LF
80.6
2
1
R1420
1/16W
5%
402
MF-LF
10K
SYNC_MASTER=M50_HENRY
SYNC_DATE=08/04/2006
NB Misc Interfaces
051-7039
H
9714
NB_BSEL<1>
TP_NB_XOR_FSB2_H7
TP_NB_XOR_LVDS_D27
TP_NB_XOR_LVDS_D28
TP_NB_XOR_LVDS_A34
MEM_VREF_NB_1
MEM_VREF_NB_0
MEM_RCOMP
MEM_RCOMP_L
=PP1V8_S3_MEM_NB
MEM_CKE<2>
MEM_CS_L<1>
MEM_CS_L<2>
MEM_CS_L<3>
MEM_ODT<1> MEM_ODT<2>
NB_CFG<12>
MEM_CS_L<0>
NB_BSEL<0>
NB_BSEL<2>
NB_CFG<3>
NB_CFG<4>
NB_CFG<6>
NB_CFG<5>
NB_CFG<7>
NB_CFG<9> NB_CFG<10>
NB_CFG<14>
NB_CFG<17>
NB_CFG<16>
NB_CFG<15>
NB_CFG<19>
NB_CFG<20>
PM_BMBUSY_L
PM_THRMTRIP_L VR_PWRGOOD_DELAY
SDVO_CTRLCLK SDVO_CTRLDATA
NB_SB_SYNC_L
MEM_CLK_P<0>
MEM_CLK_P<1> MEM_CLK_P<2>
MEM_CLK_N<0>
MEM_CLK_P<3>
MEM_CLK_N<1> MEM_CLK_N<2>
MEM_CLK_N<3>
MEM_CKE<0> MEM_CKE<1>
MEM_CKE<3>
MEM_ODT<0>
MEM_ODT<3>
NB_CLK100M_GCLKIN_N
NB_CLK100M_GCLKIN_P
DMI_S2N_N<0>
DMI_S2N_N<1>
DMI_S2N_N<2> DMI_S2N_N<3>
DMI_S2N_P<0>
DMI_S2N_P<1> DMI_S2N_P<2>
DMI_S2N_P<3>
DMI_N2S_N<0>
DMI_N2S_N<1> DMI_N2S_N<2>
DMI_N2S_N<3>
DMI_N2S_P<0>
DMI_N2S_P<2>
DMI_N2S_P<1>
DMI_N2S_P<3>
NB_RST_IN_L
NB_CFG<8>
NB_CFG<11>
NB_CFG<13>
NB_CFG<18>
=PP3V3_S0_NB
PM_DPRSLPVR
TP_NB_TESTIN_L
TP_NB_XOR_LVDS_A35
NB_TV_DCONSEL0
NB_TV_DCONSEL1
=PP3V3_S0_NB
NB_CLK_DREFSSCLKIN_P
NB_CLK_DREFSSCLKIN_N
NB_CLK_DREFCLKIN_P
NB_CLK_DREFCLKIN_N
CLK_NB_OE_L
NB_RST_IN_L_R
PM_EXTTS_L
TP_NB_RSVD3_F3
TP_NB_RSVD4_F7
19
75
20
75
20
16
30
30
30
30
30
30
30
26
30
30
30
30
30
22
22
22
22
14
23
14
59
34
3
29
28
29
29
28
29
5
28
34
34
5
5
5
20
20
20
5
5
5
20
5
20
20
23
5
19
19
22
28
28
29
28
29
28
29
29
28
28
29
28
29
34
34
5
22
22
22
5
22
22
22
5
22
22
22
5
22
22
22
6
5
5
5
20
3
5
3
19
19
19
19
33
5
58
www.Vinafix.vn
Preliminary
SA_DQ1
SA_DQ0
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ12
SA_DQ11
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ29
SA_DQ28
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ35
SA_DQ34
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ46
SA_DQ45
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
SA_BS1
SA_BS0
SA_BS2
SA_CAS*
SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM5
SA_DM4
SA_DM7
SA_DM6
SA_DQS0
SA_DQS2
SA_DQS1
SA_DQS3
SA_DQS5
SA_DQS4
SA_DQS6
SA_DQS7
SA_DQS3*
SA_DQS2*
SA_DQS4*
SA_DQS5*
SA_DQS6*
SA_DQS7*
SA_MA1
SA_MA0
SA_MA2
SA_MA3
SA_MA5
SA_MA4
SA_MA6
SA_MA7
SA_MA9
SA_MA8
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_RAS*
SA_RCVENIN*
SA_RCVENOUT*
SA_WE*
SA_DQS1*
SA_DQS0*
(4 OF 10)
DDR SYSTEM MEMORY A
IO
IO
IO
IO
IO
IO
OUT
OUT
OUT
OUT
OUT
IO
OUT
OUT
IO
IO
IO
IO
IO
IO
IO
IO
IO IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
SB_DQ1
SB_DQ0
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ12
SB_DQ11
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ29
SB_DQ28
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ35
SB_DQ34
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ46
SB_DQ45
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
SB_BS1
SB_BS0
SB_BS2
SB_CAS*
SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM5
SB_DM4
SB_DM7
SB_DM6
SB_DQS0
SB_DQS2
SB_DQS1
SB_DQS3
SB_DQS5
SB_DQS4
SB_DQS6
SB_DQS7
SB_DQS3*
SB_DQS2*
SB_DQS4*
SB_DQS5*
SB_DQS6*
SB_DQS7*
SB_MA1
SB_MA0
SB_MA2
SB_MA3
SB_MA5
SB_MA4
SB_MA6
SB_MA7
SB_MA9
SB_MA8
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_RAS*
SB_RCVENIN*
SB_RCVENOUT*
SB_WE*
SB_DQS1*
SB_DQS0*
(5 OF 10)
DDR SYSTEM MEMORY B
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
OUT
OUT
OUT
IO
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IO
OUT
OUT
OUT
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
OUT
IO
IO
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IO
OUT
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
OUT
OUT
OUT
IO
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IO
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
NC NC
NC NC
AY14
AK24
AK23
AW14
AT16
AW17
AU17
AV17
AU16
BA17
BA16
AW16
AV12
AV20
AT17
AU13
AU14
AY16
AH5
AG5
AN3
AP3
AL8
AN8
AM12
AN12
AM21
AM22
AN27
AN28
AU33
AT33
AK32
AK33
AP33
AN35
AH31
AF8
AF4
AH6
AG9
AJ32
AF6
AG4
AF9
AG7
AL2
AN1
AT3
AV2
AN2
AP1
AK35
AW2
AY2
AL5
AT5
AN9
AP9
AK7
AK8
AN7
AK9
AJ36
AL12
AL14
AT12
AT13
AP12
AP13
AR14
AR12
AT21
AP20
AM33
AP24
AL23
AN20
AP21
AL22
AP23
AP26
AM24
AL28
AK28
AM31
AN24
AM26
AL27
AK26
AN33
AM34
AM36
AN38
AP31
AR31
AJ34
AJ35
AH4
AR3
AL9
AM14
AN22
AL26
AM35
AJ33
AY13
BA20
AV14
AU12
U1200
OMIT
NB
945GM
BGA
AR27
AK18
AK16
AU23
AW27
AV27
AV28
AU27
AT28
AT27
AR28
AY24
AR23
AY27
BA27
AV24
AW24
AY23
AP5
AN5
AT7
AR7
AT10
AR10
AP16
AR16
AP29
AR29
AT35
AU35
AU39
AT39
AM40
AM39
AV41
AT40
AP41
AJ3
AJ5
AK5
AT4
AN41
AK3
AK4
AR5
AV4
AY5
AW5
AY9
AY10
AW4
BA4
AK38
AW10
BA10
AJ8
AK10
AH11
AK13
AN10
AJ9
AH10
AJ11
AJ38
AL15
AP15
AM16
AN17
AN14
AP14
AL19
AM19
AW29
AV29
AR41
AW31
AU31
AU29
AT31
BA33
AY33
AP34
AP35
AU36
BA36
AP39
AP36
AR36
AV36
BA38
AY38
AW38
AR40
AP38
AV38
AU38
AJ37
AK39
AN4
BA5
AH8
AL17
BA31
AT36
AR38
AK36
AR24
AY28
AV23
AT24
U1200
OMIT
NB
945GM
BGA
15 97
H
051-7039
NB DDR2 Interfaces
SYNC_MASTER=M50_HENRY
SYNC_DATE=08/04/2006
MEM_A_DQ<5>
MEM_A_DQS_N<0> MEM_A_DQS_N<1>
MEM_A_WE_L
MEM_A_RAS_L
MEM_A_A<13>
MEM_A_A<12>
MEM_A_A<11>
MEM_A_A<10>
MEM_A_A<8> MEM_A_A<9>
MEM_A_A<7>
MEM_A_A<6>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<3>
MEM_A_A<2>
MEM_A_A<0>
MEM_A_A<1>
MEM_A_DQS_N<7>
MEM_A_DQS_N<6>
MEM_A_DQS_N<5>
MEM_A_DQS_N<4>
MEM_A_DQS_N<2>
MEM_A_DQS_N<3>
MEM_A_DQS_P<7>
MEM_A_DQS_P<6>
MEM_A_DQS_P<4>
MEM_A_DQS_P<5>
MEM_A_DQS_P<3>
MEM_A_DQS_P<1>
MEM_A_DQS_P<2>
MEM_A_DQS_P<0>
MEM_A_DM<6> MEM_A_DM<7>
MEM_A_DM<4>
MEM_A_DM<5>
MEM_A_DM<3>
MEM_A_DM<2>
MEM_A_DM<1>
MEM_A_DM<0>
MEM_A_CAS_L
MEM_A_BS<2>
MEM_A_BS<0>
MEM_A_BS<1>
MEM_A_DQ<63>
MEM_A_DQ<62>
MEM_A_DQ<61>
MEM_A_DQ<60>
MEM_A_DQ<59>
MEM_A_DQ<58>
MEM_A_DQ<57>
MEM_A_DQ<56>
MEM_A_DQ<55>
MEM_A_DQ<54>
MEM_A_DQ<53>
MEM_A_DQ<52>
MEM_A_DQ<51>
MEM_A_DQ<50>
MEM_A_DQ<49>
MEM_A_DQ<48>
MEM_A_DQ<47>
MEM_A_DQ<45> MEM_A_DQ<46>
MEM_A_DQ<44>
MEM_A_DQ<43>
MEM_A_DQ<42>
MEM_A_DQ<41>
MEM_A_DQ<40>
MEM_A_DQ<39>
MEM_A_DQ<38>
MEM_A_DQ<37>
MEM_A_DQ<36>
MEM_A_DQ<34> MEM_A_DQ<35>
MEM_A_DQ<33>
MEM_A_DQ<32>
MEM_A_DQ<31>
MEM_A_DQ<30>
MEM_A_DQ<28>
MEM_A_DQ<29>
MEM_A_DQ<27>
MEM_A_DQ<26>
MEM_A_DQ<25>
MEM_A_DQ<24>
MEM_A_DQ<23>
MEM_A_DQ<22>
MEM_A_DQ<21>
MEM_A_DQ<20>
MEM_A_DQ<19>
MEM_A_DQ<18>
MEM_A_DQ<17>
MEM_A_DQ<16>
MEM_A_DQ<15>
MEM_A_DQ<14>
MEM_A_DQ<13>
MEM_A_DQ<11>
MEM_A_DQ<12>
MEM_A_DQ<10>
MEM_A_DQ<9>
MEM_A_DQ<8>
MEM_A_DQ<7>
MEM_A_DQ<6>
MEM_A_DQ<4>
MEM_A_DQ<3>
MEM_A_DQ<2>
MEM_A_DQ<0>
MEM_A_DQ<1>
MEM_B_DQS_N<0> MEM_B_DQS_N<1>
MEM_B_WE_L
MEM_B_RAS_L
MEM_B_A<13>
MEM_B_A<12>
MEM_B_A<11>
MEM_B_A<10>
MEM_B_A<8> MEM_B_A<9>
MEM_B_A<7>
MEM_B_A<6>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<3>
MEM_B_A<2>
MEM_B_A<0>
MEM_B_A<1>
MEM_B_DQS_N<7>
MEM_B_DQS_N<6>
MEM_B_DQS_N<5>
MEM_B_DQS_N<4>
MEM_B_DQS_N<2>
MEM_B_DQS_N<3>
MEM_B_DQS_P<7>
MEM_B_DQS_P<6>
MEM_B_DQS_P<4>
MEM_B_DQS_P<5>
MEM_B_DQS_P<3>
MEM_B_DQS_P<1>
MEM_B_DQS_P<2>
MEM_B_DQS_P<0>
MEM_B_DM<6> MEM_B_DM<7>
MEM_B_DM<4>
MEM_B_DM<5>
MEM_B_DM<3>
MEM_B_DM<2>
MEM_B_DM<1>
MEM_B_DM<0>
MEM_B_CAS_L
MEM_B_BS<2>
MEM_B_BS<0>
MEM_B_BS<1>
MEM_B_DQ<63>
MEM_B_DQ<62>
MEM_B_DQ<61>
MEM_B_DQ<60>
MEM_B_DQ<59>
MEM_B_DQ<58>
MEM_B_DQ<57>
MEM_B_DQ<56>
MEM_B_DQ<55>
MEM_B_DQ<54>
MEM_B_DQ<53>
MEM_B_DQ<52>
MEM_B_DQ<51>
MEM_B_DQ<50>
MEM_B_DQ<49>
MEM_B_DQ<48>
MEM_B_DQ<47>
MEM_B_DQ<45> MEM_B_DQ<46>
MEM_B_DQ<44>
MEM_B_DQ<43>
MEM_B_DQ<42>
MEM_B_DQ<41>
MEM_B_DQ<40>
MEM_B_DQ<39>
MEM_B_DQ<38>
MEM_B_DQ<37>
MEM_B_DQ<36>
MEM_B_DQ<34> MEM_B_DQ<35>
MEM_B_DQ<33>
MEM_B_DQ<32>
MEM_B_DQ<31>
MEM_B_DQ<30>
MEM_B_DQ<28>
MEM_B_DQ<29>
MEM_B_DQ<27>
MEM_B_DQ<26>
MEM_B_DQ<25>
MEM_B_DQ<24>
MEM_B_DQ<23>
MEM_B_DQ<22>
MEM_B_DQ<21>
MEM_B_DQ<20>
MEM_B_DQ<19>
MEM_B_DQ<18>
MEM_B_DQ<17>
MEM_B_DQ<16>
MEM_B_DQ<15>
MEM_B_DQ<14>
MEM_B_DQ<13>
MEM_B_DQ<11>
MEM_B_DQ<12>
MEM_B_DQ<10>
MEM_B_DQ<9>
MEM_B_DQ<8>
MEM_B_DQ<7>
MEM_B_DQ<6>
MEM_B_DQ<5>
MEM_B_DQ<4>
MEM_B_DQ<3>
MEM_B_DQ<2>
MEM_B_DQ<0>
MEM_B_DQ<1>
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
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29
29
29
29
29
29
29
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29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
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29
29
29
29
29
29
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29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
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29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
www.Vinafix.vn
Preliminary
VCC_SM19
VCC_SM107
VCC_SM105
VCC_SM106
VCC_SM102
VCC_SM104
VCC_SM103
VCC_SM100
VCC_SM101
VCC_SM98
VCC_SM99
VCC_SM97
VCC_SM95
VCC_SM96
VCC_SM93
VCC_SM94
VCC_SM92
VCC_SM91
VCC_SM90
VCC_SM89
VCC_SM88
VCC_SM86
VCC_SM87
VCC_SM85
VCC_SM84
VCC_SM83
VCC_SM81
VCC_SM80
VCC_SM82
VCC_SM79
VCC_SM78
VCC_SM77
VCC_SM74
VCC_SM75
VCC_SM76
VCC_SM73
VCC_SM72
VCC_SM70
VCC_SM71
VCC_SM68
VCC_SM67
VCC_SM69
VCC_SM65
VCC_SM66
VCC_SM64
VCC_SM63
VCC_SM62
VCC_SM61
VCC_SM60
VCC_SM59
VCC_SM58
VCC_SM56
VCC_SM57
VCC_SM55
VCC_SM53
VCC_SM54
VCC_SM52
VCC_SM50
VCC_SM51
VCC_SM49
VCC_SM48
VCC_SM46
VCC_SM47
VCC_SM44
VCC_SM45
VCC_SM43
VCC_SM41
VCC_SM42
VCC_SM40
VCC_SM39
VCC_SM37
VCC_SM38
VCC_SM36
VCC_SM34
VCC_SM35
VCC_SM32
VCC_SM33
VCC_SM30
VCC_SM31
VCC_SM28
VCC_SM29
VCC_SM27
VCC_SM26
VCC_SM25
VCC_SM23
VCC_SM24
VCC_SM22
VCC_SM21
VCC_SM20
VCC_SM18
VCC_SM16
VCC_SM17
VCC_SM15
VCC_SM13
VCC_SM14
VCC_SM11
VCC_SM12
VCC_SM10
VCC_SM9
VCC_SM8
VCC_SM7
VCC_SM6
VCC_SM5
VCC_SM4
VCC_SM3
VCC_SM0
VCC_SM1
VCC_SM2
VCC_110
VCC_109
VCC_108
VCC_105
VCC_106
VCC_107
VCC_104
VCC_103
VCC_101
VCC_100
VCC_102
VCC_98
VCC_99
VCC_96
VCC_97
VCC_95
VCC_94
VCC_93
VCC_92
VCC_91
VCC_90
VCC_88
VCC_89
VCC_87
VCC_86
VCC_85
VCC_83
VCC_84
VCC_82
VCC_80
VCC_81
VCC_79
VCC_78
VCC_76
VCC_77
VCC_74
VCC_73
VCC_75
VCC_72
VCC_71
VCC_70
VCC_69
VCC_68
VCC_67
VCC_66
VCC_65
VCC_64
VCC_62
VCC_63
VCC_61
VCC_60
VCC_59
VCC_57
VCC_58
VCC_55
VCC_56
VCC_53
VCC_54
VCC_52
VCC_50
VCC_51
VCC_49
VCC_46
VCC_47
VCC_48
VCC_44
VCC_45
VCC_43
VCC_42
VCC_41
VCC_40
VCC_39
VCC_38
VCC_37
VCC_36
VCC_34
VCC_35
VCC_33
VCC_32
VCC_31
VCC_30
VCC_28
VCC_29
VCC_25
VCC_26
VCC_27
VCC_24
VCC_23
VCC_21
VCC_20
VCC_22
VCC_13
VCC_14
VCC_12
VCC_16
VCC_15
VCC_17
VCC_18
VCC_19
VCC_11
VCC_10
VCC_9
VCC_8
VCC_7
VCC_4
VCC_5
VCC_6
VCC_2
VCC_3
VCC_0
VCC_1
(6 OF 10)
VCC
VCCAUX_NCTF57
VCCAUX_NCTF56
VCCAUX_NCTF55
VCCAUX_NCTF54
VCCAUX_NCTF53
VCCAUX_NCTF52
VCCAUX_NCTF51
VCCAUX_NCTF50
VCCAUX_NCTF49
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF45
VCCAUX_NCTF44
VCCAUX_NCTF46
VCCAUX_NCTF40
VCCAUX_NCTF39
VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF36
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF31
VCCAUX_NCTF30
VCCAUX_NCTF29
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF26
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF22
VCCAUX_NCTF21
VCCAUX_NCTF23
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF41
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF18
VCCAUX_NCTF17
VCCAUX_NCTF16
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF13
VCCAUX_NCTF12
VCCAUX_NCTF11
VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF8
VCCAUX_NCTF7
VCCAUX_NCTF6
VCCAUX_NCTF5
VCCAUX_NCTF4
VCCAUX_NCTF3
VCCAUX_NCTF1
VCCAUX_NCTF0
VCCAUX_NCTF2
VSS_NCTF12
VSS_NCTF11
VSS_NCTF10
VSS_NCTF9
VSS_NCTF7
VSS_NCTF8
VSS_NCTF5
VSS_NCTF6
VSS_NCTF4
VSS_NCTF2
VSS_NCTF3
VSS_NCTF0
VSS_NCTF1
VCC_NCTF72
VCC_NCTF71
VCC_NCTF70
VCC_NCTF69
VCC_NCTF68
VCC_NCTF67
VCC_NCTF66
VCC_NCTF65
VCC_NCTF64
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF60
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF56
VCC_NCTF55
VCC_NCTF53
VCC_NCTF54
VCC_NCTF52
VCC_NCTF50
VCC_NCTF51
VCC_NCTF49
VCC_NCTF48
VCC_NCTF46
VCC_NCTF47
VCC_NCTF45
VCC_NCTF44
VCC_NCTF43
VCC_NCTF41
VCC_NCTF40
VCC_NCTF42
VCC_NCTF38
VCC_NCTF39
VCC_NCTF36
VCC_NCTF37
VCC_NCTF34
VCC_NCTF35
VCC_NCTF33
VCC_NCTF31
VCC_NCTF32
VCC_NCTF30
VCC_NCTF29
VCC_NCTF28
VCC_NCTF27
VCC_NCTF26
VCC_NCTF25
VCC_NCTF24
VCC_NCTF23
VCC_NCTF22
VCC_NCTF21
VCC_NCTF20
VCC_NCTF18
VCC_NCTF19
VCC_NCTF17
VCC_NCTF16
VCC_NCTF15
VCC_NCTF13
VCC_NCTF14
VCC_NCTF11
VCC_NCTF12
VCC_NCTF10
VCC_NCTF8
VCC_NCTF9
VCC_NCTF7
VCC_NCTF6
VCC_NCTF5
VCC_NCTF4
VCC_NCTF3
VCC_NCTF2
VCC_NCTF0
VCC_NCTF1
(7 OF 10)
NCTF
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Place in cavity
1.05V or 1.5V
Layout Note:
Layout Note:
These connections can break without
NCTF balls are Not Critical To Function
impacting part performance.
Layout Note:
(Need to better define cavity)
Place near pin BA23
Place near pin BA15
AT6
AV6
AW6
AY6
BA6
AP8
AR8
AT8
AV8
AW8
AT34
AY8
BA8
AK11
AG12
AH12
AJ12
AK12
AH13
AJ13
AJ14
AU34
AJ15
AR15
AT15
AU15
AV15
AW15
AY15
BA15
AH16
AJ16
AV34
AH17
AJ17
AJ18
AJ19
AK19
AP19
AR19
AT19
AU19
AV19
AW34
AW19
AY19
BA19
AK20
AK21
AJ22
AK22
AP22
AR22
AT22
AY34
AU22
AV22
AW22
AY22
BA22
AJ23
BA23
AH24
AJ24
AH25
BA34
AJ25
AH26
AJ26
AR26
AT26
AU26
AV26
AW26
AY26
BA26
AU40
AH27
AJ27
AH28
AJ28
AH29
AJ29
AK29
AL29
AM29
AM30
AM41
AN30
AP30
AR30
AT30
AU30
AV30
AW30
AY30
BA30
AJ1
AV1
AJ6
AK6
AL6
AN6
AP6
AR6
AR34
AT41
AU41
N19
Y19
AA19
AB19
L20
M20
N20
P20
W20
Y20
V32
AB20
AC20
L21
M21
N21
W21
AA21
AC21
L22
M22
W32
N22
P22
W22
Y22
AB22
AC22
L23
M23
N23
P23
Y32
Y23
AA23
AB23
M24
N24
P24
L25
M25
N25
L26
AA32
N26
P26
L27
M27
N27
P27
L28
M28
N28
P28
J33
R28
T28
U28
V28
Y28
AA28
AB28
L29
M29
P29
L33
R29
U29
V29
W29
Y29
AA29
L30
M30
N30
P30
N33
R30
T30
U30
V30
W30
Y30
AA30
M31
N31
P31
P33
R31
T31
V31
W31
AA31
J32
L32
M32
L16
N32
M16
N16
M17
N17
P17
L18
M18
N18
L19
M19
P32
W33
AA33
U1200
OMIT
BGA
NB
945GM
2
1
C1610
402
6.3V CERM-X5R
0.47UF
10%
2
1
C1621
10UF
CERM
20%
6.3V
805-1
2
1
C1620
6.3V
20%
10UF
CERM
805-1
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
U17
Y17
AC17
AE26
AE27
AF23
AG23
AF24
AG24
R15
T15
U15
V15
W15
Y15
AA15
AB15
AF25
AC15
AD15
AE15
AF15
AG15
R16
T16
U16
V16
W16
AG25
Y16
AA16
AB16
AC16
AD16
AE16
AF16
AG16
R17
T17
AF26
V17
W17
AA17
AB17
AD17
AE17
AF17
AG17
R18
AF18
AG26
AG18
R19
AF19
AG19
AF20
AG20
AF21
AG21
AF22
AG22
AF27
AG27
R27
T27
T18
U18
V18
U27
W18
Y18
AA18
AB18
AC18
AD18
T19
U19
V19
AD19
V27
R20
T20
U20
V20
AD20
R21
T21
U21
V21
AD21
W27
R22
T22
U22
V22
AD22
R23
T23
U23
V23
AD23
Y27
R24
T24
U24
V24
W24
Y24
AA24
AB24
AC24
AD24
AA27
R25
T25
U25
V25
W25
Y25
AA25
AB25
AC25
AD25
AB27
R26
T26
U26
V26
W26
Y26
AA26
AB26
AC26
AD26
AC27
AD27
U1200
OMIT
BGA
NB
945GM
2
1
C1611
402
6.3V CERM-X5R
0.47UF
10%
2
1
C1612
402
6.3V
CERM-X5R
0.47UF
10%
2
1
C1613
402
6.3V CERM-X5R
0.47UF
10%
2
1
C1614
402
6.3V
CERM-X5R
0.47UF
10%
2
1
C1615
402
6.3V CERM-X5R
0.47UF
10%
16 97
H
051-7039
SYNC_MASTER=M51_HENRY
SYNC_DATE=08/04/2006
NB Power 1
=PP1V8_S3_MEM_NB
NB_VCCSM_LF4
NB_VCCSM_LF5
=PPVCORE_S0_NB
=PP1V5_S0_NB_VCCAUX
=PPVCORE_S0_NB
NB_VCCSM_LF1
NB_VCCSM_LF2
19
19
19
19
14
16
17
16
3
3
3
3
www.Vinafix.vn
Preliminary
VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT15
VTT14
VTT16
VTT18
VTT17
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT27
VTT26
VTT28
VTT29
VTT31
VTT30
VTT32
VTT34
VTT33
VTT35
VTT36
VTT37
VTT39
VTT38
VTT40
VTT41
VTT42
VTT43
VTT44
VTT45
VTT48
VTT46
VTT47
VTT49
VTT50
VTT52
VTT51
VTT53
VTT55
VTT54
VTT57
VTT56
VTT58
VTT59
VTT60
VTT61
VTT62
VTT64
VTT63
VTT65
VTT66
VTT67
VTT69
VTT68
VTT70
VTT71
VTT73
VTT72
VTT74
VTT76
VTT75
VCCSYNC
VCC_TXLVDS0
VCC_TXLVDS1
VCC_TXLVDS2
VCC3G0
VCC3G1
VCC3G3
VCC3G2
VCC3G4
VCC3G6
VCC3G5
VCCA_3GPLL
VCCA_3GBG
VSSA_3GBG
VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC
VCCA_DPLLB
VCCA_DPLLA
VCCA_HPLL
VSSA_LVDS
VCCA_LVDS
VCCA_MPLL
VCCA_TVBG
VSSA_TVBG
VCCA_TVDACC0
VCCA_TVDACC1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACA0
VCCA_TVDACA1
VCCD_HMPLL0
VCCD_HMPLL1
VCCD_LVDS2
VCCD_LVDS0
VCCD_LVDS1
VCCD_TVDAC
VCC_HV1
VCC_HV2
VCC_HV0
VCCD_QTVDAC
VCCAUX19
VCCAUX18
VCCAUX17
VCCAUX16
VCCAUX14
VCCAUX15
VCCAUX13
VCCAUX12
VCCAUX11
VCCAUX10
VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX6
VCCAUX5
VCCAUX9
VCCAUX8
VCCAUX7
VCCAUX21
VCCAUX20
VCCAUX23
VCCAUX24
VCCAUX22
VCCAUX25
VCCAUX26
VCCAUX29
VCCAUX28
VCCAUX27
VCCAUX30
VCCAUX31
VCCAUX33
VCCAUX32
VCCAUX34
VCCAUX35
VCCAUX36
VCCAUX38
VCCAUX37
VCCAUX39
VCCAUX40
POWER
(8 OF 10)
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
L14
M14
M1
N1
P1
R1
AB1
D2
M2
N14
P2
R2
M3
N3
P3
R3
M4
N4
P4
M5
P14
N5
P5
R5
A6
M6
P6
R6
M7
N7
P7
R14
M8
N8
P8
R8
M9
N9
P9
M10
N10
P10
T14
R10
M11
N11
P11
R11
L12
M12
N12
P12
R12
V14
T12
U12
V12
W12
Y12
AA12
AB12
L13
M13
N13
W14
R13
T13
U13
V13
W13
Y13
AA13
AB13
AC13
AD13
AB14
AC14
G20
B39
G21
H41
H22
D21
H19
C28
B28
A28
AH2
AH1
AF30
AG30
AH30
AJ30
AK30
AD12
AL30
AE12
AF12
AE13
AF13
Y14
AE14
AF14
AG14
AH14
P15
AC31
AH15
P16
P19
AH19
AH20
AJ20
AH21
AJ21
AH22
AE28
AE31
AF28
AG28
AC29
AD29
AE29
AF29
AG29
AC30
AD30
AE30
AF31
AK31
F20
E20
D20
C20
F19
E19
H20
AF2
A38
AF1
C39
B26
E21
F21
AC33
G41
A30
B30
C30
B25
B23
A23
L41
N41
R41
V41
Y41
AB41
AJ41
U1200
OMIT
BGA
NB
945GM
2
1
C1711
10%
0.47UF
6.3V
CERM-X5R
402
2
1
C1712
402
6.3V
20%
X5R
0.22UF
2
1
C1713
10%
0.47UF
CERM-X5R
6.3V
402
SYNC_MASTER=M51_HENRY
NB Power 2
SYNC_DATE=08/04/2006
051-7039
H
9717
NB_VTTLF_CAP2
NB_VTTLF_CAP1
PP1V5_S0_NB_VCCA_DPLLB
=PP2V5_S0_NB_VCCSYNC
=PP2V5_S0_NB_VCC_TXLVDS
PP1V5_S0_NB_VCC3G
PP1V5_S0_NB_VCCA_3GPLL =PP2V5_S0_NB_VCCA_3GBG
GND_NB_VSSA_3GBG
GND_NB_VSSA_CRTDAC
PP1V5_S0_NB_VCCA_DPLLA
PP1V5_S0_NB_VCCA_HPLL
GND_NB_VSSA_LVDS
=PP2V5_S0_NB_VCCA_LVDS
PP1V5_S0_NB_VCCA_MPLL
PP3V3_S0_NB_VCCA_TVBG
GND_NB_VSSA_TVBG
PP3V3_S0_NB_VCCA_TVDACC
PP3V3_S0_NB_VCCA_TVDACB
PP3V3_S0_NB_VCCA_TVDACA
=PP1V5_S0_NB_VCCD_HMPLL
=PP1V5_S0_NB_VCCD_LVDS
PP1V5_S0_NB_VCCD_TVDAC
=PP3V3_S0_NB_VCC_HV
PP1V5_S0_NB_VCCD_QTVDAC
=PP1V5_S0_NB_VCCAUX
PP2V5_S0_NB_VCCA_CRTDAC
NB_VTTLF_CAP3
=PP1V05_S0_NB_VTT
19
19
19
16
19
19
19
19
19
19
3
19
19
19
19
19
19
19
19
19
19
19
19
3
19
19
3
19
3
19
3
www.Vinafix.vn
Preliminary
VSS_1
VSS_0
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_9
VSS_8
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_19
VSS_18
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_28
VSS_27
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_37
VSS_36
VSS_39
VSS_38
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_49
VSS_48
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_57
VSS_56
VSS_59
VSS_58
VSS_61
VSS_60
VSS_64
VSS_63
VSS_62
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_73
VSS_72
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_82
VSS_80
VSS_81
VSS_84
VSS_83
VSS_85
VSS_87
VSS_86
VSS_89
VSS_88
VSS_91
VSS_90
VSS_92
VSS_93
VSS_94
VSS_96
VSS_95
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_114
VSS_113
VSS_115
VSS_117
VSS_116
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_127
VSS_126
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_137
VSS_136
VSS_138
VSS_139
VSS_140
VSS_141
VSS_143
VSS_142
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_158
VSS_157
VSS_159
VSS_160
VSS_161
VSS_162
VSS_164
VSS_163
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_172
VSS_171
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS
(9 OF 10)
VSS_272
VSS_271
VSS_269
VSS_270
VSS_268
VSS_266
VSS_267
VSS_265
VSS_264
VSS_263
VSS_261
VSS_262
VSS_260
VSS_259
VSS_258
VSS_256
VSS_257
VSS_255
VSS_254
VSS_253
VSS_251
VSS_252
VSS_250
VSS_248
VSS_249
VSS_247
VSS_246
VSS_245
VSS_243
VSS_244
VSS_242
VSS_241
VSS_240
VSS_238
VSS_239
VSS_237
VSS_236
VSS_235
VSS_233
VSS_234
VSS_232
VSS_231
VSS_230
VSS_228
VSS_229
VSS_227
VSS_225
VSS_226
VSS_224
VSS_223
VSS_222
VSS_220
VSS_221
VSS_219
VSS_218
VSS_217
VSS_215
VSS_216
VSS_214
VSS_213
VSS_212
VSS_210
VSS_211
VSS_209
VSS_207
VSS_208
VSS_205
VSS_206
VSS_204
VSS_202
VSS_203
VSS_201
VSS_200
VSS_199
VSS_197
VSS_198
VSS_196
VSS_195
VSS_194
VSS_192
VSS_193
VSS_191
VSS_190
VSS_189
VSS_187
VSS_188
VSS_186
VSS_184
VSS_185
VSS_183
VSS_182
VSS_180
VSS_181
VSS_273
VSS_274
VSS_276
VSS_275
VSS_277
VSS_279
VSS_278
VSS_281
VSS_280
VSS_282
VSS_283
VSS_284
VSS_286
VSS_285
VSS_287
VSS_288
VSS_289
VSS_291
VSS_290
VSS_293
VSS_292
VSS_294
VSS_296
VSS_295
VSS_297
VSS_299
VSS_298
VSS_301
VSS_302
VSS_300
VSS_304
VSS_303
VSS_305
VSS_306
VSS_307
VSS_309
VSS_308
VSS_311
VSS_310
VSS_312
VSS_313
VSS_314
VSS_315
VSS_317
VSS_316
VSS_318
VSS_319
VSS_320
VSS_322
VSS_321
VSS_323
VSS_324
VSS_325
VSS_327
VSS_326
VSS_328
VSS_329
VSS_330
VSS_332
VSS_331
VSS_334
VSS_333
VSS_335
VSS_337
VSS_336
VSS_338
VSS_339
VSS_340
VSS_342
VSS_343
VSS_341
VSS_345
VSS_344
VSS_346
VSS_347
VSS_348
VSS_350
VSS_349
VSS_352
VSS_351
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360
VSS
(10 OF 10)
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
AF34
AG34
AK34
AN34
D35
F35
G35
H35
J35
L35
AP40
M35
N35
P35
R35
T35
V35
W35
Y35
AA35
AB35
AV40
AH35
AR35
AV35
BA35
B36
C36
AC36
AE36
AF36
AG36
F41
AH36
AN36
AW36
AY36
D37
F37
G37
H37
J37
L37
J41
M37
N37
P37
R37
T37
V37
W37
Y37
AA37
AB37
M41
AH37
AK37
C38
AE38
AF38
AG38
AH38
AM38
AT38
D39
P41
F39
G39
H39
J39
L39
M39
N39
P39
R39
T39
T41
V39
W39
Y39
AA39
AB39
AC39
AJ39
AN39
AR39
AV39
W41
AW39
AY39
AW23
AL24
AU24
BA24
A25
D25
E25
H25
K25
P25
B40
AK25
D26
F26
K26
M26
AN26
B27
C27
F27
G27
AE40
J27
AK27
AM27
AP27
E28
J28
W28
AC28
AD28
AM28
AF40
AP28
AU28
AW28
BA28
A29
B29
C29
E29
G29
K29
AG40
N29
T29
AB29
AN29
AT29
E30
AB30
Y31
AB31
AG31
AH40
AJ31
AN31
AV31
AY31
B32
G32
AB32
AC32
AE32
AF32
AJ40
AG32
AH32
B33
D33
F33
G33
H33
M33
R33
T33
AK40
V33
Y33
AB33
AE33
AR33
AV33
AW33
C34
AC34
AE34
AN40
AA41
AC41
U1200
OMIT
BGA
945GM
NB
AL1
C2
F2
H2
J2
N2
T2
U2
Y2
AB2
AD2
AJ2
AK2
AP2
AR2
AT2
G3
AA3
AC3
AD3
AF3
AG3
AH3
AL3
AV3
AW3
AY3
C4
F4
J4
R4
U4
Y4
AJ4
AL4
AP4
AR4
AY4
AD5
AF5
AV5
B6
H6
K6
N6
U6
Y6
AB6
AD6
AG6
D7
G7
R7
AC7
AF7
AH7
AJ7
AL7
AP7
AV7
BA7
C8
K8
U8
AA8
AD8
AG8
A9
E9
G9
R9
Y9
AB9
AH9
AR9
AW9
BA9
U10
W10
AC10
AG10
AJ10
AL10
AP10
AV10
B11
D11
J11
Y11
AA11
AD11
E12
H12
K12
AC12
AY12
B13
D13
F13
P13
AG13
AL13
AM13
AN13
AR13
AV13
E14
H14
K14
U14
AA14
AD14
AK14
AT14
BA14
A15
B15
L15
M15
N15
AK15
AM15
AN15
C16
F16
J16
AL16
AN16
AV16
AK17
AM17
AP17
AR17
AY17
A18
D18
H18
P18
AH18
C19
G19
K19
W19
AC19
AN19
A20
B20
K20
AA20
AM20
AR20
AW20
C21
H21
J21
K21
P21
Y21
AB21
AL21
AN21
AR21
AV21
BA21
A22
D22
E22
F22
G22
K22
AA22
C23
F23
J23
K23
W23
AC23
AH23
AM23
AN23
AT23
U1200
OMIT
BGA
945GM
NB
18 97
H
051-7039
NB Grounds
SYNC_MASTER=M50_HENRY
SYNC_DATE=08/04/2006
www.Vinafix.vn
Preliminary
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
These 4 0.1uF caps should
Layout Note:
TVOUT DISABLE
DISPLAY DISABLE
Layout Note:
Layout Note:
LVDS DISABLE
on opposite side.
10uF caps should
Layout Note:
Place on the edge
be close to MCH
Place L and C close to MCH
TVOUT DISABLE
be within 5 mm of NB edge
1uH, 20%
Layout Note: 3GPLL 10uF cap should
be placed in cavity
Layout Note: Route to caps, then GND
Layout Note:
Place in cavity
2
1
C1970
2.5V POLY SMB2
220UF
20%
2
1
C1967
0.22uF
402
6.3V
20%
X5R
2
1
C1966
2.2UF
10%
6.3V
603
CERM1
2
1
C1965
CERM
4.7uF
6.3V
603
20%
2
1
C1976
CERM
20%
402
10V
0.1uF
2
1
C1975
10uF
20%
6.3V X5R 603
21
R1975
0.51
1%
402
MF-LF
1/16W
21
L1975
0805
1.0UH-220MA-0.12-OHM
2
1
C1918
0.1uF
10V CERM 402
20%
2
1
C1915
0.1uF
20%
402
CERM
10V
2
1
C1914
10uF
20%
6.3V X5R 603
2
1
C1916
10V CERM 402
20%
0.1uF
21
R1980
5%
402
MF-LF
1/16W
1K
2
1
R1981
402
MF-LF
1/16W
5%
1K
2
1
R1983
MF-LF 402
1/16W
5%
1K
21
R1982
5%
402
MF-LF
1/16W
1K
21
L1970
91NH
1210
21
XW1900
OMIT
SM
2
1
C1968
330UF
NOSTUFF
ELEC
6.3V
20%
CASE-C1
21
L1934
0603
FERR-120-OHM-0.2A
2
1
C1907
6.3V
20%
0.22uF
402
X5R
2
1
C1972
10uF
20%
6.3V X5R 603
2
1
C1971
603
6.3V
10uF
20%
X5R
2
1
C1906
X5R
20%
0.22uF
6.3V
402
2
1
C1905
X5R
20%
0.22uF
6.3V
402
2
1
C1904
1UF
402
6.3V
10%
CERM
2
1
C1937
402
10V CERM
20%
0.1uF
2
1
C1935
0.1uF
402
CERM
10V
20%
2
1
C1934
6.3V
20%
805
22uF
X5R
21
L1936
0603
FERR-120-OHM-0.2A
2
1
C1936
22uF
X5R 805
6.3V
20%
2
1
C1903
10uF
603
20%
6.3V X5R
2
1
C1902
603
20%
X5R
6.3V
10uF
2
1
C1901
20%
6.3V
CASE-C1
ELEC
330UF
2
1
C1900
330UF
CASE-C1
6.3V
20%
ELEC
SYNC_MASTER=M51_DAVE
NB (GM) Decoupling
SYNC_DATE=(MASTER)
19 97
H
051-7039
=PP1V5_S0_NB
=PP1V5_S0_NB_TVDAC
PP1V5_S0_NB_VCCD_QTVDAC
PP1V5_S0_NB_VCCD_TVDAC
PP3V3_S0_NB_VCCA_TVBG
PP3V3_S0_NB_VCCA_TVDACA PP3V3_S0_NB_VCCA_TVDACB
PP3V3_S0_NB_VCCA_TVDACC
TV_DACA_OUT
TV_DACB_OUT
TV_DACC_OUT
TV_IREF
TV_IRTNA
TV_IRTNB TV_IRTNC
MEM_VREF_NB_0MEM_VREF_NB_1
=PP1V05_S0_NB_VTT
=PP1V5_S0_NB_PLL
GND_NB_VSSA_3GBG
=PP1V8_S3_MEM_NB
LVDS_CLKCTLB
LVDS_DDC_DATA
MIN_LINE_WIDTH=1.0 mm
PP1V5_S0_NB_VCCA_MPLL
VOLTAGE=1.5V
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.5V
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=1.0 mm
PP1V5_S0_NB_VCC3G
VOLTAGE=1.5V
PP1V5_S0_NB_VCCA_3GPLL
MIN_LINE_WIDTH=1.0 mm MIN_NECK_WIDTH=0.2 MM
=PP2V5_S0_NB_VCCA_3GBG
=PP3V3_S0_NB_VCC_HV
VOLTAGE=1.5V
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=1.0 mm
PP1V5_S0_NB_VCCA_HPLL
PP1V5_S0_NB_VCCA_DPLLB
PP1V5_S0_NB_VCCA_DPLLA
NB_CLK_DREFSSCLKIN_P
NB_CLK_DREFSSCLKIN_N
NB_CLK_DREFCLKIN_N
CRT_VSYNC_R
=PP2V5_S0_NB_VCCSYNC
=PP1V5_S0_NB_VCCAUX
TP_LVDS_A_CLK_N
TRUE
TP_LVDS_A_CLK_P
TRUE
LVDS_A_CLK_P
NB_CLK_DREFCLKIN_P
TP_NB_VCCA_DPLLB
TRUE
TRUE
TP_CRT_DDC_DATA
CRT_HSYNC_R
TRUE
TP_CRT_DDC_CLK
CRT_DDC_CLK
TP_LVDS_VREFL
TRUE
TP_LVDS_B_DATA_P<0>
TRUE
TP_LVDS_B_DATA_N<2>
TRUE
TP_LVDS_B_DATA_N<1>
TRUE
TP_LVDS_B_DATA_P<2>
TRUE
LVDS_A_CLK_N
LVDS_B_CLK_P
TP_LVDS_B_DATA_P<1>
TRUE
LVDS_B_DATA_P<1>
LVDS_B_DATA_P<0>
TP_LVDS_DDC_CLK
TRUE
TP_LVDS_CLKCTLB
TRUE
TP_LVDS_BKLTEN
TRUE
TP_LVDS_VDDEN
TRUE
TP_GND_NB_VSSA_LVDS
TRUE
TP_LVDS_IBG
TRUE
LVDS_BKLTEN LVDS_VDDEN
LVDS_IBG
GND_NB_VSSA_LVDS
TP_LVDS_VREFH
TRUE
=PP2V5_S0_NB_VCCA_LVDS
LVDS_B_DATA_P<2>
LVDS_A_DATA_P<1>
TP_LVDS_A_DATA_P<1>
TRUE
TP_LVDS_A_DATA_N<0>
TRUE
TP_LVDS_A_DATA_N<2>
TRUE
TP_LVDS_A_DATA_N<1>
TRUE
TP_LVDS_A_DATA_P<0>
TRUE
TP_LVDS_A_DATA_P<2>
TRUE
TP_LVDS_B_DATA_N<0>
TRUE
LVDS_B_CLK_N
LVDS_A_DATA_N<0>
LVDS_A_DATA_N<1> LVDS_A_DATA_N<2>
LVDS_B_DATA_N<0>
LVDS_A_DATA_P<2>
LVDS_B_DATA_N<2>
LVDS_B_DATA_N<1>
LVDS_VREFH
LVDS_A_DATA_P<0>
TP_LVDS_B_CLK_N
TRUE
TP_LVDS_B_CLK_P
TRUE
LVDS_VREFL
=PP1V5_S0_NB_VCCD_LVDS
TP_LVDS_DDC_DATA
TRUE
TP_LVDS_BKLTCTL
TRUE
TP_SDVO_CTRLCLK
TRUE
TP_SDVO_CTRLDATA
TRUE
=PP2V5_S0_NB_VCC_TXLVDS
LVDS_BKLTCTL LVDS_CLKCTLA
LVDS_DDC_CLK
TP_NB_VCCA_DPLLA
TRUE
=PP1V5_S0_NB_3GPLL
PP1V5_S0_NB_3GPLL_F
VOLTAGE=1.5V MIN_LINE_WIDTH=1.0 mm MIN_NECK_WIDTH=0.2 MM
=PP1V5_S0_NB_3GPLL
TP_LVDS_CLKCTLA
TRUE
GND_NB_VSSA_CRTDAC
CRT_DDC_DATA
SDVO_CTRLDATA
GND_NB_VSSA_TVBG
SDVO_CTRLCLK
PP2V5_S0_NB_VCCA_CRTDAC
CRT_RED_L
CRT_RED
CRT_IREF
CRT_GREEN_L
CRT_GREEN
CRT_BLUE_L
CRT_BLUE
=PPVCORE_S0_NB
=PPVCORE_S0_NB
16
17
19
19
14 14
17
14
17
17
16
13
19
19
16
16
3
3
17
17
17
17
17
17
13
13
13
13
13
13
13
5 5
3
3
17
3
13
13
17
17
17
3
3
17
17
17
14
14
14
13
17
3
13
14
13
13
13
13
13
13
5
5
13
13
17
17
13
13
13
13
13
13
13
13
13
13
13
13
13
17
17
13
13
13
3
3
17
13
14
17
14
17
13
13
13
13
13
13
13
3
3
www.Vinafix.vn
Preliminary
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
PCIe Backward Interop. Mode
VCC Select
Reversal
DMI Lane
High = Reversed
Low = Normal
High = 1.5V
Low = 1.05V
Internal pull-down
Internal pull-down
Internal pull-down
945 External Design Spec says reserved
High = Both active
Low = Only SDVO or PCIe x1
ODT
FSB Dynamic
RESERVED
Low = Disabled
High = Enabled
RESERVED
Internal pull-up
RESERVED
00 = Partial Clock Gating Disable
01 = XOR Mode Enabled
10 = All-Z Mode Enabled 11 = Normal Operation
Internal pull-up
Low = Reversed
RESERVED
CPU Strap
RESERVED
PCIE Graphics
High = Normal
Low = RESERVED
High = DMIx4
Low = DMIx2
NB_CFG<20>
NB_CFG<19>
NB_CFG<9>
NB_CFG<8>
NB_CFG<18>
NB_CFG<17>
NB_CFG<6>
NB_CFG<16>
NB_CFG<15>
NB_CFG<5>
NB_CFG<14>
NB_CFG<13:12>
RESERVED
NB_CFG<3>
NB_CFG<4>
Lane Reversal
PROBABLY NOT NEEDED
PROBABLY NOT NEEDED
DMI x2 Select
Internal pull-up
RESERVED
NB_CFG<7>
High = Mobile CPU
NB_CFG<10>
NB_CFG<11>
RESERVED
RESERVED
Internal pull-up
Internal pull-ups
2
1
R2075
402
5%
2.2K
1/16W MF-LF
NBCFG_DMI_X2
2
1
R2085
2.2K
5% 1/16W MF-LF 402
NBCFG_DYN_ODT_DISABLE
2
1
R2058
402
1/16W
5%
2.2K
NBCFG_VCC_1V5
MF-LF
2
1
R2059
402
MF-LF
1/16W
5%
2.2K
NBCFG_DMI_REVERSE
2
1
R2060
NBCFG_SDVO_AND_PCIE
402
MF-LF
1/16W
5%
2.2K
2
1
R2077
402
MF-LF
1/16W
5%
2.2K
NO STUFF
2
1
R2079
402
MF-LF
1/16W
5%
2.2K
NBCFG_PEG_REVERSE
20 97
H
051-7039
NB Config Straps
SYNC_MASTER=M50_HENRY
SYNC_DATE=08/04/2006
NB_CFG<9>
NB_CFG<7>
NB_CFG<5>
NB_CFG<16>
NB_CFG<20>
NB_CFG<19>
NB_CFG<18>
=PP3V3_S0_NB
=PP3V3_S0_NB
=PP3V3_S0_NB
20
20
20
14
14
14
14
14
14
14
14
14
14
3
3
3
www.Vinafix.vn
Preliminary
IO
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IO
IO
IO
IO
IN
IO
DDACK*
SATARBIASN SATARBIASP
SATA_CLKN
SATA_CLKP
SATA_2TXP
SATA_2TXN
SATA_2RXN
SATA_2RXP
SATA_0TXP
SATA_0TXN
SATA_0RXP
SATA_0RXN
SATALED*
ACZ_SDOUT
ACZ_SDIN1 ACZ_SDIN2
ACZ_SDIN0
ACZ_SYNC
ACZ_BIT_CLK
LAN_TXD2
LAN_TXD0
LAN_TXD1
LAN_RXD1 LAN_RXD2
LAN_RSTSYNC
LAN_RXD0
LAN_CLK
EE_SHCLK
EE_CS
INTVRMEN
INTRUDER*
RTCRST*
RTCX2
RTCX1
THRMTRIP*
STPCLK*
NMI
SMI*
RCIN*
INTR
INIT*
INIT3_3V*
IGNNE*
GPIO49/CPUPWRGD
FERR*
TP1/DPRSTP*
TP2/DPSLP*
A20M*
CPUSPL*
A20GATE
LFRAME*
LDRQ1*/GPIO23
LDRQ0*
LAD3
LAD2
LAD0 LAD1
EE_DOUT
EE_DIN
ACZ_RST*
DIOR*
IDEIRQ
DIOW*
IORDY
DDREQ
DD0
DD1
DD3
DD2
DD5
DD4
DD6
DD7
DD8
DD11
DD9
DD10
DD12
DD13 DD14
DD15
DA0
DA1 DA2
DCS3*
DCS1*
AC-97/
AZALIA
RTC
LPC
LAN
CPU
IDE
SATA
(1 OF 6)
OUT
OUT
OUT
IN
OUT
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
OUT
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
NOTE: EE_CS HAS INTERNAL PD, ONLY ENABLED WHEN LAN_RST#=L
(INT PU)
(INT PU)
(WEAK INT PD)
NOTE: R2108=56 IN CV.
BOM CONSOLIDATION
CHANGED TO 54.9 FOR
NOTE: R2110=56 IN CV.
NOTE: PULLED UP PER INTEL
NOTE: LDRQ<0-1># HAVE INTERNAL 20K PU
INTEL CONFIRMS OK TO LEAVE PINS AS NC
- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED
INTO RESET STATE TO SAVE PWR.
NOTE: POR IS SMC WILL PUT LAN INT’F
NOTE: KEYBOARD CONTROLLER RESET CPU
NOTE: RISING-EDGE TRIGGERED AT CPU
BOM CONSOLIDATION
< 2 IN OF SB
LAYOUT NOTE: R2107 TO BE
CHANGED TO 54.9 FOR
LAYOUT NOTE: R2108 TO BE
< 2 IN OF R2107 W/O STUB
(DSTROBE)
20K PD
20K PD
20K PD
(STOP)
(HSTROBE)
NOTE: DD<7> HAS INTERNAL 11.5K PD
NOTE: ENABLE INTERNAL 1.05V SUSPEND REG
INTERNAL 20K PD ONLY ENABLED IN S3COLD
INTERNAL 20K PD
NONE
- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR
INTERNAL 20K PD ENABLED WHEN
INTERNAL 20K PD
INTERNAL 20K PD ENABLED DURING RESET AND WHEN
- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED
- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR
- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED
- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR
AC ’07
INTERNAL 20K PD
INTERNAL 20K PD ENABLED WHEN
ACZ_SDIN[0-2]
ACZ_RST#
ACZ_BIT_CLK
ACZ_SYNC
ACZ_SDOUT
INTEL HIGH DEFINITION AUDIO
NOTE: LAD<0-3> HAVE INTERNAL 20K PU
NOTE: DDREQ HAS INTERNAL 11.5K PD
LAYOUT NOTE: PLACE R2101 & R2194 WHERE ACCESSIBLE
NOTE: ALL IDE PINS HAVE INTERNAL 33-OHM SERIES R’S
(WEAK INT PU)
21
R2100
402
5%
0
MF-LF 1/16W
NOSTUFF
21
R2101
MF-LF
1/16W
5%
2.2K
402
NOSTUFF
21
R2195
1/16W
402
39
5%
MF-LF
21
R2198
39
21
R2197
39
21
R2196
39
2
1
R2199
MF-LF
1/16W
5%
10K
402
AH25
AF24
AF26
AH22
AF23
AG10
AH10
AF18
AE1
AF1
AH6
AG6
AE7
AF7
AH2
AG2
AE3
AF3
AB2
AB1
AA3
AG23
AH24
AB3
AA5
AC3
V7
V6
U7
T5
V4
U5
U3
V3
Y6
AC4
AB5
AA6
AG16
W4
Y5
AF25
AG21 AF22
AG22
AH16
AG24
AG26
Y1
Y2
W3
W1
AH15
AF15
AE15
AF16
AF12
AE12
AC12
AD12
AC13
AD14
AF13
AG13
AC15
AH14
AH13
AF14
AC14
AB13
AE14
AB15
AD16
AE16
AF17
AE17
AH17
AG27
R6
T4
T1
T3
T2
R5
U1
AH28
AE22
U2100
OMIT
ICH7-M
SB
BGA
2
1
R2194
MF-LF
1/16W
5%
10K
402
2
1
R2105
MF-LF
1/16W
1%
402
332K
21
R2107
402
1%
1/16W
MF-LF
24.9
2
1
R2108
54.9
1%
1/16W
MF-LF
402
21
R2110
1%
54.9
402
1/16W
MF-LF
SB: 1 OF 4
SYNC_DATE=08/04/2006SYNC_MASTER=M50_DOUG
051-7039
9721
H
IDE_PDD<3>
IDE_PDD<2>
TP_SB_XOR_V3
TP_SB_XOR_W3
TP_SB_XOR_T5
TP_SB_XOR_V4
TP_SB_XOR_U5
TP_SB_XOR_U3
PP3V3_S5_SB_RTC
ACZ_RST_L
ACZ_BITCLK
SB_RTC_RST_L
SB_RTC_X2
LPC_FRAME_L
TP_SB_GPIO23
TP_SB_DRQ0_L
LPC_AD<3>
LPC_AD<2>
LPC_AD<1>
LPC_AD<0>
=PP3V3_S0_SB_GPIO
=PP3V3_S0_SB_GPIO
IDE_PDD<6>
ACZ_SDATAOUT
PM_THRMTRIP_L
=PP1V05_S0_SB_CPU_IO
SMC_RCIN_L
ACZ_SYNC
IDE_PDCS1_L
IDE_PDCS3_L
IDE_PDA<2>
IDE_PDA<1>
IDE_PDA<0>
IDE_PDD<15>
IDE_PDD<14>
IDE_PDD<13>
IDE_PDD<12>
IDE_PDD<10>
IDE_PDD<9>
IDE_PDD<11>
IDE_PDD<8>
IDE_PDD<7>
IDE_PDD<4>
IDE_PDD<5>
IDE_PDD<1>
IDE_PDD<0>
IDE_PDDREQ
IDE_PDIORDY
IDE_PDIOW_L
IDE_IRQ14
IDE_PDIOR_L
SB_ACZ_RST_L
TP_CPU_CPUSLP_L
CPU_A20M_L
CPU_DPSLP_L
CPU_DPRSTP_L
CPU_PWRGD
CPU_IGNNE_L
FWH_INIT_L
CPU_INIT_L
CPU_INTR
CPU_SMI_L
CPU_NMI
CPU_STPCLK_L
CPU_THERMTRIP_R
SB_RTC_X1
SB_SM_INTRUDER_L
SB_ACZ_BITCLK
SB_ACZ_SYNC
ACZ_SDATAIN<0>
TP_SB_ACZ_SDIN2
TP_SB_ACZ_SDIN1
SB_ACZ_SDATAOUT
TP_SB_SATALED_L
SATA_A_D2R_N SATA_A_D2R_P
SATA_A_R2D_C_N
SATA_A_R2D_C_P
SATA_C_D2R_N
SATA_C_R2D_C_N SATA_C_R2D_C_P
SB_CLK100M_SATA_P
SB_CLK100M_SATA_N
SATA_RBIAS_P
SATA_RBIAS_N
IDE_PDDACK_L
SATA_C_D2R_P
CPU_RCIN_L
SB_A20GATE
CPU_FERR_L
=PP1V05_S0_SB_CPU_IO
SB_INTVRMEN
TP_SB_XOR_W1
TP_SB_XOR_Y1
TP_SB_XOR_Y2
TP_SB_XOR_U7
TP_SB_XOR_V6
TP_SB_XOR_V7
67
67
67
67
67
27
27 25
25
26
60
60
60
60
60
23
23
59
24
75
60
24
25
58
58
58
58
58
21
21
14
21
38
38
38
7
59
34
34
21
38
38
24
68
68
26
26
5
5
5
5
5
3
3
38
68
7
3
58 68
38
38
38
38
38
38
38
38
38
38
5
38
38
38
38
38
38
38
38
5
38
38
5
7
7
5
7
7
5
7
7
7
7
7
26
26
68
59
38
38
38
38
38
38
38
5
5
38
38
38
38
7
3
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