Analog Devices OP196GS, OP196HRU, OP196GP Datasheet

REV. C

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

a

Micropower, Rail-to-Rail Input and Output

Operational Amplifiers

OP196/OP296/OP496

FEATURES
Rail-to-Rail Input and Output Swing
Low Power: 60 ␮A/Amplifier
Gain Bandwidth Product: 450 kHz
Single-Supply Operation: 3 V to 12 V
Low Offset Voltage: 300 ␮V max
High Open-Loop Gain: 500 V/mV
Unity-Gain Stable
No Phase Reversal

APPLICATIONS
Battery Monitoring
Sensor Conditioners
Portable Power Supply Control
Portable Instrumentation

GENERAL DESCRIPTION

The OP196 family of CBCMOS operational amplifiers features
micropower operation and rail-to-rail input and output ranges.

The extremely low power requirements and guaranteed opera­tion from 3 V to 12 V make these amplifiers perfectly suited to
monitor battery usage and to control battery charging. Their
dynamic performance, including 26 nV/√Hz voltage noise
density, recommends them for battery-powered audio applica­tions. Capacitive loads to 200 pF are handled without oscillation.

The OP196/OP296/OP496 are specified over the HOT extended
industrial (–40°C to +125°C) temperature range. 3 V operation
is specified over the 0°C to 125°C temperature range.

The single OP196 and the dual OP296 are available in 8-lead
SO-8 surface mount packages. The dual OP296 is available in
8-lead PDIP. The quad OP496 is available in 14-lead plastic
DIP and narrow SO-14 surface-mount packages.

8-Lead Narrow-Body SO

1

2

3

4

8

7

6

5

OP196

OUT A

V+

NULL

NC

NULL

–IN A

+IN A

V–

NC = NO CONNECT

PIN CONFIGURATIONS

8-Lead Narrow-Body SO

1

2

3

4

8

7

6

5

OP296

OUT A

–IN A

+IN A

V–

OUT B

–IN B

+IN B

V+

8-Lead Plastic DIP

1

2

3

4

8

7

6

5

OP296

OUT B

–IN B

+IN B

V+

OUT A

–IN A

+IN A

V–

14-Lead Plastic DIP

1

2

3

4

5

6

7

14

13

12

11

10

9

8

OP496

OUT D

–IN D

+IN D

V–

+IN C

–IN C

OUT C

OUT A

–IN A

+IN A

V+

+IN B

–IN B

OUT B

14-Lead Narrow-Body SO

1

2

3

4

5

6

7

14

13

12

11

10

9

8

OP496

OUT D

–IN D

+IN D

V–

+IN C

–IN C

OUT C

OUT A

–IN A

+IN A

V+

+IN B

–IN B

OUT B

8-Lead TSSOP

OP296

OUT A

–IN A
+IN A

V–

OUT B
–IN B
+IN B

V+

8

1

4

5

14-Lead TSSOP

(RU Suffix)

OP496

OUT A

–IN A
+IN A

V+

OUT B

–IN B

+IN B

OUT D
–IN D
+IN D
V–

OUT C

+IN C
–IN C

14

1

7

8

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

OP196/OP296/OP496–SPECIFICATIONS

ELECTRICAL SPECIFICATIONS

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage V

OS

OP196G, OP296G, OP496G 35 300 µV
–40°C ≤ T

A

≤ +125°C 650 µV
OP296H, OP496H 800 µV
–40°C ≤ T

A

≤ +125°C 1.2 mV

Input Bias Current I

B

–40°C ≤ TA ≤ +125°C ±10 ±50 nA

Input Offset Current I

OS

±1.5 ±8nA

–40°C ≤ T

A

≤ +125°C ±20 nA

Input Voltage Range V

CM

05.0V

Common-Mode Rejection Ratio CMRR 0 V ≤ VCM ≤ 5.0 V,

–40°C ≤ T

A

≤ +125°C65 dB

Large Signal Voltage Gain A

VO

RL = 100 kΩ,

0.30 V ≤ V

OUT

≤ 4.7 V,

–40°C ≤ T

A

≤ +125°C 150 200 V/mV

Long-Term Offset Voltage V

OS

G Grade, Note 1 550 µV
H Grade, Note 1 1 mV

Offset Voltage Drift ∆V

OS

/∆T G Grade, Note 2 1.5 µV/°C

H Grade, Note 2 2 µV/°C

OUTPUT CHARACTERISTICS

Output Voltage Swing High V

OH

IL = –100 µA 4.85 4.92 V
I

L

= 1 mA 4.30 4.56 V

I

L

= 2 mA 4.1 V

Output Voltage Swing Low V

OL

IL = –1 mA 36 70 mV
I

L

= –1 mA 350 550 mV

I

L

= –2 mA 750 mV

Output Current I

OUT

±4mA

POWER SUPPLY

Power Supply Rejection Ratio PSRR ±2.5 V ≤ VS ≤ ±6 V,

–40°C ≤ T

A

≤ +125°C85 dB

Supply Current per Amplifier I

SY

V

OUT

= 2.5 V, RL =

∞

60 µA

–40°C ≤ TA ≤ +125°C4580µA

DYNAMIC PERFORMANCE

Slew Rate SR RL = 100 kΩ 0.3 V/µs
Gain Bandwidth Product GBP 350 kHz
Phase Margin ø

m

47 Degrees

NOISE PERFORMANCE

Voltage Noise en p-p 0.1 Hz to 10 Hz 0.8 µV p-p
Voltage Noise Density e

n

f = 1 kHz 26 nV/√Hz

Current Noise Density i

n

f = 1 kHz 0.19 pA/√Hz

NOTES

1

Long-term offset voltage is guaranteed by a 1,000 hour life test performed on three independent lots at 12 5°C, with an LTPD of 1.3.

2

Offset voltage drift is the average of the –40°C to +25°C delta and the +25°C to +125°C delta.

Specifications subject to change without notice.

–2–

(@ VS = 5.0 V, VCM = 2.5 V, TA = 25ⴗC, unless otherwise noted.)

REV. C

ELECTRICAL SPECIFICATIONS

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage V

OS

OP196G, OP296G, OP496G 35 300 µV
0°C ≤ T

A

≤ 125°C 650 µV
OP296H, OP496H 800 µV
0°C ≤ T

A

≤ 125°C 1.2 mV

Input Bias Current I

B

±10 ±50 nA

Input Offset Current I

OS

±1 ± 8nA

Input Voltage Range V

CM

0 3.0 V

Common-Mode Rejection Ratio CMRR 0 V ≤ VCM ≤ 3.0 V,

0°C ≤ T

A

≤ 125°C60 dB

Large Signal Voltage Gain A

VO

RL = 100 kΩ 80 200 V/mV

Long-Term Offset Voltage V

OS

G Grade, Note 1 550 µV
H Grade, Note 1 1 mV

Offset Voltage Drift ∆V

OS

/∆T G Grade, Note 2 1.5 µV/°C

H Grade, Note 2 2 µV/°C

OUTPUT CHARACTERISTICS

Output Voltage Swing High V

OH

IL = 100 µA 2.85 V

Output Voltage Swing Low V

OL

IL = –100 µA70mV

POWER SUPPLY

Supply Current per Amplifier I

SY

V

OUT

= 1.5 V, RL =

∞

40 60 µA

0°C ≤ TA ≤ 125°C80µA

DYNAMIC PERFORMANCE

Slew Rate SR RL = 100 kΩ 0.25 V/µs
Gain Bandwidth Product GBP 350 kHz
Phase Margin ø

m

45 Degrees

NOISE PERFORMANCE

Voltage Noise en p-p 0.1 Hz to 10 Hz 0.8 µV p-p
Voltage Noise Density e

n

f = 1 kHz 26 nV/√Hz

Current Noise Density i

n

f = 1 kHz 0.19 pA/√Hz

NOTES

1

Long-term offset voltage is guaranteed by a 1,000 hour life test performed on three independent lots at 12 5°C, with an LTPD of 1.3.

2

Offset voltage drift is the average of the 0°C to 25°C delta and the 25°C to 125°C delta.

Specifications subject to change without notice.

OP196/OP296/OP496

REV. C

–3–

(@ VS = 3.0 V, VCM = 1.5 V, TA = 25ⴗC, unless otherwise noted.)

OP196/OP296/OP496

REV. C

–4–

ELECTRICAL SPECIFICATIONS

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage V

OS

OP196G, OP296G, OP496G 35 300 µV
0°C ≤ T

A

≤ 125°C 650 µV
OP296H, OP496H 800 µV
0°C ≤ T

A

≤ 125°C 1.2 mV

Input Bias Current I

B

–40°C ≤ TA ≤ +125°C ±10 ±50 nA

Input Offset Current I

OS

±1 ± 8nA

–40°C ≤ T

A

≤ +125°C ±15 nA

Input Voltage Range V

CM

012V

Common-Mode Rejection Ratio CMRR 0 V ≤ VCM ≤ 12 V,

–40°C ≤ T

A

≤ +125°C65 dB

Large Signal Voltage Gain A

VO

RL = 100 kΩ 300 1000 V/mV

Long-Term Offset Voltage V

OS

G Grade, Note 1 550 µV
H Grade, Note 1 1 mV

Offset Voltage Drift ∆V

OS

/∆T G Grade, Note 2 1.5 µV/°C

H Grade, Note 2 2 µV/°C

OUTPUT CHARACTERISTICS

Output Voltage Swing High V

OH

IL = 100 µA 11.85 V
I

L

= 1 mA 11.30 V

Output Voltage Swing Low V

OL

IL = –1 mA 70 mV
I

L

= –1 mA 550 mV

Output Current I

OUT

±4mA

POWER SUPPLY

Supply Current per Amplifier I

SY

V

OUT

= 6 V, RL =

∞

60 µA

–40°C ≤ T

A

≤ +125°C80µA

Supply Voltage Range V

S

312V

DYNAMIC PERFORMANCE

Slew Rate SR RL = 100 kΩ 0.3 V/µs
Gain Bandwidth Product GBP 450 kHz
Phase Margin ø

m

50 Degrees

NOISE PERFORMANCE

Voltage Noise en p-p 0.1 Hz to 10 Hz 0.8 µV p-p
Voltage Noise Density e

n

f = 1 kHz 26 nV/√Hz

Current Noise Density i

n

f = 1 kHz 0.19 pA/√Hz

NOTES

1

Long-term offset voltage is guaranteed by a 1,000 hour life test performed on three independent lots at 12 5°C, with an LTPD of 1.3.

2

Offset voltage drift is the average of the –40°C to +25°C delta and the +25°C to +125°C delta.

Specifications subject to change without notice.

(@ VS = 12.0 V, VCM = 6 V, TA = 25ⴗC, unless otherwise noted.)

OP196/OP296/OP496

REV. C

–5–

ABSOLUTE MAXIMUM RATINGS

1

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V

Input Voltage

2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V

Differential Input Voltage

2

. . . . . . . . . . . . . . . . . . . . . . . . 15 V

Output Short Circuit Duration . . . . . . . . . . . . . . . . . Indefinite

Storage Temperature Range

P, S, RU Package . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Operating Temperature Range

OP196G, OP296G, OP496G, H . . . . . . . – 40°C to +125°C

Junction Temperature Range

P, S, RU Package . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300°C

Package Type ␪

JA

3

␪

JC

Unit

8-Lead Plastic DIP 103 43 °C/W
8-Lead SOIC 158 43 °C/W
8-Lead TSSOP 240 43 °C/W
14-Lead Plastic DIP 83 39 °C/W
14-Lead SOIC 120 36 °C/W
14-Lead TSSOP 180 35 °C/W

NOTES

1

Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.

2

For supply voltages less than 15 V, the absolute maximum input voltage is
equal to the supply voltage.

3

θJA is specified for the worst case conditions, i.e., θJA is specified for device in

socket for P-DIP package; θJA is specified for device soldered in circuit board
for SOIC and TSSOP packages.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the OP196/OP296/OP496 feature proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high-energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of functionalit y.

WARNING!

ESD SENSITIVE DEVICE

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

OP196GS –40°C to +125°C 8-Lead SOIC SO-8
OP296GP* –40°C to +125°C 8-Lead Plastic DIP N-8

OP296GS –40°C to +125°C 8-Lead SOIC SO-8
OP296HRU –40°C to +125°C 8-Lead TSSOP RU-8

OP496GP* –40°C to +125°C 14-Lead Plastic DIP N-14
OP496GS –40°C to +125°C 14-Lead SOIC SO-14
OP496HRU –40°C to +125°C 14-Lead TSSOP RU-14

*

Not for new design, obsolete April 2002.

OP196/OP296/OP496–Typical Performance Characteristics

REV. C–6–

INPUT OFFSET VOLTAGE – ␮V

200

150

100

50

0

250

–250 250–200

QUANTITY – Amplifiers

–150 –100 –50 0 50 100 150 200

VS = 3V
T

A

= 25ⴗC

COUNT = 400

TPC 1. Input Offset Voltage Distribution

200

150

100

50

0

250

–250 250–200

QUANTITY – Amplifiers

–150 –100 –50 0 50 100 150 200

VS = 5V
T

A

= 25ⴗC

COUNT = 400

INPUT OFFSET VOLTAGE – ␮V

TPC 2. Input Offset Voltage Distribution

INPUT OFFSET VOLTAGE – ␮V

200

150

100

50

0

250

–250 250–200

QUANTITY – Amplifiers

–150 –100 –50 0 50 100 150 200

VS = 12V
T

A

= 25ⴗC

COUNT = 400

TPC 3. Input Offset Voltage Distribution

INPUT OFFSET DRIFT, TCVOS – ␮V/ⴗC

20

15

10

5

0

25

–4.0 1.0–3.5

QUANTITY – Amplifiers

–3.0 –2.5 –2.0 –1.5 –1.0 –0.5 0 0.5

VS = 5V
V

CM

= 2.5V

T

A

= –40ⴗC TO ⴙ125ⴗC

TPC 4. Input Offset Voltage Distribution (TCVOS)

INPUT OFFSET DRIFT, TCVOS – ␮V/ⴗC

20

15

10

5

0

25

–4.0 1.0–3.5

QUANTITY – Amplifiers

–3.0 –2.5 –2.0 –1.5 –1.0 –0.5 0 0.5

VS = 12V
V

CM

= 6V

T

A

= –40ⴗC TO ⴙ125ⴗC

1.5

TPC 5. Input Offset Voltage Distribution (TCVOS)

TEMPERATURE – ⴗC

INPUT OFFSET VOLTAGE – ␮V

600

400

–400

–75 150–50 –25 0 25 50 75 100 125

200

0

–200

3V VS 12V

V

CM

=

V

S

2

TPC 6. Input Offset Voltage vs. Temperature

OP196/OP296/OP496

REV. C

–7–

TEMPERATURE – ⴗC

INPUT BAIS CURRENT – nA

25

20

0

–75 150–50 –25 0 25 50 75 100 125

15

10

5

VS = 5V
V

CM

= 2.5V

TPC 7. Input Bias Current vs. Temperature

SUPPLY VOLTAGE – V

16

4

2123

INPUT BIAS CURRENT – nA

5

12

8

14

TPC 8. Input Bias Current vs. Supply Voltage

COMMON-MODE VOLTAGE – V

40

0

–40

–2.5 2.5–2.0

INPUT BIAS CURRENT – nA

–1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0

30

20

–20

–30

10

–10

VS = ⴞ2.5V
T

A

= 25ⴗC

TPC 9. Input Bias Current vs. Common-Mode Voltage

LOAD CURRENT – mA

1000

100

1

0.001 100.01

OUTPUT VOLTAGE – mV

0.1 1

10

SOURCE

SINK

VS = ⴞ1.5V

TPC 10. Output Voltage to Supply Rail vs. Load Current

LOAD CURRENT – mA

1000

100

1

0.001 100.01

OUTPUT VOLTAGE – mV

0.1 1

10

SOURCE

SINK

VS = ⴞ2.5V

TPC 11. Output Voltage to Supply Rail vs. Load Current

LOAD CURRENT – mA

1000

100

1

0.001 100.01

OUTPUT VOLTAGE – mV

0.1 1

10

SOURCE

SINK

VS = ⴞ6V

TPC 12. Output Voltage to Supply Rail vs. Load Current

FREQUENCY – Hz

90

80

–10

10 1M100

OPEN-LOOP GAIN – dB

1k 10k 100k

70

60

50

40

30

20

10

0

225

PHASE SHIFT – ⴗC

0

45

90

135

180

VS = ⴞ2.5V
T

A

= –40ⴗC

GAIN

PHASE

TPC 16. Open-Loop Gain and Phase vs. Frequency
(No Load)

FREQUENCY – Hz

90

80

–10

10 1M100

OPEN-LOOP GAIN – dB

1k 10k 100k

70

60

50

40

30

20

10

0

225

PHASE SHIFT – ⴗC

0

45

90

135

180

VS = ⴞ2.5V
T

A

= 125ⴗC

PHASE

GAIN

TPC 17. Open-Loop Gain and Phase vs. Frequency
(No Load)

TEMPERATURE – ⴗC

950

800

200

–75 150–50

OPEN-LOOP GAIN – V/mV

–25 0 25 50 75 100 125

650

500

350

VS = 5V

0.3V

<

VO < 4.7V

R

L

= 100k⍀

TPC 18. Open-Loop Gain vs. Temperature

TEMPERATURE – ⴗC

4.95

4.70

3.7
–75 150–50

V

OH

OUTPUT VOLTAGE – V

–25 0 25 50 75 100 125

4.45

4.2

3.85

IL = 100␮A

IL = 1mA

IL = 2mA

VS = 5V

TPC 13. Output Voltage Swing vs. Temperature

TEMPERATURE – ⴗC

0.80

0.60

–75 150–50

V

OL

OUTPUT VOLTAGE – V

–25 0 25 50 75 100 125

0.50

0.30

0.10

IL = –100␮A

IL = –1mA

VS = 5V

TPC 14. Output Voltage Swing vs. Temperature

FREQUENCY – Hz

90

80

–10

10 1M100

OPEN-LOOP GAIN – dB

1k 10k 100k

70

60

50

40

30

20

10

0

225

PHASE SHIFT – ⴗC

0

45

90

135

180

VS = ⴞ2.5V
T

A

= 25ⴗC

PHASE

GAIN

TPC 15. Open-Loop Gain and Phase vs. Frequency
(No Load)

OP196/OP296/OP496

REV. C

–8–

OP196/OP296/OP496

REV. C

–9–

LOAD – k⍀

500

100

400

300

200

600

0

150 1100 50 10 2

OPEN-LOOP GAIN – V/mV

VS = 5V

T

A

= 25ⴗC

TPC 19. Open-Loop Gain vs. Resistive Load

FREQUENCY – Hz

70

60

–30

10 1M100

CLOSED-LOOP GAIN – dB

1k 10k 100k

50

40

30

20

10

0

–10

–20

VS = ⴞ2.5V
R

L

= 10k⍀

T

A

= 25ⴗC

TPC 20. Closed-Loop Gain vs. Frequency

FREQUENCY – Hz

1000

500

0

100 1M1k

OUTPUT IMPEDANCE – ⍀

10k 100k

900

800

700

600

400

300

200

100

ACL = 10

ACL = 1

VS = ⴞ2.5V
T

A

= 25ⴗC

TPC 21. Output Impedance vs. Frequency

FREQUENCY – Hz

CMRR – dB

140

–40

100 10M1k 10k 100k 1M

120

100

80

60

40

20

0

–20

VS = ⴞ2.5V
T

A

= 25ⴗC

ALL CHANNELS

160

TPC 22. CMRR vs. Frequency

PSRR – dB

FREQUENCY – Hz

160

140

–40

10 10M100 1k 10k 1M100k

120

100

80

60

40

20

0

–20

VS = 5V
T

A

= 25ⴗC

+PSRR

–PSRR

TPC 23. PSRR vs. Frequency

FREQUENCY – Hz

6

5

0

1k 1M10k

MAXIMUM OUTPUT SWING – V

100k

4

2

3

1

VS = ⴞ2.5V
V

IN

= 5V p-p

A

V

= 1

R

L

= 100k⍀

TPC 24. Maximum Output Swing vs. Frequency

TEMPERATURE – ⴗC

90

50

20

–75 150–50

I

SY

/A MPLIFIER – ␮A

–40 –25 0 25 50 8575 100 125

80

70

40

30

60

VS = 12V

VS = 3V

VS = 5V

TPC 25. Supply Current/Amplifier vs. Temperature

SUPPLY VOLTAGE – V

55

50

35

1133

I

SY

/A MPLIFIER – ␮A

5791112

45

40

TA = 25ⴗC

TPC 26. Supply Current/Amplifier vs. Supply Voltage

FREQUENCY – Hz

80

70

0

11k10 100

60

50

40

30

20

10

VOLTAGE NOISE DENSITY – nV/ Hz

VS = ⴞ2.5V
T

A

= 25ⴗC

V

CM

= 0V

TPC 27. Voltage Noise Density vs. Frequency

FREQUENCY – Hz

0.6

0.5

0

11k10

CURRENT NOISE DENSITY – pA/ Hz

100

0.4

0.3

0.2

0.1

VS = ⴞ2.5V
T

A

= 25ⴗC

V

CM

= 0V

TPC 28. Input Bias Current Noise Density vs. Frequency

SETTLING TIME – ␮s

10

–10

0305

INPUT STEP – V

10 15 20 25

8

2

–4

–6

–8

6

4

0

–2

ⴙOUTPUT SWING

– OUTPUT SWING

VS = ⴞ6V

T

A

= 25ⴗC

TO 0.1%

TPC 29. Settling Time to 0.1% vs. Step Size

10

0%

100

90

1s

2mV

VS = ⴞ2.5V
A

V

= 10k

e

n

= 0.8␮V p-p

TPC 30. 0.1 Hz to 10 Hz Noise

OP196/OP296/OP496

REV. C–10–

OP196/OP296/OP496

REV. C

–11–

1x

1x

2x

2x

Q8

Q7

Q6

Q5

R4A

R4B

I2

1x1x

Q4

Q3

2x2x

Q2

Q1

R3A

R3B

Q9

I3

Q13

Q11

D3

Q12

QC1

Q10

QC2

Q15

CC1

Q14

R2

R1

I1 R6

CF1

D4

Q17

D5

Q18

R5

R7

QL1

Q16

CF2

D6

Q19

2x 1x

I4

CC2

D7

1

*

5

*

Q20

1.5x

1x

D10

R9

D8

Q21

R8

D9

Q22

Q23

I5

OUT

+IN

–IN

V

EE

V

CC

*

OP196 ONLY

TPC 36. Simplified Schematic

10

0%

100

90

2␮s

20mV

VS = 2.5V
A

V

= 1

R

L

= 10k⍀

C

L

= 100pF

T

A

= 25ⴗC

100mV

0V

TPC 31. Small Signal Transient Response

10

0%

100

90

VS = ⴞ2.5V
A

V

= 1

R

L

= 100k⍀

C

L

= 100pF

TA = 25ⴗC

2␮s

20mV

100mV

0V

TPC 32. Small Signal Transient Response

10

0%

100

90

1V

VS = ⴞ2.5V
R

L

= 10k⍀

10␮s

TPC 33. Large Signal Transient Response

10

0%

100

90

1V

VS = ⴞ2.5V
R

L

= 100k⍀

10␮s

TPC 34. Large Signal Transient Response

CH A: 40.0␮V FS 5.00␮V/DIV

MKR: 36.8␮V/ Hz

0Hz

10Hz

MKR: 1.00Hz BW: 145mHz

TPC 35. 1/f Noise Corner, VS = ±5 V, AV = 1,000

OP196/OP296/OP496

REV. C

–12–

APPLICATIONS INFORMATION
Functional Description

The OP196 family of operational amplifiers is comprised of single­supply, micropower, rail-to-rail input and output amplifiers. Input
offset voltage (V

OS

) is only 300 µV maximum, while the output
will deliver ±5 mA to a load. Supply current is only 50 µA, while
bandwidth is over 450 kHz and slew rate is 0.3 V/µs. TPC 36 is
a simplified schematic of the OP196—it displays the novel cir­cuit design techniques used to achieve this performance.

Input Overvoltage Protection

The OPx96 family of op amps uses a composite PNP/NPN
input stage. Transistor Q1 in Figure 36 has a collector-base
voltage of 0 V if +IN = V

EE

. If +IN then exceeds VEE, the junc­tion will be forward biased and large diode currents will flow,
which may damage the device. The same situation applies to
+IN on the base of transistor Q5 being driven above V

CC

. There­fore, the inverting and noninverting inputs must not be driven
above or below either supply rail unless the input current is
limited.

Figure 1 shows the input characteristics for the OPx96 family.
This photograph was generated with the power supply pins
connected to ground and a curve tracer’s collector output drive
connected to the input. As shown in the figure, when the input
voltage exceeds either supply by more than 0.6 V, internal
pn-junctions energize and permit current flow from the inputs
to the supplies. If the current is not limited, the amplifier may
be damaged. To prevent damage, the input current should be
limited to no more than 5 mA.

10

0%

100

90

8

6

4

2

0

–2

–4

–6

–8

–1.5 –1 –0.5 0 0.5 1 1.5

INPUT VOLTAGE – V

INPUT CURRENT – mA

Figure 1. Input Overvoltage I-V Characteristics of the
OPx96 Family

Output Phase Reversal

Some other operational amplifiers designed for single-supply
operation exhibit an output voltage phase reversal when their
inputs are driven beyond their useful common-mode range.
Typically for single-supply bipolar op amps, the negative supply
determines the lower limit of their common-mode range. With
these common-mode limited devices, external clamping diodes
are required to prevent input signal excursions from exceeding
the device’s negative supply rail (i.e., GND) and triggering
output phase reversal.

The OPx96 family of op amps is free from output phase reversal
effects due to its novel input structure. Figure 2 illustrates the
performance of the OPx96 op amps when the input is driven
beyond the supply rails. As previously mentioned, amplifier
input current must be limited if the inputs are driven beyond

the supply rails. In the circuit of Figure 2, the source ampli­tude is ±15 V, while the supply voltage is only ±5 V. In this
case, a 2 kΩ source resistor limits the input current to 5 mA.

10

0%

100

90

VS = 5V
A

V

= 1

5V

1ms

5V

0

0

V

IN

V

OUT

VOLTAGE – 5V/DIV

TIME – 1ns/ DIV

Figure 2. Output Voltage Phase Reversal Behavior

Input Offset Voltage Nulling

The OP196 provides two offset adjust terminals that can be
used to null the amplifier’s internal V

OS

. In general, operational

amplifier terminals should never be used to adjust system offset
voltages. A 100 kΩ potentiometer, connected as shown in Fig­ure 3, is recommended to null the OP196’s offset voltage. Offset
nulling does not adversely affect TCV

OS

performance, providing

that the trimming potentiometer temperature coefficient does
not exceed ±100 ppm/°C.

6

7

2

3

V–

V+

OP196

100k⍀

4

1

5

Figure 3. Offset Nulling Circuit

Driving Capacitive Loads

OP196 family amplifiers are unconditionally stable with capaci­tive loads less than 170 pF. When driving large capacitive loads
in unity-gain configurations, an in-the-loop compensation
technique is recommended, as illustrated in Figure 4.

OP296

C

F

V

IN

R

G

R

F

R

X

C

L

V

OUT

RX = WHERE RO = OPEN-LOOP OUTPUT RESISTANCE

R

O RG

R

F

CF = I + ( ) ( ) CL R

O

I

|A

CL

|

RF + R

G

R

F

Figure 4. In-the-Loop Compensation Technique for
Driving Capacitive Loads

OP196/OP296/OP496

REV. C

–13–

A Micropower False-Ground Generator

Some single supply circuits work best when inputs are biased
above ground, typically at 1/2 of the supply voltage. In these
cases, a false-ground can be created by using a voltage divider
buffered by an amplifier. One such circuit is shown in Figure 5.

This circuit will generate a false-ground reference at 1/2 of the
supply voltage, while drawing only about 55 µA from a 5 V
supply. The circuit includes compensation to allow for a 1 µF
bypass capacitor at the false-ground output. The benefit of a
large capacitor is that not only does the false-ground present a
very low dc resistance to the load, but its ac impedance is low as well.

6

2

3

10k⍀

OP196

100⍀

4

5V OR 12V

0.022␮F

1␮F

240k⍀

240k⍀

1␮F

2.5V OR 6V

7

Figure 5. A Micropower False-Ground Generator

Single-Supply Half-Wave and Full-Wave Rectifiers

An OP296, configured as a voltage follower operating from a
single supply, can be used as a simple half-wave rectifier in low
frequency (<400 Hz) applications. A full-wave rectifier can be
configured with a pair of OP296s as illustrated in Figure 6.

A1

8

1

3

4

5V

1/2
OP296

2k⍀

2

A2

5

6

2Vp-p

<500Hz

7

1/2
OP296

R1

100k⍀

R2

100k⍀

V

OUT

A
FULL-WAVE
RECTIFIED
OUTPUT

V

OUT

B
HALF-WAVE
RECTIFIED
OUTPUT

10

0%

100

90

500mV1V

500µs

500mV

f = 500Hz

INPUT

V

OUT

B

(HALF-WAVE

OUTPUT)

V

OUT

A

(FULL-WAVE

OUTPUT)

Figure 6. Single-Supply Half-Wave and Full-Wave
Rectifiers Using an OP296

The circuit works as follows: When the input signal is above
0 V, the output of amplifier A1 follows the input signal. Since
the noninverting input of amplifier A2 is connected to A1’s
output, op amp loop control forces A2’s inverting input to the
same potential. The result is that both terminals of R1 are at the

same potential and no current flows in R1. Since there is no
current flow in R1, the same condition must exist in R2; thus,
the output of the circuit tracks the input signal. When the input
signal is below 0 V, the output voltage of A1 is forced to 0 V.
This condition now forces A2 to operate as an inverting voltage
follower because the noninverting terminal of A2 is also at 0 V.
The output voltage of V

OUT

A is then a full-wave rectified
version of the input signal. A resistor in series with A1’s
noninverting input protects the ESD diodes when the input
signal goes below ground.

Square Wave Oscillator

The oscillator circuit in Figure 7 demonstrates how a rail-to-rail
output swing can reduce the effects of power supply variations
on the oscillator’s frequency. This feature is especially valuable
in battery powered applications, where voltage regulation may
not be available. The output frequency remains stable as the
supply voltage changes because the RC charging current, which
is derived from the rail-to-rail output, is proportional to the
supply voltage. Since the Schmitt trigger threshold level is also
proportional to supply voltage, the frequency remains relatively
independent of supply voltage. For a supply voltage change
from 9 V to 5 V, the output frequency only changes about 4 Hz.
The slew rate of the amplifier limits the oscillation frequency to
a maximum of about 200 Hz at a supply voltage of 5 V.

59k⍀

1/2
OP296/
OP496

100k⍀

100k⍀

FREQ OUT

f

OSC

= < 200Hz @ V+ = 5V

1

RC

C

V+

R

2

3

4

8

1

Figure 7. Square Wave Oscillator Has Stable Frequency
Regardless of Supply Voltage Changes

A 3 V Low Dropout, Linear Voltage Regulator

Figure 8 shows a simple 3 V voltage regulator design. The regu­lator can deliver 50 mA load current while allowing a 0.2 V
dropout voltage. The OP296’s rail-to-rail output swing easily
drives the MJE350 pass transistor without requiring special
drive circuitry. With no load, its output can swing to less than
the pass transistor’s base-emitter voltage, turning the device
nearly off. At full load, and at low emitter-collector voltages, the
transistor beta tends to decrease. The additional base current is
easily handled by the OP296 output.

The AD589 provides a 1.235 V reference voltage for the regula­tor. The OP296, operating with a noninverting gain of 2.43,
drives the base of the MJE350 to produce an output voltage of

3.0 V. Since the MJE350 operates in an inverting (common­emitter) mode, the output feedback is applied to the OP296’s
noninverting input.

OP196/OP296/OP496

REV. C

–14–

1/2

OP296

4

1

3

2

8

1000pF

44.2k⍀
1%

30.9k⍀
1%

AD589

43k⍀

1.235V

MJE 350

100␮F

V

IN

5V TO 3.2V

I

L

< 50mA

V

O

Figure 8. 3 V Low Dropout Voltage Regulator

Figure 9 shows the regulator’s recovery characteristics when its
output underwent a 20 mA to 50 mA step current change.

10

0%

100

90

2V

50µs

10mV

50mA

30mA

OUTPUT

STEP
CURRENT
CONTROL

WAVEFORM

Figure 9. Output Step Load Current Recovery

Buffering a DAC Output

Multichannel TrimDACs® such as the AD8801/AD8803, are
widely used for digital nulling and similar applications. These
DACs have rail-to-rail output swings, with a nominal output
resistance of 5 kΩ. If a lower output impedance is required, an
OP296 amplifier can be added. Two examples are shown in
Figure 10. One amplifier of an OP296 is used as a simple buffer
to reduce the output resistance of DAC A. The OP296 provides
rail-to-rail output drive while operating down to a 3 V supply
and requiring only 50 µA of supply current.

5V

OP296

SIMPLE BUFFER
0V TO 5V
+4.983V
+1.1mV

R1
100k⍀

SUMMER CIRCUIT
WITH FINE TRIM
ADJUSTMENT

DIGITAL INTERFACING
OMITTED FOR CLARITY

AD8801/
AD8803

V

H

V

L

V

DD

V

REFH

GND

V

REFL

V

H

V

L

V

H

V

L

Figure 10. Buffering a TrimDAC OutputTPC

The next two DACs, B and C, sum their outputs into the other
OP296 amplifier. In this circuit DAC C provides the coarse
output voltage setting and DAC B is used for fine adjustment.
The insertion of R1 in series with DAC B attenuates its contri­bution to the voltage sum node at the DAC C output.

A High-Side Current Monitor

In the design of power supply control circuits, a great deal of
design effort is focused on ensuring a pass transistor’s long-term
reliability over a wide range of load current conditions. As a result,
monitoring and limiting device power dissipation is of prime
importance in these designs. The circuit illustrated in Figure 11
is an example of a 5 V, single-supply high-side current monitor
that can be incorporated into the design of a voltage regulator
with fold-back current limiting or a high current power supply
with crowbar protection. This design uses an OP296’s rail-to­rail input voltage range to sense the voltage drop across a 0.1 Ω
current shunt. A p-channel MOSFET is used as the feedback
element in the circuit to convert the op amp’s differential input
voltage into a current. This current is then applied to R2 to gen­erate a voltage that is a linear representation of the load current.
The transfer equation for the current monitor is given by:

Monitor Output = R2 ×

R

SENSE

R1











× I

L

For the element values shown, the Monitor Output’s transfer
characteristic is 2.5 V/A.

8

1

234

1/2

OP296

5V

5V

S

G

D

M1

3N163

MONITOR

OUTPUT

R2

2.49k⍀

R1

100⍀

R

SENSE

0.1⍀

I

L

5V

Figure 11. A High-Side Load Current Monitor

A Single-Supply RTD Amplifier

The circuit in Figure 12 uses three op amps on the OP496 to
produce a bridge driver for an RTD amplifier while operating
from a single 5 V supply. The circuit takes advantage of the
OP496’s wide output swing to generate a bridge excitation
voltage of 3.9 V. An AD589 provides a 1.235 V reference for
the bridge current. Op amp A1 drives the bridge to maintain

1.235 V across the parallel combination of the 6.19 kΩ and

2.55 MΩ resistors, which generates a 200 µA current source.
This current divides evenly and flows through both halves of
the bridge. Thus, 100 µA flows through the RTD to generate
an output voltage which is proportional to its resistance. For
improved accuracy, a 3-wire RTD is recommended to balance
the line resistance in both 100 Ω legs of the bridge.

TrimDAC is a registered trademark of Analog Devices Inc.

OP196/OP296/OP496

REV. C

–15–

* OP496 SPICE Macro-model REV. C, 5/95
* ARG / ADSC
*
* Copyright 1995 by Analog Devices, Inc.
*
* Refer to “README.DOC” file for License Statement.
* Use of this model indicates your acceptance of the
* terms and provisions in the License Statement.
*
* Node assignments
* Noninverting input
* Inverting input
* Positive supply
* Negative supply
* Output
*
*

.SUBCKT OP496 1 2 99 50 49

*
* INPUT STAGE

*

IREF 21 50 1U
QB1 21 21 99 99 QP 1
QB2 22 21 99 99 QP 1
QB34 219999QP1.5
QB4 22 22 50 50 QN 2
QB5 11 22 50 50 QN 3
Q154750QN2
Q264850QN2
Q344750QN1
Q444850QN1
Q5501799QP2
Q6503899QP2
EOS 3 2 POLY(1) (17,98) 35U 1
Q7991950QN2
Q8993 1050QN2
Q9 12 11 9 99 QP 2
Q10 13 11 10 99 QP 2
Q11 11 11 9 99 QP 1
Q12 11 11 10 99 QP 1
R1 99 5 50K
R2 99 6 50K
R3 12 50 50K
R4 13 50 50K
IOS 1 2 0.75N
C10 5 6 3.183P
C11 12 13 3.183P

CIN 1 2 1P

*
* GAIN STAGE
*

EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5
G1 98 15 POLY(2) (6,5) (13,12) 0 10U 10U
R10 15 98 251.641MEG
CC 15 49 8P
D1 15 99 DX
D2 50 15 DX

*
* COMMON-MODE STAGE
*

ECM 16 98 POLY(2) (1,98) (2,98) 0 0.5 0.5
R11 16 17 1MEG
R12 17 98 10

*
* OUTPUT STAGE
*

ISY 99 50 20U
EIN 35 50 POLY(1) (15,98) 1.42735 1
Q24 37 35 36 50 QN 1
QD4 37 37 38 99 QP 1
Q27 40 37 38 99 QP 1
R5 36 39 150K
R6 99 38 45K
Q26 39 42 50 50 QN 3
QD5 40 40 39 50 QN 1
Q28 41 40 44 50 QN 1
QL1 37 41 99 99 QP 1
R7 99 41 10.7K
I4 99 43 2U
QD7 42 42 50 50 QN 2
QD6 43 43 42 50 QN 2
Q29 47 43 44 50 QN 1
Q30 44 45 50 50 QN 1.5
QD10 45 46 50 50 QN 1
R9 45 46 175
Q31 46 47 48 99 QP 1
QD8 47 47 48 99 QP 1
QD9 48 48 51 99 QP 5
R8 99 51 2.9K
I5 99 46 1U
Q32 49 48 99 99 QP 10
Q33 49 44 50 50 QN 4
.MODEL DX D()
.MODEL QN NPN(BF=120VAF=100)
.MODEL QP PNP(BF=80 VAF=60)
.ENDS

V

OUT

5V

A3

A2

A1

100k⍀

0.1␮F

1/4
OP496

1/4
OP496

100k⍀

GAIN = 259

200⍀

10-TURNS

26.7k⍀

26.7k⍀

100⍀

6.17k⍀

37.4k⍀

5V

100⍀

RTD

2.55M⍀

AD589

1/4
OP496

NOTE:
ALL RESISTORS 1% OR BETTER

392⍀

392⍀

20k⍀

Figure 12. A Single-Supply RTD Amplifier

Amplifiers A2 and A3 are configured in a two op amp instru­mentation amplifier configuration. For ease of measurement,
the IA resistors are chosen to produce a gain of 259, so that
each 1°C increase in temperature results in a 10 mV increase in
the output voltage. To reduce measurement noise, the band­width of the amplifier is limited. A 0.1 µF capacitor, connected
in parallel with the 100 kΩ resistor on amplifier A3, creates a
pole at 16 Hz.

OP196/OP296/OP496

REV. C

–16–

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

C00312–0–1/02(C)

PRINTED IN U.S.A.

8-Lead Plastic DIP

(N-8)

8

14

5

0.430 (10.92)

0.348 (8.84)

0.280 (7.11)

0.240 (6.10)

PIN 1

SEATING
PLANE

0.022 (0.558)

0.014 (0.356)

0.060 (1.52)

0.015 (0.38)

0.210 (5.33)
MAX

0.130
(3.30)
MIN

0.070 (1.77)

0.045 (1.15)

0.100
(2.54)

BSC

0.160 (4.06)

0.115 (2.93)

0.325 (8.25)

0.300 (7.62)

0.015 (0.381)

0.008 (0.204)

0.195 (4.95)

0.115 (2.93)

8-Lead Narrow Body SOIC

(SO-8)

0.1968 (5.00)

0.1890 (4.80)

8

5

41

0.2440 (6.20)

0.2284 (5.80)

PIN 1

0.1574 (4.00)

0.1497 (3.80)

0.0688 (1.75)

0.0532 (1.35)

SEATING

PLANE

0.0098 (0.25)

0.0040 (0.10)

0.0192 (0.49)

0.0138 (0.35)

0.0500
(1.27)

BSC

0.0098 (0.25)

0.0075 (0.19)

0.0500 (1.27)

0.0160 (0.41)

8°
0°

0.0196 (0.50)

0.0099 (0.25)

x 45°

8-Lead TSSOP

(RU-8)

8

5

4

1

0.122 (3.10)

0.114 (2.90)

0.256 (6.50)

0.246 (6.25)

0.177 (4.50)

0.169 (4.30)

PIN 1

0.0256 (0.65)
BSC

SEATING

PLANE

0.006 (0.15)

0.002 (0.05)

0.0118 (0.30)

0.0075 (0.19)

0.0433
(1.10)
MAX

0.0079 (0.20)

0.0035 (0.090)

0.028 (0.70)

0.020 (0.50)

8°
0°

14-Lead Plastic DIP

(N-14)

14

17

8

0.795 (20.19)

0.725 (18.42)

0.280 (7.11)

0.240 (6.10)

PIN 1

SEATING
PLANE

0.022 (0.558)

0.014 (0.356)

0.060 (1.52)

0.015 (0.38)

0.210 (5.33)
MAX

0.130
(3.30)
MIN

0.070 (1.77)

0.045 (1.15)

0.100
(2.54)

BSC

0.160 (4.06)

0.115 (2.93)

0.325 (8.25)

0.300 (7.62)

0.015 (0.381)

0.008 (0.204)

0.195 (4.95)

0.115 (2.93)

14-Lead Narrow-Body SOIC

(SO-14)

14 8

71

0.3444 (8.75)

0.3367 (8.55)

0.2440 (6.20)

0.2284 (5.80)

0.1574 (4.00)

0.1497 (3.80)

PIN 1

SEATING

PLANE

0.0098 (0.25)

0.0040 (0.10)

0.0192 (0.49)

0.0138 (0.35)

0.0688 (1.75)

0.0532 (1.35)

0.0500
(1.27)

BSC

0.0099 (0.25)

0.0075 (0.19)

0.0500 (1.27)

0.0160 (0.41)

8°
0°

0.0196 (0.50)

0.0099 (0.25)

x 45°

14-Lead TSSOP

(RU-14)

14 8

7

1

0.201 (5.10)

0.193 (4.90)

0.256 (6.50)

0.246 (6.25)

0.177 (4.50)

0.169 (4.30)

PIN 1

SEATING

PLANE

0.006 (0.15)

0.002 (0.05)

0.0118 (0.30)

0.0075 (0.19)

0.0256
(0.65)

BSC

0.0433
(1.10)
MAX

0.0079 (0.20)

0.0035 (0.090)

0.028 (0.70)

0.020 (0.50)

8°
0°

Revision History

Location Page

Data Sheet changed from REV. B to REV. C.

Edits to TYPICAL PERFORMANCE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10