Analog Devices OP191 291 491 c Datasheet

Micropower Single-Supply

1
2

5
6
7

3
4

14
13

10

9
8

12
11

OP491

OUTD
–IND
+IND
–V
+INC
–INC
OUTC

OUTA

–INA
+INA

+V
+INB
–INB

OUTB

Rail-to-Rail Input/Output Op Amps

OP191/OP291/OP491

FEATURES
Single-Supply Operation: 2.7 V to 12 V
Wide Input Voltage Range
Rail-to-Rail Output Swing
Low Supply Current: 300 ␮A/Amp
Wide Bandwidth: 3 MHz
Slew Rate: 0.5 V/␮s
Low Offset Voltage: 700 ␮V
No Phase Reversal

APPLICATIONS
Industrial Process Control
Battery-Powered Instrumentation
Power Supply Control and Protection
Telecommunications
Remote Sensors
Low Voltage Strain Gage Amplifiers
DAC Output Amplifiers

GENERAL DESCRIPTION

The OP191, OP291, and OP491 are single, dual, and quad
micropower, single-supply, 3 MHz bandwidth amplifiers fea­turing rail-to-rail inputs and outputs. All are guaranteed to
operate from a +3 V single supply as well as ± 5 V dual supplies.

Fabricated on Analog Devices’ CBCMOS process, the OP191
family has a unique input stage that allows the input voltage to
safely extend 10 V beyond either supply without any phase inver­sion or latch-up. The output voltage swings to within millivolts
of the supplies and continues to sink or source current all the
way to the supplies.

Applications for these amplifiers include portable telecommu­nications equipment, power supply control and protection, and
interface for transducers with wide output ranges. Sensors
requiring a rail-to-rail input amplifier include Hall effect, piezo
electric, and resistive transducers.

The ability to swing rail-to-rail at both the input and output
enables designers to build multistage filters in single-supply
systems and to maintain high signal-to-noise ratios.

The OP191/OP291/OP491 are specified over the extended
industrial –40∞C to +125∞C temperature range. The OP191 single
and OP291 dual amplifiers are available in 8-lead plastic SOIC
surface-mount packages. The OP491 quad is available in 14-lead
PDIP, narrow 14-lead SOIC, and 14-lead TSSOP packages.

PIN CONFIGURATIONS

8-Lead Narrow-Body

SOIC

NC

–INA

+INA

1

2

OP191

3

–V

4

8

7

6

5

NC

+V

OUTA

NC

14-Lead Narrow-Body

SOIC

OP491

14

OUTD

13

–IND

12

+IND

11

–V

10

+INC

9

–INC

8

OUTC

OUTA

–INA

+INA

+V

+INB

–INB

OUTB

1

2

3

4

5

6

7

14-Lead TSSOP

8-Lead Narrow-Body

SOIC

OUTA

–INA

+INA

1

2

OP291

3

–V

4

8

7

6

5

+V

OUTB

–INB

+INB

14-Lead PDIP

OUTA

–INA

+INA

+V

+INB

–INB

OUTB

1

2

3

4

5

6

7

OP491

14

13

12

11

10

9

8

OUTD

–IND

+IND

–V

+INC

–INC

OUTC

REV. C

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

OP191/OP291/OP491–SPECIFICATIONS

ELECTRICAL SPECIFICATIONS

(@ VS = 3.0 V, VCM = 0.1 V, VO = 1.4 V, TA = 25ⴗC, unless otherwise noted.)

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage OP191G V

OP291G/OP491G V

Input Bias Current I

OS

OS

B

–40∞C £ T

–40∞C £ T

£ +125∞C1mV

A

£ +125∞C 1.25 mV

A

80 500 mV

80 700 mV

30 65 nA

–40∞C £ TA £ +125∞C95nA

Input Offset Current I

OS

–40∞C £ T

£ +125∞C22nA

A

0.1 11 nA

Input Voltage Range 0 3 V
Common-Mode Rejection Ratio CMRR V

Large Signal Voltage Gain A

Offset Voltage Drift DV
Bias Current Drift DI

VO

/DT 1.1 mV/∞C

OS

/DT 100 pA/∞C

B

= 0 V to 2.9 V 70 90 dB

CM

–40∞C £ T

£ +125∞C6587 dB

A

RL = 10 kW, VO = 0.3 V to 2.7 V 25 70 V/mV
–40∞C £ T

£ +125∞C50V/mV

A

Offset Current Drift DIOS/DT20pA/∞C

OUTPUT CHARACTERISTICS

Output Voltage High V

OH

RL = 100 kW to GND 2.95 2.99 V
–40∞C to +125∞C2.902.98 V

= 2 kW to GND 2.8 2.9 V

R

L

–40∞C to +125∞C2.702.80 V

Output Voltage Low V

OL

RL = 100 kW to V+ 4.5 10 mV
–40∞C to +125∞C35mV

= 2 kW to V+ 40 75 mV

R

L

–40∞C to +125∞C 130 mV

Short-Circuit Limit I

SC

Sink/Source ± 8.75 ± 13.50 mA
–40∞C to +125∞C ± 6.0 ± 10.5 mA

Open-Loop Impedance Z

OUT

f = 1 MHz, AV = 1 200 W

POWER SUPPLY

Power Supply Rejection Ratio PSRR VS = 2.7 V to 12 V 80 110 dB

£ +125∞C75110 dB

A

Supply Current/Amplifier I

SY

–40∞C £ T
VO = 0 V 200 350 mA
–40∞C £ TA £ +125∞C 330 480 mA

DYNAMIC PERFORMANCE

Slew Rate +SR RL = 10 kW 0.4 V/ms
Slew Rate –SR R
Full-Power Bandwidth BW
Settling Time t

P

S

= 10 kW 0.4 V/ms

L

1% Distortion 1.2 kHz
To 0.01% 22 ms

Gain Bandwidth Product GBP 3 MHz
Phase Margin q

O

45 Degrees

Channel Separation CS f = 1 kHz, RL = 10 kW 145 dB

NOISE PERFORMANCE

Voltage Noise en p-p 0.1 Hz to 10 Hz 2 mV p-p
Voltage Noise Density e
Current Noise Density i

Specifications subject to change without notice.

n

n

f = 1 kHz 35 nV/÷Hz

0.8 pA/÷Hz

–2–

REV. C

OP191/OP291/OP491

ELECTRICAL SPECIFICATIONS

(@ VS = 5.0 V, VCM = 0.1 V, VO = 1.4 V, TA = 25ⴗC, unless otherwise noted.)

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage OP191 V

OP291/OP491 V

Input Bias Current I

OS

OS

B

–40∞C £ T

–40∞C £ T

£ +125∞C 1.0 mV

A

£ +125∞C 1.25 mV

A

80 500 mV

80 700 mV

30 65 nA

–40∞C £ TA £ +125∞C95nA

Input Offset Current I

OS

–40∞C £ T

£ +125∞C22nA

A

0.1 11 nA

Input Voltage Range 0 5 V
Common-Mode Rejection Ratio CMRR V

Large Signal Voltage Gain A

Offset Voltage Drift DV

VO

/DT –40∞C £ TA £ +125∞C 1.1 mV/∞C

OS

= 0 V to 4.9 V 70 93 dB

CM

–40∞C £ T

£ +125∞C6590 dB

A

RL = 10 kW, VO = 0.3 V to 4.7 V 25 70 V/mV
–40∞C £ T

£ +125∞C50V/mV

A

Bias Current Drift DIB/DT 100 pA/∞C
Offset Current Drift DIOS/DT20pA/∞C

OUTPUT CHARACTERISTICS

Output Voltage High V

OH

RL = 100 kW to GND 4.95 4.99 V
–40∞C to +125∞C 4.90 4.98 V

= 2 kW to GND 4.8 4.85 V

R

L

–40∞C to +125∞C 4.65 4.75 V

Output Voltage Low V

OL

RL = 100 kW to V+ 4.5 10 mV
–40∞C to +125∞C35mV

= 2 kW to V+ 40 75 mV

R

L

–40∞C to +125∞C 155 mV

Short-Circuit Limit I

SC

Sink/Source ± 8.75 ± 13.5 mA
–40∞C to +125∞C ± 6.0 ± 10.5 mA

Open-Loop Impedance Z

OUT

f = 1 MHz, AV = 1 200 W

POWER SUPPLY

Power Supply Rejection Ratio PSRR VS = 2.7 V to 12 V 80 110 dB

£ +125∞C75110 dB

A

Supply Current/Amplifier I

SY

–40∞C £ T
VO = 0 V 220 400 mA
–40∞C £ TA £ +125∞C 350 500 mA

DYNAMIC PERFORMANCE

Slew Rate +SR RL = 10 kW 0.4 V/ms
Slew Rate –SR R
Full-Power Bandwidth BW
Settling Time t

P

S

= 10 kW 0.4 V/ms

L

1% Distortion 1.2 kHz
To 0.01% 22 ms

Gain Bandwidth Product GBP 3 MHz
Phase Margin q

O

45 Degrees

Channel Separation CS f = 1 kHz, RL = 10 kW 145 dB

NOISE PERFORMANCE

Voltage Noise en p-p 0.1 Hz to 10 Hz 2 mV p-p
Voltage Noise Density e
Current Noise Density i

NOTE
+5 V specifications are guaranteed by +3 V and ± 5 V testing.

Specifications subject to change without notice.

n

n

f = 1 kHz 35 nV/÷Hz

0.8 pA/÷Hz

REV. C

–3–

OP191/OP291/OP491

ELECTRICAL SPECIFICATIONS

(@ VO = ⴞ5.0 V, –4.9 V £ VCM £ +4.9 V, TA = 25ⴗC, unless otherwise noted.)

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage OP191 V

OP291/OP491 V

Input Bias Current I

Input Offset Current I

B

OS

OS

OS

–40∞C £ T

–40∞C £ T

–40∞C £ T

–40∞C £ T

£ +125∞C1mV

A

£ +125∞C 1.25 mV

A

£ +125∞C95nA

A

£ +125∞C22nA

A

80 500 mV

80 700 mV

30 65 nA

0.1 11 nA

Input Voltage Range –5 +5 V
Common-Mode Rejection CMR V

Large Signal Voltage Gain A

Offset Voltage Drift DV
Bias Current Drift DI

VO

/DT 1.1 mV/∞C

OS

/DT 100 pA/∞C

B

= ± 5 V 75 100 dB

CM

–40∞C £ T

£ +125∞C6797 dB

A

RL = 10 kW, VO = ± 4.7 V, 25 70
–40∞C £ T

£ +125∞C50V/mV

A

Offset Current Drift DIOS/DT20pA/∞C

OUTPUT CHARACTERISTICS

Output Voltage Swing V

O

RL = 100 kW to GND ± 4.93 ± 4.99 V
–40∞C to +125∞C ± 4.90 ± 4.98 V

= 2 kW to GND ± 4.80 ± 4.95 V

R

Short-Circuit Limit I

SC

L

–40∞C £ T
Sink/Source ± 8.75 ± 16.00 mA

£ +125∞C ± 4.65 ± 4.75 V

A

–40∞C to +125∞C ± 6 ± 13 mA

Open-Loop Impedance Z

OUT

f = 1 MHz, AV = 1 200 W

POWER SUPPLY

Power Supply Rejection Ratio PSRR V

Supply Current/Amplifier I

SY

= ± 5 V 80 110 dB

S

–40∞C £ T

£ +125∞C70100 dB

A

VO = 0 V 260 420 mA
–40∞C £ TA £ +125∞C 390 550 mA

DYNAMIC PERFORMANCE

Slew Rate ± SR R
Full-Power Bandwidth BW
Settling Time t

P

S

=10 kW 0.5 V/ms

L

1% Distortion 1.2 kHz
To 0.01% 22 ms

Gain Bandwidth Product GBP 3 MHz
Phase Margin q

O

45 Degrees

Channel Separation CS f = 1 kHz 145 dB

NOISE PERFORMANCE

Voltage Noise e
Voltage Noise Density e
Current Noise Density i

Specifications subject to change without notice.

p-p 0.1 Hz to 10 Hz 2 mV p-p

n

n

n

f = 1 kHz 35 nV/÷Hz

0.8 pA/÷Hz

INPUT

OUTPUT

5V

100

90

10

0%

5V

VS = ⴞ5V

= 2k⍀

R

L

= +1

A

V

= 20V p-p

V

IN

200␮s

Figure 1. Input and Output with Inputs Overdriven by 5 V

–4–

REV. C

OP191/OP291/OP491

ABSOLUTE MAXIMUM RATINGS

1, 2

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 V

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . GND to V

10 V

S

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

Output Short-Circuit Duration to GND . . . . . . . . . . Indefinite

Storage Temperature Range

N, R, RU Packages . . . . . . . . . . . . . . . . . . –65∞C to +150∞C

Operating Temperature Range

OP191G/OP291G/OP491G . . . . . . . . . . . . –40∞C to +125∞C

Junction Temperature Range

N, R, RU Packages . . . . . . . . . . . . . . . . . . –65∞C to +150∞C

Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300∞C

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

OP191GS –40ⴗC to +125ⴗC 8-Lead SOIC R-8
OP191GS-REEL –40ⴗC to +125ⴗC 8-Lead SOIC R-8
OP191GS-REEL7 –40ⴗC to +125ⴗC 8-Lead SOIC R-8
OP291GS –40ⴗC to +125ⴗC 8-Lead SOIC R-8
OP291GS-REEL –40ⴗC to +125ⴗC 8-Lead SOIC R-8
OP291GS-REEL7 –40ⴗC to +125ⴗC 8-Lead SOIC R-8
OP291GSZ
OP291GSZ-REEL
OP291GSZ-REEL7

*

*

*

–40ⴗC to +125ⴗC 8-Lead SOIC R-8
–40ⴗC to +125ⴗC 8-Lead SOIC R-8

–40ⴗC to +125ⴗC 8-Lead SOIC R-8
OP491GP –40ⴗC to +125ⴗC 14-Lead PDIP N-14
OP491GS –40ⴗC to +125ⴗC 14-Lead SOIC R-14
OP491GS-REEL –40ⴗC to +125ⴗC 14-Lead SOIC R-14
OP491GS-REEL7 –40ⴗC to +125ⴗC 14-Lead SOIC R-14
OP491GSZ
OP491GSZ-REEL
OP491GSZ-REEL7

*

*

*

–40ⴗC to +125ⴗC 14-Lead SOIC R-14

–40ⴗC to +125ⴗC 14-Lead SOIC R-14

–40ⴗC to +125ⴗC 14-Lead SOIC R-14
OP491GRU-REEL –40ⴗC to +125ⴗC 14-Lead TSSOP RU-14
OP491GBC DIE form

*

Z = Pb-free part.

Package Type ␪

3

JA

␪

JC

Unit

8-Lead SOIC (R) 158 43 ∞C/W
14-Lead PDIP (N) 76 33 ∞C/W
14-Lead SOIC (R) 120 36 ∞C/W
14-Lead TSSOP (RU) 180 35 ∞C/W

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

Absolute maximum ratings apply to both DICE and packaged parts, unless

otherwise noted.

3

qJA is specified for the worst-case conditions; i.e., q

for PDIP packages; q
and SOIC packages.

is specified for device soldered in circuit board for TSSOP

JA

is specified for device in socket

JA

[S-Suffix]
[S-Suffix]
[S-Suffix]
[S-Suffix]
[S-Suffix]
[S-Suffix]
[S-Suffix]
[S-Suffix]
[S-Suffix]

[P-Suffix]
[S-Suffix]
[S-Suffix]
[S-Suffix]
[S-Suffix]
[S-Suffix]
[S-Suffix]

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the

WARNING!

OP191/OP291/OP491 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

REV. C

–5–

ESD SENSITIVE DEVICE

OP191/OP291/OP491—Typical Performance Characteristics

INPUT OFFSET VOLTAGE (mV)

12525–40

VCM = 0V

85

TEMPERATURE (ⴗC)

0

–0.02

–0.04

–0.06

–0.08

–0.10

–0.12

–0.14

VCM = 2.9V

VS = 3V

VCM = 0.1V

VCM = 3V

180

VS = 3V

160

= 25ⴗC

T

A

BASED ON

140

1200 OP AMPS

120

100

80

UNITS

60

40

20

0

–0.18

INPUT OFFSET VOLTAGE (mV)

0.14

0.06–0.02–0.10

0.22

TPC 1. OP291 Input Offset Voltage
Distribution, V

40

30

20

10

0

–10

–20

–30

–40

INPUT BIAS CURRENT (nA)

–50

–60

= 3 V

S

VS = 3V

TEMPERATURE (ⴗC)

V

= 3V

CM

V

= 2.9V

CM

V

= 0.1V

CM

V

= 0V

CM

120

100

80

60

UNITS

20

0

INPUT OFFSET VOLTAGE (␮V/ ⴗC)

TPC 2. OP291 Input Offset Voltage
Drift Distribution, VS = 3 V

0

–0.2

VS = 3V

–0.4

–0.6

–0.8

–1.0

–1.2

–1.4

INPUT OFFSET CURRENT (nA)

–1.6

12525–40 85

–1.8

VS = 3V
–40ⴗC < T
BASED ON 600 OP AMPS

1400

VCM = 0.1V

VCM = 2.9V

TEMPERATURE (ⴗC)

VCM = 3V

< +125ⴗC

A

VCM = 0V

85

7

64325

12525–40

TPC 3. Input Offset Voltage vs.
Temperature, V

36

30

VS = 3V
24

18

12

6

0

–6

–12

–18

–24

INPUT BIAS CURRENT (nA)

–30

–36

0.30

0

INPUT COMMON-MODE VOLTAGE (V)

= 3 V

S

2.72.42.11.81.51.20.900.60

3.0

TPC 4. Input Bias Current vs.
Temperature, V

3.00

2.95

2.90

2.85

2.80

OUTPUT VOLTAGE SWING (V)

VS = 3V

2.75
–40

= 3 V

S

+VO @ RL = 100k⍀

+VO @ RL = 2k⍀

25

TEMPERATURE (ⴗC)

TPC 7. Output Voltage Swing vs.
Temperature, VS = 3 V

TPC 5. Input Offset Current vs.
Temperature, VS = 3 V

160

140

120

100

80

60

40

20

OPEN-LOOP GAIN (dB)

0

–20

85

125

–40

100

1k 10k 100k 1M 10M

FREQUENCY (Hz)

VS =3V

= 25ⴗC

T

A

0

45

90

135

180

225

270

TPC 8. Open-Loop Gain and Phase
vs. Frequency, VS = 3 V

TPC 6. Input Bias Current vs. Input
Common-Mode Voltage, VS = 3 V

1200

RL = 100k⍀,

= 2.9V

V

1000

800

600

400

PHASE SHIFT (ⴗC)

OPEN-LOOP GAIN (V/mV)

200

0

CM

RL = 100k⍀,

= 0.1V

V

CM

VS = 3V, VO = 0.3V/2.7V

TEMPERATURE (ⴗC)

85

TPC 9. Open-Loop Gain vs.
Temperature, VS = 3 V

12525–40

–6–

REV. C

OP191/OP291/OP491

50

40

30

20

10

0

–10

–20

–30

CLOSED-LOOP GAIN (dB)

–40

–50

10 100 10M1M100k10k1k

FREQUENCY (Hz)

VS = 3V

= 25ⴗC

T

A

TPC 10. Closed-Loop Gain vs.
Frequency, V

160

140

120

100

80

60

40

PSRR (dB)

20

0

–20

–40

100

1k 10k 100k 1M 10M

= 3 V

S

ⴙPSRR

–PSRR

FREQUENCY (Hz)

ⴞPSRR

= 3V

V

S

= 25ⴗC

T

A

160

140

120

100

80

60

40

CMRR (dB)

20

0

–20

–40

100

1k 10k 100k 1M 10M

FREQUENCY (Hz)

CMRR

=3V

V

S

= 25ⴗC

T

A

TPC 11. CMRR vs. Frequency,
V

= 3 V

S

113

112

111

110

PSRR (dB)

109

108

107

–40

25

TEMPERATURE (ⴗC)

VS = 3V

85

125

90

VS = 3V

89

88

87

CMRR (dB)

86

85

84

–40

25

TEMPERATURE (ⴗC)

85

125

TPC 12. CMRR vs. Temperature,

= 3 V

V

S

1.6
VS = 3V

1.4

1.2

1.0

0.8

0.6

SLEW RATE (V/␮s)

0.4

0.2

0

TEMPERATURE (ⴗC)

ⴙSR

–SR

25–40

85

125

TPC 13. PSRR vs. Frequency,

= 3 V

V

S

0.35

VS = 3V

0.30

0.25

0.20

0.15

0.10

SUPPLY CURRENT/AMPLIFIER (mA)

0.05
–40

25

TEMPERATURE (ⴗC)

85

TPC 16. Supply Current vs.
Temperature, V

= +3 V, +5 V, ±5 V

S

125

TPC 14. PSRR vs. Temperature,
VS = 3 V

2.8

2.6

2.4

2.2

2.0

1.8

1.6

1.4

MAXIMUM OUTPUT SWING (V)

1.2

1.0

0.50.1
FREQUENCY (kHz)

VIN = 2.8V p-p
V

= 3V

S

= 1

A

V

R

= 100k⍀

L

300

250200150100705030101.0

TPC 17. Maximum Output Swing vs.
Frequency, VS = 3 V

TPC 15. Slew Rate vs.
Temperature, VS = 3 V

MKR: 36.2 nV/冪Hz

100

90

10

0%

MKR:

0 Hz
1000 Hz

BW:

2.5kHz

15.0 Hz

TPC 18. Voltage Noise Density,

= +3 V to ±5 V, AVO = 1000

V

S

REV. C

–7–

OP191/OP291/OP491

70

VS = 5V

= 25ⴗC

T

A

60

BASED ON 600
OP AMPS

50

40

UNITS

30

20

10

0

–0.50

INPUT OFFSET VOLTAGE (mV)

0.300.10–0.10–0.30

0.50

TPC 19. OP291 Input Offset Voltage
Distribution, VS = 5 V

40

30

20

10

(nA)

B

I

–10

–20

–30

–40

= 5V

V

S

VCM = 5V

0

V

= 0V

CM

25–40

TEMPERATURE (ⴗC)

+I

B

–I

B

–I

B

+I

B

85

125

TPC 22. Input Bias Current vs.
Temperature, VS = 5 V

120

100

80

60

UNITS

40

20

0

1.0

0

INPUT OFFSET VOLTAGE (␮V/ⴗC)

VS = 5V

C < TA < +125ⴗC

–40
BASED ON 600 OP AMPS

6.05.04.03.02.0

TPC 20. OP291 Input Offset
Voltage Drift Distribution, VS = 5 V

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

INPUT OFFSET CURRENT (nA)

0

–0.2

VCM = 0V

VCM = 5V

25–40

TEMPERATURE (ⴗC)

VS = 5V

85

TPC 23. Input Offset Current vs.
Temperature, VS = 5 V

125

7.0

0.15

0.10

0.05

(mV)

OS

V

–0.05

–0.10

0

–40

VCM = 0V

V

CM

25

TEMPERATURE (ⴗC)

= 5V

85

VS = 5V

125

TPC 21. Input Offset Voltage vs.
Temperature, VS = 5 V

36

30

VS = 5V

24

18

12

6

0

–6

–12

–18

INPUT BIAS CURRENT (nA)

–24

–30

–36

0

COMMON MODE INPUT VOLTAGE (V)

5

4321

TPC 24. Input Bias Current vs.
Common-Mode Input Voltage, VS = 5 V

5.00

4.95

4.90

4.85

= 2k⍀

R

4.80

OUTPUT VOLTAGE SWING (V)

4.75
VS = 5V

4.70

–40

L

25

TEMPERATURE (ⴗC)

RL = 100k⍀

85

TPC 25. Output Voltage Swing vs.
Temperature, VS = 5 V

125

160

140

120

100

80

60

40

20

OPEN-LOOP GAIN (dB)

0

–20

–40

100

1k 10k 100k 1M 10M

FREQUENCY (Hz)

VS = 5V

= 25ⴗC

T

A

0

45

90

135

180

225

270

TPC 26. Open-Loop Gain and Phase
vs. Frequency, V

= 5 V

S

140

120

RL = 100k⍀, VCM = 5V

100

80

60

40

PHASE SHIFT (ⴗC)

OPEN-LOOP GAIN (V/mV)

20

0

–40

RL = 2k⍀, VCM = 5V

RL = 2k⍀, VCM = 0V

RL = 100k⍀, VCM = 0V

25

TEMPERATURE (ⴗC)

TPC 27. Open-Loop Gain vs.
Temperature, V

= 5 V

S

VS = 5V

85

125

–8–

REV. C

OP191/OP291/OP491

50

40

30

20

10

0

–10

–20

–30

CLOSED-LOOP GAIN (dB)

–40

–50

10 100 10M1M100k10k1k

FREQUENCY (Hz)

VS = 5V

= 25ⴗC

T

A

TPC 28. Closed-Loop Gain vs.
Frequency, V

160

140

120

100

80

60

40

PSRR (dB)

20

0

–20

–40

100

= 5 V

S

ⴞPSRR

= 5V

V

S

= 25ⴗC

T

A

+PSRR

–PSRR

1k 10k 100k 1M 10M

FREQUENCY (Hz)

TPC 31. PSRR vs. Frequency,
VS = 5 V

160

140

120

100

80

60

40

CMRR (dB)

20

0

–20

–40

100

1k 10k 100k 1M 10M

FREQUENCY (Hz)

CMRR

= 5V

V

S

= 25ⴗC

T

A

TPC 29. CMRR vs. Frequency,
V

= 5 V

S

0.6

0.5

0.4

+SR

0.3

SR (V/␮s)

0.2

0.1

0
–40

–SR

25

TEMPERATURE (ⴗC)

85

VS = 5V

TPC 32. OP291 Slew Rate vs.
Temperature, VS = 5 V

125

96

VS = 5V

95

94

93

92

91

CMRR (dB)

90

89

88

87

86

–40

25

TEMPERATURE (ⴗC)

85

125

TPC 30. CMRR vs. Temperature,
VS = 5 V

0.50
VS = 5V

0.45

SR (V/␮s)

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

–40

+SR

–SR

25

TEMPERATURE (ⴗC)

85

TPC 33. OP491 Slew Rate vs.
Temperature, VS = 5 V

125

20

18

16

14

+ISC, VS = +3V

12

10

8

6

SHORT-CIRCUIT CURRENT (mA)

4

+ISC, VS = ⴞ5V

–ISC, VS = ⴞ5V

–ISC, VS = +3V

25–40

TEMPERATURE (ⴗC)

85

125

TPC 34. Short-Circuit Current vs.
Temperature, VS = +3 V, +5 V,±5V

80

70

60

50

40

30

VOLTAGE (␮V)

20

10

0

V

= 10V p-p @ 1kHz

IN

0

A

10k⍀

FREQUENCY (Hz)

10k⍀

VS = ⴞ5V

1k⍀

B

200015001000500

TPC 35. Channel Separation,

=±5 V

V

S

V

O

2500

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

MAXIMUM OUTPUT SWING (V)

0.5

0

0.5

0.1
FREQUENCY (kHz)

VIN = 4.8V p-p
VS = 5V

= 1

A

V

= 100k⍀

R

L

4 PARTS

250100 15050 70 20030101.0

TPC 36. Maximum Output Swing
vs. Frequency, VS = 5 V

300

REV. C

–9–

OP191/OP291/OP491

5.00

–5.00

125

–4.85

–4.95

25

–4.90

–40

0

–4.80

–4.75

4.75

4.80

4.85

4.95

4.90

85

OUTPUT VOLTAGE SWING (V)

TEMPERATURE (ⴗC)

V

S

= ⴞ5V

RL = 100k⍀

R

L

= 2k⍀

RL = 100k⍀

RL = 2k⍀

10

9

8

7

6

5

4

3

2

MAXIMUM OUTPUT SWING (V)

1

0

0.5

0.1
FREQUENCY (kHz)

VIN = +9.8V p-p
VS = ⴞ5V
AV = +1
RL = 100k⍀
4 PARTS

(nA)

B

I

–10

–20

–30

–40

–50

50

40

30

20

10

0

–40

VS = ⴞ5V

VCM = +5V

VCM = –5V

25

TEMPERATURE (ⴗC)

85

+I

B

–I

B

–I

B

+I

B

125

0.15

0.10

VCM = –5V

0.05

0

–0.05

INPUT OFFSET VOLTAGE (mV)

–0.10

300

250100 15050 70 20030101.0

–40

VCM = +5V

25

TEMPERATURE (ⴗC)

VS = ⴞ5V

85

125

TPC 37. Maximum Output Swing vs.
Frequency, VS=±5V

1.6
VS = ⴞ5V

1.4

1.2

1.0

0.8

0.6

0.4

0.2

INPUT OFFSET CURRENT (nA)

0

–0.2

25–40

TEMPERATURE (ⴗC)

VCM = –5V

VCM = +5V

85

125

TPC 40. Input Offset Current vs.
Temperature, VS=±5V

70

60

50

40

30

20

10

0

OPEN-LOOP GAIN (dB)

–10

–20

–30

1k

10k 10M1M100k

FREQUENCY (Hz)

VS = ⴞ5V

= 25ⴗC

T

A

0

45

90

135

180

225

270

TPC 38. Input Offset Voltage vs.
Temperature, V

36

VS = ⴞ5V

24

12

0

–12

INPUT BIAS CURRENT (nA)

–24

–36

COMMON-MODE INPUT VOLTAGE (V)

S

–1–2–3–4–5

=±5V

0

TPC 41. Input Bias Current vs.
Common-Mode Voltage, VS=±5V

200

180

160

140

120

100

80

65

40

OPEN-LOOP GAIN (V/mV)

PHASE SHIFT (ⴗC)

25

0
–40

RL = 100k⍀

RL = 2k⍀

25

TEMPERATURE (ⴗC)

85

VS = ⴞ5V

TPC 39. Input Bias Current vs.
Temperature, V

5

4321

= ±5 V

S

TPC 42. Output Voltage Swing vs.
Temperature, VS=±5V

125

50

40

30

20

10

0

–10

–20

–30

CLOSED-LOOP GAIN (dB)

–40

–50

10 100 10M1M100k10k1k

FREQUENCY (Hz)

V

S

T

A

= ⴞ5V
= 25ⴗC

TPC 43. Open-Loop Gain and Phase

vs. Frequency, V

= ±5 V

S

TPC 44. Open-Loop Gain vs.
Temperature, VS=±5V

–10–

TPC 45. Closed-Loop Gain vs.
Frequency, V

=±5V

S

REV. C

OP191/OP291/OP491

160

100

60

–40

1k 10k 100k 1M 10M

80

100

120

140

–20

0

20

40

+PSRR

–PSRR

ⴞPSRR
V

S

= ⴞ5V

T

A

= 25ⴗC

PSRR (dB)

FREQUENCY (Hz)

160

140

120

100

80

60

40

CMRR (dB)

20

0

–20

–40

100

1k 10k 100k 1M 10M

FREQUENCY (Hz)

CMRR

= ⴞ5V

V

S

= 25ⴗC

T

A

TPC 46. CMRR vs. Frequency,
VS=±5V

115

110

105

100

PSRR (dB)

95

90

–40

VS = ⴞ5V

OP291

25

TEMPERATURE (ⴗC)

OP491

85

TPC 49. OP291/OP491 PSRR vs.
Temperature, VS=±5V

125

102

VS = ⴞ5V

101

100

99

98

97

CMRR (dB)

96

95

94

93

92

–40

25

TEMPERATURE (ⴗC)

85

125

TPC 47. CMRR vs. Temperature,
VS=±5V

0.7
VS = ⴞ5V

0.6

0.5

0.4

s)

␮

0.3

SR (V/

0.2

0.1

0

–40

+SR

–SR

25

TEMPERATURE (ⴗC)

85

125

TPC 50. Slew Rate vs. Temperature,
VS=±5V

TPC 48. PSRR vs. Frequency,

=±5V

V

S

1000

900

800

700

600

(⍀)

500

OUT

400

Z

300

200

100

0

100 1k 10M1M100k10k

A

= 10

VCL

FREQUENCY (Hz)

A

VCL

= 100

VS = 3V
TA = 25ⴗC

A

VCL

= 1

TPC 51. Output Impedance vs.
Frequency

100

90

INPUT

OUTPUT

10

0%

TPC 52. Large Signal Transient
Response, V

REV. C

1.00V

500mV

= 3 V

S

2.00␮s

VS = 3V
R

= 200k⍀

L

100mV

OUTPUT

–11–

2.00V

100

90

INPUT

VS = ⴞ5V

10

0%

R
A

2.00␮s

TPC 53. Large Signal Transient
Response, VS = ±5 V

= 200k⍀

L

= +1V/V

V

100mV1.00V

OP191/OP291/OP491

FUNCTIONAL DESCRIPTION

The OP191/OP291/OP491 are single-supply, micropower
amplifiers featuring rail-to-rail inputs and outputs. In order to
achieve wide input and output ranges, these amplifiers employ
unique input and output stages. As the simplified schematic
(Figure 2) shows, the input stage is comprised of two differential
pairs, a PNP pair and an NPN pair. These two stages do not
work in parallel. Instead, only one or the other stage is on for
any given input signal level. The PNP stage (transistors Q1 and
Q2) is required to ensure that the amplifier remains in the linear
region when the input voltage approaches and reaches the
negative rail. On the other hand, the NPN stage (transistors
Q5 and Q6) is needed for input voltages up to and including the
positive rail.

For the majority of the input common-mode range, the PNP
stage is active, as is evidenced by examining the graph of Input
Bias Current vs. Common-Mode Voltage. Notice that the bias
current switches direction at approximately 1.2 V to 1.3 V below
the positive rail. At voltages below this, the bias current flows
out of the OP291, indicating a PNP input stage. Above this
voltage, however, the bias current enters the device, revealing the
NPN stage. The actual mechanism within the amplifier for
switching between the input stages is comprised of the transistors
Q3, Q4, and Q7. As the input common-mode voltage increases,
the emitters of Q1 and Q2 follow that voltage plus a diode drop.
Eventually the emitters of Q1 and Q2 are high enough to turn
on Q3, which diverts the 8 mA of tail current away from the
PNP input stage, turning it off. Instead, the current is mirrored
through Q4 and Q7 to activate the NPN input stage.

Notice that the input stage includes 5 kW series resistors and
differential diodes, a common practice in bipolar amplifiers to
protect the input transistors from large differential voltages.
These diodes turn on whenever the differential voltage

exceeds approximately 0.6 V. In this condition, current flows
between the input pins, limited only by the two 5 kW resistors.
This characteristic is important in circuits where the amplifier
may be operated open-loop, such as a comparator. Evaluate
each circuit carefully to make sure that the increase in current
does not affect the performance.

The output stage of the OP191 family uses a PNP and an NPN
transistor as do most output stages; however, the output tran­sistors, Q32 and Q33, are actually connected with their collec­tors to the output pin to achieve the rail-to-rail output swing. As
the output voltage approaches either the positive or negative
rail, these transistors begin to saturate. Thus, the final limit on
output voltage is the saturation voltage of these transistors,
which is about 50 mV. The output stage does have inherent gain
arising from the collectors and any external load impedance.
Because of this, the open-loop gain of the amplifier is dependent
on the load resistance.

Input Overvoltage Protection

As with any semiconductor device, whenever the condition
exists for the input to exceed either supply voltage, attention
needs to be paid to the input overvoltage characteristic. When
an overvoltage occurs, the amplifier could be damaged depend­ing on the voltage level and the magnitude of the fault current.
Figure 3 shows the characteristics for the OP191 family. This
graph was generated with the power supplies at ground and a
curve tracer connected to the input. As can be seen, when the
input voltage exceeds either supply by more than 0.6 V, internal
PN junctions energize, allowing current to flow from the input
to the supplies. As described above, the OP291/OP491 does
have 5 kW resistors in series with each input, which helps limit
the current. Calculating the slope of the current versus voltage
in the graph confirms the 5 kW resistor.

+IN

5k⍀

Q1 Q2

8␮A

Q4

Q3

5k⍀

–IN

Q5

Q6

Q8

Q9

Q7

Q10

Q11

Q12

Q13 Q15

Figure 2. Simplified Schematic

Q14

Q16

Q17

Q18 Q19

Q20

Q21

Q22

Q25

Q23

Q24

Q27

Q28

Q26

Q29

Q30

Q31

10pF

Q32

Q33

V

OUT

–12–

REV. C

I

IN

2mA

1mA

–5V–10V 10V5V

–1mA

–2mA

V

IN

Figure 3. Input Overvoltage Characteristics

This input current is not inherently damaging to the device as
long as it is limited to 5 mA or less. In the case shown, for an
input of 10 V over the supply, the current is limited to 1.8 mA.
If the voltage is large enough to cause more than 5 mA of current
to flow, then an external series resistor should be added. The size
of this resistor is calculated by dividing the maximum overvoltage
by 5 mA and subtracting the internal 5 kW resistor. For example,
if the input voltage could reach 100 V, the external resistor
should be (100 V/5 mA) – 5 k = 15 kW. This resistance should
be placed in series with either or both inputs if they are subjected
to the overvoltages. For more information on general overvoltage
characteristics of amplifiers, refer to the 1993 System Applications
Guide, available from the Analog Devices Literature Center.

Output Voltage Phase Reversal

Some operational amplifiers designed for single-supply opera­tion exhibit an output voltage phase reversal when their inputs
are driven beyond their useful common-mode range. Typically
for single-supply bipolar op amps, the negative supply deter­mines the lower limit of their common-mode range. With these
devices, external clamping diodes with the anode connected to

OP191/OP291/OP491

ground and the cathode to the inputs prevent input signal excur­sions from exceeding the device’s negative supply (i.e., GND),
preventing a condition that could cause the output voltage to
change phase. JFET input amplifiers may also exhibit phase
reversal, and, if so, a series input resistor is usually required to
prevent it.

The OP191 family is free from reasonable input voltage range
restrictions due to its novel input structure. In fact, the input
signal can exceed the supply voltage by a significant amount
without causing damage to the device. As illustrated in Figure 4,
the OP191 family can safely handle a 20 V p-p input signal on
± 5 V supplies without exhibiting any sign of output voltage
phase reversal or other anomalous behavior. Thus no external
clamping diodes are required.

Overdrive Recovery

The overdrive recovery time of an operational amplifier is the
time required for the output voltage to recover to its linear region
from a saturated condition. This recovery time is important in
applications where the amplifier must recover quickly after a
large transient event, such as a comparator. The circuit shown
in Figure 5 was used to evaluate the OP191 family’s overload
recovery time. The OP191 family takes approximately 8 ms to
recover from positive saturation and approximately 6.5 ms to
recover from negative saturation.

R1

9k⍀

V

IN

10V STEP

10k⍀

V

= ⴞ5V

S

Figure 5. Overdrive Recovery Time Test Circuit

3

1/2

1

OP291

2

R2

R3

10k⍀

V

OUT

20V p-p

REV. C

␮

5␮s

+5V

V

IN

3

OP291

2

–5V

8

1/2

4

V

1

OUT

100

90

(2.5V/DIV)

IN

V

10

0%

TIME (200␮s/DIV)

100

90

(2V/DIV)

OUT

V

10

0%

20mV

TIME (200␮s/DIV)

5

20mV

s

Figure 4. Output Voltage Phase Reversal Behavior

–13–

OP191/OP291/OP491

APPLICATIONS
Single 3 V Supply, Instrumentation Amplifier

The OP291’s low supply current and low voltage operation make
it ideal for battery-powered applications, such as the instrumen­tation amplifier shown in Figure 6. The circuit uses the classic
two op amp instrumentation amplifier topology, with four resistors
to set the gain. The equation is simply that of a noninverting
amplifier as shown in the figure. The two resistors labeled R1
should be closely matched to each other as well as both resistors
labeled R2 to ensure good common-mode rejection performance.
Resistor networks ensure the closest matching as well as matched
drifts for good temperature stability. Capacitor C1 is included
to limit the bandwidth and, therefore, the noise in sensitive
applications. The value of this capacitor should be adjusted
depending on the desired closed-loop bandwidth of the instru­mentation amplifier. The RC combination creates a pole at a
frequency equal to 1/(2p ¥ R1C1). If AC-CMRR is critical,
then a matched capacitor to C1 should be included across the
second resistor labeled R1.

3V

5

8

V

IN

3

1/2

1

OP291

R1 R2 R2

2

V

= (1 + ––– ) V

OUT

R1

IN

R2

OP291

6

1/2

4

R1

C1

100pF

V

7

OUT

Figure 6. Single 3 V Supply Instrumentation Amplifier

Because the OP291 accepts rail-to-rail inputs, the input common­mode range includes both ground and the positive supply of
3V. Furthermore, the rail-to-rail output range ensures the wid­est signal range possible and maximizes the dynamic range of
the system. Also, with its low supply current of 300 mA/device,
this circuit consumes a quiescent current of only 600 mA yet still
exhibits a gain bandwidth of 3 MHz.

A question may arise about other instrumentation amplifier
topologies for single-supply applications. For example, a variation
on this topology adds a fifth resistor between the two inverting
inputs of the op amps for gain setting. While that topology works
well in dual-supply applications, it is inherently inappropriate
for single-supply circuits. The same could be said for the traditional
three op amp instrumentation amplifier. In both cases, the cir­cuits simply cannot work in single-supply situations unless a
false ground between the supplies is created.

Single-Supply RTD Amplifier

The circuit in Figure 7 uses three op amps of the OP491 to
develop a bridge configuration for an RTD amplifier that oper­ates from a single 5 V supply. The circuit takes advantage of the
OP491’s wide output swing range to generate a high bridge
excitation voltage of 3.9 V. In fact, because of the rail-to-rail
output swing, this circuit works with supplies as low as 4.0 V.
Amplifier A1 servos the bridge to create a constant excitation
current in conjunction with the AD589, a 1.235 V precision
reference. The op amp maintains the reference voltage across
the parallel combination of the 6.19 kW and 2.55 MW resistors,
which generates a 200 mA current source. This current splits
evenly and flows through both halves of the bridge. Thus, 100 mA
flows through the RTD to generate an output voltage based on
its resistance. A 3-wire RTD is used to balance the line resis­tance in both 100 W legs of the bridge to improve accuracy.

100⍀

RTD

2.55M⍀

6.19k⍀

AD589

26.7k⍀

200⍀

10 TURNS

26.7k⍀

OP491

37.4k⍀

5V

100⍀

1/4

A1

1/4

OP491

365⍀ 365⍀

100k⍀

ALL RESISTORS 1% OR BETTER

A2

GAIN = 274

OP491

5V

1/4

100k⍀

0.01pF

A3

V

OUT

Figure 7. Single-Supply RTD Amplifier

Amplifiers A2 and A3 are configured in the two op amp IA
discussed above. Their resistors are chosen to produce a gain of
274, such that each 1∞C increase in temperature results in a
10 mV change in the output voltage, for ease of measurement.
A 0.01 mF capacitor is included in parallel with the 100 kW
resistor on amplifier A3 to filter out any unwanted noise from
this high gain circuit. This particular RC combination creates a
pole at 1.6 kHz.

–14–

REV. C

OP191/OP291/OP491

A 2.5 V Reference from a 3 V Supply

In many single-supply applications, the need for a 2.5 V reference
often arises. Many commercially available monolithic 2.5 V
references require a minimum operating supply voltage of 4 V.
The problem is exacerbated when the minimum operating sys­tem supply voltage is 3 V. The circuit illustrated in Figure 8 is
an example of a 2.5 V reference that operates from a single 3 V
supply. The circuit takes advantage of the OP291’s rail-to-rail
input and output voltage ranges to amplify an AD589’s 1.235 V
output to 2.5 V. The OP291’s low TCV

of 1 mV/∞C helps

OS

maintain an output voltage temperature coefficient of less than
200 ppm/∞C. The circuit’s overall temperature coefficient is
dominated by R2 and R3’s temperature coefficient. Lower tem­perature coefficient resistors are recommended. The entire
circuit draws less than 420 mA from a 3 V supply at 25∞C.

3V

17.4k⍀

AD589

R1

R3

100k⍀

3

OP291

2

R2

100k⍀

1/2

3V

8

1

4

R1

5k⍀

2.5V

REF

RESISTORS = 1%, 100ppm/ⴗC
POTENTIOMETER = 10 TURN, 100ppm/ⴗC

Figure 8. A 2.5 V Reference that Operates on a
Single 3 V Supply

5 V Only, 12-Bit DAC Swings Rail-to-Rail

The OP191 family is ideal for use with a CMOS DAC to generate
a digitally controlled voltage with a wide output range. Figure 9
shows the DAC8043 used in conjunction with the AD589 to
generate a voltage output from 0 V to 1.23 V. The DAC is oper­ated in voltage switching mode, where the reference is connected
to the current output, I
the V

pin. This topology is inherently noninverting as opposed

REF

, and the output voltage is taken from

OUT

to the classic current output mode, which is inverting and, there­fore, unsuitable for single supply.

5V

8

V

DD

DAC8043

I

OUT

GND CLK SR1

4765

V

DIGITAL

CONTROL

R

REF

LD

2

FB

1

5V

8

3

1/2

OP291

2

1

4

V

OUT

D

= –––– (5V)

4096

17.8k⍀

1.23V

AD589

R1

3

The OP291 serves two functions. First, it is required to buffer
the high output impedance of the DAC’s V

pin, which is on

REF

the order of 10 kW. The op amp provides a low impedance output
to drive any following circuitry. Second, the op amp amplifies
the output signal to provide a rail-to-rail output swing. In this
particular case, the gain is set to 4.1 to generate a 5.0 V output
when the DAC is at full scale. If other output voltage ranges are
needed, such as 0 V to 4.095 V, the gain can easily be adjusted
by altering the value of the resistors.

A High-Side Current Monitor

In the design of power supply control circuits, a great deal of
design effort is focused on ensuring a pass transistor’s long-term
reliability over a wide range of load current conditions. As a
result, monitoring and limiting device power dissipation is of
prime importance in these designs. The circuit illustrated in
Figure 10 is an example of a 5 V, single-supply, high-side
current monitor that can be incorporated into the design of a
voltage regulator with fold-back current limiting or a high
current power supply with crowbar protection. This design uses
an OP291’s rail-to-rail input voltage range to sense the voltage
drop across a 0.1 W current shunt. A p-channel MOSFET
used as the feedback element in the circuit converts the op
amp’s differential input voltage into a current. This current is
then applied to R2 to generate a voltage that is a linear repre­sentation of the load current. The transfer equation for the
current monitor is given by

Monitor Output = R2

Ê

¥

Á
Ë

R

SENSE

R1

ˆ

I

¥

L

˜
¯

For the element values shown, the monitor output’s transfer
characteristic is 2.5 V/A.

R

MONITOR

OUTPUT

5V

100⍀

3N163

2.49k⍀

M1

R2

SENSE

0.1⍀

R1

S

G

D

I

L

3

1/2

OP291

2

5V

5V

8

1

4

Figure 10. A High-Side Load Current Monitor

232⍀1%32.4k⍀

1%

R2

R3

R4

100k⍀

1%

Figure 9. 5 V Only, 12-Bit DAC Swings Rail-to-Rail

REV. C

–15–

OP191/OP291/OP491

A 3 V, Cold Junction Compensated Thermocouple Amplifier

The OP291’s low supply operation makes it ideal for 3 V battery­powered applications such as the thermocouple amplifier shown
in Figure 11. The K-type thermocouple terminates in an
isothermal block where the junctions’ ambient temperature is
continuously monitored using a simple 1N914 diode. The diode
corrects the thermal EMF generated in the junctions by feeding
a small voltage, scaled by the 1.5 MW and 475 W resistors, to
the op amp.

To calibrate this circuit, immerse the thermocouple measuring
junction in a 0∞C ice bath and adjust the 500 W potentiometer to
0V out. Next, immerse the thermocouple in a 250∞C tempera­ture bath or oven and adjust the scale adjust potentiometer for
an output voltage of 2.50 V. Within this temperature range,
the K-type thermocouple is accurate to within ± 3∞C without
linearization.

1.235V

24.9k⍀
1%

2.1k⍀
1%

10k⍀

24.3k⍀
1%

4.99k⍀

500⍀
10 TURN

ZERO
ADJUST

1%

3.0V

2

OP291

3

SCALE

ADJUST

1.33M⍀ 20k⍀

8

1

0V = 0ⴗC

4

3V = 300ⴗC

V

OUT

ISOTHERMAL

BLOCK

ALUMEL

AL

CR

CHROMEL

K-TYPE
THERMOCOUPLE

40.7␮V/ⴗC

1N914

AD589

7.15k⍀

1.5M⍀
1%

COLD
JUNCTIONS

11.2mV

475⍀

1%

1%

Figure 11. A 3 V, Cold-Junction Compensated
Thermocouple Amplifier

Single-Supply, Direct Access Arrangement for Modems

An important building block in modems is the telephone line
interface. In the circuit shown in Figure 12, a direct access
arrangement is used for transmitting and receiving data from the
telephone line. Amplifier A1 is the receiving amplifier, and
amplifiers A2 and A3 are the transmitters. The fourth amplifier,
A4, generates a pseudo ground halfway between the supply
voltage and ground. This pseudo ground is needed for the
ac-coupled bipolar input signals.

The transmit signal, TXA, is inverted by A2 and then reinverted
by A3 to provide a differential drive to the transformer, where
each amplifier supplies half the drive signal. This is needed
because of the smaller swings associated with a single supply as
opposed to a dual supply. Amplifier A1 provides some gain for
the received signal, and it also removes the transmit signal present
at the transformer from the receive signal. To do this, the drive
signal from A2 is also fed to the noninverting input of A1 to
cancel the transmit signal from the transformer.

390pF

37.4k⍀

20k⍀, 1%

20k⍀, 1%

475⍀, 1%

0.033␮F

5.1V TO 6.2V
ZENER 5

100k⍀

10␮F 0.1␮F

T1

1:1

RXA

TXA

0.1␮F

0.1␮F
20k⍀, 1%

14

0.0047␮F

10

9

750pF

6

5

1

A4

A1

1/4

OP491

3.3k⍀

1/4

OP491

37.4k⍀, 1%

20k⍀ 1%

20k⍀ 1%

1/4

OP491

4

1/4

OP491

11

13

12

A2

8

A3

7

3V OR 5V

2

3

100k⍀

Figure 12. Single-Supply Direct Access Arrangement
for Modems

The OP491’s bandwidth of 3 MHz and rail-to-rail output swings
ensure that it can provide the largest possible drive to the trans­former at the frequency of transmission.

3 V, 50 Hz/60 Hz Active Notch Filter with False Ground

To process ac signals in a single-supply system, it is often best
to use a false-ground biasing scheme. A circuit that uses this
approach is illustrated in Figure 13. In this circuit, a false-ground
circuit biases an active notch filter used to reject 50 Hz/60 Hz
power line interference in portable patient monitoring equip­ment. Notch filters are quite commonly used to reject power
line frequency interference that often obscures low frequency
physiological signals, such as heart rates, blood pressure readings,
EEGs, and EKGs. This notch filter effectively squelches 60 Hz
pickup at a filter Q of 0.75. Substituting 3.16 kW resistors for
the 2.67 kW resistors in the twin-T section (R1 through R5)
configures the active filter to reject 50 Hz interference.

–16–

REV. C

OP191/OP291/OP491

R2

2.67k⍀

V

1␮F

IN

C4

2

3

R6
100k⍀

3V

R9

1M⍀

3V

11

1/4

OP491

4

R10
1M⍀

9

10

1

A1

R11

100k⍀

1/4

OP491

R1

2.67k⍀

(1␮Fⴛ2)

C5

0.01␮F

A3

R3

2.67k⍀

C3

2␮F

8

C1

1␮F

R12

499⍀

C2

1␮F

R4

2.67k⍀

R5

1.33k⍀
(2.67k⍀

C6

1.5V
1␮F

5

1/4

OP491

6

A2

2)
R8

1k⍀

R7

1k⍀

V

OUT

7

Figure 13. A 3 V Single-Supply, 50 Hz/60 Hz Active Notch
Filter with False Ground

Amplifier A3 is the heart of the false ground bias circuit. It
simply buffers the voltage developed by R9 and R10 and is the
reference for the active notch filter. Since the OP491 exhibits a
rail-to-rail input common-mode range, R9 and R10 are chosen
to split the 3 V supply symmetrically. An in-the-loop compen­sation scheme used around the OP491 allows the op amp to
drive C6, a 1 mF capacitor, without oscillation. C6 maintains a
low impedance ac ground over the operating frequency range of
the filter.

The filter section uses a pair of OP491s in a twin-T configura­tion whose frequency selectivity is very sensitive to the relative
matching of the capacitors and resistors in the twin-T section.
Mylar is the material of choice for the capacitors, and the rela­tive matching of the capacitors and resistors determines the
filter’s pass-band symmetry. Using 1% resistors and 5% capaci­tors produces satisfactory results.

Single-Supply, Half-Wave and Full-Wave Rectifiers

An OP191 family configured as a voltage follower operating on
a single supply can be used as a simple half-wave rectifier in
low frequency (<2 kHz) applications. A full-wave rectifier can
be configured with a pair of OP291s as illustrated in Figure 14.
The circuit works in the following way. When the input signal is
above 0 V, the output of amplifier A1 follows the input signal.
Since the noninverting input of amplifier A2 is connected to
A1’s output, op amp loop control forces the A2’s inverting input
to the same potential. The result is that both terminals of R1 are
equipotential; i.e., no current flows. Since there is no current
flow in R1, the same condition exists upon R2; thus, the output
of the circuit tracks the input signal. When the input signal is
below 0 V, the output voltage of A1 is forced to 0 V. This con­dition now forces A2 to operate as an inverting voltage follower
because the noninverting terminal of A2 is at 0 V as well. The
output voltage at V

A is then a full-wave rectified version of

OUT

the input signal. If needed, a buffered, half-wave rectified version
of the input signal is available at V

R1

100k⍀

5V

V

IN

3

100

90

10

0%

OP291

2

1/2

1V

8

4

A1

500mV

1

500mV

TIME (200␮s/DIV)

2V p-p
<2kHz

(1V/DIV)

V

(0.5V/DIV)

V

(0.5V/DIV)

OUT

OUT

V

IN

B

A

OUT

6

OP291

5

B.

R2

100k⍀

1/2

200␮s

A2

V

A

OUT

7

FULL-WAVE
RECTIFIED
OUTPUT

V

B

OUT

HALF-WAVE
RECTIFIED
OUTPUT

Figure 14. Single-Supply, Half-Wave and Full-Wave
Rectifiers Using an OP291

REV. C

–17–

OP191/OP291/OP491

* OP491 SPICE Macro-model REV. C, 5/94
* ARG/ADI
*
* Copyright 1994 by Analog Devices, Inc.
*
* Refer to “README.DOC” file for License State­ment. Use of
* this model indicates your acceptance of the
terms and provisions in the License Statement.
*
* Node assignments
* noninverting input
* inverting input
* positive supply
* negative supply
* output
*
.SUBCKT OP491 1 2 99 50 45
*
* INPUT STAGE
*
I1 99 7 8.06E-6
Q1 6 4 7 QP
Q2 5 3 7 QP
D1 3 99 DX
D2 4 99 DX
D3 34DX
D4 43DX
R1 3 8 5E3
R2 4 2 5E3
R3 5 50 6.4654E3
R4 6 50 6.4654E3
EOS 8 1 POLY(1) (16,39) –0.08E-3 1
IOS 3 4 50E-12
GB1 3 98 (21,98) 50E-9
GB2 4 98 (21,98) 50E-9
CIN 1 2 1E-12
*
* 1ST GAIN STAGE
*
EREF 98 0 (39,0) 1
G1 98 9 (6,5) 31.667E-6
R7 9 98 1E6
EC1 99 10 POLY(1) (99,39) –0.52 1
EC2 11 50 POLY(1) (39,50) –0.52 1
D5 9 10 DX
D6 11 9 DX
*
* 2ND GAIN STAGE AND DOMINANT POLE AT 1.25 Hz
*
G2 98 12 (9,39) 8E-6
R8 12 98 276.311E6
C2 12 98 16E-12
D7 12 13 DX
D8 14 12 DX
V1 99 13 0.58
V2 14 50 0.58
*
* COMMON-MODE STAGE
*
ECM 15 98 POLY(2) (1,39) (2,39) 0 0.5 0.5
R9 15 16 1E6

R10 16 98 10
*
* POLE AT 2.5 MHz
*
G3 98 18 (12,39) 1E-6
R11 18 98 1E6
C4 18 98 63.662E-15
*
* BIAS CURRENT-VS-COMMON-MODE VOLTAGE
*
EP 97 0 (99,0) 1
VB 99 17 1.3
RB 17 50 1E9
E3 19 0 (15,17) 16
D13 19 20 DX
R12 20 0 1E6
G4 98 21 (20,0) 1E-3
R13 21 98 5E3
D14 21 22 DY
E4 97 22 (POLY(1) (99,98) -0.765 1
*
* POLE AT 100 MHz
*
G6 98 40 (18,39) 1E-6
R20 40 98 1E6
C10 40 98 1.592E-15
*
* OUTPUT STAGE
*
RS1 99 39 109.375E3
RS2 39 50 109.375E3
RO1 99 45 41.667
RO2 45 50 41.667
G7 45 99 (99,40) 24E-3
G8 50 45 (40,50) 24E-3
G9 98 60 (45,40) 24E-3
D9 60 61 DX
D10 62 60 DX
V7 61 98 DC 0
V8 98 62 DC 0
FSY 99 50 POLY(2) V7 V8 0.207E-3 1 1
D11 41 45 DZ
D12 45 42 DZ
V5 40 41 0.131
V6 42 40 0.131
.MODEL DX D()
.MODEL DY D(IS=1E-9)
.MODEL DZ D(IS=1E-6)
.MODEL QP PNP(BF=66.667)
.ENDS

–18–

REV. C

OUTLINE DIMENSIONS

14

1

7

8

0.685 (17.40)

0.665 (16.89)

0.645 (16.38)

0.295 (7.49)

0.285 (7.24)

0.275 (6.99)

0.100 (2.54)
BSC

SEATING
PLANE

0.180 (4.57)
MAX

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

0.150 (3.81)

0.130 (3.30)

0.110 (2.79)

0.060 (1.52)

0.050 (1.27)

0.045 (1.14)

0.150 (3.81)

0.135 (3.43)

0.120 (3.05)

0.015 (0.38)

0.010 (0.25)

0.008 (0.20)

0.325 (8.26)

0.310 (7.87)

0.300 (7.62)

0.015 (0.38)
MIN

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

COMPLIANT TO JEDEC STANDARDS MO-095-AB

4.50

4.40

4.30

14

8

71

6.40
BSC

PIN 1

5.10

5.00

4.90

0.65
BSC

SEATING
PLANE

0.15

0.05

0.30

0.19

1.20
MAX

1.05

1.00

0.80

0.20

0.09
8ⴗ
0ⴗ

0.75

0.60

0.45

COMPLIANT TO JEDEC STANDARDS MO-153AB-1

COPLANARITY

0.10

OP191/OP291/OP491

8-Lead Standard Small Outline Package [SOIC]

Narrow Body

[S-Suffix]

(R-8)

Dimensions shown in millimeters and (inches)

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

85

1.27 (0.0500)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012AA

BSC

6.20 (0.2440)

5.80 (0.2284)

41

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

8ⴗ
0ⴗ

1.27 (0.0500)

0.40 (0.0157)

14-Lead Standard Small Outline Package [SOIC]

Narrow Body

[S-Suffix]

(R-14)

Dimensions shown in millimeters and (inches)

14-Lead Plastic Dual In-Line Package [PDIP]

[P-Suffix]

(N-14)

Dimensions shown in inches and (millimeters)

ⴛ 45ⴗ

14-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-14)

Dimensions shown in millimeters

8.75 (0.3445)

8.55 (0.3366)

8

6.20 (0.2441)

7

5.80 (0.2283)

1.75 (0.0689)

1.35 (0.0531)

SEATING
PLANE

0.25 (0.0098)

0.17 (0.0067)

4.00 (0.1575)

3.80 (0.1496)

0.25 (0.0098)

0.10 (0.0039)

COPLANARITY

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

REV. C

14

1

1.27 (0.0500)
BSC

0.51 (0.0201)

0.10

0.31 (0.0122)

COMPLIANT TO JEDEC STANDARDS MS-012AB

0.50 (0.0197)

0.25 (0.0098)

8ⴗ
0ⴗ

1.27 (0.0500)

0.40 (0.0157)

ⴛ 45ⴗ

–19–

OP191/OP291/OP491

Revision History

Location Page

3/04—Data Sheet changed from REV. B to REV. C.

Changes to OP291 SOIC PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

11/03—Data Sheet changed from REV. A to REV. B.

Edits to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Edits to PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

12/02—Data Sheet changed from REV. 0 to REV. A.

Edits to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Edits to PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Edits to DICE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

C00294–0–3/04(C)

–20–

REV. C