Analog Devices AD7243 Datasheet

LC2MOS

a

FEATURES
12-Bit CMOS DAC with

On-Chip Voltage Reference
Output Amplifier

Three Selectable Output Ranges

–5 V to +5 V, 0 V to +5 V, 0 V to +10 V
Serial Interface
300 kHz DAC Update Rate
Small Size: 16-Lead DIP or SOIC
Nonlinearity: ⴞ1/2 LSB T
Low Power Dissipation: 100 mW Typical

APPLICATIONS
Process Control
Industrial Automation
Digital Signal Processing Systems
Input/Output Ports

GENERAL DESCRIPTION

The AD7243 is a complete 12-bit, voltage output, digital-to­analog converter with output amplifier and Zener voltage refer­ence on a monolithic CMOS chip. No external trims are
required to achieve full specified performance.

The output amplifier is capable of developing +10 V across a
2 kΩ load. The output voltage ranges with single supply opera­tion are 0 V to +5 V or 0 V to +10 V, while an additional bipo­lar ± 5 V output range is available with dual supplies. The ranges
are selected using the internal gain resistor.

The data format is natural binary in both unipolar ranges, while
either offset binary or two’s complement format may be selected
in the bipolar range. A CLR function is provided which sets the
output to 0 V in both unipolar ranges and in the two’s comple­ment bipolar range, while with offset binary data format, the
output is set to –REFIN. This function is useful as a power-on
reset as it allows the output to be set to a known voltage level.

The AD7243 features a fast versatile serial interface which
allows easy connection to both microcomputers and 16-bit digi­tal signal processors with serial ports. The serial data may be
applied at rates up to 5 MHz allowing a DAC update rate of
300 kHz. A serial data output capability is also provided which
allows daisy chaining in multi-DAC systems. This feature allows
any number of DACs to be used in a system with a simple
4-wire interface. All DACs may be updated simultaneously
using LDAC.

MIN

to T

MAX

12-Bit Serial DACPORT

AD7243

FUNCTIONAL BLOCK DIAGRAM

V

DD

LDAC

2R

2R

DCEN SDO

R

OFS

V

OUT

AGND

DGND

V

SS

REFOUT

REFIN

AD7243

SDIN CLR SCLK

The AD7243 is fabricated on Linear Compatible CMOS

2

(LC

MOS), an advanced, mixed technology process. It is pack-

12 - BIT DAC

12

DAC LATCH

12

INPUT SHIFT REGISTER

BIN/

COMP

SYNC

aged in 16-lead DIP and 16-lead SOIC packages.

PRODUCT HIGHLIGHTS

1. Complete 12-Bit DACPORT

®

The AD7243 is a complete, voltage output, 12-bit DAC on
a single chip. The single chip design is inherently more
reliable than multichip designs.

2. Single or Dual Supply Operation.

3. Minimum 3-wire interface to most DSP processors.

4. DAC Update Rate–300 kHz.

5. Serial Data Output allows easy daisy-chaining in multiple
DAC systems.

DACPORT is a registered trademark of Analog Devices, Inc.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

(VDD = +12 V to +15 V,1 VSS = 0 V or –12 V to –15 V,1 AGND = DGND = O V, REFIN = +5 V,

AD7243–SPECIFICATIONS

Parameter A

STATIC PERFORMANCE

Resolution 12 12 12 Bits
Relative Accuracy
Differential Nonlinearity
Unipolar Offset Error

Bipolar Zero Error
Full-Scale Error

3

3

3

3

3, 4

Full-Scale Temperature Coefficient

REFERENCE OUTPUT

Reference Output Range, REFOUT 4.95/5.05 4.95/5.05 4.95/5.05 V min/V max
Reference Temperature Coefficient
Reference Load Change
(∆REFOUT VS. IL) –1 –1 –1 mV max Reference Load Current (IL) Change (0–100 µA)

REFERENCE INPUT

Reference Input Range, REFIN 4.95/5.05 4.95/5.05 4.95/5.05 V min/V max 5 V ± 1% for Specified Performance
Input Current 5 5 5 µA max

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance

INH

INL

IN

5

DIGITAL OUTPUT

Serial Data Out (SDO)
Output Low Voltage, V
Output High Voltage, V

OL

OH

ANALOG OUTPUT

Output Range Resistor, R
Output Voltage Ranges
Output Voltage Ranges
DC Output Impedance

AC CHARACTERISTICS

OFS

6

6

5

5

Voltage Output Settling-Time Settling Time to Within ± 1/2 LSB of Final Value

Positive Full-Scale Change 10 10 10 µs max Typically 4 µs
Negative Full-Scale Change 10 10 10 µs max Typically 5 µs

Digital-to-Analog Glitch Impulse

Digital Feedthrough

3

POWER REQUIREMENTS

Range +10.8/+16.5 +10.8/+16.5 +11.4/+15.75 V min/V max For Specified Performance Unless Otherwise Stated

V

DD

VSS Range (Dual Supplies) –10.8/–16.5 –10.8/–16.5 –11.4/–15.75 V min/V max For Specified Performance Unless Otherwise Stated
I

DD

ISS (Dual Supplies) 2 2 2 mA max Output Unloaded; Typically 1 mA

NOTES

1

Power Supply Tolerance A, B Versions: ± 10%; S Version: ±5%.

2

Temperature ranges are as follows: A, B Versions: –40°C to +85°C; S Version: –55°C to +125°C.

3

See terminology.

4

Measured with respect to REFIN and includes unipolar/bipolar offset error.

5

Guaranteed by design and characterization, not production tested.

6

0 V to +10 V output range is available only with VDD ≥ +14.25 V.

Specifications subject to change without notice.

2

± 1 ± 1/2 ± 1 LSB max
± 0.9 ± 0.9 ± 0.9 LSB max Guaranteed Monotonic
± 4 ± 4 ± 5 LSB max VSS = 0 V or –12 V to –15 V1; DAC Latch

± 5 ± 5 ± 6 LSB max VSS = –12 V to –15 V1; DAC Latch Contents All 0s
± 6 ± 6 ± 7 LSB max

5

± 5 ± 5 ± 5 ppm of FSR/ Guaranteed By Process

5

± 25 ± 25 ± 30 ppm/°C typ Guaranteed By Process

2.4 2.4 2.4 V min

0.8 0.8 0.8 V max
± 1 ± 1 ± 1 µA max VIN = 0 V to V
8 8 8 pF max

0.4 0.4 0.4 V max I

4.0 4.0 4.0 V min I

15/30 15/30 15/30 kΩ min/max Typically 20 k⍀. Guaranteed By Process
+5, +10 +5, +10 +5, +10 V Single Supply; VSS = 0 V
+5, +10, ± 5 +5, +10, ± 5 +5, +10, ± 5 V Dual Supply; VSS = –12 V to –15 V

0.5 0.5 0.5 Ω typ

3

30 30 30 nV secs typ DAC Latch Contents Toggled Between All 0s

10 10 10 nV secs typ LDAC = High

10 10 10 mA max Output Unloaded; Typically 7 mA

RL = 2 k⍀, CL = 100 pF to AGND. All Specifications T

2

B

2

S

Unit Test Conditions/Comments

°C typ

Contents All 0s

= 1.6 mA

SINK

= 400 µA

SOURCE

and All 1s

MIN

DD

to T

unless otherwise noted.)

MAX

–2–

REV. A

TIMING CHARACTERISTICS

WARNING!

ESD SENSITIVE DEVICE

(VDD = +10.8 V to +16.5 V, VSS = 0 V or –10.8 V to –16.5 V, AGND = DGND = 0 V,

1, 2

RL = 2 k⍀, CL = 100 pF. All Specifications T

MIN

to T

unless otherwise noted.)

MAX

AD7243

Limit at +25ⴗC, T

MIN

, T

MAX

Parameter (All Versions) Units Conditions/Comments

3

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

4, 5

t

10

4, 6

t

11

NOTES

1

Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

2

See Figures 7 & 8.

3

SCLK mark/space ratio range is 40/60 to 60/40.

4

SDO load capacitance is no greater than 50 pF.

5

At 25°C t10 is 130 ns max.

6

Guaranteed by design.

ABSOLUTE MAXIMUM RATINGS

(TA = +25°C unless otherwise noted)

VDD to AGND, DGND . . . . . . . . . . . . . . . . . –0.3 V to +17 V

V

to AGND, DGND . . . . . . . . . . . . . . . . . +0.3 V to –17 V

SS

AGND to DGND . . . . . . . . . . . . . . . . –0.3 V to V

2

V

to AGND . . . . . . . . . . . . . . . . . . . –6 V to VDD + 0.3 V

OUT

REFOUT to AGND . . . . . . . . . . . . . . . . . . . . . . . 0 V to V

REFIN to AGND . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V

Digital Inputs to DGND . . . . . . . . . . . –0.3 V to V

SDO to DGND . . . . . . . . . . . . . . . . . . –0.3 V to V

Operating Temperature Range

Industrial (A, B Versions) . . . . . . . . . . . . . –40°C to +85°C

200 ns min SCLK Cycle Time
15 ns min SYNC to SCLK Falling Edge Setup Time
70 ns min SYNC to SCLK Hold Time
0 ns min Data Setup Time
40 ns min Data Hold Time
0 ns min SYNC High to LDAC Low
20 ns min LDAC Pulsewidth
0 ns min LDAC High to SYNC Low
20 ns min CLR Pulsewidth
160 ns max SCLK Falling Edge to SDO Valid
>t

5

1

ns min SCLK Falling Edge to SDO Invalid

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . .+300°C

Power Dissipation (Any Package) to +75°C . . . . . . . 450 mW

Derates above +75°C by . . . . . . . . . . . . . . . . . . . . . 6 mW/°C

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

DD

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi­tions for extended periods may affect device reliability. Only one Absolute
Maximum Rating may be applied at any time.

2

The outputs may be shorted to voltages in this range provided the power dissipation
of the package is not exceeded. Short circuit current is typically 80 mA.

Extended (S Version) . . . . . . . . . . . . . . . . –55°C to +125°C

ORDERING GUIDE

Model Temperature Range Relative Accuracy Package Option

AD7243AN –40°C to +85°C ± 1 LSB N-16
AD7243BN –40°C to +85°C ± 1/2 LSB N-16
AD7243AR –40°C to +85°C ± 1 LSB R-16
AD7243BR –40°C to +85°C ± 1/2 LSB R-16
AD7243AQ –40°C to +85°C ± 1 LSB Q-16
AD7243BQ –40°C to +85°C ± 1/2 LSB Q-16
AD7243SQ

NOTES

1

N = Plastic DIP; R = SOIC; Q = Cerdip.

2

Available to /883B processing only. Contact your local sales office for military data sheet.

2

–55°C to +125°C ± 1 LSB Q-16

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7243 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

REV. A

–3–

1

AD7243

TERMINOLOGY
Bipolar Zero Error

Bipolar Zero Error is the voltage measured at V

when the

OUT

DAC is configured for bipolar output and loaded with all 0s
(Two’s Complement Coding) or with 1000 0000 0000 (Offset
Binary Coding). It is due to a combination of offset errors in the
DAC, amplifier and mismatch between the internal gain resis­tors around the amplifier.

Full-Scale Error

Full-Scale Error is a measure of the output error when the am­plifier output is at full scale (for the bipolar output range full
scale is either positive or negative full scale). It is measured with
respect to the reference input voltage and includes the offset
errors.

Digital-to-Analog Glitch Impulse

This is the voltage spike that appears at V

when the digital

OUT

code in the DAC latch changes, before the output settles to its
final value. The energy in the glitch is specified in nV secs, and
is measured for an all codes change from 0000 0000 0000 to
1111 1111 1111 and vice versa.

Digital Feedthrough

This is a measure of the voltage spike that appears on V

OUT

as a

result of feedthrough from the digital inputs on the AD7243. It
is measured with LDAC held high.

Relative Accuracy (Linearity)

Relative Accuracy, or endpoint linearity, is a measure of the
maximum deviation of the DAC transfer function from a
straight line passing through the endpoints of the transfer func­tion. It is measured after allowing for zero and full-scale errors
and is expressed in LSBs or as a percentage of full-scale reading.

Single Supply Linearity and Gain Error

The output amplifier on the AD7243 can have true negative off­sets even when the part is operated from a single +15 V supply.
However, because the negative supply rail (V

) is 0 V, the out-

SS

put cannot actually go negative. Instead, when the output offset
voltage is negative, the output voltage sits at 0 V, resulting in the
transfer function shown in Figure 1.

OUTPUT

VOLTAGE

NEGATIVE

OFFSET

0V

{

DAC CODE

Figure 1. Effect of Negative Offset (Single Supply)

AD7243 PIN FUNCTION DESCRIPTIONS (DIP and SOIC PIN NUMBERS)

Pin Mnemonic Description

1 REFIN Voltage Reference Input. It is internally buffered before being applied to the DAC. The nominal reference

voltage for specified operation of the AD7243 is 5 V.

2 REFOUT Voltage Reference Output. The internal 5 V analog reference is provided at this pin. To operate the part -

using its internal reference, REFOUT should be connected to REFIN.

3 CLR Clear, Logic Input. Taking this input low sets V

to 0 V in both unipolar ranges and the two’s complement

OUT

bipolar range and to –REFIN in the offset binary bipolar range.

4 BIN/COMP Logic Input. This input selects the data format to be either binary or two’s complement. In both unipolar

ranges, natural binary format is selected by connecting this input to a Logic “0.” In the bipolar configuration,

offset binary format is selected with a Logic “0” while a Logic “1” selects two’s complement format.
5 SCLK Serial Clock, Logic Input. Data is clocked into the input register on each falling SCLK edge.
6 SDIN Serial Data In, Logic Input. The 16-bit serial data word is applied to this input.
7 SYNC Data Synchronization Pulse, Logic Input. Taking this input low initializes the internal logic in readiness for a

new data word.
8 DGND Digital Ground. Ground reference for all digital circuitry.
9 LDAC Load DAC, Logic Input. Updates the DAC output. The DAC output is updated on the falling edge of this

signal or alternatively if this line is permanently low, an automatic update mode is selected whereby the DAC

is updated on the 16th falling SCLK pulse.
10 DCEN Daisy-Chain Enable, Logic Input. Connect this pin high if a daisy-chain interface is being used, otherwise

this pin must be connected low.
11 SDO Serial Data Out, Logic Output. With DCEN at Logic “1” this output is enabled, and the serial data in the

input shift register is clocked out on each falling SCLK edge.
12 AGND Analog Ground. Ground reference for all analog circuitry.
13 R

OFS

Output Offset Resistor for the amplifier. It is connected to V

for the +5 V range, to AGND for the +10 V

OUT

range and to REFIN for the –5 V to +5 V range.
14 V

OUT

Analog Output Voltage. This is the buffer amplifier output voltage. Three different output voltage ranges can

be chosen: 0 V to +5 V, 0 to +10 V and –5 V to +5 V.
15 V

SS

Negative Power Supply (used for the output amplifier only, may be connected to 0 V for single supply

operation or to –12 V to –15 V for dual supplies).
16 V

DD

Positive Power Supply (+12 V to +15 V).

–4–

REV. A