Analog Devices ad7228a Datasheet

LC2MOS

a

FEATURES
Eight 8-Bit DACs with Output Amplifiers
Operates with Single +5 V, +12 V or +15 V

or Dual Supplies
mP Compatible (95 ns
No User Trims Required
Skinny 24-Pin DlPs, SOIC, and 28-Terminal Surface

Mount Packages

WR Pulse)

Octal 8-Bit DAC

AD7228A

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

The AD7228A contains eight 8-bit voltage-mode digital-to­analog converters, with output buffer amplifiers and interface
logic on a single monolithic chip. No external trims are required
to achieve full specified performance for the part.

Separate on-chip latches are provided for each of the eight D/A
converters. Data is transferred into the data latches through a
common 8-bit TTL/CMOS (5 V) compatible input port. Ad­dress inputs A0, A1 and A2 determine which latch is loaded
when

WR goes low. The control logic is speed compatible with

most 8-bit microprocessors.
Specified performance is guaranteed for input reference voltages

from +2 to +10 V when using dual supplies. The part is also
specified for single supply +15 V operation using a reference of
+10 V and single supply +5 V operation using a reference of
+1.23 V. Each output buffer amplifier is capable of developing
+10 V across a 2 kΩ load.

The AD7228A is fabricated on an all ion-implanted, high­speed, Linear Compatible CMOS (LC
been specifically developed to integrate high-speed digital logic
circuits and precision analog circuits on the same chip.

2

MOS) process which has

PRODUCT HIGHLIGHTS

1. Eight DACs and Amplifiers in Small Package
The single-chip design of eight 8-bit DACs and amplifiers al­lows a dramatic reduction in board space requirements and
offers increased reliability in systems using multiple convert­ers. Its pinout is aimed at optimizing board layout with all
analog inputs and outputs at one side of the package and all
digital inputs at the other.

2. Single or Dual Supply Operation
The voltage-mode configuration of the DACs allows single
supply operation of the AD7228A. The part can also be oper­ated with dual supplies giving enhanced performance for
some parameters.

3. Microprocessor Compatibility
The AD7228A has a common 8-bit data bus with individual
DAC latches, providing a versatile control architecture for
simple interface to microprocessors. All latch enable signals
are level triggered and speed compatible with most high per­formance 8-bit microprocessors.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] Fax: [phone]

AD7228A–SPECIFICA TIONS

DUAL SUPPLY

(VDD = 10.8 V to 16.5 V; VSS = –5 V 6 10%; GND = 0 V; V
noted.) All specifications T

MIN

to T

unless otherwise noted.

MAX

= +2 V to +10 V1; RL = 2 kΩ, CL = 100 pF unless otherwise

REF

BCTU

Parameter Version2Version Version Version Units Conditions/Comments

STATIC PERFORMANCE

Resolution 8 8 8 8 Bits
Total Unadjusted Error
Relative Accuracy ± 1 ± 1/2 ± 1 ±1/2 LSB max
Differential Nonlinearity ± 1 ±1 ±1 ±1 LSB max Guaranteed Monotonic
Full-Scale Error

3

4

±2 ±1 ±2 ±1 LSB max VDD = +15 V ± 10%, V

= +10 V

REF

±1 ±1/2 ±1 ±1/2 LSB max Typical tempco is 5 ppm/°C with V
Zero Code Error
@ 25°C ±25 ±15 ±25 ±15 mV max Typical tempco is 30 µV/°C

T

to T

MIN

Minimum Load Resistance 2 2 2 2 kΩ min V

REFERENCE INPUT

Voltage Range
Input Resistance 2 2 2 2 kΩ min
Input Capacitance

MAX

1

5

AC Feedthrough –70 –70 –70 –7 0 dB typ V

±30 ±20 ±30 ±20 mV max

= +10 V

OUT

2 to 10 2 to 10 2 to 10 2 to 10 V min/V max

500 500 500 500 pF max Occurs when each DAC is loaded with all 1s.

= 8 V p-p Sine Wave @ 10 kHz

REF

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Leakage Current ±1 ±1 ±1 ±1 µA max VIN = 0 V or V
Input Capacitance

INH

INL

5

2.4 2.4 2.4 2.4 V min

0.8 0.8 0.8 0.8 V max

8 8 8 8 pF max

DD

Input Coding Binary Binary Binary Binary

DYNAMIC PERFORMANCE

5

Voltage Output Slew Rate 2 2 2 2 V/µs min
Voltage Output Settling Time

Positive Full-Scale Change 5 5 5 5 µs max V

Negative Full-Scale Change 5 5 5 5 µs max V
Digital Feedthrough 50 50 50 50 nV secs typ Code transition all 0s to all 1s. V
Digital Crosstalk

6

50 50 50 50 nV secs typ Code transition all 0s to all 1s. V

= +10 V; Settling Time to ±1/2 LSB

REF

= +10 V; Settling Time to ±1/2 LSB

REF

POWER SUPPLIES

VDD Range 10.8/16.5 10.8/16.5 10.8/16.5 10.8/16.5 V min/V max For Specified Performance
VSS Range –4.5/–5.5 –4.5/–5.5 –4.5/–5.5 –4.5/–5.5 V min/V max For Specified Performance
I

DD

@ 25°C 16 1 6 16 16 mA max

T

to T

MIN

MIN

to T

MAX

MAX

I

SS

@ 25°C 14 1 4 14 14 mA max

T

20 20 22 22 mA max

18 18 20 20 mA max

Outputs Unloaded; VIN = V

Outputs Unloaded; VIN = V

= +10 V

REF

= 0 V; WR = V

REF

= +10 V; WR = 0 V

REF

or V

INL

INH

or V

INL

INH

DD

SINGLE SUPPLY

(VDD = +15 V 6 10%, VSS; = GND = 0 V; V
AII specifications T

MIN

to T

unless otherwise noted.

MAX

= +10 V, RL = 2 kΩ, CL = 100 pF unless otherwise noted.)

REF

STATIC PERFORMANCE

Resolution 8 8 8 8 Bits
Total Unadjusted Error

3

±2 ±1 ±2 ±1 LSB max
Differential Nonlinearity ± 1 ±1 ±1 ±1 LSB max Guaranteed Monotonic
Minimum Load Resistance 2 2 2 2 kΩ min V

= +10 V

OUT

REFERENCE INPUT

Input Resistance 2 2 2 2 kΩ min
Input Capacitance

5

500 500 500 500 pF max Occurs when each DAC is loaded with all 1s.

DIGITAL INPUTS As per Dual Supply Specifications
DYNAMIC PERFORMANCE

5

Voltage Output Slew Rate 2 2 2 2 V/µs min
Voltage Output Settling Time

Positive Full-Scale Change 5 5 5 5 µs max Settling Time to ±1/2 LSB

Negative Full-Scale Change 7 7 7 7 µs max Settling Time to ±1/2 LSB
Digital Feedthrough 50 50 50 50 nV secs typ Code transition all 0s to all 1s. V
Digital Crosstalk

6

50 50 50 50 nV secs typ Code transition all 0s to all 1s. V

POWER SUPPLIES

VDD Range 13.5/16.5 13.5/16.5 13.5/16.5 13.5/16.5 V min/V max For Specified Performance
I

DD

@ 25°C 16 1 6 16 16 mA max

T

to T

MIN

MAX

NOTES

1

V

must be less than VDD by 3.5 V to ensure correct operation.

OUT

2

Temperature ranges are as follows:

B, C Versions; –40°C to +85°C
T, U Versions; –55°C to +125°C

3

Total Unadjusted Error includes zero code error, relative accuracy and full-scale error.

4

Calculated after zero code error has been adjusted out.

20 20 22 22 mA max

5

Sample tested at 25°C to ensure compliance.

6

The glitch impulse transferred to the output of one converter (not addressed) due to a

change in the digital input code to another addressed converter.

Specifications subject to change without notice.

Outputs Unloaded; VIN = V

= 0 V; WR = V

REF

= +10 V, WR = 0 V

REF

or V

INL

INH

DD

–2–

REV. A

AD7228A

(VDD = +5 V 6 5%, VSS; = 0 to –5 V 6 10%, GND = 0 V, V

+5 V SUPPLY OPERA TION

Parameter Version Version Version Version Units Conditions/Comments

STATIC PERFORMANCE

Resolution 8888Bits
Relative Accuracy ± 2 ±2 ±2 ±2 LSB max
Differential Nonlinearity ±1 ±1 ±1 ±1 LSB max Guaranteed Monotonic
Full-Scale Error ±4 ±2 ±4 ±2 LSB max
Zero Code Error

@ 25°C ±30 ±20 ± 30 ±20 mV max
T

to T

MIN

MAX

REFERENCE INPUT

Reference Input Range 1.2 1.2 1.2 1.2 V min
Reference Input Resistance 2222kΩ min

Reference Input Capacitance 500 500 500 500 pF max

POWER REQUIREMENTS

Positive Supply Range 4.75/5.25 4.75/5.25 4.75/5.25 4.75/5.25 V min/V max For Specified Performance
Positive Supply Current

@ 25°C 16161616µA max
T

to T

MIN

MIN

to T

MAX

MAX

Negative Supply Current

@ 25°C 14141414µA max
T

NOTES

All of the specifications as per Dual Supply Specifications except for negative full-scale settling-time when V

Specifications subject to change without notice.

SWITCHING CHARACTERISTICS

unless otherwise noted.) AII specifications T

BCTU

±40 ± 30 ±40 ±30 mV max

1.3 1.3 1.3 1.3 V max

20 20 22 22 µA max

18 18 20 20 µA max

SS

1, 2

(See Figures 1, 2; VDD = +5 V 6 5% or +10.8 V to +16.5 V; VSS = 0 V or –5 V 6 10%)

= 0 V.

MIN

to T

= +1.25 V, RL = 2 kV, CL = 100 pF

REF

unless otherwise noted.

MAX

Parameters All Grades (B, C Versions) (T, U Versions) Units Conditions/Comments

t

1

t

2

t

3

t

4

t

5

NOTES

1

Sample tested at 25°C to ensure compliance. All input rise and fall times measured from 10% to 90% of +5 V, tR = tF = 5 ns.

2

Timing measurement reference level is

Limit at 25°C Limit at T

0 0 0 ns min Address to WR Setup Time

0 0 0 ns min Address to WR Hold Time
70 90 100 ns min Data Valid to WR Setup Time
10 10 10 ns min Data Valid to WR Hold Time
95 120 150 ns min Write Pulse Width

V

INH+VINL

2

MIN

, T

MAX

Limit at T

MIN

, T

MAX

INTERFACE LOGIC INFORMATION

Address lines A0, A1 and A2 select which DAC accepts data
from the input port. Table I shows the selection table for the
eight DACs with Figure 1 showing the input control logic.
When the

WR signal is low, the input latch of the selected DAC
is transparent, and its output responds to activity on the data
bus. The data is latched into the addressed DAC latch on the
rising edge of

WR. While WR is high, the analog outputs remain
at the value corresponding to the data held in their respective
latches.

Table I. AD7228A Truth Table

AD7228A Control Inputs AD7228A
WR A2 A1 A0 Operation

H X X X No Operation

Device Not Selected

LLLL DAC 1 Transparent

g

L L L DAC 1 Latched
LLLH DAC 2 Transparent
L L H L DAC 3 Transparent
L L H H DAC 4 Transparent
L H L L DAC 5 Transparent
L H L H DAC 6 Transparent
L H H L DAC 7 Transparent
L H H H DAC 8 Transparent

H = High State L = Low State X = Don’t Care

REV. A

–3–

Figure 1. Input Control Logic

Figure 2. Write Cycle Timing Diagram