ANALOG DEVICES AD7193 Service Manual

24-Bit Sigma-Delta ADC with PGA

AD7193

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

Trademarks and registered trademarks are the property of their respective owners.

MCLK1 MCLK2 P0/REFIN2(–) P1/REFIN2(+)

DV

DD

DGND REFIN1(+) REFIN1(–)

AIN1 AIN2 AIN3 AIN4

AINCOM

BPDSW

AGND

AD7193

SERIAL

INTERFACE

AND

CONTROL

LOGIC

TEMP

SENSOR

CLOCK

CIRCUITRY

DOUT/RDY DIN SCLK CS SYNC

P3 P2

AVDDAGND

AIN5 AIN6 AIN7 AIN8

Σ-Δ

ADC

PGA

MUX

08367-001

Data Sheet

FEATURES

Fast settling filter option 4 differential/8 pseudo differential input channels RMS noise: 11 nV @ 4.7 Hz (gain = 128)

15.5 noise-free bits @ 2.4 kHz (gain = 128) Up to 22 noise-free bits (gain = 1) Offset drift: ±5 nV/°C Gain drift: ±1 ppm/°C Specified drift over time Automatic channel sequencer Programmable gain (1 to 128) Output data rate: 4.7 Hz to 4.8 kHz Internal or external clock Simultaneous 50 Hz/60 Hz rejection 4 general-purpose digital outputs Power supply

AV

: 3 V to 5.25 V

DD

DV

: 2.7 V to 5.25 V

DD

Current: 4.65 mA Temperature range: −40°C to +105°C 28-lead TSSOP and 32-lead LFCSP packages Interface

3-wire serial SPI, QSPI™, MICROWIRE™, and DSP compatible Schmitt trigger on SCLK

APPLICATIONS

PLC/DCS analog input modules Data acquisition Strain gage transducers

FUNCTIONAL BLOCK DIAGRAM

4-Channel, 4.8 kHz, Ultralow Noise,

Pressure measurement Temperature measurement Flow measurement Weigh scales Chromatography Medical and scientific instrumentation

GENERAL DESCRIPTION

The AD7193 is a low noise, complete analog front end for high precision measurement applications. It contains a low noise, 24-bit sigma-delta (Σ-Δ) analog-to-digital converter (ADC). The on-chip low noise gain stage means that signals of small amplitude can interface directly to the ADC.

The device can be configured to have four differential inputs or eight pseudo differential inputs. The on-chip channel sequencer allows several channels to be enabled simultaneously, and the AD7193 sequentially converts on each enabled channel, simplifying communication with the part. The on-chip 4.92 MHz clock can be used as the clock source to the ADC or, alternatively, an external clock or crystal can be used. The output data rate from the part can be varied from 4.7 Hz to 4.8 kHz.

The device has a very flexible digital filter, including a fast settling option. Variables such as output data rate and settling time are dependent on the option selected. The AD7193 also includes a zero latency option.

The part operates with a power supply from 3 V to 5.25 V. It consumes a current of 4.65 mA, and it is available in a 28-lead TSSOP package and a 32-lead LFCSP package.

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700

www.analog.com

AD7193 Data Sheet

REVISION HISTORY

12/11—Rev. B to Rev. C

Moved Revision History Section ..................................................... 3

Changes to Table 6 .......................................................................... 13

4/10—Rev. A to Rev. B

Added 32-Lead LFCSP ...................................................... Universal

Changes to Table 7 .......................................................................... 17

Changes to Communications Register, Table 16 ......................... 20

Updated Outline Dimensions ........................................................ 54

Changes to Ordering Guide ........................................................... 54

9/09—Rev. 0 to Rev. A

Changes to Internal/External Clock, Internal Clock Frequency

Parameter, Table 1 ............................................................................. 5

Changes to Figure 7 and Figure 8 .................................................. 14

Changes to Table 6 .......................................................................... 17

Changes to Table 9 .......................................................................... 18

Changes to Table 12, Table 13, and Table 14 ............................... 19

Changes to Table 19 ........................................................................ 24

Changes to Table 22 and Table 23 ................................................. 27

Changes to Offset Register and Full-Scale Register Sections .... 29

Changes to Reference Section ....................................................... 31

Changes to Data Output Coding Section .................................... 32

Changes to Sinc Changes to Sinc Changes to 50 Hz/60 Hz Rejection, Sinc

4

50 Hz/60 Hz Rejection Section ....................... 41

3

50 Hz/60 Hz Rejection Section ....................... 43

4

Filter Section ............ 47

Changes to Summary of Filter Options Section and Table 35 .. 52

7/09—Revision 0: Initial Version

Rev. C | Page 3 of 56

AD7193 Data Sheet

ADC Output Data Rate

4.7 4800

Hz

Chop disabled

1.17 1200

Hz

Chop enabled, sinc4 filter

Gain = 128, before full-scale calibration

@ 50 Hz2

115

dB

Fast settling, FS[9:0]3 = 6, average by 16,

@ 60 Hz2

115

dB

Fast settling, FS[9:0]3 = 5, average by 16,

SPECIFICATIONS

AVDD = 3 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V; REFINx(+) = 2.5 V or AVDD, REFINx(−) = AGND, MCLK = 4.92 MHz, T

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments1

1.56 1600 Hz Chop enabled, sinc3 filter No Missing Codes2 24 Bits FS[9:0]3 > 1, sinc4 filter 24 Bits FS[9:0]3 > 4, sinc3 filter Resolution See the RMS Noise and Resolution section RMS Noise and Output

Data Rates

Integral Nonlinearity

Gain = 12 ±2 ±10 ppm of FSR AVDD = 5 V ±2 ±15 ppm of FSR AVDD = 3 V

Gain > 1 ±5 ±30 ppm of FSR AVDD = 5 V ±15 ±30 ppm of FSR AVDD = 3 V Offset Error ±1 µV Chop enabled, AVDD = 5 V ±0.5 µV Chop enabled, AVDD = 3 V Offset Error Drift vs.

±5 nV/°C Gain = 32 to 128; chop disabled ±5 nV/°C Chop enabled

Offset Error Drift vs. Time 25

Gain Error4 ±0.001 %

−0.39 %

±0.003 %

±0.005 %

Gain Drift vs.

Gain Drift vs. Time 10

Power Supply Rejection 90 dB Gain = 1, VIN = 1 V 95 110 dB Gain > 1, VIN = 1 V/gain Common-Mode Rejection

4, 5

±150/gain µV Chop disabled

Temperature

@ DC 110 dB Gain = 1, VIN = 1 V

@ DC 105 dB Gain > 1, VIN = 1 V/gain

@ 50 Hz, 60 Hz2 120 dB

@ 50 Hz2 120 dB 50 Hz output data rate, 50 Hz ± 1 Hz

@ 60 Hz2 120 dB 60 Hz output data rate, 60 Hz ± 1 Hz

= T

A

to T

MIN

See the RMS Noise and Resolution section

±150/gain nV/°C Gain = 1 to 16; chop disabled

±1 ppm/°C

, unless otherwise noted.

MAX

nV/1000 hours

ppm/ 1000 hours

Gain > 32

AV

= 5 V, gain = 1, TA = 25°C

DD

(factory calibration conditions)

(see Table 27) Gain > 1, after internal full-scale calibration,

AV

≥ 4.75 V

DD

Gain > 1, after internal full-scale calibration, AV

< 4.75 V

DD

Gain = 1

10 Hz output data rate, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz

50 Hz ± 1 Hz

60 Hz ± 1 Hz

Rev. C | Page 4 of 56

Data Sheet AD7193

6

Internal Clock

60

dB

50 Hz output data rate, REJ606 = 1,

@ 60 Hz

40

dB

FS[9:0]3 = 5, average by 16, 60 Hz ± 0.5 Hz

−3 +3

nA

Gain > 1

Unbuffered Mode

Gain = 1, input current varies with input

Parameter Min Typ Max Unit Test Conditions/Comments1

Normal-Mode Rejection2

Sinc4 Filter

Internal Clock

@ 50 Hz, 60 Hz 100 dB

74 dB

@ 50 Hz 96 dB 50 Hz output data rate, 50 Hz ± 1 Hz @ 60 Hz 97 dB 60 Hz output data rate, 60 Hz ± 1 Hz

External Clock

@ 50 Hz, 60 Hz 120 dB

82 dB

@ 50 Hz 120 dB 50 Hz output data rate, 50 Hz ± 1 Hz @ 60 Hz 120 dB 60 Hz output data rate, 60 Hz ± 1 Hz

Sinc3 Filter

10 Hz output data rate, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz

50 Hz output data rate, REJ60

= 1,

50 Hz ± 1 Hz, 60 Hz ± 1 Hz

10 Hz output data rate, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz

50 Hz output data rate, REJ60

6

= 1,

50 Hz ± 1 Hz, 60 Hz ± 1 Hz

@ 50 Hz, 60 Hz 75 dB

10 Hz output data rate, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz

50 Hz ± 1 Hz, 60 Hz ± 1 Hz @ 50 Hz 70 dB 50 Hz output data rate, 50 Hz ± 1 Hz @ 60 Hz 70 dB 60 Hz output data rate, 60 Hz ± 1 Hz

External Clock

@ 50 Hz, 60 Hz 100 dB

10 Hz output data rate, 50 Hz ± 1 Hz,

60 Hz ± 1 Hz @ 50 Hz 67 dB

50 Hz output data rate, REJ606 = 1,

50 Hz ± 1 Hz, 60 Hz ± 1 Hz @ 50 Hz 95 dB 50 Hz output data rate, 50 Hz ± 1 Hz @ 60 Hz 95 dB 60 Hz output data rate, 60 Hz ± 1 Hz

Fast Settling

Internal Clock

@ 50 Hz 26 dB FS[9:0]3 = 6, average by 16, 50 Hz ± 0.5 Hz @ 60 Hz 26 dB FS[9:0]3 = 5, average by 16, 60 Hz ± 0.5 Hz

External Clock

@ 50 Hz 40 dB FS[9:0]3 = 6, average by 16, 50 Hz ± 0.5 Hz

ANALOG INPUTS

Differential Input

±V

/gain V V

REF

Voltage Ranges

−(AVDD − 1.25 V)/gain +(AVDD − 1.25 V)/gain V Gain > 1 Absolute AIN Voltage

2

Limits Unbuffered Mode AGND − 0.05 AVDD + 0.05 V Buffered Mode AGND + 0.25 AVDD − 0.25 V

Analog Input Current

Buffered Mode

Input Current2 −2 +2 nA Gain = 1

= REFINx(+) − REFINx(−), gain = 1 to 128

REF

Input Current Drift ±5 pA/°C

Input Current ±3.5 µA/V

±1 µA/V Gain > 1 Input Current Drift ±0.05 nA/V/°C External clock

±1.6 nA/V/°C Internal clock

voltage

Rev. C | Page 5 of 56

AD7193 Data Sheet

REFIN = REFINx(+) − REFINx(−), the BRIDGE POWER-DOWN

2

Parameter Min Typ Max Unit Test Conditions/Comments1

REFERENCE INPUT

REFIN Voltage 1 AVDD V

Absolute REFIN Voltage

2

Limits

Average Reference Input

Current

Average Reference Input

Current Drift ±1.3 nA/V/°C Internal clock Normal Mode Rejection2

Common-Mode

Rejection Reference Detect Levels 0.3 0.6 V

TEMPERATURE SENSOR

Accuracy ±2 °C Applies after user calibration at 25°C Sensitivity 2815 Codes/°C Bipolar mode

SWITCH RON 10 Ω Allowable Current2 30 mA Continuous current

BURNOUT CURRENTS

AIN Current 500 nA

DIGITAL OUTPUTS (P0 to P3)

Output High Voltage, VOH AVDD − 0.6 V AVDD = 3 V, I 4 V AVDD = 5 V, I Output Low Voltage, VOL 0.4 V AVDD = 3 V, I

0.4 V AVDD = 5 V, I Floating-State Leakage

Floating-State Output

INTERNAL/EXTERNAL CLOCK

Internal Clock

External Clock/Crystal

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V Hysteresis2 0.1 0.25 V Input Currents −10 +10 µA

LOGIC OUTPUT (DOUT/

Output High Voltage, V 4 V DVDD = 5 V, I Output Low Voltage, V

0.4 V DVDD = 5 V, I Floating-State Leakage

Floating-State Output

Data Output Coding Offset binary

2

Current

Capacitance

Frequency 4.72 4.92 5.12 MHz

Duty Cycle 50:50 %

Frequency 2.4576 4.9152 5.12 MHz

Input Low Voltage, V

0.4 V DVDD = 3 V

Input High Voltage, V

3.5 V DVDD = 5 V

Input Current −10 +10 µA

RDY

Current

Capacitance

differential input must be limited to ±(AV

AGND − 0.05 AV

+ 0.05 V

DD

4.5 µA/V

±0.03 nA/V/°C External clock

Same as for analog inputs

100 dB

Analog inputs must be buffered and chop disabled

−100 +100 nA

10 pF

0.8 V DVDD = 5 V

INL

2.5 V DVDD = 3 V

INH

2 V

INH

0.8 V

INL

)

DVDD − 0.6 V DVDD = 3 V, I

OH

0.4 V DVDD = 3 V, I

OL

−10 +10 µA

10 pF

Rev. C | Page 6 of 56

− 1.25 V)/gain when gain > 1

DD

= 100 μA

SOUR CE

= 200 μA

SOUR CE

= 100 μA

SINK

= 800 μA

SINK

= 100 µA

SOURCE

= 200 µA

SOURCE

= 100 µA

SINK

= 1.6 mA

SINK

Data Sheet AD7193

DVDD − DGND

2.7 5.25

V

Power Supply Currents

Parameter Min Typ Max Unit Test Conditions/Comments1

SYSTEM CALIBRATION2

Full-Scale Calibration Limit 1.05 × FS V Zero-Scale Calibration

Limit

Input Span 0.8 × FS 2.1 × FS V

POWER REQUIREMENTS7

Power Supply Voltage AVDD − AGND 3 5.25 V

AIDD Current 0.85 1 mA Gain = 1, buffer off 1 1.25 mA Gain = 1, buffer on

2.8 3.6 mA Gain = 8, buffer off

3.2 3.9 mA Gain = 8, buffer on

3.8 4.7 mA Gain = 16 to 128, buffer off

4.3 5.3 mA Gain = 16 to 128, buffer on DIDD Current 0.35 0.4 mA DVDD = 3 V

0.5 0.6 mA DVDD = 5 V

1.5 mA External crystal used IDD 3 µA Power-down mode

1

Temperature range: −40°C to +105°C.

2

Specification is not production tested but is supported by characterization data at initial product release.

3

FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register.

4

Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed gain and output data rate selected. A system full-

scale calibration reduces the gain error to the order of the noise for the programmed gain and output data rate.

5

The analog inputs are configured for differential mode.

6

REJ60 is a bit in the mode register. When the first notch of the sinc filter is at 50 Hz, a notch is placed at 60 Hz when REJ60 is set to 1. This gives simultaneous

50 Hz/60 Hz rejection.

7

Digital inputs equal to DVDD or DGND.

−1.05 × FS V

Rev. C | Page 7 of 56

AD7193 Data Sheet

t7

10

ns min

SCLK inactive edge to DOUT/

high

t9

30

ns min

Data valid to SCLK edge setup time

I

SINK

(1.6mA WIT H DVDD = 5V,

100µA WITH DV

DD

= 3V)

I

SOURCE

(200µA WIT H DVDD = 5V,

100µA WITH DV

DD

= 3V)

1.6V

TO

OUTPUT

50pF

08367-002

TIMING CHARACTERISTICS

AVDD = 3 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted.

Table 2.

Parameter Limit at T

MIN

, T

(B Version) Unit Conditions/Comments

MAX

1, 2

READ AND WRITE OPERATIONS

t3 100 ns min SCLK high pulse width t4 100 ns min SCLK low pulse width

READ OPERATION

t1 0 ns min

falling edge to DOUT/

CS

active time

RDY 60 ns max DVDD = 4.75 V to 5.25 V 80 ns max DVDD = 2.7 V to 3.6 V

3

t

0 ns min SCLK active edge to data valid delay4

2

60 ns max DVDD = 4.75 V to 5.25 V 80 ns max DVDD = 2.7 V to 3.6 V

5, 6

t

10 ns min Bus relinquish time after CS inactive edge

5

80 ns max t6 0 ns min SCLK inactive edge to CS inactive edge

RDY

WRITE OPERATION

t8 0 ns min

falling edge to SCLK active edge setup time4

CS

t10 25 ns min Data valid to SCLK edge hold time t11 0 ns min

1

Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.

2

See Figure 3 and Figure 4.

3

These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.

4

The SCLK active edge is the falling edge of SCLK.

5

These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number

is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.

6

RDY

returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the digital word can be read only once.

rising edge to SCLK edge hold time

CS

RDY

Circuit and Timing Diagrams

Figure 2. Load Circuit for Timing Characterization

Rev. C | Page 8 of 56

Data Sheet AD7193

t

2

t

3

t

4

t

1

t

6

t

5

t

7

CS (I)

DOUT/RDY ( O)

SCLK (I)

I = INPUT, O = OUTPUT

MSB LSB

08367-003

I = INPUT, O = OUTPUT

CS (I)

SCLK (I)

DIN (I)

MSB LSB

t

8

t

9

t

10

t

11

08367-004

Figure 3. Read Cycle Timing Diagram

Figure 4. Write Cycle Timing Diagram

Rev. C | Page 9 of 56

AD7193 Data Sheet

Digital Input Voltage to DGND

−0.3 V to DVDD + 0.3 V

Digital Output Voltage to DGND

−0.3 V to DVDD + 0.3 V

32-Lead LFCSP

32.5

32.71

°C/W

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

AVDD to AGND −0.3 V to +6.5 V DVDD to AGND −0.3 V to +6.5 V AGND to DGND −0.3 V to +0.3 V Analog Input Voltage to AGND −0.3 V to AVDD + 0.3 V Reference Input Voltage to AGND −0.3 V to AVDD + 0.3 V

AINx/Digital Input Current 10 mA Operating Temperature Range −40°C to +105°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature 150°C Lead Temperature, Soldering Reflow 260°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for the surface-mount packages.

Table 4. Thermal Resistance

Package Type θJA θJC Unit

28-Lead TSSOP 97.9 14 °C/W

ESD CAUTION

Rev. C | Page 10 of 56

Data Sheet AD7193

NC = NO CONNECT

1 2 3 4 5 6 7 8

9 10 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

MCLK2

SCLK

CS

P1/REFIN2(+)

P2

P3

MCLK1

DOUT/RDY SYNC DV

DD

AGND

DGND

AV

DD

P0/REFIN2(–)

NC

AINCOM

AIN4

AIN2

AIN1

BPDSW REFIN1(–) REFIN1(+)

AIN5

AIN3

AIN6

AIN7

AIN8

DIN

AD7193

TO

P VIEW

(Not to S cale)

08367-005

12

AIN2

Analog Input. This pin can be configured as the negative input of a fully differential input pair when used

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 5. 28-lead TSSOP Pin Configuration

Table 5. 28-lead TSSOP Pin Function Descriptions

Pin No. Mnemonic Description

1 MCLK1 When the master clock for the device is provided externally by a crystal, the crystal is connected between

MCLK1 and MCLK2.

2 MCLK2 Master Clock Signal for the Device. The AD7193 has an internal 4.92 MHz clock. This internal clock can be

made available on the MCLK2 pin. The clock for the AD7193 can also be provided externally in the form of a crystal or external clock. A crystal can be tied across the MCLK1 and MCLK2 pins. Alternatively, the MCLK2 pin can be driven with a CMOS-compatible clock and with the MCLK1 pin remaining unconnected.

3 SCLK Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitt-

triggered input, making the interface suitable for opto-isolated applications. The serial clock can be continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information transmitted to or from the ADC in smaller batches of data.

4

Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in

CS

systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the device.

can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and

CS

DOUT used to interface with the device.

5 P3 Digital Output Pin. This pin can function as a general-purpose output bit referenced between AVDD and

AGND.

6 P2 Digital Output Pin. This pin can function as a general-purpose output bit referenced between AVDD and

AGND.

7 P1/REFIN2(+) Digital Output Pin/Positive Reference Input. This pin functions as a general-purpose output bit referenced

between AV

and AGND. When the REFSEL bit in the configuration register = 1, this pin functions as

DD

REFIN2(+). An external reference can be applied between REFIN2(+) and REFIN2(−). REFIN2(+) can lie anywhere between AV the part functions with a reference from 1 V to AV

and AGND + 1 V. The nominal reference voltage, (REFIN2(+) − REFIN2(−)), is AVDD, but

DD

.

DD

8 P0/REFIN2(−) Digital Output Pin/Negative Reference Input. This pin functions as a general-purpose output bit referenced

between AVDD and AGND. When the REFSEL bit in the configuration register = 1, this pin functions as

REFIN2(−). This reference input can lie anywhere between AGND and AV 9 NC No Connect. Tie this pin to AGND. 10 AINCOM Analog Input AIN1 to Analog Input AIN8 are referenced to this input when configured for pseudo differential

11 AIN1 Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with

13 AIN3 Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with

operation.

AIN2 or as a pseudo differential input when used with AINCOM.

with AIN1 or as a pseudo differential input when used with AINCOM.

AIN4 or as a pseudo differential input when used with AINCOM.

Rev. C | Page 11 of 56

− 1 V.

DD

AD7193 Data Sheet

Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with

16

AIN6

Analog Input. This pin can be configured as the negative input of a fully differential input pair when used

Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with 22

AGND

Analog Ground Reference Point.

26

Logic input that allows for synchronization of the digital filters and analog modulators when using a number

Pin No. Mnemonic Description

14 AIN4 Analog Input. This pin can be configured as the negative input of a fully differential input pair when used

with AIN3 or as a pseudo differential input when used with AINCOM.

15 AIN5

AIN6 or as a pseudo differential input when used with AINCOM.

with AIN5 or as a pseudo differential input when used with AINCOM.

17 AIN7

AIN8 or as a pseudo differential input when used with AINCOM.

18 AIN8 Analog Input. This pin can be configured as the negative input of a fully differential input pair when used

with AIN7 or as a pseudo differential input when used with AINCOM.

19 REFIN1(+) Positive Reference Input. An external reference can be applied between REFIN1(+) and REFIN1(−). REFIN1(+)

can lie anywhere between AVDD and AGND + 1 V. The nominal reference voltage, (REFIN1(+) − REFIN1(−)), is AV

, but the part functions with a reference from 1 V to AVDD.

DD

20 REFIN1(−) Negative Reference Input. This reference input can lie anywhere between AGND and AVDD − 1 V. 21 BPDSW Bridge Power-Down Switch to AGND.

23 DGND Digital Ground Reference Point. 24 AVDD Analog Supply Voltage, 3 V to 5.25 V. AVDD is independent of DVDD. Therefore, DVDD can be operated at 3 V with

AV

at 5 V or vice versa.

DD

25 DVDD Digital Supply Voltage, 2.7 V to 5.25 V. DVDD is independent of AVDD. Therefore, AVDD can be operated at 3 V

with DV

SYNC

of AD7193 devices. While control logic are reset, and the analog modulator is also held in its reset state. interface but does reset

27 DOUT/

Serial Data Output/Data Ready Output. DOUT/

RDY

pin to access the output shift register of the ADC. The output shift register can contain data from any of the on-chip data or control registers. In addition, DOUT/ the completion of a conversion. If the data is not read after the conversion, the pin goes high before the next update occurs. The DOUT/ data is available. With an external serial clock, the data can be read using the DOUT/ data-/control-word information is placed on the DOUT/ SCLK rising edge.

28 DIN Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control

registers in the ADC, with the register selection bits of the communications register identifying the appropriate register.

at 5 V or vice versa.

DD

is low, the nodes of the digital filter, the filter control logic, and the calibration

SYNC

does not affect the digital

SYNC

to a high state if it is low.

RDY

serves a dual purpose. It functions as a serial data output

RDY

falling edge can be used as an interrupt to a processor, indicating that valid

RDY

has a pull-up resistor internally to DVDD.

SYNC

operates as a data ready pin, going low to indicate

RDY

pin. With CS low, the

RDY

pin on the SCLK falling edge and is valid on the

RDY

Rev. C | Page 12 of 56

Data Sheet AD7193

08367-065

NOTES

1. NC = NO CONNECT.

2. CONNECT EXPOSED PAD TO AGND.

24

DV

DD

23

AV

DD

22

DGND

21

AGND

20

BPDSW

19

NC

18

REFIN1(–)

17

REFIN1(+)

1 2 3 4 5 6 7 8

P3

P2 P1/REFIN2(+) P0/REFIN2(–)

NC NC NC

AINCOM

9

10111213141516

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

AIN8

32313029282726

25

CS

SCLK

MCLK2

MCLK1

DIN

DOUT/RDY

NC

SYNC

TOP VIEW

(Not to S cale)

AD7193

4

P0/REFIN2(−)

Digital Output Pin/Negative Reference Input. This pin functions as a general-purpose output bit referenced Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with

Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with

14

AIN6

Analog Input. This pin can be configured as the negative input of a fully differential input pair when used

Figure 6. 32-Lead LFCSP Pin Configuration

Table 6. 32-Lead LFCSP Pin Function Descriptions

Pin No. Mnemonic Description

1 P3 Digital Output Pin. This pin can function as a general-purpose output bit referenced between AVDD and

AGND.

2 P2 Digital Output Pin. This pin can function as a general-purpose output bit referenced between AVDD and

AGND.

3 P1/REFIN2(+) Digital Output Pin/Positive Reference Input. This pin functions as a general-purpose output bit referenced

between AVDD and AGND. When the REFSEL bit in the configuration register = 1, this pin functions as REFIN2(+). An external reference can be applied between REFIN2(+) and REFIN2(−). REFIN2(+) can lie anywhere between AV the part functions with a reference from 1 V to AV

and AGND + 1 V. The nominal reference voltage, (REFIN2(+) − REFIN2(−)), is AVDD, but

DD

.

DD

between AVDD and AGND. When the REFSEL bit in the configuration register = 1, this pin functions as

− 1 V.

DD

5, 6, 7, 19,

REFIN2(−). This reference input can lie anywhere between AGND and AV

NC No Connect. Tie these pins to AGND.

26 8 AINCOM Analog Input AIN1 to Analog Input AIN8 are referenced to this input when configured for pseudo differential

operation.

9 AIN1

AIN2 or as a pseudo differential input when used with AINCOM.

10 AIN2 Analog Input. This pin can be configured as the negative input of a fully differential input pair when used

with AIN1 or as a pseudo differential input when used with AINCOM.

11 AIN3 Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with

AIN4 or as a pseudo differential input when used with AINCOM.

12 AIN4 Analog Input. This pin can be configured as the negative input of a fully differential input pair when used

with AIN3 or as a pseudo differential input when used with AINCOM.

13 AIN5

AIN6 or as a pseudo differential input when used with AINCOM.

with AIN5 or as a pseudo differential input when used with AINCOM.

15 AIN7 Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with

16 AIN8 Analog Input. This pin can be configured as the negative input of a fully differential input pair when used

17 REFIN1(+) Positive Reference Input. An external reference can be applied between REFIN1(+) and REFIN1(−). REFIN1(+)

18 REFIN1(−) Negative Reference Input. This reference input can lie anywhere between AGND and AVDD − 1 V. 20 BPDSW Bridge Power-Down Switch to AGND.

AIN8 or as a pseudo differential input when used with AINCOM.

with AIN7 or as a pseudo differential input when used with AINCOM.

can lie anywhere between AVDD and AGND + 1 V. The nominal reference voltage, (REFIN1(+) − REFIN1(−)), is

, but the part functions with a reference from 1 V to AVDD.

AV

DD

Rev. C | Page 13 of 56

AD7193 Data Sheet

is low, the nodes of the digital filter, the filter control logic, and the calibration

Pin No. Mnemonic Description

21 AGND Analog Ground Reference Point. 22 DGND Digital Ground Reference Point. 23 AVDD Analog Supply Voltage, 3 V to 5.25 V. AVDD is independent of DVDD. Therefore, DVDD can be operated at 3 V with

AV

at 5 V or vice versa.

DD

24 DVDD Digital Supply Voltage, 2.7 V to 5.25 V. DVDD is independent of AVDD. Therefore, AVDD can be operated at 3 V

with DV

25

Logic input that allows for synchronization of the digital filters and analog modulators when using a number

SYNC

of AD7193 devices. While control logic are reset, and the analog modulator is also held in its reset state. interface but does reset

27 DOUT/

Serial Data Output/Data Ready Output. DOUT/

RDY

pin to access the output shift register of the ADC. The output shift register can contain data from any of the on-chip data or control registers. In addition, DOUT/ the completion of a conversion. If the data is not read after the conversion, the pin goes high before the next update occurs. The DOUT/ data is available. With an external serial clock, the data can be read using the DOUT/ data-/control-word information is placed on the DOUT/ SCLK rising edge.

28 DIN Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control

registers in the ADC, with the register selection bits of the communications register identifying the appropriate register.

29 MCLK1 When the master clock for the device is provided externally by a crystal, the crystal is connected between

MCLK1 and MCLK2.

30 MCLK2 Master Clock Signal for the Device. The AD7193 has an internal 4.92 MHz clock. This internal clock can be

made available on the MCLK2 pin. The clock for the AD7193 can also be provided externally in the form of a crystal or external clock. A crystal can be tied across the MCLK1 and MCLK2 pins. Alternatively, the MCLK2 pin can be driven with a CMOS-compatible clock and with the MCLK1 pin remaining unconnected.

31 SCLK Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitt-

triggered input, making the interface suitable for opto-isolated applications. The serial clock can be continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information transmitted to or from the ADC in smaller batches of data.

32

Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in

CS

systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the device. DOUT used to interface with the device.

EPAD The exposed pad must be connected to AGND.

at 5 V or vice versa.

DD

can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and

CS

SYNC

does not affect the digital

SYNC

to a high state if it is low.

RDY

serves a dual purpose. It functions as a serial data output

RDY

falling edge can be used as an interrupt to a processor, indicating that valid

RDY

has a pull-up resistor internally to DVDD.

SYNC

operates as a data ready pin, going low to indicate

RDY

pin. With CS low, the

RDY

pin on the SCLK falling edge and is valid on the

RDY

Rev. C | Page 14 of 56

Data Sheet AD7193

08367-006

0 200 400 600 800 1000

SAMPLE

CODE

8,387,468

8,387,470

8,387,472

8,387,474

8,387,476

8,387,478

8,387,480

8,387,482

8,387,484

8,387,486

08367-007

0

50

100

150

200

8,387,470

8,387,472

8,387,474

8,387,476

8,387,478

8,387,480

8,387,482

8,387,484

CODE

OCCURRENCE

08367-008

8,388,830

8,388,840

8,388,850

8,388,860

8,388,870

8,388,880

8,388,890

8,388,900

8,388,910

8,388,920

0 200 400 600 800 1000

SAMPLE

CODE

08367-009

0

10

20

30

40

50

8,388,830 8,388,860 8,388,890 8,388,920

CODE

OCCURRENCE

08367-010

8,388,864

8,388,866

8,388,868

8,388,870

8,388,872

8,388,874

8,388,876

8,388,878

8,388,880

0 200 400 600 800 1000

SAMPLE

CODE

08367-011

0

50

100

150

200

8,388,864 8,388,868 8,388,872 8,388,876 8,388,880

CODE

OCCURRENCE

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 7. Noise (V

Figure 8. Noise Distribution Histogram (V

= AVDD = 5 V, Output Data Rate = 4.7 Hz,

REF

Gain = 128, Chop Disabled, Sinc

4

Filter)

= AVDD = 5 V,

REF

Output Data Rate = 4.7 Hz, Gain = 128, Chop Disabled, Sinc

4

Filter)

Figure 10. Noise Distribution Histogram (V

REF

Output Data Rate = 2400 Hz, Gain = 1, Chop Disabled, Sinc

Figure 11. Noise (V

= AVDD = 5 V, Output Data Rate = 42.1 Hz (FS[9:0] = 6,

REF

Average by 16), Gain = 1, Chop Disabled, Sinc

= AVDD = 5 V,

4

Filter)

4

Filter)

Figure 9. Noise (V

= AVDD = 5 V, Output Data Rate = 2400 Hz,

REF

Gain = 1, Chop Disabled, Sinc

4

Filter)

Figure 12. Noise Distr ibution Histogram (V

= AVDD = 5 V, Output Data Rate =

REF

42.1 Hz (FS[9:0] = 6, Average by 16), Gain = 1, Chop Disabled, Sinc

4

Filter)

Rev. C | Page 15 of 56

AD7193 Data Sheet

5

–2

–1

0

1

2

3

4

–4 –3 –2 –1 0 1 2 3 4

INL (ppm of FSR)

VIN (V)

08367-012

20

–20

–15

–10

–5

0

5

10

15

–0.03 –0.02 –0.01 0 0.01 0.02 0.03

INL (ppm of FSR)

V

IN

(V)

08367-013

170

168

166

164

162

160

156

158

154

–60 –40 –20 0 20 40 60 80 100 120

OFFSET (µV)

TEMPERATURE (°C)

08367-014

0.4

–1.4

–1.2

–1.0

–0.8

–0.6

–0.4

–0.2

0

0.2

–60 –40 –20 0 20 40 60 80 100

120

OFFSET (µV)

TEMPERATURE (°C)

08367-015

–60 –40 –20 0 20 40 60 80 100 120

GAIN

TEMPERATURE (°C)

08367-016

0.999988

0.999990

0.999992

0.999994

0.999996

0.999998

1.000000

1.000002

1.000004

1.000006

1.000008

–60 –40 –20 0 20 40 60 80 100 120

GAIN

TEMPERATURE (°C)

08367-017

127.988

127.990

127.992

127.994

127.996

127.998

128.000

128.002

128.004

Figure 13. INL (Gain = 1)

Figure 14. INL (Gain = 128)

Figure 16. Offset vs. Temperature (Gain = 128, Chop Disabled)

Figure 17. Gain vs. Temperature (Gain = 1)

Figure 15. Offset vs. Temperature (Gain = 1, Chop Disabled)

Figure 18. Gain vs. Temperature (Gain = 128)

Rev. C | Page 16 of 56

Data Sheet AD7193

08367-018

14

16

18

20

22

24

1 10

100

OUTPUT DATA RAT E (Hz)

1k 10k

NOISE FREE RESOLUTION (Bits)

GAIN = 1 GAIN = 8 GAIN = 16 GAIN = 32

GAIN = 64 GAIN = 128

08367-019

10

12

14

16

18

20

22

24

1 10 100 1k 10k

OUTPUT DATA RAT E (Hz)

NOISE FREE RESOLUTION (Bits)

GAIN = 1 GAIN = 8 GAIN = 16 GAIN = 32 GAIN = 64 GAIN = 128

08367-022

16

17

18

19

20

22

21

23

1 10 100 1k

OUTPUT DATA RAT E (Hz)

NOISE FREE RESOLUTION (Bits)

GAIN = 1 GAIN = 8 GAIN = 16 GAIN = 32 GAIN = 64 GAIN = 128

Figure 19. Noise Free Resolution (Sinc4 Filter, Chop Disabled, V

Figure 20. Noise Free Resolution (Sinc3 Filter, Chop Disabled, V

REF

= 5 V)

Figure 21. Noise Free Resolution in Fast Settling Mode

(V

= 5 V, Averaging by 16, Sinc4 Filter, Chop Disabled)

REF

Rev. C | Page 17 of 56

ANALOG DEVICES AD7193 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TIMING CHARACTERISTICS

Circuit and Timing Diagrams

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS