ANALOG DEVICES AD7151 Service Manual

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Ultra-Low Power, 1-Channel, Capacitance

FEATURES

Ultra-low power

2.7 V to 3.6 V, 70 μA
Response time: 10 ms
Adaptive environmental compensation
1 capacitance input channel

Sensor capacitance (C

Sensitivity to 1 fF
EMC tested
2 modes of operation

Standalone with fixed settings

Interfaced to a microcontroller for user-defined settings
Proximity detection output flag
2-wire serial interface (I
Operating temperature

−40°C to +85°C

10-lead MSOP package

APPLICATIONS

Proximity sensing
Contactless switching
Position detection
Level detection

) 0 pF up to 13 pF

SENS

2

C compatible)

Converter for Proximity Sensing

AD7151

GENERAL DESCRIPTION

The AD7151 delivers a complete signal processing solution for
capacitive proximity sensors, featuring an ultra-low power
converter with fast response time. The AD7150 is a 2-channel
alternative to the AD7151.

The AD7151 uses Analog Devices, Inc., capacitance-to-digital
converter (CDC) technology, which combines features
important for interfacing to real sensors, such as high input
sensitivity and high tolerance of both input parasitic ground
capacitance and leakage current.

The integrated adaptive threshold algorithm compensates for
any variations in the sensor capacitance due to environmental
factors like humidity and temperature or due to changes in the
dielectric material over time.

By default, the AD7151 operates in standalone mode using the
fixed power-up settings and indicates detection on a digital
output. Alternatively, the AD7151 can be interfaced to a
microcontroller via the serial interface, the internal registers can
be programmed with user-defined settings, and the data and
status can be read from the part.

The AD7151 operates with a 2.7 V to 3.6 V power supply. It is
specified over the temperature range of −40°C to +85°C.

FUNCTIONAL BLOCK DIAGRAM

CIN

C

SENS

EXC

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of p atents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

Σ-Δ CDC

EXCITATION

VDD

AD7151

DIGITAL

FILTER

THRESHOLD

GND

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2007 Analog Devices, Inc. All rights reserved.

SERIAL

INTERFACE

SCL

SDA

OUT

07086-001

AD7151

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Specifications .................................................................. 4

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics ............................................. 7

Architecture and Main Features................................................... 10

Capacitance-to-Digital Converter............................................ 10

CAPDAC ..................................................................................... 10

Comparator and Threshold Modes.......................................... 11

Adaptive Threshold.................................................................... 11

Data Average ............................................................................... 11

Sensitivity..................................................................................... 12

Hysteresis..................................................................................... 12

Timeout........................................................................................ 12

AutoCAPDAC Adjustment....................................................... 13

Power-Down Timer ................................................................... 13

Power Supply Monitor ............................................................... 13

Register Descriptions ..................................................................... 14

Status Register............................................................................. 15

Data Register............................................................................... 16

Average Register ......................................................................... 16

Fixed Threshold Register........................................................... 16

Sensitivity Register ..................................................................... 16

Timeout Register........................................................................ 17

Setup Register ............................................................................. 18

Configuration Register .............................................................. 19

Power-Down Timer Register.................................................... 20

CAPDAC Register...................................................................... 20

Serial Number Register.............................................................. 20

Chip ID Register......................................................................... 20

Serial Interface ................................................................................ 21

Read Operation........................................................................... 21

Write Operation.......................................................................... 21

AD7151 Reset ............................................................................. 22

General Call ................................................................................ 22

Hardware Design Considerations ................................................ 23

Overview ..................................................................................... 23

Parasitic Capacitance to Ground.............................................. 23

Parasitic Resistance to Ground................................................. 23

Parasitic Parallel Resistance ...................................................... 23

Parasitic Serial Resistance ......................................................... 24

Input Overvoltage Protection................................................... 24

Input EMC Protection ............................................................... 24

Power Supply Decoupling and Filtering.................................. 24

Application Examples ................................................................ 25

Outline Dimensions....................................................................... 26

Ordering Guide .......................................................................... 26

REVISION HISTORY

11/07—Revision 0: Initial Version

Rev. 0 | Page 2 of 28

AD7151

SPECIFICATIONS

VDD = 2.7 V to 3.6 V; GND = 0 V; –40°C to +85°C, single-ended capacitance mode, unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit

1

Test Conditions/Comments

CAPACITIVE INPUT

Conversion Input Range CIN to EXC23.2 4 pF 4 pF input range

1.6 2 pF 2 pF input range

0.8 1 pF 1 pF input range

0.4 0.5 pF 0.5 pF input range
Resolution3 2.0 fF 4 pF input range

1.6 fF 2 pF input range

1.4 fF 1 pF input range

1.0 fF 0.5 pF input range
Allowed Capacitance CIN to GND3 150 pF
Allowed Resistance CIN to GND
Allowed Serial Resistance

3

3

15 MΩ

200 kΩ
Gain Error −20 +20 %
Gain Deviation over Temperature
Gain Matching Between Ranges
Offset Error

3

3

0.5 %

3

−2 +2 %

50 fF CIN and EXC pins disconnected
Offset Deviation over Temperature3 5 fF CIN and EXC pins disconnected
Integral Nonlinearity (INL)3 0.1 %
Power Supply Rejection

CAPDAC

2

3

4 fF/V

Full Range 10 12.5 pF
Resolution (LSB)3 200 fF
Differential Nonlinearity (DNL)3 0.25 LSB
AutoDAC Increment/Decrement

3

25 75 % of CIN Range

EXCITATION

Voltage ±VDD/2

V
Frequency 15.4 16 16.3 kHz
Allowed Capacitance EXC to GND
Allowed Resistance EXC to GND

3

3

300 pF
1 MΩ

LOGIC OUTPUT (OUT)

Output Low Voltage (VOL) 0.4 V I
Output High Voltage (VOH) VDD – 0.6 V I

= −4 mA

SINK

SOURCE

= 4 mA

SERIAL INTERFACE INPUTS (SCL, SDA)

Input High Voltage (VIH) 1.5 V
Input Low Voltage (VIL) 0.8 V
Input Leakage Current ±0.1 ±5 μA
Input Pin Capacitance 6 pF

OPEN-DRAIN OUTPUT (SDA)

Output Low Voltage (VOL) 0.4 V

Output High Leakage Current (IOH) 0.1 5 μA V

I

= −6.0 mA

SINK

= VDD

OUT

POWER SUPPLY MONITOR

VDD Threshold Voltage 2.45 2.65 V

Rev. 0 | Page 3 of 28

AD7151

Parameter Min Typ Max Unit

1

Test Conditions/Comments

POWER REQUIREMENTS

VDD-to-GND Voltage 2.7 3.6 V VDD = 3.3 V, nominal
IDD Current
IDD Current Power-Down Mode

4

4

70 80 μA
1 5 μA Temperature ≤ 25°C

3 10 μA Temperature = 85°C

1

Capacitance units: one picofarad (1 pF) = 1 × 10

2

The CAPDAC can be used to shift (offset) the input range. The total capacitance of the sensor can, therefore, be up to the sum of the CAPDAC value and the conversion

−12

farad (F); one femtofarad (1 fF) = 10

−15

farad (F).

input range. With the autoCAPDAC feature, the CAPDAC is adjusted automatically when the CDC input value is lower than 25% or higher than 75% of the CDC
nominal input range.

3

Specification is not production tested but is supported by characterization data at initial product release.

4

Digital inputs equal to VDD or GND.

TIMING SPECIFICATIONS

VDD = 2.7 V to 3.6 V; GND = 0 V; Input Logic 0 = 0 V; Input Logic 1 = VDD; –40°C to +85°C, unless otherwise noted.

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

CONVERTER

Conversion Time 10 ms
Wake-Up Time from Power-Down Mode
Power-Up Time
Reset Time

SERIAL INTERFACE

1, 3

1, 4

5, 6

SCL Frequency 0 400 kHz
SCL High Pulse Width, t
SCL Low Pulse Width, t

0.6 μs

HIGH

1.3 μs

LOW

SCL, SDA Rise Time, tR 0.3 μs
SCL, SDA Fall Time, t
Hold Time (Start Condition), t
Setup Time (Start Condition), t
Data Setup Time, t
Setup Time (Stop Condition), t
Data Hold Time (Master), t

F

HD;STA

SU;STA

0.1 μs

SU;DAT

SU;STO

10 ns

HD;DAT

Bus-Free Time (Between Stop and Start Condition), t

1

Specification is not production tested but is supported by characterization data at initial product release.

2

Wake-up time is the maximum delay between the last SCL edge writing the configuration register and the start of conversion.

3

Power-up time is the maximum delay between the VDD crossing the minimum level (2.7 V) and either the start of conversion or when ready to receive a serial interface

command.

4

Reset time is the maximum delay between the last SCL edge writing the reset command and either the start of conversion or when ready to receive a serial interface

command.

5

Sample tested during initial release to ensure compliance.

6

All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.

Output load = 10 pF.

t

LOW

1, 2

0.3 ms
2 ms
2 ms
See Figure 2.

0.3 μs

0.6 μs After this period, the first clock is generated.

0.6 μs Relevant for repeated start condition.

0.6 μs

1.3 μs

BUF

t

R

t

F

t

HD;STA

SCL

SDA

t

t

BUF

PS

HD;STA

t

HD;DAT

t

HIGH

t

SU;DAT

t

SU;STA

S

t

SU;STO

P

07086-002

Figure 2. Serial Interface Timing Diagram

Rev. 0 | Page 4 of 28

AD7151

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

Positive Supply Voltage VDD to GND

Voltage on Any Input or Output to GND –0.3 V to VDD + 0.3 V
ESD Rating HBM
(ESD Association Human Body Model, S5.1)
ESD Rating FICDM

(Field-Inducted Charged Device Model)
Operating Temperature Range –40°C to +85°C
Storage Temperature Range –65°C to +150°C
Maximum Junction Temperature 150°C
MSOP Package

, Thermal Impedance-to-Air

θ

JA

, Thermal Impedance-to-Case

θ

JC

Reflow Soldering (Pb-Free)

Peak Temperature 260(+0/−5)°C
Time at Peak Temperature 10 sec to 40 sec

−0.3 V to +3.9 V

4 kV

1 kV

206°C/W
44°C/W

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. 0 | Page 5 of 28

AD7151

G

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

ND

VDD

2

AD7151

NC

3

TOP VIEW

(Not to Scale)

4

CIN

NC

5

NC = NO CONNECT

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 GND Ground Pin.
2 VDD

Power Supply Voltage. This pin should be decoupled to GND using a low impedance capacitor, for example,

0.1 μF X7R multilayer ceramic.
3 NC This pin should be left as an open circuit or connected to GND.
4 CIN CDC Capacitive Input. The measured capacitance (sensor) is connected between the EXC pin and the CIN pin.
5 NC This pin should be left as an open circuit.
6 EXC CDC Excitation Output. The measured capacitance is connected between the EXC pin and the CIN pin.
7 OUT Logic Output. High level on this output indicates proximity detected on the capacitive input.
8 NC This pin should be left as an open circuit.
9 SCL

Serial Interface Clock Input. Connects to the master clock line. Requires a pull-up resistor if not provided
elsewhere in the system.

10 SDA

Serial Interface Bidirectional Data. Connects to the master data line. Requires a pull-up resistor if not provided
elsewhere in the system.

10

SDA

SCL

9

NC

8

7

OUT

EXC

6

07086-003

Rev. 0 | Page 6 of 28

AD7151

TYPICAL PERFORMANCE CHARACTERISTICS

300

200

100

OFFSET ERROR (fF)

0

–100

03

CAPACITANCE CIN TO GND (pF)

25020015010050

00

07086-104

Figure 4. Capacitance Input Offset Error vs. Capacitance CIN to GND,

= 3.3 V, EXC Pin Open Circuit

V

DD

2

0

–2

–4

GAIN ERROR (%F S)

–6

0.10

0.05

0

GAIN ERROR (%F S)

–0.05

–0.10

030025020015010050

Figure 7. Capacitance Input Gain Error vs. Capacitance EXC to GND,

200

100

0

OFFSET ERROR (fF)

–100

CAPACITANCE EXC TO GND (pF)

= 3.3 V, CIN to EXC = 2 pF

V

DD

07086-107

–8

03

CAPACITANCE CIN TO GND (pF)

25020015010050

00

07086-105

Figure 5. Capacitance Input Gain Error vs. Capacitance CIN to GND,

V

= 3.3 V, CIN to EXC = 2 pF

DD

2

1

0

OFFSET ERROR (fF)

–1

–2

03

CAPACITANCE EXC TO GND (pF)

25020015010050

00

07086-106

Figure 6. Capacitance Input Offset Error vs. Capacitance EXC to GND,

V

= 3.3 V, CIN Pin Open Circuit

DD

–200

1100010010

Figure 8. Capacitance Input Offset Error vs. Resistance CIN to GND,

10

5

0

GAIN ERROR (%F S)

–5

–10

1100010010

Figure 9. Capacitance Input Gain Error vs. Resistance CIN to GND,

RESISTANCE CI N TO GND (MΩ)

= 3.3 V, EXC Pin Open Circuit

V

DD

RESISTANCE CI N TO GND (MΩ)

= 3.3 V, CIN to EXC = 2 pF

V

DD

07086-108

07086-109

Rev. 0 | Page 7 of 28

AD7151

10

10

5

0

OFFSET ERROR (fF)

–5

–10

01

RESISTANCE EXC TO GND (MΩ)

8642

0

07086-110

Figure 10. Capacitance Input Offset Error vs. Resistance EXC to GND,

= 3.3 V, CIN Pin Open Circuit

V

DD

0.50

0.25

0

GAIN ERROR (%F S)

–0.25

5

0

GAIN ERROR (%F S)

–5

–10

1100010010

Figure 13. Capacitance Input Gain Error vs. Parallel Resistance,

4

2

0

OFFSET ERROR (fF)

–2

PARALLEL RESISTANCE (MΩ)

= 3.3 V, CIN to EXC = 2 pF

V

DD

07086-113

–0.50

01

RESISTANCE EXC TO GND (MΩ)

8642

0

07086-111

Figure 11. Capacitance Input Gain Error vs. Resistance EXC to GND,

= 3.3 V, CIN to EXC = 2 pF

V

DD

2

1

0

GAIN ERROR (%F S)

–1

–2

02

SERIAL RESI STANCE (kΩ)

20015010050

50

07086-112

Figure 12. Capacitance Input Gain Error vs. Serial Resistance

V

= 3.3 V, CIN to EXC = 2 pF

DD

–4

–50 1007550250–25

Figure 14. Capacitance Input Offset Error vs. Temperature,

V

DD

0.2

0.1

0

–0.1

GAIN ERROR (%F S)

–0.2

–0.2

–50 1007550250–25

Figure 15. Capacitance Input Gain Error vs. Temperature,

TEMPERATURE (° C)

= 3.3 V, CIN and EXC Pins Open Circuit

TEMPERATURE (° C)

V

= 3.3 V, CIN to EXC = 2 pF

DD

07086-114

07086-115

Rev. 0 | Page 8 of 28

AD7151

2

0

EXC FREQUENCY ERROR (%)

–1

–2

–1

EXC FREQUENCY ERRO R (%)

1

0

–50 1007550250–25

TEMPERATURE (° C)

Figure 16. EXC Frequency Error vs. Temperature,

= 3.3 V

V

DD

2

1

0

–20

–40

GAIN (dB)

–60

–80

022.01.51.00. 5

07086-116

INPUT S IGNAL FREQ UENCY (kHz)

.5

07086-118

Figure 18. Capacitance to Digital Converter Frequency Response

0.50

0.25

0

CAPDAC DNL (LSB)

–0.25

–2

2.7 3.63.33.0

Figure 17. EXC Frequency Error vs. V

VDD (V)

07086-117

DD

–0.50

06483216

CAPDAC CODE

Figure 19. CAPDAC Differential Nonlinearity (DNL),

= 3.3 V

V

DD

4

07086-119

Rev. 0 | Page 9 of 28