Analog Devices AD678TD, AD678SD, AD678KN, AD678KD, AD678JN Datasheet

12-Bit 200 kSPS

a

FEATURES
AC and DC Characterized and Specified

(K, B and T Grades)
200k Conversions per Second
1 MHz Full Power Bandwidth
500 kHz Full Linear Bandwidth
72 dB S/N+D (K, B, T Grades)
Twos Complement Data Format (Bipolar Mode)
Straight Binary Data Format (Unipolar Mode)
10 M⍀ Input Impedance
8-Bit or 16-Bit Bus Interface
On-Board Reference and Clock
10 V Unipolar or Bipolar Input Range
Commercial, Industrial and Military Temperature

Range Grades
MIL-STD-883 Compliant Versions Available

PRODUCT DESCRIPTION

The AD678 is a complete, multipurpose 12-bit monolithic
analog-to-digital converter, consisting of a sample-hold ampli­fier (SHA), a microprocessor compatible bus interface, a voltage
reference and clock generation circuitry.

The AD678 is specified for ac (or “dynamic”) parameters such
as S/N+D ratio, THD and IMD which are important in signal
processing applications. In addition, the AD678K, B and T
grades are fully specified for dc parameters which are important
in measurement applications.

The AD678 offers a choice of digital interface formats; the 12
data bits can be accessed by a 16-bit bus in a single read opera­tion or by an 8-bit bus in two read operations (8+4), with right
or left justification. Data format is straight binary for unipolar
mode and twos complement binary for bipolar mode. The input
has a full-scale range of 10 V with a full power bandwidth of
1 MHz and a full linear bandwidth of 500 kHz. High input im­pedance (10 MΩ) allows direct connection to unbuffered
sources without signal degradation.

This product is fabricated on Analog Devices’ BiMOS process,
combining low power CMOS logic with high precision, low
noise bipolar circuits; laser-trimmed thin-film resistors provide
high accuracy. The converter utilizes a recursive subranging
algorithm which includes error correction and flash converter
circuitry to achieve high speed and resolution.

The AD678 operates from +5 V and ±12 V supplies and dissipates
560 mW (typ). The AD678 is available in 28-lead plastic DIP,
ceramic DIP, and 44-lead J-leaded ceramic surface mount packages.

Screening to MIL-STD-883C Class B is also available.

*Protected by U.S. Patent Nos. 4,804,960; 4,814,767; 4,833,345; 4,250,445;

4,808,908; RE30,586.

Complete Sampling ADC

AD678*

FUNCTIONAL BLOCK DIAGRAM

12/8

SYNC

CONVERSION

LOGIC

REF

OUT

REF

BIPOFF

AIN

AGND

SC OE EOCEN

CS

VOLTAGE

REF.

IN

SAMPLE/

HOLD

CONTROL LOGIC

12-BIT D/A

CONVERTER

12

GAIN
STAGE

PRODUCT HIGHLIGHTS

1. COMPLETE INTEGRATION: The AD678 minimizes ex­ternal component requirements by combining a high speed
sample-hold amplifier (SHA), ADC, 5 V reference, clock and
digital interface on a single chip. This provides a fully speci­fied sampling A/D function unattainable with discrete designs.

2. SPECIFICATIONS: The AD678K, B and T grades provide
fully specified and tested ac and dc parameters. The AD678J,
A and S grades are specified and tested for ac parameters; dc
accuracy specifications are shown as typicals. DC specifica­tions (such as INL, gain and offset) are important in control
and measurement applications. AC specifications (such as
S/N+D ratio, THD and IMD) are of value in signal process­ing applications.

3. EASE OF USE: The pinout is designed for easy board lay­out, and the choice of single or two read cycle output pro­vides compatibility with 16- or 8-bit buses. Factory trimming
eliminates the need for calibration modes or external trim­ming to achieve rated performance.

4. RELIABILITY: The AD678 utilizes Analog Devices’ mono­lithic BiMOS technology. This ensures long-term reliability
compared to multichip and hybrid designs.

5. UPGRADE PATH: The AD678 provides the same pinout as
the 14-bit, 128 kSPS AD679 ADC.

6. The AD678 is available in versions compliant with MIL­STD-883. Refer to the Analog Devices Military Products
Databook or current AD678/883B data sheet for detailed
specifications.

EOC

12

OUTPUT

REGISTER

4

4-BIT FLASH

A/D

CONVERTER

AD678

DB11

DB2

DB1
(R/L)

DB0
(HBE)

V

CC

V

EE

V

DD

DGND

REV. C

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

AD678–SPECIFICATIONS

(T

to T

, VCC = +12 V ⴞ 5%, VEE = –12 V ⴞ 5%, VDD = +5 V ⴞ 10%, f

MAX

1

AC SPECIFICATIONS

MIN

flN = 10.06 kHz unless otherwise noted)

AD678J/A/S AD678K/B/T

Parameter Min Typ Max Min Typ Max Units

SIGNAL-TO-NOISE AND DISTORTION (S/N+D) RATIO

2

–0.5 dB Input (Referred to –0 dB Input) 70 71 71 73 dB
–20 dB Input (Referred to –20 dB Input) 51 53 dB
–60 dB Input (Referred to –60 dB Input) 11 13 dB

TOTAL HARMONIC DISTORTION (THD)

3

–88 –80 –88 –80 dB

0.004 0.010 0.004 0.010 %

PEAK SPURIOUS OR PEAK HARMONIC COMPONENT –87 –80 –87 –80 dB

FULL POWER BANDWIDTH 1 1 MHz

FULL LINEAR BANDWIDTH 500 500 kHz

INTERMODULATION DISTORTION (IMD)

4

2nd Order Products –85 –80 –85 –80 dB
3rd Order Products –90 –80 –90 –80 dB

NOTES

1

fIN amplitude = –0.5 dB (9.44 V p-p) bipolar mode full scale unless otherwise indicated. All measurements referred to a –0 dB (9.997 V p-p) input signal unless
otherwise indicated.

2

See Figures 13 and 14 for higher frequencies and other input amplitudes.

3

See Figure 12.

4

fA = 9.08 kHz, fB = 9.58 kHz, with f

Specifications subject to change without notice.

= 200 kSPS. See Definition of Specifications section and Figure 16.

SAMPLE

= 200 kSPS,

SAMPLE

DIGITAL SPECIFICATIONS

(All device types T

MIN

to T

, VCC = +12 V ⴞ 5%, VEE = –12 V ⴞ 5%, VDD = +5 V ⴞ 10%)

MAX

Parameter Test Conditions Min Max Units

LOGIC INPUTS
V

IH

V

IL

I

IH

I

IL

C

IN

High Level Input Voltage 2.0 V

DD

Low Level Input Voltage 0 0.8 V
High Level Input Current VIN = V

DD

–10 +10 µA
Low Level Input Current VIN = 0 V –10 +10 µA
Input Capacitance 10 pF

V

LOGIC OUTPUTS
V

OH

V

OL

I

OZ

C

OZ

Specifications subject to change without notice.

High Level Output Voltage IOH = 0.1 mA 4.0 V

= 0.5 mA 2.4 V

I

OH

Low Level Output Voltage IOL = 1.6 mA 0.4 V
High Z Leakage Current VIN = 0 or V

DD

–10 +10 µA
High Z Output Capacitance 10 pF

–2–

REV. C

AD678

DC SPECIFICATIONS

(T

to T

MIN

, VCC = +12 V ⴞ 5%, VEE = –12 V ⴞ 5%, VDD = +5 V ⴞ 10% unless otherwise noted)

MAX

AD678J/A/S AD678K/B/T

Parameter Min Typ Max Min Typ Max Units

TEMPERATURE RANGE

J, K Grades 0 +70 0 +70 °C
A, B Grades –40 +85 –40 +85 °C
S, T Grades –55 +125 –55 +125 °C

ACCURACY

Resolution 12 12 Bits
Integral Nonlinearity (INL) ± 1 ± 0.7 ± 1 LSB
Differential Nonlinearity (DNL) 12 12 Bits
Unipolar Zero Error (@ +25°C)
Bipolar Zero Error (@ +25°C)
Gain Error (@ +25°C)

1, 2

1

1

± 4 ± 2 ± 3 LSB
± 4 ± 3 ± 5 LSB
± 4 ± 3 ± 6 LSB

Temperature Drift

Unipolar/Bipolar Zero

J, K Grades ± 2 ± 2 ± 4 LSB
A, B Grades ± 4 ± 3 ± 4 LSB
S, T Grades ± 5 ± 4 ± 5 LSB

3

Gain

J, K Grades ± 4 ± 4 ± 6 LSB
A, B Grades ± 7 ± 5 ± 9 LSB
S, T Grades ± 10 ± 8 ±10 LSB

4

Gain

J, K Grades ± 2 ± 2 ± 4 LSB
A, B Grades ± 4 ± 3 ± 4 LSB
S, T Grades ± 6 ± 5 ± 6 LSB

ANALOG INPUT

Input Ranges

Unipolar Range 0 +10 0 +10 V

Bipolar Range –5 +5 –5 +5 V
Input Resistance 10 10 MΩ
Input Capacitance 10 10 pF
Input Settling Time 1 1 µs
Aperture Delay 10 10 ns
Aperture Jitter 150 150 ps

INTERNAL VOLTAGE REFERENCE

Output Voltage

5

4.98 5.02 4.98 5.02 V

External Load

Unipolar Mode +1.5 +1.5 mA

Bipolar Mode +0.5 +0.5 mA

POWER SUPPLIES

Power Supply Rejection

= +12 V ± 5% ± 2 ± 2 LSB

V

CC

V

= –12 V ± 5% ± 2 ± 2 LSB

EE

V

= +5 V ± 10% ± 2 ±2 LSB

DD

Operating Current

I

CC

I

EE

I

DD

18 20 18 20 mA
25 34 25 34 mA
812 812mA

Power Consumption 560 745 560 745 mW

NOTES

1

Adjustable to zero.

2

Includes internal voltage reference error.

3

Includes internal voltage reference drift.

4

Excludes internal voltage reference drift.

5

With maximum external load applied.

Specifications subject to change without notice.

REV. C

–3–

AD678

TIMING SPECIFICATIONS

(All grades, T
otherwise noted)

MIN

to T

, VCC = +12 V ⴞ 5%, VEE = –12 V ⴞ 5%, VDD = +5 V ⴞ 10% unless

MAX

Parameter Symbol Min Max Units

SC Delay t
Conversion Time t
Conversion Rate

l

Convert Pulsewidth t
Aperture Delay t
Status Delay t
Access Time

Float Delay

2, 3

5

Output Delay t
Format Setup t
OE Delay t
Read Pulsewidth t
Conversion Delay t
EOCEN Delay t

NOTES

1

Includes acquisition time.

2

Measured from the falling edge of OE/EOCEN (0.8 V) to the time at which the data lines/EOC cross 2.0 V or 0.8 V. See Figure 3.

3

C

= 100 pF.

OUT

4

C

= 50 pF.

OUT

5

Measured from the rising edge of OE/EOCEN (2.0 V) to the time at which the output voltage changes by 0.5 V. See Figure 3; C

Specifications subject to change without notice.

SC

C

t

CR

CP

AD

SD

t

BA

t

FD

OD

FS

OE

RP

CD

EO

50 ns

3.0 4.4 µs
5 µs

97 ns
520ns
0 400 ns
10 100 ns
10 57

4

ns

10 80 ns

0ns

47 ns
0ns
97 ns
150 ns
0ns

= 10 pF.

OUT

Figure 1. Conversion Timing

Figure 2. EOC Timing

Figure 3. Load Circuit for Bus Timing Specifications

–4–

REV. C

AD678

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

With
Respect

Specification To Min Max Units

V

CC

V

EE

V

CC

V

DD

AGND –0.3 +18 V
AGND –18 +0.3 V
V

EE

–0.3 +26.4 V

DGND 0 +7 V
AGND DGND –1 +1 V
AIN, REF

IN

AGND V

EE

V

CC

V
Digital Inputs DGND –0.5 +7 V
Digital Outputs DGND –0.5 V

+ 0.3 V

DD

Max Junction

Temperature 175 °C

Operating Temperature

J and K Grades 0 +70 °C
A and B Grades –40 +85 °C

S and T Grades –55 +125 °C
Storage Temperature –65 +150 °C
Lead Temperature

(10 sec max) +300 °C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

REF

OUT

REF

BIPOFF

AIN

AGND

SC OE EOCEN

CS

SYNC

EOC

12/8

AD678

VOLTAGE

REF.

IN

SAMPLE/

HOLD

CONTROL LOGIC

12-BIT D/A

CONVERTER

12

CONVERSION

LOGIC

GAIN
STAGE

12

OUTPUT

REGISTER

4

4-BIT FLASH

A/D

CONVERTER

DB11

DB2

DB1
(R/L)

DB0
(HBE)

V

CC

V

EE

V

DD

DGND

Functional Block Diagram

ESD SENSITIVITY

The AD678 features input protection circuitry consisting of large “distributed” diodes and polysilicon
series resistors to dissipate both high energy discharges (Human Body Model) and fast, low energy
pulses (Charged Device Model). Per Method 3015.2 of MIL-STD-883C, the AD678 has been
classified as a Category 1 device.

Proper ESD precautions are strongly recommended to avoid functional damage or performance
degradation. Charges as high as 4000 volts readily accumulate on the human body and test equipment
and discharge without detection. Unused devices must be stored in conductive foam or shunts, and
the foam should be discharged to the destination socket before devices are removed. For further
information on ESD precautions, refer to Analog Devices’ ESD Prevention Manual.

ORDERING GUIDE

1

Model

Package Temperature Range Tested and Specified Package Option

AD678JN 28-Lead Plastic DIP 0°C to +70°C AC N-28
AD678KN 28-Lead Plastic DIP 0°C to +70°C AC + DC N-28
AD678JD 28-Lead Ceramic DIP 0°C to +70°C AC D-28
AD678KD 28-Lead Ceramic DIP 0°C to +70°C AC + DC D-28
AD678AD 28-Lead Ceramic DIP –40°C to +85°C AC D-28
AD678BD 28-Lead Ceramic DIP –40°C to +85°C AC + DC D-28
AD678AJ 44-Lead Ceramic JLCC –40°C to +85°C AC J-44
AD678BJ 44-Lead Ceramic JLCC –40°C to +85°C AC + DC J-44
AD678SD 28-Lead Ceramic DIP –55°C to +125°C AC D-28
AD678TD 28-Lead Ceramic DIP –55°C to +125°C AC + DC D-28

NOTES

1

For details on grade and package offerings screened in accordance with MIL-STD-883, refer to Analog Devices Military Products Databook or /883 data sheet.

2

N = Plastic DIP; D = Ceramic DIP; J = J-Leaded Ceramic Chip Carrier.

2

REV. C

–5–