ANALOG DEVICES AD6657 Service Manual

A

VDDA

Quad IF Receiver

Data Sheet

FEATURES

11-bit, 200 MSPS output data rate per channel
Integrated noise shaping requantizer (NSR)
Performance with NSR enabled

SNR: 75.5 dBFS in 40 MHz band to 70 MHz @ 185 MSPS
SNR: 73.7 dBFS in 60 MHz band to 70 MHz @ 185 MSPS

Performance with NSR disabled

SNR: 66.5 dBFS to 70 MHz @ 185 MSPS
SFDR: 83 dBc to 70 MHz @ 185 MSPS

Low power: 1.2 W @ 185 MSPS

1.8 V analog supply operation

1.8 V LVDS (ANSI-644 levels) output
1-to-8 integer clock divider
Internal ADC voltage reference

1.75 V p-p analog input range (programmable to 2.0 V p-p)
Differential analog inputs with 800 MHz bandwidth
95 dB channel isolation/crosstalk
Serial port control
User-configurable built-in self-test (BIST) capability
Energy-saving power-down modes

APPLICATIONS

Communications
Diversity radio and smart antenna (MIMO) systems
Multimode digital receivers (3G)

WCDMA, LTE, CDMA2000

WiMAX, TD-SCDMA
I/Q demodulation systems
General-purpose software radios

AD6657

FUNCTIONAL BLOCK DIAGRAM

GND DRVDD DRGND

AD6657

VIN+A

VIN–A

VCMA

VIN+B

VIN–B

VCMB

VIN+C

VIN–C

VCMC

VIN+D

VIN–D

VCMD

PIPELINE

PIPELINE

PIPELINE

PIPELINE

REFERENCE

SERIAL PORT

SCLK SDIO CSB CLK+

14 11

ADC

ADC

ADC

ADC

NOISE SHAPING

14 11

NOISE SHAPING

14 11

NOISE SHAPING

14 11

NOISE SHAPING

REQUANTIZER

REQUANTIZER

REQUANTIZER

REQUANTIZER

AND LVDS DRIVERS

DATA MULTIPLEXER

CLOCK

DIVIDER

CLK–

Figure 1.

PRODUCT HIGHLIGHTS

1. Four ADCs are contained in a small, space-saving,

10 mm × 10 mm × 1.4 mm, 144-ball CSP_BGA package.

2. Pin selectable noise shaping requantizer (NSR) function

that allows for improved SNR within a reduced bandwidth
of up to 60 MHz at 185 MSPS.

3. LVDS digital output interface configured for low cost

FPGA families.

4. 230 mW per ADC core power consumption.

5. Operation from a single 1.8 V supply.

6. Standard serial port interface (SPI) that supports various

product features and functions, such as data formatting
(offset binary or twos complement), NSR, power-down,
test modes, and voltage reference mode.

7. On-chip integer 1-to-8 input clock divider and multichip

sync function to support a wide range of clocking schemes
and multichannel subsystems.

DC0±AB

D0±AB

PORT A

D10±AB

DC0±CD

D0±CD

PORT B

D10±CD

MODE

SYNC

PDWN

08557-001

Rev. B

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AD6657 Data Sheet

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

General Description ......................................................................... 3

Specifications..................................................................................... 4

DC Specifications ......................................................................... 4

AC Specifications.......................................................................... 5

Digital Specifications ................................................................... 6

Switching Specifications.............................................................. 7

Timing Specifications .................................................................. 8

Absolute Maximum Ratings............................................................ 9

Thermal Characteristics .............................................................. 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Typical Performance Characteristics ........................................... 12

Equivalent Circuits......................................................................... 15

Theory of Operation ...................................................................... 16

ADC Architecture ......................................................................16

Analog Input Considerations.................................................... 16

Clock Input Considerations...................................................... 18

Power Dissipation and Standby Mode .................................... 20

Channel/Chip Synchronization................................................ 20

Digital Outputs........................................................................... 21

Timing ......................................................................................... 21

Noise Shaping Requantizer (NSR) ............................................... 22

22% BW Mode (>40 MHz @ 184.32 MSPS)........................... 22

33% BW Mode (>60 MHz @ 184.32 MSPS)........................... 22

MODE Pin................................................................................... 23

Built-In Self-Test (BIST) and Output Test .................................. 24

Built-In Self-Test (BIST)............................................................ 24

Output Test Modes..................................................................... 24

Serial Port Interface (SPI).............................................................. 25

Configuration Using the SPI..................................................... 25

Hardware Interface..................................................................... 25

Memory Map .................................................................................. 26

Reading the Memory Map Register Table............................... 26

Memory Map Register Table..................................................... 27

Memory Map Register Descriptions........................................ 29

Applications Information.............................................................. 30

Design Guidelines ...................................................................... 30

Outline Dimensions....................................................................... 31

Ordering Guide .......................................................................... 31

REVISION HISTORY

8/11—Rev. A to Rev. B

Changes to Logic Input/Output (SDIO) Parameter Note,

Table 3 ................................................................................................ 6

Added Wake-Up Time (from Standby) Parameter, Table 4 and

Wake-Up Time (from Power Down) Parameter, Table 4............ 7

Changes to Figure 2.......................................................................... 8

Changes to Table 11........................................................................ 21

Updated Outline Dimensions....................................................... 31

Rev. B | Page 2 of 32

7/10—Rev. 0 to Rev. A

Changes to ADC Architecture Section........................................ 16

Changes to Figure 34 and Figure 35............................................. 18

Changes to Timing Section and Data Clock Output (DCO)

Section.............................................................................................. 21

Changes to 22% BW Mode (>40 MHz @ 184.32 MSPS) Section

and 33% BW Mode (>60 MHz @ 184.32 MSPS) Section ......... 22

Changed 0x0C to 0x79, Address 0x01, Table 13......................... 27

Changed DCO Output Delay (Global) to DCO Output Delay

(Local), Address 0x17, Table 13.................................................... 28

Changes to Design Guidelines Section........................................ 30

10/09—Revision 0: Initial Version

Data Sheet AD6657

GENERAL DESCRIPTION

The AD6657 is an 11-bit, 200 MSPS, quad-channel intermediate
frequency (IF) receiver specifically designed to support multi­antenna systems in telecommunication applications where high
dynamic range performance, low power, and small size are desired.

The device consists of four high performance analog-to-digital
converters (ADCs) and noise shaping requantizer (NSR) digital
blocks. Each ADC consists of a multistage, differential pipelined
architecture with integrated output error correction logic. The
ADC features a wide bandwidth switched-capacitor sampling
network within the first stage of the differential pipeline. An
integrated voltage reference eases design considerations. A duty
cycle stabilizer (DCS) compensates for variations in the ADC
clock duty cycle, allowing the converters to maintain excellent
performance.

Each ADC output is connected internally to an NSR block. The
integrated NSR circuitry allows for improved SNR performance
in a smaller frequency band within the Nyquist bandwidth. The
device supports two different output modes selectable via the
external MODE pin or the SPI.

With the NSR feature enabled, the outputs of the ADCs are
processed such that the AD6657 supports enhanced SNR
performance within a limited portion of the Nyquist bandwidth
while maintaining an 11-bit output resolution. The NSR block
can be programmed to provide a bandwidth of either 22% or
33% of the sample clock. For example, with a sample clock rate
of 185 MSPS, the AD6657 can achieve up to 75.5 dBFS SNR for
a 40 MHz bandwidth in the 22% mode and up to 73.7 dBFS
SNR for a 60 MHz bandwidth in the 33% mode.

With the NSR block disabled, the ADC data is provided directly to
the output with a resolution of 11 bits. The AD6657 can achieve
up to 66.5 dBFS SNR for the entire Nyquist bandwidth when
operated in this mode. This allows the AD6657 to be used in
telecommunication applications such as a digital predistortion
observation path where wider bandwidths are desired.

After digital signal processing, multiplexed output data is
routed into two 11-bit output ports such that the maximum
data rate is 400 Mbps (DDR). These outputs are set at 1.8 V
LVDS and support ANSI-644 levels.

The AD6657 receiver digitizes a wide spectrum of IF frequencies.
Each receiver is designed for simultaneous reception of a separate
antenna. This IF sampling architecture greatly reduces compo­nent cost and complexity compared with traditional analog
techniques or less integrated digital methods.

Flexible power-down options allow significant power savings.
Programming for device setup and control is accomplished
using a 3-wire SPI-compatible serial interface with numerous
modes to support board-level system testing.

The AD6657 is available in a Pb-free/RoHS compliant, 144-ball,
10 mm × 10 mm chip scale package ball grid array (CSP_BGA)
and is specified over the industrial temperature range of −40°C
to +85°C.

Rev. B | Page 3 of 32

AD6657 Data Sheet

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless
otherwise noted.

Table 1.

Parameter Temperature Min Typ Max Unit
RESOLUTION Full 11 Bits
ACCURACY

No Missing Codes Full Guaranteed
Offset Error Full −4.5 2 7.4 mV
Gain Error Full ±3 ±7 % FSR
Differential Nonlinearity (DNL)1 Full ±0.1 ±0.5 LSB
Integral Nonlinearity (INL)1 Full ±0.2 ±0.5 LSB

MATCHING CHARACTERISTIC

Offset Error Full −2.4 2.5 8.3 mV
Gain Error Full ±1 ±3 % FSR

TEMPERATURE DRIFT

Offset Error Full 2 ppm/°C
Gain Error Full 40 ppm/°C

ANALOG INPUT

Input Range Full 1.4 1.75 2.0 V p-p
Input Common-Mode Voltage Full 0.9 V
Input Resistance (Differential) Full 20 kΩ
Input Capacitance2 Full 5 pF

POWER SUPPLIES

Supply Voltage

AVDD Full 1.7 1.8 1.9 V
DRVDD Full 1.7 1.8 1.9 V

Supply Current

1

I

Full 510 548 mA

AVDD

1

I

(1.8 V LVDS) Full 155 169 mA

DRVDD

POWER CONSUMPTION

Sine Wave Input1 Full 1195 1290 mW
Standby Power3 Full 130 mW
Power-Down Power Full 4.5 18 mW

1

Measured with a 10 MHz, 0 dBFS sine wave, with 100 Ω termination on each LVDS output pair.

2

Input capacitance refers to the effective capacitance between one differential input pin and AGND.

3

Standby power is measured with a dc input and the CLKx pins inactive (set to AVDD or AGND).

Rev. B | Page 4 of 32

Data Sheet AD6657

AC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless
otherwise noted.

Table 2.

Parameter1 Temperature Min Typ Max Unit

SIGNAL-TO-NOISE-RATIO (SNR)—NSR DISABLED

fIN = 30 MHz 25°C 66.5 dBFS

fIN = 70 MHz 25°C 66.5 dBFS

fIN = 170 MHz Full 65.7 66.1 dBFS

fIN = 250 MHz 25°C 65.5 dBFS

SIGNAL-TO-NOISE-RATIO (SNR)—NSR ENABLED

22% BW Mode

fIN = 70 MHz 25°C 75.5 dBFS
fIN = 170 MHz Full 72.8 74.4 dBFS
fIN = 230 MHz 25°C 72.8 dBFS

33% BW Mode

fIN = 70 MHz 25°C 73.7 dBFS
fIN = 170 MHz Full 71.0 72.6 dBFS
fIN = 230 MHz 25°C 71.0 dBFS

SIGNAL-TO-NOISE-AND DISTORTION (SINAD)

fIN = 30 MHz 25°C 65.5 dBFS

fIN = 70 MHz 25°C 66.3 dBFS

fIN = 170 MHz Full 64.1 65.6 dBFS

fIN = 250 MHz 25°C 64.3 dBFS

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 30 MHz 25°C 10.6 Bits

fIN = 70 MHz 25°C 10.7 Bits

fIN = 170 MHz Full 10.3 10.6 Bits

fIN = 250 MHz 25°C 10.3 Bits

WORST SECOND OR THIRD HARMONIC

fIN = 30 MHz 25°C −90 dBc

fIN = 70 MHz 25°C −83 dBc

fIN = 170 MHz Full −72 −78 dBc

fIN = 250 MHz 25°C −80 dBc

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fIN = 30 MHz 25°C 90 dBc

fIN = 70 MHz 25°C 83 dBc

fIN = 170 MHz Full 72 78 dBc

fIN = 250 MHz 25°C 80 dBc

WORST OTHER HARMONIC (FOURTH THROUGH EIGHTH)

fIN = 30 MHz 25°C −100 dBc

fIN = 70 MHz 25°C −96 dBc

fIN = 170 MHz Full −82 −90 dBc

fIN = 250 MHz 25°C −95 dBc

TWO-TONE SFDR (−7 dBFS)

f

= 169 MHz, f

IN1

CROSSTALK2 Full 95 dB
ANALOG INPUT BANDWIDTH 25°C 800 MHz

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

2

Crosstalk is measured at 155 MHz with −1 dBFS on one channel and no input on the alternate channel.

= 172 MHz 25°C 82 dBc

IN2

Rev. B | Page 5 of 32

AD6657 Data Sheet

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless
otherwise noted.

Table 3.

Parameter Temperature Min Typ Max Unit

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Logic Compliance CMOS/LVDS/LVPECL
Internal Common-Mode Bias Full 0.9 V
Differential Input Voltage Full 0.2 3.6 V p-p
Input Voltage Range Full AGND − 0.3 AVDD + 0.2 V
High Level Input Voltage Full 1.2 2.0 V
Low Level Input Voltage Full 0 0.8 V
High Level Input Current Full −10 +10 μA
Low Level Input Current Full −10 +10 μA
Input Resistance Full 8 10 12 kΩ
Input Capacitance Full 4 pF

SYNC INPUT

Logic Compliance CMOS
Internal Bias Full 0.9 V
Input Voltage Range Full AGND AVDD V
High Level Input Voltage Full 1.2 AVDD V
Low Level Input Voltage Full AGND 0.6 V
High Level Input Current Full −100 +100 μA
Low Level Input Current Full −100 +100 μA
Input Resistance Full 12 16 20 kΩ
Input Capacitance Full 1 pF

LOGIC INPUT (CSB)1

High Level Input Voltage Full 1.22 2.1 V
Low Level Input Voltage Full 0 0.6 V
High Level Input Current Full −10 +10 μA
Low Level Input Current Full 40 132 μA
Input Resistance Full 26 kΩ
Input Capacitance Full 2 pF

LOGIC INPUT (SCLK)2

High Level Input Voltage Full 1.22 2.1 V
Low Level Input Voltage Full 0 0.6 V
High Level Input Current Full −92 −135 μA
Low Level Input Current Full −10 +10 μA
Input Resistance Full 26 kΩ
Input Capacitance Full 2 pF

LOGIC INPUT/OUTPUT (SDIO)1

High Level Input Voltage Full 1.22 2.1 V
Low Level Input Voltage Full 0 0.6 V
High Level Input Current Full −10 +10 μA
Low Level Input Current Full 38 128 μA
Input Resistance Full 26 kΩ
Input Capacitance Full 5 pF

Rev. B | Page 6 of 32

Data Sheet AD6657

Parameter Temperature Min Typ Max Unit

LOGIC INPUT (MODE)1

High Level Input Voltage Full 1.22 2.1 V

Low Level Input Voltage Full 0 0.6 V

High Level Input Current Full −10 +10 μA

Low Level Input Current Full 40 132 μA

Input Resistance Full 26 kΩ

Input Capacitance Full 2 pF

LOGIC INPUT (PDWN)2

High Level Input Voltage Full 1.22 2.1 V

Low Level Input Voltage Full 0 0.6 V

High Level Input Current Full −90 −134 μA

Low Level Input Current Full −10 +10 μA

Input Resistance Full 26 kΩ

Input Capacitance Full 5 pF

DIGITAL OUTPUTS (LVDS)

Differential Output Voltage (VOD) Full 247 454 mV

Output Offset Voltage (VOS) Full 1.125 1.375 V

1

Pull up.

2

Pull down.

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS dierential input, and default SPI, unless
otherwise noted.

Table 4.

Parameter Temperature Min Typ Max Unit

CLOCK INPUT PARAMETERS

Input Clock Rate Full 625 MHz

Conversion Rate1 Full 40 185 200 MSPS

CLK Pulse Width High (tCH) Full 2.7 ns

Aperture Delay (tA) Full 1.3 ns

Aperture Uncertainty (Jitter, tJ) Full 0.13 ps rms

DATA OUTPUT PARAMETERS

Data Propagation Delay (tPD) Full 3.0

DCO Propagation Delay (t

DCO to Data Skew (t

SKEW

) Full 3.2

DCO

) Full −0.4 −0.2 0 ns

Pipeline Delay (Latency) Full 9 Cycles

With NSR Enabled Full 12 Cycles
Wake-Up Time2 (from Standby) Full 0.5 μs
Wake-Up Time2 (from Power Down) Full 350 μs

OUT-OF-RANGE RECOVERY TIME Full 2 Cycles

1

Conversion rate is the clock rate after the divider.

2

Wake-up time is dependent on the value of the decoupling capacitors.

4.35

4.55

5.7 ns

5.9 ns

Rev. B | Page 7 of 32

AD6657 Data Sheet

TIMING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless
otherwise noted.

Table 5.

Parameter Description Min Typ Max Unit

SYNC TIMING REQUIREMENTS See Figure 3

t

SYNC to rising edge of CLK setup time 0.24 ns

SSYNC

t

SYNC to rising edge of CLK hold time 0.40 ns

HSYNC

SPI TIMING REQUIREMENTS See Figure 2

tDS Setup time between the data and the rising edge of SCLK 2 ns
tDH Hold time between the data and the rising edge of SCLK 2 ns
t

Period of the SCLK 40 ns

CLK

tS Setup time between CSB and SCLK 2 ns
tH Hold time between CSB and SCLK 2 ns
t

SCLK pulse width high 10 ns

HIGH

t

SCLK pulse width low 10 ns

LOW

t

EN_SDIO

t

DIS_SDIO

Timing Diagrams

VIN

Time required for the SDIO pin to switch from an input to
an output relative to the SCLK falling edge

Time required for the SDIO pin to switch from an output to
an input relative to the SCLK rising edge

N – 1

t

A

N

10 ns

10 ns

N + 4

N + 5

N + 3

CLK–

CLK+

DCO+

DCO–

D10(MSB)+AB

D10(MSB)–AB

D0(LSB)+AB

D0(LSB)–AB

N + 1

t

CH

t

CL

t

DCO

D10A D10B

D0A D0B D0A D0B D0A D0B D0A D0B D0A D0B D0A D0B

D10A D10B D10A D10B D10A D10B D10A D10B D10A D10B D10A D10B

D0A D0B

1/

f

S

t

SKEW

t

PD

N + 2

Figure 2. Data Output Timing (Timing for Channel C and Channel D Is Identical to Timing for Channel A and Channel B)

CLK+

t

HSYNC

08557-003

SYNC

t

SSYNC

Figure 3. SYNC Input Timing Requirements

08557-002

Rev. B | Page 8 of 32

Data Sheet AD6657

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

AVDD to AGND −0.3 V to +2.0 V
DRVDD to AGND −0.3 V to +2.0 V
VIN+x, VIN−x to AGND −0.3 V to AVDD + 0.2 V
CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V
SYNC to AGND −0.3 V to AVDD + 0.2 V
VCMx to AGND −0.3 V to AVDD + 0.2 V
CSB to AGND −0.3 V to DRVDD + 0.2 V
SCLK to AGND −0.3 V to DRVDD + 0.2 V
SDIO to AGND −0.3 V to DRVDD + 0.2 V
PDWN to AGND −0.3 V to DRVDD + 0.2 V
MODE to AGND −0.3 V to DRVDD + 0.2 V
Digital Outputs to AGND −0.3 V to DRVDD + 0.2 V
DCO+AB, DCO−AB, DCO+CD,

−0.3 V to DRVDD + 0.2 V

DCO−CD to AGND

Operating Temperature Range

−40°C to +85°C

(Ambient)

Maximum Junction Temperature

150°C

Under Bias

Storage Temperature Range

−65°C to +150°C

(Ambient)

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL CHARACTERISTICS

The values in Table 7 are per JEDEC JESD51-7 plus JEDEC
JESD25-5 for a 2S2P test board. Typical θ
4-layer PCB with a solid ground plane. As shown in Tabl e 7,
airflow improves heat dissipation, which reduces θ
tion, metal in direct contact with the package leads from metal
traces, through holes, ground, and power planes reduces θ

Table 7.

Airflow

Package Type

144-Ball CSP_BGA,

10 mm × 10 mm
(BC-144-1)

1

Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).

2

Per MIL-STD 883, Method 1012.1.

3

Per JEDEC JESD51-8 (still air).

Velocity θ

0 m/s 26.9 8.9 6.6
1 m/s 24.2

2.5 m/s 23.0

The values in Table 8 are from simulations. The PCB is a JEDEC
multilayer board. Thermal performance for actual applications
requires careful inspection of the conditions in the application
to determine whether they are similar to those assumed in these
calculations.

Table 8.

Airflow

Package Type

144-Ball CSP_BGA,

10 mm × 10 mm
(BC-144-1)

Veloc ity Ψ

0 m/s 14.4 0.23
1 m/s 14.0 0.50

2.5 m/s 13.9 0.53

is specified for a

JA

1

JA

2

θ

JC

JB

. In addi-

JA

3

θ

JB

Ψ

JT

.

JA

Unit

°C/W

Unit

°C/W

ESD CAUTION

Rev. B | Page 9 of 32

AD6657 Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

123456789101112

AGND VI N+C VI N–C AGND AVDD CLK– CLK+ AVDD AGND VIN–B VIN+B AGND

A

AGND AG ND VCMC AGND AVDD AVDD AVDD AVDD AGND VCMB AGND AGND

B

VIN+D AGND AGND CSB SDIO SCLK PDWN SYNC MODE AGND AGND VIN+A

C

VIN–D VCMD AGND AVDD AVDD AVDD AVDD AVDD AVDD AGND VCMA VIN–A

D

AGND AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AGND

E

AGND AG ND AGND AGND AGND AGND AGND AGND AG ND AG ND AG ND AGND

F

DRGND DRGND DRGND DRGND DRGND DRG ND DRGND DRGND DRGND DRGND DRGND DRGND

G

DRVDD DRVDD DRVDD DRVDD DRVDD DRVDD DRVDD DRVDD DRVDD DRVDD DRVDD DRVDD

H

D0–CD D2–CD D4–CD D6–CD D8–CD D10–CD D0–AB D2–AB D4–AB D6–AB D8–AB D10–AB

J

D0+CDK D2+CD D4+CD D6+CD D8+CD D10+CD D0+ AB D2+ AB D4+AB D6+AB D8+AB D10+ AB

D1–CD D3–CD D5–CD D7–CD D9–CD DCO –CD D1–AB D3–AB D5–AB D7–AB D9–AB DCO–AB

L

D1+CD

M D3+CD D5+CD D7+CD D9+CD DCO+CD D1+AB D3+AB D5+AB D7+AB D9+AB DCO+AB

Figure 4. Pin Configuration (Top View)

Table 9. Pin Function Descriptions

Pin No. Mnemonic Type Description

A5, A8, B5, B6, B7, B8,

AVDD Supply Analog Power Supply (1.8 V Nominal)
D4, D5, D6, D7, D8,
D9, E2, E3, E4, E5, E6,
E7, E8, E9, E10, E11

A1, A4, A9, A12, B1,

AGND Ground Analog Ground
B2, B4, B9, B11, B12,
C2, C3, C10, C11, D3,
D10, E1, E12, F1, F2,
F3, F4, F5, F6, F7, F8,
F9, F10, F11, F12

H1, H2, H3, H4, H5,

DRVDD Supply Digital Output Driver Supply (1.8 V Nominal)
H6, H7, H8, H9, H10,
H11, H12

G1, G2, G3, G4, G5,

DRGND Ground Digital Output Driver Ground
G6, G7, G8, G9, G10,
G11, G12

A7 CLK+ Input ADC Clock Input—True
A6 CLK− Input ADC Clock Input—Complement
C12 VIN+A Input Differential Analog Input Pin (+) for Channel A
D12 VIN−A Input Differential Analog Input Pin (−) for Channel A
D11 VCMA Output Common-Mode Level Bias Output for Analog Input Channel A
A11 VIN+B Input Differential Analog Input Pin (+) for Channel B
A10 VIN−B Input Differential Analog Input Pin (−) for Channel B
B10 VCMB Output Common-Mode Level Bias Output for Analog Input Channel B
A2 VIN+C Input Differential Analog Input Pin (+) for Channel C
A3 VIN−C Input Differential Analog Input Pin (−) for Channel C
B3 VCMC Output Common-Mode Level Bias Output for Analog Input Channel C
C1 VIN+D Input Differential Analog Input Pin (+) for Channel D
D1 VIN−D Input Differential Analog Input Pin (−) for Channel D
D2 VCMD Output Common-Mode Level Bias Output for Analog Input Channel D
K7 D0+AB Output Channel A and Channel B LVDS Output Data 0—True
J7 D0−AB Output Channel A and Channel B LVDS Output Data 0—Complement

5887-004

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