ANALOG DEVICES AD5680 Service Manual

5 V 18-Bit nanoDAC®

V

V

FEATURES

Single 18-bit nanoDAC
18-bit monotonic
12-bit accuracy guaranteed
Tiny 8-lead SOT-23 package
Power-on reset to zero scale/midscale

4.5 V to 5.5 V power supply
Serial interface
Rail-to-rail operation
SYNC

interrupt facility

Temperature range: −40°C to +105°C

APPLICATIONS

Closed-loop process control
Low bandwidth data acquisition systems
Portable battery-powered instruments
Gain and offset adjustment
Precision setpoint control

GENERAL DESCRIPTION

The AD5680, a member of the nanoDAC family, is a single,
18-bit buffered voltage-out digital-to-analog converter that
operates from a single 4.5 V to 5.5 V supply and is 18-bit
monotonic.

The AD5680 requires an external reference voltage to set the
output range of the DAC. The part incorporates a power-on
reset circuit that ensures the DAC output powers up to 0 V
(AD5680-1) or to midscale (AD5680-2) and remains there until
a valid write takes place.

The low power consumption of this part in normal operation
makes it ideally suited to portable battery-operated equipment.
The power consumption is 1.6 mW at 5 V.

The AD5680 on-chip precision output amplifier allows rail-to­rail output swing to be achieved. For remote sensing applications,
the output amplifier’s inverting input is available to the user.

in a SOT-23

AD5680

FUNCTIONAL BLOCK DIAGRAM

GND

REF

POWER-ON

RESET

DAC

REGISTER

INPUT

CONTROL

LOGIC

REF(+)

18-BIT DAC

DINSCLKSYNC

The AD5680 uses a versatile 3-wire serial interface that operates
at clock rates up to 30 MHz, and is compatible with standard
SPI®, QSPI™, MICROWIRE™, and DSP interface standards.

PRODUCT HIGHLIGHTS

1. 18 bits of resolution.

2. 12-bit accuracy guaranteed for 18-bit DAC.

3. Available in an 8-lead SOT-23.

4. Low power; typically consumes 1.6 mW at 5 V.

5. Power-on reset to zero scale or to midscale.

RELATED DEVICES

AD5662—16-bit DAC in SOT-23.

Figure 1.

DD

OUTPUT
BUFFER

AD5680

V

FB

V

OUT

05854-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006–2007 Analog Devices, Inc. All rights reserved.

AD5680

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Product Highlights........................................................................... 1

Related Devices................................................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics ................................................................ 4

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics............................................. 7

Te r mi n ol o g y .................................................................................... 10

Theory of Operation ...................................................................... 11

DAC Section................................................................................ 11

Resistor String............................................................................. 11

Output Amplifier........................................................................ 11

Interpolator Architecture .......................................................... 11

Serial Interface............................................................................ 12

Input Shift Register .................................................................... 12

SYNC

Interrupt .......................................................................... 12

Power-On Reset .......................................................................... 12

Microprocessor Interfacing....................................................... 13

Applications..................................................................................... 14

Closed-Loop Applications ........................................................ 14

Filter ............................................................................................. 14

Choosing a Reference for the AD5680.................................... 15

Using a Reference as a Power Supply for the AD5680.......... 16

Using the AD5680 with a Galvanically Isolated Interface ....16

Power Supply Bypassing and Grounding................................ 16

Outline Dimensions .......................................................................17

Ordering Guide .......................................................................... 17

REVISION HISTORY

3/07—Rev. 0 to Rev. A

Changes to Input Shift Register Section ......................................12

Changes to Figure 25...................................................................... 12

6/06—Revision 0: Initial Version

Rev. A | Page 2 of 20

AD5680

SPECIFICATIONS

VDD = 4.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; V

= VDD; all specifications T

REF

MIN

to T

, unless otherwise noted.

MAX

Table 1.

B Grade

1

Parameter Min Typ Max Unit Conditions/Comments

STATIC PERFORMANCE

2

Resolution 18 Bits
Relative Accuracy ±32 ±64 LSB
Differential Nonlinearity

3

±1 LSB Measured in 50 Hz system bandwidth
±2 LSB Measured in 300 Hz system bandwidth
Zero-Code Error 2 10 mV All 0s loaded to DAC register
Full-Scale Error −0.2 −1 % FSR All 1s loaded to DAC register
Offset Error ±10 mV
Gain Error ±1.5 % FSR
Zero-Code Error Drift ±2 µV/°C
Gain Temperature Coefficient ±2.5 ppm Of FSR/°C
DC Power Supply Rejection Ratio −100 dB DAC code = midscale; VDD = 5 V ± 10%

OUTPUT CHARACTERISTICS

Output Voltage Range 0 V
Output Voltage Settling Time 80 85 µs

3

DD

V

¼ to ¾ scale change settling to ±8 LSB,

= 2 kΩ; 0 pF < CL < 200 pF

R

L

Slew Rate 1.5 V/µs ¼ to ¾ scale
Capacitive Load Stability 2 nF RL = ∞
10 nF RL = 2 kΩ
Output Noise Spectral Density
Output Noise (0.1 Hz to 10 Hz)
Total Harmonic Distortion (THD)

4

4

4

80 nV/√Hz DAC code = midscale, 10 kHz

25 µV p-p DAC code = midscale

−80 dB V

= 2 V ± 300 mV p-p, f = 200 Hz

REF

Digital-to-Analog Glitch Impulse 5 nV-s 1 LSB change around major carry
Digital Feedthrough 0.2 nV-s
DC Output Impedance 0.5 Ω
Short-Circuit Current

4

30 mA VDD = 5 V

REFERENCE INPUT

Reference Current 40 75 µA V
Reference Input Range

5

0.75 V

DD

V

= VDD = 5 V

REF

Reference Input Impedance 125 kΩ

LOGIC INPUTS

Input Current ±2 µA All digital inputs
V

, Input Low Voltage 0.8 V VDD = 5 V

INL

V

, Input High Voltage 2 V VDD = 5 V

INH

Pin Capacitance 3 pF

POWER REQUIREMENTS

VDD 4.5 5.5 V All digital inputs at 0 V or V

DD

IDD (Normal Mode) DAC active and excluding load current
VDD = 4.5 V to 5.5 V 325 450 A VIH = VDD and VIL = GND

POWER EFFICIENCY

I

OUT/IDD

1

Temperature range for B version is −40°C to +105°C, typical at +25°C.

2

DC specifications tested with the outputs unloaded, unless otherwise stated. Linearity calculated using a reduced code range of 2048 to 260,096.

3

Guaranteed by design and characterization; not production tested.

4

Output unloaded.

5

Reference input range at ambient where maximum DNL specification is achievable.

85 % I

= 2 mA, VDD = 5 V

LOAD

Rev. A | Page 3 of 20

AD5680

TIMING CHARACTERISTICS

All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
V

= 4.5 V to 5.5 V; all specifications T

DD

Table 2.

Limit at T

MIN

Parameter VDD = 4.5 V to 5.5 V Unit Conditions/Comments

1

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

1

Maximum SCLK frequency is 30 MHz at VDD = 4.5 V to 5.5 V.

33 ns min SCLK cycle time
13 ns min SCLK high time
13 ns min SCLK low time
13 ns min

5 ns min Data setup time

4.5 ns min Data hold time
0 ns min
33 ns min

13 ns min
0 ns min

t

10

SCLK

t

8

SYNC

DIN

, T

MAX

DB23

MIN

to T

t

4

, unless otherwise noted.

MAX

t

t

3

t

6

t

5

Figure 2. Serial Write Operation

SYNC to SCLK falling edge setup time

SCLK falling edge to
Minimum

SYNC high time

SYNC rising edge

SYNC rising edge to SCLK fall ignore
SCLK falling edge to

1

t

2

DB0

t

9

t

7

SYNC fall ignore

05854-002

Rev. A | Page 4 of 20

AD5680

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

VDD to GND −0.3 V to +7 V
V

to GND −0.3 V to VDD + 0.3 V

OUT

VFB to GND −0.3 V to VDD + 0.3 V
V

to GND −0.3 V to VDD + 0.3 V

REF

Digital Input Voltage to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range

Industrial (B Version) −40°C to +105°C

Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ max) 150°C

Power Dissipation (TJ max − TA)/θ

θJA Thermal Impedance

SOT-23 Package (4-Layer Board) 119°C/W

Reflow Soldering Peak Temperature

Pb-free 260°C

JA

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. A | Page 5 of 20

AD5680

V

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

V

DD

AD5680

2

V

REF

TOP VIEW

3

V

(Not to Scale)

FB

4

OUT

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 VDD Power Supply Input. The part can be operated from 4.5 V to 5.5 V. VDD should be decoupled to GND.
2 V

Reference Voltage Input.

REF

3 VFB Feedback Connection for the Output Amplifier. VFB should be connected to V
4 V
5

Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation.

OUT

SYNC Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC

goes low, it enables the input shift register and data is transferred in on the falling edges of the following clocks.
The DAC is updated following the 24

th

clock cycle unless SYNC is taken high before this edge, in which case the

rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. SYNC

6 SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can
be transferred at rates up to 30 MHz.

7 DIN

Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input.

8 GND Ground. Ground reference point for all circuitry on the part.

GND

8

7

DIN

6

SCLK

SYNC

5

05854-003

for normal operation.

OUT

Rev. A | Page 6 of 20