ANALOG DEVICES AD5543 Service Manual
16-/14-Bit DACs
AD5543/AD5553
Rev. F
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Fax: 781.461.3113 ©2002–2012 Analog Devices, Inc. All rights reserved.
16-BIT/14- BIT SHIF T
REGISTER
DAC
REGISTER
AD5543/AD5553
DAC
V
DD
V
REF
R
FB
I
OUT
CS
CLK
SDI
GND
CONTROL
LOGIC
16 OR 14
16 OR 14
02917-001
CODE
1.0
4096
INL (LSB)
0.8
8152
12,288
16,384
20,480
24,575
28,672
32,768
36,864
40,960
45,056
49,152
53,248
57,344
61,440
65,536
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
02917-002
2
0
–2
–4
–6
–8
–10
–12
–14
10k 100k 1M 10M 100M
GAIN (dB)
FREQUENCY ( Hz )
02917-025
Data Sheet
FEATURES
16-bit resolution AD5543
14-bit resolution AD5553
±1 LSB DNL
±1 LSB INL
Low noise: 12 nV/√Hz
Low power: I
0.5 µs settling time
4Q multiplying reference input
2 mA full-scale current ± 20%, with V
Built-in RFB facilitates voltage conversion
3-wire interface
Ultracompact 8-lead MSOP and 8-lead SOIC packages
APPLICATIONS
Automatic test equipment
Instrumentation
Digitally controlled calibration
Industrial control PLCs
= 10 µA
DD
= 10 V
REF
Current Output/Serial Input,
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
GENERAL DESCRIPTION
The AD5543/AD5553 are precision 16-/14-bit, low power,
current output, small form factor digital-to-analog converters
(DACs). They are designed to operate from a single 5 V supply
with a ±10 V multiplying reference.
The applied external reference, V
output current. An internal feedback resistor (R
R-2R and temperature tracking for voltage conversion when
combined with an external op amp.
A serial-data interface offers high speed, 3-wire microcontrollercompatible inputs using serial data in (SDI), clock (CLK), and
chip select (
CS
).
The AD5543/AD5553 are packaged in ultracompact (3 mm ×
4.7 mm) 8-lead MSOP and 8-lead SOIC packages.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
, determines the full-scale
REF
) facilitates the
FB
Figure 2. Integral Nonlinearity
Figure 3. Reference Multiplying Bandwidth
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
AD5543/AD5553 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Diagrams .......................................................................... 4
Absolute Maximum Ratings ............................................................ 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
Circuit Operation ............................................................................. 9
DAC Section .................................................................................. 9
Serial Data Interface ....................................................................... 10
ESD Protection Circuits............................................................. 10
PCB Layout and Power Supply Bypassing .............................. 10
Applications Information .............................................................. 11
Stability ........................................................................................ 11
Positive Voltage Output ............................................................. 11
Bipolar Output ............................................................................ 11
Programmable Current Source ................................................ 12
Reference Selection .................................................................... 12
Amplifier Selection .................................................................... 12
Evaluation Board ............................................................................ 14
System Development Platform ................................................. 14
AD5543/AD5553 to SPORT Interface .................................... 14
Waveform Generator ................................................................. 14
Operating the Evaluation Board .............................................. 14
Bill of Materials ........................................................................... 18
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 20
REVISION HISTORY
1/12—Rev. E to Rev. F
Added Figure 15, Renumbered Sequentially ................................ 8
Change to Table 9 ........................................................................... 13
Changes to Figure 27 ...................................................................... 15
Changes to Figure 28 ...................................................................... 16
Replaced Figure 29, Figure 30, and Figure 31 ............................. 17
2/11—Rev. D to Rev. E
Added Evaluation Board Section ................................................. 14
Updated Outline Dimensions ....................................................... 20
Changes to Ordering Guide .......................................................... 21
4/10—Rev. C to Rev. D
Changes to Figure 3 .......................................................................... 1
Changes to Table 1 ............................................................................ 3
Moved Timing Diagrams Section .................................................. 4
Moved Table 4 ................................................................................... 6
Delete Figure 13; Renumbered Sequentially ................................. 8
Changes to Figure 14 ........................................................................ 8
Changes to Figure 18 ........................................................................ 9
Moved Table 5 and Table 6 ............................................................ 10
Added Reference Selection Section and Amplifier Selection
Section .............................................................................................. 12
Added Table 7, Table 8, and Table 9;
Renumbered Sequentially .............................................................. 13
10/09—Rev. B to Rev. C
Updated Outline Dimensions ..................................................... 14
Changes to Ordering Guide .......................................................... 15
7/09—Rev. A to Rev. B
Updated Format .................................................................. Universal
Change to Features Section .............................................................. 1
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 15
2/03—Rev. 0 to Rev. A
Changes to Ordering Guide ............................................................. 3
12/02—Revision 0: Initial Version
Rev. F | Page 2 of 20
Data Sheet AD5543/AD5553
Resolution
N
1 LSB = V
/216 = 153 µV when V
= 10 V (AD5543)
16
Bits
Differential Nonlinearity
DNL
Monotonic
±1
LSB max
Data = 0x3FFF for AD5553
Logic Input Low Voltage
VIL 0.8
V max
SPECIFICATIONS
VDD = 5 V ± 10%, VSS = 0 V, I
Table 1.
Parameter Symbol Condition 5 V ± 10% Unit
STATIC PERFORMANCE1
1 LSB = V
Relative Accuracy INL Grade: AD5553C ±1 LSB max
Grade: AD5543C ±1 LSB max
Grade: AD5543B ±2 LSB max
= virtual GND, GND = 0 V, V
OUT
= 10 V, TA = full operating temperature range, unless otherwise noted.
REF
REF
/214 = 610 µV when V
REF
REF
= 10 V (AD5553) 14 Bits
REF
Output Leakage Current I
Data = 0x0000, TA = 25°C 10 nA max
OUT
Data = 0x0000, TA = TA maximum 20 nA max
Full-Scale Gain Error G
Data = 0xFFFF ±1/±4 mV typ/max
FSE
Full-Scale Temperature Coefficient2 TCVFS 1 ppm/°C typ
REFERENCE INPUT
V
Range V
REF
Input Resistance R
Input Capacitance2 C
−15/+15 V min/max
REF
5 kΩ typ3
REF
5 pF typ
REF
ANALOG OUTPUT
Output Current I
Output Capacitance2 C
Data = 0xFFFF for AD5543 2 mA typ
OUT
Code dependent 200 pF typ
OUT
LOGIC INPUTS AND OUTPUT
Logic Input High Voltage VIH 2.4 V min
Input Leakage Current IIL 10 µA max
Input Capacitance2 CIL 10 pF max
INTERFACE TIMING
Clock Input Frequency f
2, 4
See Figure 4 and Figure 5
50 MHz
CLK
Clock Width High tCH 10 ns min
Clock Width Low tCL 10 ns min
t
CS to Clock Setup
Clock to CS Hold
0 ns min
CSS
t
10 ns min
CSH
Data Setup tDS 5 ns min
Data Hold tDH 10 ns min
SUPPLY CHARACTERISTICS
Power Supply Range V
4.5/5.5 V min/max
DD RANGE
Positive Supply Current IDD Logic inputs = 0 V 10 µA max
Power Dissipation P
Logic inputs = 0 V 0.055 mW max
DISS
Power Supply Sensitivity PSS ΔVDD = ±5% 0.006 %/% max
Rev. F | Page 3 of 20
AD5543/AD5553 Data Sheet
Reference Multiplying Bandwidth
BW
V
= 100 mV rms, data = 0xFFFF
6.6
MHz typ
SDI
CLK
CS
t
CSH
t
CSS
t
DS
t
DH
t
CH
t
CL
D15 D14 D13 D12 D11 D10
D9 D8 D1 D0
02917-016
t
CSH
t
CSS
t
DS
t
DH
t
CH
t
CL
SDI
CLK
CS
D13 D12 D11 D10 D9 D8 D7 D6 D1 D0
02917-017
Parameter Symbol Condition 5 V ± 10% Unit
AC CHARACTERISTICS4
Output Voltage Settling Time tS To ± 0.1% of full scale, 0.5 µs typ
Data = 0x0000 to 0xFFFF to 0x0000 for AD5543
Data = 0x0000 to 0x3FFF to 0x0000 for AD5553
REF
DAC Glitch Impulse Q V
Feedthrough Error V
OUT/VREF
Digital Feedthrough Q CS = 1 and f
Total Harmonic Distortion THD V
Output Spot Noise Voltage eN f = 1 kHz, BW = 1 Hz 12 nV/√Hz
1
All static performance tests (except I
tied to the amplifier output. The +IN op amp is grounded, and the DAC I
2
These parameters are guaranteed by design and are not subject to production testing.
3
All ac characteristic tests are performed in a closed-loop system using an AD8038 I-to-V converter amplifier except for THD where an AD8065 was used.
4
All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
) are performed in a closed-loop system using an external precision OP177 I-to-V converter amplifier. The AD5543 RFB terminal is
OUT
TIMING DIAGRAMS
= 0 V, data = 0x7FFF to 0x8000 for AD5543 7 nV-sec
REF
Data = 0x0000, V
= 5 V p-p, data = 0xFFFF, f = 1 kHz −103 dB typ
REF
is tied to the −IN op amp. Typical values represent average readings measured at 25°C.
OUT
= 100 mV rms, same channel −83 dB
REF
= 1 MHz 7 nV-sec
CLK
Figure 4. AD5543 Timing Diagram
Figure 5. AD5553 Timing Diagram
Rev. F | Page 4 of 20
Data Sheet AD5543/AD5553
V(I
) to GND
−0.3 V to VDD + 0.3 V
R-8, RM-8 (Vapor Phase, 60 sec)
215°C
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
VDD to GND −0.3 V to +8 V
V
to GND −18 V to +18 V
REF
Logic Inputs to GND −0.3 V to +8 V
OUT
Input Current to Any Pin Except Supplies ±50 mA
Package Power Dissipation (T
Thermal Resistance, θJA
8-Lead Surface Mount (MSOP) 150°C/W
8-Lead Surface Mount (SOIC) 100°C/W
Maximum Junction Temperature (T
Operating Temperature Range
Model B and Model C −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature
R-8, RM-8 (Infrared, 15 sec) 220°C
) 150°C
J Max
− TA )/θJA
J Max
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. F | Page 5 of 20
AD5543/AD5553 Data Sheet
CLK
1
SDI
2
R
FB
3
V
REF
4
CS
8
V
DD
7
GND
6
I
OUT
5
AD5543/
AD5553
TOP VIEW
(Not to Scale)
02917-004
↑
L
Shift register data advanced one bit
Latched
↑
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 6. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1 CLK Clock Input. Positive-edge triggered, clocks data into shift register.
2 SDI Serial Register Input. Data loads directly into the shift register MSB first. Extra leading bits are ignored.
3 RFB Internal Matching Feedback Resistor. This pin connects to an external op amp for voltage output.
4 V
5 I
DAC Reference Input Pin. Establishes DAC full-scale voltage. Constant input resistance vs. code.
REF
OUT
DAC Current Output. This pin connects to the inverting terminal of the external precision I-to-V op amp for
voltage output.
6 GND Analog and Digital Ground.
7 VDD Positive Power Supply Input. Specified range of operation at 5 V ± 10%.
8
CS Chip Select. Active low digital input. Transfers shift-register data to DAC register on rising edge.
See Table 4 for operation.
Table 4. Control-Logic Truth Table
CLK
CS
Serial Shift Register Function DAC Register
X H No effect Latched
+1
X1 H No effect Latched
X1
1
↑+ = positive logic transition; X = don't care.
Shift register data transferred to DAC register New data loaded from serial register
+1
Rev. F | Page 6 of 20
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