ANALOG DEVICES AD5543 Service Manual

16-/14-Bit DACs

AD5543/AD5553

Rev. F

Trademarks and registered trademarks are the prop erty of their respective owner s.

16-BIT/14- BIT SHIF T

REGISTER

DAC

REGISTER

AD5543/AD5553

DAC

V

DD

V

REF

R

FB

I

OUT

CS

CLK

SDI

GND

CONTROL

LOGIC

16 OR 14

02917-001

CODE

1.0

4096

INL (LSB)

0.8

8152

12,288

16,384

20,480

24,575

28,672

32,768

36,864

40,960

45,056

49,152

53,248

57,344

61,440

65,536

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8 –1.0

0

02917-002

2

0

–2

–4

–6

–8

–10

–12

–14

10k 100k 1M 10M 100M

GAIN (dB)

FREQUENCY ( Hz )

02917-025

Data Sheet

FEATURES

16-bit resolution AD5543 14-bit resolution AD5553 ±1 LSB DNL ±1 LSB INL Low noise: 12 nV/√Hz Low power: I

0.5 µs settling time 4Q multiplying reference input 2 mA full-scale current ± 20%, with V Built-in RFB facilitates voltage conversion 3-wire interface Ultracompact 8-lead MSOP and 8-lead SOIC packages

APPLICATIONS

Automatic test equipment Instrumentation Digitally controlled calibration Industrial control PLCs

= 10 µA

DD

= 10 V

REF

Current Output/Serial Input,

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

GENERAL DESCRIPTION

The AD5543/AD5553 are precision 16-/14-bit, low power, current output, small form factor digital-to-analog converters (DACs). They are designed to operate from a single 5 V supply with a ±10 V multiplying reference.

The applied external reference, V output current. An internal feedback resistor (R R-2R and temperature tracking for voltage conversion when combined with an external op amp.

A serial-data interface offers high speed, 3-wire microcontrollercompatible inputs using serial data in (SDI), clock (CLK), and chip select (

CS

).

The AD5543/AD5553 are packaged in ultracompact (3 mm ×

4.7 mm) 8-lead MSOP and 8-lead SOIC packages.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

, determines the full-scale

REF

) facilitates the

FB

Figure 2. Integral Nonlinearity

Figure 3. Reference Multiplying Bandwidth

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com

AD5543/AD5553 Data Sheet

REVISION HISTORY

1/12—Rev. E to Rev. F

Added Figure 15, Renumbered Sequentially ................................ 8

Change to Table 9 ........................................................................... 13

Changes to Figure 27 ...................................................................... 15

Changes to Figure 28 ...................................................................... 16

Replaced Figure 29, Figure 30, and Figure 31 ............................. 17

2/11—Rev. D to Rev. E

Added Evaluation Board Section ................................................. 14

Updated Outline Dimensions ....................................................... 20

Changes to Ordering Guide .......................................................... 21

4/10—Rev. C to Rev. D

Changes to Figure 3 .......................................................................... 1

Changes to Table 1 ............................................................................ 3

Moved Timing Diagrams Section .................................................. 4

Moved Table 4 ................................................................................... 6

Delete Figure 13; Renumbered Sequentially ................................. 8

Changes to Figure 14 ........................................................................ 8

Changes to Figure 18 ........................................................................ 9

Moved Table 5 and Table 6 ............................................................ 10

Added Reference Selection Section and Amplifier Selection

Section .............................................................................................. 12

Added Table 7, Table 8, and Table 9;

Renumbered Sequentially .............................................................. 13

10/09—Rev. B to Rev. C

Updated Outline Dimensions ..................................................... 14

Changes to Ordering Guide .......................................................... 15

7/09—Rev. A to Rev. B

Updated Format .................................................................. Universal

Change to Features Section .............................................................. 1

Updated Outline Dimensions ....................................................... 14

Changes to Ordering Guide .......................................................... 15

2/03—Rev. 0 to Rev. A

Changes to Ordering Guide ............................................................. 3

12/02—Revision 0: Initial Version

Rev. F | Page 2 of 20

Data Sheet AD5543/AD5553

Resolution

N

1 LSB = V

/216 = 153 µV when V

= 10 V (AD5543)

16

Bits

Differential Nonlinearity

DNL

Monotonic

±1

LSB max

Data = 0x3FFF for AD5553

Logic Input Low Voltage

VIL 0.8

V max

SPECIFICATIONS

VDD = 5 V ± 10%, VSS = 0 V, I

Table 1.

Parameter Symbol Condition 5 V ± 10% Unit

STATIC PERFORMANCE1

1 LSB = V Relative Accuracy INL Grade: AD5553C ±1 LSB max Grade: AD5543C ±1 LSB max Grade: AD5543B ±2 LSB max

= virtual GND, GND = 0 V, V

OUT

= 10 V, TA = full operating temperature range, unless otherwise noted.

REF

/214 = 610 µV when V

REF

= 10 V (AD5553) 14 Bits

REF

Output Leakage Current I

Data = 0x0000, TA = 25°C 10 nA max

OUT

Data = 0x0000, TA = TA maximum 20 nA max Full-Scale Gain Error G

Data = 0xFFFF ±1/±4 mV typ/max

FSE

Full-Scale Temperature Coefficient2 TCVFS 1 ppm/°C typ

REFERENCE INPUT

V

Range V

REF

Input Resistance R Input Capacitance2 C

−15/+15 V min/max

REF

5 kΩ typ3

REF

5 pF typ

REF

ANALOG OUTPUT

Output Current I

Output Capacitance2 C

Data = 0xFFFF for AD5543 2 mA typ

OUT

Code dependent 200 pF typ

OUT

LOGIC INPUTS AND OUTPUT

Logic Input High Voltage VIH 2.4 V min Input Leakage Current IIL 10 µA max Input Capacitance2 CIL 10 pF max

INTERFACE TIMING

Clock Input Frequency f

2, 4

See Figure 4 and Figure 5

50 MHz

CLK

Clock Width High tCH 10 ns min Clock Width Low tCL 10 ns min

t

CS to Clock Setup Clock to CS Hold

0 ns min

CSS

t

10 ns min

CSH

Data Setup tDS 5 ns min Data Hold tDH 10 ns min

SUPPLY CHARACTERISTICS

Power Supply Range V

4.5/5.5 V min/max

DD RANGE

Positive Supply Current IDD Logic inputs = 0 V 10 µA max Power Dissipation P

Logic inputs = 0 V 0.055 mW max

DISS

Power Supply Sensitivity PSS ΔVDD = ±5% 0.006 %/% max

Rev. F | Page 3 of 20

AD5543/AD5553 Data Sheet

Reference Multiplying Bandwidth

BW

V

= 100 mV rms, data = 0xFFFF

6.6

MHz typ

SDI

CLK

CS

t

CSH

t

CSS

t

DS

t

DH

t

CH

t

CL

D15 D14 D13 D12 D11 D10

D9 D8 D1 D0

02917-016

t

CSH

t

CSS

t

DS

t

DH

t

CH

t

CL

SDI

CLK

CS

D13 D12 D11 D10 D9 D8 D7 D6 D1 D0

02917-017

Parameter Symbol Condition 5 V ± 10% Unit

AC CHARACTERISTICS4

Output Voltage Settling Time tS To ± 0.1% of full scale, 0.5 µs typ Data = 0x0000 to 0xFFFF to 0x0000 for AD5543 Data = 0x0000 to 0x3FFF to 0x0000 for AD5553

REF

DAC Glitch Impulse Q V Feedthrough Error V

OUT/VREF

Digital Feedthrough Q CS = 1 and f Total Harmonic Distortion THD V Output Spot Noise Voltage eN f = 1 kHz, BW = 1 Hz 12 nV/√Hz

1

All static performance tests (except I

tied to the amplifier output. The +IN op amp is grounded, and the DAC I

2

These parameters are guaranteed by design and are not subject to production testing.

3

All ac characteristic tests are performed in a closed-loop system using an AD8038 I-to-V converter amplifier except for THD where an AD8065 was used.

4

All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.

) are performed in a closed-loop system using an external precision OP177 I-to-V converter amplifier. The AD5543 RFB terminal is

OUT

TIMING DIAGRAMS

= 0 V, data = 0x7FFF to 0x8000 for AD5543 7 nV-sec

REF

Data = 0x0000, V

= 5 V p-p, data = 0xFFFF, f = 1 kHz −103 dB typ

REF

is tied to the −IN op amp. Typical values represent average readings measured at 25°C.

OUT

= 100 mV rms, same channel −83 dB

REF

= 1 MHz 7 nV-sec

CLK

Figure 4. AD5543 Timing Diagram

Figure 5. AD5553 Timing Diagram

Rev. F | Page 4 of 20

Data Sheet AD5543/AD5553

V(I

) to GND

−0.3 V to VDD + 0.3 V

R-8, RM-8 (Vapor Phase, 60 sec)

215°C

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

VDD to GND −0.3 V to +8 V V

to GND −18 V to +18 V

REF

Logic Inputs to GND −0.3 V to +8 V

OUT

Input Current to Any Pin Except Supplies ±50 mA Package Power Dissipation (T Thermal Resistance, θJA

8-Lead Surface Mount (MSOP) 150°C/W

8-Lead Surface Mount (SOIC) 100°C/W Maximum Junction Temperature (T Operating Temperature Range

Model B and Model C −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature

R-8, RM-8 (Infrared, 15 sec) 220°C

) 150°C

J Max

− TA )/θJA

J Max

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. F | Page 5 of 20

AD5543/AD5553 Data Sheet

CLK

1

SDI

2

R

FB

3

V

REF

4

CS

8

V

DD

7

GND

6

I

OUT

5

AD5543/

AD5553

TOP VIEW

(Not to Scale)

02917-004

↑

L

Shift register data advanced one bit

Latched

↑

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 6. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1 CLK Clock Input. Positive-edge triggered, clocks data into shift register. 2 SDI Serial Register Input. Data loads directly into the shift register MSB first. Extra leading bits are ignored. 3 RFB Internal Matching Feedback Resistor. This pin connects to an external op amp for voltage output. 4 V 5 I

DAC Reference Input Pin. Establishes DAC full-scale voltage. Constant input resistance vs. code.

REF

OUT

DAC Current Output. This pin connects to the inverting terminal of the external precision I-to-V op amp for

voltage output. 6 GND Analog and Digital Ground. 7 VDD Positive Power Supply Input. Specified range of operation at 5 V ± 10%. 8

CS Chip Select. Active low digital input. Transfers shift-register data to DAC register on rising edge.

See Table 4 for operation.

Table 4. Control-Logic Truth Table

CLK

CS

Serial Shift Register Function DAC Register

X H No effect Latched

+1 X1 H No effect Latched X1

1

↑+ = positive logic transition; X = don't care.

Shift register data transferred to DAC register New data loaded from serial register

+1

Rev. F | Page 6 of 20

Data Sheet AD5543/AD5553

CODE (Decimal )

1.0

INL (LSB)

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8 –1.0

0 65,5368192 16,384 57,34449,15240,96032,76824,576

02917-005

CODE (Decimal )

1.0

0 65,5368192

DNL (LSB)

16,384

0.8

0.6

0.4

0.2 0

–0.2

–0.4 –0.6

–0.8 –1.0

57,34449,15240,96032,76824,576

02917-006

CODE (Decimal )

1.0

0 14,336

INL (LSB)

16,384

0.8

0.6

0.4

0.2 0

–0.2

–0.4 –0.6

–0.8 –1.0

12,28810,2408192614440962048

02917-007

DNL (LSB)

CODE (Decimal )

0

–1.0

–0.8

–0.6

–0.4

–0.2

0

0.2

0.4

0.6

0.8

1.0

16,3842048 4096 14,33612,28810,24081926144

02917-008

SUPPLY VOLTAGE V

DD

(V)

1.5

1.0

–1.5

012 4

LINEARITY ERROR (LSB)

6 8

0.5

0

–0.5

–1.0

INL

DNL

GE

V

REF

= 2.5V

T

A

= 25°C

02917-009

LOGIC INPUTVOLTAGEVIH (V)

5

4

0

SUPPLY CURRENT I

DD

(mA)

3

2

1

0

0.5 1.0 5.0

VDD = 5V TA = 25°C

2.01.5 2.5 3.0 3.5 4.0 4.5

02917-010

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 7. AD5543 Integral Nonlinearity Error

Figure 8. AD5543 Differential Nonlinearity Error

Figure 10. AD5553 Differential Nonlinearity Error

Figure 11. Linearity Error vs. VD

D

Figure 9. AD5553 Integral Nonlinearity Error

Rev. F | Page 7 of 20

Figure 12. Supply Current vs. Logic Input Voltage

AD5543/AD5553 Data Sheet

CLOCK FREQUENCY ( Hz )

3.0

2.5

0

100M10k 100k

SUPPLY CURRENT ( mA)

1M 10M

2.0

1.5

1.0

0.5

02917-011

0xFFFF

0x0000

0x8000

0x5555

FREQUENCY (Hz)

90

80

30

10k

PSRR (dB)

1M

70

60

50

40

20

10

0

1k10010

V

DD

= 5V ± 10%

V

REF

= 10V

100k

02917-012

20

–160

–140

–120

–100

–80

–60

–40

–20

0

0 252015105

POWER SPECTRUM (dB)

FREQUENCY (kHz )

02917-200

5V

A2

–5V 67.72µs

DLY

2V

136ns

02917-014

–3.65

–3.70

–3.75

–3.80

–3.85

–3.90

–3.95

–4.05

–4.00

–20 –10 0 10 20 30 40

V

OUT

(V)

TIME (ns)

02917-026

Figure 13. AD5543 Supply Current vs. Clock Frequency

Figure 14. Power Supply Rejection Ratio (PSRR) vs. Frequency

Figure 16. Settling Time

Figure 17. Midscale Transition and Digital Feedthrough

Figure 15. AD5543/AD5553 Analog THD

Rev. F | Page 8 of 20

Data Sheet AD5543/AD5553

V

REF

V

DD

R

FB

I

OUT

R R R

GND

2R 2R 2R

S1S2

DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY; SWITCHE S S 1 AND S 2 ARE CLOSED, V

DD

MUST BE POWERED.

5kΩR

02917-018

02917-019

R

FB

I

OUT

1

GND

SCLK

SDIN

V

REF

V

REF

R1

SYNC

AD5543/ AD5553

V

DD

V

DD

AGND

C1

A1

R2

V

OUT

= 0 TO –V

REF

µCONTROLLER

NOTES

1. R1 AND R2 USE D ONLY IF GAIN ADJUSTME NT IS REQUIRED.

2. C1 PHAS E COMPENSATION (4pF TO 6pF) M AY BE RE QUIRED IF A1 IS A HIGH SPEED AMPLIFIER.

CIRCUIT OPERATION

The AD5543/AD5553 contain 16-/14-bit current output, DACs, serial input registers, and DAC registers. Both converters use a 3-wire serial data interface.

DAC SECTION

The DAC architecture uses a current steering R-2R ladder design. Figure 18 shows the typical equivalent DAC structure. The DAC contains a matching feedback resistor for use with an external op amp (see Figure 19). With RFB and IOUT terminals connected to the op amp output and inverting node, respectively, a precision voltage output is achieved as

V

= −V

OUT

= −V

V

OUT

Note that the output voltage polarity is the opposite of the V polarity for dc reference voltages.

These DACs are designed to operate with either negative or positive reference voltages. The V by the internal logic to drive the on and off states of the DAC switches.

× D/65,536 (AD5543) (1)

REF

× D/16,384 (AD5553) (2)

REF

power pin is only used

DD

Figure 18. Equivalent R-2R DAC Circuit

REF

Note that a matching switch is used in series with the internal 5 kΩ feedback resistor. If users attempt to measure R must be applied to V

to achieve continuity.

DD

Figure 19. Voltage Output Configuration

, power

FB

These DACs are also designed to accommodate ac reference input signals. The AD5543 accommodates input reference voltages in the range of −12 V to +12 V. The reference voltage inputs exhibit a constant nominal input resistance value of 5 kΩ ± 30%. The DAC output (I

) is code dependent, producing

OUT

various resistances and capacitances. External amplifier choice should take into account the variation in impedance generated by the AD5543 on the inverting input node of the amplifier. The feedback resistance, in parallel with the DAC ladder resistance, dominates output voltage noise. To maintain good analog performance, power supply bypassing of 0.01 µF to 0.1 µF ceramic or chip capacitors, in parallel with a 1 µF tantalum capacitor, is recommended. Due to degradation of PSRR in frequency, users must avoid using switching power supplies.

Rev. F | Page 9 of 20

AD5543/AD5553 Data Sheet

V

SERIAL DATA INTERFACE

The AD5543/AD5553 use a 3-wire (CS, SDI, CLK) serial data interface. New serial data is clocked into the serial input register in a 16-bit data-word format for the AD5543. The MSB is loaded first. Table 5 defines the 16 data-word bits. Data is placed on the SDI pin and clocked into the register on the positive clock edge of CLK, subject to the data setup-and-hold time requirements that are specified in the interface timing specifications. Only the last 16 bits clocked into the serial register are interrogated when

CS

the

pin is strobed to transfer the serial register data to the DAC register. Because most microcontrollers output serial data in 8bit bytes, two data bytes can be written to the AD5543/AD5553. After loading the serial register, the rising edge of

CS

transfers the serial register data to the DAC register; during this strobe, the CLK should not be toggled. For the AD5553, with 16-bit clock cycles, the two LSBs are ignored.

ESD PROTECTION CIRCUITS

All logic input pins contain back-biased ESD protection Zener diodes that are connected to ground (DGND) and V shown in Figure 20.

DD

, as

PCB LAYOUT AND POWER SUPPLY BYPASSING

It is a good practice to employ compact, minimum lead length PCB layout design. The leads to the input should be as short as possible to minimize IR drop and stray inductance.

It is also essential to bypass the power supplies with quality capacitors for optimum stability. Supply leads to the device should be bypassed with 0.01 μF to 0.1 μF disc or chip ceramic capacitors. Low ESR 1 μF to 10 μF tantalum or electrolytic capacitors should also be applied at the supplies to minimize transient disturbance and filter out low frequency ripple.

The PCB metal traces between V matched to minimize gain error.

DD

DIGITAL INPUTS

5kΩ

DGND

Figure 20. Equivalent ESD Protection Circuits

and RFB should also be

REF

2917-020

Table 5. AD5543 Serial Input Register Data Format; Data Loaded MSB-First Format

B15 (MSB) B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 (LSB)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Table 6. AD5553 Serial Input Register Data Format; Data Loaded MSB-First Format

B13 (MSB)1 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 (LSB)

D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

1

A full 16-bit data-word can be loaded into the AD5553 serial input register, but only the last 14 bits entered are transferred to the DAC register when CS returns to

logic high.

Rev. F | Page 10 of 20

Data Sheet AD5543/AD5553

V

DD

V

REF

V

REF

V

DD

U2

U1

AD5543/AD5553

V

O

GND

I

OUT

R

FB

AD8628

C1

02917-021

V

REF

V

DD

U2

U1

AD5543/AD5553

V

O

GND

I

OUT

R

FB

1/2AD8628

1/2AD8620

V

OUT

V

IN

GND

V+

V–

+5V

–5V

ADR03

+5V

–2.5V

U3

U4

C1

0V < V

O

< +2.5V

02917-022

V

REF

V

DD

U2

U1

AD5553 ONLY

V

O

GND

I

OUT

R

FB

1/2AD8620

V

OUT

V

IN

GND

ADR03

U3

1/2AD8620

V+

V–

+5V

–5V

+5V

U4

C1

–2.5V < V

O

< +2.5V

C2

R3

R1

10kΩ ± 0.01%

5kΩ ± 0.01%

10kΩ ± 0.01%

+5V

R2

02917-023

APPLICATIONS INFORMATION

STABILITY

Figure 21. Optional Compensation Capacitor for Gain Peaking Prevention

In the I-to-V configuration, the I

of the DAC and the inverting

OUT

node of the op amp must be connected as close as possible to each other, and proper PCB layout technique must be employed. Because every code change corresponds to a step function, gain peaking may occur if the op amp has limited GBP and there is excessive parasitic capacitance at the inverting node.

An optional compensation capacitor, C1, can be added for stability, as shown in Figure 21. C1 should be found empirically, but 20 pF is generally adequate for the compensation.

POSITIVE VOLTAGE OUTPUT

To achieve the positive voltage output, an applied negative reference to the input of the DAC is preferred over the output inversion through an inverting amplifier because of the tolerance errors of the resistors. To generate a negative reference, the reference can be level-shifted by an op amp such that the VOUT and GND pins of the reference become the virtual ground and

−2.5 V, respectively (see Figure 22).

BIPOLAR OUTPUT

The AD5543/AD5553 are inherently 2-quadrant multiplying DACs. That is, they can easily be set up for unipolar output operation. The full-scale output polarity is the inverse of the reference input voltage.

In some applications, it may be necessary to generate the full 4-quadrant multiplying capability or a bipolar output swing, which is easily accomplished by using an additional U4 external amplifier configured as a summing amplifier (see Figure 23). In this circuit, the second amplifier, U4, provides a gain of 2 that increases the output span magnitude to 5 V. Biasing the external amplifier with a 2.5 V offset from the reference voltage results in a full 4-quadrant multiplying circuit. The transfer equation of this circuit shows that both negative and positive output voltages are created as the input data (D) is incremented from code zero (V

= −2.5 V) to midscale (V

OUT

+2.5 V).

V

= (D/32,768 − 1) × V

OUT

= (D/16,384 − 1) × V

V

OUT

For the AD5543, the resistance tolerance becomes the dominant error of which users should be aware.

= 0 V) to full-scale (V

OUT

(AD5543) (3)

REF

(AD5553) (4)

REF

OUT

=

Figure 22. Positive Voltage Output Configuration

Figure 23. 4-Quadrant Multiplying Application Circuit

Rev. F | Page 11 of 20

AD5543/AD5553 Data Sheet

( )

R3

+

( )

+

U2

U1

AD5543/AD5553

V

L

GND

I

OUT

R

FB

AD8628

AD8510

V+

V–

V

REF

V

REF

LOAD

U3

V

DD

V

SS

I

L

V

DD

V

DD

C1

10pF

R2'

15kΩ

R3'

50Ω

R3

50Ω

R1'

150kΩ

R2

15kΩ

R1

150kΩ

02917-024

PROGRAMMABLE CURRENT SOURCE

Figure 24 shows a versatile V-I conversion circuit using an improved Howland current pump. In addition to the precision current conversion it provides, this circuit enables a bidirectional current flow and high voltage compliance. This circuit can be used in 4 mA to 20 mA current transmitters with up to 500 Ω of load. In Figure 24, it can be shown that if the resistor network is matched, the load current is

R1R3R2

I

=

/

REFL

R3 in theory can be made small to achieve the current needed within the U3 output current driving capability. This circuit is versatile such that

AD8510 can deliver ±20 mA in both directions

and the voltage compliance approaches 15 V, which is limited mainly by the supply voltages of U3. However, users must pay attention to the compensation. Without C1, it can be shown that the output impedance becomes

'

Z

=

O

R3R1

( ) ( )

If the resistors are perfectly matched, ZO is infinite, which is desirable, and behaves as an ideal current source. On the other hand, if they are not matched, Z Negative can cause oscillation. As a result, C1 is needed to prevent the oscillation. For critical applications, C1 could be found empirically but typically falls in the range of a few picofarads (pF).

(5)

DV

××

R2R1

'''

can be either positive or negative.

O

(6)

R3R2R1R3R2R1

+−+

REFERENCE SELECTION

When selecting a reference for use with the AD55xx series of current output DACs, pay attention to the output voltage, temperature coefficient specification of the reference. Choosing a precision reference with a low output temperature coefficient minimizes error sources. Ta b le 7 lists some of the references available from Analog Devices, Inc., that are suitable for use with this range of current output DACs.

AMPLIFIER SELECTION

The primary requirement for the current-steering mode is an amplifier with low input bias currents and low input offset voltage. Because of the code-dependent output resistance of the DAC, the input offset voltage of an op amp is multiplied by the variable gain of the circuit. A change in this noise gain between two adjacent digital fractions produces a step change in the output voltage due to the amplifier’s input offset voltage. This output voltage change is superimposed upon the desired change in output between the two codes and gives rise to a differential linearity error, which, if large enough, can cause the DAC to be nonmonotonic.

The input bias current of an op amp also generates an offset at the voltage output because of the bias current flowing in the feedback resistor, R

Common-mode rejection of the op amp is important in voltageswitching circuits because it produces a code-dependent error at the voltage output of the circuit.

Provided that the DAC switches are driven from true wideband low impedance sources (V Consequently, the slew rate and settling time of a voltageswitching DAC circuit is determined largely by the output op amp. To obtain minimum settling time in this configuration, minimize capacitance at the V in this application) of the DAC. This is done by using low input capacitance buffer amplifiers and careful board design.

Analog Devices offers a wide range of amplifiers for both precision dc and ac applications, as listed in Ta bl e 8 and Tab l e 9.

.

FB

and AGND), they settle quickly.

IN

node (the voltage output node

REF

Figure 24. Programmable Current Source with Bidirectional Current Control

and High Voltage Compliance Capabilities

Rev. F | Page 12 of 20

Data Sheet AD5543/AD5553

Table 7. Suitable Analog Devices Precision References

Maximum Temperature

Part No. Output Voltage (V) Initial Tolerance (%)

ADR01 ADR01 ADR02 ADR02 ADR03 ADR03 ADR06 ADR06 ADR420 ADR421 ADR423 ADR425 ADR431 ADR435 ADR391 ADR395

10 0.05 3 1 20 SOIC-8 10 0.05 9 1 20 TSOT-5, SC70-5

5.0 0.06 3 1 10 SOIC-8

5.0 0.06 9 1 10 TSOT-5, SC70-5

2.5 0.1 3 1 6 SOIC-8

2.5 0.1 9 1 6 TSOT-5, SC70-5

3.0 0.1 3 1 10 SOIC-8

3.0 0.1 9 1 10 TSOT-5, SC70-5

2.048 0.05 3 0.5 1.75 SOIC-8, MSOP-8

2.50 0.04 3 0.5 1.75 SOIC-8, MSOP-8

3.00 0.04 3 0.5 2 SOIC-8, MSOP-8

5.00 0.04 3 0.5 3.4 SOIC-8, MSOP-8

2.500 0.04 3 0.8 3.5 SOIC-8, MSOP-8

5.000 0.04 3 0.8 8 SOIC-8, MSOP-8

2.5 0.16 9 0.12 5 TSOT-5

5.0 0.10 9 0.12 8 TSOT-5

Table 8. Suitable Analog Devices Precision Op Amps

V

Maximum

Part No. Supply Voltage (V)

OP97 OP1177 AD8675 AD8671 ADA4004-1 AD8603 AD8607 AD8605 AD8615 AD8616

±2 to ±20 25 0.1 0.5 600 SOIC-8 , PDIP-8 ±2.5 to ±15 60 2 0.4 500 MSOP-8, SOIC-8 ±5 to ±18 75 2 0.1 2300 MSOP-8, SOIC-8 ±5 to ±15 75 12 0.077 3000 MSOP-8, SOIC-8 ±5 to ±15 125 90 0.1 2000 SOIC-8, SOT-23-5

1.8 to 5 50 0.001 2.3 40 TSOT-5

1.8 to 5 50 0.001 2.3 40 MSOP-8, SOIC-8

2.7 to 5 65 0.001 2.3 1000 WLCSP-5, SOT-23-5

2.7 to 5 65 0.001 2.4 2000 TSOT-5

2.7 to 5 65 0.001 2.4 2000 MSOP-8, SOIC-8

OS

(μV)

Drift (ppm/°C)

IB Maximum (nA)

ISS (mA) Output Noise (μV p-p) Package(s)

0.1 Hz to 10 Hz Noise (μV p-p) Supply Current (μA) Package(s)

Table 9. Suitable Analog Devices High Speed Op Amps

Part No. Supply Voltage (V) BW @ ACL (MHz) Slew Rate (V/μs) VOS (Max) (μV) IB (Max) (nA) Package(s)

AD8065 AD8066 AD8021 AD8038 ADA4899-1 AD8057 AD8058 AD8061 AD8062 AD9631

5 to 24 145 180 1500 0.006 SOIC-8, SOT-23-5 5 to 24 145 180 1500 0.006 SOIC-8, MSOP-8 5 to 24 490 120 1000 10,500 SOIC-8, MSOP-8 3 to 12 350 425 3000 750 SOIC-8, SC70-5 5 to 12 600 310 35 100 LFCSP-8, SOIC-8 3 to 12 325 1000 5000 500 SOT-23-5, SOIC-8 3 to 12 325 850 5000 500 SOIC-8, MSOP-8

2.7 to 8 320 650 6000 350 SOT-23-5, SOIC-8

2.7 to 8 320 650 6000 350 SOIC-8, MSOP-8 ±3 to ±6 320 1300 10,000 7000 SOIC-8, PDIP-8

Rev. F | Page 13 of 20

AD5543/AD5553 Data Sheet

EVALUATION BOARD

The EVAL-AD5543/EVAL-AD5553 is used in conjunction with an SDP1Z system development platform board available from Analog Devices, which is purchased separately from the evaluation board. The USB-to-SPI communication to the AD5543 is completed using this Blackfin-based development board. The software offers a waveform generator.

SYSTEM DEVELOPMENT PLATFORM

The system development platform (SDP) is a hardware and software evaluation tool for use in conjunction with product evaluation boards. The SDP board is based on the Blackfin BF527 processor with USB connectivity to the PC through a USB 2.0 high speed port. For more information about this device, see the system development platform web page

.

AD5543/AD5553 TO SPORT INTERFACE

The Analog Devices SDP has one SPORT serial port. The SPORT interface is used to control the AD5543/AD5553, allowing clock frequencies up to 30 MHz.

WAVEFORM GENERATOR

The evaluation board software offers a waveform generator to show every change introduced and transmitted to the output.

OPERATING THE EVALUATION BOARD

The evaluation board requires ±12 V and +5 V supplies. The +12 V V the +5 V is used to power the DAC (V

DD

SPORT_TFS

SPORT_TSCLK

SPORT_DTO

ADSP-BF527

Figure 25. AD5543/AD5553 to SPORT Interface

CS

SCLK

SDIN

AD5543/AD5553

02917-124

and VSS are used to power the output amplifier, while

).

DD1

02917-125

Figure 26. Evaluation Board Software—Waveform Generator

Rev. F | Page 14 of 20

Data Sheet AD5543/AD5553

02917-126

VOUT

SCLK

SDIN

/CS

AGND

+

C1

10uF

C2

0.1uF

VREF

+

C8

10uF

C9

0.1uF

C10

0.1uF

J3

C3

5.6pF

VOUT

2

3

+

6

OP

4

V-

7 V+

8

DIS

U3

+

C4

10uF

C5

0.1uF

+

C6 10uF

C7

0.1uF

J4

5

IOUT

3

RFB

6

AGND

1

SCLK2SDIN

8

CS

7

VDD

4

VREF

U1

2

+VIN

5

TRIM

6

VOUT

4

GND

U2

ADR435

J1-1

J1-5

J1-4

J1-3

J1-2

LK1

DVDD

VDD

VSS

VDD

DVDD

SCLK

SDIN

/CS

DGND

DAC + VIN FO R S DP

OP AMP + REFERENCE SUPPLY

AD5543_53

Figure 27. Schematic of AD5543/AD5553 Evaluation Board

Rev. F | Page 15 of 20

AD5543/AD5553 Data Sheet

02917-127

VIN: USE THIS PI N TO POWER THE SDP REQUIRES 4-7V 200mA

VIO: USE TO SET I O VOLTAGE MAX DRAW 20mA

BOARD ID EEPRO M (24LC64 ) MUST BE O N I2C BUS 0, ADDRESS IS AT USER DISCRETION

I2C BUS 1 IS COMMON ACROSS BO TH CONNECTORS O N SDP - PULL UP RESIST ORS REQUIRE D

BMODE1: PUL L UP WIT H A 10k RE S ISTOR T O SET SDP TO BOOT FROM A S P I FLASH O N THE DAUGHTER BOARD

(CONNECTED TO BLACKFIN G PIO - USE I2C_0 FI RST )

MAIN I2 C BUS (CONNECTED TO BLACKFIN TWI - PULL UP RESISTORS NO T REQUIRED)

CONNECTOR

STANDARD

SDP

PARALLEL

PORT

SPORT

SPI

I2C

GENERAL

INPUT/OUTPUT

TIMERS

* *

*

* * * *

*NC ON BLACKFI N S DP

120

NC

119

NC

118

GND

117

GND

116

VIO(+3.3V)

115

GND

114

PAR_D22

113

PAR_D20

112

PAR_D18

111

PAR_D16

110

PAR_D15

109

GND

108

PAR_D12

107

PAR_D10

106

PAR_D8

105

PAR_D6

104

GND

103

PAR_D4

102

PAR_D2

101

PAR_D0

100

PAR_WR

99

PAR_INT

98

GND

97

PAR_A2

96

PAR_A0

95

PAR_FS2

94

PAR_CLK

93

GND

92

SPORT_RSCLK

91

SPORT_DR0

90

SPORT_RFS

89

SPORT_TFS

88

SPORT_DT0

87

SPORT_TSCLK

86

GND

85

SPI_SEL_A

84

SPI_MOSI

83

SPI_MISO

82

SPI_CLK

81

GND

80

SDA_0

79

SCL_0

78

GPIO1

77

GPIO3

76

GPIO5

75

GND

74

GPIO7

73

TMR_B

72

TMR_D

71

NC

70

NC

69

GND

68

NC

67

NC

66

NC

65

NC

64

NC

63

GND

62

UART_TX

61

BMODE1

60

RESET_IN

59

UART_RX

58

GND

57

NC

56

NC

55

NC

54

NC

53

NC

52

GND

51

NC

50

NC

49

TMR_C

48

TMR_A

47

GPIO6

46

GND

45

GPIO4

44

GPIO2

43

GPIO0

42

SCL_1

41

SDA_1

40

GND

39

SPI_SEL1/SPI_SS

38

SPI_SEL_C

37

SPI_SEL_B

36

GND

35

SPORT_INT

34

SPORT_DT3

33

SPORT_DT2

32

SPORT_DT1

31

SPORT_DR1

30

SPORT_DR2

29

SPORT_DR3

28

GND

27

PAR_FS1

26

PAR_FS3

25

PAR_A1

24

PAR_A3

23

GND

22

PAR_CS

21

PAR_RD

20

PAR_D1

19

PAR_D3

18

PAR_D5

17

GND

16

PAR_D7

15

PAR_D9

14

PAR_D11

13

PAR_D13

12

PAR_D14

11

GND

10

PAR_D17

9

PAR_D19

8

PAR_D21

7

PAR_D23

6

GND

5

USB_VBUS

4

GND

3

GND

2

NC

1

VIN

J2

1

A0

2

A1

3

A2

4

VSS

8

VCC

7

WP

6

SCL

5

SDA

U4

24LC64

USB_VBUS

3.3V_BF

SCLK SDIN /CS

START

3.3V_BF

STATUS

Figure 28. Schematic of SDP Interface

Rev. F | Page 16 of 20

Data Sheet AD5543/AD5553

02917-128

02917-129

02917-130

Figure 29. Silkscreen—Component Side View (Top Layer)

Figure 30 Component Side Artwork

Figure 31. Solder Side Artwork

Rev. F | Page 17 of 20

AD5543/AD5553 Data Sheet

C1

Capacitor+

10 µF

RTAJ_A

10 V SMD tantalum capacitor

C12

Capacitor

0.1 µF

C0603

50 V X7R ceramic capacitor

U4

24LC64

MSO8

64K I2C serial EEPROM MSOP8

BILL OF MATERIALS

Table 10.

Name Part Description Value PCB Decal Part Description

CS AGND Testpoint Testpoint Black testpoint

C2 Capacitor 0.1 µF C0603 50 V X7R ceramic capacitor C3 Capacitor 5.6 pF C0603 Multilayer ceramic capacitor C4 Capacitor+ 10 µF R TAJ_B 16 V tantalum capacitor C5 Capacitor 0.1 µF C0603 50 V X7R ceramic capacitor C6 Capacitor+ 10 µF R TAJ_B 16 V tantalum capacitor C7 Capacitor 0.1 µF C0603 50 V X7R ceramic capacitor C8 Capacitor+ 10 µF R TAJ_B 16 V tantalum capacitor C9 Capacitor 0.1 µF C0603 50 V X7R ceramic capacitor C10 Capacitor 0.1 µF C0603 50 V X7R ceramic capacitor C11 Capacitor 10 µF C0805 10 V 10 µF ceramic capacitor 10% X5R 0805

GL1 Ground link Component link Copper short J1 CON\POWER5 CON\POWER5 5-pin terminal block J2 SDP-STANDARD-CONN CON-120/FX8-120S-SV 120-way connector, 0.6 mm pitch, receptacle J3 SMB SMB Straight PCB mount SMB jack—50 Ω J4 SMB SMB Straight PCB mount SMB jack—50 Ω SCLK Testpoint Testpoint Red testpoint SDIN Testpoint Testpoint Red testpoint U1 AD5543/AD5553 SO8NB Digital-to-analog converter U2 ADR435 SO8NB 5 V reference U3 AD8038 SO8NB Single op amp 8-pin

Testpoint Testpoint Red testpoint

USB_VBUS Testpoint Testpoint Black testpoint VOUT Testpoint Testpoint Red testpoint VREF Testpoint Testpoint Red testpoint X1 MTHOLE-3MM MTHOLE-3MM 3 mm NPTH hole X2 MTHOLE-3MM MTHOLE-3MM 3 mm NPTH hole

Rev. F | Page 18 of 20

Data Sheet AD5543/AD5553

COMPLIANT TO JEDEC STANDA

RDS MO-187-AA

6° 0°

0.80

0.55

0.40

4

8

1

5

0.65 BSC

0.40

0.25

1.10 MAX

3.20

3.00

2.80

COPLANARITY

0.

10

0.23

0.09

3.20

3.00

2.80

5.15

4.90

4.65

PIN 1

IDENTIFIER

15° MAX

0.95

0.85

0.75

0.15

0.05

10-07-2009-B

CONTROLLING DIMENSIONS

ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHE

SES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

R

EFERENCE ONLYAND ARE NOT APPROPRIATE FOR USE IN DES

IGN.

COMPLIANT TO JEDEC STANDARDSMS-012-AA

012407-A

0.25 (0.0098)

0.17 (0.0067)

1.27 (0.0500)

0.40 (0.0157)

0.50 (0.0196)

0.25 (0.0099)

45°

8° 0°

1.75 (0.0688)

1.35 (0.0532)

SEATING

PLANE

0.25 (0.0098)

0.10 (0.0040)

4

1

8 5

5.00(0.1968)

4.80(0.1890)

4.00 (0.1574)

3.80 (0.1497)

1.27 (0.0500) BSC

6.20 (0.2441)

5.80 (0.2284)

0.51 (0.0201)

0.31 (0.0122)

COPLANARITY

0.10

OUTLINE DIMENSIONS

Figure 32. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

Figure 33. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body

(R-8)

Dimensions shown in millimeters and (inches)

Rev. F | Page 19 of 20

AD5543/AD5553 Data Sheet

Model

INL (LSB)

RES (LSB)

Temperature Range

Package Description

Package Option

Branding

AD5543CRMZ-REEL7

±1

16

−40°C to +85°C

8-Lead MSOP

RM-8

DEV

ORDERING GUIDE

1, 2

AD5543CRMZ ±1 16 −40°C to +85°C 8-Lead MSOP RM-8 DEV

AD5543BR ±2 16 −40°C to +85°C 8-Lead SOIC_N R-8 AD5543BRZ ±2 16 −40°C to +85°C 8-Lead SOIC_N R-8 AD5543BRM ±2 16 −40°C to +85°C 8-Lead MSOP RM-8 DXB AD5543BRM-REEL7 ±2 16 −40°C to +85°C 8-Lead MSOP RM-8 DXB AD5543BRMZ ±2 16 −40°C to +85°C 8-Lead MSOP RM-8 DXB# AD5543BRMZ-REEL7 ±2 16 −40°C to +85°C 8-Lead MSOP RM-8 DXB# AD5553CRM ±1 14 −40°C to +85°C 8-Lead MSOP RM-8 DUC AD5553CRM-REEL7 ±1 14 −40°C to +85°C 8-Lead MSOP RM-8 DUC AD5553CRMZ ±1 14 −40°C to +85°C 8-Lead MSOP RM-8 DUC# AD5553CRMZ-REEL7 ±1 14 −40°C to +85°C 8-Lead MSOP RM-8 DUC# EVAL-AD5543SDZ Evaluation Board

1

The AD5543 contains 1040 transistors. The die size measures 55 mil × 73 mil or 4,015 sq. mil.

2

Z = RoHS Compliant Part, # denotes RoHS-compliant product may be top or bottom marked.

registered trademarks are the property of their respective owners. D02917-0-1/12(F)

Rev. F | Page 20 of 20

ANALOG DEVICES AD5543 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TIMING DIAGRAMS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

CIRCUIT OPERATION

DAC SECTION

SERIAL DATA INTERFACE

ESD PROTECTION CIRCUITS

PCB LAYOUT AND POWER SUPPLY BYPASSING

APPLICATIONS INFORMATION

STABILITY

POSITIVE VOLTAGE OUTPUT

BIPOLAR OUTPUT

PROGRAMMABLE CURRENT SOURCE

REFERENCE SELECTION

AMPLIFIER SELECTION

EVALUATION BOARD

SYSTEM DEVELOPMENT PLATFORM

AD5543/AD5553 TO SPORT INTERFACE

WAVEFORM GENERATOR

OPERATING THE EVALUATION BOARD

BILL OF MATERIALS

OUTLINE DIMENSIONS

ORDERING GUIDE