ANALOG DEVICES AD5541A Service Manual

2.7 V to 5.5 V, Serial-Input,

VDDV

V

S

Voltage Output, Unbuffered 16-Bit DAC

FEATURES

16-bit resolution

11.8 nV/√Hz noise spectral density
1 μs settling time

1.1 nV-sec glitch energy

0.05 ppm/°C temperature drift
5 kV HBM ESD classification

0.375 mW power consumption at 3 V

2.7 V to 5.5 V single-supply operation
Hardware
50 MHz SPI-/QSPI-/MICROWIRE-/DSP-compatible interface
Power-on reset clears DAC output to zero scale
Available in 3 mm × 3 mm, 8-/10-lead LFCSP and 10-lead

MSOP

APPLICATIONS

Automatic test equipment
Precision source-measure instruments
Data acquisition systems
Medical instrumentation
Aerospace instrumentation
Communications infrastructure equipment
Industrial control

CS

and

LDAC

functions

FUNCTIONAL BLOCK DIAGRAMS

REF

LOGIC

CS

DIN
SCLK
LDAC

REF

CS

DIN

CLK
CLR

AD5541A

CONTROL

LOGIC

AD5541A-1

CONTROL

LOGIC

Figure 1. AD5541A

16-BIT DAC

16-BIT DAC LATCH

SERIAL INPUT REGISTER

DGND

DD

16-BIT DAC

16-BIT DAC LATCH

SERIAL INPUT REGISITER

AD5541A

V

OUT

AGND

08516-001

V

OUT

GENERAL DESCRIPTION

The AD5541A is a single, 16-bit, serial input, unbuffered voltage
output digital-to-analog converter (DAC) that operates from a
single 2.7 V to 5.5 V supply.

The DAC output range extends from 0 V to V
monotonic, providing ±1 LSB INL accuracy at 16 bits without
adjustment over the full specified temperature range of −40°C
to +125°C. The AD5541A is available in a 3 mm × 3 mm, 10-lead
LFCSP and 10-lead MSOP. The AD5541A-1 is available in a
3 mm × 3 mm, 8-lead LFCSP.

Offering unbuffered outputs, the AD5541A achieves a 1 µs set­tling time with low power consumption and low offset errors.
Providing low noise performance of 11.8 nV/√Hz and low
glitch, the AD5541A is suitable for deployment across multiple
end systems.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

and is guaranteed

REF

GND

Figure 2. AD5541A-1

The AD5541A uses a versatile 3-wire interface that is compatible
with 50 MHz SPI, QSPI™, MICROWIRE™, and DSP interface
standards.

Table 1. Related Devices

Part No. Description

AD5040/AD5060 2.7 V to 5.5 V 14-/16-bit buffed output DACs
AD5541/AD5542 2.7 V to 5.5 V 16-bit voltage output DACs
AD5781/AD5791 18-/20-bit voltage output DACs
AD5024/AD5064 4.5 V to 5.5 V, 12-/16-bit quad channel DACs
AD5061 Single, 16-bit nanoDAC, ±4 LSB INL, SOT-23
AD5542A 16-bit, bipolar, voltage output DAC

PRODUCT HIGHLIGHTS

1. 16-bit performance without adjustment.

2. 2.7 V to 5.5 V single operation.

3. Low 11.8 nV/√Hz noise spectral density.

4. Low 0.05 ppm/°C temperature drift.

5. 3 mm × 3 mm LFCSP and MSOP packaging.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2010–2011 Analog Devices, Inc. All rights reserved.

08516-002

AD5541A

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagrams............................................................. 1

General Description......................................................................... 1

Product Highlights........................................................................... 1

Revision History ...............................................................................2

Specifications..................................................................................... 3

AC Characteristics........................................................................ 4

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configurations and Function Descriptions........................... 7

Typical Performance Characteristics............................................. 9

Terminology .................................................................................... 13

Theory of Operation ......................................................................14

Digital-to-Analog Section .........................................................14

Serial Interface............................................................................ 14

Unipolar Output Operation...................................................... 15

Output Amplifier Selection....................................................... 15

Force Sense Amplifier Selection............................................... 16

Reference and Ground............................................................... 16

Power-On Reset.......................................................................... 16

Power Supply and Reference Bypassing.................................. 16

Applications Information.............................................................. 17

Microprocessor Interfacing....................................................... 17

AD5541A to ADSP-BF531 Interface ....................................... 17

AD5541A to SPORT Interface.................................................. 17

Layout Guidelines....................................................................... 17

Galvanically Isolated Interface ................................................. 17

Decoding Multiple DACs.......................................................... 18

Outline Dimensions....................................................................... 19

Ordering Guide .......................................................................... 20

REVISION HISTORY

3/11—Rev. 0 to Rev. A

Added 10-Lead LFCSP and 8-Lead LFCSP.....................Universal

Changes to Features, General Description, and Product

Highlights Sections and Table 1 ..................................................... 1

Added Figure 2; Renumbered Sequentially .................................. 1

Changes to Logic Inputs Parameter, Table 1 ................................. 3

Changes to Figure 3.......................................................................... 5

Changes to Table 5............................................................................ 6

Changes to Table 6............................................................................ 7

Added Figure 5 and Figure 6............................................................8

Added Table 7; Renumbered Sequentially .....................................8

Changes to Figure 15...................................................................... 10

Changed V

Section.............................................................................................. 15

Updated Outline Dimensions....................................................... 18

Changes to Ordering Guide.......................................................... 18

7/10—Revision 0: Initial Version

REF

to V

– 1 LSB in Unipolar Output Operation

REF

Rev. A | Page 2 of 20

AD5541A

SPECIFICATIONS

VDD = 2.7 V to 5.5 V, 2.5 V ≤ V

Table 2.

Parameter Min Typ Max Unit Test Condition

STATIC PERFORMANCE

Resolution 16 Bits
Relative Accuracy (INL) ±0.5 ±1.0 LSB B grade
±0.5 ±2.0 LSB A grade
Differential Nonlinearity (DNL) ±0.5 ±1.0 LSB Guaranteed monotonic

Gain Error 0.5 ±2 LSB TA = 25°C
±3 LSB −40°C < TA < +85°C
±4 LSB −40°C < TA < +125°C
Gain Error Temperature Coefficient ±0.1 ppm/°C
Zero-Code Error 0.3 ±0.7 LSB TA = 25°C
±1.5 LSB −40°C < TA < +85°C
±3 LSB −40°C < TA < +125°C
Zero-Code Temperature Coefficient ±0.05 ppm/°C
DC Power Supply Rejection Ratio ±1 LSB ∆VDD ± 10%

OUTPUT CHARACTERISTICS

Output Voltage Range 0 V
DAC Output Impedance 6.25 kΩ Tolerance typically 20%

DAC REFERENCE INPUT

3

Reference Input Range 2.0 VDD V
Reference Input Resistance 9 kΩ Unipolar operation
Reference Input Capacitance 26 pF Code 0x0000
26 pF Code 0xFFFF

LOGIC INPUTS

Input Current ±1 A
Input Low Voltage, V

0.4 V

INL

0.8 V
Input High Voltage, V

INH

1.8 V

1.3 V
Input Capacitance2 10 pF
Hysteresis Voltage2 0.15 V

POWER REQUIREMENTS

VDD 2.7 5.5 V All digital inputs at 0 V, V
IDD 125 150 µA VIH = V
V

1.8 5.5 V

LOGI C

I

15 24 µA All digital inputs at 0 V, V

LOGI C

Power Dissipation 0.625 0.825 mW

1

For 2.7 V ≤ V

2

Guaranteed by design, but not subject to production test.

3

Reference input resistance is code-dependent, minimum at 0x8555.

≤ 5.5 V: −40°C < TA < +125°C. For 1.8 V ≤ V

LOGIC

≤ VDD, AGND = DGND = 0 V, −40°C < TA < +125°C,1 unless otherwise noted.

REF

2

− 1 LSB V Unipolar operation

REF

V

= 1.8 V to 5.5 V

LOGIC

V

= 2.7 V to 5.5 V

LOGIC

V

2.4 V

≤ 2.7 V: −40°C < TA < +105°C.

LOGIC

= 4.5 V to 5.5 V

LOGIC

V

= 2.7 V to 3.6 V

LOGIC

V

= 1.8 V to 2.7 V

LOGIC

or VDD and VIL = GND

LOGI C

LOGI C

LOGI C

, or VDD

, or VDD

Rev. A | Page 3 of 20

AD5541A

AC CHARACTERISTICS

VDD = 2.7 V to 5.5 V, 2.5 V ≤ V

Table 3.

Parameter Min Typ Max Unit Test Condition

Output Voltage Settling Time 1 s To ½ LSB of full scale, CL = 10 pF
Slew Rate 17 V/s CL = 10 pF, measured from 0% to 63%
Digital-to-Analog Glitch Impulse 1.1 nV-sec 1 LSB change around major carry
Reference −3 dB Bandwidth 2.2 MHz All 1s loaded
Reference Feedthrough 1 mV p-p All 0s loaded, V
Digital Feedthrough 0.2 nV-sec
Signal-to-Noise Ratio 92 dB
Spurious Free Dynamic Range 80 dB Digitally generated sine wave at 1 kHz
Total Harmonic Distortion 74 dB

Output Noise Spectral Density 11.8 nV/√Hz DAC code = 0x0000, frequency = 1 kHz
Output Noise 0.134 V p-p 0.1 Hz to 10 Hz

≤ VDD, AGND = DGND = 0 V, −40°C < TA < +125°C, unless otherwise noted.

REF

DAC code = 0xFFFF, frequency 10 kHz,

= 2.5 V ± 1 V p-p

V

REF

= 1 V p-p at 100 kHz

REF

Rev. A | Page 4 of 20

AD5541A

TIMING CHARACTERISTICS

VDD = 5 V, 2.5 V ≤ V
noted.

Table 4.

Parameter

f

SCLK

1, 2

14 50 MHz max SCLK cycle frequency
t1 70 20 ns min SCLK cycle time
t2 35 10 ns min SCLK high time
t3 35 10 ns min SCLK low time
t4 5 5 ns min
t5 5 5 ns min
t6 5 5 ns min
t7 10 5 ns min
t8 35 10 ns min Data setup time
t9 5 4 ns min Data hold time (V
t9 5 5 ns min Data hold time (V
t10 20 20 ns min
t11 10 10 ns min
t12 15 15 ns min

1

Guaranteed by design and characterization. Not production tested.

2

All input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (V

SCLK

REF

Limit at

1.8 ≤ V

CS

≤ VDD, V

≤ 2.7 V

LOGIC

t

12

= 90% of V

INH

t

6

t

4

t

8

t

9

LOGIC

Limit at

2.7 V ≤ V

, V

LOGIC

INL

≤ 5.5 V

t

2

= 10% of V

t

1

t

, AGND = DGND = 0 V, −40°C < TA < +105°C, unless otherwise

LOGIC

Unit Description

low to SCLK high setup

CS

high to SCLK high setup

CS
SCLK high to CS
SCLK high to CS

pulse width

LDAC

high to LDAC low setup

CS

high time between active periods

CS

+ V

)/2.

INL

INH

3

t

5

t

7

low hold time
high hold time

= 90% of VDD, V

INH

= 3 V, V

INH

INL

= 0 V)

= 10% of VDD)

INL

DIN

LDAC

DB15

t

11

t

10

08516-003

Figure 3. Timing Diagram

Rev. A | Page 5 of 20

AD5541A

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 5.

Parameter Rating

VDD to AGND −0.3 V to +6 V
V

to DGND −0.3 V to +6 V

LOGI C

Digital Input Voltage to DGND

−0.3 V to V

DD/VLOGI C

+

0.3 V

V

to AGND −0.3 V to VDD + 0.3 V

OUT

AGND to DGND −0.3 V to +0.3 V
Input Current to Any Pin Except Supplies ±10 mA
Operating Temperature Range

Industrial (A, B Versions) −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature (TJ max) 150°C
Package Power Dissipation (TJ max − TA)/θJA
Thermal Impedance, θJA

LFCSP (CP-10-9) 50°C/W

LFCSP (CP-8-11) 62°C/W

MSOP (RM-10) 135°C/W
Lead Temperature, Soldering

Peak Temperature1 260°C

2

ESD

1

As per JEDEC Standard 20.

2

Human body model (HBM) classification.

5 kV

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. A | Page 6 of 20