ANALOG DEVICES AD5446 Service Manual

Multiplying DACs with Serial Interface

AD5444/AD5446

Rev. D

Trademarks and registered trademarks are the property of their respective owners.

04588-001

POWER-ON

RESET

GND

V

REF

R

FB

I

OUT

1

I

OUT

2

R

SDO

CONTROL LOGIC AND

INPUT SHIFT REGISTER

DAC REGIST E R

12-BIT

R-2R DAC

INPUT LATCH

SCLK

SDIN

SYNC

V

DD

AD5444/

AD5446

Data Sheet

FEATURES

12 MHz multiplying bandwidth
INL of ± 0.5 LSB at 12 bits
Pin-compatible 12-/14-bit current output DAC

2.5 V to 5.5 V supply operation
10-lead MSOP package
±10 V reference input
50 MHz serial interface

2.7 MSPS update rate
Extended temperature range: −40°C to +125°C
4-quadrant multiplication
Power-on reset with brownout detection

0.4 µA typical current consumption
Guaranteed monotonic

APPLICATIONS

Portable, battery-powered applications
Waveform generators
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally controlled calibration
Programmable filters and oscillators
Composite video
Ultrasound
Gain, offset, and voltage trimming
Automotive radar

12-/14-Bit High Bandwidth

GENERAL DESCRIPTION

The AD5444/AD54461 are CMOS 12-bit and 14-bit, current
output, digital-to-analog converters (DACs). Operating from a
single 2.5 V to 5.5 V power supply, these devices are suited for
battery-powered and other applications.

As a result of the CMOS submicron manufacturing process,
these parts offer excellent 4-quadrant multiplication char­acteristics of up to 12 MHz.

These DACs use a double-buffered, 3-wire serial interface that
is compatible with SPI®, QSPI™, MICROWIRE™, and most DSP
interface standards. On power-up, the internal shift register and
latches are filled with 0s, and the DAC output is at zero scale.

The applied external reference input voltage (V
the full-scale output current. These parts can handle ±10 V
inputs on the reference, despite operating from a single-supply
power supply of 2.5 V to 5.5 V. An integrated feedback resistor
(R

) provides temperature tracking and full-scale voltage output

FB

when combined with an external current-to-voltage precision
amplifier. The AD5444/AD5446 DACs are available in small
10-lead MSOP packages, which are pin-compatible with the

AD5425/AD5426/AD5432/AD5443 family of DACs.

The E VA L-AD5446SDZ board is available for evaluating DAC
performance. For more information, see the UG-327 evaluation
board user guide.

1

US Patent Number 5,689,257.

) determines

REF

FUNCTIONAL BLOCK DIAGRAM

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Figure 1.

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Tel: [phone]
Fax: [phone] ©2004–2012 A

nalog Devices, Inc. All rights reserved.

www.analog.com

AD5444/AD5446 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings ............................................................ 6

ESD Caution .................................................................................. 6

Pin Configuration and Function Descriptions ............................. 7

Typical Performance Characteristics ............................................. 8

Terminology .................................................................................... 14

General Description ....................................................................... 15

REVISION HISTORY

4/12—Rev. C to Rev. D

Changes to General Description Section ...................................... 1

Deleted Evaluation Board for the DAC Section ......................... 23

Deleted Power Supplies for the Evaluation Board Section ....... 23

Deleted Figure 54; Renumbered Sequentially............................. 24

Deleted Figure 55 and Figure 56 ................................................... 25

Updated Outline Dimensions ....................................................... 25

Changes to Ordering Guide .......................................................... 25

Deleted Figure 57 ............................................................................ 26

4/07—Rev. B to Rev. C

Changes to Table 9 ................................

Changes to Ordering Guide .......................................................... 28

Changes to Features .......................................................................... 1

Changes to General Description .................................................... 1

Changes to Table 1 ............................................................................ 3

Changes to Figure 22 ...................................................................... 10

Changes to Figure 23 ...................................................................... 10

Changes to Table 9 .......................................................................... 19

Changes to Table 1 2 ........................................................................ 27

Updated Outline Dimensions ....................................................... 28

Changes to Ordering Guide .......................................................... 28

.......................................... 19

DAC Section................................................................................ 15

Circuit Operation ....................................................................... 15

Single-Supply Applications ....................................................... 17

Adding Gain ................................................................................ 17

Divider or Programmable Gain Element ................................ 17

Amplifier Selection .................................................................... 18

Reference Selection .................................................................... 18

Serial Interface ................................................................................ 20

Microprocessor Interfacing ....................................................... 21

PCB Layout and Power Supply Decoupling ................................ 23

Overview of AD54xx and AD55xx Current Output Devices ... 24

Outline Dimensions ....................................................................... 25

Ordering Guide .......................................................................... 25

4/05—Rev. 0 to Rev. A

Added AD5446 ................................................................... Universal

Changes to Features .......................................................................... 1

Changes to General Description ..................................................... 1

Changes to Specifications ................................................................. 3

Inserted Figure 7; Renumbered Sequentially................................. 9

Inserted Figure 9; Renumbered Sequentially................................. 9

Inserted Figure 13; Renumbered Sequentially ........................... 10

Changes to Figure 22 ...................................................................... 11

Changes to Figure 23 ...................................................................... 11

Changes to Serial Interface ............................................................ 20

Changes to Figure 44 ...................................................................... 20

Changes to Figure 45 ...................................................................... 20

Updated Outline Dimensions ....................................................... 28

Changes to Ordering Guide .......................................................... 28

10/04—Revision 0: Initial Version

Rev. D | Page 2 of 28

Data Sheet AD5444/AD5446

STATIC PERFORMANCE

Total Unadjusted Error (TUE)

±1

LSB

OUT

OUT

REF

RFB Feedback Resistance

7 9 11

kΩ

Input resistance TC = −50 ppm/°C

Output High Voltage, VOH

VDD − 1

V

VDD = 4.5 V to 5 V, I

SOURCE

= 200 µA

SOURCE

SINK

SINK

±10

nA

TA = −40°C to +125°C

SPECIFICATIONS

VDD = 2.5 V to 5.5 V, V
unless otherwise noted. DC performance measured with OP177, and ac performance measured with AD8038, unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit Conditions

AD5444

Resolution 12 Bits
Relative Accuracy ±0.5 LSB
Differential Nonlinearity ±1 LSB Guaranteed monotonic

Gain Error ±0.5 LSB

AD5446

Resolution 14 Bits
Relative Accuracy ±2 LSB
Differential Nonlinearity −1/+2 LSB Guaranteed monotonic
Total Unadjusted Error (TUE) ±4 LSB

Gain Error ±2.5 LSB
Gain Error Temperature Coefficient1 ±2 ppm FSR/°C
Output Leakage Current ±1 nA Data = 0x0000, TA = 25°C, I

±10 nA Data = 0x0000, TA = −40°C to +125°C, I
REFERENCE INPUT1

Reference Input Range ±10 V
V

Input Resistance 7 9 11 kΩ Input resistance TC = −50 ppm/°C

= 10 V, I

REF

2 = 0 V. Temperature range for Y version: −40°C to +125°C. All specifications T

OUT

1

MIN

to T

MAX

,

1

Input Capacitance

Zero-Scale Code 18 22 pF
Full-Scale Code 18 22 pF

DIGITAL INPUTS/OUTPUTS1

Input High Voltage, VIH 2.0 V VDD = 3.6 V to 5 V

1.7 V VDD = 2.5 V to 3.6 V
Input Low Voltage, VIL 0.8 V VDD = 2.7 V to 5.5 V

0.7 V VDD = 2.5 V to 2.7 V

VDD − 0.5 V VDD = 2.5 V to 3.6 V, I
Output Low Voltage, VOL 0.4 V VDD = 4.5 V to 5 V, I

0.4 V VDD = 2.5 V to 3.6 V, I
Input Leakage Current, IIL ±1 nA TA = 25°C

Input Capacitance 10 pF

= 200 µA

= 200 µA

= 200 µA

Rev. D | Page 3 of 28

AD5444/AD5446 Data Sheet

REF

REF

64

dB

1 MHz

Measured to ±16 mV of FS

16

33

ns

REF

LOAD

REF

OUT

OUT

alternate loading of all 0s and all 1s

REF

REF

OUT

OUT

REF

OUT

OUT

REF

OUT

OUT

Intermodulation Distortion

79 dB

f1 = 20 kHz, f2 = 25 kHz, clock = 1 MHz, V

REF

= 3.5 V

Power Supply Range, VDD

2.5 5.5 V

Parameter Min Typ Max Unit Conditions

DYNAMIC PERFORMANCE1

Reference Multiplying Bandwidth 12 MHz V
Multiplying Feedthrough Error V
72 dB 100 kHz

44 dB 10 MHz
Output Voltage Settling Time V

Measured to ±1 mV of FS 100 110 ns
Measured to ±4 mV of FS 24 40 ns

Digital Delay 20 40 ns Interface delay time
10%-to-90% Settling Time 10 30 ns Rise and fall time, V
Digital-to-Analog Glitch Impulse 2 nV-s 1 LSB change around major carry, V
Output Capacitance

I

1 13 pF DAC latches loaded with all 0s
28 pF DAC latches loaded with all 1s
I

2 18 pF DAC latches loaded with all 0s

5 pF DAC latches loaded with all 1s

Digital Feedthrough 0.5 nV-s Feedthrough to DAC output with CS high and

= ±3.5 V, DAC loaded with all 1s
= ±3.5 V, DAC loaded with all 0s

= 10 V, R

REF

= 100 Ω, DAC latch alternately

LOAD

loaded with 0s and 1s

= 10 V, R

= 100 Ω

= 0 V

Analog THD 83 dB V
Digital THD Clock = 1 MHz, V

50 kHz f
20 kHz f

71 dB
77 dB

= 3.5 V p-p, all 1s loaded, f = 1 kHz

= 3.5 V

Output Noise Spectral Density 25 nV/√Hz @ 1 kHz
SFDR Performance (Wide Band) Clock = 10 MHz, V

50 kHz f
20 kHz f

78 dB
74 dB

SFDR Performance (Narrow Band) Clock = 1 MHz, V

50 kHz f
20 kHz f

87 dB
85 dB

= 3.5 V

= 3.5 V

POWER REQUIREMENTS

Supply Current, IDD 0.4 10 µA TA = −40°C to +125°C, logic inputs = 0 V or VDD

0.6 µA TA = 25°C, logic inputs = 0 V or VDD
Power Supply Sensitivity1 0.001 %/% ∆VDD = ±5%

1

Guaranteed by design and characterization; not subject to production test.

Rev. D | Page 4 of 28

Data Sheet AD5444/AD5446

S

TIMING CHARACTERISTICS

All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V,
V

= 10 V, I

REF

Table 2.

Parameter1

f

50 50 MHz max Maximum clock frequency.

SCLK

t1 20 20 ns min SCLK cycle time.
t2 8 8 ns min SCLK high time.
t3 8 8 ns min SCLK low time.
t4 8 8 ns min

t5 5 5 ns min Data setup time.
t6 4.5 4.5 ns min Data hold time.
t7 5 5 ns min
t8 30 30 ns min

t9 23 30 ns min SCLK active edge to SDO valid.
Update Rate 2.7 2.7 MSPS

1

Guaranteed by design and characterization; not subject to production test.

2 = 0 V, temperature range for Y version: −40°C to +125°C; all specifications T

OUT

V

= 4.5 V to

DD

5.5 V

VDD = 2.5 V to

5.5 V Unit Conditions/Comments

falling edge to SCLK active edge setup time.

SYNC

rising edge to SCLK active edge setup time

SYNC
Minimum SYNC

high time.

Consists of cycle time, SYNC
voltage settling time.

t

1

SCLK

t

SYNC

SDIN

t

4

t

8

DB15 DB0

t

6

t

5

2

Figure 2. Standalone Timing Diagram

t

3

t

7

to T

MIN

, unless otherwise noted.

MAX

high time, data setup time and output

4588-002

t

1

SCLK

t

t

4

YNC

t

6

t

5

SDIN

SDO

NOTES
ALTERNATIVELY, DATA CAN BE CLOCKED INTO INPUT SHIF T REGIS TER ON RISI NG EDGE OF SCLK AS
DETERMINED BY CO NTROL BITS. IN THIS CASE, DATA I S CLOCKED OUT OF SDO O N FALLI NG
EDGE OF SCLK. TIMING AS ABOVE, WITH SCLK INVERTED.

DB15 (N) DB0 (N)

2

t

3

DB15

(N + 1)

t

9

DB15 (N)

Figure 3. Daisy-Chain Timing Diagram

Rev. D | Page 5 of 28

DB0

(N + 1)

DB0 (N)

t

7

t

8

04588-003

AD5444/AD5446 Data Sheet

REF

OUT

OUT

Extended (Y Version)

I

OL

200µA

TO

OUTPUT

PIN

200µA

I

OH

C

L

20pF

V

OH (MIN)

+V

OL (MAX)

2

04588-004

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Transient currents of up to
100 mA do not cause SCR latch-up.

Table 3.

Parameter Rating
VDD to GND −0.3 V to +7 V
V

, RFB to GND −12 V to +12 V

I

1, I

2 to GND −0.3 V to +7 V
Logic Inputs and Outputs1 −0.3 V to VDD + 0.3 V
Input Current (All Pins Except Supplies) ±10 mA
Operating Temperature Range −40°C to +125°C

Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
10-lead MSOP θJA Thermal Impedance 206°C/W
Lead Temperature, Soldering (10 sec) 300°C
IR Reflow, Peak Temperature (<20 sec) 235°C

1

Overvoltages at SCLK,

SYNC

, and SDIN are clamped by internal diodes.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Only one absolute maximum rating can be applied at any one
time.

Figure 4. Load Circuit for SDO Timing Specifications

ESD CAUTION

Rev. D | Page 6 of 28

Data Sheet AD5444/AD5446

04588-005

10

9

8

7

6

1

2

3

4

5

I

OUT

1

I

OUT

2

GND

SCLK

SDIN

R

FB

V

REF

V

DD

SDO

AD5444/

AD5446

TOP VIEW

(Not to Scale)

SYNC

Pin No.

Mnemonic

Description

OUT

OUT

REF

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 5. Pin Configuration

Table 4. Pin Function Descriptions

1 I
2 I

1 DAC Current Output.

2 DAC Analog Ground. This pin should normally be tied to the analog ground of the system.
3 GND Ground Pin.
4 SCLK Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock

input. Alternatively, by means of the serial control bits, the device can be configured such that data is clocked
into the shift register on the rising edge of SCLK.

5 SDIN Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input.

By default on power-up, data is clocked into the shift register on the falling edge of SCLK. The control bits allow
the user to change the active edge to the rising edge.

6

Active Low Control Input. This is the frame synchronization signal for the input data. When

SYNC

is taken low,

SYNC
data is loaded to the shift register on the active edge of the following clocks. The output updates on the rising
edge of

SYNC

.

7 SDO Serial Data Output. This pin allows a number of parts to be daisy-chained. By default, data is clocked into the shift

register on the falling edge and out via SDO on the rising edge of SCLK. Data is always clocked out on the
alternate edge to data loaded to the shift register.

8 VDD Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V.
9 V

DAC Reference Voltage Input.

10 RFB DAC Feedback Resistor. Establishes voltage output for the DAC by connecting to an external amplifier output.

Rev. D | Page 7 of 28

AD5444/AD5446 Data Sheet

–0.5

–0.4

–0.3

–0.2

–0.1

0

0.1

0.2

0.3

0.4

0.5

0 512 1024 1536 2048 2560 3072 3584 4096

CO

DE

INL (LSB)

TA = 25°C
V

REF

= 10V

V

DD

= 5V

04588-006

2.0

–2.0

–1.6

–1.2

–0.8

–0.4

0

0.4

0.8

1.2

1.6

0 2048 4096 6144 8192 10240 12288 14336 16384

04588-076

CODE

INL (LSB)

T

A

= 25°C

V

REF

= 10V

V

DD

= 5V

–1.0

–0.8

–0.6

–0.4

–0.2

0

0.2

0.4

0.6

0.8

1.0

0 512 1024 1536 2048 2560 3072 3584 4096

CODE

DNL (LSB)

T

A

= 25°C

V

REF

= 10V

V

DD

= 5V

04588-008

2.0

–2.0

–1.6

–1.2

–0.8

–0.4

0

0.4

0.8

1.2

1.6

0 2048 4096 6144 8192 10240 12288 14336 16384

04588-077

CODE

DNL (LSB)

TA = 25°C
V

REF

= 10V

V

DD

= 5V

–1.00

–0.75

–0.50

–0.25

0

0.25

0.50

0.75

1.00

2 3 4 5 6 7 8 9 10

REFERENCE VOLTAGE (V)

INL (L

SB)

TA = 25°C
V

DD

= 5V

AD5444

04588-047

MAX INL

MIN INL

–2.0

–1.5

–1.0

–0.5

0

0.5

1.0

1.5

2.0

2 3 4 5 6 7 8 9 10

REFERENCE VOLTAGE (V)

DNL (LSB)

TA = 25°C
V

DD

= 5V

AD5444

04588-048

MAX DNL

MIN DNL

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 6. INL vs. Code (12-Bit DAC)

Figure 7. INL vs. Code (14-Bit DAC)

Figure 9. DNL vs. Code (14-Bit DAC)

Figure 10. INL vs. Reference Voltage

Figure 8. DNL vs. Code (12-Bit DAC)

Figure 11. DNL vs. Reference Voltage

Rev. D | Page 8 of 28

Data Sheet AD5444/AD5446

–1.0

–0.8

–0.6

–0.4

–0.2

0

0.2

0.4

0.6

0.8

1.0

0 512 1024 1536 2048 2560 3072 3584 4096

CODE

TUE (LSB)

T

A

= 25°C

V

REF

= 10V

V

DD

= 5V

04588-013

2.0

–2.0

–1.6

–1.2

–0.8

–0.4

0

0.4

0.8

1.2

1.6

0 2048 4096 6144 8192 10240 12288 14336 16384

04588-078

CODE

INL (LSB)

T

A

= 25°C

V

REF

= 10V

V

DD

= 5V

–2.0

–1.5

–1.0

0

1.0

1.5

2.0

2 3 4 5 8 9 10

R

EFERENCE VOLTAGE (V)

TUE (LSB)

04588-052

76

MAX TUE

–0.5

0.5

TA = 25°C
V

DD

= 5V

AD5444

MIN TUE

–0.3

–0.2

–0.1

0

0.1

0.2

0.3

–60 –40 –20 0 60 80 100 120 140

TEMPERATURE (°C)

GAIN ERROR (LSB)

V

REF

= 10V

04588-049

4020

VDD = 5V

VDD = 3V

–2.0

–1.5

–1.0

0

1.0

1.5

2.0

2 3 4 5 8 9 10

REFERENCE VOLTAGE (V)

GAIN ERROR ( LSB)

04588-051

76

–0.5

0.5

T

A

= 25°C

V

DD

= 5V

AD5444

I

OUT

1, VDD = 3V

I

OUT

1, VDD = 5V

–40 –20 0 20 40 60 80 100 120

TEMPERATURE (°C)

2.0

1.6

1.2

0.8

0.4

0

I

OUT

1 LEAKAGE (nA)

04588-017

Figure 12. TUE vs. Code (12-Bit DAC)

Figure 13. TUE vs. Code (14-Bit DAC)

Figure 15. Gain Error vs. Temperature

Figure 16. Gain Error vs. Reference Voltage

Figure 14. TUE vs. Reference Voltage

Figure 17. I

1 Leakage Current vs. Temperature

OUT

Rev. D | Page 9 of 28