Analog Devices AD5444 6 prb Datasheet

PRELIMINARY TECHNICAL DA T A

12/14-Bit High Bandwidth

a

Preliminary Technical Data

FEATURES
+2.5 V to +5.5 V Supply Operation
50MHz Serial Interface
10MHz Multiplying Bandwidth
±10V Reference Input
10-Lead MSOP Packages
Pin Compatible 12 and 14 Bit Current Output DACs
Extended Temperature range –40°C to +125°C
Guaranteed Monotonic
Four Quadrant Multiplication
Power On Reset with brownout detection

µµ

<0.5

µA typical Current Consumption

µµ

APPLICATIONS
Portable Battery Powered Applications
Waveform Generators
Analog Processing
Instrumentation Applications
Programmable Amplifiers and Attenuators
Digitally-Controlled Calibration
Programmable Filters and Oscillators
Composite Video
Ultrasound
Gain, offset and Voltage Trimming

Multiplying DACs with Serial Interface

AD5444/AD5446*

FUNCTIONAL BLOCK DIAGRAM

V

REF

12/14

BIT

R-2R DAC

DAC REGISTER

INPUT LATCH

CONTROL LOGIC &

INPUT SHIFT REGISTER

GND

R

R

FB

I

OUT1

I

OUT2

SDO

SYNC
SCLK
SDIN

AD5444/
AD5446

Power On

Reset

V

DD

GENERAL DESCRIPTION

The AD5444/5446 are CMOS 12 and 14-bit Current
Output digital-to-analog converters respectively.

These devices operate from a +2.5 V to 5.5 V power sup­ply, making them suited to battery powered applications
and many other applications.

These DACs utilize double buffered 3-wire serial interface
that is compatible with SPI

TM

, QSPITM, MICROWIRE

TM

The applied external reference input voltage (V
mines the full scale output current. An integrated feedback
resistor (R
voltage output when combined with an external Current to
Voltage precision amplifier.

The AD5444/5446 DACs are available in small 10-lead
MSOP packages.

and most DSP interface standards.
On power-up, the internal shift register and latches are

filled with zeros and the DAC output is at zero scale.
As a result of manufacture on a CMOS sub micron

process, they offer excellent four quadrant multiplication
characteristics, with large signal multiplying bandwidths
of 10MHz.

*US Patent Number 5,689,257
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.

REV. PrB Oct, 2003

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide W eb Site: http://www .analog.com
Fax: [phone] Analog Devices, Inc., 2003

) deter-

REF

) provides temperature tracking and full scale

FB

PRELIMINARY TECHNICAL DA T A

AD5444/AD5446–SPECIFICATIONS

1

(VDD = 2.5 V to 5.5 V, V
AC performance with AD8038 unless otherwise noted.)

Parameter Min Typ Max Units Conditions

STATIC PERFORMANCE
AD5444

Resolution 12 Bits
Relative Accuracy ±
Differential Nonlinearity ±

AD5446

Resolution 14 Bits
Relative Accuracy ±2 LSB

Differential Nonlinearity ±1 LSB Guaranteed Monotonic
Total Unadjusted Error ±2.44 mV
Gain Error ±1.22 mV
Gain Error Temp Coefficient
Output Leakage Current ±10 n A Data = 0000H, TA = 25°C, I

Output Voltage Compliance 1.23 V
REFERENCE INPUT

Reference Input Range ±10 V

V

Input Resistance 8 9.3 12 kΩ Input resistance TC = -50ppm/°C

REF

RFB Resistance 8 9.3 12 kΩ Input resistance TC = -50ppm/°C

Input Capacitance

Zero Code 3 6 pF

Full Scale Code 5 8 pF
DIGITAL INPUTS/OUTPUTS

Input High Voltage, V

Input Low Voltage, V

Output High Voltage, V

Output Low Voltage, V

Input Leakage Current, I

Input Capacitance 10 pF
DYNAMIC PERFORMANCE

Reference Multiplying BW 1 0 MHz V

Output Voltage Settling Time V

AD5440 40 tb d n s Measured to +/-1mV of FS

AD5447 80 tb d n s Measured to +/-1mV of FS

Digital Delay 20 40 ns Interface delay time

10% to 90% Dettling Time 10 30 ns Rise and Fall time, V

Digital to Analog Glitch Impulse

Multiplying Feedthrough Error DAC latch loaded with all 0s.

Output Capacitance

IOUT1 5 p F DAC Latches Loaded with all 0s

IOUT2 1 0 pF DAC Latches Loaded with all 0s

Digital Feedthrough 0. 1 nV -s Feedthrough to DAC output with CS high

= +10 V, I

REF

2

IH

IL

OL

x = O V. All specifications T

OUT

2

2

2.0 V VDD = 3.6 V to 5 V

1.7 V VDD = 2.5 V to 3.6 V

OH

VDD -1 V VDD = 4.5 V to 5 V, I
VDD - 0.5 V VDD = 2.5 V to 3.6 V, I

IL

2

to T

MIN

0.5
½

±5 ppm FSR/

±50 n A Data = 0000H, I

unless otherwise noted. DC performance measured with OP177,

MAX

LSB
LSB Guaranteed Monotonic

°C

OUT1

OUT1

0.8 V VDD = 2.7 V to 5.5 V

0.7 V VDD = 2.5 V to 2.7 V

SOURCE

0.4 V VDD = 4.5 V to 5 V, I

SINK

0.4 V VDD = 2.5 V to 3.6 V, I

= 200uA

SOURCE

= 200uA

= 200uA

SINK

= 200uA

1 µA

= +/-3.5V, DAC loaded all 1s

REF

= 10V, R

REF

LOAD

= 100Ω, C

LOAD

DAC latch alternately loaded with 0s and 1s.

= 10V, R

100Ω, C

LOAD

REF

= 15pF

LOAD

3 nV -s 1 LSB change around Major Carry, V

-75 dB Reference = 1MHz.
Reference = 10MHz.

10 pF DAC Latches Loaded with all 1s
5 pF DAC Latches Loaded with all 1s

and Alternate Loading of all 0s and all 1s.

= 15pF

=

=0V

REF

–2– REV. PrB

PRELIMINARY TECHNICAL DA T A

AD5444/AD5446

(VDD = 2.5 V to 5.5 V, V

= +10 V, I

REF

x = O V. All specifications T

OUT

MIN

to T

unless otherwise noted. DC performance measured with OP177,

MAX

AC performance with AD8038 unless otherwise noted.)

Parameter Min Typ Max Units Conditions

Total Harmonic Distortion -8 0 dB V

= 3.5 V pk-pk, All 1s loaded, f = 1kHz

REF

Digital THD, Clock = 1MHz
50kHz f

OUT

75 dB
Output Noise Spectral Density 25 nV/√Hz @ 1kHz
SFDR performance (Wideband)

Update = 1MHz, V

= 3.5V

REF

Update = 1MHz
50kHz Fout 78 dB
20kHz Fout 78 dB
SFDR performance (NarrowBand) Update = 1MHz, V

= 3.5V

REF

50kHz Fout 87 dB
20kHz Fout 87 dB
Intermodulation Distortion 78 dB f1 = 20kHz, f2 = 25kHz, Update=1MHz,

V

=3.5V

REF

POWER REQUIREMENTS

Power Supply Range 2.5 5.5 V
I

DD

Power Supply Sensitivity

NOTES

1

Temperature range is as follows: Y Version: –40°C to +125°C.

2

Guaranteed by design and characterisation, not subject to production test.

Specifications subject to change without notice.

2

1 µA Logic Inputs = 0 V or V

0.001 %/% ∆VDD = ±5%

DD

TIMING CHARACTERISTICS

Parameter VDD = 4.5 V to 5.5 V VDD = 2.5 V to 5.5 V Units Conditions/Comments

f

SCLK

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

NOTES

1

See Figures 1. Temperature range is as follows: Y Version: –40°C to +125°C. Guaranteed by design and characterisation, not subject to
production test. All input signals are specified with tr =tf = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

Specifications subject to change without notice.

SCLK

SYNC

DIN

tba 50 MHz max Max Clock frequency

20 ns min SCLK Cycle time
8 ns min SCLK High Time
8 ns min SCLK Low Time
8 ns min
5 ns min Data Setup Time

4.5 ns min Data Hold Time
5 ns min SYNC rising edge to SCLK active edge
30 ns min Minimum SYNC high time

t

8

t

4

t

6

t

5

DB15

(V

= +5 V, I

REF

t

1

t

2

2 = O V. All specifications T

OUT

SYNC falling edge to SCLK active edge setup

t

3

DB0

t

7

MIN

to T

unless otherwise noted.)

MAX

time

1

Figure 1. Timing Diagram.

–3–REV. PrB

AD5444/AD5446

PRELIMINARY TECHNICAL DA T A

ABSOLUTE MAXIMUM RATINGS

(TA = +25°C unless otherwise noted)

1, 2

VDD to GND –0.3 V to +7 V
V

REF, RFB

I

OUT

Logic Inputs & Output

to GND –12 V to +12 V

1 to GND –0.3 V to +7 V

3

-0.3V to VDD +0.3 V

Operating Temperature Range

Industrial (Y Version) –40°C to +125°C
Storage Temperature Range –65°C to +150°C
Junction Temperature +150°C
10 lead MSOP θ

Thermal Impedance 206°C/W

JA

Lead Temperature, Soldering (10seconds) 300°C
IR Reflow, Peak Temperature (<20 seconds) +235°C

NOTES

1

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent

damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Only one absolute maximum rating may
be applied at any one time.

2

Transient currents of up to 100mA will not cause SCR latchup.

3

Overvoltages at SCLK, SYNC, DIN, will be clamped by internal diodes.

ORDERING GUIDE

Model Resolution INL Temperature Range Package Description Branding Package Option

AD5444YRM 12
AD5446YRM 14

±0.5
±2

-40 oC to +125 oC MSOP RM-10

-40 oC to +125 oC MSOP RM-10

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD5444/5446 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.

–4– REV. PrB

PRELIMINARY TECHNICAL DA T A

MSOP Mnemonic Function

AD5444/AD5446

PIN FUNCTION DESCRIPTION

1I
2I

1 DAC Current Output.

OUT

2 DAC Analog Ground. This pin should normally be tied to the analog ground of the system.

OUT

3 GND Ground Pin.
4 SCLK Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of

the serial clock input. Alternatively, by means of the serial control bits, the device may be
configured such that data is clocked into the shift register on the rising edge of SCLK.

5 SDIN Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial

clock input. By default, on power up, data is clocked into the shift register on the falling edge of
SCLK. The control bits allow the user to change the active edge to rising edge.

6 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When

SYNC goes low, it powers on the SCLK and DIN buffers and the input shift register is
enabled. Data is loaded to the shift register on the active edge of the following clocks.

7 SDO Serial Data Output. This allows a number of parts to be daisychained. By default, data is clocked

into the shift register on the falling edge and out via SDO on the rising edge of SCLK. Data will
always be clocked out on the alternate edge to loading data to the shift register. Writing the
Readback control word to the shift register makes the DAC register contents available for

readback on the SDO pin, clocked out on the opposite edges to the active clock edge.
8V
9V

10 R

DD

REF
FB

Positive power supply input. These parts can be operated from a supply of +2.5 V to +5.5 V.

DAC reference voltage input pin.

DAC feedback resistor pin. Establish voltage output for the DAC by connecting to external

amplifier output.

PIN CONFIGURATION

MSOP (RM-10)

GND

SDIN

1
2

3
4

5

AD5444/

AD5446

Not to Scale)

(

I

OUT1

I

OUT2

SCLK

16

15
14
13
12

RFB
VREF
VDD
SDO
SYNC

–5–REV. PrB