Analog Devices AD5444 Datasheet

12-Bit, High Bandwidth

FEATURES

±0.5 LSB INL

2.5 V to 5.5 V supply operation
±10 V reference input
Extended temperature range: −40°C to +125°C
10-lead MSOP package
Pin-compatible 12-bit current output DAC
50 MHz serial interface
Guaranteed monotonic
4-quadrant multiplication
Power-on reset with brownout detection
<0.4 µA typical current consumption

APPLICATIONS

Portable battery-powered applications
Waveform generators
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally controlled calibration
Programmable filters and oscillators
Composite video
Ultrasound
Gain, offset, and voltage trimming
Automotive radar

Multiplying DAC with Serial Interface

GENERAL DESCRIPTION

The AD54441 is a CMOS 12-bit, current output digital-to­analog converter. The device operates from a single 2.5 V to

5.5 V power supply, making it suited to battery-powered
applications as well as many other applications.

The DAC uses a double-buffered 3-wire serial interface that is
compat ible with SPI®, QSPI™, MICROWI RE™, and most DSP
interface standards. On power-up, the internal shift register and
latches are filled with 0s, and the DAC output is at zero scale. As
a result of manufacture on a CMOS submicron process, the part
offers excellent 4-quadrant multiplication characteristics.

The applied external reference input voltage (V
the full-scale output current. The part can handle ±10 V inputs
on the reference despite operating from a single-supply power
supply of 2.5 V to 5.5 V. An integrated feedback resistor (R
provides temperature tracking and full-scale voltage output
when combined with an external current-to-voltage precision
amplifier. The AD5444 DAC is available in a small 10-lead
MSOP package that is pin compatible with the AD5425/
AD5426/AD5432/AD5443 family of DACs.

1

US Patent Number 5,689,257.

FUNCTIONAL BLOCK DIAGRAM

V

DD

AD5444

V

REF

R-2R DAC

R

12-BIT

R

I

I

OUT

OUT

AD5444

) determines

REF

)

FB

FB

1

2

POWER-ON

RESET

SYNC
SCLK

SDIN

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

INPUT SHIFT REGISTER

DAC REGISTER

INPUT LATCH

CONTROL LOGIC AND

GND

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

SDO

04588-001

www.analog.com

AD5444

TABLE OF CONTENTS

Specifications..................................................................................... 3

Divider or Programmable Gain Element................................ 16

Timing Characteristics..................................................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Te r m in o l o g y ...................................................................................... 8

Typical Performance Characteristics ............................................. 9

General Description....................................................................... 14

DAC Section................................................................................ 14

Circuit Operation ....................................................................... 14

Single-Supply Applications........................................................ 16

Adding Gain................................................................................ 16

REVISION HISTORY

10/04—Revision 0: Initial Version

Amplifier Selection .................................................................... 17

Reference Selection .................................................................... 17

Serial Interface................................................................................ 19

Microprocessor Interfacing....................................................... 20

PCB Layout and Power Supply Decoupling................................ 22

Evaluation Board for the DAC ................................................. 22

Power Supplies for the Evaluation Board................................ 22

Overview of AD54xx Devices....................................................... 26

Outline Dimensions....................................................................... 27

Ordering Guide .......................................................................... 27

Rev. 0 | Page 2 of 28

AD5444

SPECIFICATIONS

Temperature range for Y Version: −40°C to +125°C.

= 2.5 V to 5.5 V, V

V

DD

The dc performance was measured with OP177; the ac performance was measured with AD8038, unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit Conditions

STATIC PERFORMANCE

Resolution 12 Bits
Relative Accuracy ±0.5 LSB
Differential Nonlinearity ±1 LSB Guaranteed monotonic
Total Unadjusted Error (TUE) ±1 LSB

Gain Error ±0.5 LSB
Gain Error Temp Coefficient1 ±5 ppm FSR/°C
Output Leakage Current ±1 nA Data = 0x0000, TA = 25°C, I

±10 nA Data = 0x0000, TA = −40°C to +125°C, I
REFERENCE INPUT1

Reference Input Range ±10 V
V

Input Resistance 7 9 11 kΩ Input resistance TC = −50 ppm/°C

REF

RFB Feedback Resistance 7 9 11 kΩ Input resistance TC = −50 ppm/°C
Input Capacitance

Zero-Scale Code 18 22 pF

Full-Scale Code 18 22 pF

DIGITAL INPUTS/OUTPUTS1

Input High Voltage, VIH 2.0 V VDD = 3.6 V to 5 V

1.7 V VDD = 2.5 V to 3.6 V
Input Low Voltage, VIL 0.8 V VDD = 2.7 V to 5.5 V

0.7 V VDD = 2.5 V to 2.7 V
Output High Voltage, VOH VDD − 1 V VDD = 4.5 V to 5 V, I
V
Output Low Voltage, VOL 0.4 V VDD = 4.5 V to 5 V, I

0.4 V VDD = 2.5 V to 3.6 V, I
Input Leakage Current, IIL ±1 nA TA = 25°C
±10 nA TA = −40°C to +125°C
Input Capacitance 10 pF

DYNAMIC PERFORMANCE1

Reference Multiplying BW 10 MHz V
Output Voltage Settling Time

Measured to ±1 mV of FS 100 110 ns

Measured to ±4 mV of FS 24 40 ns

Measured to ±16 mV of FS 16 33 ns
Digital Delay 20 40 ns Interface delay time
10% to 90% Settling Time 10 30 ns Rise and fall time, V
Digital-to-Analog Glitch Impulse 2 nV-s 1 LSB change around major carry, V
Output Capacitance

I

1 13 pF DAC latches loaded with all 0s

OUT

28 pF DAC latches loaded with all 1s

I

2 18 pF DAC latches loaded with all 0s

OUT

5 pF DAC latches loaded with all 1s

Digital Feedthrough 0.5 nV-s

= 10 V, I

REF

2 = 0 V. All specifications T

OUT

− 0.5 V VDD = 2.5 V to 3.6 V, I

DD

MIN

to T

, unless otherwise noted.

MAX

= ±3.5 V, DAC loaded all 1s

REF

= 10 V, R

V

REF

loaded with 0s and 1s

Feedthrough to DAC output with
alternate loading of all 0s and all 1s

1

OUT

= 200 µA

SOURCE

= 200 µA

SOURCE

= 200 µA

SINK

= 200 µA

SINK

= 100 Ω, DAC latch alternately

LOAD

= 10 V, R

REF

= 100 Ω,

LOAD

REF

= 0 V

CS high and

OUT

1

Rev. 0 | Page 3 of 28

AD5444

Parameter Min Typ Max Unit Conditions

Analog THD 83 dB V
Digital THD Clock = 1 MHz, V
50 kHz f
20 kHz f

OUT

OUT

71 dB 50 kHz f

77 dB 20 kHz f
Output Noise Spectral Density 25 nV/√Hz @ 1 kHz
SFDR Performance (Wideband) Clock = 10 MHz, V

50 kHz f
20 kHz f

OUT

OUT

78 dB

74 dB
SFDR Performance (Narrow-Band) Clock = 1 MHz, V

50 kHz f
20 kHz f

OUT

OUT

87 dB

85 dB
Intermodulation Distortion 79 dB f1 = 20 kHz, f2 = 25 kHz, Clock = 1 MHz, V

POWER REQUIREMENTS

Power Supply Range 2.5 5.5 V
IDD 0.4 10 µA TA = −40°C to +125°C, logic inputs = 0 V or V

0.6 µA TA = 25°C, logic inputs = 0 V or V
Power Supply Sensitivity1 0.001 %/% ∆VDD = ±5%

1

Guaranteed by design and characterization, not subject to production test.

= 3.5 V p-p, all 1s loaded, f = 1 kHz

REF

= 3.5 V

REF

OUT

OUT

= 3.5 V

REF

= 3.5 V

REF

DD

= 3.5 V

REF

DD

Rev. 0 | Page 4 of 28

AD5444

TIMING CHARACTERISTICS

Temperature range for Y Version: −40°C to +125°C. See Figure 2.
Guaranteed by design and characterization, not subject to production test.
All input signals are specified with tr = tf = 1 ns (10% to 90% of V

= 5 V, I

V

REF

All specifications T

2 = 0 V.

OUT

MIN

to T

, unless other wise noted.

MAX

Table 2.

Parameter VDD = 4.5 V to 5.5 V VDD = 2.5 V to 5.5 V Unit Conditions / Comments

f

50 50 MHz max Maximum Clock Frequency

SCLK

t1 20 20 ns min SCLK Cycle Time
t2 8 8 ns min SCLK High Time
t3 8 8 ns min SCLK Low Time
t4 8 8 ns min

t5 5 5 ns min Data Setup Time
t6 4.5 4.5 ns min Data Hold Time
t7 5 5 ns min

t8 30 30 ns min
t9 23 30 ns min SCLK Active Edge to SDO Valid

SCLK

t

2

Figure 2. Standalone Timing Diagram

SYNC

SDIN

t

4

t

8

DB15 DB0

t

6

t

5

) and timed from a voltage level of (VIL + VIH)/2.

DD

SYNC Falling Edge to SCLK Active Edge Setup Time

SYNC Rising Edge to SCLK Active Edge
Minimum

t

1

t

3

t

7

SYNC High Time

04588-002

t

1

SCLK

t

t

4

SYNC

t

6

t

5

SDIN

SDO

ALTERNATIVELY, DATA CAN BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS
DETERMINED BY CONTROL BITS. IN THIS CASE, DATA WOULD BE CLOCKED OUT OF SDO ON FALLING
EDGE OF SCLK. TIMING AS ABOVE, WITH SCLK INVERTED.

DB15 (N) DB0 (N)

2

t

3

DB15
(N+1)

t

9

DB15 (N)

Figure 3. Daisy-Chain Timing Diagram

Rev. 0 | Page 5 of 28

t

7

t

8



DB0 (N+1)

DB0 (N)

04588-003

AD5444

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.
Transient currents of up to 100 mA do not cause SCR latch-up.

Table 3.

Parameter Rating

VDD to GND
V

, RFB to GND

REF

I

1, I

OUT

Logic Inputs and Output

2 to GND

OUT

1

Input Current to Any Pin except Supplies ±10 mA
Operating Temperature Range

Extended (Y Version) −40°C to +125°C

Storage Temperature Range
Junction Temperature 150°C
10-lead MSOP θJA Thermal Impedance
Lead Temperature, Soldering (10 s) 300°C

−0.3 V to +7 V

−12 V to +12 V

−0.3 V to +7 V

−0.3 V to VDD + 0.3 V

−65°C to +150°C

206°C/W

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability. Only one absolute maximum rating may
be applied at any one time.

IR Reflow, Peak Temperature (<20 s) 235°C

1

Overvoltages at SCLK,

, and DIN are clamped by internal diodes.

SYNC

TO

OUTPUT

PIN

Figure 4. Load Circuit for SDO Timing Specifications

C

L

20pF

200µA

200µA

I

OL

V

+V

OH (MIN)

OL (MAX)

2

I

OH

04588-004

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 6 of 28

AD5444

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

I

OUT

I

OUT

GND

SCLK

SDIN

1

1

2

2

3

(Not to Scale)

4

5

AD5444

TOP VIEW

10

R

FB

V

9

REF

8

V

DD

7

SDO

6

SYNC

04588-005

Figure 5. Pin Configuration MSOP (RM-10)

Table 4. Pin Function Descriptions

Pin No. Mnemonic Function

1 I
2 I

1 DAC Current Output.

OUT

2 DAC Analog Ground. This pin should normally be tied to the analog ground of the system.

OUT

3 GND Ground Pin.
4 SCLK

Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock
input. Alternatively, by means of the serial control bits, the device can be configured such that data is clocked into
the shift register on the rising edge of SCLK.

5 SDIN

Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input. By
default on power-up, data is clocked into the shift register on the falling edge of SCLK. The control bits allow the
user to change the active edge to the rising edge.

6

SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC is taken low, data

is loaded to the shift register on the active edge of the following clocks. The output updates on the rising edge of
SYNC.

7 SDO

Serial Data Output. This pin allows a number of parts to be daisy-chained. By default, data is clocked into the shift
register on the falling edge and out via SDO on the rising edge of SCLK. Data is always clocked out on the

alternate edge to loading data to the shift register.
8 VDD Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V.
9 V

DAC Reference Voltage Input.

REF

10 RFB DAC Feedback Resistor. Establishes voltage output for the DAC by connecting to an external amplifier output.

Rev. 0 | Page 7 of 28

AD5444

TERMINOLOGY

Relative Accuracy

Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero scale and full scale and is normally expressed
in LSBs or as a percentage of full-scale reading.

Digital Feedthrough

When the device is not selected, high frequency logic activity on
the device’s digital inputs can be capacitively coupled through
the device to show up as noise on the I

pins and, subse-

OUT

quently, into the following circuitry. This noise is digital
feedthrough.

Differential Nonlinearity

Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of −1 LSB maximum
over the operating temperature range ensures monotonicity.

Gain Error

Gain error or full-scale error is a measure of the output error
between an ideal DAC and the actual device output. For this
DAC, ideal maximum output is V

− 1 LSB. Gain error of the

REF

DAC is adjustable to zero with external resistance.

Output Leakage Current

Output leakage current is current that flows in the DAC ladder
switches when these are turned off. For the I

1 terminal, it can

OUT

be measured by loading all 0s to the DAC and measuring the

1 current. Minimum current flows in the I

I

OUT

2 line when

OUT

the DAC is loaded with all 1s.

Output Capacitance

Capacitance from I

OUT

1 or I

2 to AGND.

OUT

Output Current Settling Time

The amount of time it takes for the output to settle to a
specified level for a full-scale input change. For this device, it is
specified with a 100 Ω resistor to ground. The settling time

SYNC

specification includes the digital delay from the

rising

edge to the full-scale output change.

Digital-to-Analog Glitch Impulse

The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-s or nV-s,
depending upon whether the glitch is measured as a current or
voltage signal.

Multiplying Feedthrough Error

The error due to capacitive feedthrough from the DAC
reference input to the DAC I

1 terminal, when all 0s are

OUT

loaded to the DAC.

Total Harmonic Distortion (THD)

The DAC is driven by an ac reference. The ratio of the rms sum
of the harmonics of the DAC output to the fundamental value is
the THD. Usually only the lower-order harmonics such as
second to fifth are included.

2

2

2

THD

2

3

2

log20

=

+++

VVVV

5

4

V

1

Digital Intermodulation Distortion

Second-order intermodulation (IMD) measurements are the
relative magnitudes of the fa and fb tones generated digitally by
the DAC and the second-order products at 2fa − fb and 2fb − fa.

Compliance Voltage Range

The maximum range of (output) terminal voltage for which the
device provides the specified characteristics.

Spurious-Free Dynamic Range (SFDR)

The usable dynamic range of a DAC before spurious noise
interferes or distorts the fundamental signal. SFDR is the
measure of difference in amplitude between the fundamental
and the largest harmonically or nonharmonically related spur
from dc to full Nyquist bandwidth (half the DAC sampling rate
or fs/2). Narrow-band SFDR is a measure of SFDR over an
arbitrary window size, in this case 50% of the fundamental.
Digital SFDR is a measure of the usable dynamic range of the
DAC when the signal is a digitally generated sine wave.

Rev. 0 | Page 8 of 28

AD5444

TYPICAL PERFORMANCE CHARACTERISTICS

0.5
TA = 25°C

INL (LSB)

0.4

0.3

0.2

0.1

–0.1
–0.2

–0.3

–0.4

–0.5

= 10V

V

REF

= 5V

V

DD

0

0 512 1024 1536 2048 2560 3072 3584 4096

CODE

Figure 6. INL vs. Code

1.0
TA = 25°C

0.8
V

= 10V

REF

V

= 5V

DD

0.6

0.4

0.2

0.0

DNL (LSB)

–0.2
–0.4

–0.6

–0.8

–1.0

0 512 1024 1536 2048 2560 3072 3584 4096

CODE

Figure 7.DNL vs. Code

1.00

TA = 25°C
V

0.75

0.50

0.25

INL (LSB)

–0.25

–0.50

–0.75

–1.00

= 5V

DD

AD5444

MAX INL

0

MIN INL

2345678910

REFERENCE VOLTAGE (V)

Figure 8.INL vs. Reference Voltage

04588-006

04588-008

04588-047

2.0
TA = 25°C

V

1.5

1.0

0.5

DNL (LSB)

–05

–1.0

–1.5

–2.0

= 5V

DD

AD5444

MAX DNL

0

2345678910

MIN DNL

REFERENCE VOLTAGE (V)

Figure 9.DNL vs. Reference Voltage

1.0
TA = 25°C

0.8
V

= 10V

REF

V

= 5V

DD

0.6

0.4

0.2

0.0

TUE (LSB)

–0.2
–0.4

–0.6

–0.8

–1.0

0 512 1024 1536 2048 2560 3072 3584 4096

CODE

Figure 10.TUE vs. Code

2.0

TA = 25°C
V

= 5V

DD

1.5

AD5444

1.0

0.5

0

TUE (LSB)

–0.5

–1.0

–1.5

–2.0

2345 8910

MAX TUE

MIN TUE

76

REFERENCE VOLTAGE (V)

Figure 11.TUE vs. Reference Voltage

04588-048

04588-0-013

04588-052

Rev. 0 | Page 9 of 28