ANALOG DEVICES AD5253, AD5254 Service Manual

Quad 64-/256-Position I2C Nonvolatile

www.BDTIC.com/ADI

FEATURES

AD5253: quad 64-position resolution
AD5254: quad 256-position resolution
1 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Nonvolatile memory
Power-on refreshed to EEMEM settings in 300 μs typ
EEMEM rewrite time = 540 μs typ
Resistance tolerance stored in nonvolatile memory
12 extra bytes in EEMEM for user-defined information

2

C-compatible serial interface

I
Direct read/write access of RDAC
Predefined linear increment/decrement commands
Predefined ±6 dB step change commands
Synchronous or asynchronous quad-channel update
Wiper setting readback
4 MHz bandwidth—1 kΩ version
Single supply 2.7 V to 5.5 V
Dual supply ±2.25 V to ±2.75 V
2 slave address-decoding bits allow operation of 4 devices
100-year typical data retention, T
Operating temperature: –40°C to +85°C

APPLICATIONS

Mechanical potentiometer replacement
Low resolution DAC replacement
RGB LED backlight control
White LED brightness adjustment
RF base station power amp bias control
Programmable gain and offset control
Programmable attenuators
Programmable voltage-to-current conversion
Programmable power supply
Programmable filters
Sensor calibrations

GENERAL DESCRIPTION

The AD5253/AD5254 are quad-channel, I2C®, nonvolatile
mem-ory, digitally controlled potentiometers with 64/256
positions, respectively. These devices perform the same
electronic adjust-ment functions as mechanical potentiometers,
trimmers, and variable resistors.

The parts’ versatile programmability allows multiple modes of
operation, including read/write access in the RDAC and EEMEM
registers, increment/decrement of resistance, resistance changes
in ±6 dB scales, wiper setting readback, and extra EEMEM for
storing user-defined information, such as memory data for other
components, look-up table, or system identification information.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

1

stores wiper settings w/write protection

2

and EEMEM registers

= 55°C

A

Memory Digital Potentiometers

AD5253/AD5254

FUNCTIONAL BLOCK DIAGRAM

V

DD

V

SS

DGND

WP

SCL
SDA

AD0
AD1

SERIAL

INTERFACE

The AD5253/AD5254 allow the host I2C controllers to write
any of the 64-/256-step wiper settings in the RDAC registers
and store them in the EEMEM. Once the settings are stored,
they are restored automatically to the RDAC registers at system
power-on; the settings can also be restored dynamically.

The AD5253/AD5254 provide additional increment,
decrement, +6 dB step change, and –6 dB step change in
synchronous or asynchronous channel update mode. The
increment and decrement functions allow stepwise linear
adjustments, with a ± 6 dB step change equivalent to doubling
or halving the RDAC wiper setting. These functions are useful
for steep-slope, nonlinear adjustments, such as white LED
brightness and audio volume control.

The AD5253/AD5254 have a patented resistance-tolerance
storing function that allows the user to access the EEMEM and
obtain the absolute end-to-end resistance values of the RDACs
for precision applications.

The AD5253/AD5254 are available in TSSOP-20 packages in
1 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ options. All parts are
guaranteed to operate over the –40°C to +85°C extended
industrial temperature range.

1

The terms nonvolatile memory and EEMEM are used interchangeably.

2

The terms digital potentiometer and RDAC are used interchangeably.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003–2009 Analog Devices, Inc. All rights reserved.

RDAC EEMEM

EEMEM

POWER-ON

REFRESH

DATA

I2C

CONTROL

COMMAND

DECODE LOGIC

ADDRESS

DECODE LOGIC

CONTROL LOGIC

AD5253/AD5254

RAB TOL

Figure 1.

RDAC0
REGIS-

TER

RDAC1
REGIS-

TER

RDAC2
REGIS-

TER

RDAC3
REGIS-

TER

RDAC0

RDAC1

RDAC2

RDAC3

A0
W0
B0

A1
W1
B1

A2
W2
B2

A3
W3
B3

03824-0-001

AD5253/AD5254

www.BDTIC.com/ADI

TABLE OF CONTENTS

Features .............................................................................................. 1

I2C-Compatible 2-Wire Serial Bus ........................................... 20

Applications ....................................................................................... 1 

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Electrical Characteristics ................................................................. 3

1 kΩ Version .................................................................................. 3

10 kΩ, 50 kΩ, 100 kΩ Versions .................................................. 5

Interface Timing Characteristics ................................................ 7

Absolute Maximum Ratings ............................................................ 8

ESD Caution .................................................................................. 8

Pin Configuration and Function Descriptions ............................. 9

Typical Performance Characteristics ........................................... 10

I2C Interface ..................................................................................... 14

I2C Interface General Description ............................................ 14

I2C Interface Detail Description ............................................... 15

Theory of Operation ...................................................................... 21

Linear Increment/Decrement Commands ............................. 21

±6 dB Adjustments (Doubling/Halving Wiper Setting) ....... 21

Digital Input/Output Configuration........................................ 22

Multiple Devices on One Bus ................................................... 22

Terminal Voltage Operation Range ......................................... 23

Power-Up and Power-Down Sequences .................................. 23

Layout and Power Supply Biasing ............................................ 23

Digital Potentiometer Operation ............................................. 24

Programmable Rheostat Operation ......................................... 24

Programmable Potentiometer Operation ............................... 25

Applications Information .............................................................. 26

RGB LED Backlight Controller for LCD Panels .................... 26

Outline Dimensions ....................................................................... 28

Ordering Guide .......................................................................... 29

REVISION HISTORY

10/09—Rev. A to Rev. B

Change to Figure 27 ....................................................................... 15

9/05—Rev. 0 to Rev. A

Change to Figure 6 ......................................................................... 10

Change to EEMEM Write Protection Section ............................ 18

Changes to Figure 37 ...................................................................... 22

Deleted Table 13 and Table 14 ...................................................... 24

Change to Figure 43 ....................................................................... 25

Changes to Ordering Guide .......................................................... 29

5/03—Revision 0: Initial Version

Rev. B | Page 2 of 32

AD5253/AD5254

www.BDTIC.com/ADI

ELECTRICAL CHARACTERISTICS

1 kΩ VERSION

VDD = +3 V ± 10% or +5 V ± 10%, VSS = 0 V or VDD/VSS = ±2.5 V ± 10%, VA = VDD, VB = 0 V, –40°C < TA < +85°C, unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ1 Max Unit

DC CHARACTERISTICS—

RHEOSTAT MODE
Resolution N AD5253 6 Bits
AD5254 8 Bits
Resistor Differential Nonlinearity2
R
R
R
Resistor Nonlinearity2 R-INL RWB, RWA = NC, VDD = 5.5 V, AD5253 –0.5 ±0.2 +0.5 LSB
R
R
R
Nominal Resistor Tolerance ΔRAB/RAB T
Resistance Temperature Coefficient (ΔRAB/RAB) × 106/ΔT 650 ppm/°C
Wiper Resistance RW I
I
Channel-Resistance Matching ΔR

DC CHARACTERISTICS—

POTENTIOMETER DIVIDER MODE
Differential Nonlinearity3 DNL AD5253 –0.5 ±0.1 +0.5 LSB
AD5254 –1.00 ±0.25 +1.00 LSB
Integral Nonlinearity3 INL AD5253 –0.5 ±0.2 +0.5 LSB
AD5254 –2.0 ±0.5 +2.0 LSB
Voltage Divider Tempco (ΔVW/VW) × 106/ΔT Code = half scale 25 ppm/°C
Full-Scale Error V
Code = full scale, VDD = 5.5 V, AD5254 –16 –11 0 LSB
Code = full scale, VDD = 2.7 V, AD5253 –6 –4 0 LSB
Code = full scale, VDD = 2.7 V, AD5254 –23 –16 0 LSB
Zero-Scale Error V
Code = zero scale, VDD = 5.5 V, AD5254 0 11 16 LSB
Code = zero scale, VDD = 2.7 V, AD5253 0 4 6 LSB
Code = zero scale, VDD = 2.7 V, AD5254 0 15 20 LSB

RESISTOR TERMINALS

Voltage Range4 V
Capacitance5 A, B CA, CB

Capacitance5 W CW

Common-Mode Leakage Current ICM V

R-DNL RWB, RWA = NC, VDD = 5.5 V, AD5253 –0.5 ±0.2 +0.5 LSB

, RWA = NC, VDD = 5.5 V, AD5254 –1.00 ±0.25 +1.00 LSB

WB

, RWA = NC, VDD = 2.7 V, AD5253 –0.75 ±0.30 +0.75 LSB

WB

, RWA = NC, VDD = 2.7 V, AD5254 –1.5 ±0.3 +1.5 LSB

WB

, RWA = NC, VDD = 5.5 V, AD5254 –2.0 ±0.5 +2.0 LSB

WB

, RWA = NC, VDD = 2.7 V, AD5253 –1.0 +2.5 +4.0 LSB

WB

, RWA = NC, VDD = 2.7 V, AD5254 –2 +9 +14 LSB

WB

= 25°C –30 +30 %

A

= 1 V/R, VDD = 5 V 75 130 Ω

W

= 1 V/R, VDD = 3 V 200 300 Ω

W

/ΔR

AB1

0.15 %

AB2

Code = full scale, VDD = 5.5 V, AD5253 –5 –3 0 LSB

WFSE

Code = zero scale, VDD = 5.5 V, AD5253 0 3 5 LSB

WZSE

, VB, VW V

A

f = 1 kHz, measured to GND,

VDD V

SS

85 pF

code = half scale
f = 1 kHz, measured to GND,

95 pF

code = half scale

= VB = VDD/2 0.01 1.00 μA

A

Rev. B | Page 3 of 32

AD5253/AD5254

www.BDTIC.com/ADI

Parameter Symbol Conditions Min Typ1 Max Unit

DIGITAL INPUTS AND OUTPUTS

Input Logic High VIH V
V
Input Logic Low VIL V
V
Output Logic High (SDA) VOH R
Output Logic Low (SDA) VOL R

I

WP Leakage Current

WP

A0 Leakage Current IA0 A0 = GND 3 μA

I

Input Leakage Current

(Other than WP

and A0)

Input Capacitance5 C

V

I

5 pF

I

POWER SUPPLIES

Single-Supply Power Range VDD V
Dual-Supply Power Range VDD/VSS ±2.25 ±2.75 V
Positive Supply Current IDD V
Negative Supply Current ISS

EEMEM Data Storing Mode Current I
EEMEM Data Restoring Mode

Current

6

Power Dissipation7 P

V

DD_STORE

I

DD_RESTORE

V

V

DISS

Power Supply Sensitivity PSS ΔVDD = 5 V ± 10% −0.025 +0.010 +0.025 %/%
ΔVDD = 3 V ± 10% –0.04 +0.02 +0.04 %/%

DYNAMIC CHARACTERISTICS

5, 8

Bandwidth –3 dB BW RAB = 1 kΩ 4 MHz
Total Harmonic Distortion THD VA =1 V rms, VB = 0 V, f = 1 kHz 0.05 %
VW Settling Time tS V
Resistor Noise Voltage e

N_WB

Digital Crosstalk CT

Analog Coupling CAT

1

Typical values represent average readings at 25°C and VDD = 5 V.

2

Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum and minimum resistance wiper positions. R-DNL is the

relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5254 1 kΩ version at V

= VDD/R for both VDD = 3 V and VDD = 5 V.

I

W

3

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output digital-to-analog converter. VA = VDD and VB = 0 V.

DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.

4

Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other.

5

Guaranteed by design and not subject to production test.

6

Command 0 NOP should be activated after Command 1 to minimize I

7

P

is calculated from IDD × VDD = 5 V.

DISS

8

All dynamic characteristics use VDD = 5 V.

= 5 V, VSS = 0 V 2.4 V

DD

= +2.7 V/0 V or VDD/VSS = ±2.5 V 2.1 V

DD/VSS

= 5 V, VSS = 0 V 0.8 V

DD

= +2.7 V/0 V or VDD/VSS = ±2.5 V 0.6 V

DD/VSS

= 2.2 kΩ to VDD = 5 V, VSS = 0 V 4.9 V

PULL-UP

= 2.2 kΩ to VDD = 5 V, VSS = 0 V 0.4 V

PULL-UP

= VDD

WP

= 0 V or VDD ±1 μA

IN

= 0 V 2.7 5.5 V

SS

= VDD or VIL = GND 5 15 μA

IH

= VDD or VIL = GND, VDD = 2.5 V,

V

IH

= –2.5 V

V

SS

= VDD or VIL = GND 35 mA

IH

= VDD or VIL = GND 2.5 mA

IH

= VDD = 5 V or VIL = GND 0.075 mW

IH

= VDD, VB = 0 V 0.2 μs

A

= 500 Ω, f = 1 kHz

R

WB

5 μA

–5 –15 μA

3 nV/√Hz

(thermal noise only)

= VDD, VB = 0 V, measure VW with

V

A

–80 dB
adjacent RDAC making full-scale
change

Signal input at A0 and measure the

–72 dB
output at W1, f = 1 kHz

DD

current consumption.

DD_RESTORE

= 2.7 V,

Rev. B | Page 4 of 32

AD5253/AD5254

www.BDTIC.com/ADI

10 kΩ, 50 kΩ, 100 kΩ VERSIONS

VDD = +3 V ± 10% or +5 V ± 10%, VSS = 0 V or VDD/VSS = ±2.5 V ± 10%, VA = VDD, VB = 0 V, –40°C < TA < +85°C, unless otherwise noted.

Table 2.

Parameter Symbol Conditions Min Typ1 Max Unit

DC CHARACTERISTICS—

RHEOSTAT MODE
Resolution N AD5253/AD5254 6/8 Bits
Resistor Differential Nonlinearity2 R-DNL RWB, RWA = NC, AD5253 −0.75 ±0.10 +0.75 LSB
R
Resistor Nonlinearity2 R-INL RWB, RWA = NC, AD5253 −0.75 ±0.25 +0.75 LSB
R
Nominal Resistor Tolerance ΔRAB/RAB T
Resistance Temperature

Coefficient
Wiper Resistance RW I
I
Channel-Resistance Matching ΔR
R

DC CHARACTERISTICS—

POTENTIOMETER DIVIDER MODE
Differential Nonlinearity3 DNL AD5253 −0.5 ±0.1 +0.5 LSB
AD5254 −1.0 ±0.3 +1.0 LSB
Integral Nonlinearity3 INL AD5253 −0.50 ±0.15 +0.50 LSB
AD5254 −1.5 ±0.5 +1.5 LSB
Voltage Divider

Temperature Coefficient
Full-Scale Error V
Code = full scale, AD5254 −3 −1 0 LSB
Zero-Scale Error V
Code = zero scale, AD5254 0 1.2 3.0 LSB

RESISTOR TERMINALS

Voltage Range4 V
Capacitance5 A, B CA, CB

Capacitance5 W CW

Common-Mode Leakage Current ICM V

DIGITAL INPUTS AND OUTPUTS

Input Logic High VIH V
V
Input Logic Low VIL V
V
Output Logic High (SDA) VOH R
Output Logic Low (SDA) VOL R
WP Leakage Current
A0 Leakage Current IA0 A0 = GND 3 μA
Input Leakage Current

(Other than WP

and A0)

Input Capacitance5 C

, RWA = NC, AD5254 −1.00 ±0.25 +1.00 LSB

WB

, RWA = NC, AD5254 −2.5 ±1.0 +2.5 LSB

WB

= 25°C −20 +20 %

A

(ΔR

) × 106/ΔT 650 ppm/°C

AB/RAB

= 1 V/R, VDD = 5 V 75 130 Ω

W

= 1 V/R, VDD = 3 V 200 300 Ω

W

/ΔR

AB1

R

AB2

= 10 kΩ, 50 kΩ 0.15 %

AB

= 100 kΩ 0.05 %

AB

(ΔV

) × 106/ΔT Code = half scale 15 ppm/°C

W/VW

Code = full scale, AD5253 −1.0 −0.3 0 LSB

WFSE

Code = zero scale, AD5253 0 0.3 1.0 LSB

WZSE

, VB, VW V

A

f = 1 kHz, measured to GND,

VDD V

SS

85 pF

code = half scale
f = 1 kHz, measured to GND,

95 pF

code = half scale

= VB = VDD/2 0.01 1 μA

A

= 5 V, VSS = 0 V 2.4 V

DD

= +2.7 V/0 V or VDD/VSS = ±2.5 V 2.1 V

DD/VSS

= 5 V, VSS = 0 V 0.8 V

DD

= +2.7 V/0 V or VDD/VSS = ±2.5 V 0.6 V

DD/VSS

= 2.2 kΩ to VDD = 5 V, VSS = 0 V 4.9 V

PULL-UP

= 2.2 kΩ to VDD = 5 V, VSS = 0 V 0.4 V

PULL-UP

I

WP

V

I

I

5 pF

I

= VDD

WP

= 0 V or VDD ±1 μA

IN

5 μA

Rev. B | Page 5 of 32

AD5253/AD5254

www.BDTIC.com/ADI

Parameter Symbol Conditions Min Typ1 Max Unit

POWER SUPPLIES

Single-Supply Power Range VDD V
Dual-Supply Power Range VDD/VSS ±2.25 ±2.75 V
Positive Supply Current IDD V
Negative Supply Current ISS

I

EEMEM Data Storing Mode

V

DD_STORE

Current

EEMEM Data Restoring Mode

Current

6

I

DD_RESTORE

Power Dissipation7 P

V

V

DISS

Power Supply Sensitivity PSS ΔVDD = 5 V ± 10% −0.005 +0.002 +0.005 %/%
ΔVDD = 3 V ± 10% −0.010 +0.002 +0.010 %/%

DYNAMIC CHARACTERISTICS

5, 8

–3 dB Bandwidth BW RAB = 10 kΩ/50 kΩ/100 kΩ 400/80/40 kHz
Total Harmonic Distortion THDW V
VW Settling Time tS

Resistor Noise Voltage e

N_WB

Digital Crosstalk CT

Analog Coupling CAT

1

Typical values represent average readings at 25°C and VDD = 5 V.

2

Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum and minimum resistance wiper positions. R-DNL is the

relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5254 1 kΩ version at VDD = 2.7 V,
IW = VDD/R for both VDD = 3 V and VDD = 5 V.

3

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider, similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits

of ±1 LSB maximum are guaranteed monotonic operating conditions.

4

Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other.

5

Guaranteed by design and not subject to production test.

6

Command 0 NOP should be activated after Command 1 to minimize I

7

P

is calculated from IDD × VDD = 5 V.

DISS

8

All dynamic characteristics use VDD = 5 V.

= 0 V 2.7 5.5 V

SS

= VDD or VIL = GND 5 15 μA

IH

= VDD or VIL = GND, VDD = 2.5 V,

V

IH

= −2.5 V

V

SS

= VDD or VIL = GND, TA = 0°C to 85°C 35 mA

IH

= VDD or VIL = GND, TA = 0°C to 85°C 2.5 mA

IH

= VDD = 5 V or VIL = GND 0.075 mW

IH

= 1 V rms, VB = 0 V, f = 1 kHz 0.05 %

A

= VDD, VB = 0 V,

V

A

= 10 kΩ/50 kΩ/100 kΩ

R

AB

= 10 kΩ/50 kΩ/100 kΩ, code =

R

AB

−5 −15 μA

1.5/7/14 μs

9/20/29 nV/√Hz

midscale, f = 1 kHz (thermal noise only)

= VDD, VB = 0 V, measure VW with

V

A

−80 dB

adjacent RDAC making full-scale change
Signal input at A0 and measure output

−72 dB

at W1, f = 1 kHz

current consumption.

DD_RESTORE

Rev. B | Page 6 of 32

AD5253/AD5254

www.BDTIC.com/ADI

INTERFACE TIMING CHARACTERISTICS

All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching
characteristics are measured using both V

Table 3.

Parameter1 Symbol Conditions Min Typ2 Max Unit

INTERFACE TIMING

SCL Clock Frequency f
t

Bus-Free Time Between Stop and Start t1 1.3 μs

BUF

t

Hold Time (Repeated Start) t2

HD;STA

t

Low Period of SCL Clock t3 1.3 μs

LOW

t

High Period of SCL Clock t4 0.6 μs

HIGH

t

Set-up Time for Start Condition t5 0.6 μs

SU;STA

t

Data Hold Time t6 0 0.9 μs

HD;DAT

t

Data Set-up Time t7 100 ns

SU;DAT

tF Fall Time of Both SDA and SCL Signals t8 300 ns
tR Rise Time of Both SDA and SCL Signals t9 300 ns
t

Set-up Time for Stop Condition t10 0.6 μs

SU;STO

EEMEM Data Storing Time t
EEMEM Data Restoring Time at Power-On3 t

EEMEM Data Restoring Time upon Restore

Command or Reset Operation

3

EEMEM Data Rewritable Time4 t

FLASH/EE MEMORY RELIABILITY

Endurance5 100 K cycles
Data Retention

1

See Figure 23 for location of measured values.

2

Typical values represent average readings at 25°C and VDD = 5 V.

3

During power-up, all outputs are preset to midscale before restoring the EEMEM contents. RDAC0 has the shortest EEMEM restore time, whereas RDAC3 has the longest.

4

Delay time after power-on or reset before new EEMEM data to be written.

5

Endurance is qualified to 100,000 cycles per JEDEC Std. 22 Method A117 and measured at –40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles.

6

Retention lifetime equivalent at junction temperature TJ = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates

with junction temperature.

7

When the part is not in operation, the SDA and SCL pins should be pulled high. When these pins are pulled low, the I2C interface at these pins conducts a current of

about 0.8 mA at V

6, 7

100 Years

= 5.5 V and 0.2 mA at VDD = 2.7 V.

DD

= 3 V and 5 V.

DD

400 kHz

SCL

EEMEM_STORE

EEMEM_RESTORE1

t

EEMEM_RESTORE2

EEMEM_REWRITE

After this period, the first clock pulse is

0.6 μs

generated.

26 ms

rise time dependent. Measure without

V

DD

decoupling capacitors at V

DD

and VSS.

300 μs

VDD = 5 V. 300 μs

540 μs

Rev. B | Page 7 of 32

AD5253/AD5254

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted

Table 4.

Parameter Rating

VDD to GND −0.3 V, +7 V
VSS to GND +0.3 V, −7 V
VDD to VSS 7 V
VA, VB, VW to GND VSS, VDD
Maximum Current

IWB, IWA Pulsed ±20 mA
IWB Continuous (RWB ≤ 1 kΩ, A Open)1 ±5 mA
IWA Continuous (RWA ≤ 1 kΩ, B Open)1 ±5 mA
IAB Continuous

(R

= 1 kΩ/10 kΩ/50 kΩ/100 kΩ)1

AB

Digital Inputs and Output Voltage to GND 0 V, 7 V
Operating Temperature Range −40°C to +85°C
Maximum Junction Temperature (T
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
TSSOP-20 Thermal Resistance2 θJA 143°C/W

1

Maximum terminal current is bound by the maximum applied voltage across

any two of the A, B, and W terminals at a given resistance, the maximum
current handling of the switches, and the maximum power dissipation of the
package. VDD = 5 V.

2

Package power dissipation = (T

JMAX

JMAX

− TA)/θJA.

±5 mA/±500 μA/
±100 μA/±50 μA

) 150°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. B | Page 8 of 32

AD5253/AD5254

A

www.BDTIC.com/ADI

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

W0

B0
A0

AD0

WP
W1

B1
A1

SD

V

SS

1
2

AD5253/

3

AD5254

4

TOP VIEW

(Not to Scale)

5
6
7
8
9

10

20
19
18
17
16
15
14
13
12
11

V

DD

W3
B3
A3
AD1
DGND
SCL
W2
B2
A2

03824-0-002

Figure 2. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 W0 Wiper Terminal of RDAC0. VSS ≤ VW0 ≤ VDD.
2 B0 B Terminal of RDAC0. VSS ≤ VB0 ≤ VDD.
3 A0 A Terminal of RDAC0. VSS ≤ VA0 ≤ VDD.
4 AD0 I2C Device Address 0. AD0 and AD1 allow four AD5253/AD5254 devices to be addressed.
5

WP

Write Protect, Active Low. V

≤ VDD + 0.3 V.

WP

6 W1 Wiper Terminal of RDAC1. VSS ≤ VW1 ≤ VDD.
7 B1 B Terminal of RDAC1. VSS ≤ VB1 ≤ VDD.
8 A1 A Terminal of RDAC1. VSS ≤ VA1 ≤ VDD.
9 SDA

Serial Data Input/Output Pin. Shifts in one bit at a time upon positive clock edges. MSB loaded first. Open-drain
MOSFET requires pull-up resistor.

10 VSS

Negative Supply. Connect to 0 V for single supply or –2.7 V for dual supply, where V
rather than grounded in dual supply, V

must be able to sink 35 mA for 26 ms when storing data to EEMEM.

SS

– VSS ≤ +5.5 V. If VSS is used

DD

11 A2 A Terminal of RDAC2. VSS ≤ VA2 ≤ VDD.
12 B2 B Terminal of RDAC2. VSS ≤ VB2 ≤ VDD.
13 W2 Wiper Terminal of RDAC2. VSS ≤ VW2 ≤ VDD.
14 SCL

Serial Input Register Clock Pin. Shifts in one bit at a time upon positive clock edges. V

SCL

resistor is recommended for SCL to ensure minimum power.
15 DGND Digital Ground. Connect to system analog ground at a single point.
16 AD1 I2C Device Address 1. AD0 and AD1 allow four AD5253/AD5254 devices to be addressed.
17 A3 A Terminal of RDAC3. VSS ≤ VA3 ≤ VDD.
18 B3 B Terminal of RDAC3. VSS ≤ VB3 ≤ VDD.
19 W3 Wiper Terminal of RDAC3. VSS ≤ VW3 ≤ VDD.
20 VDD

Positive Power Supply Pin. Connect +2.7 V to +5 V for single supply or ±2.7 V for dual supply, where V

must be able to source 35 mA for 26 ms when storing data to EEMEM.

V

DD

≤ (VDD + 0.3 V). Pull-up

– VSS ≤ +5.5 V.

DD

Rev. B | Page 9 of 32

AD5253/AD5254

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

1.0

0.8

0.6

0.4

0.2

0

–0.2

R-INL (LSB)

–0.4

–0.6

–0.8

–1.0

0 32 64 96 128 160 192 224 256

TA= –40°C, +25°C, +85°C, +125°C

CODE (Decimal)

Figure 3. R-INL vs. Code Figure 6. DNL vs. Code

03824-0-015

1.0

0.8

0.6

0.4

0.2

0

–0.2

DNL (LSB)

–0.4

–0.6

–0.8

–1.0

0 32 64 96 128 160 192 224 256

T

= –40°C, +25°C, +85°C, +125°C

A

CODE (Decimal)

03824-0-018

1.0

0.8

0.6

0.4

0.2

0

–0.2

R-DNL (LSB)

–0.4

–0.6

–0.8

–1.0

0 32 64 96 128 160 192 224 256

TA = –40°C, +25°C, +85°C, +125°C

CODE (Decimal)

Figure 4. R-DNL vs. Code Figure 7. Supply Current vs. Temperature

1.0

0.8

0.6

0.4

0.2

0

–0.2

INL (LSB)

–0.4

–0.6

–0.8

–1.0

0 32 64 96 128 160 192 224 256

T

= –40°C, +25°C, +85°C, +125°C

A

CODE (Decimal)

Figure 5. INL vs. Code Figure 8. Supply Current vs. Digital Input Voltage, TA = 25°C

03824-0-016

03824-0-017

10

8

6

4

2

0

(μA)

DD

I

–2

–4

–6

–8

–10

–40 –20 0 20 40 60 80 100 120

10

1

0.1

(mA)

DD

I

0.01

0.001

0.0001
0123456

IDD @ VDD= +5.5V

IDD @ VDD= +2.7V

ISS @ VDD= +2.7V, VSS= –2.7V

TEMPERATURE (°C)

VDD= 5.5V

VDD= 2.7V

DIGITAL INPUT VOLTAGE (V)

03824-0-019

03824-0-020

Rev. B | Page 10 of 32

AD5253/AD5254

www.BDTIC.com/ADI

240
220
200
180
160
140

(Ω)

120

WB

R

100

80
60
40
20

0

10 23456

VDD= 2.7V

T

= 25°C

A

V

BIAS

(V)

Figure 9. Wiper Resistance vs. V

VDD= 5.5V

T

= 25°C

A

DATA = 0x00

03824-0-021

BIAS

30

VDD= 5V
T

= –40°C/+85°C

25

20

15

10

5

POTENTIOMETER MODE TEMPCO (ppm/°C)

0

0 32 64 96 128 160 192 224 256

CODE (Decimal)

A

V

= V

A

VB= 0V

DD

Figure 12. Potentiometer Mode Tempco (∆VWB/VWB)/∆T × 106 vs. Code

03824-0-024

6

4

2

(%)

WB

0

ΔR

–2

–4

–6

–40 –20 0 20 40 60 80 100 120

TEMPERATURE (°C)

Figure 10. Change of RWB vs. Temperature

90

80

70

60

50

40

30

20

RHEOSTAT MODE TEMPCO (ppm/°C)

10

0

0 32 64 96 128 160 192 224 256

CODE (Decimal)

VDD= 5V
T

= –40°C/+85°C

A

V

= V

A

DD

VB= 0V

Figure 11. Rheostat Mode Tempco (∆RWB/RWB)/∆T × 106 vs. Code

03824-0-022

03824-0-023

0

–6

–12

–18

–24

–30

0x08

GAIN (dB)

–36

–42

–48

–54

–60

0x04

0x02

1k 10k10 100 100k 1M 10M

FREQUENCY (Hz)

0x01

0x40
0x20

0x10

0x00

Figure 13. Gain vs. Frequency vs. Code, RAB = 1 kΩ, TA = 25°C

0

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

0xFF
0x80

0x40
0x20
0x10

0x08
0x04

0x01
0x00

0x02

1k 10k10 100 100k 1M 10M

FREQUENCY (Hz)

Figure 14. Gain vs. Frequency vs. Code, RAB = 10 kΩ, TA = 25°C

0xFF

0x80

03824-0-025

03824-0-026

Rev. B | Page 11 of 32

AD5253/AD5254

www.BDTIC.com/ADI

0

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

0x80

0x40
0x20
0x10

0x08

0x04
0x02
0x01

1k 10k10 100 100k 1M 10M

FREQUENCY (Hz)

0xFF

Figure 15. Gain vs. Frequency vs. Code, RAB = 50 kΩ, TA = 25°C

0x00

03824-0-027

1.2

1.0

0.8

0.6

(mA)

DD

I

0.4

0.2

0

1 10010 1k 10k 100k 1M 10M

CLOCK FREQUENCY (Hz)

TA= 25°C

VDD= 5.5V

VDD= 2.7V

Figure 18. Supply Current vs. Digital Input Clock Frequency

03824-0-030

0

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

0x80

0x40

0x20

0x10

0x08

0x04
0x02
0x01

1k 10k10 100 100k 1M 10M

FREQUENCY (Hz)

0xFF

Figure 16. Gain vs. Frequency vs. Code, RAB = 100 kΩ, TA = 25°C

100

80

60

40

20

)

Ω

(

0

AB

R

–20

Δ

–40

–60

–80

–100

0 32 64 96 128 160 192 224 256

100k

Ω

1k

Ω

CODE (Decimal)

10k

Ω

50k

VDD = 5.5V

Ω

Figure 17. ΔRAB vs. Code, TA = 25°C

0x00

03824-0-028

03824-0-029

CLK

V

DD

V

W

DIGITAL FEEDTHROUGH

MIDSCALE TRANSITION

7FH ≥ 80H

400ns/DIV

Figure 19. Clock Feedthrough and Midscale Transition Glitch

V

DD

(NO DE­COUPLING
CAPS)

V

WB0

(0xFF
STORED
IN EEMEM)

V

WB3

(0xFF
STORED
IN EEMEM)

MIDSCALE
PRESET

MIDSCALE
PRESET

Figure 20. t

RESTORE RDAC0
SETTING TO 0xFF

EEMEM_RESTORE

RESTORE RDAC3
SETTING TO 0xFF

VDD = VA0 = VA3 = 3.3V
GND = VB0 = VB3

of RDAC0 and RDAC3

= 5V

03824-0-031

03824-0-046

Rev. B | Page 12 of 32

AD5253/AD5254

www.BDTIC.com/ADI

6

6

5

(mA)

4

WB_MAX

3

RAB= 10kΩ

RAB= 100kΩ

0 8 16 24 32 40 48 56 64

THEORETICAL I

2

1

0

RAB= 1kΩ

RAB= 50kΩ

CODE (Decimal)

Figure 21. AD5253 I

vs. Code Figure 22. AD5254 I

WB_MAX

VA= VB= OPEN
T

=25°C

A

03824-0-033

RAB= 50kΩ

RAB= 1kΩ

CODE (Decimal)

WB_MAX

VA= VB= OPEN
T

=25°C

A

vs. Code

5

(mA)

4

WB_MAX

3

2

THEORETICAL I

1

0

0 32 64 96 128 160 192 224 256

RAB= 10kΩ

RAB= 100kΩ

03824-0-034

Rev. B | Page 13 of 32

AD5253/AD5254

www.BDTIC.com/ADI

I2C INTERFACE

t

2

SCL

t

8

t

t

6

9

t

2

3

t

8

SDA

t

t

1

PS

I2C INTERFACE GENERAL DESCRIPTION

From Master to Slave

From Slave to Master

S = start condition
P = stop condition
A = acknowledge (SDA low)

= not acknowledge (SDA high)

A
R/

= read enable at high; write enable at low

W

SLAVE ADDRESS

(7-BIT)

R/W A/AS

t

9

Figure 23. I

t

4

2

C Interface Timing Diagram

A

INSTRUCTIONS

(8-BIT)

t

7

t

5

S

A

DATA

(8-BIT)

t

10

03824-0-003

P

P

0 WRITE

Figure 24. I

2

C—Master Writing Data to Slave

DATA TRANSFERRED

(N BYTES + ACKNOWLEDGE)

03824-0-004

SLAVE ADDRESS

(7-BIT)

R/W AS

A A

1 READ

Figure 25. I

2

DATA

(8-BIT)

C—Master Reading Data from Slave

DATA TRANSFERRED

(N BYTES + ACKNOWLEDGE)

DATA

(8-BIT)

P

03824-0-005

SLAVE ADDRESS

(7-BIT)

R/W R/WS

A

READ OR WRITE (N BYTES +

DATA

ACKNOWLEDGE)

Figure 26. I

A/A

S

SLAVE ADDRESS

REPEATED START READ

DIRECTION OF TRANSFER MAY

2

C—Combined Write/Read

A

OR WRITE

CHANGE AT THIS POINT

DATA

(N BYTES +

ACKNOWLEDGE)

A/A

P

03824-0-006

Rev. B | Page 14 of 32

AD5253/AD5254

www.BDTIC.com/ADI

I2C INTERFACE DETAIL DESCRIPTION

From Master to Slave

From Slave to Master

S = start condition
P = stop condition
A = acknowledge (SDA low)

= not acknowledge (SDA high)

A
AD1, AD0 = I

R/

= read enable bit at logic high; write enable bit at logic low

W
CMD/
EE/

RDAC

A4, A3, A2, A1, A0 = RDAC/EEMEM register addresses

2

C device address bits, must match with the logic states at Pins AD1, AD0

= command enable bit at logic high; register access bit at logic low

REG

= EEMEM register at logic high; RDAC register at logic low

S 0 1 0 1 1 A

SLAVE ADDRESS INSTRUCTIONS

D
1

A
D
0

0 WRITE

0 A A4A3A2A1A0A PDATA0

CMD/

REG

0 REG

EE/

RDAC

AND ADDRESS

(1 BYTE +

ACKNOWLEDGE)

A/

A

03824-0-007

Figure 27. Single Write Mode

S 0 1 0 1 1 A

SLAVE ADDRESS INSTRUCTIONS

A

0 A A4A3A2A1A

D

1

D

0

0 WRITE

CMD/

REG

0 REG

Figure 28. Consecutive Write Mode

0

EE/

RDAC

AND ADDRESS

0

DATA

RDAC_N + 1

DATA

(N BYTE +

ACKNOWLEDGE)

A/

PA ARDAC_N

A

03824-0-008

Table 6. Addresses for Writing Data Byte Contents to RDAC Registers (R/

= 0, CMD/

W

REG

= 0, EE/

RDAC

= 0)

A4 A3 A2 A1 A0 RDAC Data Byte Description

0 0 0 0 0 RDAC0 6-/8-bit wiper setting (2 MSB of AD5253 are X)
0 0 0 0 1 RDAC1 6-/8-bit wiper setting (2 MSB of AD5253 are X)
0 0 0 1 0 RDAC2
0 0 0 1 1 RDAC3
0 0 1 0 0 Reserved
: : : : : :
: : : : : :

6-/8-bit wiper setting (2 MSB of AD5253 are X)
6-/8-bit wiper setting (2 MSB of AD5253 are X)

0 1 1 1 1 Reserved

Rev. B | Page 15 of 32

AD5253/AD5254

www.BDTIC.com/ADI

RDAC/EEMEM Write

Setting the wiper position requires an RDAC write operation.
The single write operation is shown in Figure 27, and the
consecutive write operation is shown in Figure 28. In the
consecutive write operation, if the

is selected and the

RDAC

address starts at 0, the first data byte goes to RDAC0, the second
data byte goes to RDAC1, the third data byte goes to RDAC2,
and the fourth data byte goes to RDAC3. This operation can be
continued for up to eight addresses with four unused addresses;
it then loops back to RDAC0. If the address starts at any of the
eight valid addresses, N, the data first goes to RDAC_N,
RDAC_N + 1, and so on; it loops back to RDAC0 after the
eighth address. The RDAC address is shown in . Tabl e 6

While the RDAC wiper setting is controlled by a specific
RDAC register, each RDAC register corresponds to a specific
EEMEM location, which provides nonvolatile wiper storage
functionality. The addresses are shown in Tab le 7 . The single
and consecutive write operations also apply to EEMEM write
operations.

There are 12 nonvolatile memory locations: EEMEM4 to
EEMEM15. Users can store 12 bytes of information, such as
memory data for other components, look-up tables, or system
identification information.

In a write operation to the EEMEM registers, the device disables

2

the I

C interface during the internal write cycle. Acknowledge
polling is required to determine the completion of the write
cycle. See the EEMEM Write-Acknowledge Polling section.

RDAC/EEMEM Read

The AD5253/AD5254 provide two different RDAC or EEMEM
read operations. For example, Figure 29 shows the method of
reading the RDAC0 to RDAC3 contents without specifying the
address, assuming Address RDAC0 was already selected in the
previous operation. If an RDAC_N address other than RDAC0
was previously selected, readback starts with Address N,
followed by N + 1, and so on.

Figure 30 illustrates a random RDAC or EEMEM read
operation. This operation allows users to specify which RDAC
or EEMEM register is read by issuing a dummy write command
to change the RDAC address pointer and then proceeding with
the RDAC read operation at the new address location.

Table 7. Addresses for Writing (Storing) RDAC Settings and
User-Defined Data to EEMEM Registers
(R/

= 0, CMD/

W

A4 A3 A2 A1 A0 Data Byte Description

0 0 0 0 0 Store RDAC0 setting to EEMEM01
0 0 0 0 1 Store RDAC1 setting to EEMEM11
0 0 0 1 0 Store RDAC2 setting to EEMEM21
0 0 0 1 1 Store RDAC3 setting to EEMEM31
0 0 1 0 0 Store user data to EEMEM4
0 0 1 0 1 Store user data to EEMEM5
0 0 1 1 0 Store user data to EEMEM6
0 0 1 1 1 Store user data to EEMEM7
0 1 0 0 0 Store user data to EEMEM8
0 1 0 0 1 Store user data to EEMEM9
0 1 0 1 0 Store user data to EEMEM10
0 1 0 1 1 Store user data to EEMEM11
0 1 1 0 0 Store user data to EEMEM12
0 1 1 0 1 Store user data to EEMEM13
0 1 1 1 0 Store user data to EEMEM14
0 1 1 1 1 Store user data to EEMEM15

REG

= 0, EE/

RDAC

= 1)

Table 8. Addresses for Reading (Restoring) RDAC Settings
and User Data from EEMEM
(R/

= 1, CMD/

W

A4 A3 A2 A1 A0 Data Byte Description

0 0 0 0 0 Read RDAC0 setting from EEMEM0
0 0 0 0 1 Read RDAC1 setting from EEMEM1
0 0 0 1 0 Read RDAC2 setting from EEMEM2
0 0 0 1 1 Read RDAC3 setting from EEMEM3
0 0 1 0 0 Read User data from EEMEM4
0 0 1 0 1 Read user data from EEMEM5
0 0 1 1 0 Read user data from EEMEM6
0 0 1 1 1 Read user data from EEMEM7
0 1 0 0 0 Read user data from EEMEM8
0 1 0 0 1 Read user data from EEMEM9
0 1 0 1 0 Read user data from EEMEM10
0 1 0 1 1 Read user data from EEMEM11
0 1 1 0 0 Read user data from EEMEM12
0 1 1 0 1 Read user data from EEMEM13
0 1 1 1 0 Read user data from EEMEM14
0 1 1 1 1 Read user data from EEMEM15

1

Users can store any of the 64 RDAC settings for AD5253 or any of the 256

RDAC settings for the AD5254 directly to the EEMEM. This is not limited to
current RDAC wiper setting.

REG

= 0, EE/

RDAC

= 1)

Rev. B | Page 16 of 32

AD5253/AD5254

www.BDTIC.com/ADI

From Master to Slave

From Slave to Master

S = start condition
P = stop condition
A = acknowledge (SDA low)

= not acknowledge (SDA high)

A
AD1, AD0 = I
R/

= read enable bit at logic high; write enable bit at logic low

W
CMD/
C3, C2, C1, C0 = command bits
A2, A1, A0 = RDAC/EEMEM register addresses

2

C device address bits, must match with the logic states at Pins AD1, AD0

= command enable bit at logic high; register access bit at logic low

REG

S 0 1 0 1 1 A

SLAVE ADDRESS (N BYTES + ACKNOWLEDGE)

A

1 A PARDAC_N OR EEMEM_N

D

D

1

0

1 READ

REGISTER DATA

RDAC_N + 1 OR EEMEM_N + 1

REGISTER DATA

A

03824-0-009

Figure 29. RDAC Current Read (Restricted to Previously Selected Address Stored in the Register)

A0A

0 WRITE

ADDRESS

REPEATED START 1 READ

SLAVE ADDRESSINSTRUCTIONAL AND

Figure 30. RDAC or EEMEM Random Read

A1S

RDAC OR

EEMEM DATA

(N BYTES + ACKNOWLEDGE)

A/A

PS SLAVE ADDRESS

03824-0-010

S 0 1 0 1 1 A

RDAC SLAVE ADDRESS

Figure 31. RDAC Quick Command Write (Dummy Write)

D
1

A
D

0

0 WRITE

CMD/

0 A C3C2C1C0A2A1A0A P

REG

1 CMD

03824-0-011

Rev. B | Page 17 of 32

AD5253/AD5254

www.BDTIC.com/ADI

RDAC/EEMEM Quick Commands

The AD5253/AD5254 feature 12 quick commands that facilitate
easy manipulation of RDAC wiper settings and provide RDAC­to-EEMEM storing and restoring functions. The command
format is shown in Figure 31, and the command descriptions
are shown in Ta ble 9 .

When using a quick command, issuing a third byte is not
needed, but is allowed. The quick commands reset and store
RDAC to EEMEM require acknowledge polling to determine
whether the command has finished executing.

RAB Tolerance Stored in Read-Only Memory

The AD5253/AD5254 feature patented RAB tolerances storage in
the nonvolatile memory. The tolerance of each channel is stored
in the memory during the factory production and can be read
by users at any time. The knowledge of the stored tolerance,
which is the average of R
users to predict R

AB

over all codes (see Figure 16), allows

AB

accurately. This feature is valuable for
precision, rheostat mode, and open-loop applications, in which
knowledge of absolute resistance is critical.

The stored tolerances reside in the read-only memory and are
expressed as percentages. Each tolerance is 16 bits long and is
stored in two memory locations (see Ta b le 1 0). The tolerance
data is expressed in sign magnitude binary format stored in two
bytes; an example is shown in Figure 32 . For the first byte in
Register N, the MSB is designated for the sign (0 = + and 1 = –)
and the 7 LSB is designated for the integer portion of the
tolerance. For the second byte in Register N + 1, all eight data

Table 9. RDAC-to-EEMEM Interface and RDAC Operation Quick Command Bits (CMD/

C3 C2 C1 C0 Command Description

0 0 0 0 NOP
0 0 0 1 Restore EEMEM (A1, A0) to RDAC (A1, A0)1
0 0 1 0 Store RDAC (A1, A0) to EEMEM (A1, A0)
0 0 1 1 Decrement RDAC (A1, A0) 6 dB
0 1 0 0 Decrement all RDACs 6 dB
0 1 0 1 Decrement RDAC (A1, A0) one step
0 1 1 0 Decrement all RDACs one step
0 1 1 1 Reset: restore EEMEMs to all RDACs
1 0 0 0 Increment RDACs (A1, A0) 6 dB
1 0 0 1 Increment all RDACs 6 dB
1 0 1 0 Increment RDACs (A1, A0) one step
1 0 1 1 Increment all RDACs one step
1 1 0 0 Reserved
:

:
1 1 1 1 Reserved

1

This command leaves the device in the EEMEM read power state, which consumes power. Issue the NOP command to return the device to its idle state.

:
:

:
:

:
:

:
:

bits are designated for the decimal portion of tolerance. As
shown in Tab l e 1 0 and Figure 32, for example, if the rated R

is

AB

10 kΩ and the data readback from Address 11000 shows 0001
1100 and Address 11001 shows 0000 1111, then RDAC0
tolerance can be calculated as

MSB: 0 = +
Next 7 MSB: 001 1100 = 28
8 LSB: 0000 1111 = 15 × 2

–8

= 0.06
Tolerance = 28.06% and, therefore,
R

AB_ACTUAL

= 12.806 kΩ

EEMEM Write-Acknowledge Polling

After each write operation to the EEMEM registers, an internal
write cycle begins. The I
determine if the internal write cycle is complete and the I
interface is enabled, interface polling can be executed. I

2

C interface of the device is disabled. To

2

C

2

C
interface polling can be conducted by sending a start condition
followed by the slave address and the write bit. If the I

2

C
interface responds with an ACK, the write cycle is complete and
the interface is ready to proceed with further operations. Other-

2

wise, I

C interface polling can be repeated until it succeeds.

Command 2 and Command 7 also require acknowledge polling.

EEMEM Write Protection

Setting the WP pin to logic low after EEMEM programming
protects the memory and RDAC registers from future write

operations. In this mode, the EEMEM and RDAC read
operations function as normal.

= 1, A2 = 0)

REG

Rev. B | Page 18 of 32

AD5253/AD5254

www.BDTIC.com/ADI

Table 10. Address Table for Reading Tolerance (CMD/

A4 A3 A2 A1 A0 Data Byte Description

1 1 0 0 0 Sign and 7-bit integer values of RDAC0 tolerance (read only)
1 1 0 0 1 8-bit decimal value of RDAC0 tolerance (read only)
1 1 0 1 0
1 1 0 1 1
1 1 1 0 0
1 1 1 0 1
1 1 1 1 0

Sign and 7-bit integer values of RDAC1 tolerance (read only)
8-bit decimal value of RDAC1 tolerance (read only)
Sign and 7-bit integer values of RDAC2 tolerance (read only)
8-bit decimal value of RDAC2 tolerance (read only)
Sign and 7-bit integer values of RDAC3 tolerance (read only)

1 1 1 1 1 8-bit decimal value of RDAC3 tolerance (read only)

AA

D7 D6 D5 D4 D3 D2 D1 D0

6252423222120

SIGN

2

REG

= 0, EE/

= 1, A4 = 1)

RDAC

D7 D6 D5 D4 D3 D2 D1 D0

2–12–22–32–42–52–62

A

–8

–7

2

SIGN

Figure 32. Format of Stored Tolerance in Sign Magnitude Format with Bit Position Descriptions (Unit is Percent, Only Data Bytes Are Shown)

7 BITS FOR INTEGER NUMBER

8 BITS FOR DECIMAL NUMBER

03824-0-012

Rev. B | Page 19 of 32

AD5253/AD5254

A

Y

XXXXXXX

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I2C-COMPATIBLE 2-WIRE SERIAL BUS

START B

MASTER

SCL
SD

1

1

0

11

0

FRAME 1

SLAVE ADDRESS BYTE

AD1 AD0

R/W

ACK. BY

AD525x

9

1

X

INSTRUCTION BYTE

Figure 33. General I

1

SCL

0

1

SDA

START BY

MASTER

0

FRAME1

SLAVE ADDRESS BYTE

11

AD1

AD0

Figure 34. General I

The first byte of the AD5253/AD5254 is a slave address byte
(see Figure 33 and Figure 34). It has a 7-bit slave address and an

W

R/

bit. The 5 MSB of the slave address is 01011, and the next
2 LSB is determined by the states of the AD1 and AD0 pins.
AD1 and AD0 allow the user to place up to four
AD5253/AD5254 devices on one bus.

2

AD5253/AD5254 can be controlled via an I

C-compatible serial

bus and are connected to this bus as slave devices. The 2-wire

2

I

C serial bus protocol (see Figure 33 and Figure 34) follows:

1. The master initiates a data transfer by establishing a start

condition, such that SDA goes from high to low while SCL

is high (see Figure 33). The following byte is the slave

address byte, which consists of the 5 MSB of a slave address

2

defined as 01011. The next two bits are AD1 and AD0, I

C
device address bits. Depending on the states of their AD1
and AD0 bits, four AD5253/AD5254 devices can be
addressed on the same bus. The last LSB, the R/

W

bit,
determines whether data is read from or written to the
slave device.

The slave whose address corresponds to the transmitted
address responds by pulling the SDA line low during the
ninth clock pulse (this is called an acknowledge bit). At
this stage, all other devices on the bus remain idle while
the selected device waits for data to be written to or read
from its serial register.

2. In the write mode (except when restoring EEMEM to the

RDAC register), there is an instruction byte that follows
the slave address byte. The MSB of the instruction byte is
labeled CMD/

. MSB = 1 enables CMD, the command

REG

instruction byte; MSB = 0 enables general register writing.
The third MSB in the instruction byte, labeled EE/

RDAC

,

is true when MSB = 0 or when the device is in general
writing mode. EE enables the EEMEM register, and REG
enables the RDAC register. The 5 LSB, A4 to A0, designates

Rev. B | Page 20 of 32

9

1

D6 D5

D7

ACK. BY

AD525x

FRAME 2

2

C Write Pattern

91 9

R/W

ACK. BY

AD525x

D7 D6 D5 D4 D3 D2

FRAME 2

RDAC REGISTER

2

C Read Pattern

D1 D0

the addresses of the EEMEM and RDAC registers (see
Figure 27 Figure 28

and ). When MSB = 1 or when the
device is in CMD mode, the four bits following the MSB
are C3 to C1, which correspond to 12 predefined EEMEM
controls and quick commands; there are also four factory­reserved commands. The 3 LSB—A2, A1, and A0—are 4­channel RDAC addresses (see ). After
acknowledging the instruction byte, the last byte in the
write mode is the data byte. Data is transmitted over the
serial bus in sequences of nine clock pulses (eight data bits
followed by an acknowledge bit). The transitions on the
SDA line must occur during the low period of SCL and
remain stable during the high period of SCL (see ).

3. In current read mode, the RDAC0 data byte immediately

follows the acknowledgment of the slave address byte.
After an acknowledgement, RDAC1 follows, then RDAC2,
and so on. (There is a slight difference in write mode,
where the last eight data bits representing RDAC3 data are
followed by a no acknowledge bit.) Similarly, the
transitions on the SDA line must occur during the low
period of SCL and remain stable during the high period of
SCL (see Figure 34). Another reading method, random
read method, is shown in Figure 30.

4. When all data bits have been read or written, a stop

condition is established by the master. A stop condition is
defined as a low-to-high transition on the SDA line that
occurs while SCL is high. In write mode, the master pulls
the SDA line high during the 10
stop condition (see Figure 33). In read mode, the master
issues a no acknowledge for the ninth clock pulse, that is,
the SDA line remains high. The master brings the SDA line
low before the 10
line high to establish a stop condition (see Figure 34).

D4 D3 D2 D1

FRAME 1

DATA BYTE

NO ACK. BY

MASTER

STOP BY
MASTER

th

clock pulse and then brings the SDA

9

D0

ACK. BY

AD525x

STOP BY

03824-0-014

MASTER

03824-0-013

Figure 31

Figure 33

th

clock pulse to establish a

AD5253/AD5254

www.BDTIC.com/ADI

THEORY OF OPERATION

The AD5253/AD5254 are quad-channel digital potentiometers
in 1 kΩ, 10 kΩ, 50 kΩ, or 100 kΩ that allow 64/256 linear resis­tance step adjustments. The AD5253/AD5254 employ double­gate CMOS EEPROM technology, which allows resistance
settings and user-defined data to be stored in the EEMEM
registers. The EEMEM is nonvolatile, such that settings remain
when power is removed. The RDAC wiper settings are restored
from the nonvolatile memory settings during device power-up
and can also be restored at any time during operation.

The AD5253/AD5254 resistor wiper positions are determined
by the RDAC register contents. The RDAC register acts like a
scratch-pad register, allowing unlimited changes of resistance
settings. RDAC register contents can be changed using the
device’s serial I

2

C interface. The format of the data-words and

the commands to program the RDAC registers are discussed in

2

the I

C Interface section.

The four RDAC registers have corresponding EEMEM memory
locations that provide nonvolatile storage of resistor wiper
position settings. The AD5253/AD5254 provide commands to
store the RDAC register contents to their respective EEMEM
memory locations. During subsequent power-on sequences, the
RDAC registers are automatically loaded with the stored value.

Whenever the EEMEM write operation is enabled, the device
activates the internal charge pump and raises the EEMEM cell
gate bias voltage to a high level; this essentially erases the
current content in the EEMEM register and allows subsequent
storage of the new content. Saving data to an EEMEM register
consumes about 35 mA of current and lasts approximately
26 ms. Because of charge-pump operation, all RDAC channels
may experience noise coupling during the EEMEM writing
operation.

The EEMEM restore time in power-up or during operation is
about 300 μs. Note that the power-up EEMEM refresh time
depends on how fast V

reaches its final value. As a result, any

DD

supply voltage decoupling capacitors limit the EEMEM restore
time during power-up. For example, Figure 20 shows the
power-up profile of the V

where there is no decoupling

DD

capacitors and the applied power is a digital signal. The device
initially resets the RDACs to midscale before restoring the
EEMEM contents. The omission of the decoupling capacitors
should only be considered when the fast restoring time is
absolutely needed in the application. In addition, users should
issue a NOP Command 0 immediately after using Command 1
to restore the EEMEM setting to RDAC, thereby minimizing
supply current dissipation. Reading user data directly from
EEMEM does not require a similar NOP command execution.

In addition to the movement of data between RDAC and
EEMEM registers, the AD5253/AD5254 provide other shortcut
commands that facilitate programming, as shown in Tabl e 11 .

Table 11. Quick Commands

Command Description

0 NOP.
1

2 Store RDAC register setting to EEMEM.
3 Decrement RDAC 6 dB (shift data bits right).
4 Decrement all RDACs 6 dB (shift all data bits right).
5 Decrement RDAC one step.
6 Decrement all RDACs one step.
7 Reset EEMEM contents to all RDACs.
8 Increment RDAC 6 dB (shift data bits left).
9 Increment all RDACs 6 dB (shift all data bits left).
10 Increment RDAC one step.
11 Increment all RDACs one step.
12 to 15 Reserved.

Restore EEMEM content to RDAC. User should
issue NOP immediately after this command to
conserve power.

LINEAR INCREMENT/DECREMENT COMMANDS

The increment and decrement commands (10, 11, 5, and 6) are
useful for linear step-adjustment applications. These commands
simplify microcontroller software coding by allowing the
controller to send just an increment or decrement command to
the AD5253/AD5254. The adjustments can be directed to a
single RDAC or to all four RDACs.

±6 dB ADJUSTMENTS (DOUBLING/HALVING WIPER SETTING)

The AD5253/AD5254 accommodate ±6 dB adjustments of the
RDAC wiper positions by shifting the register contents to left/
right for increment/decrement operations, respectively. Com­mand 3, Command 4, Command 8, and Command 9 can be
used to increment or decrement the wiper positions in 6 dB
steps synchronously or asynchronously.

Incrementing the wiper position by +6 dB essentially doubles
the RDAC register value, whereas decrementing the wiper
position by –6 dB halves the register content. Internally, the
AD5253/AD5254 use shift registers to shift the bits left and
right to achieve a ±6 dB increment or decrement. The
maximum number of adjustments is nine and eight steps for
incrementing from zero scale and decrementing from full scale,
respectively. These functions are useful for various audio/video
level adjustments, especially for white LED brightness settings
in which human visual responses are more sensitive to large
adjustments than to small adjustments.

Rev. B | Page 21 of 32

AD5253/AD5254

S

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DIGITAL INPUT/OUTPUT CONFIGURATION

SDA is a digital input/output with an open-drain MOSFET that
requires a pull-up resistor for proper communication. On the
other hand, SCL and

resistors are recommended to minimize the MOSFET cross­conduction current when the driving signals are lower than
V

. SCL and WP have ESD protection diodes, as shown in

DD

and . Figure 35 Figure 36

can be permanently tied to VDD without a pull-up resistor if

WP
the write-protect feature is not used. If
internal current source pulls it low to enable write protection. In
applications in which the device is programmed infrequently,
this allows the part to default to write-protection mode after
any one-time factory programming or field calibration without
using an on-board pull-down resistor. Because there are
protection diodes on all inputs, the signal levels must not be
greater than V

to prevent forward biasing of the diodes.

DD

are digital inputs for which pull-up

WP

is left floating, an

WP

V

DD

MULTIPLE DEVICES ON ONE BUS

The AD5253/AD5254 are equipped with two addressing pins,
AD1 and AD0, that allow up to four AD5253/AD5254 devices
to be operated on one I
AD1 and AD0 on each device must first be defined. An example
is shown in Tabl e 12 and Figure 37. In I
device is issued a different slave address—01011(AD1)(AD0)—
to complete the addressing.

Table 12. Multiple Devices Addressing

AD1 AD0 Device Addressed

0 0 U1
0 1 U2
1 0
1 1 U4

R

PRP

MASTER

2

C bus. To achieve this result, the states of

2

C programming, each

U3

5V

5V

5V

5V

SDA

SCL

CL

GND

Figure 35. SCL Digital Input

SCL

SDA

AD1
AD0

AD5253/
AD5254

03824-0-035

V

DD

Figure 37. Multiple AD5253/AD5254 Devices on a Single Bus

In wireless base station smart-antenna systems that require
arrays of digital potentiometers to bias the power amplifiers,
large numbers of AD5253/AD5254 devices can be addressed by

SDA

SCL SDA

AD1
AD0

AD5253/
AD5254

SCL SDA

AD1
AD0

AD5253/
AD5254

SCL

AD1
AD0

AD5253/
AD5254

03824-0-037

using extra decoders, switches, and I/O buses, as shown in

INPUTS

Figure 38. For example, to communicate to a total of 16 devices,
four decoders and 16 sets of combinational switches (four sets

WP

shown in Figure 38) are needed. Two I/O buses serve as the
common inputs of the four 2 × 4 decoders and select four sets
of outputs at each combination. Because the four sets of

03824-0-036

GND

Figure 36. Equivalent

WP

Digital Input

combination switch outputs are unique, as shown in Figure 38,
a specific device is addressed by properly programming the I

2

C
with the slave address defined as 01011(AD1)(AD0). This
operation allows one of 16 devices to be addressed, provided
that the inputs of the two decoders do not change states. The
inputs of the decoders are allowed to change once the operation
of the specified device is completed.

Rev. B | Page 22 of 32

AD5253/AD5254

V

V

www.BDTIC.com/ADI

+5V

X

+5V

+5V

X

+5V

× 4

AD1
AD0

× 4

AD1

+5

P2

Y

P2

Y

R3

N3

Y

× 4

× 4

AD0

AD1

Y

AD0

AD1
AD0

03824-0-038

2 × 4
DECODER

2 × 4
DECODER

2 × 4
DECODER

2 × 4
DECODER

R1

N142

R2

X

4

4

4

N2

X

P3

R3

P4

R4

Figure 38. Four Devices with AD1 and AD0 of 00

TERMINAL VOLTAGE OPERATION RANGE

The AD5253/AD5254 are designed with internal ESD diodes
for protection; these diodes also set the boundaries for the
terminal operating voltages. Positive signals present on
Ter mi n al A, Te rm in a l B , or Te r m in al W th a t e x ce ed V
clamped by the forward-biased diode. Similarly, negative signals
on Te rm in a l A , Te rm in a l B , or Te rm in a l W th at a re m ore
negative than V
users should not operate V
the voltage across V

are also clamped (see Figure 39). In practice,

SS

, VWA, and VWB to be higher than

AB

to VSS, but VAB, VWA, and VWB have no

DD

polarity constraint.

DD

are

V

DD

A

W

B

V

SS

Figure 39. Maximum Terminal Voltages Set by V

and V

DD

03824-0-039

SS

POWER-UP AND POWER-DOWN SEQUENCES

Because the ESD protection diodes limit the voltage compliance
at Te rm i na l A , Ter mi na l B, a nd Te rm in a l W (Figure 39), it is
important to power V

before applying any voltage to

DD/VSS

these terminals. Otherwise, the diodes are forward biased such
that V
user’s circuit. Similarly, V

are powered unintentionally and may affect the

DD/VSS

should be powered down last.

DD/VSS

The ideal power-up sequence is in the following order: GND,
V

, VSS, digital inputs, and VA/VB/VW. The order of powering

DD

V

, VB, VW, and the digital inputs is not important, as long as

A

they are powered after V

DD/VSS

.

LAYOUT AND POWER SUPPLY BIASING

It is always a good practice to employ a compact, minimum
lead-length layout design. The leads to the input should be as
direct as possible, with a minimum conductor length. Ground
paths should have low resistance and low inductance.

Similarly, it is also good practice to bypass the power supplies
with quality capacitors. Low equivalent series resistance (ESR)
1 μF to 10 μF tantalum or electrolytic capacitors should be
applied at the supplies to minimize any transient disturbance
and filter low frequency ripple. Figure 40 illustrates the basic
supply-bypassing configuration for the AD5253/AD5254.

AD5253/AD5254

DD

SS

C1

C3

10μF

0.1μF

C4

C2

10μF

0.1μF

Figure 40. Power Supply-Bypassing Configuration

The ground pin of the AD5253/AD5254 is used primarily as a
digital ground reference. To minimize the digital ground
bounce, the AD5253/AD5254 ground terminal should be joined
remotely to the common ground (see Figure 40).

V

DD

V

SS

GND

03824-0-040

Rev. B | Page 23 of 32

AD5253/AD5254

www.BDTIC.com/ADI

DIGITAL POTENTIOMETER OPERATION

The structure of the RDAC is designed to emulate the
performance of a mechanical potentiometer. The RDAC
contains a string of resistor segments with an array of analog
switches that act as the wiper connection to the resistor array.
The number of points is the resolution of the device. For
example, the AD5253/AD5254 emulate 64/256 connection
points with 64/256 equal resistance, R
provide better than 1.5%/0.4% resolution.

Figure 41 provides an equivalent diagram of the connections
between the three terminals that make up one channel of the
RDAC. Switches SW
switches SW(0) to SW(2

and SWB are always on, but only one of

A

N–1

) can be on at a time (determined by
the setting decoded from the data bit). Because the switches are
nonideal, there is a 75 Ω wiper resistance, R
is a function of supply voltage and temperature: Lower supply
voltages and higher temperatures result in higher wiper
resistances. Consideration of wiper resistance dynamics is
important in applications in which accurate prediction of
output resistance is required.

RDAC

WIPER

REGISTER

AND

DECODER

R

S

, allowing them to

S

SW

A

SW (2N– 1)

N

SW (2

– 2)

. Wiper resistance

W

A

X

W

X

PROGRAMMABLE RHEOSTAT OPERATION

If either the W-to-B or W-to-A terminal is used as a variable
resistor, the unused terminal can be opened or shorted with W;
such operation is called rheostat mode (see Figure 42). The
resistance tolerance can range ±20%.

A

W

B

Figure 42. Rheostat Mode Configuration

The nominal resistance of the AD5253/AD5254 has 64/256
contact points accessed by the wiper terminal, plus the B
terminal contact. The 6-/8-bit data-word in the RDAC register
is decoded to select one of the 64/256 settings. The wiper’s first
connection starts at the B terminal for Data 0x00. This B termi­nal connection has a wiper contact resistance, R
regardless of the nominal resistance. The second connection
(the AD5253 10 kΩ part) is the first tap point where R
(R

= RAB/64 + RW = 156 Ω + 75 Ω) for Data 0x01, and so on.

WB

Each LSB data value increase moves the wiper up the resistor
ladder until the last tap point is reached at R
Figure 41 for a simplified diagram of the equivalent RDAC circuit.

The general equation that determines the digitally programmed
output resistance between W and B is

AD5253: RWB(D) = (D/64) × RAB + 75 Ω (1)

AD5254: RWB(D) = (D/256) × RAB + 75 Ω (2)

A

W

B

A

W

B

, of 75 Ω,

W

WB

= 9893 Ω. See

WB

03824-0-042

= 231 Ω

where:

R

S

SW(1)

R

S

SW(0)

RS= RAB/2

DIGITAL
CIRCUITRY
OMIITTED FOR
CLARITY

N

SW

B

Figure 41. Equivalent RDAC Structure

B

X

03824-0-041

D is the decimal equivalent of the data contained in the
RDAC latch.

R

is the nominal end-to-end resistance.

AB

Rev. B | Page 24 of 32

AD5253/AD5254

www.BDTIC.com/ADI

(%)

AB

R

100

R

WA

75

50

25

R

WB

PROGRAMMABLE POTENTIOMETER OPERATION

If all three terminals are used, the operation is called potenti­ometer mode (see Figure 44); the most common configuration
is the voltage divider operation.

V

I

Figure 44. Potentiometer Mode Configuration

A

V

C

W

B

03824-0-044

0

0

Figure 43. AD5253 R

10 32 48 63

D (Code in Decimal)

(D) and RWB(D) vs. Decimal Code

WA

03824-0-043

Since the digital potentiometer is not ideal, a 75 Ω finite wiper
resistance is present that can easily be seen when the device is
programmed at zero scale. Because of the fine geometric and
interconnects employed by the device, care should be taken to
limit the current conduction between W and B to no more than
±5 mA continuous for a total resistance of 1 kΩ or a pulse of
±20 mA to avoid degradation or possible destruction of the
device. The maximum dc current for AD5253 and AD5254 are
shown in Figure 21 and Figure 22, respectively.

Similar to the mechanical potentiometer, the resistance of the
RDAC between Wiper W and Terminal A also produces a
digitally controlled complementary resistance, R
terminals are used, the B terminal can be opened. The R

. When these

WA

WA

starts at a maximum value and decreases as the data loaded into
the latch increases in value (see Figure 43. The general equation
for this operation is

AD5253: RWA(D) = [(64 – D)/64] × RAB + 75 Ω (3)

AD5254: RWA(D) = [(256 – D)/256] × RAB + 75 Ω (4)

The typical distribution of R

from channel-to-channel

AB

matches is about ±0.15% within a given device. On the other
hand, device-to-device matching is process-lot dependent with
a ±20% tolerance.

If the wiper resistance is ignored, the transfer function is simply

AD5253:

AD5254:

V +×=

W

V +×=

W

D

64

D

256

(5)

VV

B

AB

(6)

VV

B

AB

A more accurate calculation that includes the wiper resistance
effect is

D

+

RR

W

AB

N

2

)(

where 2

= (7)

DV

W

N

is the number of steps.

+

AB

V

A

RR

2

W

Unlike in rheostat mode operation, where the tolerance is high,
potentiometer mode operation yields an almost ratiometric

N

function of D/2
R

terms. Therefore, the tolerance effect is almost cancelled.

W

with a relatively small error contributed by the

Similarly, the ratiometric adjustment also reduces the
temperature coefficient effect to 50 ppm/°C, except at low value
codes where R

dominates.

W

Potentiometer mode operations include other applications such
as op amp input, feedback-resistor networks, and other voltage­scaling applications. The A, W, and B terminals can, in fact, be
input or output terminals, provided that |V
not exceed V

to VSS.

DD

|, |VW|, and |VB| do

A

Rev. B | Page 25 of 32

AD5253/AD5254

www.BDTIC.com/ADI

APPLICATIONS INFORMATION

RGB LED BACKLIGHT CONTROLLER FOR LCD PANELS

Because high power (>1 W) RGB LEDs offer superior color
quality compared with cold cathode florescent lamps (CCFLs)
as backlighting sources, it is likely that high-end LCD panels
will employ RGB LEDs as backlight in the near future. Unlike
conventional LEDs, high power LEDs have a forward voltage of
2 V to 4 V and consume more than 350 mA at maximum
brightness. The LED brightness is a linear function of the
conduction current, but not of the forward voltage. To increase
the brightness of a given color, multiple LEDs can be connected
in series, rather than in parallel, to achieve uniform brightness.
For example, three red LEDs configured in series require an
average of 6 V to 12 V headroom, but the circuit operation
requires current control. As a result, Figure 45 shows the
implementation of one high power RGB LED controller using a
AD5254, a boost regulator, an op amp, and power MOSFETs.

The ADP1610 (U2 in Figure 45) is an adjustable boost regulator
with its output adjusted by the AD5254’s RDAC3. Such an
output should be set high enough for proper operation but low
enough to conserve power. The ADP1610’s 1.2 V band gap
reference is buffered to provide the reference level for the
voltage dividers set by the AD5254’s RDAC0 to RDAC2 and
Resistor R2 to Resistor R4. For example, by adjusting the
AD5254’s RDAC0, the desirable voltage appears across the
sense resistors, R
and power MOSFET N1 do whatever is necessary to regulate
the current of the loop. As a result, the current through the
sense resistor and the red LEDs is

I =

R

R8 is needed to prevent oscillation.

In addition to the 256 levels of adjustable current/brightness,
users can also apply a PWM signal at U3’s

finer brightness resolution or better power efficiency.

. If U2’s output is set properly, op amp U3A

R

V

RR

(8)

R

R

pin to achieve

SD

Rev. B | Page 26 of 32

AD5253/AD5254

www.BDTIC.com/ADI

+5V

C10

10μF

C1

0.1μF

U3D

AD8594

SCL
SDA

R4 R3 R2

L1 - SLF6025-100M1R0
D1 - MBR0520LT1

R7R6

22kΩ 22kΩ

V

= 2.5V

REF

250kΩ 250kΩ

U1

V

DD

RDAC3

CLK
SDI

10kΩ

R1

R5

A3

B3

10kΩ

100kΩ

R

C

C

AD5254

250kΩ

RDAC2

10kΩ

RDAC1

10kΩ

RDAC0

10kΩ

V

GND AD0 AD1

SS

A2

W2

B2

A1

W1

B1

A0

W0

B0

Figure 45. Digital Potentiometer-Based RGB LED Controller

10kΩ

C

390μF

U2

IN

ADP1610

SW

FB
SD
COMP

SS RT GND

C

SS

10μF

PWM

SD

L1

+5V

V+

AD8594

V–

U3B

AD8594

U3A

AD8594

10μF
D1

C11

8

U3C

4

C3

0.1μF

10μF

R10

4.7Ω

N3

RB

R9

4.7Ω

DB1

DB2

DB3

VB

IB

IRFL3103

VRB

0.1Ω
N2

RG

R8

4.7Ω

DG1

DG2

DG3

IG

VG

IRFL3103

VRG

0.1Ω
N1

RR

V

OUT

DR1

DR2

DR3

IR

VR

IRFL3103

VRR

0.1Ω

03824-0-045

Rev. B | Page 27 of 32

AD5253/AD5254

Y

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

6.60

6.50

6.40

PIN 1

0.15

0.05

COPLANARIT

20

1

0.65

BSC

0.30

0.19

0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AC

1.20 MAX

11

10

SEATING
PLANE

4.50

4.40

4.30

6.40 BSC

0.20

0.09
8°

0°

0.75

0.60

0.45

Figure 46. 20-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-20)

Dimensions shown in millimeters

Rev. B | Page 28 of 32

AD5253/AD5254

www.BDTIC.com/ADI

ORDERING GUIDE

Package

Model1 Step R

(kΩ) Temperature Range Package Description

AB

Option

AD5253BRU1 64 1 −40°C to +85°C 20-Lead TSSOP RU-20 75
AD5253BRU1-RL7 64 1 −40°C to +85°C 20-Lead TSSOP RU-20 1,000
AD5253BRUZ12 64 1 −40°C to +85°C 20-Lead TSSOP RU-20 75
AD5253BRUZ1-RL72 64 1 −40°C to +85°C 20-Lead TSSOP RU-20 1,000
AD5253BRU10 64 10 −40°C to +85°C 20-Lead TSSOP RU-20 75
AD5253BRU10-RL7 64 10 −40°C to +85°C 20-Lead TSSOP RU-20 1,000
AD5253BRUZ102 64 10 −40°C to +85°C 20-Lead TSSOP RU-20 75
AD5253BRUZ10-RL72 64 10 −40°C to +85°C 20-Lead TSSOP RU-20 1,000
AD5253BRU50 64 50 −40°C to +85°C 20-Lead TSSOP RU-20 75
AD5253BRU50-RL7 64 50 −40°C to +85°C 20-Lead TSSOP RU-20 1,000
AD5253BRUZ502 64 50 −40°C to +85°C 20-Lead TSSOP RU-20 75
AD5253BRUZ50-RL72 64 50 −40°C to +85°C 20-Lead TSSOP RU-20 1,000
AD5253BRU100 64 100 −40°C to +85°C 20-Lead TSSOP RU-20 75
AD5253BRU100-RL7 64 100 −40°C to +85°C 20-Lead TSSOP RU-20 1,000
AD5253BRUZ1002 64 100 −40°C to +85°C 20-Lead TSSOP RU-20 75
AD5253BRUZ100-RL72 64 100 −40°C to +85°C 20-Lead TSSOP RU-20 1,000
AD5253EVAL 64 10 Evaluation Board 1
AD5254BRU1 256 1 −40°C to +85°C 20-Lead TSSOP RU-20 75
AD5254BRU1-RL7 256 1 −40°C to +85°C 20-Lead TSSOP RU-20 1,000
AD5254BRUZ12 256 1 −40°C to +85°C 20-Lead TSSOP RU-20 75
AD5254BRUZ1-RL72 256 1 −40°C to +85°C 20-Lead TSSOP RU-20 1,000
AD5254BRU10 256 10 −40°C to +85°C 20-Lead TSSOP RU-20 75
AD5254BRU10-RL7 256 10 −40°C to +85°C 20-Lead TSSOP RU-20 1,000
AD5254BRUZ102 256 10 −40°C to +85°C 20-Lead TSSOP RU-20 75
AD5254BRUZ10-RL72 256 10 −40°C to +85°C 20-Lead TSSOP RU-20 1,000
AD5254BRU50 256 50 −40°C to +85°C 20-Lead TSSOP RU-20 75
AD5254BRU50-RL7 256 50 −40°C to +85°C 20-Lead TSSOP RU-20 1,000
AD5254BRUZ502 256 50 −40°C to +85°C 20-Lead TSSOP RU-20 75
AD5254BRUZ50-RL72 256 50 −40°C to +85°C 20-Lead TSSOP RU-20 1,000
AD5254BRU100 256 100 −40°C to +85°C 20-Lead TSSOP RU-20 75
AD5254BRU100-RL7 256 100 −40°C to +85°C 20-Lead TSSOP RU-20 1,000
AD5254BRUZ1002 256 100 −40°C to +85°C 20-Lead TSSOP RU-20 75
AD5254BRUZ100-RL72 256 100 −40°C to +85°C 20-Lead TSSOP RU-20 1,000
EVAL-AD5254EBZ2 256 10 Evaluation Board 1

1

In the package marking, Line 1 shows the part number. Line 2 shows the branding information, such that B1 = 1 kΩ, B10 = 10 kΩ, and so on. There is also a

“#” marking for the Pb-free part. Line 3 shows the date code in YYWW.

2

Z = RoHS Compliant Part.

Ordering
Quantity

Rev. B | Page 29 of 32

AD5253/AD5254

www.BDTIC.com/ADI

NOTES

Rev. B | Page 30 of 32

AD5253/AD5254

www.BDTIC.com/ADI

NOTES

Rev. B | Page 31 of 32

AD5253/AD5254

www.BDTIC.com/ADI

NOTES

Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.

© 2003–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03824-0-10/09(B)

Rev. B | Page 32 of 32