ANALOG DEVICES AD5253, AD5254 Service Manual

Quad 64-/256-Position I2C Nonvolatile

www.BDTIC.com/ADI

FEATURES

AD5253: quad 64-position resolution
AD5254: quad 256-position resolution
1 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Nonvolatile memory
Power-on refreshed to EEMEM settings in 300 μs typ
EEMEM rewrite time = 540 μs typ
Resistance tolerance stored in nonvolatile memory
12 extra bytes in EEMEM for user-defined information

2

C-compatible serial interface

I
Direct read/write access of RDAC
Predefined linear increment/decrement commands
Predefined ±6 dB step change commands
Synchronous or asynchronous quad-channel update
Wiper setting readback
4 MHz bandwidth—1 kΩ version
Single supply 2.7 V to 5.5 V
Dual supply ±2.25 V to ±2.75 V
2 slave address-decoding bits allow operation of 4 devices
100-year typical data retention, T
Operating temperature: –40°C to +85°C

APPLICATIONS

Mechanical potentiometer replacement
Low resolution DAC replacement
RGB LED backlight control
White LED brightness adjustment
RF base station power amp bias control
Programmable gain and offset control
Programmable attenuators
Programmable voltage-to-current conversion
Programmable power supply
Programmable filters
Sensor calibrations

GENERAL DESCRIPTION

The AD5253/AD5254 are quad-channel, I2C®, nonvolatile
mem-ory, digitally controlled potentiometers with 64/256
positions, respectively. These devices perform the same
electronic adjust-ment functions as mechanical potentiometers,
trimmers, and variable resistors.

The parts’ versatile programmability allows multiple modes of
operation, including read/write access in the RDAC and EEMEM
registers, increment/decrement of resistance, resistance changes
in ±6 dB scales, wiper setting readback, and extra EEMEM for
storing user-defined information, such as memory data for other
components, look-up table, or system identification information.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

1

stores wiper settings w/write protection

2

and EEMEM registers

= 55°C

A

Memory Digital Potentiometers

AD5253/AD5254

FUNCTIONAL BLOCK DIAGRAM

V

DD

V

SS

DGND

WP

SCL
SDA

AD0
AD1

SERIAL

INTERFACE

The AD5253/AD5254 allow the host I2C controllers to write
any of the 64-/256-step wiper settings in the RDAC registers
and store them in the EEMEM. Once the settings are stored,
they are restored automatically to the RDAC registers at system
power-on; the settings can also be restored dynamically.

The AD5253/AD5254 provide additional increment,
decrement, +6 dB step change, and –6 dB step change in
synchronous or asynchronous channel update mode. The
increment and decrement functions allow stepwise linear
adjustments, with a ± 6 dB step change equivalent to doubling
or halving the RDAC wiper setting. These functions are useful
for steep-slope, nonlinear adjustments, such as white LED
brightness and audio volume control.

The AD5253/AD5254 have a patented resistance-tolerance
storing function that allows the user to access the EEMEM and
obtain the absolute end-to-end resistance values of the RDACs
for precision applications.

The AD5253/AD5254 are available in TSSOP-20 packages in
1 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ options. All parts are
guaranteed to operate over the –40°C to +85°C extended
industrial temperature range.

1

The terms nonvolatile memory and EEMEM are used interchangeably.

2

The terms digital potentiometer and RDAC are used interchangeably.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003–2009 Analog Devices, Inc. All rights reserved.

RDAC EEMEM

EEMEM

POWER-ON

REFRESH

DATA

I2C

CONTROL

COMMAND

DECODE LOGIC

ADDRESS

DECODE LOGIC

CONTROL LOGIC

AD5253/AD5254

RAB TOL

Figure 1.

RDAC0
REGIS-

TER

RDAC1
REGIS-

TER

RDAC2
REGIS-

TER

RDAC3
REGIS-

TER

RDAC0

RDAC1

RDAC2

RDAC3

A0
W0
B0

A1
W1
B1

A2
W2
B2

A3
W3
B3

03824-0-001

AD5253/AD5254

www.BDTIC.com/ADI

TABLE OF CONTENTS

Features .............................................................................................. 1

I2C-Compatible 2-Wire Serial Bus ........................................... 20

Applications ....................................................................................... 1 

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Electrical Characteristics ................................................................. 3

1 kΩ Version .................................................................................. 3

10 kΩ, 50 kΩ, 100 kΩ Versions .................................................. 5

Interface Timing Characteristics ................................................ 7

Absolute Maximum Ratings ............................................................ 8

ESD Caution .................................................................................. 8

Pin Configuration and Function Descriptions ............................. 9

Typical Performance Characteristics ........................................... 10

I2C Interface ..................................................................................... 14

I2C Interface General Description ............................................ 14

I2C Interface Detail Description ............................................... 15

Theory of Operation ...................................................................... 21

Linear Increment/Decrement Commands ............................. 21

±6 dB Adjustments (Doubling/Halving Wiper Setting) ....... 21

Digital Input/Output Configuration........................................ 22

Multiple Devices on One Bus ................................................... 22

Terminal Voltage Operation Range ......................................... 23

Power-Up and Power-Down Sequences .................................. 23

Layout and Power Supply Biasing ............................................ 23

Digital Potentiometer Operation ............................................. 24

Programmable Rheostat Operation ......................................... 24

Programmable Potentiometer Operation ............................... 25

Applications Information .............................................................. 26

RGB LED Backlight Controller for LCD Panels .................... 26

Outline Dimensions ....................................................................... 28

Ordering Guide .......................................................................... 29

REVISION HISTORY

10/09—Rev. A to Rev. B

Change to Figure 27 ....................................................................... 15

9/05—Rev. 0 to Rev. A

Change to Figure 6 ......................................................................... 10

Change to EEMEM Write Protection Section ............................ 18

Changes to Figure 37 ...................................................................... 22

Deleted Table 13 and Table 14 ...................................................... 24

Change to Figure 43 ....................................................................... 25

Changes to Ordering Guide .......................................................... 29

5/03—Revision 0: Initial Version

Rev. B | Page 2 of 32

AD5253/AD5254

www.BDTIC.com/ADI

ELECTRICAL CHARACTERISTICS

1 kΩ VERSION

VDD = +3 V ± 10% or +5 V ± 10%, VSS = 0 V or VDD/VSS = ±2.5 V ± 10%, VA = VDD, VB = 0 V, –40°C < TA < +85°C, unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ1 Max Unit

DC CHARACTERISTICS—

RHEOSTAT MODE
Resolution N AD5253 6 Bits
AD5254 8 Bits
Resistor Differential Nonlinearity2
R
R
R
Resistor Nonlinearity2 R-INL RWB, RWA = NC, VDD = 5.5 V, AD5253 –0.5 ±0.2 +0.5 LSB
R
R
R
Nominal Resistor Tolerance ΔRAB/RAB T
Resistance Temperature Coefficient (ΔRAB/RAB) × 106/ΔT 650 ppm/°C
Wiper Resistance RW I
I
Channel-Resistance Matching ΔR

DC CHARACTERISTICS—

POTENTIOMETER DIVIDER MODE
Differential Nonlinearity3 DNL AD5253 –0.5 ±0.1 +0.5 LSB
AD5254 –1.00 ±0.25 +1.00 LSB
Integral Nonlinearity3 INL AD5253 –0.5 ±0.2 +0.5 LSB
AD5254 –2.0 ±0.5 +2.0 LSB
Voltage Divider Tempco (ΔVW/VW) × 106/ΔT Code = half scale 25 ppm/°C
Full-Scale Error V
Code = full scale, VDD = 5.5 V, AD5254 –16 –11 0 LSB
Code = full scale, VDD = 2.7 V, AD5253 –6 –4 0 LSB
Code = full scale, VDD = 2.7 V, AD5254 –23 –16 0 LSB
Zero-Scale Error V
Code = zero scale, VDD = 5.5 V, AD5254 0 11 16 LSB
Code = zero scale, VDD = 2.7 V, AD5253 0 4 6 LSB
Code = zero scale, VDD = 2.7 V, AD5254 0 15 20 LSB

RESISTOR TERMINALS

Voltage Range4 V
Capacitance5 A, B CA, CB

Capacitance5 W CW

Common-Mode Leakage Current ICM V

R-DNL RWB, RWA = NC, VDD = 5.5 V, AD5253 –0.5 ±0.2 +0.5 LSB

, RWA = NC, VDD = 5.5 V, AD5254 –1.00 ±0.25 +1.00 LSB

WB

, RWA = NC, VDD = 2.7 V, AD5253 –0.75 ±0.30 +0.75 LSB

WB

, RWA = NC, VDD = 2.7 V, AD5254 –1.5 ±0.3 +1.5 LSB

WB

, RWA = NC, VDD = 5.5 V, AD5254 –2.0 ±0.5 +2.0 LSB

WB

, RWA = NC, VDD = 2.7 V, AD5253 –1.0 +2.5 +4.0 LSB

WB

, RWA = NC, VDD = 2.7 V, AD5254 –2 +9 +14 LSB

WB

= 25°C –30 +30 %

A

= 1 V/R, VDD = 5 V 75 130 Ω

W

= 1 V/R, VDD = 3 V 200 300 Ω

W

/ΔR

AB1

0.15 %

AB2

Code = full scale, VDD = 5.5 V, AD5253 –5 –3 0 LSB

WFSE

Code = zero scale, VDD = 5.5 V, AD5253 0 3 5 LSB

WZSE

, VB, VW V

A

f = 1 kHz, measured to GND,

VDD V

SS

85 pF

code = half scale
f = 1 kHz, measured to GND,

95 pF

code = half scale

= VB = VDD/2 0.01 1.00 μA

A

Rev. B | Page 3 of 32

AD5253/AD5254

www.BDTIC.com/ADI

Parameter Symbol Conditions Min Typ1 Max Unit

DIGITAL INPUTS AND OUTPUTS

Input Logic High VIH V
V
Input Logic Low VIL V
V
Output Logic High (SDA) VOH R
Output Logic Low (SDA) VOL R

I

WP Leakage Current

WP

A0 Leakage Current IA0 A0 = GND 3 μA

I

Input Leakage Current

(Other than WP

and A0)

Input Capacitance5 C

V

I

5 pF

I

POWER SUPPLIES

Single-Supply Power Range VDD V
Dual-Supply Power Range VDD/VSS ±2.25 ±2.75 V
Positive Supply Current IDD V
Negative Supply Current ISS

EEMEM Data Storing Mode Current I
EEMEM Data Restoring Mode

Current

6

Power Dissipation7 P

V

DD_STORE

I

DD_RESTORE

V

V

DISS

Power Supply Sensitivity PSS ΔVDD = 5 V ± 10% −0.025 +0.010 +0.025 %/%
ΔVDD = 3 V ± 10% –0.04 +0.02 +0.04 %/%

DYNAMIC CHARACTERISTICS

5, 8

Bandwidth –3 dB BW RAB = 1 kΩ 4 MHz
Total Harmonic Distortion THD VA =1 V rms, VB = 0 V, f = 1 kHz 0.05 %
VW Settling Time tS V
Resistor Noise Voltage e

N_WB

Digital Crosstalk CT

Analog Coupling CAT

1

Typical values represent average readings at 25°C and VDD = 5 V.

2

Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum and minimum resistance wiper positions. R-DNL is the

relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5254 1 kΩ version at V

= VDD/R for both VDD = 3 V and VDD = 5 V.

I

W

3

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output digital-to-analog converter. VA = VDD and VB = 0 V.

DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.

4

Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other.

5

Guaranteed by design and not subject to production test.

6

Command 0 NOP should be activated after Command 1 to minimize I

7

P

is calculated from IDD × VDD = 5 V.

DISS

8

All dynamic characteristics use VDD = 5 V.

= 5 V, VSS = 0 V 2.4 V

DD

= +2.7 V/0 V or VDD/VSS = ±2.5 V 2.1 V

DD/VSS

= 5 V, VSS = 0 V 0.8 V

DD

= +2.7 V/0 V or VDD/VSS = ±2.5 V 0.6 V

DD/VSS

= 2.2 kΩ to VDD = 5 V, VSS = 0 V 4.9 V

PULL-UP

= 2.2 kΩ to VDD = 5 V, VSS = 0 V 0.4 V

PULL-UP

= VDD

WP

= 0 V or VDD ±1 μA

IN

= 0 V 2.7 5.5 V

SS

= VDD or VIL = GND 5 15 μA

IH

= VDD or VIL = GND, VDD = 2.5 V,

V

IH

= –2.5 V

V

SS

= VDD or VIL = GND 35 mA

IH

= VDD or VIL = GND 2.5 mA

IH

= VDD = 5 V or VIL = GND 0.075 mW

IH

= VDD, VB = 0 V 0.2 μs

A

= 500 Ω, f = 1 kHz

R

WB

5 μA

–5 –15 μA

3 nV/√Hz

(thermal noise only)

= VDD, VB = 0 V, measure VW with

V

A

–80 dB
adjacent RDAC making full-scale
change

Signal input at A0 and measure the

–72 dB
output at W1, f = 1 kHz

DD

current consumption.

DD_RESTORE

= 2.7 V,

Rev. B | Page 4 of 32

AD5253/AD5254

www.BDTIC.com/ADI

10 kΩ, 50 kΩ, 100 kΩ VERSIONS

VDD = +3 V ± 10% or +5 V ± 10%, VSS = 0 V or VDD/VSS = ±2.5 V ± 10%, VA = VDD, VB = 0 V, –40°C < TA < +85°C, unless otherwise noted.

Table 2.

Parameter Symbol Conditions Min Typ1 Max Unit

DC CHARACTERISTICS—

RHEOSTAT MODE
Resolution N AD5253/AD5254 6/8 Bits
Resistor Differential Nonlinearity2 R-DNL RWB, RWA = NC, AD5253 −0.75 ±0.10 +0.75 LSB
R
Resistor Nonlinearity2 R-INL RWB, RWA = NC, AD5253 −0.75 ±0.25 +0.75 LSB
R
Nominal Resistor Tolerance ΔRAB/RAB T
Resistance Temperature

Coefficient
Wiper Resistance RW I
I
Channel-Resistance Matching ΔR
R

DC CHARACTERISTICS—

POTENTIOMETER DIVIDER MODE
Differential Nonlinearity3 DNL AD5253 −0.5 ±0.1 +0.5 LSB
AD5254 −1.0 ±0.3 +1.0 LSB
Integral Nonlinearity3 INL AD5253 −0.50 ±0.15 +0.50 LSB
AD5254 −1.5 ±0.5 +1.5 LSB
Voltage Divider

Temperature Coefficient
Full-Scale Error V
Code = full scale, AD5254 −3 −1 0 LSB
Zero-Scale Error V
Code = zero scale, AD5254 0 1.2 3.0 LSB

RESISTOR TERMINALS

Voltage Range4 V
Capacitance5 A, B CA, CB

Capacitance5 W CW

Common-Mode Leakage Current ICM V

DIGITAL INPUTS AND OUTPUTS

Input Logic High VIH V
V
Input Logic Low VIL V
V
Output Logic High (SDA) VOH R
Output Logic Low (SDA) VOL R
WP Leakage Current
A0 Leakage Current IA0 A0 = GND 3 μA
Input Leakage Current

(Other than WP

and A0)

Input Capacitance5 C

, RWA = NC, AD5254 −1.00 ±0.25 +1.00 LSB

WB

, RWA = NC, AD5254 −2.5 ±1.0 +2.5 LSB

WB

= 25°C −20 +20 %

A

(ΔR

) × 106/ΔT 650 ppm/°C

AB/RAB

= 1 V/R, VDD = 5 V 75 130 Ω

W

= 1 V/R, VDD = 3 V 200 300 Ω

W

/ΔR

AB1

R

AB2

= 10 kΩ, 50 kΩ 0.15 %

AB

= 100 kΩ 0.05 %

AB

(ΔV

) × 106/ΔT Code = half scale 15 ppm/°C

W/VW

Code = full scale, AD5253 −1.0 −0.3 0 LSB

WFSE

Code = zero scale, AD5253 0 0.3 1.0 LSB

WZSE

, VB, VW V

A

f = 1 kHz, measured to GND,

VDD V

SS

85 pF

code = half scale
f = 1 kHz, measured to GND,

95 pF

code = half scale

= VB = VDD/2 0.01 1 μA

A

= 5 V, VSS = 0 V 2.4 V

DD

= +2.7 V/0 V or VDD/VSS = ±2.5 V 2.1 V

DD/VSS

= 5 V, VSS = 0 V 0.8 V

DD

= +2.7 V/0 V or VDD/VSS = ±2.5 V 0.6 V

DD/VSS

= 2.2 kΩ to VDD = 5 V, VSS = 0 V 4.9 V

PULL-UP

= 2.2 kΩ to VDD = 5 V, VSS = 0 V 0.4 V

PULL-UP

I

WP

V

I

I

5 pF

I

= VDD

WP

= 0 V or VDD ±1 μA

IN

5 μA

Rev. B | Page 5 of 32

AD5253/AD5254

www.BDTIC.com/ADI

Parameter Symbol Conditions Min Typ1 Max Unit

POWER SUPPLIES

Single-Supply Power Range VDD V
Dual-Supply Power Range VDD/VSS ±2.25 ±2.75 V
Positive Supply Current IDD V
Negative Supply Current ISS

I

EEMEM Data Storing Mode

V

DD_STORE

Current

EEMEM Data Restoring Mode

Current

6

I

DD_RESTORE

Power Dissipation7 P

V

V

DISS

Power Supply Sensitivity PSS ΔVDD = 5 V ± 10% −0.005 +0.002 +0.005 %/%
ΔVDD = 3 V ± 10% −0.010 +0.002 +0.010 %/%

DYNAMIC CHARACTERISTICS

5, 8

–3 dB Bandwidth BW RAB = 10 kΩ/50 kΩ/100 kΩ 400/80/40 kHz
Total Harmonic Distortion THDW V
VW Settling Time tS

Resistor Noise Voltage e

N_WB

Digital Crosstalk CT

Analog Coupling CAT

1

Typical values represent average readings at 25°C and VDD = 5 V.

2

Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum and minimum resistance wiper positions. R-DNL is the

relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5254 1 kΩ version at VDD = 2.7 V,
IW = VDD/R for both VDD = 3 V and VDD = 5 V.

3

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider, similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits

of ±1 LSB maximum are guaranteed monotonic operating conditions.

4

Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other.

5

Guaranteed by design and not subject to production test.

6

Command 0 NOP should be activated after Command 1 to minimize I

7

P

is calculated from IDD × VDD = 5 V.

DISS

8

All dynamic characteristics use VDD = 5 V.

= 0 V 2.7 5.5 V

SS

= VDD or VIL = GND 5 15 μA

IH

= VDD or VIL = GND, VDD = 2.5 V,

V

IH

= −2.5 V

V

SS

= VDD or VIL = GND, TA = 0°C to 85°C 35 mA

IH

= VDD or VIL = GND, TA = 0°C to 85°C 2.5 mA

IH

= VDD = 5 V or VIL = GND 0.075 mW

IH

= 1 V rms, VB = 0 V, f = 1 kHz 0.05 %

A

= VDD, VB = 0 V,

V

A

= 10 kΩ/50 kΩ/100 kΩ

R

AB

= 10 kΩ/50 kΩ/100 kΩ, code =

R

AB

−5 −15 μA

1.5/7/14 μs

9/20/29 nV/√Hz

midscale, f = 1 kHz (thermal noise only)

= VDD, VB = 0 V, measure VW with

V

A

−80 dB

adjacent RDAC making full-scale change
Signal input at A0 and measure output

−72 dB

at W1, f = 1 kHz

current consumption.

DD_RESTORE

Rev. B | Page 6 of 32

AD5253/AD5254

www.BDTIC.com/ADI

INTERFACE TIMING CHARACTERISTICS

All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching
characteristics are measured using both V

Table 3.

Parameter1 Symbol Conditions Min Typ2 Max Unit

INTERFACE TIMING

SCL Clock Frequency f
t

Bus-Free Time Between Stop and Start t1 1.3 μs

BUF

t

Hold Time (Repeated Start) t2

HD;STA

t

Low Period of SCL Clock t3 1.3 μs

LOW

t

High Period of SCL Clock t4 0.6 μs

HIGH

t

Set-up Time for Start Condition t5 0.6 μs

SU;STA

t

Data Hold Time t6 0 0.9 μs

HD;DAT

t

Data Set-up Time t7 100 ns

SU;DAT

tF Fall Time of Both SDA and SCL Signals t8 300 ns
tR Rise Time of Both SDA and SCL Signals t9 300 ns
t

Set-up Time for Stop Condition t10 0.6 μs

SU;STO

EEMEM Data Storing Time t
EEMEM Data Restoring Time at Power-On3 t

EEMEM Data Restoring Time upon Restore

Command or Reset Operation

3

EEMEM Data Rewritable Time4 t

FLASH/EE MEMORY RELIABILITY

Endurance5 100 K cycles
Data Retention

1

See Figure 23 for location of measured values.

2

Typical values represent average readings at 25°C and VDD = 5 V.

3

During power-up, all outputs are preset to midscale before restoring the EEMEM contents. RDAC0 has the shortest EEMEM restore time, whereas RDAC3 has the longest.

4

Delay time after power-on or reset before new EEMEM data to be written.

5

Endurance is qualified to 100,000 cycles per JEDEC Std. 22 Method A117 and measured at –40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles.

6

Retention lifetime equivalent at junction temperature TJ = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates

with junction temperature.

7

When the part is not in operation, the SDA and SCL pins should be pulled high. When these pins are pulled low, the I2C interface at these pins conducts a current of

about 0.8 mA at V

6, 7

100 Years

= 5.5 V and 0.2 mA at VDD = 2.7 V.

DD

= 3 V and 5 V.

DD

400 kHz

SCL

EEMEM_STORE

EEMEM_RESTORE1

t

EEMEM_RESTORE2

EEMEM_REWRITE

After this period, the first clock pulse is

0.6 μs

generated.

26 ms

rise time dependent. Measure without

V

DD

decoupling capacitors at V

DD

and VSS.

300 μs

VDD = 5 V. 300 μs

540 μs

Rev. B | Page 7 of 32

AD5253/AD5254

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted

Table 4.

Parameter Rating

VDD to GND −0.3 V, +7 V
VSS to GND +0.3 V, −7 V
VDD to VSS 7 V
VA, VB, VW to GND VSS, VDD
Maximum Current

IWB, IWA Pulsed ±20 mA
IWB Continuous (RWB ≤ 1 kΩ, A Open)1 ±5 mA
IWA Continuous (RWA ≤ 1 kΩ, B Open)1 ±5 mA
IAB Continuous

(R

= 1 kΩ/10 kΩ/50 kΩ/100 kΩ)1

AB

Digital Inputs and Output Voltage to GND 0 V, 7 V
Operating Temperature Range −40°C to +85°C
Maximum Junction Temperature (T
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
TSSOP-20 Thermal Resistance2 θJA 143°C/W

1

Maximum terminal current is bound by the maximum applied voltage across

any two of the A, B, and W terminals at a given resistance, the maximum
current handling of the switches, and the maximum power dissipation of the
package. VDD = 5 V.

2

Package power dissipation = (T

JMAX

JMAX

− TA)/θJA.

±5 mA/±500 μA/
±100 μA/±50 μA

) 150°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. B | Page 8 of 32

AD5253/AD5254

A

www.BDTIC.com/ADI

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

W0

B0
A0

AD0

WP
W1

B1
A1

SD

V

SS

1
2

AD5253/

3

AD5254

4

TOP VIEW

(Not to Scale)

5
6
7
8
9

10

20
19
18
17
16
15
14
13
12
11

V

DD

W3
B3
A3
AD1
DGND
SCL
W2
B2
A2

03824-0-002

Figure 2. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 W0 Wiper Terminal of RDAC0. VSS ≤ VW0 ≤ VDD.
2 B0 B Terminal of RDAC0. VSS ≤ VB0 ≤ VDD.
3 A0 A Terminal of RDAC0. VSS ≤ VA0 ≤ VDD.
4 AD0 I2C Device Address 0. AD0 and AD1 allow four AD5253/AD5254 devices to be addressed.
5

WP

Write Protect, Active Low. V

≤ VDD + 0.3 V.

WP

6 W1 Wiper Terminal of RDAC1. VSS ≤ VW1 ≤ VDD.
7 B1 B Terminal of RDAC1. VSS ≤ VB1 ≤ VDD.
8 A1 A Terminal of RDAC1. VSS ≤ VA1 ≤ VDD.
9 SDA

Serial Data Input/Output Pin. Shifts in one bit at a time upon positive clock edges. MSB loaded first. Open-drain
MOSFET requires pull-up resistor.

10 VSS

Negative Supply. Connect to 0 V for single supply or –2.7 V for dual supply, where V
rather than grounded in dual supply, V

must be able to sink 35 mA for 26 ms when storing data to EEMEM.

SS

– VSS ≤ +5.5 V. If VSS is used

DD

11 A2 A Terminal of RDAC2. VSS ≤ VA2 ≤ VDD.
12 B2 B Terminal of RDAC2. VSS ≤ VB2 ≤ VDD.
13 W2 Wiper Terminal of RDAC2. VSS ≤ VW2 ≤ VDD.
14 SCL

Serial Input Register Clock Pin. Shifts in one bit at a time upon positive clock edges. V

SCL

resistor is recommended for SCL to ensure minimum power.
15 DGND Digital Ground. Connect to system analog ground at a single point.
16 AD1 I2C Device Address 1. AD0 and AD1 allow four AD5253/AD5254 devices to be addressed.
17 A3 A Terminal of RDAC3. VSS ≤ VA3 ≤ VDD.
18 B3 B Terminal of RDAC3. VSS ≤ VB3 ≤ VDD.
19 W3 Wiper Terminal of RDAC3. VSS ≤ VW3 ≤ VDD.
20 VDD

Positive Power Supply Pin. Connect +2.7 V to +5 V for single supply or ±2.7 V for dual supply, where V

must be able to source 35 mA for 26 ms when storing data to EEMEM.

V

DD

≤ (VDD + 0.3 V). Pull-up

– VSS ≤ +5.5 V.

DD

Rev. B | Page 9 of 32

AD5253/AD5254

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

1.0

0.8

0.6

0.4

0.2

0

–0.2

R-INL (LSB)

–0.4

–0.6

–0.8

–1.0

0 32 64 96 128 160 192 224 256

TA= –40°C, +25°C, +85°C, +125°C

CODE (Decimal)

Figure 3. R-INL vs. Code Figure 6. DNL vs. Code

03824-0-015

1.0

0.8

0.6

0.4

0.2

0

–0.2

DNL (LSB)

–0.4

–0.6

–0.8

–1.0

0 32 64 96 128 160 192 224 256

T

= –40°C, +25°C, +85°C, +125°C

A

CODE (Decimal)

03824-0-018

1.0

0.8

0.6

0.4

0.2

0

–0.2

R-DNL (LSB)

–0.4

–0.6

–0.8

–1.0

0 32 64 96 128 160 192 224 256

TA = –40°C, +25°C, +85°C, +125°C

CODE (Decimal)

Figure 4. R-DNL vs. Code Figure 7. Supply Current vs. Temperature

1.0

0.8

0.6

0.4

0.2

0

–0.2

INL (LSB)

–0.4

–0.6

–0.8

–1.0

0 32 64 96 128 160 192 224 256

T

= –40°C, +25°C, +85°C, +125°C

A

CODE (Decimal)

Figure 5. INL vs. Code Figure 8. Supply Current vs. Digital Input Voltage, TA = 25°C

03824-0-016

03824-0-017

10

8

6

4

2

0

(μA)

DD

I

–2

–4

–6

–8

–10

–40 –20 0 20 40 60 80 100 120

10

1

0.1

(mA)

DD

I

0.01

0.001

0.0001
0123456

IDD @ VDD= +5.5V

IDD @ VDD= +2.7V

ISS @ VDD= +2.7V, VSS= –2.7V

TEMPERATURE (°C)

VDD= 5.5V

VDD= 2.7V

DIGITAL INPUT VOLTAGE (V)

03824-0-019

03824-0-020

Rev. B | Page 10 of 32