Analog Devices AD5251 2 Datasheet

Dual 64-and 256-Position I2C Nonvolatile

FEATURES

AD5251: Dual 64-position resolution AD5252: Dual 256-position resolution 1 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Nonvolatile memory Power-on refreshed with EEMEM settings in 300 µs typ EEMEM rewrite time = 540 µs typ

Resistance tolerance stored in nonvolatile memory 12 extra bytes in EEMEM for user-defined information

2

C compatible serial interface

I Direct read/write access of RDAC Predefined linear increment/decrement commands Predefined ±6 dB step change commands Synchronous or aysynchronous dual channel update Wiper setting read back 4 MHz bandwidth—1 kΩ version Single supply 2.7 V to 5.5 V Dual supply ±2.25 V to ±2.75 V 2 slave address decoding bits allow operation of 4 devices 100-year typical data retention T Operating temperature –40°C to +85°C

APPLICATIONS

Mechanical potentiometer replacement General purpose DAC replacement LCD panel V

COM

GENERAL DESCRIPTION

The AD5251/AD5252 are dual-channel, I2C, nonvolatile memory, digitally controlled potentiometers with 64/256 positions, respectively. These devices perform the same electronic adjustment functions as mechanical potentiometers, trimmers, and variable resistors. The parts’ versatile programmability allows multiple modes of operation, including read/write access in the RDAC and EEMEM registers, increment/decrement of resistance, resistance changes in ±6 dB scales, wiper setting readback, and extra EEMEM for storing user-defined information such as memory data for other components, look-up table, or system identification information.

The AD5251/AD5252 allow the host I any of the 64- or 256-step wiper settings in the RDAC registers and store them in the EEMEM. Once the settings are stored,

1

stores wiper setting w/write protection

2

and EEMEM registers

= 55°C

A

adjustment

2

C controllers to write

Memory Digital Potentiometers

AD5251/AD5252

White LED brightness adjustment RF base station power amp bias control Programmable gain and offset control Programmable voltage-to-current conversion Programmable power supply Sensor calibrations

FUNDAMENTAL BLOCK DIAGRAM

V

DD

V

SS

DGND

WP

SCL SDA

AD0 AD1

I2C

SERIAL

INTERFACE

POWER-

ON RESET

1

The terms nonvolatile memory and EEMEM are used interchangeably.

2

The terms digital potentiometer and RDAC are used interchangeably.

they are restored automatically to the RDAC registers at system power-on; the settings can also be restored dynamically.

The AD5251/AD5252 provide additional increment, decrement, +6 dB step change, and –6 dB step change in synchronous or asynchronous channel update modes. The increment and decrement functions allow stepwise linear adjustments, while ±6 dB step changes are equivalent to doubling or halving the RDAC wiper setting. These functions are useful for steep-slope nonlinear adjustments such as white LED brightness and audio volume control. The parts have a patented resistance tolerance storing function which enable the user to access the EEMEM and obtain the absolute end-to-end resistance values of the RDACs for precision applications.

The AD5251/AD5252 are available in TSSOP-14 packages in 1 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ options and all parts can operate over the –40°C to +85°C extended industrial temperature range.

RDAC EEMEM

EEMEM

POWER-ON

REFRESH

DATA

CONTROL

RAB TOL

COMMAND

DECODE LOGIC

ADDRESS

DECODE LOGIC

CONTROL LOGIC

Figure 1.

RDAC1 REGIS-

TER

RDAC3 REGIS-

TER

RDAC1

RDAC3

AD5251/

AD5252

A1 W1 B1

A3 W3 B3

03823-0-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

www.analog.com

AD5251/AD5252

TABLE OF CONTENTS

Electrical Characteristics ................................................................. 3

Interface Timing Characteristics................................................ 7

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Description .............................. 9

2

I

C Interface Timing Diagram.................................................... 9

2

I

C Interface General Description................................................ 10

2

I

C Interface Detail Description ................................................... 11

RDAC/EEMEM Write ............................................................... 11

2

I

C Compatible 2-Wire Serial Bus................................................ 15

Typical Performance Characteristics ........................................... 16

Operational Overview.................................................................... 20

Linear Increment and Decrement Commands ...................... 20

±6 dB Adjustments (Doubling/Halving WIPER Setting)..... 20

Digital Input/Output Configuration........................................ 21

Multiple Devices on One Bus ................................................... 21

Terminal Voltage Operation Range ......................................... 21

Power-Up and Power-Down Sequences .................................. 21

Layout and Power Supply Biasing ............................................ 22

Digital Potentiometer Operation ............................................. 22

Programmable Rheostat Operation......................................... 22

Programmable Potentiometer Operation ............................... 23

Applications..................................................................................... 24

LCD Panel V

Adjustment ..................................................... 24

com

Current-Sensing Amplifier ....................................................... 24

Adjustable High Power LED Driver ........................................ 24

Outline Dimensions ....................................................................... 25

Ordering Guide .......................................................................... 25

REVISION HISTORY

6/04—Revision 0: Initial Version

Rev.0 | Page 2 of 28

AD5251/AD5252

ELECTRICAL CHARACTERISTICS

1 kΩ Version. VDD = 3 V ± 10% or 5 V ± 10%; VSS = 0 V or VDD/VSS = ± 2.5 V ± 10%; VA = +VDD, VB = 0 V, –40°C < TA < +85°C, unless otherwise noted. Table 1.

Parameter Symbol Conditions Min Typ1Max Unit

DC CHARACTERISTICS RHEOSTAT MODE

Resolution N AD5251/AD5252 6/8 Bits Resistor Differential

Nonlinearity

2

R R R Resistor Nonlinearity2 R-INL RWB, RWA = NC, VDD = 5.5 V, AD5251 –0.5 ±0.2 +0.5 LSB R R R Nominal Resistor Tolerance ∆RAB/R Resistance Temperature

Coefficent Wiper Resistance R I Channel Resistance Matching ∆R

DC CHARACTERISTIC POTENTIOMETER DIVIDER MODE

Differential Nonlinearity

3

AD5252 –1 ±0.25 +1 LSB Integral Nonlinearity3 INL AD5251 –0.5 ±0.2 +0.5 LSB AD5252 –2 ±0.5 +2 LSB Voltage Divider Temperature

Coefficent Full-Scale Error V Code = full scale, VDD = 5.5 V, AD5252 –16 –11 0 LSB Code = full scale, VDD = 2.7 V, AD5251

Code = full scale, VDD = 2.7 V, AD5252 –23 –16 0 LSB Zero-Scale Error V Code = zero scale, VDD = 5.5 V, AD5252 0 11 16 LSB Code = zero scale, VDD = 2.7 V, AD5251 0 4 6 LSB Code = zero scale, VDD = 2.7 V, AD5252 0 15 20 LSB

RESISTOR TERMINALS

Voltage Range

4

Capacitance5 Ax, Bx CA, C

Capacitance5 Wx C

Common-Mode Leakage

Current

DIGITAL INPUTS and OUTPUTS

Input Logic High V V Input Logic Low V Output Logic High (SDA) V Output Logic Low (SDA) V

R-DNL RWB, RWA = NC, VDD = 5.5 V, AD5251 –0.5 ±0.2 +0.5 LSB

, RWA = NC, VDD = 5.5 V, AD5252 –1 ±0.25 +1 LSB

WB

, RWA = NC, VDD = 2.7 V, AD5251 –0.75 ±0.3 +0.75 LSB

WB

, RWA = NC, VDD = 2.7 V, AD5252 –1.5 ±0.3 +1.5 LSB

WB

, RWA = NC, VDD = 5.5 V, AD5252 –2 ±0.5 +2 LSB

WB

, RWA = NC, VDD = 2.7 V, AD5251 –1 +2.5 +4 LSB

WB

, RWA = NC, VDD = 2.7 V, AD5252 –2 +9 +14 LSB

WB

TA = 25°C –30 +30 %

IW = 1 V/R, VDD = 5 V 75 130 Ω

= 1 V/R, VDD = 3 V 200 300 Ω

W

0.15 %

(∆R

W

AB

) × 106/∆T 650 ppm/°C

AB/RAB

/∆R

AB1

AB3

DNL AD5251 –0.5 ±0.1 +0.5 LSB

(∆V

VA, VB, V

) × 106/∆T Code = half scale 25 ppm/°C

W/VW

WFSE

WZSE

W

B

Code = full scale, VDD = 5.5 V, AD5251 –5 –3 0 LSB

−6

–4 0 LSB

Code = zero scale, VDD = 5.5 V, AD5251 0 3 5 LSB

V f = 1 kHz, measured to GND,

SS

85 pF

VDDV

Code = half scale

W

f = 1 kHz, measured to GND,

95 pF

Code = half scale

I

CM

IH

IL

OH

OL

VA = VB = VDD/2 0.01 1 µA

VDD = 5 V, VSS = 0 V 2.4 V

= 2.7 V/0 V or VDD/VSS = ± 2.5 V 2.1 V

DD/VSS

VDD = 5V, VSS = 0 V 0.8 V R

= 2.2 kΩ to VDD = 5 V, VSS = 0 V 4.9 V

PULL-UP

R

= 2.2 kΩ to VDD =5 V, VSS = 0 V 0.4 V

PULL-UP

Rev. 0 | Page 3 of 28

AD5251/AD5252

Parameter Symbol Conditions Min Typ1Max Unit

I

Leakage Current

A0 Leakage Current I Input Leakage Current (Other

WP

than

and A0)

Input Capacitance5 C

WP

A0

I

WP

= V

DD

A0 = GND 3 µA VIN = 0 V or V

DD

5 pF

POWER SUPPLIES

Single-Supply Power Range V

DD

Dual-Supply Power Range VDD/V Positive Supply Current I Negative Supply Current I

EEMEM Data Storing Mode

DD

SS

I

DD_STORE

SS

VSS = 0 V 2.7 5.5 V ±2.25 ±2.75 V VIH = VDD or VIL = GND 5 15 µA VIH = VDD or VIL = GND, VDD = +2.5 V,

= –2.5 V

V

SS

VIH = VDD or VIL = GND 35 mA

Current EEMEM Data Restoring Mode

6

Current Power Dissipation

7

I

DD_RESTORE

P

DISS

VIH = VDD or VIL = GND 2.5 mA

VIH = VDD = 5 V or VIL = GND 0.075 mW Power Supply Sensitivity PSS ∆VDD = 5 V ± 10% −0.025 0.01 0.025 %/% ∆VDD = 3 V ± 10% –0.04 0.02 0.04 %/%

DYNAMIC CHARACTERISTICS

5, 8

Bandwidth –3 dB BW RAB = 1 kΩ 4 MHz Total Harmonic Distortion THD VA = 1 V rms, VB = 0 V, f = 1 kHz 0.05 % VW Settling Time t Resistor Noise Voltage e

Digital Crosstalk C

S

N_WB

T

VA = VDD, VB = 0 V 0.2 µs

RWB = 500 Ω, f = 1 kHz (thermal noise only) 3

VA = VDD, VB = 0 V, measure VW with

adjacent RDAC making full-scale change Analog Coupling C

AT

Signal input at A1 and measure the

output at W3, f = 1 kHz

1

Typical represents the average reading at 25°C and VDD = 5 V.

2

Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5252 1 kΩ version at V

3

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL

specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.

4

Resistor Terminals A, B, and W have no limitations on polarity with respect to each other.

5

Guaranteed by design and not subject to production test.

6

cmd 0 NOP should be activated after cmd 1 to minimize I

7

P

DISS

8

All dynamic characteristics use VDD = 5 V.

= 2.7 V, IW = VDD/R for both VDD = 3 V or VDD = 5 V.

DD

is calculated from IDD × VDD = 5 V.

current consumption.

DD_READ

5 µA

±1 µA

–5 –15 µA

Hz

nV/√

–80 dB

–72 dB

Rev. 0 | Page 4 of 28

AD5251/AD5252

10 kΩ, 50 kΩ, 100 kΩ Versions. VDD = +3 V ± 10% or + 5 V ± 10%. VSS = 0 V or VDD/VSS = ± 2.5 V ± 10%. VA = +VDD, VB = 0 V, –40°C < T Table 2.

Parameter Symbol Conditions Min Ty p DC CHARACTERISTICS RHEOSTAT MODE

Resolution N AD5251/AD5252 6/8 Bits Resistor Differential NL R Resistor Nonlinearity2 R-INL RWB, RWA = NC, AD5251 −0.75 ±0.25 +0.75 LSB R Nominal Resistor Tolerance ∆RAB/R Resistance Temperature

Coefficent Wiper Resistance R I

Channel Resistance Matching ∆R R DC CHARACTERISTICS POTENTIOMETER DIVIDER

MODE

Differential Nonlinearity

AD5252 −1 ±0.3 +1 LSB

Integral Nonlinearity3 INL AD5251 −0.5 ±0.15 +0.5 LSB

AD5252 −1.5 ±0.5 +1.5 LSB

Voltage Divider

Temperature Coefficent (∆VW/VW) × 106/∆T Code = half scale 15 ppm/°C

Full-Scale Error V

Code = full scale, AD5252 −3 −1 0 LSB

Zero-Scale Error V Code = zero scale, AD5252 0 1.2 3 LSB RESISTOR TERMINALS

Voltage Range

Capacitance5 Ax, Bx CA, C

Capacitance5 Wx C

Common-Mode Leakage

Current DIGITAL INPUTS and OUTPUTS

Input Logic High V

V

Input Logic Low V

V

Output Logic High (SDA) V

Output Logic Low (SDA) V

Leakage Current

A0 Leakage Current I

Input Leakage Current

(Other than WP and A0)

Input Capacitance5 C POWER SUPPLIES

Single-Supply Power Range V

< +85°C, unless otherwise noted.

A

2

R-DNL RWB, RWA = NC, AD5251 −0.75 ±0.1 +0.75 LSB

AB

(∆R

AB/RAB

W

/∆R

AB1

3

4

DNL AD5251 −0.5 ±0.1 +0.5 LSB

WFSE

WZSE

VA, VB, V

W

B

W

I

CM

IH

IL

OH

OL

I

WP

A0

I

DD

1

, RWA = NC, AD5252 −1 ±0.25 +1 LSB

WB

, RWA = NC, AD5252 −2.5 ±1 +2.5 LSB

WB

Max Unit

TA = 25°C −20 +20 %

) × 106/∆T 650 ppm/°C

IW = 1 V/R, VDD = 5 V 75 130 Ω

= 1 V/R, VDD = 3 V 200 300 Ω

W

AB2

RAB = 10 kΩ, 50 kΩ 0.15 %

= 100 kΩ 0.05 %

AB

Code = full scale, AD5251 −1 −0.3 0 LSB

Code = zero scale, AD5251 0 0.3 1 LSB

V f = 1 kHz, measured to GND,

SS

85 pF

VDDV

Code = half scale f = 1 kHz, measured to GND,

95 pF

Code = half scale VA = VB = VDD/2 0.01 1 µA

VDD =5 V, VSS = 0 V 2.4 V

= +2.7 V/0 V or VDD/VSS = ±2.5 V 2.1 V

DD/VSS

VDD = 5 V, VSS = 0 V 0.8 V

= +2.7 V/0 V or VDD/VSS =±2.5 V 0.6 V

DD/VSS

R

= 2.2 kΩ to VDD = 5 V, VSS = 0 V 4.9 V

PULL-UP

R

= 2.2 kΩ to VDD = 5 V, VSS = 0 V 0.4 V

PULL-UP

WP

= V

DD

5 µA

A0 = GND 3 µA

VIN = 0 V or V

DD

±1 µA

5 pF

VSS = 0 V 2.7 5.5 V

Rev. 0 | Page 5 of 28

AD5251/AD5252

Parameter Symbol Conditions Min Ty p

Dual-Supply Power Range VDD/V Positive Supply Current I Negative Supply Current I

DD

SS

±2.25 ±2.75 V VIH = VDD or VIL = GND 5 15 µA VIH = VDD or VIL = GND, VDD = +2.5 V, VSS

−5 −15 µA

1

Max Unit

= -2.5 V

EEMEM Data Storing Mode

I

DD_STORE

VIH = VDD or VIL = GND, TA = 0°C to 85°C 35 mA

Current EEMEM Data Restoring Mode

Current

6

Power Dissipation7 P

I

DD_RESTORE

DISS

VIH = VDD or VIL = GND, TA = 0°C to 85°C 2.5 mA

VIH = VDD = 5 V or VIL = GND 0.075 mW

Power Supply Sensitivity PSS ∆VDD = 5 V ±10% −0.005 +0.002 +0.005 %/% ∆VDD = 3 V ±10% −0.01 +0.002 +0.01 %/% DYNAMIC CHARACTERISTICS

5, 8

–3 dB Bandwidth BW RAB = 10 kΩ/50 kΩ/100 kΩ 400/80/40 kHz

Total Harmonic Distortion THD

VW Settling Time t

S

W

VA = 1 Vrms, VB = 0 V, f = 1 kHz 0.05 % VA = VDD, VB = 0 V, R

= 10 kΩ/50

AB

1.5/7/14 µs

kΩ/100 kΩ

Resistor Noise Voltage e

N_WB

10 kΩ/50 kΩ/100 kΩ, code = midscale,

9/20/29

nV/√

f = 1 kHz (thermal noise only)

Digital Crosstalk C

T

VA = VDD, VB = 0 V, Measure VW with

-80 dB adjacent RDAC making full scale change

Analog Coupling C

AT

Signal input at A1 and measure output

-72 dB at W3, f = 1kHz

1

Typical represents the average reading at 25°C and VDD = 5 V.

2

Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5252 1 kΩ version at V

3

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL

specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.

4

Resistor Terminals A, B, and W have no limitations on polarity with respect to each other.

5

Guaranteed by design and not subject to production test.

6

cmd 0 NOP should be activated after cmd 1 to minimize I

7

P

DISS

8

All dynamic characteristics use VDD = 5 V.

= 2.7 V, IW = VDD/R for both VDD = 3 V or VDD = 5 V.

DD

is calculated from IDD × VDD = 5 V.

current consumption.

DD_READ

Hz

Rev. 0 | Page 6 of 28

AD5251/AD5252

INTERFACE TIMING CHARACTERISTICS

Guaranteed by design, not subject to production test. See Figure 3 for location of measured values. All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V), and timed from a voltage level of 1.5 V. Switching characteristics are measured using both V Table 3. Interface Timing and EEMEM Reliability Characteristics (All Parts).

Parameter Symbol Conditions Min Typ Max Unit

INTERFACE TIMING

SCL Clock Frequency f tBUF Bus Free Time between STOP and

START t

Hold Time (Repeated START) t

HD;STA

t

Low Period of SCL Clock t

LOW

t

High Period of SCL Clock t

HIGH

t

Setup Time For START Condition t

SU;STA

t

HD;DAT

t

Data Setup Time t

SU;DAT

tF Fall Time of Both SDA and SCL Signals t tR Rise Time of Both SDA and SCL Signals t t

Setup Time for STOP Condition t

SU;STO

EEMEM Data Storing Time t EEMEM Data Restoring Time at

Power-On

EEMEM Data Restoring Time Upon Restore Command or RESET Operation

EEMEM Rewritable Time (delay time after Power On or RESET before EEMEM can be written)

FLASH/EE MEMORY RELIABILITY

Endurance Data Retention

1

During power-up, all outputs preset to midscale before restoring to the final EEMEM contents. RDAC0 has the shortest, whereas RDAC3 has the longest EEMEM data

restoring time.

2

Retention lifetime equivalent at junction temperature TJ = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates

with junction temperature.

3

When the part is not in operation, the SDA and SCL pins should be pulled to high. When these pins are pulled to low, the I2C interface at these pins conducts current of

about 0.8 mA at V

= 3 V and 5 V.

DD

Data Hold Time t

1

2

3

= 5.5 V and 0.2 mA at VDD = 2.7 V.

DD

SCL

t

1

2

400 kHz

1.3 µs

After this period, the first clock pulse

0.6

µs

is generated

3

4

5

6

7

8

9

10

EEMEM_STORE

t

EEMEM_RESTORE1

t

EEMEM_RESTORE2

t

EEMEM_REWRITE

1.3

0.6

0.6 0 100

0.6

0.9 µs

300 ns 300 ns µs

26 ms VDD rise time dependent. Measure

without decoupling capacitors at V

.

and V

SS

300 µs

DD

VDD = 5 V 300 µs

540 µs

µs µs µs

ns

100 kCycles 100 Years

Rev. 0 | Page 7 of 28

AD5251/AD5252

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted . Table 4.

Parameter Rating

VDD to GND −0.3 V, +7 V VSS to GND +0.3 V, −7 V VDD to V

SS

VA, VB, VW to GND VSS, V

7 V

DD

Maximum Current IWB, IWA Pulsed ±20 mA IWB Continuous (RWB ≤ 1 kΩ, A Open)

1

±5 mA IWA Continuous (RWA ≤ 1 kΩ, B Open)1 ±5 mA IAB Continuous

= 1 kΩ/10 kΩ/50 kΩ/100 kΩ)1

(R

AB

Digital Inputs and Output Voltage

±5 mA/±500 µA/

±100 µA/±50 µA

0 V, 7 V to GND

Operating Temperature Range −40°C to +85°C Maximum Junction Temperature

)

(T

J MAX

150°C

Storage Temperature −65°C to +150°C Lead Temperature (Soldering,10 sec) 300°C Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C TSSOP-14 Thermal Resistance2 θ

JA

136°C/W

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

1

Maximum terminal current is bounded by the maximum applied voltage

across any two of the A, B, and W terminals at a given resistance, the maximum current handling of the switches, and the maximum power dissipation of the package. V

2

Package power dissipation = (TJMAX − TA)/θJA.

DD

= 5 V.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev.0 | Page 8 of 28

AD5251/AD5252

A

PIN CONFIGURATION AND FUNCTION DESCRIPTION

V

AD0

WP W1

SDA

DD

B1 A1

1

2

AD5251/

3

AD5252

4

TOP VIEW

(Not to Scale)

5

6

7

14

W3

13

B3

12

A3

11

AD1

10

DGND

9

SCL

8

V

SS

03823-0-002

Figure 2. AD5251/AD5252 in TSSOP-14

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 V

DD

Positive Power Supply Pin. Connect +2.7 V to +5 V for single supply or ±2.7 V for dual supply, where V

– VSS ≤ 5.5 V. VDD must be able to source 35 mA for 26 ms when storing data to

DD

EEMEM. 2 AD0 I2C Device Address 0. AD0 and AD1 allow four AD5251/AD5252s to be addressed. 3

WP

4 W1 Wiper Terminal of RDAC1. VSS ≤ VW1 ≤ VDD.

Write Protect, Active Low. VWP ≤ VDD + 0.3 V.

1

5 B1 B Terminal of RDAC1. VSS ≤ VB1 ≤ VDD.1 6 A1 A Terminal of RDAC1. VSS ≤ VA1 ≤ VDD.1 7 SDA

Serial Data Input/Output Pin. Shifts in one bit at a time on positive clock edges. MSB loaded

first. Open-drain MOSFET requires pull-up resistor. 8 V

SS

Negative Supply. Connect to 0 V for single supply or –2.7 V for dual supply, where VDD – VSS ≤

+5.5 V. If V

is used, other than grounded, in dual supply, VSS must be able to sink 35 mA for

SS

26 ms when storing data to EEMEM. 9 SCL

Serial Input Register Clock Pin. Shifts in one bit at a time on positive clock edges. V

+ 0.3 V). Pull-up resistor is recommended for SCL to ensure minimum power.

(V

DD

10 DGND Digital Ground. Connect to system analog ground at a single point. 11 AD1 I2C Device Address 1. AD0 and AD1 allow four AD5251/AD5252s to be addressed. 12 A3 A Terminal of RDAC3. VSS ≤ VA3 ≤ VDD.1 13 B3 B Terminal of RDAC3. VSS ≤ VB3 ≤ VDD.1 14 W3 W Terminal of RDAC3. VSS ≤ VW3 ≤ VDD.1

1

For quad-channel device software compatibility, the dual potentiometers in the parts are designated as RDAC1 and RDAC3.

SCL

≤

I2C INTERFACE TIMING DIAGRAM

t

SCL

SD

t

8

t

3

2

t

9

t

8

t

1

PS P

Figure 3. I

t

9

t

4

2

C Timing Diagram

t

5

Rev. 0 | Page 9 of 28

6

t

7

t

10

03823-0-003

Analog Devices AD5251 2 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNDAMENTAL BLOCK DIAGRAM

ELECTRICAL CHARACTERISTICS

INTERFACE TIMING CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTION

I2C INTERFACE TIMING DIAGRAM