ANALOG DEVICES AD5246 Service Manual

128-Position I2C-Compatible

SDA

www.BDTIC.com/ADI

FEATURES

128-position
End-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Ultracompact SC70-6 (2 mm × 2.1 mm) package

2

C® compatible interface

I
Full read/write of wiper register
Power-on preset to midscale
Single supply 2.7 V to 5.5 V
Low temperature coefficient 45 ppm/°C
Low power, I
Wide operating temperature –40°C to +125°C
Evaluation board available
Available in lead-free (Pb-free) package

APPLICATIONS

Mechanical potentiometer replacement in new designs
Transducer adjustment of pressure, temperature, position,

chemical, and optical sensors
RF amplifier biasing
Automotive electronics adjustment
Gain control and offset adjustment

GENERAL OVERVIEW

The AD5246 provides a compact 2 mm × 2.1 mm packaged
solution for 128-position adjustment applications. This device
performs the same electronic adjustment function as a variable
resistor. Available in four different end-to-end resistance values
(5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ), these low temperature coefficient
devices are ideal for high accuracy and stability variable
resistance adjustments.

The wiper settings are controllable through the I
digital interface, which can also be used to read back the present
wiper register control word. The resistance between the wiper
and either end point of the fixed resistor varies linearly with
respect to the digital code transferred into the RDAC

= 3 μA typical

DD

2

C compatible

1

latch.

Digital Resistor

FUNCTIONAL BLOCK DIAGRAM

V

DD

SCL

I2C INTERFACE

WIPER

REGISTER

GND

Figure 1.

A

AD5246

W

B

03875-001

Operating from a 2.7 V to 5.5 V power supply and consuming

lows for usage in portable battery-operated applications.

3 µA al

1

The terms digital potentiometer, VR, and RDAC are used interchangeably

in this document.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

AD5246

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TABLE OF CONTENTS

Specifications..................................................................................... 3

Electrical Characteristics—5 kΩ Version.................................. 3

Electrical Characteristics—10 kΩ, 50 kΩ, 100 kΩ Versions .. 4

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings............................................................ 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Test Ci r c ui t s .....................................................................................11

2

I

C Interface..................................................................................... 12

Operation......................................................................................... 13

Programming the Variable Resistor......................................... 13

REVISION HISTORY

7/05—Rev. 0 to Rev. A

Changes to Table 1 ............................................................................3

Changes to Table 2 ............................................................................4

Changes to Absolute Maximum Ratings .......................................6

Moved Pin Configuration and Function Descriptions ................7

Deleted Table 7 ................................................................................12

Changes to Operation Section .......................................................13

Deleted Figure 31.............................................................................14

Changes to Figure 30 and Figure 32 .............................................14

2

I

C Compatible 2-Wire Serial Bus ........................................... 13

Level Shifting for Bidirectional Interface................................ 14

ESD Protection ........................................................................... 14

Terminal Voltage Operating Range ......................................... 14

Maximum Operating Current .................................................. 14

Power-Up Sequence ................................................................... 14

Layout and Power Supply Bypassing ....................................... 15

Constant Bias to Retain Resistance Setting............................. 15

Evaluation Board ........................................................................ 15

Outline Dimensions ....................................................................... 16

Ordering Guide .......................................................................... 16

9/03—Revision 0: Initial Version

Rev. A | Page 2 of 16

AD5246

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SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 KΩ VERSION

VDD = 5 V ± 10% or 3 V ± 10%; VA = +VDD; –40°C < TA < +125°C, unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ1Max Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resistor Differential Nonlinearity
Resistor Integral Nonlinearity
Nominal Resistor Tolerance
Resistance Temperature Coefficient (∆RAB/RAB)/∆T Wiper = no connect 45 ppm/°C
R

WB

Code = 0x00, VDD = 2.7 V 150 400 Ω

RESISTOR TERMINALS

Voltage Range

4

Capacitance5 B C
Capacitance5 W C
Common-Mode Leakage I

DIGITAL INPUTS AND OUTPUTS

Input Logic High V
Input Logic Low V
Input Logic High V
Input Logic Low V
Input Current I
Input Capacitance

5

POWER SUPPLIES

Power Supply Range V
Supply Current I
Power Dissipation

6

Power Supply Sensitivity PSSR VDD = +5 V ± 10%, code = midscale ±0.01 ±0.02 %/%

DYNAMIC CHARACTERISTICS

Bandwidth –3 dB BW_5K RAB = 5 kΩ, code = 0x40 1.2 MHz
Total Harmonic Distortion THD
VW Settling Time t
Resistor Noise Voltage Density e

1

Typical specifications represent average readings at 25°C and VDD = 5 V.

2

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

3

Code = 0x7F.

4

Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other.

5

Guaranteed by design; not subject to production test.

6

P

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

7

VDD = 5 V.

5, 7

2

2

3

R-DNL R
R-INL R
∆R

AB

R

WB

V

B, W

B

W

CM

IH

IL

IH

IL

IL

C

IL

DD RANGE

DD

P

DISS

WB

WB

–1.5 ±0.1 +1.5 LSB
–4 ±0.75 +4 LSB

TA = 25°C –30 +30 %

Code = 0x00, VDD = 5 V 75 150 Ω

GND V

V

DD

f = 1 MHz, measured to GND, code = 0x40 45 pF
f = 1 MHz, measured to GND, code = 0x40 60 pF
1 nA

VDD = 5 V 2.4 V
VDD = 5 V 0.8 V
VDD = 3 V 2.1 V
VDD = 3 V 0.6 V
VIN = 0 V or 5 V ±1 μA
5 pF

2.7 5.5 V
VIH = 5 V or VIL = 0 V 3 8 μA
VIH = 5 V or VIL = 0 V, VDD = 5 V 40 μW

W

S

N_WB

VA = 1 V rms, VB = 0 V, f = 1 kHz 0.05 %
VA = 5 V, ±1 LSB error band 1 μs
RWB = 2.5 kΩ, RS = 0 Ω 6 nV/√Hz

Rev. A | Page 3 of 16

AD5246

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ELECTRICAL CHARACTERISTICS—10 KΩ, 50 KΩ, 100 KΩ VERSIONS

VDD = 5 V ± 10% or 3 V ± 10%; VA = VDD; –40°C < TA < +125°C, unless otherwise noted.

Table 2.

Parameter Symbol Conditions Min Typ

DC CHARACTERISTICS, RHEOSTAT MODE

Resistor Differential Nonlinearity
Resistor Integral Nonlinearity
Nominal Resistor Tolerance

2

2

3

R-DNL RWB, VA = no connect –1 ±0.1 +1 LSB
R-INL RWB, VA = no connect –2 ±0.25 +2 LSB
∆R

AB

TA = 25°C –20 +20 %
Resistance Temperature Coefficient (∆RAB/RAB)/∆T Wiper = no connect 45 ppm/°C
R

WB

R

WB

Code=0x00, VDD = 5 V 75 150 Ω
Code=0x00, VDD = 2.7 V 150 400 Ω

RESISTOR TERMINALS

Voltage Range
Capacitance5 B C
Capacitance5 W C
Common-Mode Leakage I

4

V

B, W

B

W

CM

GND V

f = 1 MHz, measured to GND, code = 0x40 45 pF

f = 1 MHz, measured to GND, code = 0x40 60 pF

1 nA

DIGITAL INPUTS AND OUTPUTS

Input Logic High V
Input Logic Low V
Input Logic High V
Input Logic Low V
Input Current I
Input Capacitance

5

IH

IL

IH

IL

IL

C

IL

VDD = 5 V 2.4 V

VDD = 5 V 0.8 V

VDD = 3 V 2.1 V

VDD = 3 V 0.6 V

VIN = 0 V or 5 V ±1 μA

5 pF

POWER SUPPLIES

Power Supply Range V
Supply Current I
Power Dissipation

6

DD RANGE

DD

P

DISS

2.7 5.5 V

VIH = 5 V or VIL = 0 V 3 8 μA

VIH = 5 V or VIL = 0 V, VDD = 5 V 40 μW
Power Supply Sensitivity PSSR VDD = +5 V ± 10%, code = midscale ±0.01 ±0.02 %/%

DYNAMIC CHARACTERISTICS

5, 7

Bandwidth –3 dB BW RAB = 10 kΩ/50 kΩ/100 kΩ, code = 0x40 600/100/40 kHz
Total Harmonic Distortion THD
VW Settling Time (10 kΩ/50 kΩ/100 kΩ) t
Resistor Noise Voltage Density e

1

Typical specifications represent average readings at 25°C and VDD = 5 V.

2

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

3

Code = 0x7F.

4

Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other.

5

Guaranteed by design; not subject to production test.

6

P

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

7

All dynamic characteristics use VDD = 5 V.

W

S

N_WB

VA = 1 V rms, f = 1 kHz, RAB = 10 kΩ 0.05 %

VA = 5 V ±1 LSB error band 2 μs

RWB = 5 kΩ, RS = 0 9 nV/√Hz

1

Max Unit

V

DD

Rev. A | Page 4 of 16

AD5246

www.BDTIC.com/ADI

TIMING CHARACTERISTICS

VDD = 5 V ± 10% or 3 V ± 10%; VA = VDD; –40°C < TA < +125°C, unless otherwise noted.

Table 3.

Parameter Symbol Conditions Min Typ1Max Unit

I2C INTERFACE TIMING CHARACTERISTICS

SCL Clock Frequency f
t

Bus Free Time Between STOP and START t

BUF

t

Hold Time (Repeated START) t

HD;STA

t

Low Period of SCL Clock t

LOW

t

High Period of SCL Clock t

HIGH

t

Setup Time for Repeated START Condition t

SU;STA

t

Data Hold Time t

HD;DAT

t

Data Setup Time t

SU;DAT

tF Fall Time of Both SDA and SCL Signals t
tR Rise Time of Both SDA and SCL Signals t
t

Setup Time for STOP Condition t

SU;STO

1

Typical specifications represent average readings at 25°C and VDD = 5 V.

2

Guaranteed by design; not subject to production test.

3

See timing diagrams (Figure 26, Figure 27, and Figure 28) for locations of measured values.

4

Specifications apply to all parts.

2, , 3 4

SCL

1

2

400 kHz

1.3 μs
After this period, the first clock pulse is

generated 0.6 μs

3

4

5

6

7

8

9

10

1.3 μs

0.6 50 μs

0.6 μs

0.9 μs
100 ns
300 ns
300 ns

0.6 μs

Rev. A | Page 5 of 16