ANALOG DEVICES AD5246 Service Manual

128-Position I2C-Compatible

SDA

www.BDTIC.com/ADI

FEATURES

128-position
End-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Ultracompact SC70-6 (2 mm × 2.1 mm) package

2

C® compatible interface

I
Full read/write of wiper register
Power-on preset to midscale
Single supply 2.7 V to 5.5 V
Low temperature coefficient 45 ppm/°C
Low power, I
Wide operating temperature –40°C to +125°C
Evaluation board available
Available in lead-free (Pb-free) package

APPLICATIONS

Mechanical potentiometer replacement in new designs
Transducer adjustment of pressure, temperature, position,

chemical, and optical sensors
RF amplifier biasing
Automotive electronics adjustment
Gain control and offset adjustment

GENERAL OVERVIEW

The AD5246 provides a compact 2 mm × 2.1 mm packaged
solution for 128-position adjustment applications. This device
performs the same electronic adjustment function as a variable
resistor. Available in four different end-to-end resistance values
(5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ), these low temperature coefficient
devices are ideal for high accuracy and stability variable
resistance adjustments.

The wiper settings are controllable through the I
digital interface, which can also be used to read back the present
wiper register control word. The resistance between the wiper
and either end point of the fixed resistor varies linearly with
respect to the digital code transferred into the RDAC

= 3 μA typical

DD

2

C compatible

1

latch.

Digital Resistor

FUNCTIONAL BLOCK DIAGRAM

V

DD

SCL

I2C INTERFACE

WIPER

REGISTER

GND

Figure 1.

A

AD5246

W

B

03875-001

Operating from a 2.7 V to 5.5 V power supply and consuming

lows for usage in portable battery-operated applications.

3 µA al

1

The terms digital potentiometer, VR, and RDAC are used interchangeably

in this document.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

AD5246

www.BDTIC.com/ADI

TABLE OF CONTENTS

Specifications..................................................................................... 3

Electrical Characteristics—5 kΩ Version.................................. 3

Electrical Characteristics—10 kΩ, 50 kΩ, 100 kΩ Versions .. 4

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings............................................................ 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Test Ci r c ui t s .....................................................................................11

2

I

C Interface..................................................................................... 12

Operation......................................................................................... 13

Programming the Variable Resistor......................................... 13

REVISION HISTORY

7/05—Rev. 0 to Rev. A

Changes to Table 1 ............................................................................3

Changes to Table 2 ............................................................................4

Changes to Absolute Maximum Ratings .......................................6

Moved Pin Configuration and Function Descriptions ................7

Deleted Table 7 ................................................................................12

Changes to Operation Section .......................................................13

Deleted Figure 31.............................................................................14

Changes to Figure 30 and Figure 32 .............................................14

2

I

C Compatible 2-Wire Serial Bus ........................................... 13

Level Shifting for Bidirectional Interface................................ 14

ESD Protection ........................................................................... 14

Terminal Voltage Operating Range ......................................... 14

Maximum Operating Current .................................................. 14

Power-Up Sequence ................................................................... 14

Layout and Power Supply Bypassing ....................................... 15

Constant Bias to Retain Resistance Setting............................. 15

Evaluation Board ........................................................................ 15

Outline Dimensions ....................................................................... 16

Ordering Guide .......................................................................... 16

9/03—Revision 0: Initial Version

Rev. A | Page 2 of 16

AD5246

www.BDTIC.com/ADI

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 KΩ VERSION

VDD = 5 V ± 10% or 3 V ± 10%; VA = +VDD; –40°C < TA < +125°C, unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ1Max Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resistor Differential Nonlinearity
Resistor Integral Nonlinearity
Nominal Resistor Tolerance
Resistance Temperature Coefficient (∆RAB/RAB)/∆T Wiper = no connect 45 ppm/°C
R

WB

Code = 0x00, VDD = 2.7 V 150 400 Ω

RESISTOR TERMINALS

Voltage Range

4

Capacitance5 B C
Capacitance5 W C
Common-Mode Leakage I

DIGITAL INPUTS AND OUTPUTS

Input Logic High V
Input Logic Low V
Input Logic High V
Input Logic Low V
Input Current I
Input Capacitance

5

POWER SUPPLIES

Power Supply Range V
Supply Current I
Power Dissipation

6

Power Supply Sensitivity PSSR VDD = +5 V ± 10%, code = midscale ±0.01 ±0.02 %/%

DYNAMIC CHARACTERISTICS

Bandwidth –3 dB BW_5K RAB = 5 kΩ, code = 0x40 1.2 MHz
Total Harmonic Distortion THD
VW Settling Time t
Resistor Noise Voltage Density e

1

Typical specifications represent average readings at 25°C and VDD = 5 V.

2

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

3

Code = 0x7F.

4

Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other.

5

Guaranteed by design; not subject to production test.

6

P

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

7

VDD = 5 V.

5, 7

2

2

3

R-DNL R
R-INL R
∆R

AB

R

WB

V

B, W

B

W

CM

IH

IL

IH

IL

IL

C

IL

DD RANGE

DD

P

DISS

WB

WB

–1.5 ±0.1 +1.5 LSB
–4 ±0.75 +4 LSB

TA = 25°C –30 +30 %

Code = 0x00, VDD = 5 V 75 150 Ω

GND V

V

DD

f = 1 MHz, measured to GND, code = 0x40 45 pF
f = 1 MHz, measured to GND, code = 0x40 60 pF
1 nA

VDD = 5 V 2.4 V
VDD = 5 V 0.8 V
VDD = 3 V 2.1 V
VDD = 3 V 0.6 V
VIN = 0 V or 5 V ±1 μA
5 pF

2.7 5.5 V
VIH = 5 V or VIL = 0 V 3 8 μA
VIH = 5 V or VIL = 0 V, VDD = 5 V 40 μW

W

S

N_WB

VA = 1 V rms, VB = 0 V, f = 1 kHz 0.05 %
VA = 5 V, ±1 LSB error band 1 μs
RWB = 2.5 kΩ, RS = 0 Ω 6 nV/√Hz

Rev. A | Page 3 of 16

AD5246

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ELECTRICAL CHARACTERISTICS—10 KΩ, 50 KΩ, 100 KΩ VERSIONS

VDD = 5 V ± 10% or 3 V ± 10%; VA = VDD; –40°C < TA < +125°C, unless otherwise noted.

Table 2.

Parameter Symbol Conditions Min Typ

DC CHARACTERISTICS, RHEOSTAT MODE

Resistor Differential Nonlinearity
Resistor Integral Nonlinearity
Nominal Resistor Tolerance

2

2

3

R-DNL RWB, VA = no connect –1 ±0.1 +1 LSB
R-INL RWB, VA = no connect –2 ±0.25 +2 LSB
∆R

AB

TA = 25°C –20 +20 %
Resistance Temperature Coefficient (∆RAB/RAB)/∆T Wiper = no connect 45 ppm/°C
R

WB

R

WB

Code=0x00, VDD = 5 V 75 150 Ω
Code=0x00, VDD = 2.7 V 150 400 Ω

RESISTOR TERMINALS

Voltage Range
Capacitance5 B C
Capacitance5 W C
Common-Mode Leakage I

4

V

B, W

B

W

CM

GND V

f = 1 MHz, measured to GND, code = 0x40 45 pF

f = 1 MHz, measured to GND, code = 0x40 60 pF

1 nA

DIGITAL INPUTS AND OUTPUTS

Input Logic High V
Input Logic Low V
Input Logic High V
Input Logic Low V
Input Current I
Input Capacitance

5

IH

IL

IH

IL

IL

C

IL

VDD = 5 V 2.4 V

VDD = 5 V 0.8 V

VDD = 3 V 2.1 V

VDD = 3 V 0.6 V

VIN = 0 V or 5 V ±1 μA

5 pF

POWER SUPPLIES

Power Supply Range V
Supply Current I
Power Dissipation

6

DD RANGE

DD

P

DISS

2.7 5.5 V

VIH = 5 V or VIL = 0 V 3 8 μA

VIH = 5 V or VIL = 0 V, VDD = 5 V 40 μW
Power Supply Sensitivity PSSR VDD = +5 V ± 10%, code = midscale ±0.01 ±0.02 %/%

DYNAMIC CHARACTERISTICS

5, 7

Bandwidth –3 dB BW RAB = 10 kΩ/50 kΩ/100 kΩ, code = 0x40 600/100/40 kHz
Total Harmonic Distortion THD
VW Settling Time (10 kΩ/50 kΩ/100 kΩ) t
Resistor Noise Voltage Density e

1

Typical specifications represent average readings at 25°C and VDD = 5 V.

2

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

3

Code = 0x7F.

4

Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other.

5

Guaranteed by design; not subject to production test.

6

P

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

7

All dynamic characteristics use VDD = 5 V.

W

S

N_WB

VA = 1 V rms, f = 1 kHz, RAB = 10 kΩ 0.05 %

VA = 5 V ±1 LSB error band 2 μs

RWB = 5 kΩ, RS = 0 9 nV/√Hz

1

Max Unit

V

DD

Rev. A | Page 4 of 16

AD5246

www.BDTIC.com/ADI

TIMING CHARACTERISTICS

VDD = 5 V ± 10% or 3 V ± 10%; VA = VDD; –40°C < TA < +125°C, unless otherwise noted.

Table 3.

Parameter Symbol Conditions Min Typ1Max Unit

I2C INTERFACE TIMING CHARACTERISTICS

SCL Clock Frequency f
t

Bus Free Time Between STOP and START t

BUF

t

Hold Time (Repeated START) t

HD;STA

t

Low Period of SCL Clock t

LOW

t

High Period of SCL Clock t

HIGH

t

Setup Time for Repeated START Condition t

SU;STA

t

Data Hold Time t

HD;DAT

t

Data Setup Time t

SU;DAT

tF Fall Time of Both SDA and SCL Signals t
tR Rise Time of Both SDA and SCL Signals t
t

Setup Time for STOP Condition t

SU;STO

1

Typical specifications represent average readings at 25°C and VDD = 5 V.

2

Guaranteed by design; not subject to production test.

3

See timing diagrams (Figure 26, Figure 27, and Figure 28) for locations of measured values.

4

Specifications apply to all parts.

2, , 3 4

SCL

1

2

400 kHz

1.3 μs
After this period, the first clock pulse is

generated 0.6 μs

3

4

5

6

7

8

9

10

1.3 μs

0.6 50 μs

0.6 μs

0.9 μs
100 ns
300 ns
300 ns

0.6 μs

Rev. A | Page 5 of 16

AD5246

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.
Table 4.

Parameter Value

VDD to GND –0.3 V to +7 V
VA, VW to GND V
Terminal Current, A–B, A–W, B–W

Digital Inputs and Output Voltage to GND 0 V to VDD + 0.3 V
Operating Temperature Range –40°C to +125°C
Maximum Junction Temperature (T
Storage Temperature –65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
Thermal Resistance3 θJA: SC70-6 340°C/W

1

Maximum terminal current is bounded by the maximum current handling of

2

Package power dissipation = (T

1

Pulsed
Continuous ±5 mA

) 150°C

JMAX

the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.

− TA)/θ

JMAX

JA.

DD

±20 mA

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. A | Page 6 of 16

AD5246

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

V

1

DD

AD5246

2

GND

SCL

TOP VIEW

(Not to Scale)

3

Figure 2. Pin Configuration

B

6

5

W

SDA

4

03875-018

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 V

DD

Positive Power Supply.
2 GND Digital Ground.
3 SCL Serial Clock Input. Positive edge triggered.
4 SDA Serial Data Input/Output.
5 W W Terminal.
6 B B Terminal.

Rev. A | Page 7 of 16

AD5246

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

RHEOSTAT MODE INL (LSB)

RHEOSTAT MODE INL (LSB)

–0.6
–0.8

–1.0

16 32 48

0

Figure 3. R-INL vs. Code vs. Supply Voltages

0.5

0.4

0.3

0.2

0.1
0

–0.1

–0.2

–0.3

RHEOSTAT MODE DNL (LSB)

–0.4

–0.5

VDD = 2.7V

0

16 32 48 64 80 96 112 128

Figure 4. R-DNL vs. Code vs. Supply Voltages

1.0

0.8

TA = +85°C

0.6

0.4

0.2

0

–0.2

–0.4

RHEOSTAT MODE INL (LSB)

–0.6

–0.8
–1.0

16 32 48

0

Figure 5. R-INL vs. Code vs. Temperature

CODE (Decimal)

V

DD

CODE (Decimal)

TA = –40°C

TA = +25°C

CODE (Decimal)

VDD = 2.7V

V

= 5.5V

DD

64 80 96 112 128

= 5.5V

64 80 96 112 128

TA = +125°C

TA= 25

°

C

= 10kΩ

R

AB

TA = 25°

C

= 10kΩ

R

AB

TA = –40°

TA = +25°C
TA = +85°C
TA = +125°C

03875-020

03875-021

C

03875-022

0.5

–40°C

0.4

°

C

+25

°

C

+85

0.3

0.2

0.1

–0.1

–0.2

RHEOSTAT MODE DNL (LSB)

–0.3

–0.4

–0.5

+125

0

0

°

C

16 32 48

Figure 6. R-DNL vs. Code vs. Temperature

0

–0.5

–1.0

–1.5

–2.0

RHEOSTAT MODE INL (LSB)

FSE, FULL-SCALE ERROR (LSB)

–2.5

–3.0

–40

–25 –10 5 20 35 50 65 80

Figure 7. Full-Scale Error vs. Temperature

1.50

1.25

1.00

0.75

0.50

0.25

ZSE, ZERO-SCALE ERROR (LSB)

0

–40

–25 –10 5

Figure 8. Zero-Scale Error vs. Temperature

VDD = 2.7V

= 10kΩ

R

AB

TA = –40°

C, +25°C, +85°C, +125°C

64 80 96 112

CODE (Decimal)

VDD = 5.5V, VA = 5.5V

VDD = 2.7V, VA = 2.7V

TEMPERATURE (°

C)

95 110 125

VDD = 5.5V, VA = 5.5V

V

= 2.7V, VA = 2.7V

DD

20 35 50 65 80 95 110 125

TEMPERATURE (°C)

03875-023

128

03875-024

03875-025

Rev. A | Page 8 of 16

AD5246

www.BDTIC.com/ADI

100

10

1

SUPPLY CURRENT (μA)

0.1

DD,

I

0.01
–40

–25 –10

5 20 35 50 65 80 95 110 125

TEMPERATURE (°

Figure 9. Supply Current vs. Temperature

500

400

C)

RHEOSTAT MODE TEMPCO (ppm/°

300

200

100

–100

–200

–300
–400

–500

0

0

TA = –40°C to +85°C

TA = –40°C to +125°C

16 32 48

CODE (Decimal)

Figure 10. Rheostat Mode Tempco ∆R

0

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

1k

0x40

0x20
0x10

0x08
0x04

0x02
0x01

10k

FREQUENCY (Hz)

Figure 11. Gain vs. Frequency vs. Code, R

DIGITAL INPUTS = 0V
CODE = 0x40

VDD = 5.5V

VDD = 2.7V

C)

VDD = 2.7V

RAB = 10kΩ

64 80 96 112 128

/∆T vs. Code

WB

100k 1M 10M

= 5 kΩ

AB

03875-026

03875-027

03875-028

0

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

1k

0x40

0x20

0x10
0x08
0x04
0x02

0x01

10k

FREQUENCY (Hz)

Figure 12. Gain vs. Frequency vs. Code, R

0

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

1k

0x40

0x20

0x10
0x08

0x04
0x02
0x01

10k

FREQUENCY (Hz)

Figure 13. Gain vs. Frequency vs. Code, R

0

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

1k

0x40

0x20
0x10

0x08

0x04

0x02

0x01

10k

FREQUENCY (Hz)

Figure 14. Gain vs. Frequency vs. Code, R

100k 1M 10M

= 10 kΩ

AB

100k 1M 10M

= 50 kΩ

AB

100k 1M 10M

= 100 kΩ

AB

03875-029

03875-030

03875-031

Rev. A | Page 9 of 16

AD5246

K

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0

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

1k

0.30

0.25

0.20

0.15

(μA)

DD

I

0.10

0.05

0

1k

360

300

100kΩ

10k

100k 1M 10M

FREQUENCY (Hz)

Figure 15. –3 dB Bandwidth @ Code = 0x80

A - VDD = 5.5V
CODE = 0x55

= 5.5V

B - V

DD

CODE = 0x7F

= 2.7V

C - V

DD

CODE = 0x55

= 2.7V

D - V

DD

CODE = 0x7F

10k 100k 1M

FREQUENCY (Hz)

Figure 16. I

vs. Frequency

DD

10kΩ

50kΩ

A

B

TA = 25°C
R

AB

CODE = 0x00

5kΩ

TA= 25°C

C

D

= 50k

TA = 25°C

= 10kΩ

R

AB

F

= 100kHz

CLK

5V
0V

03875-006

03875-032

VDD = 5.5V
V

= 0V

B

V

W

CL

1μs/DIV

Figure 18. Digital Feedthrough

03875-033

VDD = 5.5V
V
CODE 0x40 to 0x3F

V

W

= 0V

B

200ns/DIV

TA = 25°C

= 10kΩ

R

AB

03875-007

Figure 19. Midscale Glitch, Code 0x40 to 0x3F

Ω

VDD = 5.5V

= 0V

V

B

CODE 00

TO 7F

H

H

TA = 25°C

= 10k

R

AB

IW = 50μA

Ω

= 2.7V

V

240

)

Ω

(

180

WB

R

120

60

0

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

DD

Figure 17. R

WB

V

BIAS

vs. V

(V)

BIAS

vs. V

V

1

W

V

= 5.5V

DD

03875-008

DD

Figure 20. Large Signal Settling Time

Rev. A | Page 10 of 16

μ

s/DIV

40

03875-005

AD5246

V

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TEST CIRCUITS

Figure 21 to Figure 25 define the test conditions used in the product Specification tables.

DUT

W

B

igure 21. Test Circuit for Resistor Position Nonlinearity Error

F

(Rheostat Operation; R-INL, R-DNL)

DUT

V

DD

V+

F

igure 22. Test Circuit for Power Supply Sensitivity (PSS, PSSR)

W

B

I

W

V

MS

V+ = V

±

DD

PSRR (dB) = 20 LOG

PSS (%/%) =

V

MS

10%

ΔV
ΔV

03875-004

%

MS

%

DD

ΔV

MS

( )

ΔV

DD

03875-009

0.1V

RSW=

I

DUT

B

W

I

SW

VDD TO GND

SW

CODE = 0x00

0.1V

03875-040

igure 24. Test Circuit for Incremental On Resistance

F

DUT

I

CM

W

B

V

CM

NO CONNECT

03875-012

F

igure 25. Test Circuit for Common-Mode Leakage Current

DUT

10kΩ

IN

B

2.5V

10kΩ

+15V

W

OP27

–15V

V

OUT

03875-010

igure 23. Test Circuit for Gain vs. Frequency

F

Rev. A | Page 11 of 16

AD5246

Y

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I2C INTERFACE

Table 6. Write Mode

S 0 1 0 1 1 1 0
Slave Address Byte Data Byte

Table 7. Read Mode

S 0 1 0 1 1 1 0 R A 0 D6 D5 D4 D3 D2 D1 D0 A P
Slave Address Byte Data Byte

A X D6 D5 D4 D3 D2 D1 D0 A P

W

S = Start Condition.

P = Stop Condition.

A = Acknowledge.

X = Don’t Care.

SCL

SDA

t

1

PS

START B

MASTER

t

8

t

2

t

3

t

9

t

8

Figure 26. I

SCL

0 1 0 1 1 1 0 R/W

SDA

FRAME 1

SLAVE ADDRESS BYTE

= Write.

W

R = Read.

D6, D5, D4, D3, D2, D1, D0 = Data Bits.

t

9

t

6

t

4

2

C Interface, Detailed Timing Diagram

Figure 27. Writing to the RDAC Register

t

7

119

XD6 D4D3D2D1D0

ACK BY
AD5246

D5

DATA BYTE

t

5

S

FRAME 2

t

2

t

10

ACK BY
AD5246

19

STOP BY

MASTER

03875-014

P

03875-019

1 919

SCL

0 D6D5D4D3D2D1D0

ACK BY
AD5246

FRAME 2

RDAC REGISTER

START BY

MASTER

0 1 0 1 1 1 0 R/W

SDA

FRAME 1

SLAVE ADDRESS BYTE

Figure 28. Reading from the RDAC Register

Rev. A | Page 12 of 16

NO ACK
BY MASTER

STOP BY
MASTER

03875-013

AD5246

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OPERATION

The AD5246 is a 128-position, digitally controlled variable
resistor (VR) device.

PROGRAMMING THE VARIABLE RESISTOR

Rheostat Operation

The nominal resistance of the RDAC between Terminal A
and Terminal B is available in 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ.
The final two or three digits of the part number determine
the nominal resistance value, that is, 10 kΩ = 10, 50 kΩ = 50.
The nominal resistance (R
accessed by the wiper terminal. The 7-bit data in the RDAC
latch is decoded to select one of the 128 possible settings.

The general equation determining the digitally programmed
o

utput resistance between W and B is

) of the VR has 128 contact points

AB

I2C COMPATIBLE 2-WIRE SERIAL BUS

The first byte of the AD5246 is a slave address byte (see Tab l e 6

W

and Tabl e 7). It has a 7-bit slave address and an R/
seven MSBs of the slave address are 0101110 followed by 0
for a write command or 1 to place the device in read mode.

2

The 2-wire I

1. The mast

C serial bus protocol operates as follows:

er initiates data transfer by establishing a START
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high (see Figure 27). The
fol

lowing byte is the slave address byte, which consists of

the 7-bit slave address followed by an R/

determines whether data will be read from or written to
the slave device).

bit. The

bit (this bit

W

D

DR ×+×= 2

)(

128

(1)

RR

WABWB

where:

he decimal equivalent of the binary code loaded in the

D is t
7-bit RDAC register.

R

is the end-to-end resistance.

AB

R

is the wiper resistance contributed by the on resistance

W

of each internal switch.

Ax

D6
D5
D4
D3
D2
D1
D0

DECODER

Figure 29. AD5246 Equivalent RDAC Circuit

RDAC

LATCH

AND

R

S

R

S

R

S

Wx

Bx

03875-015

Note that in the zero-scale condition, there is a relatively small
finite wiper resistance. Care should be taken to limit the current
flow between W and B in this state to a maximum pulse current
of no more than 20 mA. Otherwise, degradation or possible
destruction of the internal switch contact can occur.

Typical device-to-device matching is process lot dependent and

y vary by up to ±30%. Since the resistance element is proc-

ma
essed in thin-film technology, the temperature coefficient of
R

is only 45 ppm/°C.

AB

The slave whose address corresponds to the transmitted
addr

ess responds by pulling the SDA line low during the
ninth clock pulse (this is termed the acknowledge bit).
At this stage, all other devices on the bus remain idle while
the selected device waits for data to be written to or read
from its serial register. If the R/

bit is high, the master

W
reads from the slave device. Conversely, if the R/

low, the master writes to the slave device.

n write mode, after acknowledgement of the slave address

2. I

byte, the next byte is the data byte. Data is transmitted over
the serial bus in sequences of nine clock pulses (eight data
bits followed by an acknowledge bit). The transitions on
the SDA line must occur during the low period of SCL and
remain stable during the high period of SCL (see

3. I

n read mode, after acknowledgment of the slave address
byte, data is received over the serial bus in sequences of
nine clock pulses (a slight difference from the write mode
where eight data bits are followed by an acknowledge bit).
Similarly, the transitions on the SDA line must occur
during the low period of SCL and remain stable during
the high period of SCL (see

hen all data bits have been read or written, a STOP

4. W

Figure 28).

condition is established by the master. A STOP condition
is defined as a low-to-high transition on the SDA line while
SCL is high. In write mode, the master pulls the SDA line
high during the tenth clock pulse to establish a STOP
condition (see

o Acknowledge for the ninth clock pulse (that is, the

a N

Figure 27). In read mode, the master issues

SDA line remains high). The master then brings the SDA
line low before the tenth clock pulse, which goes high to
establish a STOP condition (see

Figure 28).

bit is

W

Tabl e 6).

Rev. A | Page 13 of 16

AD5246

V

www.BDTIC.com/ADI

A repeated write function gives the user flexibility to update the
RDAC output a number of times after addressing the part only
once. For example, after the RDAC has acknowledged its slave
address in write mode, the RDAC output updates on each succes­sive byte. If different instructions are needed, the write/read mode
has to start again with a new slave address and data byte.
Similarly, a repeated read function of the RDAC is also allowed.

LEVEL SHIFTING FOR BIDIRECTIONAL INTERFACE

While most legacy systems may be operated at one voltage,
a new component may be optimized at another. When two
systems operate the same signal at two different voltages, proper
level shifting is needed. For instance, one can use a 1.8 V

2

E

PROM to interface with a 5 V digital potentiometer. A level
shifting scheme is needed to enable a bidirectional communi­cation so that the setting of the digital potentiometer can be
stored to and retrieved from the E

2

PROM. Figure 30 shows
one of the implementations. M1 and M2 can be any N channel
signal FETs, or if V

falls below 2.5 V, M1 and M2 can be low

DD

threshold FETs such as the FDV301N.

= 1.8V V

DD1

R

SDA1

SCL1

1.8V

R

P

P

G

S

D

M1

R

P

G

S

D

M2

E2PROM

Figure 30. Level Shifting for Operation at Different Potentials

R

AD5246

5V

=

DD2

P

SDA2

SCL2

5V

03875-011

ESD PROTECTION

All digital inputs are protected with a series input resistor
and parallel Zener ESD structures, as shown in Figure 31.

pplies to the digital input pins SDA and SCL.

This a

340Ω

LOGIC

V

DD

B

W

03875-016

GND

Figure 32. Maximum Terminal Voltages Set by V

and GND

DD

MAXIMUM OPERATING CURRENT

At low code values, the user should be aware that due to low
resistance values, the current through the RDAC may exceed
the 5 mA limit. In Figure 33, a 5 V supply is placed on the

per, and the current through Terminal W and Terminal B is

wi
plotted with respect to code. A line is also drawn denoting the
5 mA current limit. Note that at low code values (particularly
for the 5 k and 10 k options), the current level increases
significantly. Care should be taken to limit the current flow
between W and B in this state to a maximum continuous
current of 5 mA and a maximum pulse current of no more than
20 mA. Otherwise, degradation or possible destruction of the
internal switch contacts can occur.

100

10

1

IWB CURRENT (mA)

0.1

0.01
0

16 32 48

Figure 33. Maximum Operating Current

5mA CURRENT LIMIT

RAB= 10k

RAB= 100k

64 80 96 112 128

CODE (Decimal)

R

AB

Ω

RAB= 50k

= 5k

Ω

Ω

Ω

03875-034

03875-002

GND

Figure 31. ESD Protection of Digital Pins

TERMINAL VOLTAGE OPERATING RANGE

The AD5246 VDD and GND power supply defines the boundary
conditions for proper 3-terminal digital potentiometer
operation. Supply signals present on Terminal B and
Terminal W that exceed V

or GND are clamped by

DD

POWER-UP SEQUENCE

Since the ESD protection diodes limit the voltage compliance
at Te r mi n al B an d Ter min al W (s ee Figure 32), it is important

power V

to
and Terminal W; otherwise, the diode is forward biased such
that V
the user’s circuit. The ideal power-up sequence is in the follow­ing order: GND, V
relative order of powering V
is not important, providing they are powered after V

/GND before applying any voltage to Terminal B

DD

is powered unintentionally and may affect the rest of

DD

, digital inputs, and then VB/VBW. The

DD

the internal forward biased diodes (see Figure 32).

Rev. A | Page 14 of 16

B and V

B

and the digital inputs

W

/GND.

DD

AD5246

www.BDTIC.com/ADI

LAYOUT AND POWER SUPPLY BYPASSING

It is a good practice to use a compact, minimum lead-length
layout design. The leads to the inputs should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.

Similarly, it is good practice to bypass the power supplies with
qu

ality capacitors for optimum stability. Supply leads to the
device should be bypassed with 0.01 µF to 0.1 µF disc or chip
ceramic capacitors. Low ESR 1 µF to 10 µF tantalum or
electrolytic capacitors should also be applied at the supplies to
minimize any transient disturbance and low frequency ripple
(see

Figure 34). Note that the digital ground should also be

j

oined remotely to the analog ground at one point to minimize

the ground bounce.

V

V

DD

+

C1

C3

Figure 34. Power Supply Bypassing

10μF

0.1μF

DD

AD5246

GND

03875-017

CONSTANT BIAS TO RETAIN RESISTANCE SETTING

For users who desire nonvolatility but cannot justify the addi­tional cost for the EEMEM, the AD5246 may be considered as
a low cost alternative by maintaining a constant bias to retain
the wiper setting. The AD5246 was designed specifically with
low power in mind, which allows low power consumption
even in battery-operated systems. The graph in

onstrates the power consumption from a 3.4 V 450 mA/hr

dem
Li-ion cell phone battery, which is connected to the AD5246.
The measurement over time shows that the device draws
approximately 1.3 µA and consumes negligible power. Over
a course of 30 days, the battery was depleted by less than 2%,
the majority of which is due to the intrinsic leakage current
of the battery itself.

Figure 35

110%

108%

106%

104%

102%

100%

98%

96%

BATTERY LIFE DEPLETED

94%

92%

90%

0

51015

DAYS

Figure 35. Battery Operating Life Depletion

TA= 25°

C

20 25 30

03875-035

This demonstrates that constantly biasing the pot is not an
impractical approach. Most portable devices do not require the
removal of batteries for the purpose of charging. Although the
resistance setting of the AD5246 will be lost when the battery
needs replacement, such events occur rather infrequently, so
that this inconvenience is justified by the lower cost and smaller
size offered by the AD5246. If and when total power is lost,
the user should be provided with a means to adjust the setting
accordingly.

EVALUATION BOARD

An evaluation board, along with all necessary software, is
available to program the AD5246 from any PC running
Windows® 98, Windows 2000, or Windows XP®. The graphical
user interface, as shown in

asy to use. More detailed information is available in the user

e
manual, which comes with the board.

Figure 36, is straightforward and

Figure 36. AD5246 Evaluation Board Software

Rev. A | Page 15 of 16

03875-041

AD5246

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

2.20

2.00

1.80

2.40

0.30

0.15

4 5 6

3 2 1

0.65 BSC

2.10

1.80

1.10

0.80

SEATING
PLANE

0.40

0.10

0.22

0.08

1.35

1.25

1.15

1.00

0.90

0.70

0.10 MAX

PIN 1

1.30 BSC

0.10 COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-203-AB

Figure 37. 6-Lead Thin Shrink Small Outline Transistor Package [SC70]

(K

S-6)

Dimensions shown in millimeters

0.46

0.36

0.26

ORDERING GUIDE

Model RAB (kΩ) Temperature Range Package Description Package Option Branding

AD5246BKS5-R2 5 –40°C to +125°C 6-lead SC70 KS-6 D16
AD5246BKS5-RL7 5 –40°C to +125°C 6-lead SC70 KS-6 D16
AD5246BKSZ5-RL7
AD5246BKS10-R2 10 –40°C to +125°C 6-lead SC70 KS-6
AD5246BKS10-RL7 10 –40°C to +125°C 6-lead SC70 KS-6
AD5246BKSZ10-RL7 10 –40°C to +125°C 6-lead SC70 KS-6
AD5246BKS50-R2 50 –40°C to +125°C 6-lead SC70 KS-6 D1C
AD5246BKS50-RL7 50 –40°C to +125°C 6-lead SC70 KS-6
AD5246BKSZ50-RL7 50 –40°C to +125°C 6-lead SC70 KS-6
AD5246BKS100-R2 100 –40°C to +125°C 6-lead SC70 KS-6 D1A
AD5246BKS100-RL7 100 –40°C to +125°C 6-lead SC70 KS-6
AD5246BKSZ100-R2 100 –40°C to +125°C 6-lead SC70 KS-6
AD5246BKSZ100-RL7 100 –40°C to +125°C 6-lead SC70 KS-6 D9D
AD5246EVAL Evaluation Board

1

Z = Pb-free part.

2

The evaluation board is shipped with the 10 kΩ R resistor option; however, the board is compatible with all available resistor value options.

1

5 –40°C to +125°C 6-lead SC70 KS-6 D93

D1D
D1D

1

D92

D1C

1

D94

D1A

1

1

2

AB

D9D

Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.

© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

C03875–0–7/05(A)

Rev. A | Page 16 of 16